24AA025E48-IOT

24AA02E48/24AA025E48 2K I2C™ Serial EEPROMs with EUI-48™ Node Identity Device Selection Table Part Number 24AA02E48 24AA025E48 Note 1: 100 kHz for VCC Range 1.7-5.5V 1.7-5.5V VCC 4,000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • Available Packages: - 8-lead SOIC and 5-lead SOT-23 (24AA02E48) - 8-lead SOIC and 6-lead SOT-23 (24AA025E48) • Pb-free and RoHS Compliant • Temperature Ranges: - Industrial (I): -40°C to +85°C Description: The Microchip Technology Inc. 24AA02E48/ 24AA025E48 (24AAXXXE48*) is a 2 Kbit Electrically Erasable PROM. The device is organized as two blocks of 128 x 8-bit memory with a 2-wire serial interface. Low-voltage design permits operation down to 1.7V, with maximum standby and active currents of only 1 A and 1 mA, respectively. The 24AAXXXE48 also has a page write capability for up to 8 bytes of data (16 bytes on the 24AA025E48). The 24AAXXXE48 is available in the standard 8-pin SOIC, 5-lead SOT-23, and 6-lead SOT-23 packages. Package Types (24AA02E48) SOT-23 NC NC NC Vss SDA 2 3 4 Vcc NC VSS 1 2 3 4 SOIC 8 7 6 5 VCC NC SCL SDA SCL 1 5 Package Types (24AA025E48) SOT-23 SCL VSS SDA 1 2 3 6 5 4 VCC A0 A1 A0 A1 A2 VSS 1 2 3 4 SOIC 8 7 6 5 VCC NC SCL SDA *24AAXXXE48 is used in this document as a generic part number for the 24AA02E48 and 24AA025E48 devices.  2010 Microchip Technology Inc. DS22124D-page 1 24AA02E48/24AA025E48 Block Diagram A0(1) A1(1) A2(1) HV Generator Memory Control Logic I/O Control Logic XDEC EEPROM Array SDA SCL VCC VSS Write-Protect Circuitry YDEC Sense Amp. R/W Control Note 1: Pins A0, A1 and A2 are not available on the 24AA02E48. DS22124D-page 2  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.3V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied..................................................................................................-40°C to +85°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): Min. — DC CHARACTERISTICS Param. No. Sym. — D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 VIH VIL VHYS VOL ILI ILO CIN, COUT ICC read ICCS Standby Current Characteristic SCL, SDA, A0, A1, and A2 pins High-level Input Voltage Low-level Input Voltage Hysteresis of Schmitt Trigger inputs Low-level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (all inputs/outputs) TA = -40°C to +85°C, VCC = +1.7V to +5.5V Typ. — — — — — — — — 0.1 0.05 0.01 Max. — — 0.3 VCC — 0.40 ±1 ±1 10 3 1 1 Units — V V V V A A pF mA mA  — — — (Note) IOL = 3.0 mA, VCC = 2.5V VIN = VSS or VCC VOUT = VSS or VCC VCC = 5.0V (Note) TA = 25°C, FCLK = 1 MHz VCC = 5.5V, SCL = 400 kHz — Industrial SDA = SCL = VCC WP = VSS Conditions 0.7 VCC — 0.05 VCC — — — — — — — ICC write Operating Current Note: This parameter is periodically sampled and not 100% tested.  2010 Microchip Technology Inc. DS22124D-page 3 24AA02E48/24AA025E48 TABLE 1-2: AC CHARACTERISTICS Industrial (I): Min. — — 600 4000 1300 4700 — — — 600 4000 600 4700 0 100 250 600 4000 — — 1300 4700 Typ. — — — — — — — — — — — — — — — — — — — — — — — — TA = -40°C to +85°C, VCC = +1.7V to +5.5V Max. 400 100 — — — — 300 1000 300 — — — — — — — — — 900 3500 — — Units kHz ns ns ns ns ns ns ns ns ns ns ns Conditions 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V (Note 1) 1.7V  VCC  2.5V (Note 1) (Note 1) 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V (Note 2) 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V 2.5V  VCC  5.5V 1.7V  VCC  2.5V AC CHARACTERISTICS Param. No. 1 2 3 4 5 6 7 8 9 10 11 12 Sym. FCLK THIGH Characteristic Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time Start condition hold time Start condition setup time Data input hold time Data input setup time Stop condition setup time Output valid from clock (Note 2) Bus free time: Time the bus must be free before a new transmission can start Output fall time from VIH minimum to VIL maximum Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO TAA TBUF 13 TOF — — — — — — 250 250 50 ns 2.5V  VCC  5.5V 1.7V  VCC  2.5V (Notes 1 and 3) 14 TSP ns 15 16 Note 1: 2: 3: 4: TWC — — 1M — — 5 — ms — cycles 25°C (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.microchip.com. DS22124D-page 4  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 FIGURE 1-1: BUS TIMING DATA 5 3 SCL 7 SDA IN 6 14 11 SDA OUT 12 8 9 10 2 4 FIGURE 1-2: BUS TIMING START/STOP D3 SCL 7 SDA 6 10 Start Stop  2010 Microchip Technology Inc. DS22124D-page 5 24AA02E48/24AA025E48 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name A0 A1 A2 VSS SDA SCL NC VCC Note 1: PIN FUNCTION TABLE SOIC 1 2 3 4 5 6 7 8 5-Pin SOT-23 — — — 2 3 1 5 4 6-Pin SOT-23 5 4 — 2 3 1 — 6 Description Chip Address Input(1) Chip Address Input(1) Chip Address Input(1) Ground Serial Address/Data I/O Serial Clock Not Connected +1.7V to 5.5V Power Supply Chip address inputs A0, A1 and A2 are not connected on the 24AA02E48. 2.1 Serial Address/Data Input/Output (SDA) SDA is a bidirectional pin used to transfer addresses and data into and out of the device. Since it is an opendrain terminal, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz). For normal data transfer, SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating Start and Stop conditions. 2.2 Serial Clock (SCL) The SCL input is used to synchronize the data transfer to and from the device. 2.3 A0, A1, A2 Chip Address Inputs The A0, A1 and A2 pins are not used by the 24AA02E48. They may be left floating or tied to either VSS or VCC. For the 24AA025E48, the levels on the A0, A1 and A2 inputs are compared with the corresponding bits in the slave address. The chip is selected if the compare is true. For the 6-lead SOT-23 package, pin A2 is not connected and its corresponding bit in the slave address should always be set to ‘0’. Up to eight 24AA025E48 devices (four for the SOT-23 package) may be connected to the same bus by using different Chip Select bit combinations. These inputs must be connected to either VSS or VCC. DS22124D-page 6  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 3.0 FUNCTIONAL DESCRIPTION 4.4 Data Valid (D) The 24AAXXXE48 supports a bidirectional, 2-wire bus and data transmission protocol. A device that sends data onto the bus is defined as transmitter, while a device receiving data is defined as a receiver. The bus has to be controlled by a master device which generates the Serial Clock (SCL), controls the bus access and generates the Start and Stop conditions, while the 24AAXXXE48 works as slave. Both master and slave can operate as transmitter or receiver, but the master device determines which mode is activated. The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of data bytes transferred between Start and Stop conditions is determined by the master device and is, theoretically, unlimited (although only the last sixteen will be stored when doing a write operation). When an overwrite does occur, it will replace data in a first-in first-out (FIFO) fashion. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24AAXXXE48 does not generate any Acknowledge bits if an internal programming cycle is in progress. 4.1 Bus Not Busy (A) Both data and clock lines remain high. 4.2 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must be ended with a Stop condition. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the acknowledge related clock pulse. Of course, setup and hold times must be taken into account. During reads, a master must signal an end of data to the slave by not generating an Acknowledge bit on the last byte that has been clocked out of the slave. In this case, the slave (24AAXXXE48) will leave the data line high to enable the master to generate the Stop condition. FIGURE 4-1: (A) SCL (B) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (D) (D) (C) (A) SDA Start Condition Address or Acknowledge Valid Data Allowed to Change Stop Condition  2010 Microchip Technology Inc. DS22124D-page 7 24AA02E48/24AA025E48 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the master device. The control byte consists of a four-bit control code. For the 24AAXXXE48, this is set as ‘1010’ binary for read and write operations. For the 24AA02E48 the next three bits of the control byte are “don’t cares”. For the 24AA025E48, the next three bits of the control byte are the Chip Select bits (A2, A1, A0). The Chip Select bits allow the use of up to eight 24AA025E48 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A2, A1 and A0 pins for the device to respond. These bits are in effect the three Most Significant bits of the word address. For the 6-pin SOT-23 package, the A2 address pin is not available. During device addressing, the A2 Chip Select bit should be set to ‘0’. The last bit of the control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is selected. Following the Start condition, the 24AAXXXE48 monitors the SDA bus, checking the device type identifier being transmitted and, upon a ‘1010’ code, the slave device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24AAXXXE48 will select a read or write operation. Operation Read Write Control Code Chip Select Chip Address Chip Address R/W S 1 CONTROL BYTE ALLOCATION Read/Write Bit Control Code 0 1 0 Chip Select Bits A2* A1* A0* R/W ACK Slave Address Start Bit Note: Acknowledge Bit * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48. 5.1 Contiguous Addressing Across Multiple Devices The Chip Select bits A2, A1 and A0 can be used to expand the contiguous address space for up to 16K bits by adding up to eight 24AA025E48 devices on the same bus. In this case, software can use A0 of the control byte as address bit A8, A1 as address bit A9 and A2 as address bit A10. It is not possible to sequentially read across device boundaries. For the SOT-23 package, up to four 24AA025E48 devices can be added for up to 8K bits of address space. In this case, software can us A0 of the control byte as address bit A8, and A1 as address bit A9. It is not possible to sequentially read across device boundaries. 1010 1010 1 0 FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte Address Low Byte 1 0 1 0 A2* A1* A0* R/W A 7 • • • • • • A 0 Control Code Note: Chip Select bits * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48. DS22124D-page 8  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 6.0 6.1 WRITE OPERATION Byte Write Following the Start condition from the master, the device code (4 bits), the chip address (3 bits) and the R/W bit which is a logic-low, is placed onto the bus by the master transmitter. This indicates to the addressed slave receiver that a byte with a word address will follow once it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the master is the word address and will be written into the Address Pointer of the 24AAXXXE48. After receiving another Acknowledge signal from the 24AAXXXE48, the master device will transmit the data word to be written into the addressed memory location. The 24AAXXXE48 acknowledges again and the master generates a Stop condition. This initiates the internal write cycle and, during this time, the 24AAXXXE48 will not generate Acknowledge signals (Figure 6-1). If the master should transmit more than 8 words (16 for the 24AA025E48) prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received an internal write cycle will begin (Figure 6-2). Note: Page write operations are limited to writing bytes within a single physical page regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of [page size – 1]. If a page write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page, as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. 6.2 Page Write The write-control byte, word address and the first data byte are transmitted to the 24AAXXXE48 in the same way as in a byte write. However, instead of generating a Stop condition, the master transmits up to 8 data bytes to the 24AAXXXE48, which are temporarily stored in the on-chip page buffer and will be written into memory once the master has transmitted a Stop condition. Upon receipt of each word, the three lower-order Address Pointer bits (four for the 24AA025E48) are internally incremented by ‘1’. The higher-order five bits (four for the 24AA025E48) of the word address remain constant. 6.3 Write Protection The upper half of the array (80h-FFh) is permanently write-protected. Write operations to this address range are inhibited. Read operations are not affected. The remaining half of the array (00h-7Fh) can be written to and read from normally. FIGURE 6-1: Bus Activity Master S T A R T S BYTE WRITE Control Byte Word Address Data S T O P P A C K A C K A C K SDA Line Bus Activity 1 0 1 0 A2* A1*A0* 0 Chip Select Bits Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48. FIGURE 6-2: Bus Activity Master SDA Line Bus Activity Note: PAGE WRITE S T A R T Control Byte *** Word Address (n) Data (n) Data (n + 1) Data (n + 7) S T O P P S 1 0 1 0 A2 A1 A0 0 A A C C Chip K K Select Bits * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48. A C K A C K A C K  2010 Microchip Technology Inc. DS22124D-page 9 24AA02E48/24AA025E48 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a write command has been issued from the master, the device initiates the internally-timed write cycle and ACK polling can then be initiated immediately. This involves the master sending a Start condition followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, no ACK will be returned. If the cycle is complete, the device will return the ACK and the master can then proceed with the next read or write command. See Figure 7-1 for a flow diagram of this operation. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? Yes Next Operation No DS22124D-page 10  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 8.0 READ OPERATION 8.3 Sequential Read Read operations are initiated in the same way as write operations, with the exception that the R/W bit of the slave address is set to ‘1’. There are three basic types of read operations: current address read, random read and sequential read. Sequential reads are initiated in the same way as a random read, except that once the 24AAXXXE48 transmits the first data byte, the master issues an acknowledge as opposed to a Stop condition in a random read. This directs the 24AAXXXE48 to transmit the next sequentially-addressed 8-bit word (Figure 8-3). To provide sequential reads, the 24AAXXXE48 contains an internal Address Pointer that is incremented by one upon completion of each operation. This Address Pointer allows the entire memory contents to be serially read during one operation. 8.1 Current Address Read The 24AAXXXE48 contains an address counter that maintains the address of the last word accessed, internally incremented by ‘1’. Therefore, if the previous access (either a read or write operation) was to address n, the next current address read operation would access data from address n + 1. Upon receipt of the slave address with R/W bit set to ‘1’, the 24AAXXXE48 issues an acknowledge and transmits the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the 24AAXXXE48 discontinues transmission (Figure 8-1). 8.4 Noise Protection The 24AAXXXE48 employs a VCC threshold detector circuit which disables the internal erase/write logic if the VCC is below 1.5V at nominal conditions. The SCL and SDA inputs have Schmitt Trigger and filter circuits which suppress noise spikes to assure proper device operation, even on a noisy bus. 8.2 Random Read Random read operations allow the master to access any memory location in a random manner. To perform this type of read operation, the word address must first be set. This is accomplished by sending the word address to the 24AAXXXE48 as part of a write operation. Once the word address is sent, the master generates a Start condition following the acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. The master then issues the control byte again, but with the R/W bit set to a ‘1’. The 24AAXXXE48 will then issue an acknowledge and transmit the 8-bit data word. The master will not acknowledge the transfer, but does generate a Stop condition, and the 24AAXXXE48 will discontinue transmission (Figure 8-2). FIGURE 8-1: CURRENT ADDRESS READ Bus Activity Master S T A R T S1 0 1 Control Byte S T O P P A C K N o A C K Data (n) SDA Line Bus Activity 0 A2* A1*A0* 1 Chip Select Bits Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48.  2010 Microchip Technology Inc. DS22124D-page 11 24AA02E48/24AA025E48 FIGURE 8-2: RANDOM READ S T A R T Control Byte *** Bus Activity Master Word Address (n) S T A R T A C K Control Byte *** Data (n) S T O P P N o A C K SDA Line Bus Activity S 1 0 1 0 A2A1A0 0 Chip Select Bits A C K S 1 0 1 0 A2A1A0 1 Chip Select Bits A C K Note: * Bits A0, A1 and A2 are “don’t cares” for the 24AA02E48. FIGURE 8-3: Bus Activity Master SDA Line Bus Activity SEQUENTIAL READ Control Byte 1 A C K A C K A C K A C K N o A C K Data (n) Data (n + 1) Data (n + 2) Data (n + x) S T O P P DS22124D-page 12  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 9.0 PRE-PROGRAMMED EUI-48™ NODE ADDRESS The 6-byte EUI-48 node address value is stored in array locations 0xFA through 0xFF, as shown in Figure 9-2. The first 3 bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. Microchip’s OUI is 0x0004A3. The remaining 3 bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 48-bit value. The 24AAXXXE48 is programmed at the factory with a globally unique, EUI-48™ and EUI-64™ compatible node address stored in the upper half of the array and permanently write-protected. The remaining 1,024 bits are available for application use. FIGURE 9-1: MEMORY ORGANIZATION 00h Standard EEPROM 80h Write-Protected EUI-48™ Block FFh 9.1 EUI-64™ Support The pre-programmed EUI-48 node address can easily be encapsulated at the application level to form a globally unique, 64-bit node address for systems utilizing the EUI-64 standard. This is done by adding 0xFFFE between the OUI and the Extension Identifier, as shown below. FIGURE 9-2: EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE Description 24-bit Organizationally Unique Identifier 00h FAh 04h A3h 12h 24-bit Extension Identifier 34h 56h FFh Data Array Address Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address: 00-04-A3-FF-FE-12-34-56  2010 Microchip Technology Inc. DS22124D-page 13 24AA02E48/24AA025E48 10.0 10.1 PACKAGING INFORMATION Package Marking Information 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN Example: 24A2E48I SN e3 1027 13F 5-Lead SOT-23 Example: XXNN 2K3F 6-Lead SOT-23 Example: XXNN HS3F 1st Line Marking Code Part Number SOT-23 I Temp. 24AA02E48 24AA025E48 Note: 2KNN HSNN SOIC I Temp. 24A2E48T 4A25E48T NN = Alphanumeric traceability code DS22124D-page 14  2010 Microchip Technology Inc. 24AA02E48/24AA025E48 Legend: XX...X T Y YY WW NNN Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) e3 Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Note: Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2010 Microchip Technology Inc. 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