25AA02E48
2K SPI Bus Serial EEPROM with EUI-48™ Node Identity
Device Selection Table
Part Number 25AA02E48 VCC Range 1.8-5.5V Page Size 16 Bytes Temp. Ranges I Packages SN, OT
Features:
• Pre-programmed Globally Unique, 48-bit Node Address • Compatible with EUI-48™ and EUI-64™ • 10 MHz max. Clock Frequency • Low-Power CMOS Technology: - Max. Write Current: 5 mA at 5.5V - Read Current: 5 mA at 5.5V, 10 MHz - Standby Current: 1 A at 2.5V • 256 x 8-bit Organization • Write Page mode (up to 16 bytes) • Sequential Read • Self-Timed Erase and Write Cycles (5 ms max.) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: >200 years - ESD protection: >4000V • Temperature Ranges Supported: - Industrial (I): -40C to +85C • Pb-Free and RoHS Compliant
Description:
The Microchip Technology Inc. 25AA02E48 is a 2 Kbit Serial Electrically Erasable Programmable Read-Only Memory (EEPROM). The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. The 25AA02E48 is available in the standard 8-lead SOIC and 6-lead SOT-23 packages.
Package Types (not to scale)
SOT-23
(OT)
SCK VSS SI 1 2 3 6 5 4 VDD CS SO
SOIC
(SN)
CS SO WP VSS
1 2 3 4
8 7 6 5
VCC HOLD SCK SI
Pin Function Table
Name CS SO WP VSS SI SCK HOLD VCC Function Chip Select Input Serial Data Output Write-Protect Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
2010 Microchip Technology Inc.
DS22123B-page 1
25AA02E48
1.0 ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings(†)
VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias .................................................................................................................-40°C to 85°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I): Min. 0.7 VCC -0.3 -0.3 — — VCC -0.5 — — — TA = -40°C to +85°C Max. VCC +1 0.3 VCC 0.2 VCC 0.4 0.2 — ±1 ±1 7 Units V V V V V V A A pF VCC2.7V (Note 1) VCC < 2.7V (Note 1) IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V IOH = -400 A CS = VCC, VIN = VSS TO VCC CS = VCC, VOUT = VSS TO VCC TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C VCC = 1.8V to 5.5V Test Conditions
DC CHARACTERISTICS Param. No. D001 D002 D003 D004 D005 D006 D007 D008 D009 Sym. VIH1 VIL1 VIL2 VOL VOL VOH ILI ILO CINT Characteristic High-level Input voltage Low-level Input Voltage Low-level Output Voltage High-level Output Voltage Input Leakage Current Output Leakage Current Internal Capacitance (all inputs and outputs)
D010
ICC Read Operating Current
— — — — Standby Current —
5 2.5 5 3 1
mA mA mA mA A
D011 D012 Note:
ICC Write ICCS
This parameter is periodically sampled and not 100% tested.
DS22123B-page 2
2010 Microchip Technology Inc.
25AA02E48
TABLE 1-2: AC CHARACTERISTICS
Industrial (I): Min. — — — 50 100 150 100 200 250 50 10 20 30 20 40 50 — — 50 100 150 50 100 150 50 50 — — — 0 — — — 20 40 80 TA = -40°C to +85°C Max. 10 5 3 — — — — — — — — — — — — — 100 100 — — — — — — — — 50 100 160 — 40 80 160 — — — Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns VCC = 1.8V to 5.5V Test Conditions 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V — 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V (Note 1) (Note 1) 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V — — 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V (Note 1) 4.5V VCC 5.5V (Note 1) 2.5V VCC 4.5V (Note 1) 1.8V VCC 2.5V (Note 1) 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V
AC CHARACTERISTICS Param. Sym. No. 1 FCLK Characteristic Clock Frequency
2
TCSS
CS Setup Time
3
TCSH
CS Hold Time
4 5
TCSD Tsu
CS Disable Time Data Setup Time
6
THD
Data Hold Time
7 8 9
TR TF THI
CLK Rise Time CLK Fall Time Clock High Time
10
TLO
Clock Low Time
11 12 13
TCLD TCLE TV
Clock Delay Time Clock Enable Time Output Valid from Clock Low Output Hold Time Output Disable Time
14 15
THO TDIS
16
THS
HOLD Setup Time
Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.
2010 Microchip Technology Inc.
DS22123B-page 3
25AA02E48
TABLE 1-2: AC CHARACTERISTICS (CONTINUED)
Industrial (I): Min. 20 40 80 30 60 160 30 60 160 — 1M TA = -40°C to +85°C Max. — — — — — — — — — 5 — Units ns ns ns ns ns ns ns ns ns ms VCC = 1.8V to 5.5V Test Conditions 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V 4.5V VCC 5.5V (Note 1) 2.5V VCC 4.5V (Note 1) 1.8V VCC 2.5V (Note 1) 4.5V VCC 5.5V 2.5V VCC 4.5V 1.8V VCC 2.5V (Note 3) AC CHARACTERISTICS Param. Sym. No. 17 THH Characteristic HOLD Hold Time
18
THZ
HOLD Low to Output High-Z HOLD High to Output Valid Internal Write Cycle Time (byte or page) Endurance
19
THV
20 21
TWC —
E/W (NOTE 2) Cycles
Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.
TABLE 1-3:
AC Waveform: VLO = 0.2V
AC TEST CONDITIONS
— (Note 1) (Note 2) — 0.5 VCC 0.5 VCC
VHI = VCC - 0.2V VHI = 4.0V CL = 100 pF
Timing Measurement Reference Level Input Output Note 1: For VCC 4.0V 2: For VCC 4.0V
DS22123B-page 4
2010 Microchip Technology Inc.
25AA02E48
FIGURE 1-1:
CS 16 SCK 18 SO n+2 n+1 n High-Impedance 19 n 5 n n-1 n-1 17 16 17
HOLD TIMING
Don’t Care SI HOLD n+2 n+1 n
FIGURE 1-2:
SERIAL INPUT TIMING
4
CS 2 Mode 1,1 SCK Mode 0,0 5 SI 6 LSB in 7 8 3
12 11
MSB in
SO
High-Impedance
FIGURE 1-3:
SERIAL OUTPUT TIMING
CS 9 SCK 13 SO MSB out Don’t Care 14 15 ISB out 10 3 Mode 1,1 Mode 0,0
SI
2010 Microchip Technology Inc.
DS22123B-page 5
25AA02E48
2.0
2.1
FUNCTIONAL DESCRIPTION
Principles of Operation
The 25AA02E48 is a 256-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in software to match the SPI protocol. The 25AA02E48 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSb first, LSb last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA02E48 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted.
After setting the write enable latch, the user may proceed by driving CS low, issuing a WRITE instruction, followed by the remainder of the address, and then the data to be written. Up to 16 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Additionally, a page address begins with XXXX 0000 and ends with XXXX 1111. If the internal address counter reaches XXXX 1111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and overwrite any data that previously existed in those locations. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a Page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary.
2.2
Read Sequence
The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25AA02E48 followed by an 8-bit address. See Figure 2-1 for more details. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. Data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. The internal Address Pointer automatically increments to the next higher address after each byte of data is shifted out. When the highest address is reached (FFh), the address counter rolls over to address 00h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1).
For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is driven high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the STATUS register may be read to check the status of the WIP, WEL, BP1 and BP0 bits (Figure 2-6). Attempting to read a memory array location will not be possible during a write cycle. Polling the WIP bit in the STATUS register is recommended in order to determine if a write cycle is in progress. When the write cycle is completed, the write enable latch is reset.
2.3
Write Sequence
Prior to any attempt to write data to the 25AA02E48, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25AA02E48. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS driven high, data will not be written to the array since the write enable latch was not properly set.
DS22123B-page 6
2010 Microchip Technology Inc.
25AA02E48
BLOCK DIAGRAM
STATUS Register HV Generator
I/O Control Logic
Memory Control Logic
X Dec
EEPROM Array
Page Latches
SI SO CS SCK HOLD WP VCC VSS
Y Decoder
Sense Amp. R/W Control
TABLE 2-1:
INSTRUCTION SET
Instruction Format 0000 x011 0000 x010 0000 x100 0000 x110 0000 x101 0000 x001 Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read STATUS register Write STATUS register
Instruction Name READ WRITE WRDI WREN RDSR WRSR x = don’t care
FIGURE 2-1:
CS 0 SCK 1
READ SEQUENCE
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Address Byte
Instruction SI 0 0 0 0 0 0 1
1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out 7 6 5 4 3 2 1 0
High-Impedance SO
2010 Microchip Technology Inc.
DS22123B-page 7
25AA02E48
FIGURE 2-2:
CS 0 SCK Instruction SI 0 0 0 0 0 0 1 Address Byte 0 A7 A6 A5 A4 A3 A2 A1 A0 High-Impedance SO 7 6 Data Byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Twc
BYTE WRITE SEQUENCE
FIGURE 2-3:
CS 0 SCK 1 2
PAGE WRITE SEQUENCE
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Address Byte Data Byte 1 6 5 4 3 2 1 0
Instruction SI 0 0 0 0 0 01
0 A7 A6 A5 A4 A3 A2 A1 A0 7
CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 SI 7 6 5 4 3 2 1 0 7 6 Data Byte 3 5 4 3 2 1 0 7 Data Byte n (16 max) 6 5 4 3 2 1 0
DS22123B-page 8
2010 Microchip Technology Inc.
25AA02E48
2.4 Write Enable (WREN) and Write Disable (WRDI)
The following is a list of conditions under which the write enable latch will be reset: • • • • • Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WP pin is brought low
The 25AA02E48 contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch.
FIGURE 2-4:
WRITE ENABLE SEQUENCE (WREN)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
1
0
SO
High-Impedance
FIGURE 2-5:
WRITE DISABLE SEQUENCE (WRDI)
CS 0 SCK 1 2 3 4 5 6 7
SI
0
0
0
0
0
1
0
0
High-Impedance SO
2010 Microchip Technology Inc.
DS22123B-page 9
25AA02E48
2.5 Read Status Register Instruction (RDSR)
The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction, which is shown in Figure 2-7. These bits are nonvolatile and are described in more detail in Table 2-3.
The Read Status Register instruction (RDSR) provides access to the STATUS register. See Figure 2-6 for the RDSR timing sequence. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows:
TABLE 2-2:
STATUS REGISTER
0 R WIP
7 654 3 2 1 – – – – W/R W/R R X X X X BP1 BP0 WEL W/R = writable/readable. R = read-only.
The Write-In-Process (WIP) bit indicates whether the 25AA02E48 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only.
FIGURE 2-6:
CS 0 SCK
READ STATUS REGISTER TIMING SEQUENCE (RDSR)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 1 0 1 Data from STATUS register 7 6 5 4 3 2 1 0
High-Impedance SO
DS22123B-page 10
2010 Microchip Technology Inc.
25AA02E48
2.6 Write Status Register Instruction (WRSR)
TABLE 2-3:
BP1
ARRAY PROTECTION
BP0 Array Addresses Write-Protected none upper 1/4 (C0h-FFh) upper 1/2 (80h-FFh) all (00h-FFh)
The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register as shown in Table 2-2. See Figure 2-7 for the WRSR timing sequence. Four levels of protection for the array are selectable by writing to the appropriate bits in the STATUS register. The user has the ability to write-protect none, one, two, or all four of the segments of the array as shown in Table 2-3.
0 0 1 1
0 1 0 1
FIGURE 2-7:
CS 0 SCK
WRITE STATUS REGISTER TIMING SEQUENCE (WRSR)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Instruction SI 0 0 0 0 0 0 0 1 7 6
Data to STATUS register 5 4 3 2 1 0
High-Impedance SO
2010 Microchip Technology Inc.
DS22123B-page 11
25AA02E48
2.7 Data Protection 2.8 Power-On State
The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued The 25AA02E48 powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state
TABLE 2-4:
WP (pin 3) 0 (low) 1 (high) 1 (high)
WRITE-PROTECT FUNCTIONALITY MATRIX
WEL (SR bit 1) x 0 1 Protected Blocks Protected Protected Protected Unprotected Blocks Protected Protected Writable STATUS Register Protected Protected Writable
x = don’t care
DS22123B-page 12
2010 Microchip Technology Inc.
25AA02E48
3.0 PRE-PROGRAMMED EUI-48™ NODE ADDRESS
The 6-byte EUI-48™ node address value is stored in array locations 0xFA through 0xFF, as shown in Figure 3-2. The first 3 bytes are the Organizationally Unique Identifier (OUI) assigned to Microchip by the IEEE Registration Authority. Microchip’s OUI is 0x0004A3. The remaining 3 bytes are the Extension Identifier, and are generated by Microchip to ensure a globally-unique, 48-bit value.
The 25AA02E48 is programmed at the factory with a globally unique, EUI-48™ and EUI-64™ compatible node address stored in the upper 1/4 of the array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use.
FIGURE 3-1:
MEMORY ORGANIZATION
00h
3.1
EUI-64™ Support
Standard EEPROM
Write-Protected EUI-48™ Block
C0h FFh
The pre-programmed EUI-48 node address can easily be encapsulated at the application level to form a globally unique, 64-bit node address for systems utilizing the EUI-64 standard. This is done by adding 0xFFFE between the OUI and the Extension Identifier, as shown below.
FIGURE 3-2:
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE
Description
24-bit Organizationally Unique Identifier 00h FAh 04h A3h 12h
24-bit Extension Identifier 34h 56h FFh
Data Array Address
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56 Corresponding EUI-64™ Node Address: 00-04-A3-FF-FE-12-34-56
3.2
Factory-Programmed Write Protection
In order to help guard against accidental corruption of the EUI-48 node address, the BP1 and BP0 bits of the STATUS register are programmed at the factory to ‘0’ and ‘1’, respectively, as shown in the following table: 7 X — 6 X — 5 X — 4 X — 3 BP1 0 2 BP0 1 1 WEL — 0 WIP —
This protects the upper 1/4 of the array (0xC0 to 0xFF) from write operations. This array block can be utilized for writing by clearing the BP bits with a Write Status Register (WRSR) instruction. Note that if this is performed, care must be taken to prevent overwriting the EUI-48 value.
2010 Microchip Technology Inc.
DS22123B-page 13
25AA02E48
4.0 PIN DESCRIPTIONS
4.5 Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the 25AA02E48. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. The descriptions of the pins are listed in Table 4-1.
TABLE 4-1:
Name CS SO WP VSS SI SCK HOLD VCC SOIC 1 2 3 4 5 6 7 8
PIN FUNCTION TABLE
SOT-23 5 4 — 2 3 1 — 6 Function Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage
4.6
Hold (HOLD)
4.1
Chip Select (CS)
A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated.
The HOLD pin is used to suspend transmission to the 25AA02E48 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25AA02E48 must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line.
4.2
Serial Output (SO)
The SO pin is used to transfer data out of the 25AA02E48. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock.
4.3
Write-Protect (WP)
The WP pin is a hardware write-protect input pin. When it is low, all writes to the array or STATUS register are disabled, but any other operations function normally. When WP is high, all functions, including nonvolatile writes operate normally. At any time, when WP is low, the write enable Reset latch will be reset and programming will be inhibited. However, if a write cycle is already in progress, WP going low will not change or disable the write cycle. See Table 2-4 for the Write-Protect Functionality Matrix.
4.4
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock.
DS22123B-page 14
2010 Microchip Technology Inc.
25AA02E48
5.0
5.1
PACKAGING INFORMATION
Package Marking Information
8-Lead SOIC Example:
XXXXXXXT XXXXYYWW NNN
25A2E48I SN e3 0827 1L7
6-Lead SOT-23
Example:
XXNN
20L7
1st Line Marking Code Part Number SOT-23 I Temp. 25AA02E48 Note: 20NN NN = Alphanumeric traceability code
Legend: XX...X T Y YY WW NNN
e3
Note:
Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn)
For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
Note:
Note:
Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion.
*Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.
2010 Microchip Technology Inc.
DS22123B-page 15
25AA02E48
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