25LC160

Not recommended for new designs – Please use 25AA160A/B or 25LC160A/B. 25AA160/25LC160/25C160 16K SPI™ Bus Serial EEPROM Device Selection Table Part Number 25AA160 25LC160 25C160 VCC Range 1.8-5.5V 2.5-5.5V 4.5-5.5V Max Clock Frequency 1 MHz 2 MHz 3 MHz Temp Ranges I I I,E Description: The Microchip Technology Inc. 25AA160/25LC160/ 25C160 (25XX160*) are 16 Kbit Serial Electrically Erasable PROMs. The memory is accessed via a simple Serial Peripheral Interface™ (SPI™) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of chip select, allowing the host to service higher priority interrupts. Features: • Low-power CMOS technology: - Write current: 3 mA maximum - Read current: 500 µA typical - Standby current: 500 nA typical • 2048 x 8-bit organization • 16 byte page • Write cycle time: 5 ms max. • Self-timed erase and write cycles • Block write protection: - Protect none, 1/4, 1/2 or all of array • Built-in write protection: - Power on/off data protection circuitry - Write enable latch - Write-protect pin • Sequential read • High reliability: - Endurance: 1 M cycles - Data retention: > 200 years - ESD protection: > 4000V • 8-pin PDIP and SOIC packages • Temperature ranges supported: - Industrial (I): - Automotive (E) (25C160): -40°C to +85°C -40°C to +125°C Package Types PDIP/SOIC CS SO WP VSS 1 25XX160 2 3 4 8 7 6 5 VCC HOLD SCK SI Block Diagram Status Register HV Generator I/O Control Logic Memory Control Logic X Dec EEPROM Array Page Latches SI SO CS SCK HOLD WP *25XX160 is used in this document as a generic part number for the 25AA160/25LC160/25C160 devices. SPI™ is a trademark of Motorola Inc. VCC VSS Y Decoder Sense Amp. R/W Control  2004 Microchip Technology Inc. DS21231D-page 1 25AA160/25LC160/25C160 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ........................................................................................................ -0.6V to VCC + 1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias ...............................................................................................................-40°C to 125°C Soldering temperature of leads (10 seconds) .......................................................................................................+300°C ESD protection on all pins ......................................................................................................................................... 4 KV † NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. 1.1 DC Characteristics Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Automotive (E): TA = -40°C to +125°C VCC = 4.5V to 5.5V (25C160 only) Min. 2.0 0.7 VCC -0.3 -0.3 — — VCC -0.5 -10 -10 — Max. VCC+1 VCC+1 0.8 0.3 VCC 0.4 0.2 — 10 10 7 Units V V V V V V V µA µA pF Conditions VCC ≥ 2.7V (Note) VCC< 2.7V (Note) VCC ≥ 2.7V (Note) VCC < 2.7V (Note) IOL = 2.1 mA IOL = 1.0 mA, VCC < 2.5V IOH = -400 µA CS = VCC, VIN = VSS TO VCC CS = VCC, VOUT = VSS TO VCC TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note) VCC = 5.5V; FCLK = 3.0 MHz; SO = Open VCC = 2.5V; FCLK = 2.0 MHz; SO = Open VCC = 5.5V VCC = 2.5V CS = VCC = 5.5V, Inputs tied to VCC or VSS CS = VCC = 2.5V, Inputs tied to VCC or VSS DC CHARACTERISTICS Param. No. D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 Sym. VIH1 VIH2 VIL1 VIL2 VOL VOL VOH ILI ILO CINT Characteristics High-level input voltage Low-level input voltage Low -level output voltage High-level output voltage Input leakage current Output leakage current Internal Capacitance (all inputs and outputs) Operating Current D11 ICC Read — — 1 500 mA µA D12 D13 ICC Write ICCS Standby Current — — — — 5 3 5 1 mA mA µA µA Note: This parameter is periodically sampled and not 100% tested. DS21231D-page 2  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 1.2 AC Characteristics Industrial (I): Automotive (E): Characteristic Clock Frequency Min. — — — 100 250 500 150 250 475 500 30 50 50 50 100 100 — — 150 230 475 150 230 475 50 50 Clock — — — 0 — — — 100 100 200 100 100 200 100 150 200 100 150 200 — 1M TA = -40°C to +85°C TA = -40°C to +125°C Max. 3 2 1 — — — — — — — — — — — — — 2 2 — — — — — — — — 150 230 475 — 200 250 500 — — — — — — — — — — — — 5 — Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms E/W Cycles VCC = 1.8V to 5.5V VCC = 4.5V to 5.5V (25C160 only) Conditions VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V — VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V (Note 1) (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V — — VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V VCC = 4.5V to 5.5V (Note 1) VCC = 2.5V to 4.5V (Note 1) VCC = 1.8V to 2.5V (Note 1) VCC = 4.5V to 5.5V VCC = 2.5V to 4.5V VCC = 1.8V to 2.5V — (Note 2) AC CHARACTERISTICS Param. No. 1 Sym. FCLK 2 TCSS CS Setup Time 3 TCSH CS Hold Time 4 5 TCSD TSU CS Disable Time Data Setup Time 6 THD Data Hold Time 7 8 9 TR TF THI CLK Rise Time CLK Fall Time Clock High Time 10 TLO Clock Low Time 11 12 13 TCLD TCLE TV Clock Delay Time Clock Enable Time Output Valid from Low Output Hold Time Output Disable Time 14 15 THO TDIS 16 THS HOLD Setup Time 17 THH HOLD Hold Time 18 THZ HOLD Low to Output HighZ HOLD High to Output Valid 19 THV 20 21 TWC — Internal Write Cycle Time Endurance Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at: www.microchip.com.  2004 Microchip Technology Inc. DS21231D-page 3 25AA160/25LC160/25C160 FIGURE 1-1: CS 16 SCK 18 SO n+2 n+1 n High-impedance 5 n n-1 19 n n-1 17 16 17 HOLD TIMING don’t care SI HOLD n+2 n+1 n FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 Mode 1,1 SCK Mode 0,0 5 SI MSB in 6 LSB in 7 11 8 3 12 SO High-impedance FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 SCK 13 14 SO MSB out 15 ISB out 10 3 Mode 1,1 Mode 0,0 SI don’t care DS21231D-page 4  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 1.3 AC Test Conditions VLO = 0.2V VHI = VCC - 0.2V VHI = 4.0V Input Output Note 1: For VCC ≤ 4.0V 2: For VCC > 4.0V — (Note 1) (Note 2) SO 0.5 VCC 0.5 VCC 1.8 KΩ 100 pF 2.25 KΩ FIGURE 1-4: AC TEST CIRCUIT VCC AC Waveform: Timing Measurement Reference Level  2004 Microchip Technology Inc. DS21231D-page 5 25AA160/25LC160/25C160 2.0 PIN DESCRIPTIONS 2.4 Serial Input (SI) The descriptions of the pins are listed in Table 2-1. The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. TABLE 2-1: Name CS SO WP VSS SI SCK HOLD Vcc PDIP 1 2 3 4 5 6 7 8 PIN FUNCTION TABLE SOIC 1 2 3 4 5 6 7 8 Description Chip Select Input Serial Data Output Write-Protect Pin Ground Serial Data Input Serial Clock Input Hold Input Supply Voltage 2.5 Serial Clock (SCK) The SCK is used to synchronize the communication between a master and the 25XX160. Instructions, addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. 2.6 Hold (HOLD) 2.1 Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. The HOLD pin is used to suspend transmission to the 25XX160 while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25XX160 must remain selected during this sequence. The SI, SCK, and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. 2.2 Serial Output (SO) The SO pin is used to transfer data out of the 25XX160. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 2.3 Write-Protect (WP) This pin is used in conjunction with the WPEN bit in the Status register to prohibit writes to the nonvolatile bits in the Status register. When WP is low and WPEN is high, writing to the nonvolatile bits in the Status register is disabled. All other operations function normally. When WP is high, all functions, including writes to the nonvolatile bits in the Status register operate normally. If the WPEN bit is set, WP low during a Status register write sequence will disable writing to the Status register. If an internal write cycle has already begun, WP going low will have no effect on the write. The WP pin function is blocked when the WPEN bit in the Status register is low. This allows the user to install the 25XX160 in a system with WP pin grounded and still be able to write to the Status register. The WP pin functions will be enabled when the WPEN bit is set high. DS21231D-page 6  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 3.0 3.1 FUNCTIONAL DESCRIPTION Principles of Operation 3.3 Write Sequence The 25XX160 are 2048 byte Serial EEPROMs designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC16C6X/7X microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly with the software. The 25XX160 contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. The WP pin must be held high to allow writing to the memory array. Table 3-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSB first, LSB last. Data is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25XX160 in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. Prior to any attempt to write data to the 25XX160, the write enable latch must be set by issuing the WREN instruction (Figure 3-4). This is done by setting CS low and then clocking out the proper instruction into the 25XX160. After all eight bits of the instruction are transmitted, the CS must be brought high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS being brought high, the data will not be written to the array because the write enable latch will not have been properly set. Once the write enable latch is set, the user may proceed by setting the CS low, issuing a WRITE instruction, followed by the 16-bit address, with the five MSBs of the address being "don’t care" bits, and then the data to be written. Up to 16 bytes of data can be sent to the 25XX160 before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. A page address begins with xxxx xxxx xxxx 0000 and ends with xxxx xxxx xxxx 1111. If the internal address counter reaches xxxx xxxx xxxx 1111 and the clock continues, the counter will roll back to the first address of the page and overwrite any data in the page that may have been written. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is brought high at any other time, the write operation will not be completed. Refer to Figure 3-2 and Figure 3-3 for more detailed illustrations on the byte write sequence and the page write sequence respectively. While the write is in progress, the Status register may be read to check the status of the WPEN, WIP, WEL, BP1, and BP0 bits (Figure 3-6). A read attempt of a memory array location will not be possible during a write cycle. When the write cycle is completed, the write enable latch is reset. 3.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25XX160 followed by the 16-bit address, with the five MSBs of the address being "don’t care" bits. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. The data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses. The internal address pointer is automatically incremented to the next higher address after each byte of data is shifted out. When the highest address is reached (07FFh), the address counter rolls over to address 0000h allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 3-1). TABLE 3-1: INSTRUCTION SET Instruction Format 0000 0011 0000 0010 0000 0100 0000 0110 0000 0101 0000 0001 Description Read data from memory array beginning at selected address Write data to memory array beginning at selected address Reset the write enable latch (disable write operations) Set the write enable latch (enable write operations) Read Status register Write Status register Instruction Name READ WRITE WRDI WREN RDSR WRSR  2004 Microchip Technology Inc. DS21231D-page 7 25AA160/25LC160/25C160 FIGURE 3-1: CS 0 SCK instruction SI 0 0 0 0 0 0 1 16-bit address 1 15 14 13 12 2 1 0 data out 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 READ SEQUENCE High-impedance SO FIGURE 3-2: CS BYTE WRITE SEQUENCE Twc 0 SCK instruction SI 0 0 0 0 0 0 1 16-bit address 0 15 14 13 12 2 1 0 7 6 data byte 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 High-impedance SO FIGURE 3-3: CS 0 SCK 1 2 PAGE WRITE SEQUENCE 3 4 5 6 7 8 9 10 11 21 22 23 24 25 26 27 28 29 30 31 instruction SI 0 0 0 0 0 01 16-bit address 0 15 14 13 12 2 1 0 7 6 data byte 1 5 4 3 2 1 0 CS 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 SCK data byte 2 SI 7 6 5 4 3 2 1 0 7 6 data byte 3 5 4 3 2 1 0 7 data byte n (16 max) 6 5 4 3 2 1 0 DS21231D-page 8  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 3.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed The 25XX160 contains a write enable latch. See Table 3-3 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 3-4: WRITE ENABLE SEQUENCE CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 1 0 High-impedance SO FIGURE 3-5: WRITE DISABLE SEQUENCE CS 0 SCK 1 2 3 4 5 6 7 SI 0 0 0 0 0 1 0 1 0 High-impedance SO  2004 Microchip Technology Inc. DS21231D-page 9 25AA160/25LC160/25C160 3.5 Read Status Register (RDSR) The Read Status Register (RDSR) instruction provides access to the Status register. The Status register may be read at any time, even during a write cycle. The Status register is formatted as follows: 7 WPEN 6 X 5 X 4 X 3 BP1 2 BP0 1 WEL 0 WIP The Write Enable Latch (WEL) bit indicates the status of the write enable latch. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the Status register. This bit is read-only. The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction. These bits are nonvolatile. See Figure 3-6 for the RDSR timing sequence. The Write-In-Process (WIP) bit indicates whether the 25XX160 is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 3-6: READ STATUS REGISTER TIMING SEQUENCE CS 0 SCK instruction SI 0 0 0 0 0 1 0 1 data from Status register 7 6 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 High-impedance SO 3.6 Write Status Register (WRSR) TABLE 3-2: BP1 0 0 1 1 ARRAY PROTECTION BP0 0 1 0 1 Array Addresses Write-Protected none upper 1/4 (0600h - 07FFh) upper 1/2 (0400h - 07FFh) all (0000h - 07FFh) The Write Status register (WRSR) instruction allows the user to select one of four levels of protection for the array by writing to the appropriate bits in the Status register. The array is divided up into four segments. The user has the ability to write-protect none, one, two or all four of the segments of the array. The partitioning is controlled as shown in Table 3-2. The Write-Protect Enable (WPEN) bit is a nonvolatile bit that is available as an enable bit for the WP pin. The Write-Protect (WP) pin and the Write-Protect Enable (WPEN) bit in the Status register control the programmable hardware write-protect feature. Hardware write protection is enabled when WP pin is low and the WPEN bit is high. Hardware write protection is disabled when either the WP pin is high or the WPEN bit is low. When the chip is hardware write-protected, only writes to nonvolatile bits in the Status register are disabled. See Table 3-3 for a matrix of functionality on the WPEN bit. See Figure 3-7 for the WRSR timing sequence. DS21231D-page 10  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 FIGURE 3-7: CS 0 SCK instruction SI 0 0 0 0 0 0 0 1 7 6 data to Status register 5 4 3 2 1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 WRITE STATUS REGISTER TIMING SEQUENCE High-impedance SO 3.7 Data Protection 3.8 • • • • Power On State The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A WRITE ENABLE instruction must be issued to set the write enable latch • After a byte write, page write, or Status register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued The 25XX160 powers on in the following state: The device is in low power Standby mode (CS = 1) The write enable latch is reset SO is in high-impedance state A low level on CS is required to enter active state TABLE 3-3: WPEN WRITE-PROTECT FUNCTIONALITY MATRIX WP WEL Protected Blocks Protected Protected Protected Protected Unprotected Blocks Protected Writable Writable Writable Status Register Protected Writable Protected Writable X 0 1 X X X Low High 0 1 1 1  2004 Microchip Technology Inc. DS21231D-page 11 25AA160/25LC160/25C160 4.0 4.1 PACKAGING INFORMATION Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: 25LC160 I/PNNN YYWW 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: 25C160 I/SNYYWW NNN Legend: XX...X Customer specific information* YYear code (last digit of calendar year) YYYear code (last 2 digits of calendar year) WWWeek code (week of January 1 is week ‘01’) NNNAlphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard PICmicro device marking consists of Microchip part number, year code, week code, and traceability code. For PICmicro device marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. For QTP devices, any special marking adders are included in QTP price. DS21231D-page 12  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n 1 α E A A2 c L A1 β eB B1 p B Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c B1 B eB α β MIN INCHES* NOM 8 .100 .155 .130 .313 .250 .373 .130 .012 .058 .018 .370 10 10 MAX MIN § .140 .115 .015 .300 .240 .360 .125 .008 .045 .014 .310 5 5 .170 .145 .325 .260 .385 .135 .015 .070 .022 .430 15 15 MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 MAX 4.32 3.68 8.26 6.60 9.78 3.43 0.38 1.78 0.56 10.92 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018  2004 Microchip Technology Inc. DS21231D-page 13 25AA160/25LC160/25C160 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) E E1 p D 2 B n 1 45° h α c A A2 φ β L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L φ c B α β MIN .053 .052 .004 .228 .146 .189 .010 .019 0 .008 .013 0 0 INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN .069 .061 .010 .244 .157 .197 .020 .030 8 .010 .020 15 15 MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 MAX 1.75 1.55 0.25 6.20 3.99 5.00 0.51 0.76 8 0.25 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 DS21231D-page 14  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 APPENDIX A: Revision D Added note to page 1 header (Not recommended for new designs). Updated document format. REVISION HISTORY  2004 Microchip Technology Inc. DS21231D-page 15 25AA160/25LC160/25C160 NOTES: DS21231D-page 16  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have access to the Internet and a web browser, such as Netscape® or Microsoft® Internet Explorer. Files are also available for FTP download from our FTP site. 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Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21231D FAX: (______) _________ - _________ Device: 25AA160/25LC160/25C160 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21231D-page 18  2004 Microchip Technology Inc. 25AA160/25LC160/25C160 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) Device 25AA160: 16 Kbit 1.8V SPI Serial EEPROM 25AA160T: 16 Kbit 1.8V SPI Serial EEPROM (Tape and Reel) 25LC160: 16 Kbit 2.5V SPI Serial EEPROM 25LC160T: 16 Kbit 2.5V SPI Serial EEPROM (Tape and Reel) 25C160: 16 Kbit 5.0V SPI Serial EEPROM 25C160T: 16 Kbit 5.0V SPI Serial EEPROM (Tape and Reel) 25AA160-I/P: Industrial Temp., PDIP package 25AA160-I/SN: Industrial Temp., SOIC package 25LC160-I/SN: Industrial Temp., SOIC package 25LC160T-I/SN: Tape and Reel, Industrial Temp., SOIC package 25C160-E/P: Extended Temp., PDIP package 25C160-E/SN: Extended Temp., SOIC package c) d) e) Temperature Range I E = -40°C to +85°C = -40°C to +125°C = = Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead f) Package P SN Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2004 Microchip Technology Inc. DS21231D-page 19 25AA160/25LC160/25C160 NOTES: DS21231D-page 20  2004 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2004, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2004 Microchip Technology Inc. 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