93AA46A_10

93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1K Microwire Compatible Serial EEPROM Device Selection Table Part Number 93AA46A 93AA46B 93LC46A 93LC46B 93C46A 93C46B 93AA46C 93LC46C 93C46C VCC Range 1.8-5.5 1.8-5-5 2.5-5.5 2.5-5.5 4.5-5.5 4.5-5.5 1.8-5.5 2.5-5.5 4.5-5.5 ORG Pin No No No No No No Yes Yes Yes Word Size 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8- or 16-bit 8- or 16-bit 8- or 16-bit Temp Ranges I I I, E I, E I, E I, E I I, E I, E Packages P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, OT, MC P, SN, ST, MS, MC P, SN, ST, MS, MC P, SN, ST, MS, MC Features: • • • • • • • • • • • • • • Low-Power CMOS Technology ORG Pin to Select Word Size for ‘46C’ Version 128 x 8-bit Organization ‘A’ Devices (no ORG) 64 x 16-bit Organization ‘B’ Devices (no ORG) Self-Timed Erase/Write Cycles (including Auto-Erase) Automatic Erase All (ERAL) Before Write All (WRAL) Power-On/Off Data Protection Circuitry Industry Standard 3-Wire Serial I/O Device Status Signal (Ready/Busy) Sequential Read Function 1,000,000 Erase/Write Cycles Data Retention > 200 Years Pb-free and RoHS Compliant Temperature Ranges Supported: - Industrial (I) -40°C to +85°C - Automotive (E) -40°C to +125°C Pin Function Table Name CS CLK DI DO VSS NC ORG VCC Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground No internal connection Memory Configuration Power Supply Function Description: The Microchip Technology Inc. 93XX46A/B/C devices are 1Kbit low-voltage serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93AA46C, 93LC46C or 93C46C are dependent upon external logic levels driving the ORG pin to set word size. For dedicated 8-bit communication, the 93AA46A, 93LC46A or 93C46A devices are available, while the 93AA46B, 93LC46B and 93C46B devices provide dedicated 16-bit communication. Advanced CMOS technology makes these devices ideal for lowpower, nonvolatile memory applications. The entire 93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All packages are Pb-free (Matte Tin) finish.  2010 Microchip Technology Inc. DS21749H-page 1 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C Package Types (not to scale) ROTATED SOIC (ex: 93LC46BX) NC VCC CS CLK 1 2 3 4 8 ORG* 7 VSS 6 DO 5 DI CS CLK DI DO PDIP/SOIC (P, SN) 1 2 3 4 8 7 6 5 VCC NC ORG* VSS TSSOP/MSOP (ST, MS) CS CLK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG* VSS DO VSS DI SOT-23 (OT) 1 2 3 6 5 4 VCC CS CLK DFN (MC) CS CLK DI DO 1 2 3 4 8 7 6 5 VCC NC ORG* VSS *ORG pin is NC on A/B devices DS21749H-page 2  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ..........................................................................................................-0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied................................................................................................-40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V Min. 2.0 0.7 VCC -0.3 -0.3 — — 2.4 VCC - 0.2 — — — — — — — — — — Typ — — — — — — — — — — — — 500 — — 100 — — Max. VCC +1 VCC +1 0.8 0.2 VCC 0.4 0.2 — — ±1 ±1 7 2 — 1 500 — 1 5 Units V V V V V V V V A A pF mA A mA A A A A Conditions VCC 2.7V VCC 2.7V VCC 2.7V VCC 2.7V IOL = 2.1 mA, VCC = 4.5V IOL = 100 A, VCC = 2.5V IOH = -400 A, VCC = 4.5V IOH = -100 A, VCC = 2.5V VIN = VSS or VCC VOUT = VSS or VCC VIN/VOUT = 0V (Note 1) TA = 25°C, FCLK = 1 MHz FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 2.5V FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 3.0V FCLK = 2 MHz, VCC = 2.5V I-Temp E-Temp CLK = CS = 0V ORG = DI = VSS or VCC (Note 2) (Note 3) (Note 1) 93AA46A/B/C, 93LC46A/B/C 93C46A/B/C All parameters apply over the specified ranges unless otherwise noted. Param. No. D1 D2 D3 D4 D5 D6 D7 D8 D9 Symbol VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT ICC write Parameter High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/outputs) Write current ICC read Read current D10 ICCS Standby current D11 VPOR VCC voltage detect — — 1.5 3.8 — — V V Note 1: This parameter is periodically sampled and not 100% tested. 2: ORG pin not available on ‘A’ or ‘B’ versions. 3: Ready/Busy status must be cleared from DO; see Section 3.4 “Data Out (DO)”.  2010 Microchip Technology Inc. DS21749H-page 3 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V TO +5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V TO +5.5V Min. — Max. 3 2 1 — Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns Conditions 4.5VVCC  5.5V, 93XX46C only 2.5V VCC  5.5V 1.8V VCC 2.5V 4.5VVCC  5.5V, 93XX46C only 2.5V VCC  5.5V 1.8V VCC 2.5V 4.5VVCC  5.5V, 93XX46C only 2.5V VCC  5.5V 1.8V VCC 2.5V 4.5VVCC  5.5V 2.5V VCC  4.5V 1.8V VCC 2.5V 1.8V VCC 5.5V 1.8V VCC 5.5V 4.5VVCC  5.5V, 93XX46C only 2.5V VCC  5.5V 1.8V VCC 2.5V 4.5VVCC  5.5V, 93XX46C only 2.5V VCC  5.5V 1.8V VCC 2.5V 4.5VVCC  5.5V, CL = 100 pF 2.5V VCC  4.5V, CL = 100 pF 1.8V VCC 2.5V, CL = 100 pF 4.5VVCC 5.5V, (Note 1) 1.8VVCC  4.5V, (Note 1) 4.5VVCC  5.5V, CL = 100 pF 2.5V VCC  4.5V, CL = 100 pF 1.8V VCC 2.5V, CL = 100 pF Erase/Write mode (AA and LC versions) Erase/Write mode (93C versions) ERAL mode, 4.5V  VCC  5.5V WRAL mode, 4.5V  VCC  5.5V All parameters apply over the specified ranges unless otherwise noted. Param. No. A1 Symbol FCLK Parameter Clock frequency A2 TCKH Clock high time 200 250 450 100 200 450 50 100 250 0 250 50 100 250 50 100 250 — — — — — — A3 TCKL Clock low time — A4 TCSS Chip Select setup time — A5 A6 A7 TCSH TCSL TDIS Chip Select hold time Chip Select low time Data input setup time — — — A8 TDIH Data input hold time — ns A9 TPD Data output delay time 200 250 400 100 200 200 300 500 6 2 6 15 — ns A10 A11 TCZ TSV Data output disable time Status valid time ns ns A12 A13 A14 A15 A16 TWC TWC TEC TWL — Program cycle time — — — — ms ms ms ms Endurance 1M cycles 25°C, VCC = 5.0V, (Note 2) Note 1: This parameter is periodically sampled and not 100% tested. 2: This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model, which may be obtained from Microchip’s web site at www.microchip.com. DS21749H-page 4  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C FIGURE 1-1: CS VIH VIL VIH CLK VIL TDIS VIH DI VIL DO (Read) DO (Program) Note: VOH VOL VOH VOL Status Valid TSV TPD TPD TCZ TDIH TCSS TCKH TCKL TCSH SYNCHRONOUS DATA TIMING TCZ TSV is relative to CS. TABLE 1-3: INSTRUCTION SET FOR X16 ORGANIZATION (93XX46B OR 93XX46C WITH ORG = 1) Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 A5 1 0 1 A5 A5 0 A4 0 0 1 A4 A4 1 Address A3 X X X A3 A3 X A2 X X X A2 A2 X A1 X X X A1 A1 X A0 X X X A0 A0 X Data In — — — — — D15 - D0 D15 - D0 Data Out (RDY/BSY) (RDY/BSY) High-Z High-Z D15 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 9 9 9 9 25 25 25 TABLE 1-4: INSTRUCTION SET FOR X8 ORGANIZATION (93XX46A OR 93XX46C WITH ORG = 0) Instruction ERASE ERAL EWDS EWEN READ WRITE WRAL SB 1 1 1 1 1 1 1 Opcode 11 00 00 00 10 01 00 Address A6 A5 A4 A3 A2 A1 A0 1 0 1 0 0 1 X X X X X X X X X X X X X X X Data In — — — — — D7 - D0 D7 - D0 Data Out (RDY/BSY) (RDY/BSY) High-Z High-Z D7 - D0 (RDY/BSY) (RDY/BSY) Req. CLK Cycles 10 10 10 10 18 18 18 A6 A5 A4 A3 A2 A1 A0 A6 A5 A4 A3 A2 A1 A0 0 1 X X X X X  2010 Microchip Technology Inc. DS21749H-page 5 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.0 FUNCTIONAL DESCRIPTION 2.3 Data Protection When the ORG pin (93XX46C) is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a High-Z state except when reading data from the device, or when checking the Ready/ Busy status during a programming operation. The Ready/Busy status can be verified during an erase/ write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. DO will enter the High-Z state on the falling edge of CS. All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices or 3.8V for ‘93C’ devices. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. Note: For added protection, an EWDS command should be performed after every write operation and an external 10 k pulldown protection resistor should be added to the CS pin. 2.1 Start Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL or WRAL). As soon as CS is high, the device is no longer in Standby mode. An instruction following a Start condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in. Note: When preparing to transmit an instruction, either the CLK or DI signal levels must be at a logic low as CS is toggled active high. After power-up, the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed. Block Diagram VCC VSS Address Decoder Address Counter Data Register DI ORG* CS CLK Mode Decode Logic Clock Register Output Buffer DO Memory Array 2.2 Data In/Data Out (DI/DO) It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation if A0 is a logic high level. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of A0, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO. *ORG input is not available on A/B devices DS21749H-page 6  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.4 Erase The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. CS is brought low following the loading of the last address bit. This falling edge of the CS pin initiates the self-timed programming cycle, except on ‘93C’ devices where the rising edge of CLK before the last address bit initiates the write cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction. Note: After the Erase cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. FIGURE 2-1: CS ERASE TIMING FOR 93AA AND 93LC DEVICES TCSL Check Status CLK DI 1 1 1 AN AN-1 AN-2 ••• A0 TSV TCZ Ready DO High-Z Busy TWC High-Z FIGURE 2-2: CS ERASE TIMING FOR 93C DEVICES TCSL Check Status CLK DI 1 1 1 AN AN-1 AN-2 ••• A0 TSV TCZ Ready DO High-Z Busy TWC High-Z  2010 Microchip Technology Inc. DS21749H-page 7 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.5 Erase All (ERAL) The Erase All (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different opcode. The ERAL cycle is completely self-timed and commences at the falling edge of the CS, except on ‘93C’ devices where the rising edge of CLK before the last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). Note: After the ERAL command is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. VCC must be  4.5V for proper operation of ERAL. FIGURE 2-3: CS ERAL TIMING FOR 93AA AND 93LC DEVICES TCSL Check Status CLK DI 1 0 0 1 0 x ••• x TSV TCZ Ready DO High-Z Busy TEC High-Z VCC must be  4.5V for proper operation of ERAL. FIGURE 2-4: CS ERAL TIMING FOR 93C DEVICES TCSL Check Status CLK DI 1 0 0 1 0 x ••• x TSV TCZ Ready High-Z DO High-Z Busy TEC DS21749H-page 8  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.6 Erase/Write Disable and Enable (EWDS/EWEN) enabled until an EWDS instruction is executed or Vcc is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. The 93XX46A/B/C powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. Once the EWEN instruction is executed, programming remains FIGURE 2-5: CS EWDS TIMING TCSL CLK DI 1 0 0 0 0 x ••• x FIGURE 2-6: EWEN TIMING TCSL CS CLK DI 1 0 0 1 1 x ••• x 2.7 Read The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (if ORG pin is low or A-version devices) or 16-bit (if ORG pin is high or B-version devices) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. FIGURE 2-7: CS READ TIMING CLK DI 1 1 0 AN ••• A0 DO High-Z 0 Dx ••• D0 Dx ••• D0 Dx ••• D0  2010 Microchip Technology Inc. DS21749H-page 9 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.8 Write The WRITE instruction is followed by 8 bits (if ORG is low or A-version devices) or 16 bits (if ORG pin is high or B-version devices) of data, which are written into the specified address. For 93AA46A/B/C and 93LC46A/B/C devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the selftimed auto-erase and programming cycle is initiated by the rising edge of CLK on the last data bit. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. Note: After the Write cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. FIGURE 2-8: CS WRITE TIMING FOR 93AA AND 93LC DEVICES TCSL CLK DI 1 0 1 AN ••• A0 Dx ••• D0 TSV TCZ Ready DO High-Z Busy TWC High-Z FIGURE 2-9: CS WRITE TIMING FOR 93C DEVICES TCSL CLK DI 1 0 1 AN ••• A0 Dx ••• D0 TSV TCZ Ready DO High-Z Busy TWC High-Z DS21749H-page 10  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 2.9 Write All (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. For 93AA46A/B/C and 93LC46A/B/C devices, after the last data bit is clocked into DI, the falling edge of CS initiates the self-timed auto-erase and programming cycle. For 93C46A/B/C devices, the self-timed autoerase and programming cycle is initiated by the rising edge of CLK on the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). Note: After the Write All cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. VCC must be  4.5V for proper operation of WRAL. FIGURE 2-10: CS WRAL TIMING FOR 93AA AND 93LC DEVICES TCSL CLK DI 1 0 0 0 1 x ••• x Dx ••• D0 TSV TCZ Ready DO High-Z Busy TWL HIGH-Z VCC must be  4.5V for proper operation of WRAL. FIGURE 2-11: CS WRAL TIMING FOR 93C DEVICES TCSL CLK DI 1 0 0 0 1 x ••• x Dx ••• D0 TSV TCZ Ready DO High-Z Busy HIGH-Z TWL  2010 Microchip Technology Inc. DS21749H-page 11 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 3.0 PIN DESCRIPTIONS PIN DESCRIPTIONS SOIC/PDIP/ MSOP/ TSSOP/DFN 1 2 3 4 5 6 7 8 SOT-23 5 4 3 1 2 — — 6 Rotated SOIC 3 4 5 6 7 8 1 2 Chip Select Serial Clock Data In Data Out Ground Organization/93XX46C No Internal Connection/93XX46A/B No Internal Connection Power Supply Function TABLE 3-1: Name CS CLK DI DO Vss ORG/NC NC VCC 3.1 Chip Select (CS) 3.3 Data In (DI) A high level selects the device; a low level deselects the device and forces it into Standby mode. However, a programming cycle that is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. Data In (DI) is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out (DO) is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high after being low for minimum Chip Select low time (TCSL) and an erase or write operation has been initiated. The Status signal is not available on DO if CS is held low during the entire erase or write cycle. In this case, DO is in the High-Z mode. If status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. Note: After a programming cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low level) and can be continued anytime with respect to clock high time (TCKH) and clock low time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don't care” if CS is low (device deselected). If CS is high, but the Start condition has not been detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. CLK and DI then become “don't care” inputs waiting for a new Start condition to be detected. 3.5 Organization (ORG) When the ORG pin is connected to VCC or Logic HI, the (x16) memory organization is selected. When the ORG pin is tied to VSS or Logic LO, the (x8) memory organization is selected. For proper operation, ORG must be tied to a valid logic level. 93XX46A devices are always (x8) organization and 93XX46B devices are always (x16) organization. DS21749H-page 12  2010 Microchip Technology Inc. 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 4.0 4.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP (150 mil) XXXXXXT YWWNNN Example: 3L46BI 5281L7 6-Lead SOT-23 XXNN Example: 1EL7 8-Lead PDIP XXXXXXXX T/XXXNNN YYWW Example: 93LC46B I/P e3 1L7 0528 8-Lead SOIC Example: XXXXXXXT XXXXYYWW NNN 93LC46BI SN e3 0528 1L7 8-Lead Rotated SOIC Example: XXXXXXXT XXXXYYWW NNN 93L46BXI SN e3 0528 1L7 8-Lead TSSOP XXXX TYWW NNN Example: L46B I528 1L7 8-Lead 2x3 DFN XXX YWW NN Example: 314 528 L7  2010 Microchip Technology Inc. DS21749H-page 13 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 1st Line Marking Codes Part Number TSSOP A46A A46B A46C L46A L46B L46C C46A C46B C46C MSOP 3A46AT 3A46BT 3A46CT 3L46AT 3L46BT 3L46CT 3C46AT 3C46BT 3C46CT SOT-23 I Temp. 1BNN 1LNN — 1ENN 1PNN — 1HNN 1TNN — E Temp. — — — 1FNN 1RNN — 1JNN 1UNN — I Temp. 301 311 321 304 314 324 307 317 327 DFN E Temp. — — — 305 315 325 308 318 328 93AA46A 93AA46B 93AA46C 93LC46A 93LC46B 93LC46C 93C46A 93C46B 93C46C Note: T = Temperature grade (I, E) NN = Alphanumeric traceability code Legend: XX...X T Y YY WW NNN e3 Note: Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. 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