93LC76C

93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8K Microwire Compatible Serial EEPROM Device Selection Table Part Number 93AA76A 93AA76B 93LC76A 93LC76B 93C76A 93C76B 93AA76C 93LC76C 93C76C VCC Range 1.8-5.5 1.8-5-5 2.5-5.5 2.5-5.5 4.5-5.5 4.5-5.5 1.8-5.5 2.5-5.5 4.5-5.5 ORG Pin No No No No No No Yes Yes Yes PE Pin No No No No No No Yes Yes Yes Word Size 8-bit 16-bit 8-bit 16-bit 8-bit 16-bit 8 or 16-bit 8 or 16-bit 8 or 16-bit Temp Ranges I I I, E I, E I, E I, E I I, E I, E Packages OT OT OT OT OT OT P, SN, ST, MS, MC P, SN, ST, MS, MC P, SN, ST, MS, MC Features: • • • • • • • • • • • • • • • Low-power CMOS technology ORG pin to select word size for ‘76C’ version 1024 x 8-bit organization ‘A’ devices (no ORG) 512 x 16-bit organization ‘B’ devices (no ORG) Program Enable pin to write-protect the entire array (‘76C’ version only) Self-timed erase/write cycles (including auto-erase) Automatic ERAL before WRAL Power-on/off data protection circuitry Industry standard 3-wire serial I/O Device Status signal (Ready/Busy) Sequential read function 1,000,000 E/W cycles Data retention > 200 years Pb-free and RoHS compliant Temperature ranges supported: - Industrial (I) -40°C to +85°C - Automotive (E) -40°C to +125°C Description: The Microchip Technology Inc. 93XX76A/B/C devices are 8K bit, low-voltage, serial Electrically Erasable PROMs (EEPROM). Word-selectable devices such as the 93XX76C are dependent upon external logic levels driving the ORG pin to set word size. In the SOT-23 package, the 93XX76A devices provide dedicated 8-bit memory organization, while the 93XX76B devices provide dedicated 16-bit memory organization. A Program Enable (PE) pin allows the user to write-protect the entire memory array. Advanced CMOS technology makes these devices ideal for low-power, nonvolatile memory applications. The 93XX Series is available in standard packages including 8-lead PDIP and SOIC, and advanced packaging including 8-lead MSOP, 6-lead SOT-23, 8-lead 2x3 DFN and 8-lead TSSOP. All packages are Pb-free and RoHS compliant. Package Types (not to scale) PDIP/SOIC (P, SN) CS CLK DI DO 1 2 3 4 8 7 6 5 VCC PE ORG VSS DO VSS DI SOT-23 (OT) 1 2 3 6 5 4 DFN (MC) VCC PE ORG VSS CS CLK DI DO 1 2 3 4 8 7 6 5 VCC PE ORG VSS VCC CS CLK Pin Function Table Name CS CLK DI DO VSS PE ORG VCC Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Program Enable Memory Configuration Power Supply Function TSSOP/MSOP (ST, MS) CS CLK DI DO 1 2 3 4 8 7 6 5 © 2006 Microchip Technology Inc. DS21796H-page 1 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings (†) VCC .............................................................................................................................................................................7.0V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-40°C to +125°C ESD protection on all pins ......................................................................................................................................................≥ 4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V Min 2.0 0.7 VCC -0.3 -0.3 — — 2.4 VCC - 0.2 — — — — — — — — — — Typ — — — — — — — — — — — — 500 — — 100 — — Max VCC +1 VCC +1 0.8 0.2 VCC 0.4 0.2 — — ±1 ±1 7 3 — 1 500 — 1 5 Units V V V V V V V V μA μA pF mA μA mA μA μA μA μA Conditions VCC ≥ 2.7V VCC < 2.7V VCC ≥ 2.7V VCC < 2.7V IOL = 2.1 mA, VCC = 4.5V IOL = 100 μA, VCC = 2.5V IOH = -400 μA, VCC = 4.5V IOH = -100 μA, VCC = 2.5V VIN = VSS or VCC VOUT = VSS or VCC VIN/VOUT = 0V (Note 1) TA = 25°C, FCLK = 1 MHz FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 2.5V FCLK = 3 MHz, VCC = 5.5V FCLK = 2 MHz, VCC = 3.0V FCLK = 2 MHz, VCC = 2.5V I – Temp E – Temp CLK = CS = 0V ORG = DI = PE = VSS or VCC (Note 2) (Note 3) (Note 1) 93AA76A/B/C, 93LC76A/B/C 93C76A/B/C All parameters apply over the specified ranges unless otherwise noted. Param. Symbol No. D1 D2 D3 D4 D5 D6 D7 D8 D9 VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 VOH1 VOH2 ILI ILO CIN, COUT Parameter High-level input voltage Low-level input voltage Low-level output voltage High-level output voltage Input leakage current Output leakage current Pin capacitance (all inputs/ outputs) ICC write Write current ICC read Read current D10 ICCS Standby current D11 VPOR VCC voltage detect — — 1.5 3.8 — — V V Note 1: 2: 3: This parameter is periodically sampled and not 100% tested. ORG and PE pins not available on ‘A’ or ‘B’ versions. Ready/Busy status must be cleared from DO, see Section 3.4 “Data Out (DO)”. DS21796H-page 2 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C TABLE 1-2: AC CHARACTERISTICS Industrial (I): TA = -40°C to +85°C, VCC = +1.8V to 5.5V Automotive (E): TA = -40°C to +125°C, VCC = +2.5V to 5.5V Min — Max 3 2 1 — Units MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ms ms ms Conditions 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 1.8V ≤ VCC < 5.5V 1.8V ≤ VCC < 5.5V 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4.5V ≤ VCC < 5.5V 2.5V ≤ VCC < 4.5V 1.8V ≤ VCC < 2.5V 4.5V ≤ VCC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF 4.5V ≤ VCC < 5.5V, (Note 1) 1.8V ≤ VCC < 4.5V, (Note 1) 4.5V ≤ VCC < 5.5V, CL = 100 pF 2.5V ≤ VCC < 4.5V, CL = 100 pF 1.8V ≤ VCC < 2.5V, CL = 100 pF Erase/Write mode (AA and LC versions) Erase/Write mode (93C versions) ERAL mode, 4.5V ≤ VCC ≤ 5.5V WRAL mode, 4.5V ≤ VCC ≤ 5.5V All parameters apply over the specified ranges unless otherwise noted. Param. Symbol No. A1 FCLK Parameter Clock frequency A2 TCKH Clock high time 200 250 450 100 200 450 50 100 250 0 250 50 100 250 50 100 250 — A3 TCKL Clock low time — A4 TCSS Chip Select setup time — A5 A6 A7 TCSH TCSL TDIS Chip Select hold time Chip Select low time Data input setup time — — — A8 TDIH Data input hold time — A9 TPD Data output delay time 100 250 400 100 200 200 300 500 5 2 6 15 — A10 A11 TCZ TSV Data output disable time Status valid time — — A12 A13 A14 A15 A16 Note 1: 2: TWC TWC TEC TWL — Program cycle time — — — — Endurance 1M cycles 25°C, VCC = 5.0V, (Note 2) This parameter is periodically sampled and not 100% tested. This application is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which may be obtained from Microchip’s web site at www.microchip.com. © 2006 Microchip Technology Inc. DS21796H-page 3 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C FIGURE 1-1: CS VIH VIL VIH CLK VIL TDIS VIH DI VIL TPD DO (Read) DO (Program) VOH VOL VOH Status Valid VOL TSV is relative to CS. TCZ TSV TPD TCZ TDIH TCSS TCKH TCKL TCSH SYNCHRONOUS DATA TIMING Note: TABLE 1-3: INSTRUCTION SET FOR X 16 ORGANIZATION (93XX76B OR 93XX76C WITH ORG = 1) Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 X 1 X 1 X 0 0 Address A8 A7 A6 A5 A4 A3 A2 A1 A0 1 x x x x x x x x A8 A7 A6 A5 A4 A3 A2 A1 A0 0 X X X X X X X X A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 x x x x x x x x x x x x x x x x Data In — — — — D15-D0 D15-D0 — Data Out D15-D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 29 13 13 13 29 29 13 TABLE 1-4: INSTRUCTION SET FOR X 8 ORGANIZATION (93XX76A OR 93XX76C WITH ORG = 0) Instruction READ EWEN ERASE ERAL WRITE WRAL EWDS SB 1 1 1 1 1 1 1 Opcode 10 00 11 00 01 00 00 X 1 X 1 X 0 0 Address A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 x x x x x x x x x A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 0 x x x x x x x x x A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 1 0 x x x x x x x x x x x x x x x x x x Data In — — — — D7-D0 D7-D0 — Data Out D7-D0 High-Z (RDY/BSY) (RDY/BSY) (RDY/BSY) (RDY/BSY) High-Z Req. CLK Cycles 22 14 14 14 22 22 14 DS21796H-page 4 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.0 FUNCTIONAL DESCRIPTION 2.2 Data In/Data Out (DI/DO) When the ORG pin (93XX76C) is connected to VCC, the (x16) organization is selected. When it is connected to ground, the (x8) organization is selected. Instructions, addresses and write data are clocked into the DI pin on the rising edge of the clock (CLK). The DO pin is normally held in a High-Z state except when reading data from the device, or when checking the Ready/ Busy status during a programming operation. The Ready/Busy status can be verified during an Erase/ Write operation by polling the DO pin; DO low indicates that programming is still in progress, while DO high indicates the device is ready. DO will enter the High-Z state on the falling edge of CS. It is possible to connect the Data In and Data Out pins together. However, with this configuration it is possible for a “bus conflict” to occur during the “dummy zero” that precedes the read operation, if A0 is a logic highlevel. Under such a condition the voltage level seen at Data Out is undefined and will depend upon the relative impedances of Data Out and the signal source driving A0. The higher the current sourcing capability of the driver, the higher the voltage at the Data Out pin. In order to limit this current, a resistor should be connected between DI and DO. 2.3 Data Protection 2.1 Start Condition The Start bit is detected by the device if CS and DI are both high with respect to the positive edge of CLK for the first time. Before a Start condition is detected, CS, CLK and DI may change in any combination (except to that of a Start condition), without resulting in any device operation (Read, Write, Erase, EWEN, EWDS, ERAL or WRAL). As soon as CS is high, the device is no longer in Standby mode. An instruction following a Start condition will only be executed if the required opcode, address and data bits for any particular instruction are clocked in. Note: When preparing to transmit an instruction, either the CLK or DI signal levels must be at a logic low as CS is toggled active high. All modes of operation are inhibited when VCC is below a typical voltage of 1.5V for ‘93AA’ and ‘93LC’ devices or 3.8V for ‘93C’ devices. The EWEN and EWDS commands give additional protection against accidentally programming during normal operation. Note: For added protection, an EWDS command should be performed after every write operation and an external 10 kΩ pull-down protection resistor should be added to the CS pin. After power-up the device is automatically in the EWDS mode. Therefore, an EWEN instruction must be performed before the initial ERASE or WRITE instruction can be executed. Note: To prevent accidental writes to the array in the 93XX76C devices, set the PE pin to a logic low. Block Diagram VCC VSS Address Decoder Memory Array Address Counter Data Register DI ORG* CS PE* CLK Clock Register Mode Decode Logic Output Buffer DO *ORG and PE inputs are not available on A/B devices. © 2006 Microchip Technology Inc. DS21796H-page 5 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.4 Erase The ERASE instruction forces all data bits of the specified address to the logical ‘1’ state. The rising edge of CLK before the last address bit initiates the write cycle. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been erased and the device is ready for another instruction. Note: After the Erase cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. FIGURE 2-1: CS ERASE TIMING TCSL Check Status CLK DI 1 1 1 AN AN-1 AN-2 ••• A0 TSV TCZ Ready High-Z TWC DO High-Z Busy DS21796H-page 6 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.5 Erase All (ERAL) The Erase All (ERAL) instruction will erase the entire memory array to the logical ‘1’ state. The ERAL cycle is identical to the erase cycle, except for the different opcode. The ERAL cycle is completely self-timed. The rising edge of CLK before the last data bit initiates the write cycle. Clocking of the CLK pin is not necessary after the device has entered the ERAL cycle. The DO pin indicates the Ready/Busy status of the device, if CS is brought high after a minimum of 250 ns low (TCSL). Note: After the ERAL command is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. VCC must be ≥ 4.5V for proper operation of ERAL. FIGURE 2-2: CS ERAL TIMING TCSL Check Status CLK DI 1 0 0 1 0 x ••• x TSV TCZ Ready High-Z TEC DO High-Z Busy © 2006 Microchip Technology Inc. DS21796H-page 7 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.6 Erase/Write Disable and Enable (EWDS/EWEN) Once the EWEN instruction is executed, programming remains enabled until an EWDS instruction is executed or VCC is removed from the device. To protect against accidental data disturbance, the EWDS instruction can be used to disable all erase/write functions and should follow all programming operations. Execution of a READ instruction is independent of both the EWEN and EWDS instructions. The 93XX76A/B/C powers up in the Erase/Write Disable (EWDS) state. All programming modes must be preceded by an Erase/Write Enable (EWEN) instruction. FIGURE 2-3: CS EWDS TIMING TCSL CLK DI 1 0 0 0 0 x ••• x FIGURE 2-4: EWEN TIMING TCSL CS CLK DI 1 0 0 1 1 x ••• x 2.7 Read The READ instruction outputs the serial data of the addressed memory location on the DO pin. A dummy zero bit precedes the 8-bit (If ORG pin is low or A-Version devices) or 16-bit (If ORG pin is high or B-version devices) output string. The output data bits will toggle on the rising edge of the CLK and are stable after the specified time delay (TPD). Sequential read is possible when CS is held high. The memory data will automatically cycle to the next register and output sequentially. FIGURE 2-5: CS READ TIMING CLK DI 1 1 0 An ••• A0 DO High-Z 0 Dx ••• D0 Dx ••• D0 Dx ••• D0 DS21796H-page 8 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.8 Write The WRITE instruction is followed by 8 bits (if ORG is low or A-version devices) or 16 bits (if ORG pin is high or B-version devices) of data which are written into the specified address. The self-timed auto-erase and programming cycle is initiated by the rising edge of CLK on the last data bit. The DO pin indicates the Ready/Busy status of the device, if CS is brought high after a minimum of 250 ns low (TCSL). DO at logical ‘0’ indicates that programming is still in progress. DO at logical ‘1’ indicates that the register at the specified address has been written with the data specified and the device is ready for another instruction. Note: The write sequence requires a logic high signal on the PE pin prior to the rising edge of the last data bit. Note: After the Write cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. FIGURE 2-6: CS WRITE TIMINGS TCSL CLK DI 1 0 1 An ••• A0 Dx ••• D0 TSV TCZ Ready DO High-Z Busy TWC High-Z © 2006 Microchip Technology Inc. DS21796H-page 9 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 2.9 Write All (WRAL) The Write All (WRAL) instruction will write the entire memory array with the data specified in the command. The self-timed auto-erase and programming cycle is initiated by the rising edge of CLK on the last data bit. Clocking of the CLK pin is not necessary after the device has entered the WRAL cycle. The WRAL command does include an automatic ERAL cycle for the device. Therefore, the WRAL instruction does not require an ERAL instruction, but the chip must be in the EWEN status. The DO pin indicates the Ready/Busy status of the device if CS is brought high after a minimum of 250 ns low (TCSL).. Note: The write sequence requires a logic high signal on the PE pin prior to the rising edge of the last data bit. Note: After the Write All cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. VCC must be ≥ 4.5V for proper operation of WRAL. FIGURE 2-7: CS WRAL TIMING TCSL CLK DI 1 0 0 0 1 x ••• x Dx ••• D0 TSV TCZ Ready High-Z TWL DO High-Z Busy DS21796H-page 10 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 3.0 PIN DESCRIPTIONS PIN DESCRIPTIONS SOIC/PDIP/MSOP/ TSSOP/DFN 1 2 3 4 5 6 7 8 SOT-23 5 4 3 1 2 — — 6 Chip Select Serial Clock Data In Data Out Ground Organization / 93XX76C Program Enable Power Supply Function TABLE 3-1: Name CS CLK DI DO VSS ORG PE VCC 3.1 Chip Select (CS) 3.3 Data In (DI) A high level selects the device; a low level deselects the device and forces it into Standby mode. However, a programming cycle which is already in progress will be completed, regardless of the Chip Select (CS) input signal. If CS is brought low during a program cycle, the device will go into Standby mode as soon as the programming cycle is completed. CS must be low for 250 ns minimum (TCSL) between consecutive instructions. If CS is low, the internal control logic is held in a Reset status. Data In (DI) is used to clock in a Start bit, opcode, address and data synchronously with the CLK input. 3.4 Data Out (DO) Data Out (DO) is used in the Read mode to output data synchronously with the CLK input (TPD after the positive edge of CLK). This pin also provides Ready/Busy status information during erase and write cycles. Ready/Busy status information is available on the DO pin if CS is brought high after being low for minimum Chip Select Low Time (TCSL) and an erase or write operation has been initiated. The Status signal is not available on DO, if CS is held low during the entire erase or write cycle. In this case, DO is in the High-Z mode. If status is checked after the erase/write cycle, the data line will be high to indicate the device is ready. Note: After a programming cycle is complete, issuing a Start bit and then taking CS low will clear the Ready/Busy status from DO. 3.2 Serial Clock (CLK) The Serial Clock is used to synchronize the communication between a master device and the 93XX series device. Opcodes, address and data bits are clocked in on the positive edge of CLK. Data bits are also clocked out on the positive edge of CLK. CLK can be stopped anywhere in the transmission sequence (at high or low-level) and can be continued anytime with respect to Clock High Time (TCKH) and Clock Low Time (TCKL). This gives the controlling master freedom in preparing opcode, address and data. CLK is a “don’t care” if CS is low (device deselected). If CS is high, but the Start condition has not been detected (DI = 0), any number of clock cycles can be received by the device without changing its status (i.e., waiting for a Start condition). CLK cycles are not required during the self-timed write (i.e., auto erase/write) cycle. After detection of a Start condition the specified number of clock cycles (respectively, low-to-high transitions of CLK) must be provided. These clock cycles are required to clock in all required opcode, address and data bits before an instruction is executed. CLK and DI then become “don’t care” inputs waiting for a new Start condition to be detected. 3.5 Organization (ORG) When the ORG pin is connected to VCC or Logic HI, the (x16) memory organization is selected. When the ORG pin is tied to VSS or Logic LO, the (x8) memory organization is selected. For proper operation, ORG must be tied to a valid logic level. 93XX76A devices are always x8 organization and 93XX76B devices are always x16 organization. © 2006 Microchip Technology Inc. DS21796H-page 11 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 3.6 Program Enable (PE) This pin allows the user to enable or disable the ability to write data to the memory array. If the PE pin is tied to VCC, the device can be programmed. If the PE pin is tied to VSS, programming will be inhibited. This pin cannot be floated, it must be tied to VCC or VSS. PE is not available on 93XX76A or 93XX76B. On those devices, programming is always enabled. DS21796H-page 12 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 4.0 4.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP (150 mil) Example: 3L76CI 5281L7 XXXXXXT YWWNNN 6-Lead SOT-23 XXNN Example: 4EL7 SOT23 Marking Codes Device 93AA76A 93AA76B 93LC76A 93LC76B 93C76A 93C76B I-temp 4BNN 4LNN 4ENN 4PNN 4HNN 4TNN E-temp – – 4FNN 4RNN 4JNN 4UNN 8-Lead PDIP XXXXXXXX T/XXXNNN YYWW Example: 93LC76C I/P e3 1L7 0528 Pb-free topside mark is same; Pb-free noted only on carton label. 8-Lead SOIC Example: XXXXXXXT XXXXYYWW NNN 93LC76CI SN e3 0528 1L7 8-Lead TSSOP XXXX TYWW NNN Example: L76C I528 1L7 8-Lead 2x3 DFN XXX YWW NN Example: 3B4 528 L7 © 2006 Microchip Technology Inc. DS21796H-page 13 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 1st Line Marking Codes Part Number TSSOP 93AA76C 93LC76C 93C76C Note: A76C L76C C76C T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) MSOP I Temp. 3A76CT 3L76CT 3C76CT 3B1 3B4 3B7 E Temp. — 3B5 3B8 DFN e3 Note: For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. Note: Note: Please visit www.microchip.com/Pbfree for the latest information on Pb-free conversion. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. DS21796H-page 14 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 c A ϕ A1 Units Dim e nsion Limits N e A T hickn e ss A2 A1 E W idth E1 D L L1 ϕ c b L1 MILLIMETERS NOM 8 0.65 BSC — 0.85 — 4.90 BSC 3 .00 BSC 3 .00 BSC 0.60 0.95 REF — — — L MIN MAX Numb e r of Pins Pitch Ov e rall H e ight Mold e d Packag e Standoff Ov e rall Width Mold e d Packag e Ov e rall L e ngth Foot L e ngth Footprint Foot Angl e L e ad Thickn e ss L e ad Width — 0.75 0.00 1.10 0.95 0.15 0.40 0° 0.08 0.22 0.80 8° 0.2 3 0.40 Notes: 1. Pin 1 visual ind e x f e atur e m ay vary, but must b e l ocat e d within th e h atch e d ar e a. 2. Dim e nsions D and E1 do not includ e m old flash or protrusions. Mold flash or protrusions shall not e xc ee d 0.15 mm p e r sid e . 3 . Dim e nsioning and tol e rancing p e r ASME Y14.5M BSC: Basic Dim e nsion. Th e or e tically e xact valu e s hown without tol e ranc e s. REF: R e f e r e nc e D im e nsion, usually without tol e ranc e , for information purpos e s only. Microchip Te chnology Drawing No. C04–111, S e pt. 8, 2006 © 2006 Microchip Technology Inc. DS21796H-page 15 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 6-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 B p1 D n 1 α c φ A A2 β L A1 Units Dimension Limits Number of Pins Pitch Outside lead pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L φ c B α β .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 MIN INCHES* NOM 6 .038 BSC .075 BSC .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.90 0.90 0.00 2.60 1.50 2.80 0.35 0 0.09 0.35 0 0 MAX MIN MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 Revised 09-12-05 DS21796H-page 16 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8-Lead Plastic Dual In-line (P) – 300 mil (PDIP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E1 D 2 n 1 α E A A2 c L A1 β eB B1 p B MAX Number of Pins Pitch Top to Seating Plane A .140 .170 4.32 Molded Package Thickness A2 .115 .145 3.68 Base to Seating Plane A1 .015 Shoulder to Shoulder Width E .300 .313 .325 8.26 Molded Package Width E1 .240 .250 .260 6.60 Overall Length D .360 .373 .385 9.78 Tip to Seating Plane L .125 .130 .135 3.43 c Lead Thickness .008 .012 .015 0.38 Upper Lead Width B1 .045 .058 .070 1.78 Lower Lead Width B .014 .018 .022 0.56 eB Overall Row Spacing § .310 .370 .430 10.92 α Mold Draft Angle Top 5 10 15 15 β Mold Draft Angle Bottom 5 10 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-018 Units Dimension Limits n p MIN INCHES* NOM 8 .100 .155 .130 MAX MIN MILLIMETERS NOM 8 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 9.14 9.46 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 © 2006 Microchip Technology Inc. DS21796H-page 17 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 45° h α c A A2 φ β L A1 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff § A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .146 .157 3.99 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 φ Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 α Mold Draft Angle Top 0 15 15 β Mold Draft Angle Bottom 0 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 Units Dimension Limits n p MIN INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 DS21796H-page 18 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm (TSSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 e D 2 1 n b α c ϕ β L A1 A2 A Units Dimension Limits Number of Pins n Pitch e Overall Height A Molded Package Thickness A2 Standoff A1 Overall Width E Molded Package Width E1 Molded Package Length D Foot Length L Foot Angle ϕ Lead Thickness c Lead Width b Mold Draft Angle Top α Mold Draft Angle Bottom β MIN – .031 .002 .169 .114 .018 0° .004 .007 INCHES NOM 8 .026 BSC – .039 – .252 BSC .173 .118 .024 – – – 12° REF 12° REF MAX MIN .047 .041 .006 .177 .122 .030 8° .008 .012 MILLIMETERS* NOM MAX 8 0.65 BSC – – 1.20 0.80 1.00 1.05 0.05 – 0.15 6.40 BSC 4.30 4.40 4.50 2.90 3.00 3.10 0.45 0.60 0.75 0° – 8° 0.09 – 0.20 0.19 – 0.30 12° REF 12° REF *Controlling Parameter Notes: 1. Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M REF: Reference Dimension, usually without tolerance, for information purposes only. See ASME Y14.5M Drawing No. C04-086 Revised 7-25-06 © 2006 Microchip Technology Inc. DS21796H-page 19 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C 8-Lead Plastic Dual Flat No Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D b N L e N K E E2 EXPOSED PAD NOTE 1 1 2 D2 2 1 NOTE 1 TOP VIEW BOTTOM VIEW A A3 A1 NOTE 2 MILLIMETERS NOM 8 0.50 BSC 0.90 0.02 0.20 REF 2.00 BSC 3.00 BSC — — 0.25 0.40 — Units Dimension Limits Number of Pins N Pitch e Overall Height A Standoff A1 Contact Thickness A3 Overall Length D Overall Width E Exposed Pad Length D2 Exposed Pad Width E2 Contact Width b Contact Length § L Contact-to-Exposed Pad § K MIN MAX 0.80 0.00 1.00 0.05 1.30 1.50 0.18 0.30 0.20 1.75 1.90 0.30 0.50 — Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. § Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–123, Sept. 8, 2006 DS21796H-page 20 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C APPENDIX A: Revision C Corrections to Section 1.0, Electrical Characteristics. Section 4.1, 6-Lead SOT-23 package to OT. Revision D Corrections to Device Selection Table, Table 1-1, Table 1-2, Section 2.4, Section 2.5, Section 2.8 and Section 2.9. Added note to Figure 2-7. Revision E Added DFN package. Revision F Added notes throughout. Revision G Revised note in Sections 2.8 and 2.9. Replaced DFN package drawing. Revision H Updated Package Drawings REVISION HISTORY © 2006 Microchip Technology Inc. DS21796H-page 21 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C NOTES: DS21796H-page 22 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2006 Microchip Technology Inc. DS21796H-page 23 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS21796H FAX: (______) _________ - _________ Device: 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS21796H-page 24 © 2006 Microchip Technology Inc. 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X X /XX Package X Lead Finish Examples: a) b) c) 93AA76C-I/MS: 8K, 1024x8 or 512x16 Serial EEPROM, MSOP package, 1.8V 93AA76AT-I/OT: 8K, 1024x8 Serial EEPROM, SOT-23 package, tape and reel, 1.8V 93AA76CT-I/MS: 8K, 1024x8 or 512x16 Serial EEPROM, MSOP package, tape and reel, 1.8V 93LC76C-I/MS: 8K, 1024x8 or 512x16 Serial EEPROM, MSOP package, 2.5V 93LC76BT-I/OT: 8K, 512x16 Serial EEPROM, SOT-23 package, tape and reel, 2.5V 93C76C-I/MS: 8K, 1024x8 or 512x16 Serial EEPROM, MSOP package, 5.0V 93C76AT-I/OT: 8K, 1024x8 Serial EEPROM, SOT-23 package, tape and reel, 5.0V Tape & Reel Temperature Range Device: 93AA76A: 8K 1.8V Microwire Serial EEPROM (x8) 93AA76B: 8K 1.8V Microwire Serial EEPROM (x16) 93AA76C: 8K 1.8V Microwire Serial EEPROM w/ORG 93LC76A: 8K 2.5V Microwire Serial EEPROM (x8) 93LC76B: 8K 2.5V Microwire Serial EEPROM (x16) 93LC76C: 8K 2.5V Microwire Serial EEPROM w/ORG 93C76A: 93C76B: 93C76C: 8K 5.0V Microwire Serial EEPROM (x8) 8K 5.0V Microwire Serial EEPROM (x16) 8K 5.0V Microwire Serial EEPROM w/ORG a) b) a) b) Tape & Reel: Blank = T = Standard pinout Tape & Reel Temperature Range: I E = = -40°C to +85°C -40°C to +125°C Package: MS OT P SN ST MC = = = = = = Plastic MSOP (Micro Small outline, 8-lead) SOT-23, 6-lead (Tape & Reel only) Plastic DIP (300 mil body), 8-lead Plastic SOIC (150 mil body), 8-lead TSSOP, 8-lead 2x3 DFN, 8-lead Lead Finish: Blank = G = Pb-free – Matte Tin (see Note 1) Pb-free – Matte Tin only Note 1: Most products manufactured after January 2005 will have a Matte Tin (Pb-free) finish. Most products manufactured before January 2005 will have a finish of approximately 63% Sn and 37% Pb (Sn/Pb). Please visit www.microchip.com for the latest information on Pb-free conversion, including conversion date codes. © 2006 Microchip Technology Inc. DS21796H-page 25 93AA76A/B/C, 93LC76A/B/C, 93C76A/B/C NOTES: DS21796H-page 26 © 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. 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