LF182X

PIC16F/LF182X/PIC12F/LF1822 PIC16F/LF182X/PIC12F/LF1822 Memory Programming Specification This document includes the programming specifications for the following devices: • PIC12F1822 • PIC16F1823 • PIC16F1824 • PIC16F1825 • PIC16F1826 • PIC16F1827 • PIC16F1828 • PIC16F1829 • PIC12LF1822 • PIC16LF1823 • PIC16LF1824 • PIC16LF1825 • PIC16LF1826 • PIC16LF1827 • PIC16LF1828 • PIC16LF1829 1.1.2 LOW-VOLTAGE ICSP PROGRAMMING In Low-Voltage ICSP™ mode, these devices can be programmed using a single VDD source in the operating range. The MCLR/VPP pin does not have to be brought to a different voltage, but can instead be left at the normal operating voltage. 1.1.2.1 Single-Supply ICSP Programming 1.0 OVERVIEW The PIC16F/LF182X and PIC12F/LF1822 devices can be programmed using either the high-voltage In-Circuit Serial Programming™ (ICSP™) method or the lowvoltage ICSP™ method. The LVP bit in Configuration Word 2 enables singlesupply (low-voltage) ICSP programming. The LVP bit defaults to a ‘1’ (enabled) from the factory. The LVP bit may only be programmed to ‘0’ by entering the HighVoltage ICSP mode, where the MCLR/VPP pin is raised to VIHH. Once the LVP bit is programmed to a ‘0’, only the High-Voltage ICSP mode is available and only the High-Voltage ICSP mode can be used to program the device. Note 1: The High-Voltage ICSP mode is always available, regardless of the state of the LVP bit, by applying VIHH to the MCLR/VPP pin. 2: While in Low-Voltage ICSP mode, MCLR is always enabled, regardless of the MCLRE bit, and the port pin can no longer be used as a general purpose input. 1.1 1.1.1 Hardware Requirements HIGH-VOLTAGE ICSP PROGRAMMING In High-Voltage ICSP™ mode, these devices require two programmable power supplies: one for VDD and one for the MCLR/VPP pin.  2010 Microchip Technology Inc. Advance Information DS41390C-page 1 PIC16F/LF182X/PIC12F/LF1822 1.2 Pin Utilization Five pins are needed for ICSP™ programming. The pins are listed in Table 1-1 and Table 1-2. TABLE 1-1: PIN DESCRIPTIONS DURING PROGRAMMING – PIC16F1826/PIC16LF1826, PIC16F1827/PIC16LF1827 During Programming Function ICSPCLK ICSPDAT Program/Verify mode VDD VSS P Pin Type I I/O (1) Pin Name RB6 RB7 RA5/MCLR/VPP VDD VSS Legend: Note 1: Pin Description Clock Input – Schmitt Trigger Input Data Input/Output – Schmitt Trigger Input Program Mode Select/Programming Power Supply Power Supply Ground P P I = Input, O = Output, P = Power In the PIC12F/LF1822 and PIC16F/LF182X, the programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current. TABLE 1-2: PIN DESCRIPTIONS DURING PROGRAMMING – PIC12F/LF1822, PIC16F/LF1823, PIC16F/LF1824, PIC16F/LF1825, PIC16F/LF1828 and PIC16F/LF1829 During Programming Function ICSPCLK ICSPDAT Program/Verify mode VDD VSS P Pin Type I I/O (1) Pin Name RA1 RA0 RA3/MCLR/VPP VDD VSS Legend: Note 1: Pin Description Clock Input – Schmitt Trigger Input Data Input/Output – Schmitt Trigger Input Program Mode Select/Programming Power Supply Power Supply Ground P P I = Input, O = Output, P = Power In the PIC12F/LF1822 and PIC16F/LF182X, the programming high voltage is internally generated. To activate the Program/Verify mode, high voltage needs to be applied to MCLR input. Since the MCLR is used for a level source, MCLR does not draw any significant current. DS41390C-page 2 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 2.0 DEVICE PINOUTS FIGURE 2-3: The pin diagrams for the PIC16F/LF182X and PIC12F/ LF1822 family are shown in Figure 2-1 through Figure 2-9. The pins that are required for programming are listed in Table 1-1 and shown in bold lettering in the pin diagrams. 28-PIN DIAGRAM FOR PIC16F1826/1827 AND PIC16LF1826/1827 QFN RA4 RA3 RA2 RA1 RA0 NC 25 23 22 24 NC FIGURE 2-1: 18-PIN DIAGRAM FOR PIC16F1826/1827 AND PIC16LF1826/1827 27 26 28 RA5/MCLR/VPP 1 NC NC 21 PDIP, SOIC RA2 RA3 VSS VSS 2 3 4 5 6 7 PIC16F1826/1827 20 19 NC 17 16 15 RA7 RA6 VDD VDD RB7/ICSPDAT RB6/ICSPCLK PIC16LF1826/1827 18 1 2 PIC16F1826/1827 PIC16LF1826/1827 18 17 16 15 14 13 12 11 10 RA1 RA0 RA7 11 12 13 NC 3 4 5 6 7 8 9 RB1 RB2 RB3 RA5/MCLR/VPP VSS RB0 RB1 RB2 RB3 RA6 VDD RB7/ICSPDAT RB6/ICSPCLK RB5 RB4 FIGURE 2-4: PDIP, SOIC 8-PIN DIAGRAM FOR PIC12F1822/PIC12LF1822 PIC12F1822 PIC12LF1822 FIGURE 2-2: 20-PIN DIAGRAM FOR PIC16F1826/1827 AND PIC16LF1826/1827 RB4 RB5 NC RA4 8 9 10 14 RB0 NC VDD RA5 RA4 RA3/MCLR/VPP 1 2 3 4 8 7 6 5 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 SSOP RA2 RA3 1 2 PIC16F1826/1827 PIC16LF1826/1827 20 19 18 17 16 15 14 13 12 11 RA1 RA0 RA7 RA6 VDD VDD RB7/ICSPDAT PIC12F1822 PIC12LF1822 RA4 RA5/MCLR/VPP VSS VSS RB0 RB1 RB2 RB3 3 4 5 6 7 8 9 FIGURE 2-5: DFN VDD RA5 RA4 RA3/MCLR/VPP 8-PIN DIAGRAM FOR PIC12F1822/PIC12LF1822 RB6/ICSPCLK RB5 RB4 1 2 3 4 8 7 6 5 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 10  2010 Microchip Technology Inc. Advance Information DS41390C-page 3 PIC16F/LF182X/PIC12F/LF1822 FIGURE 2-6: 14-PIN DIAGRAM FOR PIC16F/LF1823, PIC16F/ LF1824 AND PIC16F/LF1825 FIGURE 2-8: 20-PIN DIAGRAM FOR PIC16F/LF1828 AND PIC16F/LF1829 PDIP, SOIC, TSSOP PIC16F/LF1823/1824/1825 PDIP, SOIC, TSSOP VDD RA5 RA4 RA3/MCLR/VPP RC5 RC4 RC3 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 VDD RA5 RA4 RA3/MCLR/VPP RC5 RC4 RC3 RC6 RC7 1 2 20 19 VSS RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 RC1 RC2 RB4 RB5 RB6 PIC16F/LF1828/1829 3 4 5 6 7 8 9 10 18 17 16 15 14 13 12 11 FIGURE 2-7: 16-PIN DIAGRAM FOR PIC16F/LF1823, PIC16F/ LF1824 AND PIC16F/LF1825 RB7 QFN (3x3 or 4x4) VDD NC NC VSS 16 15 14 13 RA5 RA4 RA3/MCLR/VPP RC5 12 2 PIC16F/LF1823/ 11 10 3 1824/1825 4 9 5678 1 RA0/ICSPDAT RA1/ICSPCLK RA2 RC0 FIGURE 2-9: QFN 4x4 RC4 RC3 RC2 RC1 20-PIN DIAGRAM FOR PIC16F/LF1828 AND PIC16F/LF1829 RA4 RA5 VDD Vss RA0/ICSPDAT 20 19 18 17 16 RA3/MCLR/VPP RC5 RC4 RC3 RC6 1 15 2 14 3 PIC16F/LF1828/1829 13 4 12 5 11 6 7 8 9 10 - RA1/ICSPCLK RA2 RC0 RC1 RC2 DS41390C-page 4 Advance Information RC7 RB7 RB6 RB5 RB4  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 3.0 MEMORY MAP The memory for the PIC16F/LF182X and PIC12F/LF1822 devices is broken into two sections: program memory and configuration memory. Only the size of the program memory changes between devices, the configuration memory remains the same. FIGURE 3-1: PIC12F1822/PIC12LF1822, PIC16F1823/PIC16LF1823, PIC16F1826/PIC16LF1826 PROGRAM MEMORY MAPPING 2 KW 0000h 07FFh Implemented Maps to 0-07FFh 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 8009h 800Ah 800Bh-81FFh User ID Location User ID Location User ID Location User ID Location Reserved Reserved Device ID Configuration Word 1 Configuration Word 2 Calibration Word 1 FFFFh Calibration Word 2 Reserved Maps to 8000-81FFh 7FFFh 8000h 8200h Program Memory Implemented Configuration Memory  2010 Microchip Technology Inc. Advance Information DS41390C-page 5 PIC16F/LF182X/PIC12F/LF1822 FIGURE 3-2: PIC16F/LF1827, PIC16F/LF1824 AND PIC16F/LF1828 PROGRAM MEMORY MAPPING 4 KW 0000h 0FFFh Implemented Maps to 0-0FFFh 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 8009h 800Ah 800Bh-81FFh User ID Location User ID Location User ID Location User ID Location Reserved Reserved Device ID Configuration Word 1 Configuration Word 2 Calibration Word 1 FFFFh Calibration Word 2 Reserved Maps to 8000-81FFh 7FFFh 8000h 8200h Program Memory Implemented Configuration Memory DS41390C-page 6 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 FIGURE 3-3: PIC16F/LF1825 AND PIC16F/LF1829 PROGRAM MEMORY MAPPING 4 KW 0000h 1FFFh Implemented Maps to 0-1FFFh 8000h 8001h 8002h 8003h 8004h 8005h 8006h 8007h 8008h 8009h 800Ah 800Bh-81FFh User ID Location User ID Location User ID Location User ID Location Reserved Reserved Device ID Configuration Word 1 Configuration Word 2 Calibration Word 1 FFFFh Calibration Word 2 Reserved Maps to 8000-81FFh 7FFFh 8000h 8200h Program Memory Implemented Configuration Memory  2010 Microchip Technology Inc. Advance Information DS41390C-page 7 PIC16F/LF182X/PIC12F/LF1822 3.1 User ID Location 3.2 Device ID A user may store identification information (user ID) in four designated locations. The user ID locations are mapped to 8000h-8003h. Each location is 14 bits in length. Code protection has no effect on these memory locations. Each location may be read with code protection enabled or disabled. Note: MPLAB® IDE only displays the 7 Least Significant bits (LSb) of each user ID location, the upper bits are not read. It is recommended that only the 7 LSb’s be used if MPLAB IDE is the primary tool used to read these addresses. The device ID word is located at 8006h. This location is read-only and cannot be erased or modified. REGISTER 3-1: R DEV8 bit 13 R DEV1 bit 6 Legend: R = Readable bit -n = Value at POR bit 13-5 bit 4-0 DEVICE ID: DEVICE ID REGISTER(1) R DEV7 R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 bit 7 R DEV0 R REV4 R REV3 R REV2 R REV1 R REV0 bit 0 P = Programmable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DEV: Device ID bits These bits are used to identify the part number. REV: Revision ID bits These bits are used to identify the revision. Note 1: This location cannot be written. DS41390C-page 8 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 TABLE 3-1: DEVICE ID VALUES DEVICE ID VALUES DEV 10 0111 100 10 0111 101 10 1000 100 10 1000 101 10 0111 001 10 1000 001 10 0111 000 10 1000 000 10 0111 010 10 1000 010 10 0111 011 10 1000 011 10 0111 110 10 1000 110 10 0111 111 10 1000 111 REV x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx x xxxx DEVICE PIC16F1826 PIC16F1827 PIC16LF1826 PIC16LF1827 PIC16F1823 PIC16LF1823 PIC12F1822 PIC12LF1822 PIC16F1824 PIC16LF1824 PIC16F1825 PIC16LF1825 PIC16F1828 PIC16LF1828 PIC16F1829 PIC16LF1829 3.3 Configuration Words There are two Configuration Words, Configuration Word 1 (8007h) and Configuration Word 2 (8008h). The individual bits within these Configuration Words are used to enable or disable device functions such as the Brown-out Reset, code protection and Power-up Timer. 3.4 Calibration Words The internal calibration values are factory calibrated and stored in Calibration Words 1 and 2 (8009h, 800Ah). The Calibration Words do not participate in erase operations. The device can be erased without affecting the Calibration Words.  2010 Microchip Technology Inc. Advance Information DS41390C-page 9 PIC16F/LF182X/PIC12F/LF1822 REGISTER 3-2: R/P-1 FCMEN bit 13 R/P-1 MCLRE bit 6 Legend: R = Readable bit -n = Value at POR bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ FCMEN: Fail-Safe Clock Monitor Enable bit 1 = Fail-Safe Clock Monitor is enabled 0 = Fail-Safe Clock Monitor is disabled IESO: Internal External Switchover bit 1 = Internal/External Switchover mode is enabled 0 = Internal/External Switchover mode is disabled CLKOUTEN: Clock Out Enable bit 1 = CLKOUT function is disabled. I/O or oscillator function on CLKOUT pin. 0 = CLKOUT function is enabled on CLKOUT pin BOREN: Brown-out Reset Enable bits(1) 11 = BOR enabled 10 = BOR enabled during operation and disabled in Sleep 01 = BOR controlled by SBOREN bit of the PCON register 00 = BOR disabled CPD: Data Code Protection bit(2) 1 = Data memory code protection is disabled 0 = Data memory code protection is enabled CP: Code Protection bit(3) 1 = Program memory code protection is disabled 0 = Program memory code protection is enabled MCLRE: MCLR/VPP Pin Function Select bit If LVP bit = 1: This bit is ignored. If LVP bit = 0: 1 = MCLR/VPP pin function is MCLR; Weak pull-up enabled. 0 = MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of WPUA register. PWRTE: Power-up Timer Enable bit(1) 1 = PWRT disabled 0 = PWRT enabled WDTE: Watchdog Timer Enable bit 11 = WDT enabled 10 = WDT enabled while running and disabled in Sleep 01 = WDT controlled by the SWDTEN bit in the WDTCON register 00 = WDT disabled FOSC: Oscillator Selection bits 111 = ECH: External Clock, High-Power mode: on CLKIN pin 110 = ECM: External Clock, Medium-Power mode: on CLKIN pin 101 = ECL: External Clock, Low-Power mode: on CLKIN pin 100 = INTOSC oscillator: I/O function on OSC1 pin 011 = EXTRC oscillator: RC function on OSC1 pin 010 = HS oscillator: High-speed crystal/resonator on OSC2 pin and OSC1 pin 001 = XT oscillator: Crystal/resonator on OSC2 pin and OSC1 pin 000 = LP oscillator: Low-power crystal on OSC2 pin and OSC1 pin 1: 2: 3: Enabling Brown-out Reset does not automatically enable Power-up Timer. The entire data EEPROM will be erased when the code protection is turned off during an erase. The entire program memory will be erased when the code protection is turned off. ‘0’ = Bit is cleared x = Bit is unknown P = Programmable Bit R/P-1 PWRTE R/P-1 WDTE1 R/P-1 WDTE0 R/P-1 FOSC2 R/P-1 FOSC1 R/P-1 FOSC0 bit 0 CONFIGURATION WORD 1 R/P-1 IESO R/P-1 CLKOUTEN R/P-1 BOREN1 R/P-1 BOREN0 R/P-1 CPD R/P-1 CP bit 7 bit 12 bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 Note DS41390C-page 10 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 REGISTER 3-3: R/P-1 LVP bit 13 U-1 — bit 6 Legend: R = Readable bit -n = Value at POR bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ LVP: Low-Voltage Programming Enable bit(1) 1 = Low-voltage programming enabled 0 = HV on MCLR/VPP must be used for programming DEBUG: In-Circuit Debugger Mode bit 1 = In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins 0 = In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger Unimplemented: Read as ‘1’ BORV: Brown-out Reset Voltage Selection bit 1 = Brown-out Reset voltage set to 1.9V 0 = Brown-out Reset voltage set to 2.7V STVREN: Stack Overflow/Underflow Reset Enable bit 1 = Stack overflow or underflow will cause a Reset 0 = Stack overflow or underflow will not cause a Reset PLLEN: PLL Enable bit 1 = 4xPLL enabled 0 = 4xPLL disabled Unimplemented: Read as ‘1’ Reserved: Read as ‘1’(2) Unimplemented: Read as ‘1’ WRT: Flash Memory Self-Write Protection bits 2 kW Flash memory (PIC16F1826/PIC16LF1826): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to 7FFh may be modified by EECON control 01 = 000h to 3FFh write-protected, 400h to 7FFh may be modified by EECON control 00 = 000h to 7FFh write-protected, no addresses may be modified by EECON control 4 kW Flash memory (PIC16F1827/PIC16LF1827): 11 = Write protection off 10 = 000h to 1FFh write-protected, 200h to FFFh may be modified by EECON control 01 = 000h to 7FFh write-protected, 800h to FFFh may be modified by EECON control 00 = 000h to FFFh write-protected, no addresses may be modified by EECON control The LVP bit cannot be programmed to ‘0’ when Programming mode is entered via LVP. This bit must be programmed as a ‘1’. ‘0’ = Bit is cleared x = Bit is unknown P = Programmable Bit U-1 — R-1 RESERVED(2) U-1 — U-1 — R/P-1 WRT1 R/P-1 WRT0 bit 0 CONFIGURATION WORD 2 R/P-1 DEBUG U-1 — R/P-1 BORV R/P-1 STVREN R/P-1 PLLEN U-1 — bit 7 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7-5 bit 4 bit 3-2 bit 1-0 Note 1: 2:  2010 Microchip Technology Inc. Advance Information DS41390C-page 11 PIC16F/LF182X/PIC12F/LF1822 4.0 PROGRAM/VERIFY MODE 4.1.3 PROGRAM/VERIFY MODE EXIT In Program/Verify mode, the program memory and the configuration memory can be accessed and programmed in serial fashion. ICSPDAT and ICSPCLK are used for the data and the clock, respectively. All commands and data words are transmitted LSb first. Data changes on the rising edge of the ICSPCLK and latched on the falling edge. In Program/Verify mode both the ICSPDAT and ICSPCLK are Schmitt Trigger inputs. The sequence that enters the device into Program/Verify mode places all other logic into the Reset state. Upon entering Program/Verify mode, all I/Os are automatically configured as high-impedance inputs and the address is cleared. To exit Program/Verify mode take MCLR to VDD or lower (VIL). See Figures 8-3 and 8-4. 4.2 Low-Voltage Programming (LVP) Mode The Low-Voltage Programming mode allows the PIC16F/LF182X and PIC12F/LF1822 devices to be programmed using VDD only, without high voltage. When the LVP bit of Configuration Word 2 register is set to ‘1’, the low-voltage ICSP programming entry is enabled. To disable the Low-Voltage ICSP mode, the LVP bit must be programmed to ‘0’. This can only be done while in the High-Voltage Entry mode. Entry into the Low-Voltage ICSP Program/Verify modes requires the following steps: 1. 2. MCLR is brought to VIL. A 32-bit key sequence is presented on ICSPDAT, while clocking ICSPCLK. 4.1 High-Voltage Program/Verify Mode Entry and Exit There are two different methods of entering Program/ Verify mode via high-voltage: • VPP – First entry mode • VDD – First entry mode 4.1.1 VPP – FIRST ENTRY MODE To enter Program/Verify mode via the VPP-first method the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. All other pins should be unpowered. Raise the voltage on MCLR from 0V to VIHH. Raise the voltage on VDD FROM 0V to the desired operating voltage. The key sequence is a specific 32-bit pattern, '0100 1101 0100 0011 0100 1000 0101 0000' (more easily remembered as MCHP in ASCII). The device will enter Program/Verify mode only if the sequence is valid. The Least Significant bit of the Least Significant nibble must be shifted in first. Once the key sequence is complete, MCLR must be held at VIL for as long as Program/Verify mode is to be maintained. For low-voltage programming timing, see Figure 8-8 and Figure 8-9. Exiting Program/Verify mode is done by no longer driving MCLR to VIL. See Figure 8-8 and Figure 8-9. Note: To enter LVP mode, the LSB of the Least Significant nibble must be shifted in first. This differs from entering the key sequence on other parts. The VPP-first entry prevents the device from executing code prior to entering Program/Verify mode. For example, when Configuration Word 1 has MCLR disabled (MCLRE = 0), the power-up time is disabled (PWRTE = 0), the internal oscillator is selected (FOSC = 100), and ICSPCLK and ICSPDAT pins are driven by the user application, the device will execute code. Since this may prevent entry, VPP-first entry mode is strongly recommended. See the timing diagram in Figure 8-2. 4.1.2 VDD – FIRST ENTRY MODE To enter Program/Verify mode via the VDD-first method the following sequence must be followed: 1. 2. 3. Hold ICSPCLK and ICSPDAT low. Raise the voltage on VDD from 0V to the desired operating voltage. Raise the voltage on MCLR from VDD or below to VIHH. The VDD-first method is useful when programming the device when VDD is already applied, for it is not necessary to disconnect VDD to enter Program/Verify mode. See the timing diagram in Figure 8-1. DS41390C-page 12 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 4.3 Program/Verify Commands The PIC16F/LF182X and PIC12F/LF1822 implement 13 programming commands; each six bits in length. The commands are summarized in Table 4-1. Commands that have data associated with them are specified to have a minimum delay of TDLY between the command and the data. After this delay 16 clocks are required to either clock in or clock out the 14-bit data word. The first clock is for the Start bit and the last clock is for the Stop bit. TABLE 4-1: COMMAND MAPPING Command Mapping Binary (MSb … LSb) x x x x x x x x x x x x x 0 0 0 0 0 0 1 0 1 0 0 0 1 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 1 0 0 1 1 0 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 1 1 Hex 00h 02h 03h 04h 05h 06h 16h 08h 18h 0Ah 09h 0Bh 11h 0, data (14), 0 0, data (14), 0 0, data (8), zero (6), 0 0, data (14), 0 0, data (8), zero (6), 0 — — — — — Internally Timed Internally Timed Internally Timed Data/Note Load Configuration Load Data For Program Memory Load Data For Data Memory Read Data From Program Memory Read Data From Data Memory Increment Address Reset Address Begin Internally Timed Programming Begin Externally Timed Programming End Externally Timed Programming Bulk Erase Program Memory Bulk Erase Data Memory Row Erase Program Memory  2010 Microchip Technology Inc. Advance Information DS41390C-page 13 PIC16F/LF182X/PIC12F/LF1822 4.3.1 LOAD CONFIGURATION The Load Configuration command is used to access the configuration memory (User ID Locations, Configuration Words, Calibration Words). The Load Configuration command sets the address to 8000h and loads the data latches with one word of data (see Figure 4-1). After issuing the Load Configuration command, use the Increment Address command until the proper address to be programmed is reached. The address is then programmed by issuing either the Begin Internally Timed Programming or Begin Externally Timed Programming command. The only way to get back to the program memory (address 0) is to exit Program/Verify mode or issue the Reset Address command after the configuration memory has been accessed by the Load Configuration command. FIGURE 4-1: LOAD CONFIGURATION 1 ICSPCLK 0 2 3 4 5 6 TDLY 1 2 15 16 ICSPDAT 0 0 0 0 X 0 LSb MSb 0 4.3.2 LOAD DATA FOR PROGRAM MEMORY The Load Data for Program Memory command is used to load one 14-bit word into the data latches. The word programs into program memory after the Begin Internally Timed Programming or Begin Externally Timed Programming command is issued (see Figure 4-2). FIGURE 4-2: LOAD DATA FOR PROGRAM MEMORY 1 2 3 4 5 6 TDLY 1 2 15 16 ICSPCLK 0 1 0 0 0 X 0 LSb MSb 0 ICSPDAT DS41390C-page 14 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 4.3.3 LOAD DATA FOR DATA MEMORY The Load Data for Data Memory command will load a 14-bit “data word” when 16 cycles are applied. However, the data memory is only 8 bits wide and thus, only the first 8 bits of data after the Start bit will be programmed into the data memory. It is still necessary to cycle the clock the full 16 cycles in order to allow the internal circuitry to reset properly (see Figure 4-3). FIGURE 4-3: LOAD DATA FOR DATA MEMORY COMMAND 1 ICSPCLK 1 2 3 4 5 6 TDLY 1 2 15 16 ICSPDAT 1 0 0 0 X 0 LSb MSb 0 4.3.4 READ DATA FROM PROGRAM MEMORY The Read Data from Program Memory command will transmit data bits out of the program memory map currently accessed, starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the first falling clock edge, and it will revert to Input mode (high-impedance) after the 16th falling edge of the clock. If the program memory is code-protected (CP), the data will be read as zeros (see Figure 4-4). FIGURE 4-4: READ DATA FROM PROGRAM MEMORY 1 2 3 4 5 6 TDLY 1 2 15 16 ICSPCLK ICSPDAT (from Programmer) ICSPDAT (from device) Input 0 0 1 0 0 X x LSb MSb Input Output  2010 Microchip Technology Inc. Advance Information DS41390C-page 15 PIC16F/LF182X/PIC12F/LF1822 4.3.5 READ DATA FROM DATA MEMORY The Read Data from Data Memory command will transmit data bits out of the data memory starting with the second rising edge of the clock input. The ICSPDAT pin will go into Output mode on the second rising edge, and it will revert to Input mode (high-impedance) after the 16th rising edge. The data memory is 8 bits wide, and therefore, only the first 8 bits that are output are actual data. If the data memory is code-protected, the data is read as all zeros. A timing diagram of this command is shown in Figure 4-5. FIGURE 4-5: READ DATA FROM DATA MEMORY COMMAND 1 2 3 4 5 6 TDLY 1 2 15 16 ICSPCLK ICSPDAT (from Programmer) ICSPDAT (from device) Input 1 0 1 0 0 X x LSb MSb Input Output 4.3.6 INCREMENT ADDRESS The address is incremented when this command is received. It is not possible to decrement the address. To reset this counter, the user must use the Reset Address command or exit Program/Verify mode and reenter it. If the address is incremented from address 7FFFh, it will wrap-around to location 0000h. If the address is incremented from FFFFh, it will wrap-around to location 8000h. FIGURE 4-6: INCREMENT ADDRESS Next Command 1 2 3 4 5 6 TDLY 1 2 3 ICSPCLK 0 1 1 0 0 X X X X ICSPDAT Address Address + 1 DS41390C-page 16 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 4.3.7 RESET ADDRESS The Reset Address command will reset the address to 0000h, regardless of the current value. The address is used in program memory or the configuration memory. FIGURE 4-7: RESET ADDRESS Next Command 1 2 3 4 5 6 TDLY 1 2 3 ICSPCLK 0 1 1 0 1 X X X X ICSPDAT Address N 0000h 4.3.8 BEGIN INTERNALLY TIMED PROGRAMMING A Load Configuration or Load Data for Program Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. An internal timing mechanism executes the write. The user must allow for the program cycle time, TPINT, for the programming to complete. The End Externally Timed Programming command is not needed when the Begin Internally Timed Programming is used to start the programming. The program memory address that is being programmed is not erased prior to being programmed. However, the EEPROM memory address that is being programmed is erased prior to being programmed with internally timed programming. FIGURE 4-8: BEGIN INTERNALLY TIMED PROGRAMMING 1 2 3 4 5 6 TPINT Next Command 1 2 3 ICSPCLK ICSPDAT 0 0 0 1 0 X X X X  2010 Microchip Technology Inc. Advance Information DS41390C-page 17 PIC16F/LF182X/PIC12F/LF1822 4.3.9 BEGIN EXTERNALLY TIMED PROGRAMMING A Load Configuration, Load Data for Program Memory or Load Data for Data Memory command must be given before every Begin Programming command. Programming of the addressed memory will begin after this command is received. To complete the programming the End Externally Timed Programming command must be sent in the specified time window defined by TPEXT. No internal erase is performed for the data EEPROM, therefore, the device should be erased prior to executing this command. The Begin Externally Timed Programming command cannot be used for programming the Configuration Words (see Figure 4-9). FIGURE 4-9: BEGIN EXTERNALLY TIMED PROGRAMMING End Externally Timed Programming Command 1 2 3 4 5 6 TPEXT 1 2 3 ICSPCLK 0 0 0 1 1 X 0 1 0 ICSPDAT 4.3.10 END EXTERNALLY TIMED PROGRAMMING This command is required after a Begin Externally Timed Programming command is given. This command must be sent within the time window specified by TPEXT after the Begin Externally Timed Programming command is sent. After sending the End Externally Timed Programming command, an additional delay (TDIS) is required before sending the next command. This delay is longer than the delay ordinarily required between other commands (see Figure 4-10). FIGURE 4-10: END EXTERNALLY TIMED PROGRAMMING 1 2 3 4 5 6 TDIS Next Command 2 1 3 ICSPCLK ICSPDAT 0 1 0 1 1 X X X X DS41390C-page 18 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 4.3.11 BULK ERASE PROGRAM MEMORY The Bulk Erase Program Memory command performs two different functions dependent on the current state of the address. Address 0000h-7FFFh: Program Memory is erased Configuration Words are erased If CPD = 0, Data Memory is erased Address 8000h-8008h: Program Memory is erased Configuration Words are erased User ID Locations are erased If CPD = 0, Data Memory is erased A Bulk Erase Program Memory command should not be issued when the address is greater than 8008h. After receiving the Bulk Erase Program Memory command the erase will not complete until the time interval, TERAB, has expired. Note: The code protection Configuration bit (CP) has no effect on the Bulk Erase Program Memory command. FIGURE 4-11: BULK ERASE PROGRAM MEMORY 1 2 3 4 5 6 TERAB Next Command 2 1 3 ICSPCLK ICSPDAT 1 0 0 1 0 X X X X 4.3.12 BULK ERASE DATA MEMORY To perform an erase of the data memory, after a Bulk Erase Data Memory command, wait a minimum of TERAB to complete Bulk Erase. To erase data memory when data code-protect is active (CPD = 0), the Bulk Erase Program Memory command should be used. After receiving the Bulk Erase Data Memory command, the erase will not complete until the time interval, TERAB, has expired. Note: Data memory will not erase if codeprotected (CPD = 0). FIGURE 4-12: BULK ERASE DATA MEMORY COMMAND Wait a minimum of TERAB 1 2 3 4 5 6 1 Next Command 2 ICSPCLK ICSPDAT 1 1 0 1 X X X 0  2010 Microchip Technology Inc. Advance Information DS41390C-page 19 PIC16F/LF182X/PIC12F/LF1822 4.3.13 ROW ERASE PROGRAM MEMORY The Row Erase Program Memory command will erase an individual row. Refer to Table 4-2 for row sizes of specific devices and the PC bits used to address them. If the program memory is code-protected the Row Erase Program Memory command will be ignored. When the address is 8000h-8008h the Row Erase Program Memory command will only erase the user ID locations regardless of the setting of the CP Configuration bit. After receiving the Row Erase Program Memory command the erase will not complete until the time interval, TERAR, has expired. TABLE 4-2: PROGRAMMING ROW SIZE AND LATCHES Devices PC Row Size 32 16 32 32 Number of Latches 8 16 32 32 PIC16F1826/1827 PIC12F1822/16F1823 PIC16F1824/1825 PIC16F1828/1829 FIGURE 4-13: ROW ERASE PROGRAM MEMORY 1 2 3 4 5 6 TERAR Next Command 2 1 3 ICSPCLK ICSPDAT 1 0 0 0 1 X X X X DS41390C-page 20 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 5.0 PROGRAMMING ALGORITHMS The PIC12F1822/16F182X devices use internal latches to temporarily store the 14-bit words used for programming. Refer to Table 4-2 for specific latch in formation. The data latches allow the user to write the program words with a single Begin Externally Timed Programming or Begin Internally Timed Programming command. The Load Program Data or the Load Configuration command is used to load a single data latch. The data latch will hold the data until the Begin Externally Timed Programming or Begin Internally Timed Programming command is given. The data latches are aligned with the LSbs of the address. The PC’s address at the time the Begin Externally Timed Programming or Begin Internally Timed Programming command is given will determine which location(s) in memory are written. Writes cannot cross the physical boundary. For example, with the PIC16F1827, attempting to write from address 0002h0009h will result in data being written to 0008h-000Fh. If more than the maximum number of data latches are written without a Begin Externally Timed Programming or Begin Internally Timed Programming command, the data in the data latches will be overwritten. The following figures show the recommended flowcharts for programming.  2010 Microchip Technology Inc. Advance Information DS41390C-page 21 PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-1: DEVICE PROGRAM/VERIFY FLOWCHART Start Enter Programming Mode Bulk Erase Device Write Program Memory(1) Write User IDs Write Data Memory(3) Verify Program Memory Verify User IDs Verify Data Memory Write Configuration Words(2) Verify Configuration Words Exit Programming Mode Done Note 1: 2: 3: See Figure 5-2. See Figure 5-5. See Figure 5-6. DS41390C-page 22 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-2: PROGRAM MEMORY FLOWCHART Start Bulk Erase Program Memory(1, 2) Program Cycle(3) Read Data from Program Memory Data Correct? No Report Programming Failure Yes Increment Address Command No All Locations Done? Yes Done Note 1: 2: 3: This step is optional if device has already been erased or has not been previously programmed. If the device is code-protected or must be completely erased, then Bulk Erase device per Figure 5-8. See Figure 5-3 or Figure 5-4.  2010 Microchip Technology Inc. Advance Information DS41390C-page 23 PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-3: ONE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS DS41390C-page 24 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-4: MULTIPLE-WORD PROGRAM CYCLE Program Cycle Load Data for Program Memory Latch 1 Increment Address Command Load Data for Program Memory Latch 2 Increment Address Command Load Data for Program Memory Latch n Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS  2010 Microchip Technology Inc. Advance Information DS41390C-page 25 PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-5: CONFIGURATION MEMORY PROGRAM FLOWCHART Start Load Configuration Bulk Erase Program Memory(1) One-word Program Cycle(2) (User ID) Read Data From Program Memory Command Data Correct? Yes Increment Address Command No No Report Programming Failure Address = 8004h? Yes Increment Address Command Increment Address Command Increment Address Command One-word Program Cycle(2) (Config. Word 1) Read Data From Program Memory Command No Report Programming Failure Data Correct? Yes Increment Address Command One-word Program Cycle(2) (Config. Word 2) Read Data From Program Memory Command Data Correct? Yes No Report Programming Failure Note 1: 2: This step is optional if device is erased or not previously programmed. See Figure 5-3. Done DS41390C-page 26 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-6: DATA MEMORY PROGRAM FLOWCHART Start Bulk Erase Data Memory Data Program Cycle(1) Read Data From Data Memory Command Data Correct? Yes Increment Address Command No All Locations Done? Yes Done No Report Programming Failure Note 1: See Figure 5-7.  2010 Microchip Technology Inc. Advance Information DS41390C-page 27 PIC16F/LF182X/PIC12F/LF1822 FIGURE 5-7: DATA MEMORY PROGRAM CYCLE Program Cycle Load Data for Data Memory Begin Programming Command (Internally timed) Begin Programming Command (Externally timed) Wait TPINT Wait TPEXT End Programming Command Wait TDIS FIGURE 5-8: ERASE FLOWCHART Start Load Configuration Bulk Erase Program Memory Bulk Erase Data Memory Done Note: This sequence does not erase the Calibration Words. DS41390C-page 28 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 6.0 CODE PROTECTION 7.0 HEX FILE USAGE Code protection is controlled using the CP bit in Configuration Word 1. When code protection is enabled, all program memory locations (0000h-7FFFh) read as all ‘0’. Further programming is disabled for the program memory (0000h-7FFFh). Data memory is protected with its own code-protect bit (CPD). When data code-protection is enabled (CPD = 0), all data memory locations read as ‘0’. Further programming is disabled for the data memory. Data memory can still be programmed and read during program execution. The user ID locations and Configuration Words can be programmed and read out regardless of the code protection settings. In the hex file there are two bytes per program word stored in the Intel® INHX32 hex format. Data is stored LSB first, MSB second. Because there are two bytes per word, the addresses in the hex file are 2x the address in program memory. (Example: Configuration Word 1 is stored at 8007h on the PIC16F/LF182X and PIC12F/LF1822. In the hex file this will be referenced as 1000Eh-1000Fh). 7.1 Configuration Word 6.1 Program Memory Code protection is enabled by programming the CP bit in Configuration Word 1 register to ‘0’. The only way to disable code protection is to use the Bulk Erase Program Memory command. To allow portability of code, it is strongly recommended that the programmer is able to read the Configuration Words and user ID locations from the hex file. If the Configuration Words information was not present in the hex file, a simple warning message may be issued. Similarly, while saving a hex file, Configuration Words and user ID information should be included. 7.2 Device ID and Revision 6.2 Data Memory Data memory protection is enabled by programming the CPD bit in Configuration Word 1 register to ‘0’. The only way to disable code protection is to use the Bulk Erase Program Memory command. Note: To ensure system security, if CPD bit = 0, the Bulk Erase Program Memory command will also erase data memory. If a device ID is present in the hex file at 1000Ch1000Dh (8006h on the part), the programmer should verify the device ID (excluding the revision) against the value read from the part. On a mismatch condition the programmer should generate a warning message. 7.3 Data EEPROM The programmer should be able to read data memory information from a hex file and write data memory contents to a hex file. The physical address range of the 256 byte data memory is 0000h-00FFh. However, these addresses are logically mapped to address 1E000h-1E1FFh in the hex file. This provides a way of differentiating between the data and program memory locations in this range. The format for data memory storage is one data byte per address location, LSb aligned.  2010 Microchip Technology Inc. Advance Information DS41390C-page 29 PIC16F/LF182X/PIC12F/LF1822 7.4 Checksum Computation 7.4.1 The checksum is calculated by two different methods dependent on the setting of the CP Configuration bit. PROGRAM CODE PROTECTION DISABLED TABLE 7-1: Device PIC16F1826 PIC16F1827 PIC16LF1826 PIC16LF1827 PIC12F1822 PIC12LF1822 PIC16F1823 PIC16LF1823 PIC16F1824 PIC16LF1824 PIC16F1825 PIC16LF1825 PIC16F1828 PIC16LF1828 PIC16F1829 PIC16LF1829 CONFIGURATION WORD MASK VALUES Config. Word 1 Mask 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh 3FFFh Config. Word 2 Mask 3713h 3713h 3703h 3703h 3713h 3713h 3713h 3713h 3713h 3713h 3713h 3713h 3713h 3713h 3713h 3713h With the program code protection disabled, the checksum is computed by reading the contents of the PIC16F/LF182X and PIC12F/LF1822 program memory locations and adding up the program memory data starting at address 0000h, up to the maximum user addressable location. Any Carry bit exceeding 16 bits are ignored. Additionally, the relevant bits of the Configuration Words are added to the checksum. All unimplemented Configuration bits are masked to ‘0’. Note: Data memory checksum. does not effect the EXAMPLE 7-1: PIC16F1827 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED PIC16F1827, BLANK DEVICE Sum of Memory addresses 0000h-0FFFh Configuration Word 1 Configuration Word 1 mask Configuration Word 2 Configuration Word 2 mask Checksum = F000h + 3FFFh + 3713h = 6712h F000h 3FFFh 3FFFh 3FFFh 3713h = F000h + (3FFFh and 3FFFh) + (3FFFh and 3713h) EXAMPLE 7-2: PIC16LF1827 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION DISABLED PIC16LF1827, 00AAh AT FIRST AND LAST ADDRESS Sum of Memory addresses 0000h-0FFFh Configuration Word 1 Configuration Word 1 mask Configuration Word 2 Configuration Word 2 mask = 7156h + 3FFFh + 3703h = E858h 7156h 3FFFh 3FFFh 3FFFh 3703h Checksum = 7156h + (3FFFh and 3FFFh) + (3FFFh and 3703h) DS41390C-page 30 Advance Information  2010 Microchip Technology Inc. PIC16F/LF182X/PIC12F/LF1822 7.4.2 PROGRAM CODE PROTECTION ENABLED With the program code protection enabled, the checksum is computed in the following manner: The Least Significant nibble of each User ID is used to create a 16-bit value. The masked value of User ID location 8000h is the Most Significant nibble. This Sum of User IDs is summed with the Configuration Words (all unimplemented Configuration bits are masked to ‘0’). Note: Data memory checksum. does not effect the EXAMPLE 7-3: PIC16F1827 CHECKSUM COMPUTED WITH PROGRAM CODE PROTECTION ENABLED PIC16F1827, BLANK DEVICE Configuration Word 1 Configuration Word 1 mask Configuration Word 2 Configuration Word 2 mask User ID (8000h) User ID (8001h) User ID (8002h) User ID (8003h) 3F7Fh 3FFFh 3FFFh 3713h 0006h 0007h 0001h 0002h (0001h and 000Fh)