MCP1824/MCP1824S
300 mA, Low Voltage, Low Quiescent Current LDO Regulator
Features
• 300 mA Output Current Capability • Input Operating Voltage Range: 2.1V to 6.0V • Adjustable Output Voltage Range: 0.8V to 5.0V (MCP1824 only) • Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V • Other Fixed Output Voltage Options Available Upon Request • Low Dropout Voltage: 200 mV Typical at 300 mA • Typical Output Voltage Tolerance: 0.4% • Stable with 1.0 µF Ceramic Output Capacitor • Fast Response to Load Transients • Low Supply Current: 120 µA (typical) • Low Shutdown Supply Current: 0.1 µA (typical) (MCP1824 only) • Fixed Delay on Power Good Output (MCP1824 only) • Short Circuit Current Limiting and Overtemperature Protection • 5-Lead Plastic SOT-223, SOT-23 Package Options (MCP1824) • 3-Lead Plastic SOT-223 Package Option (MCP1824S)
Description
The MCP1824/MCP1824S is a 300 mA Low Dropout (LDO) linear regulator that provides high current and low output voltages. The MCP1824 comes in a fixed or adjustable output voltage version, with an output voltage range of 0.8V to 5.0V. The 300 mA output current capability, combined with the low output voltage capability, make the MCP1824 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1824S is a 3-pin fixed voltage version. The MCP1824/MCP1824S is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 µF of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1824/MCP1824S is typically less than 120 µA over the entire input voltage range, making it attractive for portable computing applications that demand high output current. The MCP1824 versions have a Shutdown (SHDN) pin. When shut down, the quiescent current is reduced to less than 0.1 µA. On the MCP1824 fixed output versions, the scaleddown output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 110 µs (typical). The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions.
Applications
• • • • • • High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers 2.5V to 1.XV Regulators
2007 Microchip Technology Inc.
DS22070A-page 1
©
MCP1824/MCP1824S
Package Types
MCP1824 Fixed/Adjustable SOT-223-5
6 5 4
MCP1824S
SOT-23-5
SOT-223-3
4
1
2
3 1 2 3
1
2
3
4
5
SOT-223 Pin 1 2 3 4 5 6 Fixed SHDN VIN GND (TAB) VOUT PWRGD GND (TAB) Adjustable SHDN VIN GND (TAB) VOUT ADJ GND (TAB) Fixed VIN
SOT-23 Adjustable VIN GND (TAB) SHDN ADJ VOUT —
Pin 1 2 3 4
SOT-223 VIN GND (TAB) VOUT GND (TAB)
GND (TAB) SHDN PWRGD VOUT —
©
DS22070A-page 2
2007 Microchip Technology Inc.
MCP1824/MCP1824S
Typical Applications
MCP1824 Fixed Output Voltage PWRGD
On Off VIN = 2.3V to 2.8V C1 4.7 µF SHDN VIN 1 GND VOUT
R1 100 kΩ VOUT = 1.8V @ 300 mA
C2 1 µF
MCP1824 Adjustable Output Voltage VADJ R2 20 kΩ
On Off VIN = 2.1V to 2.8V C1 4.7 µF GND SHDN VIN 1 VOUT
R1 40 kΩ
VOUT = 1.2V @ 300 mA
C2 1 µF
2007 Microchip Technology Inc.
DS22070A-page 3
©
MCP1824/MCP1824S
Functional Block Diagram - Adjustable Output (MCP1824)
PMOS VIN VOUT
Undervoltage Lock Out (UVLO)
ISNS
Cf
Rf ADJ/SENSE
SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA –
Overtemperature Sensing
©
DS22070A-page 4
2007 Microchip Technology Inc.
MCP1824/MCP1824S
Functional Block Diagram - Fixed Output (MCP1824S)
PMOS VIN VOUT
Undervoltage Lock Out (UVLO)
Sense ISNS Cf
Rf
SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA –
Overtemperature Sensing
2007 Microchip Technology Inc.
DS22070A-page 5
©
MCP1824/MCP1824S
Functional Block Diagram - Fixed Output (MCP1824)
PMOS VIN VOUT
Undervoltage Lock Out (UVLO)
Sense ISNS Cf
Rf
SHDN Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference PWRGD + EA –
Overtemperature Sensing
©
DS22070A-page 6
2007 Microchip Technology Inc.
MCP1824/MCP1824S
1.0 ELECTRICAL CHARACTERISTICS
† Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
Absolute Maximum Ratings †
Input Voltage, VIN .............................................................6.5V Maximum Voltage on Any Pin ... (GND – 0.3V) to (VIN + 0.3)V Maximum Power Dissipation......... Internally-Limited (Note 6) Output Short Circuit Duration ................................ Continuous Storage temperature .....................................-65°C to +150°C Maximum Junction Temperature, TJ ........................... +150°C Operating Junction Temperature, TJ .............-40°C to +125°C EESD protection on all pins ........... ≥ 4 kV HBM; ≥ 300V MM
AC/DC CHARACTERISTICS
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Input Operating Voltage Output Voltage Range Input Quiescent Current Input Quiescent Current for SHDN Mode Maximum Continuous Output Current Line Regulation Load Regulation Output Short Circuit Current Dropout Voltage Pulsed Applications Maximum Pulsed Output Current IPULSE — 500 — mA VIN = 2.1V to 6.0V VR = 0.8V to 5.0V, Duty Cycle ≤ 60%, Period < 10 ms Sym VIN VOUT Iq ISHDN IOUT ΔVOUT/ (VOUT x ΔVIN) ΔVOUT/VOUT IOUT_SC VDROPOUT Min 2.1 0.8 — — 300 — -1.0 — — Typ — — 120 0.1 — ±0.05 ±0.5 720 200 Max 6.0 5.0 220 3 — ±0.17 1.0 — 320 Units V V µA µA mA %/V % mA mV IL = 0 mA, VOUT = 0.8V to 5.0V SHDN = GND VIN = 2.1V to 6.0V VR = 0.8V to 5.0V (Note 1) ≤ VIN ≤ 6V IOUT = 1 mA to 300 mA, (Note 4) RLOAD < 0.1Ω, Peak Current Note 5, IOUT = 300 mA, VIN(MIN) = 2.1V Conditions
Note 1: 2: 3: 4: 5: 6:
7:
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
2007 Microchip Technology Inc.
DS22070A-page 7
©
MCP1824/MCP1824S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Maximum Pulsed Output Duty Cycle Sym IPULSE_DUTY Min — Typ — Max 60 Units % Conditions VIN = 2.1V to 6.0V, VR = 0.8V to 5.0V, IOUT = 500 mA, Period < 10 ms VIN = 2.1V to 6.0V VR = 0.8V to 5.0V, IOUT = 500 mA
Maximum Pulsed Output Period
IPULSE_PERIOD
—
—
10
ms
Adjust Pin Characteristics (Adjustable Output Only) Adjustable Output Voltage Range Adjust Pin Reference Voltage Adjust Pin Leakage Current Adjust Temperature Coefficient VOUT_ADJ VADJ IADJ TCVOUT VOUT VPWRGD_VIN 0.8 0.402 -10 — — 0.410 ±0.01 40 5.5 0.418 +10 — V V nA ppm/°C VIN = 2.1V to VIN = 6.0V, IOUT = 1 mA VIN = 6.0V, VADJ = 0V to 6V Note 3
Fixed-Output Characteristics (Fixed Output Only) Voltage Regulation Power Good Characteristics PWRGD Input Voltage Operating Range 1.0 1.2 — — 6.0 6.0 V TA = +25°C TA = -40°C to +125°C For VIN < 2.1V, ISINK = 100 µA PWRGD Threshold Voltage (Referenced to VOUT) VPWRGD_TH 89 90 PWRGD Threshold Hysteresis PWRGD Output Voltage Low PWRGD Output Current Sink Capability PWRGD Leakage PWRGD Time Delay Note 1: 2: 3: 4: 5: 6: VPWRGD_HYS VPWRGD_L IPWRGD PWRGD_LK TPG 1.0 — 1.2 — — 92 92 2.0 0.05 6.0 1 110 95 94 3.0 0.4 — — — %VOUT V mA nA µs IPWRGD SINK = 1.2 mA, ADJ = 0V VPWRGD = 0.200V VPWRGD = VIN = 6.0V Rising Edge RPULLUP = 10 kΩ %VOUT Falling Edge VOUT < 2.5V Fixed, VOUT = Adj. VOUT >= 2.5V Fixed VR - 2.5% VR ±0.5% VR + 2.5% V Note 2
7:
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
©
DS22070A-page 8
2007 Microchip Technology Inc.
MCP1824/MCP1824S
AC/DC CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR = 1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Detect Threshold to PWRGD Active Time Delay Shutdown Input Logic High Input Logic Low Input SHDN Input Leakage Current VSHDN-HIGH VSHDN-LOW SHDNILK 45 — -0.1 — — ±0.001 — 15 +0.1 %VIN %VIN µA VIN = 2.1V to 6.0V VIN = 2.1V to 6.0V VIN = 6V, SHDN =VIN, SHDN = GND Sym TVDET-PWRGD Min — Typ 200 Max — Units µs Conditions VOUT = VPWRGD_TH + 50 mV to VPWRGD_TH - 50 mV
AC Performance Output Delay From SHDN Output Noise TOR eN — — 100 2.0 — — µs µV/√Hz SHDN = GND to VIN, VOUT = GND to 95% VR IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V f = 100 Hz, IOUT = 10 mA, VINAC = 200 mV pk-pk, CIN = 0 µF IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V
Power Supply Ripple Rejection Ratio
PSRR
—
55
—
dB
Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: 5: 6:
TSD ΔTSD
— —
150 10
— —
°C °C
7:
The minimum VIN must meet two conditions: VIN ≥ 2.1V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant.
2007 Microchip Technology Inc.
DS22070A-page 9
©
MCP1824/MCP1824S
TEMPERATURE SPECIFICATIONS
Parameters Temperature Ranges Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Thermal Package Resistances Thermal Resistance, 3LD SOT-223 Thermal Resistance, 5LD SOT-23 Thermal Resistance, 5LD SOT-223 θJA θJC θJA θJC θJA θJC — — — — — — 62 15 256 81 62 15 — — — — — — °C/W °C/W °C/W EIA/JEDEC JESD51-751-7 4 Layer Board EIA/JEDEC JESD51-751-7 4 Layer Board EIA/JEDEC JESD51-751-7 4 Layer Board TJ TJ TA -40 — -65 — — — +125 +150 +150 °C °C °C Steady State Transient Sym Min Typ Max Units Conditions
©
DS22070A-page 10
2007 Microchip Technology Inc.
MCP1824/MCP1824S
2.0
Note:
TYPICAL PERFORMANCE CURVES
The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
140 Quiescent Current ( A) 130 120 110 100 90 2 3 4 Input Voltage (V) 5 6 Line Regulation (%/V)
VOUT = 1.2V Adj IOUT = 0 mA 130°C 90°C 25°C 0°C -45°C
0.10 0.08 0.06 0.04 0.02 0.00 -0.02 -0.04 -0.06 -0.08 -0.10
IOUT = 1 mA
VOUT = 1.2V adj VIN = 2.1V to 6.0V
FIGURE 2-1: Quiescent Current vs. Input Voltage (Adjustable Version).
180 Ground Current ( A)
Load Regulation (%)
FIGURE 2-2: Ground Current vs. Load Current (Adjustable Version).
170 Quiescent Current ( A)
Adjust Pin Voltage (V)
FIGURE 2-3: Quiescent Current vs. Junction Temperature (Adjustable Version).
2007 Microchip Technology Inc.
μ
μ μ
IOUT = 50 mA IOUT=100 mA IOUT=200 mA IOUT=300 mA
-45
-20
5
30
55
80
105
130
Temperature (°C)
FIGURE 2-4: Line Regulation vs. Temperature (Adjustable Version).
0.10
170 160 150 140 130 120 110 100 0 50 100 150
VIN=2.5V VIN=3.3V VIN=5.0V
VOUT = 1.2V Adj
VOUT = 3.3V
IOUT = 1.0 mA to 300 mA VOUT = 0.8V
0.05 0.00 -0.05 -0.10
VOUT = 5.0V
VOUT = 1.8V
-0.15 -0.20
200
250
300
-45
-20
5
30
55
80
105
130
Load Current (mA)
Temperature (°C)
FIGURE 2-5: Load Regulation vs. Temperature (Adjustable Version).
0.413 0.412 0.411 0.410 0.409 0.408 0.407
VIN = 2.1V VIN = 4.0V VIN = 6.0V VOUT = 1.2V IOUT = 1.0 mA
160 150 140 130 120 110 100 90 -45 -20 5 30 55
VIN=2.1V VIN=3.0V VIN=5.0V VIN=6.0V
VOUT = 0.8V Adj IOUT = 0 mA
VIN=4.0V
80
105
130
-45
-20
5
30
55
80
105
130
Temperature (°C)
Temperature (°C)
FIGURE 2-6: Adjust Pin Voltage vs. Temperature (Adjustable Version).
DS22070A-page 11
©
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
0.30 Quiescent Current ( A) Dropout Voltage (V) 160 150 140 130 120 110 100 90 0 50 100 150 200 250 300 2 3 4 Input Voltage (V) 5 6
0.20 0.15 0.10 0.05 0.00
VOUT = 5.0V Adj
VOUT = 2.5V Adj
Load Current (mA)
FIGURE 2-7: Dropout Voltage vs. Load Current (Adjustable Version).
0.24 0.23 0.22 0.21 0.20 0.19 0.18 0.17 0.16 0.15 0.14 -45 -20 5
FIGURE 2-10: Voltage.
150 Quiescent Current ( A) 140 130 120 110 100 90
IOUT = 300 mA
Dropout Voltage (V)
VOUT = 5.0V Adj
VOUT = 3.3V Adj VOUT = 2.5V Adj
30
55
80
105
130
Temperature (°C)
FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version).
Power Good Time Delay (µS) 110
FIGURE 2-11: Voltage.
250 Ground Current ( A)
100
VIN = 5.0V
VOUT = 0.8V Fixed IOUT = 0 mA
90 80 70 60 50 -45 -20 5 30 55 80 105 130 Temperature (°C)
VIN = 2.1V VIN = 3.3V
FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature.
FIGURE 2-12: Current.
©
DS22070A-page 12
μ
μ
0.25
VOUT = 0.8V IOUT = 0 mA +130°C +90°C +25°C 0°C -45°C
Quiescent Current vs. Input
VOUT = 2.5V IOUT = 0 mA
+130°C +90°C +25°C +0°C -45°C
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Input Voltage (V)
Quiescent Current vs. Input
200 150 100 50 0 0 50 100
VIN = 2.1V for VR=0.8V VIN = 3.5V for VR=3.0V
μ
VOUT=3.0V
VOUT=0.8V
150
200
250
300
Load Current (mA)
Ground Current vs. Load
2007 Microchip Technology Inc.
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
130 Quiescent Current ( A) 125 120 115 110 105 100 95 90 -45 -20 5 30 55 80 105 130
VOUT = 2.5V
IOUT = 0 mA
0.042 Line Regulation (%/V) 0.038 0.034 0.030 0.026 0.022 0.018 0.014 0.010 -45 -20 5 30 55 80 105 130
IOUT = 200 mA IOUT = 300 mA IOUT = 50 mA IOUT = 100 mA IOUT = 1 mA VR = 2.5V VIN = 3.0V to 6.0V
FIGURE 2-13: Temperature.
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 -45
Load Regulation (%)
FIGURE 2-14:
Line Regulation (%/V)
Load Regulation (%)
FIGURE 2-15: Temperature.
2007 Microchip Technology Inc.
μ
Ishdn ( A)
μ
VOUTc 0.8V =
Temperature (°C)
Temperature (°C)
Quiescent Current vs.
FIGURE 2-16: Temperature.
Line Regulation vs.
VR = 0.8V
VIN = 6.0V
VIN = 2.3V VIN = 3.3V
0.20 0.15 0.10 0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -45
VIN = 4.0V
VOUT = 0.8V IOUT = 1 mA to 300 mA
VIN = 2.1V VIN = 5.0V
VIN = 6.0V
-20
5
30
55
80
105
130
-20
5
30
55
80
105
130
Temperature (°C)
Temperature (°C)
ISHDN vs. Temperature.
FIGURE 2-17: Temperature.
0.10
Load Regulation vs.
0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 0.02 0.01 0.00
IOUT = 1 mA IOUT = 50 mA
VOUT = 0.8V VIN = 2.1V to 6.0V
0.05 0.00 -0.05 -0.10 -0.15 -0.20 -0.25 -0.30 -45
VOUT = 0.8V
IOUT = 1 mA to 300 mA
VOUT = 2.5V
IOUT = 100 mA
IOUT = 200 mA IOUT = 300 mA
VOUT = 5.0V
-45
-20
5
30
55
80
105
130
-20
5
30
55
80
105
130
Temperature (°C)
Temperature (°C)
Line Regulation vs.
FIGURE 2-18: Temperature.
Load Regulation vs.
DS22070A-page 13
©
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
0.20 0.18 0.16 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0.00 0 50 100 10.000
Dropout Voltage (V)
VOUT = 5.0V VOUT = 2.5V
Noise (mV/√Hz)
1.000
VR=0.8V, VIN=2.1V
IOUT=200 mA
0.100
150
200
250
300
0.010 0.01
0.1
Load Current (mA)
1 10 Frequency (kHz)
100
FIGURE 2-19: Current.
0.24
Dropout Voltage vs. Load
FIGURE 2-22: Output Noise Voltage Density vs. Frequency.
0.0 -10.0 -20.0 PSRR (dB)
IOUT = 300 mA
Dropout Voltage (V)
0.22 0.20 0.18 0.16 0.14 0.12 -45 -20 5 30 55 80 105 130 Temperature (°C)
VOUT = 2.5V VOUT = 5.0V
-30.0 -40.0 -50.0 -60.0 -70.0 -80.0 0.01 0.1
VR=1.2V Adj VIN=2.5V VINAC = 200 mV p-p CIN=0 F IOUT=10 mA
1 10 Frequency (kHz)
100
FIGURE 2-20: Temperature.
Dropout Voltage vs.
FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (Adj.).
0.0
Short Circuit Current (mA)
600.00 500.00 400.00 300.00 200.00 100.00 0.00 0 1 2 3
VOUT = 0.8V
-10.0 -20.0
PSRR (dB)
-30.0 -40.0 -50.0 -60.0 -70.0 -80.0 -90.0 0.01
VR=3.0V (Fixed) VIN=3.5V VINAC=200 mV p-p CIN=0 F IOUT=10 mA
4
5
6
0.1
Input Voltage (V)
1 10 Frequency (kHz)
100
FIGURE 2-21: Input Voltage.
Short Circuit Current vs.
FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency.
©
DS22070A-page 14
2007 Microchip Technology Inc.
μ μ
VR=3.0V, VIN=3.8V
COUT=10 F cer CIN=4.7 F cer
1000
μ
1000
μ
1000
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
FIGURE 2-25: Startup from VIN (Adjustable Version).
FIGURE 2-28: Timing.
Power Good (PWRGD)
FIGURE 2-26: Startup from Shutdown (Adjustable Version).
FIGURE 2-29:
Dynamic Line Response.
FIGURE 2-27: Timing.
Power Good (PWRGD)
FIGURE 2-30:
Dynamic Line Response.
2007 Microchip Technology Inc.
DS22070A-page 15
©
MCP1824/MCP1824S
Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.5V, Fixed output, SHDN = 10 kΩ pullup to VIN.
900 PWRGD Voltage (mV) 800 700 600 500 400 300 200 100 0 0 2 4 6 8 10 12 14 16 18 20 PWRGD Sink Current (mA)
VR = 5.0V VR = 3.0V VR = 0.8V
FIGURE 2-31:
Dynamic Load Response.
FIGURE 2-33: Voltage Vs Load.
Power Good Pulldown
FIGURE 2-32:
Dynamic Load Response.
FIGURE 2-34:
Startup Current.
©
DS22070A-page 16
2007 Microchip Technology Inc.
MCP1824/MCP1824S
3.0 PIN DESCRIPTION
PIN FUNCTION TABLE
SOT-23 5-Pin Adj 1 2 3 4
—
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
SOT-223 3-Pin Fixed
—
5-Pin Fixed 1 2 3 4 5
—
5-Pin Fixed 3 1 2 5 4
— —
5-Pin Adj 3 1 2 5
—
Name
Description
SHDN VIN GND VOUT PWRGD ADJ EP
Shutdown Control Input (active-low) Input Voltage Supply Ground Regulated Output Voltage Power Good Output Output Voltage Adjust/Sense Input Exposed Pad of the Package (ground potential)
1 2 3
— —
5
4
—
Exposed Exposed Exposed Pad Pad Pad
3.1
Shutdown Control Input (SHDN)
3.4
Regulated Output Voltage (VOUT)
The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 µA.
The VOUT pin is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 µF is required for LDO stability. The MCP1824/MCP1824S is stable with ceramic, tantalum, and aluminumelectrolytic capacitors. See Section 4.3 “Output Capacitor” for output capacitor selection guidance.
3.5
Power Good Output (PWRGD)
3.2
Input Voltage Supply (VIN)
Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 µF to 10 µF should be sufficient for most applications. The type of capacitor used can be ceramic, tantalum, or aluminum electrolytic. The low ESR characteristics of the ceramic capacitor will yield better noise and PSRR performance at high frequency.
For fixed applications, the PWRGD output is an opendrain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is delayed by 110 µs (typical) from the time the LDO output is within 92% + 3% (maximum hysteresis) of the regulated output value on power-up. This delay time is internally fixed.
3.6
Output Voltage Adjust Input (ADJ)
3.3
Ground (GND)
For the optimal Noise and Power Supply Rejection Ratio (PSRR) performance, the GND pin of the LDO should be tied to an electrically quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the ground current of the LDO, so a heavy trace is not required. For applications that have switching or noisy inputs, tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients.
For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the users the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device.
3.7
Exposed Pad (EP)
The SOT-223 package has an exposed metal pad on the bottom of the package. The exposed metal pad gives the device better thermal characteristics by providing a good thermal path to either the PCB or heatsink to remove heat from the device. The exposed pad of the package is at ground potential.
2007 Microchip Technology Inc.
DS22070A-page 17
©
MCP1824/MCP1824S
4.0 DEVICE OVERVIEW
The MCP1824/MCP1824S is a 300 mA output current, Low Dropout (LDO) voltage regulator. The low dropout voltage of 200 mV typical at 300 mA of current makes it ideal for battery-powered applications. The input voltage range is 2.1V to 6.0V. Unlike other high output current LDOs, the MCP1824/MCP1824S only draws a maximum of 220 µA of quiescent current. The MCP1824 adds a shutdown control input pin and a power good output pin. The two output voltage options are fixed or adjustable. The adjustable option is available on the MCP1824 devices. The adjustable output voltage is set using two external resistors. The allowable resistance value range for resistor R2 is from 10 kΩ to 200 kΩ. Solving Equation 4-1 for R1 yields Equation 4-2.
EQUATION 4-2:
CALCULATING ADJ PIN RESISTOR VALUES
⎠ ⎞ ⎝ ⎛
Where: VOUT VADJ = =
V OUT R 1 = R 2 ------------- – 1 V ADJ
LDO Output Voltage ADJ Pin Voltage (typically 0.41V)
4.1
LDO Output Voltage
4.2
The MCP1824 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for either version. The MCP1824S LDO is available as a fixed voltage device.
Output Current and Current Limiting
4.1.1
ADJUST INPUT
The adjustable version of the MCP1824 uses the ADJ pin to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1824. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, Equation 4-1 represents the equation for setting VOUT.
The MCP1824/MCP1824S LDO is tested and ensured to supply a minimum of 300 mA of output current. The MCP1824/MCP1824S has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1824/MCP1824S also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 720 mA (typical). If the overload condition is a soft overload, the MCP1824/MCP1824S will supply higher load currents of up to 900 mA. The MCP1824/MCP1824S should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 300 mA or less. Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150°C (typical), the LDO will shut down the output voltage. See Section 4.8 “Overtemperature Protection” for more information on overtemperature shutdown.
EQUATION 4-1:
CALCULATING VOUT
⎠ ⎞ ⎝ ⎛
Where: VOUT VADJ = =
R1 + R 2 V OUT = V ADJ -----------------R2
LDO Output Voltage ADJ Pin Voltage (typically 0.41V)
MCP1824-ADJ
VOUT On Off 1 2345
SHDN
R1 ADJ
C2 1 µF
VIN C1 4.7 µF GND R2
FIGURE 4-1: Typical Adjustable Output Voltage Application Circuit.
©
DS22070A-page 18
2007 Microchip Technology Inc.
MCP1824/MCP1824S
4.3 Output Capacitor
The MCP1824/MCP1824S requires a minimum output capacitance of 1 µF for output voltage stability. Ceramic capacitors are recommended because of their size, cost, and environmental robustness qualities. Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 µF X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1824/MCP1824S to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 µF is recommended. Aluminum-electrolytic capacitors are not recommended for low temperature applications of < -25°C. delay is fixed at 110 µs (typical). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 200 µs delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA minimum (VPWRGD < 0.4V maximum).
VPWRGD_TH VOUT TPG
4.4
Input Capacitor
Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 µF to 4.7 µF is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from, in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO.
VOH TVDET_PWRGD
PWRGD VOL
FIGURE 4-2:
Power Good Timing.
VIN
TOR 30 µs 70 µs TPG
4.5
Power Good Output (PWRGD)
SHDN
The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section 1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in the Electrical Characteristics table). The power good time
VOUT
PWRGD
FIGURE 4-3: Shutdown.
Power Good Timing from
2007 Microchip Technology Inc.
DS22070A-page 19
©
MCP1824/MCP1824S
4.6 Shutdown Input (SHDN) 4.7
The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 µs delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After the 30 µs delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100 µs. See Figure 4-4 for a timing diagram of the SHDN input. TOR 400 ns (typ) 30 µs SHDN 70 µs
Dropout Voltage and Undervoltage Lockout
Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.5V differential applied. The MCP1824/ MCP1824S LDO has a very low dropout voltage specification of 210 mV (typical) at 300 mA of output current. See Section 1.0 “Electrical Characteristics” for maximum dropout voltage specifications. The MCP1824/MCP1824S LDO operates across an input voltage range of 2.1V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.00V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 1.82V (typical). Since the MCP1824/MCP1824S LDO undervoltage lockout activates at 1.82V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.8V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.1V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout.
4.8
Overtemperature Protection
VOUT
FIGURE 4-4: Diagram.
Shutdown Input Timing
The MCP1824/MCP1824S LDO has temperaturesensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature.
©
DS22070A-page 20
2007 Microchip Technology Inc.
MCP1824/MCP1824S
5.0
5.1
APPLICATION CIRCUITS/ ISSUES
Typical Application
In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1824/ MCP1824S as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation:
The MCP1824/MCP1824S is used for applications that require high LDO output current and a power good output.
VOUT = 2.5V @ 300 mA
EQUATION 5-2:
P I ( GND ) = VIN ( MAX ) × I VIN Where: PI(GND VIN(MAX) IVIN = = = Power dissipation due to the quiescent current of the LDO Maximum input voltage Current flowing in the VIN pin with no LDO output current (LDO quiescent current)
MCP1824-2.5
On Off 3.3V SHDN VIN C1 4.7 µF GND PWRGD 1 2345 R1 10 kΩ C2 10 µF
FIGURE 5-1: 5.1.1
Typical Application Circuit.
APPLICATION CONDITIONS
Package Type = = = = = = = = = SOT-223-5 3.3V ± 5% 3.465V 3.135V 0.350V 2.5V 300 mA maximum 0.240W 14.88°C
Input Voltage Range VIN maximum VIN minimum VDROPOUT (max) VOUT (typical) IOUT PDISS (typical) Temperature Rise
The total power dissipated within the MCP1824/ MCP1824S is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1824/ MCP1824S is 120 µA. Operating at a maximum VIN of 3.465V results in a power dissipation of 0.12 milli-Watts for a 2.5V output. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1824/MCP1824S is +125°C. To estimate the internal junction temperature of the MCP1824/MCP1824S, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RθJA) of the device. The thermal resistance from junction to ambient for the SOT-223-5 package is estimated at 62° C/W.
5.2
5.2.1
Power Calculations
POWER DISSIPATION
EQUATION 5-3:
T J ( MAX ) = P TOTAL × R θ JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RθJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature
The internal power dissipation within the MCP1824/ MCP1824S is a function of input voltage, output voltage, output current and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO.
EQUATION 5-1:
P LDO = ( VIN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) ) Where: PLDO VIN(MAX) VOUT(MIN) = = = LDO Pass device internal power dissipation Maximum input voltage LDO minimum output voltage
2007 Microchip Technology Inc.
DS22070A-page 21
©
MCP1824/MCP1824S
The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation.
5.3
Typical Application
Internal power dissipation, junction temperature rise, junction temperature, and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected.
EQUATION 5-4:
P D ( MAX ) ( T J ( MAX ) – T A ( MAX ) ) = --------------------------------------------------R θ JA
5.3.1
Package
POWER DISSIPATION EXAMPLE
PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature TA(MAX) = maximum ambient temperature RθJA = Thermal resistance from junction-toambient
Package Type = SOT-223-5 Input Voltage VIN = 3.3V ± 5% LDO Output Voltage and Current VOUT = 2.5V IOUT = 300 mA Maximum Ambient Temperature TA(MAX) = 60°C Internal Power Dissipation PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX) PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) x 300 mA PLDO = 0.308 Watts
EQUATION 5-5:
T J ( RISE ) = P D ( MAX ) × R θ JA TJ(RISE) = Rise in device junction temperature over the ambient temperature PD(MAX) = Maximum device power dissipation RθJA = Thermal resistance from junction-toambient
5.3.1.1
Device Junction Temperature Rise
EQUATION 5-6:
T J = T J ( RISE ) + T A TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature
The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (RθJA) is derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is JESD51. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RθJA TJRISE = 0.308 W x 62° C/W TJRISE = 19.1°C
©
DS22070A-page 22
2007 Microchip Technology Inc.
MCP1824/MCP1824S
5.3.1.2 Junction Temperature Estimate
To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 19.1°C + 60.0°C TJ = 79.1°C
5.3.1.3
Maximum Package Power Dissipation at 60°C Ambient Temperature
SOT-223-5 (62°C/W RθJA): PD(MAX) = (125°C – 60°C) / 62°C/W PD(MAX) = 1.048W SOT-23-5 (256°C/Watt RθJA): PD(MAX) = (125°C – 60°C)/ 256°C/W PD(MAX) = 0.254W From this table, you can see the difference in maximum allowable power dissipation between the SOT-223-5 package and the SOT-23-5 package.
2007 Microchip Technology Inc.
DS22070A-page 23
©
MCP1824/MCP1824S
6.0
6.1
PACKAGING INFORMATION
Package Marking Information
3-Lead SOT-223 (MCP1824S) Part Number XXXXXXX XXXYYWW NNN MCP1824ST-0802E/DB MCP1824ST-1202E/DB MCP1824ST-1802E/DB MCP1824ST-2502E/DB MCP1824ST-3002E/DB MCP1824ST-3302E/DB MCP1824ST-5002E/DB Marking Code 1824S08 1824S12 1824S18 1824S25 1824S30 1824S33 1824S50 1824S08 EDB0710 256 Example:
Legend: XX...X Y YY WW NNN
e3
*
Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package.
Note:
In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.
©
DS22070A-page 24
2007 Microchip Technology Inc.
MCP1824/MCP1824S
Package Marking Information (Continued)
5-Lead SOT-223 (MCP1824) Part Number XXXXXXX XXXYYWW NNN MCP1824T-0802E/DC MCP1824T-1202E/DC MCP1824T-1802E/DC MCP1824T-2502E/DC MCP1824T-3002E/DC MCP1824T-3302E/DC MCP1824T-5002E/DC MCP1824T-ADJE/DC Marking Code 1824082 1824122 1824182 1824252 1824302 1824332 1824502 1824ADJ 1824082 EDC0710 256 Example:
5-Lead SOT-23 Marking Code ULNN UMNN UPNN UQNN URNN USNN UTNN UKNN
Example:
Part Number
XXNN
1
MCP1824T-0802E/OT MCP1824T-1202E/OT MCP1824T-1802E/OT MCP1824T-2502E/OT MCP1824T-3002E/OT MCP1824T-3302E/OT MCP1824T-5002E/OT MCP1824T-ADJE/OT
UL25
1
2007 Microchip Technology Inc.
DS22070A-page 25
©
MCP1824/MCP1824S
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