MCP1826

MCP1826/MCP1826S 1000 mA, Low Voltage, Low Quiescent Current LDO Regulator Features • 1000 mA Output Current Capability • Input Operating Voltage Range: 2.3V to 6.0V • Adjustable Output Voltage Range: 0.8V to 5.0V (MCP1826 only) • Standard Fixed Output Voltages: - 0.8V, 1.2V, 1.8V, 2.5V, 3.0V, 3.3V, 5.0V • Other Fixed Output Voltage Options Available Upon Request • Low Dropout Voltage: 250 mV Typical at 1000 mA • Typical Output Voltage Tolerance: 0.5% • Stable with 1.0 µF Ceramic Output Capacitor • Fast response to Load Transients • Low Supply Current: 120 µA (typ) • Low Shutdown Supply Current: 0.1 µA (typ) (MCP1826 only) • Fixed Delay on Power Good Output (MCP1826 only) • Short Circuit Current Limiting and Overtemperature Protection • TO-263-5 (DDPAK-5), TO-220-5, SOT-223-5 Package Options (MCP1826). • TO-263-3 (DDPAK-3), TO-220-3, SOT-223-3 Package Options (MCP1826S). Description The MCP1826/MCP1826S is a 1000 mA Low Dropout (LDO) linear regulator that provides high current and low output voltages. The MCP1826 comes in a fixed or adjustable output voltage version, with an output voltage range of 0.8V to 5.0V. The 1000 mA output current capability, combined with the low output voltage capability, make the MCP1826 a good choice for new sub-1.8V output voltage LDO applications that have high current demands. The MCP1826S is a 3-pin fixed voltage version. The MCP1826/MCP1826S is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the entire regulator solution. Only 1 µF of output capacitance is needed to stabilize the LDO. Using CMOS construction, the quiescent current consumed by the MCP1826/MCP1826S is typically less than 120 µA over the entire input voltage range, making it attractive for portable computing applications that demand high output current. The MCP1826 versions have a Shutdown (SHDN) pin. When shut down, the quiescent current is reduced to less than 0.1 µA. On the MCP1826 fixed output versions the scaleddown output voltage is internally monitored and a power good (PWRGD) output is provided when the output is within 92% of regulation (typical). The PWRGD delay is internally fixed at 200 µs (typical). The overtemperature and short circuit current-limiting provide additional protection for the LDO during system fault conditions. Applications • • • • • • High-Speed Driver Chipset Power Networking Backplane Cards Notebook Computers Network Interface Cards Palmtop Computers 2.5V to 1.XV Regulators © 2007 Microchip Technology Inc. DS22057A-page 1 MCP1826/MCP1826S Package Types MCP1826 DDPAK-5 TO-220-5 Fixed/Adjustable DDPAK-3 MCP1826S TO-220-3 1 12345 12345 2 3 1 2 3 SOT-223-5 6 SOT-223-3 4 1 2 3 4 5 1 2 3 Pin 1 2 3 4 5 6 Fixed SHDN VIN GND (TAB) VOUT PWRGD GND (TAB) Adjustable SHDN VIN GND (TAB) VOUT ADJ GND (TAB) Pin 1 2 3 4 VIN GND (TAB) VOUT GND (TAB) DS22057A-page 2 © 2007 Microchip Technology Inc. MCP1826/MCP1826S Typical Application MCP1826 Fixed Output Voltage PWRGD On Off VIN = 2.3V to 2.8V C1 4.7 µF SHDN VIN 1 GND VOUT R1 100 kΩ VOUT = 1.8V @ 1000 mA C2 1 µF MCP1826 Adjustable Output Voltage VADJ R2 20 kΩ On Off VIN = 2.3V to 2.8V C1 4.7 µF GND SHDN VIN 1 VOUT R1 40 kΩ VOUT = 1.2V @ 1000 mA C2 1 µF © 2007 Microchip Technology Inc. DS22057A-page 3 MCP1826/MCP1826S Functional Block Diagram - Adjustable Output PMOS VIN VOUT Undervoltage Lock Out (UVLO) ISNS Cf Rf ADJ/SENSE SHDN Overtemperature Sensing Driver w/limit and SHDN SHDN VREF V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference + EA – DS22057A-page 4 © 2007 Microchip Technology Inc. MCP1826/MCP1826S Functional Block Diagram - Fixed Output (3-Pin) PMOS VIN VOUT Undervoltage Lock Out (UVLO) SHDN Sense ISNS Cf Rf Overtemperature Sensing Driver w/limit and SHDN SHDN VREF + EA – V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference © 2007 Microchip Technology Inc. DS22057A-page 5 MCP1826/MCP1826S Functional Block Diagram - Fixed Output (5-Pin) PMOS VIN VOUT Undervoltage Lock Out (UVLO) SHDN Sense ISNS Cf Rf Overtemperature Sensing Driver w/limit and SHDN SHDN VREF + EA – V IN SHDN Soft-Start Comp GND 92% of VREF TDELAY Reference PWRGD DS22057A-page 6 © 2007 Microchip Technology Inc. MCP1826/MCP1826S 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VIN ....................................................................................6.5V Maximum Voltage on Any Pin .. (GND – 0.3V) to (VDD + 0.3)V Maximum Power Dissipation......... Internally-Limited (Note 6) Output Short Circuit Duration ................................ Continuous Storage temperature .....................................-65°C to +150°C Maximum Junction Temperature, TJ ........................... +150°C ESD protection on all pins (HBM/MM) ........... ≥ 4 kV; ≥ 300V AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Input Operating Voltage Input Quiescent Current Input Quiescent Current for SHDN Mode Maximum Output Current Line Regulation Load Regulation Output Short Circuit Current Adjust Pin Reference Voltage Adjust Pin Leakage Current Adjust Temperature Coefficient Voltage Regulation Note 1: 2: 3: 4: 5: 6: Sym VIN Iq ISHDN IOUT ΔVOUT/ (VOUT x ΔVIN) ΔVOUT/VOUT IOUT_SC VADJ IADJ TCVOUT VOUT Min 2.3 — — 1000 — -1.0 — 0.402 -10 — VR - 2.5% 120 0.1 — ±0.05 ±0.5 2.2 0.410 ±0.01 40 Typ Max 6.0 220 3 — ±0.20 1.0 — 0.418 +10 — Units V µA µA mA %/V % A V nA ppm/°C V Note 1 IL = 0 mA, VOUT = 0.8V to 5.0V SHDN = GND VIN = 2.3V to 6.0V VR = 0.8V to 5.0V, Note 1 (Note 1) ≤ VIN ≤ 6V IOUT = 1 mA to 1000 mA, (Note 4) RLOAD < 0.1Ω, Peak Current VIN = 2.3V to VIN = 6.0V, IOUT = 1 mA VIN = 6.0V, VADJ = 0V to 6V Note 3 Note 2 Conditions Adjust Pin Characteristics (Adjustable Output Only) Fixed-Output Characteristics (Fixed Output Only) VR ±0.5% VR + 2.5% The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. 7: © 2007 Microchip Technology Inc. DS22057A-page 7 MCP1826/MCP1826S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Dropout Characteristics Dropout Voltage Power Good Characteristics PWRGD Input Voltage Operating Range VPWRGD_VIN 1.0 1.2 VPWRGD_TH 89 90 PWRGD Threshold Hysteresis PWRGD Output Voltage Low PWRGD Leakage PWRGD Time Delay Detect Threshold to PWRGD Active Time Delay Shutdown Input Logic High Input Logic Low Input SHDN Input Leakage Current AC Performance Output Delay From SHDN Output Noise TOR eN — — 100 2.0 — — µs µV/√Hz SHDN = GND to VIN VOUT = GND to 95% VR IOUT = 200 mA, f = 1 kHz, COUT = 10 µF (X7R Ceramic), VOUT = 2.5V VSHDN-HIGH VSHDN-LOW SHDNILK 45 — -0.1 — — ±0.001 — 15 +0.1 %VIN %VIN µA VIN = 2.3V to 6.0V VIN = 2.3V to 6.0V VIN = 6V, SHDN =VIN, SHDN = GND VPWRGD_HYS VPWRGD_L PWRGD_LK TPG TVDET-PWRGD 1.0 — — — — 92 92 2.0 0.2 1 125 200 95 94 3.0 0.4 — — — %VOUT V nA µs µs IPWRGD SINK = 1.2 mA, ADJ = 0V VPWRGD = VIN = 6.0V Rising Edge RPULLUP = 10 kΩ VOUT = VPWRGD_TH + 20 mV to VPWRGD_TH - 20 mV — — 6.0 6.0 %VOUT V TA = +25°C TA = -40°C to +125°C For VIN < 2.3V, ISINK = 100 µA PWRGD Threshold Voltage (Referenced to VOUT) Falling Edge VOUT < 2.5V Fixed, VOUT = Adj. VOUT >= 2.5V Fixed VDROPOUT — 250 400 mV Note 5, IOUT = 1000 mA, VIN(MIN) = 2.3V Sym Min Typ Max Units Conditions Note 1: 2: 3: 4: 5: 6: 7: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. DS22057A-page 8 © 2007 Microchip Technology Inc. MCP1826/MCP1826S AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise noted, VIN = VOUT(MAX) + VDROPOUT(MAX), Note 1, VR=1.8V for Adjustable Output, IOUT = 1 mA, CIN = COUT = 4.7 µF (X7R Ceramic), TA = +25°C. Boldface type applies for junction temperatures, TJ (Note 7) of -40°C to +125°C Parameters Power Supply Ripple Rejection Ratio Sym PSRR Min — Typ 60 Max — Units dB Conditions f = 100 Hz, COUT = 4.7 µF, IOUT = 100 µA, VINAC = 100 mV pk-pk, CIN = 0 µF IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V IOUT = 100 µA, VOUT = 1.8V, VIN = 2.8V Thermal Shutdown Temperature Thermal Shutdown Hysteresis Note 1: 2: 3: 4: 5: 6: TSD ΔTSD — — 150 10 — — °C °C 7: The minimum VIN must meet two conditions: VIN ≥ 2.3V and VIN ≥ VOUT(MAX) + VDROPOUT(MAX). VR is the nominal regulator output voltage for the fixed cases. VR = 1.2V, 1.8V, etc. VR is the desired set point output voltage for the adjustable cases. VR = VADJ * ((R1/R2)+1). Figure 4-1. TCVOUT = (VOUT-HIGH – VOUT-LOW) *106 / (VR * ΔTemperature). VOUT-HIGH is the highest voltage measured over the temperature range. VOUT-LOW is the lowest voltage measured over the temperature range. Load regulation is measured at a constant junction temperature using low duty-cycle pulse testing. Load regulation is tested over a load range from 1 mA to the maximum specified output current. Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below its nominal value that was measured with an input voltage of VIN = VOUT(MAX) + VDROPOUT(MAX). The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e., TA, TJ, θJA). Exceeding the maximum allowable power dissipation will cause the device operating junction temperature to exceed the maximum +150°C rating. Sustained junction temperatures above 150°C can impact device reliability. The junction temperature is approximated by soaking the device under test at an ambient temperature equal to the desired junction temperature. The test time is small enough such that the rise in the junction temperature over the ambient temperature is not significant. TEMPERATURE SPECIFICATIONS Parameters Temperature Ranges Operating Junction Temperature Range Maximum Junction Temperature Storage Temperature Range Thermal Package Resistances Thermal Resistance, 3L-DDPAK Thermal Resistance, 3L-TO-220 Thermal Resistance, 3L-SOT-223 Thermal Resistance, 5L-DDPAK Thermal Resistance, 5L-TO-220 Thermal Resistance, 5L-SOT-223 θJA θJC θJA θJC θJA θJC θJA θJC θJA θJC θJA θJC — — — — — — — — — — — — 31.4 3.0 29.4 2.0 62 15.0 31.2 3.0 29.3 2.0 62 15.0 — — — — — — — — — — — — °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W 4-Layer JC51 Standard Board 4-Layer JC51 Standard Board EIA/JEDEC JESD51-751-7 4 Layer Board 4-Layer JC51 Standard Board 4-Layer JC51 Standard Board EIA/JEDEC JESD51-751-7 4 Layer Board TJ TJ TA -40 — -65 — — — +125 +150 +150 °C °C °C Steady State Transient Sym Min Typ Max Units Conditions © 2007 Microchip Technology Inc. DS22057A-page 9 MCP1826/MCP1826S 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output. 140 Quiescent Current (μA) 130 120 110 100 90 80 2 3 4 Input Voltage (V) 5 6 130°C 130°C +90°C +90°C +25°C +25°C 0°C -45°C Line Regulation (%/V) VOUT = 1.2V Adj IOUT = 0 mA 0.10 0.09 0.08 0.07 0.06 0.05 0.04 0.03 IOUT = 1 mA VOUT = 1.2V Adj VIN = 2.3V to 6.0V IOUT = 50 mA IOUT = 100 mA IOUT = 250 mA IOUT = 1000 mA -45 -20 5 30 55 80 105 130 Temperature (°C) FIGURE 2-1: Quiescent Current vs. Input Voltage (Adjustable Version). 180 Ground Current (μA) 160 150 140 130 120 110 100 0 250 500 Load Current (mA) 750 1000 VIN = 2.3V VIN = 3.3V VIN = 5.0V FIGURE 2-4: Line Regulation vs. Temperature (Adjustable Version). 0.15 Load Regulation (%) 170 VOUT = 1.2V Adj IOUT = 1.0 mA to 1000 mA VOUT = 3.3V 0.10 0.05 0.00 -0.05 -0.10 -0.15 -45 -20 5 VOUT = 5.0V VOUT = 1.8V VOUT = 0.8V 30 55 80 105 130 Temperature (°C) FIGURE 2-2: Ground Current vs. Load Current (Adjustable Version). 140 135 130 125 120 115 110 105 100 95 90 85 FIGURE 2-5: Load Regulation vs. Temperature (Adjustable Version). 0.411 Adjust Pin Voltage (V) 0.410 0.409 0.408 0.407 0.406 VIN = 2.3V VIN = 6.0V VIN = 5.0V Quiescent Current (μA) VOUT = 1.2V Adj IOUT = 0 mA VOUT = 1.2V IOUT = 1.0 mA VIN = 5.0V VIN = 4.0V VIN = 3.0V VIN = 2.3V VIN = 5.0V -45 -20 5 30 55 80 105 130 -45 -20 5 30 55 80 105 130 Temperature (°C) Temperature (°C) FIGURE 2-3: Quiescent Current vs. Junction Temperature (Adjustable Version). FIGURE 2-6: Adjust Pin Voltage vs. Temperature (Adjustable Version). DS22057A-page 10 © 2007 Microchip Technology Inc. MCP1826/MCP1826S Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output. 0.30 Dropout Voltage (V) 0.25 0.20 0.15 0.10 0.05 0.00 0 200 400 600 800 1000 Load Current (mA) VOUT = 5.0V Adj VOUT = 2.5V Adj 150 Quiescent Current (μA) 140 130 120 110 100 90 2 VOUT = 0.8V IOUT = 0 mA +130°C +90°C +25°C 0°C -45°C 3 4 Input Voltage (V) 5 6 FIGURE 2-7: Dropout Voltage vs. Load Current (Adjustable Version). 0.34 Dropout Voltage (V) 0.31 0.28 0.25 VOUT = 2.5V Adj VOUT = 5.0V Adj FIGURE 2-10: Voltage. 150 Quiescent Current (μA) 140 130 120 110 100 90 80 3 3.5 +130°C +90°C +25°C 0°C -45°C Quiescent Current vs. Input IOUT = 1.0A VOUT = 2.5V IOUT = 0 mA 0.22 0.19 -45 -20 5 30 55 80 105 130 Temperature (°C) 4 4.5 5 5.5 6 Input Voltage (V) FIGURE 2-8: Dropout Voltage vs. Temperature (Adjustable Version). 170.0000 160.0000 150.0000 140.0000 130.0000 120.0000 110.0000 100.0000 -45 -20 5 30 55 80 105 130 Temperature (°C) VIN = 5.0V VIN = 3.9V VIN = 3.1V VIN = 6.0V FIGURE 2-11: Voltage. 200 Ground Current (μA) 180 160 140 120 100 80 60 0 250 Quiescent Current vs. Input Power Good Time Delay (µS) VOUT = 2.5V IOUT= 0 mA VIN = 2.3V for VR=0.8V VIN = 3.9V for VR=3.3V VOUT=3.3V VOUT=0.8V 500 Load Current (mA) 750 1000 FIGURE 2-9: Power Good (PWRGD) Time Delay vs. Temperature. FIGURE 2-12: Current. Ground Current vs. Load © 2007 Microchip Technology Inc. DS22057A-page 11 MCP1826/MCP1826S Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output. 130 Quiescent Current (μA) 125 120 115 110 105 100 95 90 -45 -20 5 30 55 80 105 130 Temperature (°C) VOUT = 0.8V VOUT = 2.5V IOUT = 0 mA 0.040 Line Regulation (%/V) 0.035 0.030 0.025 0.020 IOUT = 1000 mA IOUT = 1 mA VR = 2.5V VIN = 3.1 to 6.0V IOUT = 50 mA IOUT = 250 mA 0.015 -45 -20 5 30 55 Temperature (°C) IOUT = 500 mA 80 105 130 FIGURE 2-13: Temperature. 0.50 0.40 ISHDN (μA) 0.30 0.20 VIN = 5.0V VIN = 6.0V Quiescent Current vs. FIGURE 2-16: Temperature. Line Regulation vs. VR = 0.8V 0.30 Load Regulation (%) 0.20 0.10 0.00 -0.10 -0.20 -0.30 VOUT = 0.8V VIN = 2.3V IOUT = 1 mA to 1000 mA VIN = 4.0V VIN = 3.0V VIN = 2.3V 0.10 0.00 -45 -20 5 30 55 80 105 130 Temperature (°C) -45 -20 5 30 55 80 105 130 Temperature (°C) FIGURE 2-14: ISHDN vs. Temperature. FIGURE 2-17: Load Regulation vs. Temperature (VOUT < 2.5V Fixed). 0.00 -0.05 Load Regulation (%) -0.10 -0.15 -0.20 -0.25 -0.30 -0.35 -0.40 -45 -20 5 30 55 80 105 130 VOUT = 5.0V IOUT = 1 mA to 1000 mA VOUT = 2.5V 0.10 IOUT = 1 mA Line Regulation (%/V) 0.08 IOUT = 50 mA VOUT = 0.8V VIN = 2.3V to 6.0V 0.06 0.04 0.02 0.00 -45 -20 5 30 55 80 IOUT = 1A IOUT = 100 mA IOUT = 500mA 105 130 Temperature (°C) Temperature (°C) FIGURE 2-15: Temperature. Line Regulation vs. FIGURE 2-18: Load Regulation vs. Temperature (VOUT ≥ 2.5V Fixed). DS22057A-page 12 © 2007 Microchip Technology Inc. MCP1826/MCP1826S Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output. 0.30 Dropout Voltage (V) 0.25 0.20 0.15 VOUT = 5.0V VOUT = 2.5V 10.000 VR=0.8V, VIN=2.3V COUT=1 μF ceramic X7R CIN=10 μF ceramic IOUT=200 mA Noise (mV/ √Hz) 1.000 VR=3.3V, VIN=4.1V 0.10 0.05 0.00 0 200 400 600 800 1000 Load Current (mA) 0.100 0.010 0.01 0.1 1 10 Frequency (kHz) 100 1000 FIGURE 2-19: Current. 0.34 Dropout Voltage (V) 0.32 0.30 0.28 0.26 0.24 0.22 0.20 -45 -20 5 Dropout Voltage vs. Load FIGURE 2-22: Output Noise Voltage Density vs. Frequency. IOUT = 1000 mA VOUT = 2.5V 0 -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 VR=1.2V Adj COUT=10 μF ceramic X7R VIN=3.1V CIN=0 μF IOUT=10 mA VOUT = 5.0V 30 55 80 105 130 0.1 Temperature (°C) 1 10 Frequency (kHz) 100 1000 FIGURE 2-20: Temperature. Dropout Voltage vs. FIGURE 2-23: Power Supply Ripple Rejection (PSRR) vs. Frequency (Adjustable). 2.00 1.80 1.60 1.40 1.20 1.00 0.80 0.60 0.40 0.20 0.00 0 1 2 3 4 0 VOUT = 0.8V Short Circuit Current (A) -10 -20 PSRR (dB) -30 -40 -50 -60 -70 -80 0.01 VR=3.3V Fixed COUT=22 μF ceramic X7R VIN=3.9V CIN=0 μF IOUT=10 mA 5 6 0.1 Input Voltage (V) 1 10 Frequency (kHz) 100 1000 FIGURE 2-21: Input Voltage. Short Circuit Current vs. FIGURE 2-24: Power Supply Ripple Rejection (PSRR) vs. Frequency. © 2007 Microchip Technology Inc. DS22057A-page 13 MCP1826/MCP1826S .Note: Unless otherwise indicated, COUT = 4.7 µF Ceramic (X7R), CIN = 4.7 µF Ceramic (X7R), IOUT = 1 mA, Temperature = +25°C, VIN = VOUT + 0.6V, Fixed output. FIGURE 2-25: 2.5V (Adj.) Startup from VIN. FIGURE 2-28: Dynamic Line Response. FIGURE 2-26: Shutdown. 2.5V (Adj.) Startup from FIGURE 2-29: Dynamic Load Response (10 mA to 1000 mA). FIGURE 2-27: Timing. Power Good (PWRGD) FIGURE 2-30: Dynamic Load Response (100 mA to 1000 mA). DS22057A-page 14 © 2007 Microchip Technology Inc. MCP1826/MCP1826S 3.0 PIN DESCRIPTION PIN FUNCTION TABLE 5-Pin Fixed Output 1 2 3 4 5 — The descriptions of the pins are listed in Table 3-1. TABLE 3-1: 3-Pin Fixed Output — Adjustable Output 1 2 3 4 — Name SHDN VIN GND VOUT PWRGD ADJ EP Description Shutdown Control Input (active-low) Input Voltage Supply Ground Regulated Output Voltage Power Good Output Voltage Adjust/Sense Input Exposed Pad of the Package (ground potential) 1 2 3 — — 5 Exposed Pad Exposed Pad Exposed Pad 3.1 Shutdown Control Input (SHDN) 3.5 Power Good Output (PWRGD) The SHDN input is used to turn the LDO output voltage on and off. When the SHDN input is at a logic-high level, the LDO output voltage is enabled. When the SHDN input is pulled to a logic-low level, the LDO output voltage is disabled. When the SHDN input is pulled low, the PWRGD output also goes low and the LDO enters a low quiescent current shutdown state where the typical quiescent current is 0.1 µA. The PWRGD output is an open-drain output used to indicate when the LDO output voltage is within 92% (typically) of its nominal regulation value. The PWRGD threshold has a typical hysteresis value of 2%. The PWRGD output is delayed by 200 µs (typical) from the time the LDO output is within 92% + 3% (max hysteresis) of the regulated output value on power-up. This delay time is internally fixed. 3.2 Input Voltage Supply (VIN) 3.6 Output Voltage Adjust Input (ADJ) Connect the unregulated or regulated input voltage source to VIN. If the input voltage source is located several inches away from the LDO, or the input source is a battery, it is recommended that an input capacitor be used. A typical input capacitance value of 1 µF to 10 µF should be sufficient for most applications. For adjustable applications, the output voltage is connected to the ADJ input through a resistor divider that sets the output voltage regulation value. This provides the user the capability to set the output voltage to any value they desire within the 0.8V to 5.0V range of the device. 3.3 Ground (GND) 3.7 Exposed Pad (EP) Connect the GND pin of the LDO to a quiet circuit ground. This will help the LDO power supply rejection ratio and noise performance. The ground pin of the LDO only conducts the quiescent current of the LDO (typically 120 µA), so a heavy trace is not required. For applications have switching or noisy inputs tie the GND pin to the return of the output capacitor. Ground planes help lower inductance and voltage spikes caused by fast transient load currents and are recommended for applications that are subjected to fast load transients. The DDPAK and TO-220 package have an exposed tab on the package. A heat sink may may be mount to the tab to aid in the removal of heat from the package during operation. The exposed tab is at the ground potential of the LDO. 3.4 Regulated Output Voltage (VOUT) The VOUT pin is the regulated output voltage of the LDO. A minimum output capacitance of 1.0 µF is required for LDO stability. The MCP1826/MCP1826S is stable with ceramic, tantalum and aluminum-electrolytic capacitors. See Section 4.3 “Output Capacitor” for output capacitor selection guidance. © 2007 Microchip Technology Inc. DS22057A-page 15 MCP1826/MCP1826S 4.0 DEVICE OVERVIEW EQUATION 4-2: V OUT – V ADJ R 1 = R 2 ⎛ --------------------------------⎞ ⎝ ⎠ V ADJ = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V) The MCP1826/MCP1826S is a high output current, Low Dropout (LDO) voltage regulator. The low dropout voltage of 300 mV typical at 1000 mA of current makes it ideal for battery-powered applications. Unlike other high output current LDOs, the MCP1826/MCP1826S only draws a maximum of 220 µA of quiescent current. The MCP1826 has a shutdown control input and a power good output. Where: VOUT VADJ 4.1 LDO Output Voltage 4.2 Output Current and Current Limiting The 5-pin MCP1826 LDO is available with either a fixed output voltage or an adjustable output voltage. The output voltage range is 0.8V to 5.0V for both versions. The 3-pin MCP1826S LDO is available as a fixed voltage device. 4.1.1 ADJUST INPUT The MCP1826/MCP1826S LDO is tested and ensured to supply a minimum of 1000 mA of output current. The MCP1826/MCP1826S has no minimum output load, so the output load current can go to 0 mA and the LDO will continue to regulate the output voltage to within tolerance. The MCP1826/MCP1826S also incorporates an output current limit. If the output voltage falls below 0.7V due to an overload condition (usually represents a shorted load condition), the output current is limited to 2.2A (typical). If the overload condition is a soft overload, the MCP1826/MCP1826S will supply higher load currents of up to 2.5A. The MCP1826/MCP1826S should not be operated in this condition continuously as it may result in failure of the device. However, this does allow for device usage in applications that have higher pulsed load currents having an average output current value of 1000 mA or less. Output overload conditions may also result in an overtemperature shutdown of the device. If the junction temperature rises above 150°C, the LDO will shut down the output voltage. See Section 4.8 “Overtemperature Protection” for more information on overtemperature shutdown. The adjustable version of the MCP1826 uses the ADJ pin (pin 5) to get the output voltage feedback for output voltage regulation. This allows the user to set the output voltage of the device with two external resistors. The nominal voltage for ADJ is 0.41V. Figure 4-1 shows the adjustable version of the MCP1826. Resistors R1 and R2 form the resistor divider network necessary to set the output voltage. With this configuration, the equation for setting VOUT is: EQUATION 4-1: R1 + R2 V OUT = V ADJ ⎛ ------------------⎞ ⎝ R2 ⎠ = = LDO Output Voltage ADJ Pin Voltage (typically 0.41V) Where: VOUT VADJ 4.3 MCP1826-ADJ VOUT On Off SHDN Output Capacitor 1 2345 R1 ADJ The MCP1826/MCP1826S requires a minimum output capacitance of 1 µF for output voltage stability. Ceramic capacitors are recommended because of their size, cost and environmental robustness qualities. C2 1 µF VIN C1 4.7 µF GND R2 FIGURE 4-1: Typical adjustable output voltage application circuit. The allowable resistance value range for resistor R2 is from 10 kΩ to 200 kΩ. Solving the equation for R1 yields the following equation: Aluminum-electrolytic and tantalum capacitors can be used on the LDO output as well. The Equivalent Series Resistance (ESR) of the electrolytic output capacitor must be no greater than 1 ohm. The output capacitor should be located as close to the LDO output as is practical. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. A typical 1 µF X7R 0805 capacitor has an ESR of 50 milli-ohms. Larger LDO output capacitors can be used with the MCP1826/MCP1826S to improve dynamic performance and power supply ripple rejection performance. A maximum of 22 µF is recommended. Aluminum-electrolytic capacitors are not recommended for low-temperature applications of ≤ 25°C. DS22057A-page 16 © 2007 Microchip Technology Inc. MCP1826/MCP1826S 4.4 Input Capacitor VPWRGD_TH VOUT TPG Low input source impedance is necessary for the LDO output to operate properly. When operating from batteries, or in applications with long lead length (> 10 inches) between the input source and the LDO, some input capacitance is recommended. A minimum of 1.0 µF to 4.7 µF is recommended for most applications. For applications that have output step load requirements, the input capacitance of the LDO is very important. The input capacitance provides the LDO with a good local low-impedance source to pull the transient currents from in order to respond quickly to the output load step. For good step response performance, the input capacitor should be of equivalent (or higher) value than the output capacitor. The capacitor should be placed as close to the input of the LDO, as is practical. Larger input capacitors will also help reduce any high-frequency noise on the input and output of the LDO and reduce the effects of any inductance that exists between the input source voltage and the input capacitance of the LDO. VOH TVDET_PWRGD PWRGD VOL FIGURE 4-2: Power Good Timing. VIN TOR 70 µs 30 µs 4.5 Power Good Output (PWRGD) SHDN The PWRGD output is used to indicate when the output voltage of the LDO is within 92% (typical value, see Section 1.0 “Electrical Characteristics” for Minimum and Maximum specifications) of its nominal regulation value. As the output voltage of the LDO rises, the PWRGD output will be held low until the output voltage has exceeded the power good threshold plus the hysteresis value. Once this threshold has been exceeded, the power good time delay is started (shown as TPG in the Electrical Characteristics table). The power good time delay is fixed at 200 µs (typical). After the time delay period, the PWRGD output will go high, indicating that the output voltage is stable and within regulation limits. If the output voltage of the LDO falls below the power good threshold, the power good output will transition low. The power good circuitry has a 170 µs delay when detecting a falling output voltage, which helps to increase noise immunity of the power good output and avoid false triggering of the power good output during fast output transients. See Figure 4-2 for power good timing characteristics. When the LDO is put into Shutdown mode using the SHDN input, the power good output is pulled low immediately, indicating that the output voltage will be out of regulation. The timing diagram for the power good output when using the shutdown input is shown in Figure 4-3. The power good output is an open-drain output that can be pulled up to any voltage that is equal to or less than the LDO input voltage. This output is capable of sinking 1.2 mA (VPWRGD < 0.4V maximum). TPG VOUT PWRGD FIGURE 4-3: Shutdown. Power Good Timing from 4.6 Shutdown Input (SHDN) The SHDN input is an active-low input signal that turns the LDO on and off. The SHDN threshold is a percentage of the input voltage. The typical value of this shutdown threshold is 30% of VIN, with minimum and maximum limits over the entire operating temperature range of 45% and 15%, respectively. The SHDN input will ignore low-going pulses (pulses meant to shut down the LDO) that are up to 400 ns in pulse width. If the shutdown input is pulled low for more than 400 ns, the LDO will enter Shutdown mode. This small bit of filtering helps to reject any system noise spikes on the shutdown input signal. On the rising edge of the SHDN input, the shutdown circuitry has a 30 µs delay before allowing the LDO output to turn on. This delay helps to reject any false turn-on signals or noise on the SHDN input signal. After © 2007 Microchip Technology Inc. DS22057A-page 17 MCP1826/MCP1826S the 30 µs delay, the LDO output enters its soft-start period as it rises from 0V to its final regulation value. If the SHDN input signal is pulled low during the 30 µs delay period, the timer will be reset and the delay time will start over again on the next rising edge of the SHDN input. The total time from the SHDN input going high (turn-on) to the LDO output being in regulation is typically 100 µs. See Figure 4-4 for a timing diagram of the SHDN input. TOR 400 ns (typ) 30 µs SHDN 70 µs 4.7 Dropout Voltage and Undervoltage Lockout Dropout voltage is defined as the input-to-output voltage differential at which the output voltage drops 2% below the nominal value that was measured with a VR + 0.5V differential applied. The MCP1826/ MCP1826S LDO has a very low dropout voltage specification of 300 mV (typical) at 1000 mA of output current. See Section 1.0 “Electrical Characteristics” for maximum dropout voltage specifications. The MCP1826/MCP1826S LDO operates across an input voltage range of 2.3V to 6.0V and incorporates input Undervoltage Lockout (UVLO) circuitry that keeps the LDO output voltage off until the input voltage reaches a minimum of 2.00V (typical) on the rising edge of the input voltage. As the input voltage falls, the LDO output will remain on until the input voltage level reaches 1.82V (typical). Since the MCP1826/MCP1826S LDO undervoltage lockout activates at 1.82V as the input voltage is falling, the dropout voltage specification does not apply for output voltages that are less than 1.8V. For high-current applications, voltage drops across the PCB traces must be taken into account. The trace resistances can cause significant voltage drops between the input voltage source and the LDO. For applications with input voltages near 2.3V, these PCB trace voltage drops can sometimes lower the input voltage enough to trigger a shutdown due to undervoltage lockout. VOUT FIGURE 4-4: Diagram. Shutdown Input Timing 4.8 Overtemperature Protection The MCP1826/MCP1826S LDO has temperaturesensing circuitry to prevent the junction temperature from exceeding approximately 150°C. If the LDO junction temperature does reach 150°C, the LDO output will be turned off until the junction temperature cools to approximately 140°C, at which point the LDO output will automatically resume normal operation. If the internal power dissipation continues to be excessive, the device will again shut off. The junction temperature of the die is a function of power dissipation, ambient temperature and package thermal resistance. See Section 5.0 “Application Circuits/ Issues” for more information on LDO power dissipation and junction temperature. DS22057A-page 18 © 2007 Microchip Technology Inc. MCP1826/MCP1826S 5.0 5.1 APPLICATION CIRCUITS/ ISSUES Typical Application In addition to the LDO pass element power dissipation, there is power dissipation within the MCP1826/ MCP1826S as a result of quiescent or ground current. The power dissipation as a result of the ground current can be calculated using the following equation: The MCP1826/MCP1826S is used for applications that require high LDO output current and a power good output. VOUT = 2.5V @ 1000 mA MCP1826-2.5 On Off 3.3V SHDN VIN C1 4.7 µF GND 1 2345 R1 10 kΩ C2 10 µF EQUATION 5-2: P I ( GND ) = V IN ( MAX ) × I VIN Where: PI(GND VIN(MAX) IVIN = = = Power dissipation due to the quiescent current of the LDO Maximum input voltage Current flowing in the VIN pin with no LDO output current (LDO quiescent current) PWRGD FIGURE 5-1: 5.1.1 Typical Application Circuit. APPLICATION CONDITIONS Package Type = TO-220-5 Input Voltage Range = 3.3V ± 5% VIN maximum = 3.465V VIN minimum = 3.135V VDROPOUT (max) = 0.350V VOUT (typical) = 2.5V IOUT = 1000 mA maximum PDISS (typical) = 0.965W Temperature Rise = 28.27°C The total power dissipated within the MCP1826/ MCP1826S is the sum of the power dissipated in the LDO pass device and the P(IGND) term. Because of the CMOS construction, the typical IGND for the MCP1826/ MCP1826S is 120 µA. Operating at a maximum VIN of 3.465V results in a power dissipation of 0.12 milli-Watts for a 2.5V output. For most applications, this is small compared to the LDO pass device power dissipation and can be neglected. The maximum continuous operating junction temperature specified for the MCP1826/MCP1826S is +125°C. To estimate the internal junction temperature of the MCP1826/MCP1826S, the total internal power dissipation is multiplied by the thermal resistance from junction to ambient (RθJA) of the device. The thermal resistance from junction to ambient for the TO-220-5 package is estimated at 29.3°C/W. 5.2 5.2.1 Power Calculations POWER DISSIPATION EQUATION 5-3: T J ( MAX ) = P TOTAL × R θ JA + T AMAX TJ(MAX) = Maximum continuous junction temperature PTOTAL = Total device power dissipation RθJA = Thermal resistance from junction to ambient TAMAX = Maximum ambient temperature The internal power dissipation within the MCP1826/ MCP1826S is a function of input voltage, output voltage, output current and quiescent current. Equation 5-1 can be used to calculate the internal power dissipation for the LDO. EQUATION 5-1: P LDO = ( V IN ( MAX ) ) – V OUT ( MIN ) ) × I OUT ( MAX ) ) Where: PLDO VIN(MAX) VOUT(MIN) = = = LDO Pass device internal power dissipation Maximum input voltage LDO minimum output voltage © 2007 Microchip Technology Inc. DS22057A-page 19 MCP1826/MCP1826S The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. Equation 5-4 can be used to determine the package maximum internal power dissipation. 5.3 Typical Application Internal power dissipation, junction temperature rise, junction temperature and maximum power dissipation is calculated in the following example. The power dissipation as a result of ground current is small enough to be neglected. EQUATION 5-4: P D ( MAX ) ( T J ( MAX ) – T A ( MAX ) ) = --------------------------------------------------R θ JA 5.3.1 Package POWER DISSIPATION EXAMPLE PD(MAX) = Maximum device power dissipation TJ(MAX) = maximum continuous junction temperature TA(MAX) = maximum ambient temperature RθJA = Thermal resistance from junction-toambient Package Type = TO-220-5 Input Voltage VIN = 3.3V ± 5% LDO Output Voltage and Current VOUT = 2.5V IOUT = 1000 mA Maximum Ambient Temperature TA(MAX) = 60°C Internal Power Dissipation PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX) PLDO = ((3.3V x 1.05) – (2.5V x 0.975)) x 1000 mA PLDO = 1.028 Watts EQUATION 5-5: T J ( RISE ) = P D ( MAX ) × R θ JA TJ(RISE) = Rise in device junction temperature over the ambient temperature PD(MAX) = Maximum device power dissipation RθJA = Thermal resistance from junction-toambient 5.3.1.1 Device Junction Temperature Rise EQUATION 5-6: T J = T J ( RISE ) + T A TJ = Junction temperature TJ(RISE) = Rise in device junction temperature over the ambient temperature TA = Ambient temperature The internal junction temperature rise is a function of internal power dissipation and the thermal resistance from junction-to-ambient for the application. The thermal resistance from junction-to-ambient (RθJA) is derived from EIA/JEDEC standards for measuring thermal resistance. The EIA/JEDEC specification is JESD51. The standard describes the test method and board specifications for measuring the thermal resistance from junction to ambient. The actual thermal resistance for a particular application can vary depending on many factors such as copper area and thickness. Refer to AN792, “A Method to Determine How Much Power a SOT23 Can Dissipate in an Application” (DS00792), for more information regarding this subject. TJ(RISE) = PTOTAL x RθJA TJRISE = 1.028 W x 29.3°C/W TJRISE = 30.12°C DS22057A-page 20 © 2007 Microchip Technology Inc. MCP1826/MCP1826S 5.3.1.2 Junction Temperature Estimate To estimate the internal junction temperature, the calculated temperature rise is added to the ambient or offset temperature. For this example, the worst-case junction temperature is estimated below: TJ = TJRISE + TA(MAX) TJ = 30.12°C + 60.0°C TJ = 90.12°C 5.3.1.3 Maximum Package Power Dissipation at 60°C Ambient Temperature TO-220-5 (29.3° C/W RθJA): PD(MAX) = (125°C – 60°C) / 29.3°C/W PD(MAX) = 2.218W DDPAK-5 (31.2°C/Watt RθJA): PD(MAX) = (125°C – 60°C)/ 31.2°C/W PD(MAX) = 2.083W From this table, you can see the difference in maximum allowable power dissipation between the TO-220-5 package and the DDPAK-5 package. © 2007 Microchip Technology Inc. DS22057A-page 21 MCP1826/MCP1826S 6.0 6.1 PACKAGING INFORMATION Package Marking Information 3-Lead DDPAK (MCP1826S) Example: XXXXXXXXX XXXXXXXXX YYWWNNN 1 2 3 MCP1826S e3 0.8EEB^^ 0730256 1 2 3 3-Lead SOT-223 (MCP1826S) Example: XXXXXXX XXXYYWW NNN 1826S08 EDB0730 256 3-Lead TO-220 (MCP1826S) Example: XXXXXXXXX XXXXXXXXX YYWWNNN MCP1826S 12EAB^^ e3 0730256 1 2 3 1 2 3 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS22057A-page 22 © 2007 Microchip Technology Inc. MCP1826/MCP1826S Package Marking Information (Continued) 5-Lead DDPAK (MCP1826) Example: XXXXXXXXX XXXXXXXXX YYWWNNN MCP1826 e 1.0EET^^3 0730256 12345 12345 5-Lead SOT-223 (MCP1826) Example: XXXXXXX XXXYYWW NNN 1826-08 EDC0730 256 5-Lead TO-220 (MCP1826) Example: XXXXXXXXX XXXXXXXXX YYWWNNN MCP1826 e3 08EAT^^ 0730256 12345 12345 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2007 Microchip Technology Inc. DS22057A-page 23 MCP1826/MCP1826S DS22057A-page 24 © 2007 Microchip Technology Inc. MCP1826/MCP1826S © 2007 Microchip Technology Inc. DS22057A-page 25 MCP1826/MCP1826S DS22057A-page 26 © 2007 Microchip Technology Inc. MCP1826/MCP1826S © 2007 Microchip Technology Inc. DS22057A-page 27 MCP1826/MCP1826S DS22057A-page 28 © 2007 Microchip Technology Inc. MCP1826/MCP1826S © 2007 Microchip Technology Inc. DS22057A-page 29 MCP1826/MCP1826S NOTES: DS22057A-page 30 © 2007 Microchip Technology Inc. MCP1826/MCP1826S APPENDIX A: REVISION HISTORY Revision A (August 2007) • Original Release of this Document. © 2007 Microchip Technology Inc. DS22057A-page 31 MCP1826/MCP1826S NOTES: DS22057A-page 32 © 2007 Microchip Technology Inc. MCP1826/MCP1826S PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XX X X X/ XX Examples: a) b) c) d) e) f) g) h) i) a) b) c) d) e) f) g) h) MCP1826-0802E/XX: MCP1826-1002E/XX: MCP1826-1202E/XX: MCP1826-1802E/XX MCP1826-2502EXX: MCP1826-3002E/XX: MCP1826-3302E/XX MCP1826-5002E/XX: MCP1826-ADJE/XX: 0.8V LDO Regulator 1.0V LDO Regulator 1.2V LDO Regulator 1.8V LDO Regulator 25V LDO Regulator 3.0V LDO Regulator 3.3V LDO Regulator 5.0V LDO Regulator ADJ LDO Regulator Output Feature Tolerance Temp. Package Voltage Code Device: MCP1826: 1000 mA Low Dropout Regulator MCP1826T: 1000 mA Low Dropout Regulator Tape and Reel MCP1826S: 1000 mA Low Dropout Regulator MCP1826ST: 1000 mA Low Dropout Regulator Tape and Reel 08 12 18 25 30 33 50 ADJ = = = = = = = = 0.8V “Standard” 1.2V “Standard” 1.8V “Standard” 2.5V “Standard” 3.0V “Standard” 3.3V “Standard” 5.0V “Standard” Adjustable Output Voltage ** (MCP1826 only) Output Voltage *: *Contact factory for other output voltage options ** When ADJ is used, the “extra feature code” and “tolerance” columns do not apply. Refer to examples. Extra Feature Code: Tolerance: Temperature: Package Type: 0 2 E AB AT DB DC EB ET = Fixed = 2.0% (Standard) = -40°C to +125°C = = = = = = Plastic Transistor Outline, TO-220, 3-lead Plastic Transistor Outline, TO-220, 5-lead Plastic Transistor Outline, SOT-223, 3-lead Plastic Transistor Outline, SOT-223, 5-lead Plastic, DDPAK, 3-lead Plastic, DDPAK, 5-lead MCP1826S-0802E/XX:0.8V LDO Regulator MCP1826S-1002E/XX:1.0V LDO Regulator MCP1826S-1202E/XX 1.2V LDO Regulator MCP1826S-1802E/XX 1.8V LDO Regulator MCP1826S-2502E/XX 2.5V LDO Regulator MCP1826S-2502E/XX 3.0V LDO Regulator MCP1826S-3302E/XX 3.3V LDO Regulator MCP1826S-5002E/XX 5.0V LDO Regulator XX = = = = = = AB for 3LD TO-220 package AT for 5LD TO-220 package DB for 3LD SOT-223 package DC for 5LD SOT-223 package EB for 3LD DDPAK package ET for 5LD DDPAK package Note: ADJ (Adjustable) only available in 5-lead version. © 2007 Microchip Technology Inc. DS22057A-page 33 MCP1826/MCP1826S NOTES: DS22057A-page 34 © 2007 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2007 Microchip Technology Inc. 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