MCP2140T-ISS

M Features • Implements the IrDA standard, including: - IrLAP - IrLMP - IAS - TinyTP - IrCOMM (9-wire “cooked” service class) • Provides IrDA standard physical signal layer support including: - Bidirectional communication - CRC implementation - Fixed Data communication rate of 9600 baud • Includes UART-to-IrDA standard encoder/ decoder functionality: - Easily interfaces with industry standard UARTs and infrared transceivers • UART interface for connecting to Data Communications Equipment (DCE) or Data Terminal Equipment (DTE) systems • Transmit/Receive formats (bit width) supported: - 1.63 µs • Hardware UART Support: - 9.6 kbaud baud rate - 29 Byte Data Buffer Size • Infrared Supported: - 9.6 kbaud baud rate - 64 Byte Data Packet Size • Operates as Secondary Device • Automatic Low Power mode - < 60 µA when no IR activity present (PHACT = L) ® MCP2140 Package Types PDIP, SOIC RXPDREF TXIR PHACT RESET VSS NC TX RX RI 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 RXPD CD OSC1/CLKI OSC2 VDD RTS CTS DTR DSR IrDA® Standard Protocol Stack Controller With Fixed 9600 Baud Communication Rate MCP2140 SSOP RXPDREF TXIR PHACT RESET VSS VSS NC TX RX RI 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 RXPD CD OSC1/CLKI OSC2 VDD VDD RTS CTS DTR DSR MCP2140 Block Diagram MCP2140 TX Encode and Protocol Handler Logic PHACT Baud Rate Generator Protocol Handler and Decode + RXPD RXPDREF OSC1 OSC2 TXIR CMOS Technology • • • • • Low power, high-speed CMOS technology Fully static design Low voltage operation Industrial temperature range Low power consumption - < 1 mA @ 3.0V, 7.3728 MHz (typical) RX RTS CTS DSR DTR CD RI UART Control  2003 Microchip Technology Inc. Preliminary DS21790A-page 1 MCP2140 MCP2140 System Block Diagram PICmicro® Microcontroller SO UART TX MCP2140 Decode Baud Rate Generator RX RTS CTS DSR DTR CD RI PHACT + IR Receive Detect RXPDREF Circuitry RXPD IR Photo diode TXIR IR LED SI I/O I/O I/O I/O I/O I/O UART Flow Control (1) Encode UART Control MCP2140 Status (1) I/O Logic Note 1: Not all microcontroller I/O pins are required to be connected to the MCP2140. DS21790A-page 2 Preliminary  2003 Microchip Technology Inc. MCP2140 1.0 DEVICE OVERVIEW 1.1 Applications The MCP2140 is a cost-effective, low pin count (18-pin), easy-to-use device for implementing IrDA standard wireless connectivity. The MCP2140 provides support for the IrDA standard protocol “stack”, bit encoding/ decoding and low cost, discrete IR receiver circuitry. The serial and IR interface baud rates are fixed at 9600 baud. The serial interface and IR interface baud rates are dependent on the device frequency, but IrDA standard operation requires a device frequency of 7.3728 MHz. The MCP2140 will specify to the Primary Device the IR baud rate during the Discover phase. The MCP2140 can operate in Data Communication Equipment (DCE) and Data Terminal Equipment (DTE) applications, and sits between a UART and an infrared optical transceiver. The MCP2140 encodes an asynchronous serial data stream, converting each data bit to the corresponding infrared (IR) formatted pulse. IR pulses received are decoded and then handled by the protocol handler state machine. The protocol handler sends the appropriate data bytes to the Host Controller in UARTformatted serial data. The MCP2140 supports “point-to-point” applications, that is, one Primary device and one Secondary device. The MCP2140 operates as a Secondary device and does not support “multi-point” applications. Sending data using IR light requires some hardware and the use of specialized communication protocols. These protocol and hardware requirements are described, in detail, by the IrDA standard specifications. The encoding/decoding functionality of the MCP2140 is designed to be compatible with the physical layer component of the IrDA standard. This part of the standard is often referred to as “IrPHY”. The complete IrDA standard specification is available for download from the IrDA website at www.IrDA.org. The MCP2140 Infrared Communications Controller, supporting the IrDA standard, provides embedded system designers the easiest way to implement IrDA standard wireless connectivity. Figure 1-1 shows a typical application block diagram, while Table 1-2 shows the pin definitions. TABLE 1-1: OVERVIEW OF FEATURES MCP2140 UART, IR Fixed Yes RESET, POR (PWRT and OST) 18-pin DIP, SOIC, 20-pin SSOP Features Serial Communications Baud Rate Selection Low Power Mode Resets (and Delays) Packages Infrared communication is a wireless, two-way data connection using infrared light generated by low-cost transceiver signaling technology. This provides reliable communication between two devices. Infrared technology offers: • Universal standard for connecting portable computing devices • Easy, effortless implementation • Economical alternative to other connectivity solutions • Reliable, high-speed connections • Safe to use in any environment (can even be used during air travel) • Eliminates the hassle of cables • Allows PCs and other electronic devices (such as PDAs, cell phones, etc.) to communicate with each other • Enhances mobility by allowing users to easily connect The MCP2140 allows the easy addition of IrDA standard wireless connectivity to any embedded application that uses serial data. Figure 1-1 shows typical implementation of the MCP2140 in an embedded system. The IrDA protocol for printer support is not included in the IrCOMM 9-wire “cooked” service class.  2003 Microchip Technology Inc. Preliminary DS21790A-page 3 MCP2140 FIGURE 1-1: SYSTEM BLOCK DIAGRAM MCP2140 TX Decode Baud Rate Generator RX RTS CTS DSR DTR CD RI PHACT + IR Receive Detect RXPDREF Circuitry RXPD IR Photo diode TXIR IR LED PICmicro® Microcontroller SO UART SI I/O I/O I/O I/O I/O I/O UART Flow Control (1) Encode UART Control MCP2140 Status (1) I/O Logic Note 1: Not all microcontroller I/O pins are required to be connected to the MCP2140. DS21790A-page 4 Preliminary  2003 Microchip Technology Inc. MCP2140 TABLE 1-2: Pin Name RXPDREF TXIR PHACT MCP2140 PIN DESCRIPTION NORMAL OPERATION (DCE) Pin Number PDIP 1 2 3 SOIC 1 2 3 SSOP 1 2 3 Pin Type I O OC Buffer Type A — — Description IR Receive Photo Detect Diode reference voltage. This voltage will typically be in the range of VDD/2. Asynchronous transmit to IrDA transceiver. Protocol Handler Active. Indicates the state of the MCP2140 Protocol Handler. This output is an open collector, so an external pull-up resistor may be required. 1 = Protocol Handler is in the Discovery or NRM state 0 = Protocol Handler is in NDM state or the MCP2140 is in Low Power mode Resets the Device Ground reference for logic and I/O pins No connect Asynchronous receive; from Host Controller UART Asynchronous transmit; to Host Controller UART Ring Indicator. The state of this bit is communicated to the IrDA Primary Device. 1 = No Ring Indicate Present 0 = Ring Indicate Present Data Set Ready. Indicates that the MCP2140 has established a valid IrDA link with a Primary Device(1). This signal is locally emulated and not related to the DTR bit of the IrDA Primary Device. 1 = An IR link has not been established (No IR Link) 0 = An IR link has been established (IR Link) Data Terminal Ready. Indicates that the Embedded device connected to the MCP2140 is ready for IR data. The state of this bit is communicated to the IrDA Primary Device via the IrDA DSR bit carried by IrCOMM. 1 = Embedded device not ready 0 = Embedded device ready Clear to Send. Indicates that the MCP2140 is ready to receive data from the Host Controller. This signal is locally emulated and not related to the CTS/RTS bit of the IrDA Primary Device. 1 = Host Controller should not send data 0 = Host Controller may send data RESET VSS NC TX RX RI 4 5 6 7 8 9 4 5 6 7 8 9 4 5, 6 7 8 9 10 I — I I O I ST P — TTL — TTL DSR 10 10 11 O — DTR 11 11 12 I TTL CTS 12 12 13 O — Legend: TTL = TTL compatible input A = Analog CMOS = CMOS compatible input I = Input ST = Schmitt Trigger input with CMOS levels P = Power OC = Open collector output O = Output 1: The state of the DTR output pin does not reflect the state of the DTR bit of the IrDA Primary Device.  2003 Microchip Technology Inc. Preliminary DS21790A-page 5 MCP2140 TABLE 1-2: Pin Name RTS MCP2140 PIN DESCRIPTION NORMAL OPERATION (DCE) (CONTINUED) Pin Number PDIP 13 SOIC 13 SSOP 14 Pin Type I Buffer Type TTL Description Request to Send. Indicates that a Host Controller is ready to receive data from the MCP2140. This signal is locally emulated and not related to the CTS/RTS bit of the IrDA Primary device. 1 = Host Controller not ready to receive data 0 = Host Controller ready to receive data Positive supply for logic and I/O pins. Oscillator crystal output. Carrier Detect. The state of this bit is communicated to the IrDA Primary device via the IrDA CD bit. 1 = No Carrier Present 0 = Carrier Present IR RX Photo Detect Diode input. This input signal is required to be a pulse to indicate an IR bit. When the amplitude of the signal crosses the amplitude threshold set by the RXPDREF pin, the IR bit is detected. The pulse has minimum and maximum requirements as specified in Parameter IR131A. VDD OSC2 OSC1/CLKIN CD 14 15 16 17 14 15 16 17 15, 16 17 18 19 — O I I P — ST CMOS Oscillator crystal input/external clock source input. RXPD 18 18 20 I A Legend: TTL = TTL compatible input A = Analog CMOS = CMOS compatible input I = Input ST = Schmitt Trigger input with CMOS levels P = Power OC = Open collector output O = Output 1: The state of the DTR output pin does not reflect the state of the DTR bit of the IrDA Primary Device. DS21790A-page 6 Preliminary  2003 Microchip Technology Inc. MCP2140 2.0 DEVICE OPERATION 2.3.1.1 The MCP2140 serial interface and IR baud rates are fixed at 9600 baud, given a 7.3728 MHz device clock. Crystal Oscillator / Ceramic Resonators 2.1 Power-Up Any time the device is powered up (Parameter D003), the Power-Up Timer delay (Parameter 33) occurs, followed by an Oscillator Start-up Timer (OST) delay (Parameter 32). Once these delays complete, communication with the device may be initiated. This communication is from both the infrared transceiver’s side and the controller’s UART interface. A crystal or ceramic resonator can be connected to the OSC1 and OSC2 pins to establish oscillation (Figure 2-1). The MCP2140 oscillator design requires the use of a parallel-cut crystal. Use of a series of cut crystals may give a frequency outside of the crystal manufacturers specifications. FIGURE 2-1: CRYSTAL OPERATION (CERAMIC RESONATOR) OSC1 To internal logic RF 2.2 Device Reset C1 XTAL OSC2 C2 RS (Note) The MCP2140 is forced into the reset state when the RESET pin is in the low state. Once the RESET pin is brought to a high state, the Device Reset sequence occurs. Once the sequence completes, functional operation begins. MCP2140 See Table 2-1 and Table 2-2 for recommended values of C1 and C2. Note: A series resistor may be required for AT strip cut crystals. 2.3 Device Clocks The MCP2140 requires a clock source to operate. This clock source is used to establish the device timing, including the device “Bit Clock”. TABLE 2-1: Freq 7.3728 MHz Note: 2.3.1 CLOCK SOURCE CAPACITOR SELECTION FOR CERAMIC RESONATORS OSC1 (C1) 10 - 22 pF OSC2 (C2) 10 - 22 pF The clock source can be supplied by one of the following: • Crystal • Resonator • External clock The frequency of this clock source must be 7.3728 MHz (electrical specification Parameter 1A) for device communication at 9600 baud. Higher capacitance increases the stability of the oscillator, but also increases the start-up time. These values are for design guidance only. Since each resonator has its own characteristics, the user should consult the resonator manufacturer for appropriate values of external components. TABLE 2-2: Freq 7.3728 MHz Note: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR OSC1 (C1) 15 - 30 pF OSC2 (C2) 15 - 30 pF Higher capacitance increases the stability of the oscillator but also increases the startup time. These values are for design guidance only. RS may be required to avoid overdriving crystals with low drive level specification. Since each crystal has its own characteristics, the user should consult the crystal manufacturer for appropriate values of external components.  2003 Microchip Technology Inc. Preliminary DS21790A-page 7 MCP2140 2.3.1.2 External Clock For applications where a clock is already available elsewhere, users may directly drive the MCP2140 provided that this external clock source meets the AC/DC timing requirements listed in Section 4.3, “Timing Diagrams and Specifications”. Figure 2-2 shows how an external clock circuit should be configured. FIGURE 2-2: Clock From external system Open EXTERNAL CLOCK OSC1 OSC2 MCP2140 2.3.2 BIT CLOCK The device crystal is used to derive the communication bit clock (BITCLK). There are 16 BITCLKs for each bit time. The BITCLKs are used for the generation of the start bit and the eight data bits. The stop bit uses the BITCLK when the data is transmitted (not for reception). This clock is a fixed-frequency and has minimal variation in frequency (specified by the crystal manufacturer). DS21790A-page 8 Preliminary  2003 Microchip Technology Inc. MCP2140 2.4 Host UART Interface 2.4.4 HARDWARE HANDSHAKING The Host UART interface communicates with the Host Controller. This interface has eight signals associated with it: TX, RX, RTS, CTS, DSR, DTR, CD and RI. Several of these signals are locally generated (not passed over the IR interface). The Host UART is a half-duplex interface, meaning that the system is either transmitting or receiving, but not both simultaneously. Note 1: The MCP2140 generates several nondata signals locally. 2: The MCP2140 emulates a 3-wire serial connection (TXD, RXD and GND). The transceiver’s Transmit Data (TXD), Receive Data (RXD) signals, and the state of the CD. RI and DTR input pins are carried back and forth to the Primary device. 3: The RTS and CTS signals are local emulations. There are three Host UART signals used to control the handshaking operation between the Host Controller and the MCP2140. They are: • DSR • RTS • CTS 2.4.4.1 DSR The DSR signal is used to indicate that a link has been established between the MCP2140 and the Primary Device. Please refer to Section 2.13, “How Devices Connect”, for information on how devices connect. 2.4.4.2 RTS 2.4.1 BAUD RATE The baud rate for the MCP2140 serial port (the TX and RX pins) is fixed at 9600 baud when the device frequency is 7.3728 MHz. The RTS signal indicates to the MCP2140 that the Host Controller is ready to receive serial data. Once an IR data packet has been received, the RTS signal will be low for the received data to be transferred to the Host Controller. If the RTS signal remains high, an IR link timeout will occur and the MCP2140 will disconnect from the Primary Device. 2.4.4.3 CTS 2.4.2 TRANSMITTING The MCP2140 generates the CTS signal locally due to buffer limitations. The MCP2140 uses a 64-byte buffer for incoming data from the IR Host. Another 29-byte buffer is provided to buffer data from the UART serial port. The MCP2140 can handle IR data and Host UART serial port data simultaneously. A hardware handshaking pin (CTS) is provided to inhibit the Host Controller from sending serial data when the Host UART buffer is not available (Figure 2-3). Figure 2-4 shows a flow chart for Host UART flow control using the CTS signal. Note: When the CTS output signal goes high, the UART FIFO will store up to 6 bytes. This is to allow devices that have a slow response time to a change on the CTS signal time to stop sending additional data (such as a modem). When the controller sends serial data to the MCP2140, the controller’s baud rate is required to match the baud rate of the MCP2140’s serial port. 2.4.3 RECEIVING When the controller receives serial data from the MCP2140, the controller’s baud rate is required to match the baud rate of the MCP2140’s serial port. FIGURE 2-3: CTS HOST UART CTS SIGNAL AND THE RECEIVE BUFFER Receive Buffer IR Data Packet Transmitted Full (29 Bytes) Receive Buffer Empty Receive Buffer Empty MCP2140 Can Receive Data Receive Buffer Has 22 Bytes, MCP2140 Can Receive Data CTS Pin Driven High IR Data Packet Starts Transmission  2003 Microchip Technology Inc. Preliminary DS21790A-page 9 MCP2140 FIGURE 2-4: HOST UART CTS FLOW CONTROL FLOWCHART IR Flow Start CTS Low? N Y Transmit Byte CTS Low? N Y CNTR = 6 DTR Low? N Y Lost IR Link Transmit Byte CTS Low? N Y CNTR = CNTR - 1 CNTR = 0? N Y DS21790A-page 10 Preliminary  2003 Microchip Technology Inc. MCP2140 2.5 Encoder/Decoder The encoder converts the UART format data into the IrDA Standard format data and the decoder converts IrDA Standard format data into UART format data. Each bit time is comprised of 16-bit clocks. If the value to be transmitted (as determined by the TX pin) is a logic-low, the TXIR pin will output a low level for 7-bit clock cycles, a logic high level for 3-bit clock cycles or a minimum of 1.6 µsec (see Parameter IR121). The remaining 6-bit clock cycles will be low. If the value to transmit is a logic-high, the TXIR pin will output a low level for the entire 16-bit clock cycles. 2.5.1 ENCODER (MODULATION) The data that the MCP2140 UART received (on the TX pin) that needs to be transmitted (on the TXIR pin) will need to be modulated. This modulated signal drives the IR transceiver module. Figure 2-5 shows the encoding of the modulated signal. Note: The signal on the TXIR pin does not actually line up in time with the bit value that was transmitted on the TX pin, as shown in Figure 2-5. The TX bit value is shown to represent the value to be transmitted on the TXIR pin. FIGURE 2-5: ENCODING Start Bit 16 CLK Data bit 0 Data bit 1 Data bit 2 Data bit ... BITCLK TX Bit Value TXIR 24 Tosc 0 1 0 0 1 0 7 CLK  2003 Microchip Technology Inc. Preliminary DS21790A-page 11 MCP2140 2.5.2 DECODER (DEMODULATION) 2.6 IR Port Baud Rate The modulated signal (data) from the IR transceiver module (on RXIR pin) needs to be demodulated to form the received data (on RX pin). Once demodulation of the data byte occurs, the data that is received is transmitted by the MCP2140 UART (on the RX pin). Figure 2-6 shows the decoding of the modulated signal. Note: The signal on the RX pin does not actually line up in time with the bit value that was received on the RXIR pin, as shown in Figure 2-6. The RXIR bit value is shown to represent the value to be transmitted on the RX pin. The baud rate for the MCP2140 IR port (the TXIR and RXIR pins) is fixed at the default rate of 9600 baud. The Primary device will be informed of this parameter during NDM. The Host UART baud rate and the IR port baud rate are the same. Each bit time is comprised of 16-bit clocks. If the value to be received is a logic-low, the RXIR pin will be a low level for the first 3-bit clock cycles, or a minimum of 1.6 µs. The remaining 13-bit clock cycles (or difference up to the 16-bit clock time) will be high. If the value to be received is a logic-high, the RXIR pin will be a high level for the entire 16-bit clock cycles. The level on the RX pin will be in the appropriate state for the entire 16 clock cycles. FIGURE 2-6: DECODING Start Bit 16 CLK Data bit 0 Data bit 1 Data bit 2 Data bit ... BITCLK (CLK) RXIR Bit Value RXPD RXPDREF ≥ 13 CLK ≥ 1.6 µs (up to 3 CLK) 16 CLK RX 0 1 0 0 1 0 16 CLK 16 CLK 16 CLK 16 CLK 16 CLK DS21790A-page 12 Preliminary  2003 Microchip Technology Inc. MCP2140 2.7 IrDA DATA PROTOCOLS SUPPORTED BY MCP2140 2.7.1 IRCOMM IrCOMM provides the method to support serial and parallel port emulation. This is useful for legacy COM applications, such as printers and modem devices. The IrCOMM standard is a syntax that allows the Primary device to consider the Secondary device a serial device. IrCOMM allows for emulation of serial or parallel (printer) connections of various capabilities. The MCP2140 supports the 9-wire “cooked” service class of IrCOMM. Other service classes supported by IrCOMM are shown in Figure 2-8. The IrDA protocol for printer support is not included in the IrCOMM 9-wire “cooked” service class. The MCP2140 supports these required IrDA standard protocols: • Physical Signaling Layer (PHY) • Link Access Protocol (IrLAP) • Link Management Protocol/Information Access Service (IrLMP/IAS) The MCP2140 also supports some of the optional protocols for IrDA standard data. The optional protocols implemented by the MCP2140 are: • Tiny TP • IrCOMM Figure 2-7 shows the IrDA data protocol stack and those components implemented by the MCP2140. FIGURE 2-7: IrDA DATA - PROTOCOL STACKS IrObex IrLan IrComm (1) IrMC IrTran-P LM-IAS Tiny Transport Protocol (Tiny TP) IR Link Management - Mux (IrLMP) IR Link Access Protocol (IrLAP) Asynchronous Synchronous Synchronous (2, 3) 4 PPM Serial IR Serial IR (4 Mb/s) (9600 -115200 b/s) (1.152 Mb/s) Optional IrDA data protocols not supported by the M CP2140 Note 1: The MCP2140 implements the 9-wire “cooked” service class serial replicator. 2: The MCP2140 is fixed at 9600 baud 3: An optical transceiver is required. Supported by the MCP2140 FIGURE 2-8: IRCOMM SERVICE CLASSES IrCOMM Services Uncooked Services Cooked Services Serial 3-wire Raw Parallel Centronics IEEE 1284 Serial 3-wire Cooked 9-wire Cooked Parallel IrLPT Supported by M CP2140  2003 Microchip Technology Inc. Preliminary DS21790A-page 13 MCP2140 2.8 Minimizing Power 2.8.1 AUTOMATIC LOW POWER MODE During IR communication between a Primary Device and the MCP2140, the MCP2140 is in an operational mode. In this mode, the MCP2140 consumes the operational current (Parameter D010). For many applications, the time that IR communication is occurring is a small percentage of the applications operational time. The ability for the IR controller to be in a low power mode during this time will save on the applications power consumption. The MCP2140 will automatically enter a low power mode once IR activity has stopped and will return to operational mode once IR activity is detected on the RXPD and RXPDREF pins. Another way to minimize system power is to use an I/O pin of the Host Controller to enable power to the IR circuity The Automatic Low Power mode allows the system to achieve the lowest possible operating current. When the IR link has been “closed”, the protocol handler state machine returns to the Normal Disconnect Mode (NDM). During NDM, if no IR activity occurs for about 10 seconds, the device is disabled and enters into Low Power mode. In this mode, the device oscillator is shut down and the PHACT pin will be low (Parameter D010A). Table 2-3 shows the MCP2140 current. These are specified in Parameter D010 and Parameter D010A. TABLE 2-3: Mode PHACT = H PHACT = L Note: DEVICE MAXIMUM OPERATING CURRENT Current 2.2 mA 60 µA Comment IR communications is occurring. No IR communications. Additional system current is from the Receiver/Transmitter circuitry. 2.8.2 RETURNING TO DEVICE OPERATION The device will exit the Low Power mode when the RXPD pin voltage crosses the REPDREF pin reference voltage. A device reset will also cause the MCP2140 to exit Low Power mode. After device initialization, if no IR activity occurs for about 10 seconds, the device is disabled and returns into the Low Power mode. Note: For proper operation, the device oscillator must be within oscillator specification in the time frame specified in Parameter IR140. 2.9 PHACT Signal The PHACT signal indicates that the MCP2140 Protocol Handler is active. This output pin is an open collector, so when interfacing to the Host Controller, a pull-up resistor is required. DS21790A-page 14 Preliminary  2003 Microchip Technology Inc. MCP2140 2.10 Buffers and Throughput TABLE 2-4: Bytes Transferred (3) THROUGHPUT Bytes/ CTS Low 23 (max) (1) 29 Time (S) 0.810133 0.6500 Effective Baud Rate 2962 (1) 3692 (2) The IR data rate of the MCP2140 is fixed at 9.6 kbaud. The actual throughput will be less due to several factors. The most significant factors are under the control of the developer. One factor beyond the control of the designer is the overhead associated with the IrDA standard. A throughput example is shown in Table 2-4. Figure 2-9 shows the CTS waveform, what the state of the buffers can be and the operation of the Host UART and IR interfaces. Figure 2-10 shows the screen-capture of a Host Controller transmitting 240 bytes. Data is not transmitted after CTS goes high (so only a maximum of 23 bytes of the 29 byte buffer are utilized). Between data packets, the CTS time can vary, depending on the Primary Device (see blue circled CTS pulse in Figure 2-10). 240 240 Note 1: Measured from Figure 2-10. 2: Interpolated from Figure 2-10. 3: 10 bits transferred for each byte. Note: IrDA throughput is based on many factors associated with characteristics of the Primary and Secondary devices. These characteristics may cause your throughput to be more or less than is shown in Table 2-4. FIGURE 2-9: CTS HOST UART RECEIVE BUFFER AND CTS WAVEFORM Receive Buffer IR Data Packet Transmitted Full (29 Bytes) Receive Buffer Empty Receive Buffer Empty MCP2140 Can Receive Data Receive Buffer Has 22 Bytes, MCP2140 Can Receive Data CTS Pin Driven High IR Data Packet Starts Transmission FIGURE 2-10: HOST CONTROLLER TRANSMISSION OF A 240 BYTE PACKET  2003 Microchip Technology Inc. Preliminary DS21790A-page 15 MCP2140 2.10.1 IMPROVING THROUGHPUT 2.10.1.1 From the Primary Device Actual maximum throughput is dependent on several factors, including: • Characteristics of the Primary device • Characteristics of the MCP2140 • IrDA standard protocol overhead The IrDA standard specifies how the data is passed between the Primary device and Secondary device. In IrCOMM, an additional 8 bytes are used by the protocol for each packet transfer. The most significant factor in data throughput is how well the data frames are filled. If only 1 byte is sent at a time, the throughput overhead of the IrCOMM protocol is 89% (see Table 2-5). The best way to maximize throughput is to align the amounts of data with the receive buffer (IR and Host UART) packet size of the MCP2140. Then there is the delay between when data packets are sent and received. See Figure 2-10 for an example of this delay (look at CTS signal falling edges). In this screen capture, a Palm™ m105 is receiving a 240byte string of data from the MCP2140. When the CTS signal goes high, the Host Controller stops sending data (23 bytes per CTS low-time). The CTS falling edge to CTS falling edge is approximately 90 ms (typical). This CTS high-time affects the total data throughput. The CTS high-time will be dependant on the characteristics of the Primary device. The MCP2140 uses a fixed IR Receiver data block size of 64 bytes. The minimum size frame the Primary device can respond with is 6 bytes. 2.10.1.2 From the MCP2140 The MCP2140 uses a fixed Host UART Receiver data block size of 29 bytes. 2.11 Turnaround Latency An IR link can be compared to a one-wire data connection. The IR transceiver can transmit or receive, but not both at the same time. A delay of one bit time is recommended between the time a byte is received and another byte is transmitted. 2.12 Device ID The MCP2140 has a fixed Device ID. This Device ID is “MCP2140 xx”, with the xx indicating the silicon revision of the device. TABLE 2-5: IRCOMM OVERHEAD % Data Packet IrCOMM IrCOMM Size Overhead Overhead % (1) MCP2140 (Bytes) (Bytes) Comment IR Receive Host UART Receive 64 1 29 23 1 8 8 8 8 8 11 % 89 % 22 % 26 % 89 % Note 3 Note 4 Note 2 Note 1: Overhead % = Overhead/(Overhead + Data). 2: The maximum number of bytes of the IR Receive buffer. 3: The maximum number of bytes of the Host UART Receive buffer. 4: The CTS signal is driven high at 23 byte. DS21790A-page 16 Preliminary  2003 Microchip Technology Inc. MCP2140 2.13 Optical Interface 2.13.2 INTEGRATED TRANSCEIVER The MCP2140 requires an infrared transceiver for the optical interface. This transceiver can be a single-chip solution (integrated) or be implemented with discrete devices. T he MCP2140 was designed to use a discrete implementation that allows the lowest system power consumption and a low cost implementation (see Section 2.12.1, “Discrete Transceiver Solution”). It is possible to use an integrated optical transceiver solution, with the addition of four components. Two components are required to condition the input signal to ensure that the RXIR pulse width is not greater than 1.5 µs (see Parameter IR131A). The other two components are required to set the RXIR signal trip point (typically VDD/2). Figure 2-12 shows an example MCP2140 optical transceiver circuit, using a Vishay®/ Temic TFDS4500. 2.13.1 DISCRETE TRANSCEIVER SOLUTION The MCP2140 was designed to use a discrete implementation that allows the lowest system power consumption as well as a low cost implementation. Figure 2-12 shows transceiver circuit. a typical discrete optical FIGURE 2-11: CIRCUIT FOR A DISCRETE OPTICAL TRANSCEIVER FIGURE 2-12: CIRCUIT FOR AN INTEGRATED OPTICAL TRANSCEIVER +5 V RXPDREF (To MCP2140 Pin 1) This figure will be available in Revision B of the MCP2140 data sheet. Please conact the Microchip factory via email (tech.support@microchip.com) for additional information. Care must be taken in the design and layout of the photo-detect circuit, due to the small signals that are being detected and their sensitivity to noise. +5 V R14 (2) 10 kΩ R15 (2) 10 kΩ +5 V R13 47Ω U6 1 2 3 4 8 7 6 5 Q1 (1) MUN211T1 RXPD (To MCP2140 Pin 18) +5 V R11 22Ω TXIR (To MCP2140 Pin 2) C19 (1) 68 pF C18 .1 µF TFDS4500 Note 1: These components are used to control the width of the TFDS4500 RXD output signal. Q1 is a digital transistor, which includes the bias resistors. 2: These components are used to set the reference voltage that the RXPD signal needs to cross to “detect” a bit. Table 2-6 shows a list of common manufacturers of integrated optical transceivers.  2003 Microchip Technology Inc. Preliminary DS21790A-page 17 MCP2140 2.14 How The MCP2140 Connects When two devices, implementing the IrDA standard feature, establish a connection using the IrCOMM protocol, the process is analogous to connecting two devices with serial ports using a cable. This is referred to as a “point-to-point” connection. This connection is limited to half-duplex operation because the IR transceiver cannot transmit and receive at the same time. The purpose of the IrDA standard protocol is to allow this half-duplex link to emulate, as much as possible, a full-duplex connection. In general, this is done by dividing the data into “packets”, or groups of data. These packets can be sent back and forth, when needed, without risk of collision. The rules of how and when these packets are sent constitute the IrDA standard protocol. The MCP2140 supports elements of this IrDA standard protocol to communicate with other IrDA standard compatible devices. When a wired connection is used, the assumption is made that both sides have the same communications parameters and features. A wired connection has no need to identify the other connector because it is assumed that the connectors are properly connected. According to the IrDA standard, a connection process has been defined to identify other IrDA standard compatible devices and establish a communication link. There are three steps that these two devices go through to make this connection. They are: • Normal Disconnect Mode (NDM) • Discovery Mode • Normal Connect Mode (NCM) Figure 2-13 shows the connection sequence. ports. If you used such a cell phone with a Personal Digital Assistant (PDA), the PDA that supports the IrDA standard feature would be the Primary device and the cell phone would be the Secondary device. When a Primary device polls for another device, a nearby Secondary device may respond. When a Secondary device responds, the two devices are defined to be in the Normal Disconnect Mode (NDM) state. NDM is established by the Primary device broadcasting a packet and waiting for a response. These broadcast packets are numbered. Usually, 6 or 8 packets are sent. The first packet is number 0, while the last packet is usually numbered 5 or 7. Once all the packets are sent, the Primary device sends an ID packet, which is not numbered. The Secondary device waits for these packets and then responds to one of the packets. The packet responds to determine the “timeslot” to be used by the Secondary device. For example, if the Secondary device responds after packet number 2, the Secondary device will use timeslot 2. If the Secondary device responds after packet number 0, the Secondary device will use timeslot 0. This mechanism allows the Primary device to recognize as many nearby devices as there are timeslots. The Primary device will continue to generate timeslots and the Secondary device should continue to respond, even if there’s nothing to do. Note 1: The MCP2140 can only be used to implement a Secondary device. 2: The MCP2140 supports a system with only one Secondary device having exclusive use of the IrDA standard infrared link (known as “point-to-point” communication). 3: The MCP2140 always responds to packet number 0. This means that the MCP2140 will always use timeslot 0. 4: If another Secondary device is nearby, the Primary device may fail to recognize the MCP2140, or the Primary device may not recognize either of the devices. During NDM, the MCP2140 handles all responses to the Primary device (Figure 2-13) without any communication with the Host Controller. The Host Controller is inhibited by the CTS signal of the MCP2140 from sending data to the MCP2140. 2.14.1 NORMAL DISCONNECT MODE (NDM) When two IrDA standard compatible devices come into range, they must first recognize each other. The basis of this process is that one device has some task to accomplish and the other device has a resource needed to accomplish this task. One device is referred to as a Primary device while the other is referred to as a Secondary device. The distinction between Primary device and Secondary device is important because it is the responsibility of the Primary device to provide the mechanism to recognize other devices. So the Primary device must first poll for nearby IrDA standard compatible devices and, during this polling, the default baud rate of 9600 baud is used by both devices. For example, if you want to print from an IrDA-equipped laptop to an IrDA-equipped printer, utilizing the IrDA standard feature, you would first bring your laptop in range of the printer. In this case, the laptop is the one that has something to do and the printer has the resource to do it. Thus, the laptop is called the Primary device and the printer is the Secondary device. Some data-capable cellphones have IrDA standard infrared DS21790A-page 18 Preliminary  2003 Microchip Technology Inc. MCP2140 2.14.2 DISCOVERY MODE 2.14.3 NORMAL CONNECT MODE (NCM) Discovery mode allows the Primary device to determine the capabilities of the MCP2140 (Secondary device). Discovery mode is entered once the MCP2140 (Secondary device) has sent a XID response to the Primary device and the Primary device has completed sending the XIDs and a Broadcast ID. If this sequence is not completed, a Primary and Secondary device can stay in NDM indefinitely. When the Primary device has something to do, it initiates Discovery, which has two parts. They are: • Link initialization • Resource determination The first step is for the Primary and Secondary devices to determine, and then adjust to, each other’s hardware capabilities. These capabilities are parameters like: • • • • Data rate Turnaround time Number of packets without a response How long to wait before disconnecting Once discovery has been completed, the Primary device and MCP2140 (Secondary device) can freely exchange data. The MCP2140 uses a hardware handshake to stop the local serial port from sending data when the MCP2140 Host UART Receiving buffer is full.. Note: Data loss will result if this hardware handshake is not observed. Both the Primary device and the MCP2140 (Secondary device) check to make sure that data packets are received by the other without errors. Even when data is not required to be sent, the Primary and Secondary devices will still exchange packets to ensure that the connection hasn’t, unexpectedly, been dropped. When the Primary device has finished, it transmits the “close link” command to the MCP2140 (Secondary device). The MCP2140 will confirm the “close link” command and both the Primary device and the MCP2140 (Secondary device) will revert to the NDM state. Note: If the NCM mode is unexpectedly terminated for any reason (including the Primary device not issuing a close link command), the MCP2140 will revert to the NDM state approximately 10 seconds after the last frame has been received. Both the Primary and Secondary devices begin communications at 9600 baud, the default baud rate. The Primary device sends its parameters and the Secondary device responds with its parameters. For example, if the Primary device supports all data rates up to 115.2 kbaud and the Secondary device only supports 9.6 kbaud, the link will be established at 9.6 kbaud. Note: The MCP2140 is limited to a data rate of 9.6 kbaud. Once the hardware parameters are established, the Primary device must determine if the Secondary device has the resources it requires. If the Primary device has a job to print, it must know if it’s talking to a printer, and not a modem or other device. This determination is made using the Information Access Service (IAS). The job of the Secondary device is to respond to IAS queries made by the Primary device. The Primary device must ask a series of questions like: • What is the name of your service? • What is the address of this service? • What are the capabilities of this device? When all the Primary device’s questions are answered, the Primary device can access the service provided by the Secondary device. During Discovery mode, the MCP2140 handles all responses to the Primary device (see Figure 2-13) without any communication with the Host Controller. The Host Controller is inhibited by the CTS signal of the MCP2140 from sending data to the MCP2140. It is the responsibility of the Host Controller program to understand the meaning of the data received and how the program should respond to it. It’s just as if the data were being received by the Host Controller from a UART. 2.14.3.1 Primary Device Notification The MCP2140 identifies itself to the Primary device as a modem. Note: The MCP2140 identifies itself as a modem to ensure that it is identified as a serial device with a limited amount of memory. However, the MCP2140 is not a modem, and the nondata circuits are not handled in a modem fashion.  2003 Microchip Technology Inc. Preliminary DS21790A-page 19 MCP2140 FIGURE 2-13: HIGH LEVEL MCP2140 CONNECTION SEQUENCE Primary Device Normal Disconnect Mode (NDM) No IR Activity (for 10 seconds) Send XID Commands (timeslots n, n+1, ...) (approximately 70 ms between XID commands) MCP2140 (Secondary Device) PHACT pin driven Low PHACT pin driven High No Response Finish sending XIDs (max timeslots - y frames) Broadcast ID XID Response in timeslot y, claiming this timeslot, (MCP214X always claims timeslot 0) No Response to these XIDs No Response to Broadcast ID Discovery Send SNRM Command (w/ parameters and connection address) UA response with parameters using connect address Open channel for IAS Queries Confirm channel open for IAS Send IAS Queries Provide IAS responses Open channel for data Confirm channel open for data Normal Response Mode (NRM) Send Data or Status Send Data or Status (MCP2140 DSR pin driven low) Send Data or Status Send Data or Status Shutdown link Confirm shutdown (back to NDM state) No IR Activity (for 10 seconds) PHACT pin driven Low DS21790A-page 20 Preliminary  2003 Microchip Technology Inc. MCP2140 2.15 References The IrDA Standards download page can be found at: http://www.irda.org/standards/specifications Some common manufacturers of optical transceivers are shown in Table 2-6. TABLE 2-6: COMMON OPTICAL TRANSCEIVER MANUFACTURERS Company Web Site Address www.sharpsma.com www.infineon.com www.agilent.com www.vishay.com www.rohm.com Company Sharp ® Infineon® Agilent Rohm ® Vishay®/Temic  2003 Microchip Technology Inc. Preliminary DS21790A-page 21 MCP2140 NOTES: DS21790A-page 22 Preliminary  2003 Microchip Technology Inc. MCP2140 3.0 DEVELOPMENT TOOLS An MCP2140 Demo/Development board is planned. Please check with the Microchip Technology Inc. web site (www.microchip.com) or your local Microchip sales office for product availability.  2003 Microchip Technology Inc. Preliminary DS21790A-page 23 MCP2140 NOTES: DS21790A-page 24 Preliminary  2003 Microchip Technology Inc. MCP2140 4.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Ambient Temperature under bias ........................................................................................................... –40°C to +125°C Storage Temperature ............................................................................................................................. –65°C to +150°C Voltage on VDD with respect to VSS ........................................................................................................... -0.3V to +7.5V Voltage on RESET with respect to VSS ...................................................................................................... -0.3V to +14V Voltage on all other pins with respect to VSS ................................................................................. –0.3V to (VDD + 0.3V) Total Power Dissipation (1) ........................................................................................................................................... 1W Max. Current out of VSS pin .................................................................................................................................. 300 mA Max. Current into VDD pin ..................................................................................................................................... 250 mA Input Clamp Current, IIK (VI < 0 or VI > VDD) ................................................................................................................... ±20 mA Output Clamp Current, IOK (V0 < 0 or V0 > VDD)............................................................................................................. ±20 mA Max. Output Current sunk by any Output pin.......................................................................................................... 25 mA Max. Output Current sourced by any Output pin..................................................................................................... 25 mA Note 1: Power Dissipation is calculated as follows: P DIS = VDD x {IDD - ∑ IOH} + ∑ {(VDD-VOH) x IOH} + ∑(VOL x IOL) †NOTICE: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2003 Microchip Technology Inc. Preliminary DS21790A-page 25 MCP2140 FIGURE 4-1: 6.0 5.5 5.0 VDD (Volts) 4.5 4.0 3.5 3.0 2.5 VOLTAGE-FREQUENCY GRAPH, -40°C ≤ TA ≤ +85°C 0 4 8 7.3728 10 12 16 20 Frequency (MHz) DS21790A-page 26 Preliminary  2003 Microchip Technology Inc. MCP2140 4.1 DC Characteristics Electrical Characteristics: Standard Operating Conditions (unless otherwise specified) Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Characteristic Supply Voltage RAM Data Retention Voltage (2) VDD Start Voltage to ensure Power-on Reset VDD Rise Rate to ensure Power-on Reset Supply Current (3, 4) Min 3.0 2.0 — 0.05 — — Typ(1) — — VSS — — 25 Max 5.5 — — — 2.2 60 Units V V V V/ms mA µA VDD = 3.0V, PHACT = H VDD = 3.0V, PHACT = L Conditions See Figure 4-1 Device Oscillator/Clock stopped DC Specifications Param. No. D001 D002 D003 D004 D010 D010A Sym VDD VDR VPOR SVDD IDD Note 1: Data in the Typical (“Typ”) column is based on characterization results at 25°C. This data is for design guidance only and is not tested. 2: This is the limit to which VDD can be lowered without losing RAM data. 3: When the device is in IR communication (PHACT pin is high), supply current is mainly a function of the operating voltage and frequency. Pin loading, pin rate and temperature have an impact on the current consumption.The test conditions for all IDD measurements are made when device is: OSC1 = external square wave, from rail-to-rail; all input pins pulled to VSS, RXIR = VDD, RESET = VDD; 4: When the device is in low power mode (PHACT pin is low), current is measured with all input pins tied to VDD or VSS and the output pins driving a high or low level into infinite impedance.  2003 Microchip Technology Inc. Preliminary DS21790A-page 27 MCP2140 4.1 DC Characteristics (Continued) Electrical Characteristics: Standard Operating Conditions (unless otherwise specified) Operating temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 4.1. Characteristic Input Low Voltage VIL D030 D030A D032 D033 VIH D040 D040A D042 D043 Input pins with TTL buffer (TX, RI, DTR, RTS, and CD) RESET OSC1 Input High Voltage Input pins with TTL buffer (TX, RI, DTR, RTS, and CD) RESET OSC1 Input Leakage Current (Notes 1, 2) D060 D061 D063 D080 D083 D090 D092 VOH VOL IIL Input pins RESET OSC1 Output Low Voltage TXIR, RX, DSR, and CTS pins OSC2 Output High Voltage (Note 2) TXIR, RX, DSR, and CTS pins OSC2 Capacitive Loading Specs on Output Pins D100 D101 COSC2 OSC2 pin CIO All Input or Output pins — — — — 15 50 pF pF When external clock is used to drive OSC1. VDD - 0.7 VDD - 0.7 — — — — V V IOH = -3.0 mA, VDD = 4.5V IOH = -1.3 mA, VDD = 4.5V — — — — 0.6 0.6 V V IOL = 8.5 mA, VDD = 4.5V IOL = 1.6 mA, VDD = 4.5V — — — — — — ±1 ±5 ±5 µA µA µA VSS ≤ VPIN ≤ VDD, pin at high-impedance. VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD 2.0 0.25 VDD + 0.8 0.8 VDD 0.7 VDD — — — — — VDD VDD VDD VDD V V V V 4.5V ≤ V DD ≤ 5.5V otherwise VSS VSS VSS VSS — — — — 0.8V 0.15 VDD 0.2 VDD 0.3 VDD V V V V 4.5V ≤ V DD ≤ 5.5V otherwise Min Typ Max Units Conditions DC Specifications Param No. Sym Note 1: The leakage current on the RESET pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. 2: Negative current is defined as coming out of the pin. DS21790A-page 28 Preliminary  2003 Microchip Technology Inc. MCP2140 4.2 4.2.1 Timing Parameter Symbology and Load Conditions TIMING CONDITIONS The timing parameter symbols have been created following one of the following formats: The temperature and voltages specified in Table 4-2 apply to all timing specifications, unless otherwise noted. Figure 4-2 specifies the load conditions for the timing specifications. TABLE 4-1: SYMBOLOGY 2. TppS T Time 1. TppS2ppS T F Frequency E Error Lowercase letters (pp) and their meanings: pp io Input or Output pin rx Receive bitclk RX/TX BITCLK drt Device Reset Timer Uppercase letters and their meanings: S F Fall H High I Invalid (high-impedance) L Low osc tx RST Oscillator Transmit Reset P R V Z Period Rise Valid High-impedance TABLE 4-2: AC TEMPERATURE AND VOLTAGE SPECIFICATIONS Electrical Characteristics: Standard Operating Conditions (unless otherwise stated): Operating temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating voltage VDD range as described in DC spec Section 4.1. AC Specifications FIGURE 4-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Pin VSS CL CL = 50 pF for all pins except OSC2 15 pF for OSC2 when external clock is used to drive OSC1  2003 Microchip Technology Inc. Preliminary DS21790A-page 29 MCP2140 4.3 Timing Diagrams and Specifications EXTERNAL CLOCK TIMING Q4 OSC1 1 2 3 3 4 4 Q1 Q2 Q3 Q4 Q1 FIGURE 4-3: TABLE 4-3: EXTERNAL CLOCK TIMING REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic External CLKIN Period (2, 3) Min 90.422 90.422 90.422 7.3728 7.3728 — — — Typ(1) — — — 7.3728 — — — — Max 90.422 — 90.422 7.3728 7.3728 ± 0.01 ± 0.01 15 Units ns ns ns MHz MHz % % ns Conditions Device Operation Low Power mode (PHACT drive Low) AC Specifications Param. No. 1 Sym TOSC Oscillator Period (2) 1A FOSC External CLKIN Frequency (2, 3) Oscillator Frequency (2) 1B 1C 4 FERR ECLK Error in Frequency External Clock Error TosR, Clock in (OSC1) TosF Rise or Fall Time Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. These parameters are for design guidance only and are not tested. 2: All specified values are based on oscillator characterization data under standard operating conditions. Exceeding these specified limits may result in unstable oscillator operation and/or higher than expected current consumption. When an external clock input is used, the “max” cycle time limit is “DC” (no clock) for all devices. 3: A duty cycle of no more than 60% (High time/Low time or Low time/High time) is recommended for external clock inputs. DS21790A-page 30 Preliminary  2003 Microchip Technology Inc. MCP2140 FIGURE 4-4: OUTPUT WAVEFORM Q4 OSC1 Q1 Q2 Q3 Output Pin Old Value 20, 21 New Value Note: Refer to Figure 4-2 for load conditions. TABLE 4-4: OUTPUT TIMING REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic RX and TXIR pin rise time (2) RX and TXIR pin fall time (2) Min — — Typ(1) 10 10 Max 40 40 Units ns ns Conditions AC Specifications Param. No. 20 21 Sym ToR ToF Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. 2: See Figure 4-2 for loading conditions.  2003 Microchip Technology Inc. Preliminary DS21790A-page 31 MCP2140 FIGURE 4-5: VDD RESET Reset Detected PWRT Timeout OSC Timeout Internal RESET 34 Output Pin 34 33 32 30 RESET AND DEVICE RESET TIMING TABLE 4-5: RESET AND DEVICE RESET REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Min 2000 1024 28 — Typ(1) — — 72 — Max — 1024 132 2 Units ns TOSC ms µs VDD = 5.0V Conditions VDD = 5.0V AC Specifications Param. No. 30 32 33 34 Sym TRSTL RESET Pulse Width (low) TOST TIOZ Oscillator Start-up Timer Period Output High-impedance from RESET Low or device Reset TPWRT Power up Timer Period Note 1: Data in the Typical (“Typ”) column is at 5V, 25°C unless otherwise stated. DS21790A-page 32 Preliminary  2003 Microchip Technology Inc. MCP2140 FIGURE 4-6: UART ASYNCHRONOUS TRANSMISSION WAVEFORM Start Bit IR100 Data Bit IR100 Data Bit IR100 Data Bit IR100 TX pin IR103 Note: Refer to Figure 4-2 for load conditions. IR103 TABLE 4-6: UART ASYNCHRONOUS TRANSMISSION REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Min 768 — — — Typ — — — — Max 768 ±2 ±1 25 Units TOSC % % ns Conditions BAUD2:BAUD0 = 00 AC Specifications Param. No. IR100 IR101 Sym TTXBIT Transmit Baud rate ETXBIT Transmit (TX pin) Baud rate Error (into MCP2140) IR102 ETXIRBIT Transmit (TXIR pin) Baud rate Error (out of MCP2140) (1) IR103 TTXRF TX pin rise time and fall time Note 1: This error is not additive to IR101 parameter.  2003 Microchip Technology Inc. Preliminary DS21790A-page 33 MCP2140 FIGURE 4-7: UART ASYNCHRONOUS RECEIVE TIMING Start Bit IR110 Data Bit IR110 Data Bit IR110 Data Bit IR110 RX pin IR113 Note: Refer to Figure 4-2 for load conditions. IR113 TABLE 4-7: UART ASYNCHRONOUS RECEIVE REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85×C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Min 768 — — — Typ — — — — Max Units 768 ±1 ±1 25 Conditions AC Specifications Param. No. IR110 IR111 IR112 IR113 Sym TRXBIT Receive Baud Rate ERXBIT Receive (RXPD and RXPDREF pin detection) Baud rate Error (into MCP2140) ERXBIT Receive (RX pin) Baud rate Error (out of MCP2140) (1) TTXRF RX pin rise time and fall time TOSC BAUD2:BAUD0 = 00 % % ns Note 1: This error is not additive to the IR111 parameter. DS21790A-page 34 Preliminary  2003 Microchip Technology Inc. MCP2140 FIGURE 4-8: TXIR WAVEFORMS Start Bit IR100A BITCLK IR122 TXIR IR121 0 1 0 0 1 0 IR122 IR122 IR122 IR122 IR122 Data bit 7 Data bit 6 Data bit 5 Data bit ... TABLE 4-8: TXIR REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Transmit Baud Rate TXIR pulse width TXIR bit period (1) Min 768 24 — Typ — — 16 Max 768 24 — Units TOSC TOSC TBITCLK Conditions BAUD = 9600 AC Specifications Param. No. IR100A IR121 IR122 Sym TTXIRBIT TTXIRPW TTXIRP Note 1: TBITCLK = TTXBIT/16.  2003 Microchip Technology Inc. Preliminary DS21790A-page 35 MCP2140 FIGURE 4-9: RXPD/RXPDREF WAVEFORMS Start Bit IR110A BITCLK RXPD RXPDREF IR131A IR131B 0 Start Bit IR131B 1 Data bit 7 IR131B 0 Data bit 6 IR131B 0 Data bit 5 IR131B 1 Data bit ... IR131B 0 Data bit 7 Data bit 6 Data bit 5 Data bit ... RXPD RXPDREF IRD160 IRD161 RXPD RXPDREF IRD161 IRD160 TABLE 4-9: RXPD/RXPDREF REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Min 768 0.01 — 20 Typ — — 16 — Max 768 1.5 — — Units TOSC µs TBITCLK mV Conditions BAUD = 9600 AC Specifications Param. No. Sym IR110A TRXPDBIT Receive Baud Rate IR131A TRXPDPW RXPD pulse width IR132 TRXPDP RXPD/RXPDREF bit period (1) IRD060 VRXPDD∆ Quiescent Delta Voltage between RXPD and RXPDREF IRD061 VRXPDE IR Pulse Detect Delta Voltage (RXPD to RXPDREF) IR133 TRESP Response Time (2) * These parameters characterized but not tested. Note 1: TBITCLK = TRXBIT/16. 30 — — — — 400 * mV ns RXPD signal must cross RXPDREF signal level 2: Response time measured with RXPDREF at (VDD - 1.5V)/2, while RXPD transitions from VSS to VDD. DS21790A-page 36 Preliminary  2003 Microchip Technology Inc. MCP2140 FIGURE 4-10: OSC1 RXPD RXPDREF IR140 LOW POWER WAVEFORM TABLE 4-10: LOW POWER REQUIREMENTS Electrical Characteristics: Standard Operating Conditions (unless otherwise specified): Operating Temperature: -40°C ≤ TA ≤ +85°C (industrial) Operating Voltage VDD range is described in Section 4.1 Characteristic Min — Typ — Max 4 Units ms Conditions AC Specifications Param. No. IR140 Sym TRXPD2OSC RXPD pulse edge to valid device oscillator (1) Note 1: At 9600 Baud, 4 ms is 4 bytes (of the 11 byte repeated SOF character). This allows the MCP2140 to recognize a SOF character and properly receive the IR packet.  2003 Microchip Technology Inc. Preliminary DS21790A-page 37 MCP2140 NOTES: DS21790A-page 38 Preliminary  2003 Microchip Technology Inc. MCP2140 5.0 DC AND AC CHARACTERISTICS GRAPHS AND TABLES Not available at this time.  2003 Microchip Technology Inc. Preliminary DS21790A-page 39 MCP2140 NOTES: DS21790A-page 40 Preliminary  2003 Microchip Technology Inc. MCP2140 6.0 6.1 PACKAGING INFORMATION Package Marking Information 18-Lead PDIP (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXYYWWNNN Example: MCP2140-I/P XXXXXXXXXXXXXXXXX XXXXX0352987 18-Lead SOIC (300 mil) XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXXYYWWNNN Example: MCP2140-I/SO XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX XXXXX0352987 20-Lead SSOP (209 mil, 5.30 mm) Example: XXXXXXXXXXX XXXXXXXXXXX XXXYYWWNNN MCP2140 I/SS XXX0352987 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Note : In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard device marking consists of Microchip part number, year code, week code and traceability code.  2003 Microchip Technology Inc. Preliminary DS21790A-page 41 MCP2140 18-Lead Plastic Dual In-line (P) – 300 mil (PDIP) E1 D 2 n E A L A1 B1 β eB Units Dimension Limits n p INCHES* NOM 18 .100 .140 .155 .115 .130 .015 .300 .313 .240 .250 .890 .898 .125 .130 .008 .012 .045 .058 .014 .018 .310 .370 5 10 5 10 MILLIMETERS NOM 18 2.54 3.56 3.94 2.92 3.30 0.38 7.62 7.94 6.10 6.35 22.61 22.80 3.18 3.30 0.20 0.29 1.14 1.46 0.36 0.46 7.87 9.40 5 10 5 10 B p 1 α A2 c MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane A .170 Molded Package Thickness A2 .145 Base to Seating Plane A1 Shoulder to Shoulder Width E .325 Molded Package Width E1 .260 Overall Length D .905 Tip to Seating Plane L .135 c Lead Thickness .015 Upper Lead Width B1 .070 Lower Lead Width B .022 eB Overall Row Spacing § .430 α Mold Draft Angle Top 15 β Mold Draft Angle Bottom 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-007 4.32 3.68 8.26 6.60 22.99 3.43 0.38 1.78 0.56 10.92 15 15 DS21790A-page 42 Preliminary  2003 Microchip Technology Inc. MCP2140 18-Lead Plastic Small Outline (SO) – Wide, 300 mil (SOIC) E p E1 D 2 B n 1 h 45 ° α c A A2 β φ L A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D h L φ c B α β MIN .093 .088 .004 .394 .291 .446 .010 .016 0 .009 .014 0 0 INCHES* NOM 18 .050 .099 .091 .008 .407 .295 .454 .020 .033 4 .011 .017 12 12 MAX MIN .104 .094 .012 .420 .299 .462 .029 .050 8 .012 .020 15 15 MILLIMETERS NOM 18 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 11.33 11.53 0.25 0.50 0.41 0.84 0 4 0.23 0.27 0.36 0.42 0 12 0 12 MAX 2.64 2.39 0.30 10.67 7.59 11.73 0.74 1.27 8 0.30 0.51 15 15 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-051  2003 Microchip Technology Inc. Preliminary DS21790A-page 43 MCP2140 20-Lead Plastic Shrink Small Outline (SS) – 209 mil, 5.30 mm (SSOP) E E1 p D B n 2 1 α c A A2 φ L β A1 Number of Pins Pitch Overall Height Molded Package Thickness Standoff § Overall Width Molded Package Width Overall Length Foot Length Lead Thickness Foot Angle Lead Width Mold Draft Angle Top Mold Draft Angle Bottom * Controlling Parameter § Significant Characteristic Units Dimension Limits n p A A2 A1 E E1 D L c φ B α β MIN .068 .064 .002 .299 .201 .278 .022 .004 0 .010 0 0 INCHES* NOM 20 .026 .073 .068 .006 .309 .207 .284 .030 .007 4 .013 5 5 MAX MIN .078 .072 .010 .322 .212 .289 .037 .010 8 .015 10 10 MILLIMETERS NOM 20 0.65 1.73 1.85 1.63 1.73 0.05 0.15 7.59 7.85 5.11 5.25 7.06 7.20 0.56 0.75 0.10 0.18 0.00 101.60 0.25 0.32 0 5 0 5 MAX 1.98 1.83 0.25 8.18 5.38 7.34 0.94 0.25 203.20 0.38 10 10 Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-150 Drawing No. C04-072 DS21790A-page 44 Preliminary  2003 Microchip Technology Inc. MCP2140 APPENDIX A: Revision A • This is a new data sheet REVISION HISTORY APPENDIX B: NETWORK LAYERING REFERENCE MODEL Figure B-1 shows the ISO Network Layering Reference Model. The shaded areas are implemented by the MCP2140, while the cross-hatched area is implemented by an infrared transceiver. The unshaded areas should be implemented by the Host Controller. FIGURE B-1: ISO REFERENCE LAYER MODEL OSI REFERENCE LAYERS Application Presentation Session Transport Network Data Link Layer Regions implemented by the Optical Transceiver logic Supervisor Regions implemented by the MCP2140 Has to be implemented in Host Controller firmware (such as a PICmicro® microcontroller) LLC (Logical Link Control) Acceptance Filtering Overload Notification Recovery Management MAC (Medium Access Control) Data Encapsulation/Decapsulation Frame Coding (stuffing, destuffing) Medium Access Management Error Detection Error Signalling Acknowledgment Serialization/Deserialization Physical Layer PLS (Physical Signalling) Bit Encoding/Decoding Bit Timing Synchronization PMA (Physical Medium Attachment) Driver/Receiver Characteristics MDI (Medium Dependent Interface) Connectors Fault confinement (MAC-LME) Bus Failure management (PLS-LME)  2003 Microchip Technology Inc. Preliminary DS21790A-page 45 MCP2140 The IrDA Standard specifies the following protocols: • Physical Signaling Layer (PHY) • Link Access Protocol (IrLAP) • Link Management Protocol/Information Access Service (IrLMP/IAS) The IrDA data lists optional protocols. They are: • • • • • • • Tiny TP IrTran-P IrOBEX IrLAN IrCOMM IrMC IrDA Lite B.1 IrDA STANDARD DATA PROTOCOLS SUPPORTED BY MCP2140 The MCP2140 supports these required IrDA standard protocols: • Physical Signaling Layer (PHY) • Link Access Protocol (IrLAP) • Link Management Protocol/Information Access Service (IrLMP/IAS) The MCP2140 also supports some of the optional protocols for IrDA data. The optional protocols that the MCP2140 implements are: • Tiny TP • IrCOMM Figure B-2 shows the IrDA data protocol stack and which components are implemented by the MCP2140. B.1.1 PHYSICAL SIGNAL LAYER (PHY) FIGURE B-2: IRDA DATA - PROTOCOL STACKS (1) The MCP2140 provides the following Physical Signal Layer specification support: • Bidirectional communication • Data Packets are protected by a CRC - 16-bit CRC for speeds up to 115.2 kbaud Note: MCP2140 supports 9600 Baud only. • Data Communication Rate - 9600 baud minimum data rate (with primary speed/cost steps of 115.2 kbaud Note: MCP2140 supports 9600 Baud only. The following Physical Layer Specification is dependant on the optical transceiver logic used in the application. The specification states: • Communication Range, which sets the end user expectation for discovery, recognition and performance. - Continuous operation from contact to at least 1 meter (typically 2 meters can be reached) - A low power specification reduces the objective for operation from contact to at least 20 cm (low power and low power) or 30 cm (low power and standard power) IrTran-P LM-IAS IrObex IrLan IrComm IrMC Tiny Transport Protocol (Tiny TP) IR Link Management - Mux (IrLMP) IR Link Access Protocol (IrLAP) Asynchronous Synchronous Synchronous (2, 3) 4 PPM Serial IR Serial IR (4 Mb/s) (9600 -115200 b/s) (1.152 Mb/s) Supported by the MCP2140 Optional IrDA data protocols not supported by the MCP2140 Note 1: The MCP2140 implements the 9-wire “cooked” service class serial replicator. 2: The MCP2140 is fixed at 9600 Baud. 3: An optical transceiver is required. DS21790A-page 46 Preliminary  2003 Microchip Technology Inc. MCP2140 B.1.2 IrLAP The IrLAP protocol provides: • Management of communication processes on the link between devices • A device-to-device connection for the reliable, ordered transfer of data • Device discover procedures • Hidden node handling. 115.2 kbaud Note: Not supported by MCP2140. Figure B-3 identifies the key parts and hierarchy of the IrDA protocols. The bottom layer is the Physical layer, IrPHY. This is the part that converts the serial data to and from pulses of IR light. IR transceivers can’t transmit and receive at the same time. The receiver has to wait for the transmitter to finish sending. This is sometimes referred to as a “Half-Duplex” connection. The IR Link Access Protocol (IrLAP) provides the structure for packets (or “frames”) of data to emulate data that would normally be free to stream back and forth. Figure B-4 shows how the IrLAP frame is organized. The frame is preceded by some number of Beginning of Frame characters (BOFs). The value of the BOF is generally 0xC0, but 0xFF may be used if the last BOF character is a 0xC0. The purpose of multiple BOFs is to give the other station some warning that a frame is coming. The IrLAP frame begins with an address byte (“A” field), then a control byte (“C” field). The control byte is used to differentiate between different types of frames and is also used to count frames. Frames can carry status, data or commands. The IrLAP protocol has a command syntax of it’s own. These commands are part of the control byte. Lastly, IrLAP frames carry data. This data is the information (or “I”) field. The integrity of the frame is ensured with a 16-bit CRC, referred to as the Frame Check Sequence (FCS). The 16-bit CRC value is transmitted LSB first. The end of the frame is marked with an EOF character, which is always a 0xC1. The frame structure described here is used for all versions of IrDA protocols used for serial wire replacement for speeds up to 115.2 kbaud. Note 1: The MCP2140 only supports communication baud rate of 9600 baud. 2: Another IrDA standard that is entering into general usage is IR Object Exchange (IrOBEX). This standard is not used for serial connection emulation. 3: IrDA communication standards faster than 115.2 kbaud use a different CRC method and physical layer. FIGURE B-3: IrDA STANDARD PROTOCOL LAYERS Host O.S. or Application IrCOMM IrLMP – IAS Protocols resident in MCP2140 IrLAP IR pulses transmitted and received IrPHY FIGURE B-4: IrLAP FRAME X BOFs BOF A C I FCS EOF 2 (1+N) of C0h payload bytes C1h In addition to defining the frame structure, IrLAP provides the “housekeeping” functions of opening, closing and maintaining connections. The critical parameters that determine the performance of the link are part of this function. These parameters control how many BOFs are used, identify the speed of the link, how fast either party may change from receiving to transmitting, etc. IrLAP has the responsibility of negotiating these parameters to the highest common set so that both sides can communicate as quickly and reliably as possible.  2003 Microchip Technology Inc. Preliminary DS21790A-page 47 MCP2140 B.1.3 IrLMP B.1.4 The IrLMP protocol provides: • Multiplexing of the IrLAP layer. This allows multiple channels above an IrLAP connection. • Protocol and service discovery. This is accomplished via the Information Access Service (IAS). When two devices that contain the IrDA standard feature are connected, there is generally one device that has something to do and the other device that has the resource to do it. For example, a laptop may have a job to print and an IrDA standard compatible printer has the resources to print it. In IrDA standard terminology, the laptop is a Primary device and the printer is the Secondary device. When these two devices connect, the Primary device must determine the capabilities of the Secondary device to determine if the Secondary device is capable of doing the job. This determination is made by the Primary device asking the Secondary device a series of questions. Depending on the answers to these questions, the Primary device may or may not elect to connect to the Secondary device. The queries from the Primary device are carried to the Secondary device using IrLMP. The responses to these queries can be found in the Information Access Service (IAS) of the Secondary device. The IAS is a list of the resources of the Secondary device. The Primary device compares the IAS responses with its requirements and then makes the decision if a connection should be made. LINK MANAGEMENT INFORMATION ACCESS SERVICE (LM-IAS) Each LM-IAS entity maintains an information database to provide: • Information on services for other devices that contain the IrDA standard feature (Discovery) • Information on services for the device itself • Remote accessing of another device’s information base This is required so that clients on a remote device can find configuration information needed to access a service. B.1.5 TINY TP Tiny TP provides the flow control on IrLMP connections. An optional service of Segmentation and Reassembly can be handled. B.1.6 IRCOMM IrCOMM provides the method to support serial and parallel port emulation. This is useful for legacy COM applications, such as printers and modem devices. The IrCOMM standard is a syntax that allows the Primary device to consider the Secondary device a serial device. IrCOMM allows for emulation of serial or parallel (printer) connections of various capabilities. Note: The MCP2140 supports the 9-wire “cooked” service class of IrCOMM. Other service classes supported by IrCOMM are shown in Figure B-5. FIGURE B-5: IRCOMM SERVICE CLASSES IrCOMM Services Uncooked Services Cooked Services Serial 3-wire Raw Parallel Centronics IEEE 1284 Serial 3-wire Cooked 9-wire Cooked Parallel IrLPT Supported by M CP2140 DS21790A-page 48 Preliminary  2003 Microchip Technology Inc. MCP2140 B.1.7 OTHER OPTIONAL IrDA DATA PROTOCOLS Other IrDA data protocols have been developed to specific application requirements. These IrDA data protocols are briefly described in the following subsections. For additional information, please refer to the IrDA web site (www.IrDA.org). B.1.7.1 IrTran-P IrTran-P provides the protocol to exchange images with digital image capture devices/cameras. Note: Not supported by MCP2140. B.1.7.2 IrOBEX IrOBEX provides OBject EXchange services. This is similar to HTTP. Note: Not supported by MCP2140. B.1.7.3 IrLAN IrLAN describes a protocol to support IR wireless access to a Local Area Network (LAN). Note: Not supported by MCP2140. B.1.7.4 IrMC IrMC describes how mobile telephony and communication devices can exchange information. This information includes phone book, calender and message data. Also how call control and real-time voice are handled (RTCON). Note: Not supported by MCP2140. B.1.7.5 IrDA Lite IrDA Lite describes how to reduce the application code requirements, while maintaining compatibility with the full implementation. Note: Not supported by MCP2140.  2003 Microchip Technology Inc. Preliminary DS21790A-page 49 MCP2140 APPENDIX C: HOW DEVICES CONNECT tant (PDA), the PDA that supports the IrDA standard feature would be the Primary device and the cell phone would be the Secondary device. When a Primary device polls for another device, a nearby Secondary device may respond. When a Secondary device responds, the two devices are defined to be in the Normal Disconnect Mode (NDM) state. NDM is established by the Primary device broadcasting a packet and waiting for a response. These broadcast packets are numbered. Usually 6 or 8 packets are sent. The first packet is number 0, the last packet is usually number 5 or 7. Once all the packets are sent, the Primary device sends an ID packet, which is not numbered. The Secondary device waits for these packets and then responds to one of the packets. The packet responds to determines the “timeslot” to be used by the Secondary device. For example, if the Secondary device responds after packet number 2, then the Secondary device will use timeslot 2. If the Secondary device responds after packet number 0, then the Secondary device will use timeslot 0. This mechanism allows the Primary device to recognize as many nearby devices as there are timeslots. The Primary device will continue to generate timeslots and the Secondary device should continue to respond, even if there’s nothing to do. Note 1: The MCP2140 can only be used to implement a Secondary device. 2: The MCP2140 supports a system with only one Secondary device having exclusive use of the IrDA standard infrared link (known as “point-to-point” communication). 3: The MCP2140 always responds to packet number 2. This means that the MCP2140 will always use timeslot 2. 4: If another Secondary device is nearby, the Primary device may fail to recognize the MCP2140, or the Primary device may not recognize either of the devices. When two devices implementing the IrDA standard feature establish a connection using the IrCOMM protocol, the process is analogous to connecting two devices with serial ports using a cable. This is referred to as a “point-to-point” connection. This connection is limited to half-duplex operation because the IR transceiver cannot transmit and receive at the same time. The purpose of the IrDA protocols is to allow this half-duplex link to emulate, as much as possible, a full-duplex connection. In general, this is done by dividing the data into “packets”, or groups of data. These packets can then be sent back and forth, when needed, without risk of collision. The rules of how and when these packets are sent constitute the IrDA protocols. When a wired connection is used, the assumption is made that both sides have the same communications parameters and features. A wired connection has no need to identify the other connector because it is assumed that the connectors are properly connected. In the IrDA standard, a connection process has been defined to identify other IrDA compatible devices and establish a communication link. There are three steps that these two devices go through to make this connection. They are: • Normal Disconnect Mode (NDM) • Discovery Mode • Normal Connect Mode (NCM) Figure C-1 shows the connection sequence. C.1 Normal Disconnect Mode (NDM) When two IrDA standard compatible devices come into range they must first recognize each other. The basis of this process is that one device has some task to accomplish and the other device has a resource needed to accomplish this task. One device is referred to as a Primary device and the other is referred to as a Secondary device. This distinction between Primary device and Secondary device is important. It is the responsibility of the Primary device to provide the mechanism to recognize other devices. So the Primary device must first poll for nearby IrDA standard compatible devices. During this polling, the default baud rate of 9600 baud is used by both devices. For example, if you want to print from an IrDA equipped laptop to an IrDA printer, utilizing the IrDA standard feature, you would first bring your laptop in range of the printer. In this case, the laptop is the one that has something to do and the printer has the resource to do it. The laptop is called the Primary device and the printer is the Secondary device. Some data-capable cell phones have IrDA standard infrared ports. If you used such a cell phone with a Personal Digital Assis- DS21790A-page 50 Preliminary  2003 Microchip Technology Inc. MCP2140 C.2 Discovery Mode C.3 Normal Connect Mode (NCM) Discovery mode allows the Primary device to determine the capabilities of the MCP2140 (Secondary device). Discovery mode is entered once the MCP2140 (Secondary device) has sent an XID response to the Primary device and the Primary device has completed sending the XIDs and then sends a Broadcast ID. If this sequence is not completed, then a Primary and Secondary device can stay in NDM indefinitely. When the Primary device has something to do, it initiates Discovery. Discovery has two parts. They are: • Link initialization • Resource determination The first step is for the Primary and Secondary devices to determine, and then adjust to, each other’s hardware capabilities. These capabilities are parameters like: • • • • Data rate Turn around time Number of packets without a response How long to wait before disconnecting Once discovery has been completed, the Primary device and Secondary device can freely exchange data. Both the Primary device and the Secondary device check to make sure that data packets are received by the other without errors. Even when data is required to be sent, the Primary and Secondary devices will still exchange packets to ensure that the connection hasn’t, unexpectedly, been dropped. When the Primary device has finished, it then transmits the close link command to the Secondary device. The Secondary device will confirm the close link command and both the Primary device and the Secondary device will revert to the NDM state. Note: If the NCM mode is unexpectedly terminated for any reason (including the Primary device not issuing a close link command), the Secondary device will revert to the NDM state after a time delay (after the last frame has been received). Both the Primary and Secondary device begin communications at 9600 baud, which is the default baud rate. The Primary device sends its parameters, then the Secondary device responds with its parameters. For example, if the Primary supports all data rates up to 115.2 kbaud and the Secondary device only supports 9.6 kbaud, the link will be established at 9.6 kbaud. Note: The MCP2140 is limited to a data rate of 9.6 kbaud. Once the hardware parameters are established, the Primary device must determine if the Secondary device has the resources it requires. If the Primary device has a job to print, then it must know if it’s talking to a printer, not a modem or other device. This determination is made using the Information Access Service (IAS). The job of the Secondary device is to respond to IAS queries made by the Primary device. The Primary device must ask a series of questions like: • What is the name of your service? • What is the address of this service? • What are the capabilities of this device? When all the Primary device’s questions are answered, the Primary device can access the service provided by the Secondary device.  2003 Microchip Technology Inc. Preliminary DS21790A-page 51 MCP2140 FIGURE C-1: HIGH LEVEL IRCOMM CONNECTION SEQUENCE Primary Device Normal Disconnect Mode (NDM) Send XID Commands (timeslots n, n+1, ...) (approximately 70ms between XID commands) Secondary Device (MCP2140) No Response Finish sending XIDs (max timeslots - y frames) Broadcast ID XID Response in timeslot y, claiming this timeslot, (MCP2140 always claims timeslot 0) No Response to these XIDs No Response to Broadcast ID Discovery Send SNRM Command (w/ parameters and connection address) UA response with parameters using connect address Open channel for IAS Queries Confirm channel open for IAS Send IAS Queries Provide IAS responses Open channel for data Confirm channel open for data Normal Response Mode (NRM) Send Data or Status Send Data or Status (MCP2140 DSR pin driven low) Send Data or Status Send Data or Status Shutdown link Confirm shutdown (back to NDM state) DS21790A-page 52 Preliminary  2003 Microchip Technology Inc. MCP2140 APPENDIX D: DB-9 PIN INFORMATION APPENDIX E: KNOW PRIMARY DEVICE COMPATIBILITY ISSUES Table D-1 shows the DB-9 pin information and the direction of the MCP2140 signals. The MCP2140 is designed for use in Data Communications Equipment (DCE) applications. Table E-1 show the known issues of Primary Devices interfacing to the MCP2140. TABLE D-1: DB-9 Signal Pin No. 1 2 3 4 5 6 7 8 9 CD RX TX DTR GND DSR RTS CTS RI DB-9 SIGNAL INFORMATION Direction HC → MCP2140 MCP2140 → HC HC → MCP2140 HC → MCP2140 — MCP2140 → HC HC → MCP2140 MCP2140 → HC HC → MCP2140 Comment Carrier Detect Received Data Transmit Data Data Terminal Ready Ground Data Set Ready Request to Send Clear to Send Ring Indicator Legend: HC = Host Controller TABLE E-1: Primary Device HP Jornada 720 PRIMARY DEVICE ISSUES Operating System Issue Result HPC Pro/Windows CE™ 3.0 Jornada 720 transmits 0xFF (not MCP2140 will not connect (Pocket PC) 0xC0) for extra SOF (Start-of- to the Jornada 720. Frame) characters during NDM. Personal Computers Windows® 2000 (do not have The operating system will reset if MCP2140 will not connect list of which versions) an IR device ID of “null” is to the PC received.  2003 Microchip Technology Inc. Preliminary DS21790A-page 53 MCP2140 NOTES: DS21790A-page 54 Preliminary  2003 Microchip Technology Inc. MCP2140 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device MCP2140: Infrared Communications Controller MCP2140T: Infrared Communications Controller (Tape and Reel) I P SO SS = = = = -40°C to +85°C Plastic DIP (300 mil, Body), 18-lead Plastic SOIC (300 mil, Body), 18-lead Plastic SSOP (209 mil, Body), 20-lead MCP2140-I/P = Industrial Temp., PDIP packaging MCP2140-I/SO = Industrial Temp., SOIC package MCP2140T-I/SS = Tape and Reel, Industrial Temp., SSOP package c) Temperature Range Package Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products.  2003 Microchip Technology Inc. Preliminary DS21790A-page 55 MCP2140 NOTES: DS21790A-page 56 Preliminary  2003 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, KEELOQ, MPLAB, PIC, PICmicro, PICSTART, PRO MATE and PowerSmart are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, microID , MXDEV, MXLAB, PICMASTER, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Accuron, Application Maestro, dsPIC, dsPICDEM, dsPICDEM.net, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, PICC, PICkit, PICDEM, PICDEM.net, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPIC, Select Mode, SmartSensor, SmartShunt, SmartTel and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2003, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received QS-9000 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona in July 1999 and Mountain View, California in March 2002. The Company’s quality system processes and procedures are QS-9000 compliant for its PICmicro ® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, non-volatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001 certified.  2003 Microchip Technology Inc. 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B505A, Fullhope Plaza, No. 12 Hong Kong Central Rd. Qingdao 266071, China Tel: 86-532-5027355 Fax: 86-532-5027205 Italy Microchip Technology SRL Via Quasimodo, 12 20025 Legnano (MI) Milan, Italy Tel: 39-0331-742611 Fax: 39-0331-466781 India Microchip Technology Inc. India Liaison Office Marketing Support Division Divyasree Chambers 1 Floor, Wing A (A3/A4) No. 11, O’Shaugnessey Road Bangalore, 560 025, India Tel: 91-80-2290061 Fax: 91-80-2290062 United Kingdom Microchip Ltd. 505 Eskdale Road Winnersh Triangle Wokingham Berkshire, England RG41 5TU Tel: 44 118 921 5869 Fax: 44-118 921-5820 03/25/03 DS21790A-page 58 Preliminary  2003 Microchip Technology Inc.