MCP3202_08

MCP3202 2.7V Dual Channel 12-Bit A/D Converter with SPI Serial Interface Features • • • • • • • • • • • • • • • 12-Bit resolution ±1 LSB maximum DNL ±1 LSB maximum INL (MCP3202-B) ±2 LSB maximum INL (MCP3202-C) Analog inputs programmable as single-ended or pseudo-differential pairs On-chip sample and hold SPI serial interface (modes 0,0 and 1,1) Single supply operation: 2.7V-5.5V 100 ksps maximum sampling rate at VDD = 5V 50 ksps maximum sampling rate at VDD = 2.7V Low power CMOS technology 500 nA typical standby current, 5 µA maximum 550 µA maximum active current at 5V Industrial temp range: -40°C to +85°C 8-pin MSOP, PDIP, SOIC and TSSOP packages Description The Microchip Technology Inc. MCP3202 is a successive approximation 12-bit Analog-to-Digital (A/D) Converter with on-board sample and hold circuitry. The MCP3202 is programmable to provide a single pseudo-differential input pair or dual singleended inputs. Differential Nonlinearity (DNL) is specified at ±1 LSB, and Integral Nonlinearity (INL) is offered in ±1 LSB (MCP3202-B) and ±2 LSB (MCP3202-C) versions. Communication with the device is done using a simple serial interface compatible with the SPI protocol. The device is capable of conversion rates of up to 100 ksps at 5V and 50 ksps at 2.7V. The MCP3202 device operates over a broad voltage range (2.7V - 5.5V). Low-current design permits operation with typical standby and active currents of only 500 nA and 375 µA, respectively. The MCP3202 is offered in 8-pin MSOP, PDIP, TSSOP and 150 mil SOIC packages. Applications • • • • Sensor Interface Process Control Data Acquisition Battery Operated Systems Package Types PDIP, MSOP, SOIC, TSSOP CS/SHDN CH0 CH1 VSS VDD VSS 1 2 3 4 8 7 6 5 VDD/VREF CLK DOUT DIN MCP3202 Functional Block Diagram CH0 CH1 Input Channel Mux DAC Comparator Sample and Hold Control Logic CS/SHDN DIN CLK 12-Bit SAR Shift Register DOUT © 2008 Microchip Technology Inc. DS21034E-page 1 MCP3202 NOTES: DS21034E-page 2 © 2008 Microchip Technology Inc. MCP3202 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD – VSS ........................................................................7.0V All Inputs and Outputs w.r.t. VSS ............– 0.6V to VDD + 0.6V Storage Temperature ................................... –65°C to +150°C Ambient temperature with power applied.......–65°C to +150°C Maximum Junction Temperature (TJ)......................... .+150°C ESD Protection On All Pins (HBM) ...................................≥ 4 kV ELECTRICAL CHARACTERISTICS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE. Parameter Conversion Rate: Conversion Time Analog Input Sample Time Sym tCONV tSAMPLE Min. — Typ. — 1.5 Max. 12 Units clock cycles clock cycles ksps ksps bits LSB LSB LSB LSB LSB dB dB dB V See Sections 3.1 and 4.1 mV μA Ω pF See Sections 3.1 and 4.1 VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VIN = 0.1V to 4.9V@1 kHz VDD = VREF = 5V VDD = VREF = 2.7V Conditions Throughput Rate DC Accuracy: Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Dynamic Performance: Total Harmonic Distortion Signal-to-Noise and Distortion (SINAD) Spurious Free Dynamic Range Analog Inputs: Input Voltage Range for CH0 or CH1 in Single-Ended Mode Input Voltage Range for IN+ in Pseudo-Differential Mode Input Voltage Range for IN- in Pseudo-Differential Mode Leakage Current Switch Resistance Sample Capacitor Digital Input/Output: Data Coding Format High Level Input Voltage Low Level Input Voltage fSAMPL — — — — 12 ±0.75 ±1 ±0.5 ±1.25 ±1.25 -82 72 86 — — — .001 1k 20 100 50 INL DNL — — — — — ±1 ±2 ±1 ±3 ±5 — — — VDD VDD+INVSS+100 ±1 — — MCP3202-B MCP3202-C No missing codes over temperature THD SINAD SFDR — — — VSS IN+ IN- INVSS-100 — — — RSS CSAMPLE See Figure 4-1 See Figure 4-1 VIH VIL Straight Binary 0.7 VDD — — — — 0.3 VDD V V Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information. © 2008 Microchip Technology Inc. DS21034E-page 3 MCP3202 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5.5V, VSS = 0V, TA = -40°C to +85°C, fSAMPLE = 100 ksps and fCLK = 18*fSAMPLE. Parameter High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance (All Inputs/Outputs) Timing Parameters: Clock Frequency Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data Input Setup Time Data Input Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Power Requirements: Operating Voltage Operating Current Standby Current Sym VOH VOL ILI ILO CIN, COUT Min. 4.1 — -10 -10 — Typ. — — — — — Max. — 0.4 10 10 10 Units V V µA µA pF Conditions IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD VDD = 5.0V (Note 1) TA = +25°C, f = 1 MHz VDD = 5V (Note 2) VDD = 2.7V (Note 2) fCLK tHI tLO tSUCS tSU tHD tDO tEN tDIS tCSH tR tF — — — — — — — — — — — — — 100 50 50 — — — 500 — — 1.8 0.9 2 2 — — — 200 200 100 — 100 100 MHz MHz MHz MHz ns ns ns ns ns ns ns ns ns See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 See Test Circuits, Figure 1-2 Note 1 VDD IDD IDDS 2.7 — — — 375 0.5 5.5 550 5 V µA µA VDD = 5.0V, DOUT unloaded CS = VDD = 5.0V Note 1: This parameter is established by characterization and not 100% tested. 2: Because the sample cap will eventually lose charge, effective clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. See Section 6.2 “Maintaining Minimum Clock Speed” for more information. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Thermal Resistance, 8L-TSSOP θJA θJA θJA θJA — — — — 211 89.5 149.5 139 — — — — °C/W °C/W °C/W °C/W TA TA TA -40 -40 -65 — — — +85 +85 +150 °C °C °C Sym Min Typ Max Units Conditions DS21034E-page 4 © 2008 Microchip Technology Inc. MCP3202 tCSH CS tSUCS tHI tLO CLK tSU DIN tHD tR MSB OUT MSB IN tEN tDO NULL BIT tF LSB tDIS DOUT FIGURE 1-1: Serial Timing. Load circuit for tDIS and tEN Test Point VDD 3 kΩ Test Point DOUT CL = 100 pF 3 kΩ 100 pF VSS VDD /2 tDIS Waveform 2 tEN Waveform tDIS Waveform 1 Load circuit for tR, tF, tDO 1.4V DOUT Voltage Waveforms for tR, tF DOUT tR tF VOH VOL Voltage Waveforms for tEN CS CLK DOUT tEN 1 2 3 4 B11 Voltage Waveforms for tDO CLK tDO DOUT Voltage Waveforms for tDIS CS DOUT Waveform 1* TDIS DOUT Waveform 2† 10% VIH 90% * Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. † Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-2: Test Circuits. © 2008 Microchip Technology Inc. DS21034E-page 5 MCP3202 NOTES: DS21034E-page 6 © 2008 Microchip Technology Inc. MCP3202 2.0 Note: TYPICAL PERFORMANCE CHARACTERISTICS The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 2.0 Positive INL 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 50 75 100 125 150 Negative INL 1.5 1.0 VDD = 2.7V Positive INL INL (LSB) INL (LSB) 0.5 0.0 -0.5 -1.0 -1.5 -2.0 0 20 40 60 80 100 Negative INL Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-1: vs. Sample Rate. Integral Nonlinearity (INL) FIGURE 2-4: Integral Nonlinearity (INL) vs. Sample Rate (VDD = 2.7V). 1.0 1.0 0.8 0.6 Positive INL fSAMPLE = 100 ksps 0.8 0.6 0.4 fSAMPLE = 50 ksps Positive INL INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.5 4.0 4.5 5.0 Negative INL INL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 2.5 3.0 3.5 4.0 4.5 5.0 Negative INL VDD(V) VDD(V) FIGURE 2-2: vs. VDD. 1.0 0.8 0.6 0.4 Integral Nonlinearity (INL) FIGURE 2-5: vs. VDD. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 VDD = 2.7V FSAMPLE = 50 ksps Integral Nonlinearity (INL) INL (LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 INL (LSB) 0 512 1024 1536 2048 2560 3072 3584 4096 Digital Code Digital Code FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: Integral Nonlinearity (INL) vs. Code (Representative Part, VDD = 2.7V). © 2008 Microchip Technology Inc. DS21034E-page 7 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL Positive INL 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative INL VDD = 2.7V fSAMPLE = 50 ksps Positive INL INL (LSB) INL (LSB) Temperature (°C) Temperature (°C) FIGURE 2-7: vs. Temperature. 1.0 0.8 0.6 Integral Nonlinearity (INL) FIGURE 2-10: Integral Nonlinearity (INL) vs. Temperature (VDD = 2.7V). 2.0 1.5 DNL (LSB) VDD = 2.7V DNL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 25 Positive DNL 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 Negative DNL Positive DNL Negative DNL 50 75 100 125 150 0 20 40 60 80 100 Sample Rate (ksps) Sample Rate (ksps) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Sample Rate. FIGURE 2-11: Differential Nonlinearity (DNL) vs. Sample Rate (VDD = 2.7V). 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 Negative DNL Positive DNL fSAMPLE = 50 ksps 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 3.0 3.5 4.0 Negative DNL Positive DNL fSAMPLE = 100 ksps DNL (LSB) 4.5 5.0 DNL (LSB) 2.5 3.0 3.5 4.0 4.5 5.0 VDD(V) VDD(V) FIGURE 2-9: (DNL) vs. VDD. Differential Nonlinearity FIGURE 2-12: (DNL) vs. VDD. Differential Nonlinearity DS21034E-page 8 © 2008 Microchip Technology Inc. MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 VDD = 2.7V fSAMPLE = 50 ksps DNL (LSB) Digital Code DNL (LSB) Digital Code FIGURE 2-13: Differential Nonlinearity (DNL) vs. Code (Representative Part). FIGURE 2-16: Differential Nonlinearity (DNL) vs. Code (Representative Part, VDD = 2.7V). 1.0 0.8 0.6 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 Negative DNL Positive DNL VDD = 2.7V fSAMPLE = 50 ksps DNL (LSB) DNL (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 Positive DNL Negative DNL 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-14: Differential Nonlinearity (DNL) vs. Temperature. 2.0 1.5 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 2.5 3.0 3.5 fSAMPLE = 100 ksps fSAMPLE = 50 ksps FIGURE 2-17: Differential Nonlinearity (DNL) vs. Temperature (VDD = 2.7V). 2.0 1.8 Offset Error (LSB) Gain Error (LSB) fSAMPLE = 10 ksps 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 fSAMPLE = 100 ksps fSAMPLE = 50 ksps fSAMPLE = 10 ksps 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0 VDD(V) VDD(V) FIGURE 2-15: Gain Error vs. VDD. FIGURE 2-18: Offset Error vs. VDD. © 2008 Microchip Technology Inc. DS21034E-page 9 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 VDD = 5V fSAMPLE = 100 2.0 Offset Error (LSB) Gain Error (LSB) VDD = 2.7V fSAMPLE = 50 ksps 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 VDD = 5V fSAMPLE = 100 ksps VDD = 2.7V fSAMPLE = 50 ksps 50 75 -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-19: Gain Error vs. Temperature. FIGURE 2-22: Temperature. 100 Offset Error vs. 100 90 80 70 60 50 40 30 20 10 0 1 10 VDD = 2.7V fSAMPLE = 50 ksps VDD = 5V fSAMPLE = 100 ksps 90 80 VDD = 5V fSAMPLE = 100 ksps SINAD (dB) SNR (dB) 70 60 50 40 30 20 10 0 VDD = 2.7V fSAMPLE = 50 ksps 100 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-20: Signal-to-Noise Ratio (SNR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 1 FIGURE 2-23: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. 80 70 VDD = 5V f SAMPLE = 100 ksps SINAD (dB) 60 50 40 30 20 10 0 VDD = 2.7V f SAMPLE = 50 ksps THD (dB) VDD = 2.7V fSAMPLE = 50 ksps VDD = 5V fSAMPLE = 100 ksps 10 100 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-21: Total Harmonic Distortion (THD) vs. Input Frequency. FIGURE 2-24: Signal-to-Noise and Distortion (SINAD) vs. Signal Level. DS21034E-page 10 © 2008 Microchip Technology Inc. MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 12.0 11.5 12.0 fSAMPLE = 50ksps V DD = 5V FSAMPLE = 100 ksps 11.5 11.0 ENOB (rms) 11.0 10.5 10.0 9.5 9.0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 fSAMPLE = 100 ksps ENOB (rms) 10.5 10.0 9.5 9.0 8.5 8.0 1 10 100 V DD = 2.7V FSAMPLE = 50 ksps VDD (V) Input Frequency (kHz) FIGURE 2-25: (ENOB) vs. VDD. 100 90 80 70 60 50 40 30 20 10 0 1 Effective Number of Bits FIGURE 2-28: Effective Number of Bits (ENOB) vs. Input Frequency. 0 Power Supply Rejection (dB) VDD = 5V fSAMPLE = 100 ksps -10 -20 -30 -40 -50 -60 -70 -80 1 10 100 1000 10000 SFDR (dB) VDD = 2.7V fSAMPLE = 50 ksps 10 100 Input Frequency (kHz) R ipple Frequency (kHz) FIGURE 2-26: Spurious Free Dynamic Range (SFDR) vs. Input Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 10000 20000 FIGURE 2-29: Power Supply Rejection (PSR) vs. Ripple Frequency. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 0 5000 10000 VDD = 5V VDD = 2.7V fSAMPLE = 50 ksps fINPUT = 998.76 Hz 4096 points Amplitude (dB) fINPUT = 9.985 kHz 4096 points 30000 40000 50000 Amplitude (dB) fSAMPLE = 100 ksps 15000 20000 25000 Frequency (Hz) Frequency (Hz) FIGURE 2-27: Frequency Spectrum of 10 kHz input (Representative Part). FIGURE 2-30: Frequency Spectrum of 1 kHz input (Representative Part, VDD = 2.7V). © 2008 Microchip Technology Inc. DS21034E-page 11 MCP3202 Note: Unless otherwise indicated, VDD = 5V, VSS = 0V, fSAMPLE = 100 ksps, fCLK = 18* fSAMPLE, TA = +25°C. 500 450 400 350 250 200 150 100 50 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 300 80 70 60 CS = VDD All points at FCLK = 1.8 MHz except at VDD = 2.5V, FCLK = 900 kHz IDDS (pA) IDD (µA) 50 40 30 20 10 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 VDD (V) VDD (V) FIGURE 2-31: 500 450 400 350 300 250 200 150 100 50 0 10 V DD = 2.7V V DD = 5V IDD vs. VDD. FIGURE 2-34: IDDS vs. VDD. 100.00 VDD =CS =5V 10.00 IDDS (nA) IDD (µA) 1.00 0.10 0.01 -50 - 25 0 25 50 75 100 100 1000 10000 Tem perature (°C) Clock Frequency (kHz) FIGURE 2-32: 500 IDD vs. Clock Frequency. FIGURE 2-35: 2.0 IDDS vs. Temperature. Analog Input Leakage (nA) 450 400 350 300 250 200 150 100 50 0 VDD = 5V FCLK = 1.8 MHz 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 -50 -25 0 25 50 75 100 VDD = 5V FCLK = 1.8 MHz IDD (µA) V DD = 2.7V FCLK = 900 kHz -50 -25 0 25 50 75 100 Temperature (°C) Temperature (°C) FIGURE 2-33: IDD vs. Temperature. FIGURE 2-36: Analog Input leakage current vs. Temperature. DS21034E-page 12 © 2008 Microchip Technology Inc. MCP3202 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3.1. Additional descriptions of the device pins follows. TABLE 3-1: MCP3202 PIN FUNCTION TABLE Symbol CS/SHDN CH0 CH1 VSS DIN DOUT CLK VDD/VREF Description Chip Select/Shutdown Input Channel 0 Analog Input Channel 1 Analog Input Ground Serial Data In Serial Data Out Serial Clock +2.7V to 5.5V Power Supply and Reference Voltage Input MSOP, PDIP, SOIC, TSSOP 1 2 3 4 5 6 7 8 3.1 Analog Inputs (CH0/CH1) 3.3 Serial Clock (CLK) Analog inputs for channels 0 and 1 respectively. These channels can be programmed to be used as two independent channels in single ended-mode or as a single pseudo-differential input where one channel is IN+ and one channel is IN–. See Section 5.0 “Serial Communications” for information on programming the channel configuration. The SPI clock pin is used to initiate a conversion and to clock out each bit of the conversion as it takes place. See Section 6.2 “Maintaining Minimum Clock Speed” for constraints on clock speed. 3.4 Serial Data Input (DIN) 3.2 Chip Select/Shutdown (CS/SHDN) The SPI port serial data input pin is used to clock in input channel configuration data. The CS/SHDN pin is used to initiate communication with the device when pulled low and will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions. 3.5 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. © 2008 Microchip Technology Inc. DS21034E-page 13 MCP3202 NOTES: DS21034E-page 14 © 2008 Microchip Technology Inc. MCP3202 4.0 DEVICE OPERATION 4.2 Digital Output Code The MCP3202 A/D Converter employs a conventional SAR architecture. With this architecture, a sample is acquired on an internal sample/hold capacitor for 1.5 clock cycles starting on the second rising edge of the serial clock after the start bit has been received. Following this sample time, the input switch of the converter opens and the device uses the collected charge on the internal sample and hold capacitor to produce a serial 12-bit digital output code. Conversion rates of 100 ksps are possible on the MCP3202. See Section 6.2 “Maintaining Minimum Clock Speed” for information on minimum clock rates. Communication with the device is done using a 3-wire SPI-compatible interface. The digital output code produced by an A/D Converter is a function of the input signal and the reference voltage. For the MCP3202, VDD is used as the reference voltage. As the VDD level is reduced, the LSB size is reduced accordingly. The theoretical digital output code produced by the A/D Converter is shown below. EQUATION 4-1: 4096•V IN Digital Output Code = ---------------------V DD where: VIN = = analog input voltage supply voltage 4.1 Analog Inputs VDD The MCP3202 device offers the choice of using the analog input channels configured as two singleended inputs or a single pseudo-differential input. Configuration is done as part of the serial command before each conversion begins. When used in the pseudo-differential mode, CH0 and CH1 are programmed as the IN+ and IN– inputs as part of the command string transmitted to the device. The IN+ input can range from IN– to VREF (VDD + IN–). The IN– input is limited to ±100 mV from the VSS rail. The IN– input can be used to cancel small signal common-mode noise which is present on both the IN+ and IN– inputs. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 12-bit accurate voltage level during the 1.5 clock cycle sampling period. The analog input model is shown in Figure 4-1. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor, CSAMPLE. Consequently, larger source impedances increase the offset, gain, and integral linearity errors of the conversion. Ideally, the impedance of the signal source should be near zero. This is achievable with an operational amplifier such as the MCP601 which has a closed loop output impedance of tens of ohms. The adverse affects of higher source impedances are shown in Figure 4-2. When operating in the pseudo-differential mode, if the voltage level of IN+ is equal to or less than IN–, the resultant code will be 000h. If the voltage at IN+ is equal to or greater than {[VDD + (IN–)] – 1 LSB}, then the output code will be FFFh. If the voltage level at IN– is more than 1 LSB below VSS, then the voltage level at the IN+ input will have to go below VSS to see the 000h output code. Conversely, if IN- is more than 1 LSB above VSS, then the FFFh code will not be seen unless the IN+ input level goes above VDD level. © 2008 Microchip Technology Inc. DS21034E-page 15 MCP3202 VDD RSS CHx VT = 0.6V Sampling Switch SS RS = 1 kW CSAMPLE = DAC capacitance = 20 pF VSS Legend VA RSS CHx CPIN VT ILEAKAGE SS RS CSAMPLE = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance VA CPIN 7 pF VT= 0.6V ILEAKAGE ±1 nA FIGURE 4-1: 2.0 Analog Input Model. Clock Frequency (MHz) 1.8 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0.0 100 1000 V DD = 2.7V VDD = 5V 10000 Input Resistance (Ohms) FIGURE 4-2: Maximum Clock Frequency vs. Input Resistance (RS) to maintain less than a 0.1 LSB deviation in INL from nominal conditions. DS21034E-page 16 © 2008 Microchip Technology Inc. MCP3202 5.0 5.1 SERIAL COMMUNICATIONS Overview Communication with the MCP3202 is done using a standard SPI-compatible serial interface. Initiating communication with the device is done by bringing the CS line low. See Figure 5-1. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit and the ODD/SIGN bit follow the start bit and are used to select the input channel configuration. The SGL/DIFF is used to select single ended or psuedo-differential mode. The ODD/SIGN bit selects which channel is used in single ended mode, and is used to determine polarity in pseudo-differential mode. Following the ODD/SIGN bit, the MSBF bit is transmitted to and is used to enable the LSB first format for the device. If the MSBF bit is high, then the data will come from the device in MSB first format and any further clocks with CS low will cause the device to output zeros. If the MSBF bit is low, then the device will output the converted word LSB first after the word has been transmitted in the MSB first format. See Figure 5-2. Table 5-1 shows the configuration bits for the MCP3202. The device will begin to sample the analog input on the second rising edge of the clock, after the start bit has been received. The sample period will end on the falling edge of the third clock following the start bit. On the falling edge of the clock for the MSBF bit, the device will output a low null bit. The next sequential 12 clocks will output the result of the conversion with MSB first as shown in Figure 5-1. Data is always output from the device on the falling edge of the clock. If all 12 data bits have been transmitted and the device continues to receive clocks while the CS is held low, (and MSBF = 1), the device will output the conversion result LSB first as shown in Figure 5-2. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.1 “Using the MCP3202 with Microcontroller (MCU) SPI Ports” for more details on using the MCP3202 devices with hardware SPI ports. TABLE 5-1: CONFIGURATION BITS FOR THE MCP3202 Config Bits SGL/ ODD/ DIFF SIGN Channel Selection 0 + — IN+ IN1 — + ININ+ GND Single Ended Mode PseudoDifferential Mode 1 1 0 0 0 1 0 1 tCYC tCSH CS tSUCS CLK tCYC DIN Start SGL/ ODD/ MS DIFF SIGN BF Don’t Care Start SGL/ ODD/ DIFF SIGN DOUT HI-Z Null Bit B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0* tCONV tSAMPLE tDATA** HI-Z * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. See Figure 5-2 below for details on obtaining LSB first data. ** tDATA: during this time, the bias current and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 5-1: Communication with the MCP3202 using MSB first format only. © 2008 Microchip Technology Inc. DS21034E-page 17 MCP3202 tCYC CS tSUCS CLK Power Down tCSH Start DIN SGL/ DIFF ODD/ SIGN MSBF Don’t Care DOUT HI-Z tSAMPLE Null B11 B10 B9 Bit B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 * HI-Z (MSB) tCONV tDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** tDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. FIGURE 5-2: Communication with MCP3202 using LSB first format. DS21034E-page 18 © 2008 Microchip Technology Inc. MCP3202 6.0 6.1 APPLICATIONS INFORMATION Using the MCP3202 with Microcontroller (MCU) SPI Ports 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-2 shows the similar case of SPI Mode 1,1 where the clock idles in the ‘high’ state. As shown in Figure 6-1, the first byte transmitted to the A/D Converter contains seven leading zeros before the start bit. Arranging the leading zeros this way produces the output 12 bits to fall in positions easily manipulated by the MCU. The MSB is clocked out of the A/D Converter on the falling edge of clock number 12. After the second eight clocks have been sent to the device, the MCU receive buffer will contain three unknown bits (the output is at high-impedance until the null bit is clocked out), the null bit and the highest order four bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Depending on how communication routines are used, it is very possible that the number of clocks required for communication will not be a multiple of eight. Therefore, it may be necessary for the MCU to send more clocks than are actually required. This is usually done by sending ‘leading zeros’ before the start bit, which are ignored by the device. As an example, Figure 6-1 and Figure 6-2 show how the MCP3202 can be interfaced to a MCU with a hardware SPI port. Figure 6-1 depicts the operation shown in SPI Mode CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN DOUT MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) Start SGL/ DIFF MSBF ODD/ SIGN Don’t Care HI-Z Start Bit NULL B11 BIT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X 1 SGL/ ODD/ MSBF DIFF SIGN X X X X X X X X X X X X X X X X X X X X X X X X 0 B11 (Null) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don’t Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-1: SPI Communication using 8-bit segments (Mode 0,0: SCLK idles low). CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN DOUT MCU Transmitted Data (Aligned with falling edge of clock) MCU Received Data (Aligned with rising edge of clock) 0 0 0 HI-Z Start MSBF ODD/ SIGN SGL/ DIFF Don’t Care Start Bit 0 0 0 0 1 SGL/ ODD/ MSBF DIFF SIGN NULL B11 BIT B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X X X X X X X X X X X X X X X X X X X X X X X X 0 B11 (Null) B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don’t Care Bits Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-2: SPI Communication using 8-bit segments (Mode 1,1: SCLK idles high). © 2008 Microchip Technology Inc. DS21034E-page 19 MCP3202 6.2 Maintaining Minimum Clock Speed 6.4 Layout Considerations When the MCP3202 initiates the sample period, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample cap while the conversion is taking place. At 85°C (worst case condition), the part will maintain proper charge on the sample capacitor for at least 1.2 ms after the sample period has ended. This means that the time between the end of the sample period and the time that all 12 data bits have been clocked out must not exceed 1.2 ms (effective clock frequency of 10 kHz). Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D Converter does not require a constant clock speed or duty cycle, as long as all timing specifications are met. When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board and no traces should run underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors. See Figure 6-4. For more information on layout tips when using A/D Converters, refer to AN688 “Layout Tips for 12-Bit A/D Converter Applications” (DS00688). VDD Connection 6.3 Buffering/Filtering the Analog Inputs If the signal source for the A/D Converter is not a lowimpedance source, it will have to be buffered or inaccurate conversion results may occur. It is also recommended that a filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 6-3 below where an op amp is used to drive the analog input of the MCP3202. This amplifier provides a low-impedance output for the converter input and a low-pass filter, which eliminates unwanted high frequency noise. Low-pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab® software. FilterLab will calculate capacitor and resistor values, as well as, determine the number of poles that are required for the application. For more information on filtering signals, see the application note AN699 “Anti-Aliasing Analog Filters for Data Acquisition Systems”. ” Device 4 Device 1 Device 3 Device 2 VDD 10 µF FIGURE 6-4: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. VIN R1 C1 R2 C2 MCP601 + - 0.1 µF IN+ MCP3202 IN- R3 R4 FIGURE 6-3: The MCP601 Operational Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by the MCP3202. DS21034E-page 20 © 2008 Microchip Technology Inc. MCP3202 7.0 7.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP Example: XXXXXX YWWNNN 3202CI 817256 8-Lead PDIP (300 mil) XXXXXXXX XXXXXNNN YYWW Example: 3202-B e3 I/P^^256 0817 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: 3202-BI e3 SN^^ 0817 256 8-Lead TSSOP Example: XXXX YYWW NNN 202C I817 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( 3 ) e can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2008 Microchip Technology Inc. DS21034E-page 21 MCP3202 /HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 06 >0623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 2 e b A2 c φ A A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F L1 0,//,0(7(56 0,1 120 %6& ± ± ± %6& %6& %6& 5() ƒ ± ± ƒ 0$; L /HDG :LGWK E ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS21034E-page 22 © 2008 Microchip Technology Inc. MCP3202 /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± 1RWH PLO %RG\ >3',3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 D 3 E A A2 A1 L c e b1 b 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ † 1 H $ $ $ ( ( ' / F E E H% ± ± ± %6& ± 0,1 eB ,1&+(6 120 0$; ± ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD † 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % © 2008 Microchip Technology Inc. DS21034E-page 23 MCP3202 /HDG 3ODVWLF 6PDOO 2XWOLQH 61 ± 1DUURZ 1RWH PP %RG\ >62,&@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D e N E E1 NOTE 1 1 2 3 b h φ c h α A A2 A1 L L1 β 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII † 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK &KDPIHU RSWLRQDO )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ ( ( ' K / / I F E D E ƒ ƒ ƒ ± 0,1 0,//,0(7(56 120 %6& ± ± ± %6& %6& %6& ± ± 5() ± ± ± ± ± ƒ ƒ ± 0$; ƒ 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD † 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS21034E-page 24 © 2008 Microchip Technology Inc. MCP3202 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2008 Microchip Technology Inc. DS21034E-page 25 MCP3202 /HDG 3ODVWLF 7KLQ 6KULQN 6PDOO 2XWOLQH 67 ± 1RWH PP %RG\ >76623@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D N E E1 NOTE 1 1 b 2 e c A A2 φ A1 L1 L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F ƒ ± 0,1 0,//,0(7(56 120 %6& ± ± %6& 0$; 5() ± ± ƒ /HDG :LGWK E ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS21034E-page 26 © 2008 Microchip Technology Inc. MCP3202 APPENDIX A: REVISION HISTORY Revision E (December 2008) The following is the list of modifications: 1. Updates to packaging outline drawings. Revision D (December 2006) The following is the list of modifications: 1. Updates to packaging outline drawings. Revision C (August 2001) The following is the list of modifications: 1. Undocumented changes. Revision B (June 2000) The following is the list of modifications: 1. Undocumented changes. Revision A (August 1999) • Initial release of this document. © 2008 Microchip Technology Inc. DS21034E-page 27 MCP3202 NOTES: DS21034E-page 28 © 2008 Microchip Technology Inc. MCP3202 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device -X X /XX Package Examples: a) b) MCP3202-CI/MS: Industrial temperature, 8LD MSOP package. MCP3202-BI/P: B Performance grade, Industrial temperature, 8LD PDIP package MCP3202-BI/SN: C Performance grade, Industrial temperature, 8LD SOIC package MCP3202T-BI/SN: Tape and Reel, B Performance grade, Industrial temperature., 8LD SOIC package MCP3202T-CI/ST: Tape and Reel, C Performance grade, Industrial temperature, 8LD TSSOP package. Performance Temperature Grade Range Device MCP3202: 12-Bit Serial A/d Converter MCP3202T: 12-Bit Serial A/D Converter (Tape and Reel) (MSOP, SOIC and TSSOP package only) = ±1 LSB INL (TSSOP not available) = ±2 LSB INL = -40°C to +85°C = -40°C to +125°C = = = = (Industrial) (Extended) c) Performance Grade: B C Temperature Range I E MS P SN ST d) e) Package Plastic Micro Small Outline (MSOP), 8-Lead Plastic DIP (300 mil Body), 8-Lead Plastic SOIC (150 mil Body), 8-Lead TSSOP (4.4 mm Body), 8-Lead (C Grade only) © 2008 Microchip Technology Inc. DS21034E-page 29 MCP3202 NOTES: DS21034E-page 30 © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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