MCP3301_11

MCP3301 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface Features • • • • • • • • • • • Full Differential Inputs ±1 LSB max DNL ±1 LSB max INL (MCP3301-B) ±2 LSB max INL (MCP3301-C) Single supply operation: 4.5V to 5.5V 100 ksps sampling rate with 5V supply voltage 50 nA typical standby current, 1 µA max 450 µA max active current at 5V Industrial temp range: -40°C to +85°C 8-pin MSOP, PDIP, and SOIC packages Mixed Signal PICtail™ Demo Board (P/N: MXSIGDM) compatible General Description The MCP3301 13-bit A/D converter features full differential inputs and low power consumption in a small package that is ideal for battery-powered systems and remote data acquisition applications. Incorporating a successive approximation architecture with on-board sample and hold circuitry, the 13-bit A/D converter is specified to have ±1 LSB Differential Nonlinearity (DNL) and ±1 LSB Integral Nonlinearity (INL) for B-grade devices and ±2 LSB for C-grade devices. The industry-standard SPI serial interface enables 13bit A/D converter capability to be added to any PIC® microcontroller. The MCP3301 features a low current design that permits operation with typical standby and active currents of only 50 nA and 300 µA, respectively. The device is capable of conversion rates of up to 100 ksps with tested specifications over a 4.5V to 5.5V supply range. The reference voltage can be varied from 400 mV to 5V, yielding input-referred resolution between 98 µV and 1.22 mV. The MCP3301 is available in 8-pin PDIP, 150 mil SOIC, and MSOP packages. The full differential inputs of this device enable a wide variety of signals to be used in applications such as remote data acquisition, portable instrumentation, and battery-operated applications. Applications • Remote Sensors • Battery-operated Systems • Transducer Interface Functional Block Diagram VREF VDD VSS Package Types CDAC IN+ INSample & Hold Circuits MSOP, PDIP, SOIC VREF IN(+) IN(-) VSS 1 2 3 4 8 7 6 5 VDD CLK DOUT CS/SHDN + Comparator 13-Bit SAR MCP3301 Control Logic Shift Register CS/SHDN CLK DOUT  2011 Microchip Technology Inc. DS21700D-page 1 MCP3301 NOTES: DS21700D-page 2  2011 Microchip Technology Inc. MCP3301 1.0 ELECTRICAL CHARACTERISTICS *Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Maximum Ratings* VDD........................................................................ 7.0V All inputs and outputs w.r.t. VSS .....-0.3V to VDD +0.3V Storage temperature .......................... -65°C to +150°C Ambient temp. with power applied ..... -65°C to +125°C Maximum Junction Temperature ....................... 150°C ESD protection on all pins (HBM)   4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 17*FSAMPLE Parameter Conversion Rate Maximum Sampling Frequency Conversion Time Acquisition Time DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Positive Gain Error Negative Gain Error Offset Error Dynamic Performance Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Common-Mode Rejection Power Supply Rejection Note 1: 2: 3: 4: 5: 6: 7: 8: 9: THD SINAD SFDR CMRR PSR — — — — — -91 78 92 79 74 — — — — — dB dB dB dB dB Note 3 Note 3 Note 3 Note 6 Note 4 INL DNL — — — -3 -3 -3 12 data bits + sign ±0.5 ±1 ±0.5 -0.75 -0.5 +3 ±1 ±2 ±1 +2 +2 +6 bits LSB LSB LSB LSB LSB MCP3301-B MCP3301-C Monotonic with no missing codes over temperature Symbol Min Typ Max Units Conditions FSAMPLE tCONV tACQ — — 13 1.5 100 ksps CLK periods CLK periods See FCLK specifications (Note 8) This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD = 5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz MSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance  2011 Microchip Technology Inc. DS21700D-page 3 MCP3301 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 17*FSAMPLE Parameter Reference Input Voltage Range Current Drain Analog Inputs Full-Scale Input Span Absolute Input Voltage IN(+)-IN(-) IN(+) IN(-) Leakage Current Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance Timing Specifications Clock Frequency (Note 8) Clock High Time Clock Low Time CS Fall To First Rising CLK Edge CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Note 1: 2: 3: 4: 5: 6: 7: 8: 9: VIH VIL VOH VOL ILI ILO CIN, COUT Binary Two’s Complement 0.7 VDD — 4.1 — -10 -10 — — — — — — — — — 0.3 VDD — 0.4 10 10 10 V V V V µA µA pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD TAMB = 25°C, f = 1 MHz, Note 1 VDD = 5V, FSAMPLE = 100 ksps Note 5 Note 5 RS CSAMPLE -VREF -0.3 -0.3 — — — — — — 0.001 1 25 VREF VDD + 0.3 VDD + 0.3 ±1 — — V V V µA k pF See Figure 5-3 See Figure 5-3 0.4 — — — 100 0.001 VDD 150 3 V µA µA Note 2 CS = VDD = 5V Symbol Min Typ Max Units Conditions FCLK tHI tLO tSUCS tDO tEN tDIS tCSH tR tF 0.085 275 275 100 — — — 580 — — — — — — — — — — — — 1.7 — — — 125 200 125 200 100 — 100 100 MHz ns ns ns ns ns ns ns ns ns ns ns VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 See test circuits, Figure 1-2; Note 1 See test circuits, Figure 1-2; Note 1 See test circuits, Figure 1-2; Note 1 This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD = 5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz MSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance DS21700D-page 4  2011 Microchip Technology Inc. MCP3301 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TAMB = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 17*FSAMPLE Parameter Power Requirements Operating Voltage Operating Current Standby Current Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistance Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-PDIP Thermal Resistance, 8L-SOIC Note 1: 2: 3: 4: 5: 6: 7: 8: 9: JA JA JA — — — 206 85 163 — — — °C/W °C/W °C/W TA TA TA -40 -40 -65 — — — +85 +85 +150 °C °C °C VDD IDD IDDS 4.5 — — — — 300 200 0.05 5.5 450 — 1 V µA µA Note 9 VDD , VREF = 5V, DOUT unloaded VDD, VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD = 5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz MSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2.1 “Maintaining Minimum Clock Speed” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance . tCSH CS tSUCS tHI CLK tEN HI-Z tDO tR Sign Bit tDIS tF LSB HI-Z tLO DOUT Null Bit FIGURE 1-1: Timing Parameters.  2011 Microchip Technology Inc. DS21700D-page 5 MCP3301 1.1 Test Circuits 1 k 1/2 MCP602 + 5V ±500 mVp-p To VDD on DUT 1.4V MCP3301 DOUT 3 k Test Point 2.63V 20 k 5VP-P 1 k 1 k CL = 100 pF FIGURE 1-2: Test Point Load circuit for tR, tF, tDO. FIGURE 1-4: Power Supply Sensitivity Test Circuit (PSRR). VDD VREF = 5V VDD = 5V 0.1 µF MCP3301 DOUT 3 k 100 pF VDD/2 tDIS Waveform 2 tEN Waveform 5V P-P IN(+) IN(-) 1 µF 0.1 µF VSS tDIS Waveform 1 Voltage Waveforms for tDIS CS 5V P-P VREFVDD MCP3301 VSS VIH 90% TDIS V CM = 2.5V DOUT Waveform 1* FIGURE 1-5: Full Differential Test Configuration Example. DOUT Waveform 2† 10% VREF=2.5V VDD=5V 0.1 µF 0.1 µF 5VP-P VREF DD V MCP3301 IN(-) VSS IN(+) *Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. †Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. 1 µF FIGURE 1-3: Load circuit for TDIS and TEN. VCM=2.5V FIGURE 1-6: Pseudo Differential Test Configuration Example. DS21700D-page 6  2011 Microchip Technology Inc. MCP3301 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 1.0 0.8 0.6 Positive INL 0.4 1.0 0.8 0.6 0.4 Positive INL INL(LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 50 100 150 200 Negative INL INL(LSB) 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 -25 0 25 50 75 100 125 150 Negative INL Sample Rate (ksps) Temperature(°C) FIGURE 2-1: vs. Sample Rate. 2.0 1.5 1.0 Integral Nonlinearity (INL) FIGURE 2-4: vs. Temperature. 1.0 0.8 0.6 0.4 Integral Nonlinearity (INL) Positive INL INL (LSB) 0.5 0.0 -0.5 DNL (LSB) Positive INL 0.2 0.0 -0.2 Negative INL -0.4 -0.6 -0.8 -1.0 Negative INL -1.0 -1.5 -2.0 0 1 2 3 4 5 0 50 100 150 200 VREF (V) Sample Rate(ksps) FIGURE 2-2: vs. VREF. 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 Integral Nonlinearity (INL) FIGURE 2-5: Differential Nonlinearity (DNL) vs. Sample Rate. 2.0 1.5 1.0 DNL (LSB) INL(LSB) 0.5 0.0 -0.5 Positive INL Negative INL -1.0 -1.5 -1024 0 1024 2048 3072 4096 -2.0 0 1 2 3 4 5 6 Code VREF (V) FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: (DNL) vs. VREF. Differential Nonlinearity  2011 Microchip Technology Inc. DS21700D-page 7 MCP3301 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 1 0.8 0.6 0.4 20 18 16 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 Offset Error (LSB) -3072 -2048 -1024 0 1024 2048 3072 4096 14 12 10 8 6 4 2 0 0 1 2 DNL(LSB) Code VREF (V) 3 4 5 6 FIGURE 2-7: Differential Nonlinearity (DNL) vs. Code (Representative Part). 1.0 0.8 0.6 FIGURE 2-10: Offset Error vs. VREF. 0.0 -0.2 Positive Gain Error (LSB) -0.4 -0.6 -0.8 -1.0 -1.2 -1.4 -1.6 -1.8 DNL Error (LSB) 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 -50 0 Positive DNL Negative DNL 50 100 150 -50 0 50 100 150 Temperature (°C) Temperature (°C) FIGURE 2-8: Differential Nonlinearity (DNL) vs. Temperature. 5 4 3 FIGURE 2-11: Temperature. 100 90 80 70 Positive Gain Error vs. Positive Gain Error (LSB) SNR (dB) 0 1 2 3 4 5 6 2 1 0 -1 -2 60 50 40 30 20 10 0 VREF (V) 1 10 100 Input Frequency (kHz) FIGURE 2-9: Positive Gain Error vs. VREF. FIGURE 2-12: Signal to Noise Ratio (SNR) vs. Input Frequency. DS21700D-page 8  2011 Microchip Technology Inc. MCP3301 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 0 -10 -20 -30 80 70 60 SINAD (dB) 50 40 30 20 10 THD (dB) -40 -50 -60 -70 -80 -90 -100 1 10 100 0 -40 -35 -30 -25 -20 -15 -10 -5 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-13: Total Harmonic Distortion (THD) vs. Input Frequency. 3.5 3 FIGURE 2-16: Signal to Noise and Distortion (SINAD) vs. Input Signal Level. 13 12 11 10 9 Offset Error (LSB) 2.5 2 1.5 1 0.5 0 -50 0 50 100 150 8 7 0 1 2 ENOB (rms) Temperature (°C) 3 VREF (V) 4 5 6 FIGURE 2-14: Temperature. 90 80 70 60 Offset Error vs. FIGURE 2-17: (ENOB) vs. VREF. 100 90 80 70 Effective Number of Bits SINAD (dB) SFDR (dB) 1 10 100 50 40 30 20 10 0 60 50 40 30 20 10 0 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-15: Signal to Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-18: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.  2011 Microchip Technology Inc. DS21700D-page 9 MCP3301 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 5000 10000 15000 20000 25000 450 400 350 300 Amplitude (dB) IDD (µA) 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Frequency (Hz) VDD (V) FIGURE 2-19: Frequency Spectrum of 10 kHz Input (Representative Part). 13 12.8 12.6 FIGURE 2-22: IDD vs. VDD. 500 450 400 350 ENOB (rms) 12.4 12.2 12 11.8 11.6 11.4 11.2 1 10 100 IDD (µA) 300 250 200 150 100 50 0 0 50 100 150 200 Input Frequency (kHz) Sample Rate (ksps) FIGURE 2-20: Effective Number of Bits (ENOB) vs. Input Frequency. -30 -35 -40 -45 FIGURE 2-23: IDD vs. Sample Rate. 345 340 335 330 PSR(dB) -55 -60 -65 -70 -75 -80 1 10 100 1000 10000 IDD (µA) -50 325 320 315 310 305 300 295 -50 0 50 100 150 Ripple Frequency (kHz) Temperature (°C) FIGURE 2-21: Power Supply Rejection (PSR) vs. Ripple Frequency. A 0.1 µF bypass capacitor is connected to the VDD pin. FIGURE 2-24: IDD vs. Temperature. DS21700D-page 10  2011 Microchip Technology Inc. MCP3301 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 120 80 70 60 80 100 IREF (µA) IDDS (pA) 50 40 30 20 60 40 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 6 2 2.5 3 3.5 4 4.5 5 5.5 6 0 VDD (V) VDD (V) FIGURE 2-25: IREF vs. VDD. FIGURE 2-28: IDDS vs. VDD. 100 90 80 70 100 10 IREF (µA) 50 40 30 20 10 0 0 50 100 150 200 IDDS (nA) 60 1 0.1 0.01 0.001 -50 -25 0 25 50 75 100 Sample Rate (ksps) Temperature (°C) FIGURE 2-26: IREF vs. Sample Rate. FIGURE 2-29: IDDS vs. Temperature. 73.8 73.6 73.4 73.2 8 7 Negative Gain Error (LSB) 6 5 4 3 2 1 0 -1 IREF (µA) 73 72.8 72.6 72.4 72.2 72 71.8 -50 0 Temperature (°C) 50 100 150 0 1 2 VREF (V) 3 4 5 6 FIGURE 2-27: IREF vs. Temperature. FIGURE 2-30: Negative Gain Error vs. Reference Voltage.  2011 Microchip Technology Inc. DS21700D-page 11 MCP3301 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 17*FSAMPLE, TA = 25°C. 1 80 Common Mode Rejection Ration(dB) -50 0 50 100 150 0.8 79 78 77 76 75 74 73 72 71 70 Negative Gain Error (LSB) 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 Temperature (°C) 1 10 100 Input Frequency (kHz) 1000 FIGURE 2-31: Temperature. Negative Gain Error vs. FIGURE 2-32: vs. Frequency. Common Mode Rejection DS21700D-page 12  2011 Microchip Technology Inc. MCP3301 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: MSOP, PDIP, SOIC 1 2 3 4 5 6 7 8 PIN FUNCTION TABLE Name VREF IN(+) IN(-) VSS CS/SHDN DOUT CLK VDD Reference Voltage Input Positive Analog Input Negative Analog Input Ground Chip Select / Shutdown Input Serial Data Out Serial Clock +4.5V to 5.5V Power Supply Function 3.1 Voltage Reference (VREF) 3.5 Chip Select/Shutdown (CS/SHDN) This input pin provides the reference voltage for the device, which determines the maximum range of the analog input signal and the LSB size. The LSB size is determined by the equation shown below. As the reference input is reduced, the LSB size is reduced accordingly. The CS/SHDN pin is used to initiate communication with the device when pulled low. This pin will end a conversion and put the device in low power standby when pulled high. The CS/SHDN pin must be pulled high between conversions and cannot be tied low for multiple conversions. See Figure 6-2 for serial communication protocol. EQUATION 2 x VREF LSB Size = 8192 When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the accuracy of the ADC conversion results. 3.6 Serial Data Output (DOUT) The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure 6-2 for serial communication protocol. 3.7 Serial Clock (CLK) 3.2 Positive Analog Input (IN+) This pin has an absolute voltage range of VSS-0.3V to VDD+0.3V. The full scale input range is defined as the absolute value of (IN+) - (IN-). The SPI clock pin is used to initiate a conversion, as well as to clock out each bit of the conversion as it takes place. See Section 5.2 “Driving the Analog Input” for constraints on clock speed, and Figure 6-2 for serial communication protocol. 3.8 Power Supply (VDD) 3.3 Negative Analog Input (IN-) This pin has an absolute voltage range of VSS-0.3V to VDD+0.3V. The full scale input range is defined as the absolute value of (IN+) - (IN-). 3.4 Ground Connection (VSS) The device can operate from 2.7V to 5.5V, but the performance is applicable from a 4.5V to 5.5V supply range. To ensure accuracy, a 0.1 µF ceramic bypass capacitor should be placed as close as possible to the pin. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 5.6 “Layout Considerations”, for more information regarding circuit layout.  2011 Microchip Technology Inc. DS21700D-page 13 MCP3301 NOTES: DS21700D-page 14  2011 Microchip Technology Inc. MCP3301 4.0 DEFINITION OF TERMS Bipolar Operation - This applies to either a differential or single-ended input configuration, where both positive and negative codes are output from the A/D converter. Full bipolar range includes all 8192 codes. For bipolar operation on a single-ended input signal, the A/D converter must be configured to operate in pseudo differential mode. Unipolar Operation - This applies to either a singleended or differential input signal where only one side of the device transfer is being used. This could be either the positive or negative side, depending on which input (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. Full Differential Operation - Applying a full differential signal to both the IN(+) and IN(-) inputs is referred to as full differential operation. This configuration is described in Figure 1-5. Pseudo-Differential Operation - Applying a singleended signal to only one of the input channels with a bipolar output is referred to as pseudo differential operation. To obtain a bipolar output from a singleended input signal the inverting input of the A/D converter must be biased above VSS. This operation is described in Figure 1-6. Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipolar transfer function is defined as the maximum integral nonlinearity error. The endpoints of the transfer function are a point 1/2 LSB above the first code transition (0x1000) and 1/2 LSB below the last code transition (0x0FFF). Differential Nonlinearity - The difference between two measured adjacent code transitions and the 1 LSB ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the last positive code transition (0x0FFF) and the ideal voltage level of VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal voltage level of -VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2 LSB voltage level. Acquisition Time - The acquisition time is defined as the time during which the internal sample capacitor is charging. This occurs for 1.5 clock cycles of the external CLK as defined in Figure 6-2. Conversion Time - The conversion time occurs immediately after the acquisition time. During this time, successive approximation of the input signal occurs as the 13-bit result is being calculated by the internal circuitry. This occurs for 13 clock cycles of the external CLK as defined in Figure 6-2. Signal to Noise Ratio - Signal to Noise Ratio (SNR) is defined as the ratio of the signal to noise measured at the output of the converter. The signal is defined as the rms amplitude of the fundamental frequency of the input signal. The noise value is dependant on the device noise as well as the quantization error of the converter and is directly affected by the number of bits in the converter. The theoretical signal to noise ratio limit based on quantization error only for an N-bit converter is defined as: EQUATION SNR =  6.02 N + 1.76  dB For a 13-bit converter, the theoretical SNR limit is 80.02 dB. Total Harmonic Distortion - Total Harmonic Distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental, measured at the output of the converter. For the MCP3301, it is defined using the first 9 harmonics, as shown in the following equation: EQUATION V 2 + V 3 + V 4 + ..... + V 8 + V 9 THD(-dB) = – 20 log ------------------------------------------------------------------------------2 V1 Here V1 is the rms amplitude of the fundamental and V2 through V9 are the rms amplitudes of the second through ninth harmonics. Signal-to-Noise plus Distortion (SINAD) - Numerically defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic performance of the converter, including any harmonic distortion. 2 2 2 2 2 EQUATION SINAD (dB) = 20 log 10  SNR  10  + 10 –  THD  10  EffectIve Number of Bits - Effective Number of Bits (ENOB) states the relative performance of the ADC in terms of its resolution. This term is directly related to SINAD by the following equation: EQUATION SINAD – 1.76 ENOB  N  = ----------------------------------6.02 For SINAD performance of 78 dB, the effective number of bits is 12.66. Spurious Free Dynamic Range - Spurious Free Dynamic Range (SFDR) is the ratio of the rms value of the fundamental to the next largest component in the output spectrum of the ADC. This is, typically, the first harmonic, but could also be a noise peak.  2011 Microchip Technology Inc. DS21700D-page 15 MCP3301 NOTES: DS21700D-page 16  2011 Microchip Technology Inc. MCP3301 5.0 5.1 APPLICATIONS INFORMATION Conversion Description 5.2 Driving the Analog Input The MCP3301MCP3301 A/D converter employs a conventional SAR architecture. With this architecture, the potential between the IN+ and IN- inputs are simultaneously sampled and stored with the internal sample circuits for 1.5 clock cycles (tACQ). Following this sample time, the input hold switches of the converter open and the device uses the collected charge to produce a serial 13-bit binary two’s complement output code. This conversion process is driven by the external clock and must include 13 clock cycles, one for each bit. During this process, the most significant bit (MSB) is output first. This bit is the sign bit and indicates whether the IN+ input or the IN- input is at a higher potential. The analog input of the MCP3301 is easily driven either differentially or single-ended. Any signal that is common to the two input channels will be rejected by the common mode rejection of the device. During the charging time of the sample capacitor, a small charging current will be required. For low source impedances, this input can be driven directly. For larger source impedances, a larger acquisition time will be required, due to the RC time constant that includes the source impedance. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 13-bit accurate voltage level during the 1.5 clock cycle acquisition period. An analog input model is shown in Figure 5-3. This model is accurate for an analog input, regardless of whether it is configured as a single-ended input or the IN+ and IN- input in differential mode. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance with no additional acquisition time increases the offset, gain, and integral linearity errors of the conversion. To overcome this, a slower clock speed can be used to allow for the longer charging time. Figure 5-2 shows the maximum clock speed associated with source impedances. 1.8 IN+ Hold CSAMP CDAC + Comp INHold CSAMP 13-Bit SAR Shift Register Max Clock Frequency (MHz) DOUT 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 100 1000 10000 100000 FIGURE 5-1: Simplified Block Diagram. Input Resistance (ohms) FIGURE 5-2: Maximum Clock Frequency vs. Source Resistance (RS) to maintain ±1 LSB INL.  2011 Microchip Technology Inc. DS21700D-page 17 MCP3301 VDD CHx VT = 0.6V Sampling Switch SS RSS = 1 k CSAMPLE = DAC capacitance = 25 pF VSS Legend VA RS CHx CPIN VT ILEAKAGE SS RSS CSAMPLE RS VA CPIN 7 pF VT = 0.6V ILEAKAGE ±1 nA = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pin due to various junctions sampling switch sampling switch resistor sample/hold capacitance FIGURE 5-3: 5.2.1 Analog Input Model. MAINTAINING MINIMUM CLOCK SPEED Using the values in Figure 5-4, we have a 100 Hz corner frequency. See Figure 5-2 for the relationship between input impedance and acquisition time. When the MCP3301 initiates, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. For MCP3301 devices, the recommended minimum clock speed during the conversion cycle (tCONV) is 85 kHz. Failure to meet this criteria may introduce linearity errors into the conversion outside the rated specifications. It should be noted that, during the entire conversion cycle, the A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met. VDD = 5V 0.1 µF C 10 µF VIN 1 k R IN+ INMCP3301 VREF 5.3 Biasing Solutions 1 µF VOUT VIN 0.1 µF MCP1525 For pseudo-differential bipolar operation, the biasing circuit shown in Figure 5-4 shows a single-ended input AC coupled to the converter. This configuration will give a digital output range of -4096 to +4095. With the 2.5V reference, the LSB size is equal to 610 µV. Although the ADC is not production tested with a 2.5V reference as shown, linearity will not change more than 0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and DNL errors versus VREF at VDD = 5V. A trade-off exists between the high-pass corner and the acquisition time. The value of C will need to be quite large in order to bring down the high-pass corner. The value of R needs to be 1 k or less, since higher input impedances require additional acquisition time. FIGURE 5-4: Pseudo-differential biasing circuit for bipolar operation. DS21700D-page 18  2011 Microchip Technology Inc. MCP3301 Using an external operational amplifier on the input allows for gain and buffers the input signal from the input to the ADC, allowing for a higher source impedance. This circuit is shown in Figure 5-5. VDD = 5V 10 k 1 k VIN MCP6022 + 1 µF 1 M IN+ INMCP3301 VREF 0.1 µF 5.4 Common Mode Input Range The common mode input range has no restriction and is equal to the absolute input voltage range: VSS -0.3V to VDD + 0.3V. However, for a given VREF, the common mode voltage has a limited swing if the entire range of the A/D converter is to be used. Figure 5-7 and Figure 5-8 show the relationship between VREF and the common mode voltage. A smaller VREF allows for wider flexibility in a common mode voltage. VREF levels, down to 400 mV, exhibit less than 0.1 LSB change in INL and DNL. For characterization graphs that show this performance relationship, see Figure 2-2 and Figure 2-6. VDD = 5V Common Mode Range (V) 1 µF VIN VOUT MCP1525 0.1 µF 5 4 3 2 1 0 -1 0.25 0.95V 4.05V 2.8V FIGURE 5-5: Adding an amplifier allows for gain and also buffers the input from any high impedance sources. This circuit shows that some headroom will be lost due to the amplifier output not being able to swing all the way to the rail. An example would be for an output swing of 0V to 5V. This limitation can be overcome by supplying a VREF that is slightly less than the common mode voltage. Using a 2.048V reference for the A/D converter, while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure 5-6. VDD = 5V 10 k 1 k VIN MCP606 + 1 µF 1 M 2.3V 1.0 2.5 VREF (V) 4.0 5.0 FIGURE 5-7: Common Mode Range of Full Differential input signal versus VREF. VDD = 5V 5 4.05V 2.8V 0.1 µF Common Mode Range (V) 4 3 2 1 0 -1 0.25 IN+ INMCP3301 VREF 10 k 2.048V 2.3V 0.95V 0.5 1.25 VREF (V) 2.0 2.5 1 µF VOUT VIN MCP1525 0.1 µF FIGURE 5-8: Common Mode Range versus VREF for Pseudo Differential Input. FIGURE 5-6: Circuit solution to overcome amplifier output swing limitation.  2011 Microchip Technology Inc. DS21700D-page 19 MCP3301 5.5 Buffering/Filtering the Analog Inputs 5.6 Layout Considerations When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces should be separated as much as possible on the board with no traces running underneath the device or bypass capacitor. Extra precautions should be taken to keep traces with high frequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors (Figure 5-10). For more information on layout tips when using the MCP3301 or other ADC devices, refer to AN-688 “Layout Tips for 12-Bit A/D Converter Applications”. VDD Connection 0.1 µF VREF IN+ MCP3301 7.86 k VIN 14.6 k 1 µF 2.2 µF MCP601 + IN- Inaccurate conversion results may occur if the signal source for the A/D converter is not a low impedance source. Buffering the input will solve the impedance issue. It is also recommended that an analog filter be used to eliminate any signals that may be aliased back into the conversion results. Using an op amp to drive the analog input of the MCP3301 is illustrated in Figure 5-9. This amplifier provides a low impedance source for the converter input and low pass filter, which eliminates unwanted high frequency noise. Values shown are for a 10 Hz Butterworth Low pass filter. Low pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab® software. FilterLab will calculate capacitor and resistor values as well as determine the number of poles that are required for the application. For more information on filtering signals, see AN-699 “Anti-Aliasing Analog Filters for Data Acquisition Systems”. VDD 4.096V Reference 0.1 µF 1 µF MCP1541 CL 10 µF Device 4 Device 1 FIGURE 5-9: The MCP601 Operational Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by the MCP3301. Device 3 Device 2 FIGURE 5-10: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths.MCP3301 DS21700D-page 20  2011 Microchip Technology Inc. MCP3301 6.0 6.1 SERIAL COMMUNICATIONS Output Code Format The output code format is a binary two’s complement scheme with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the IN- input, the sign bit will be a zero. If the IN- input is higher, the sign bit will be a ‘1’. The diagram shown in Figure 6-1 shows the output code transfer function. In this diagram, the horizontal axis is the analog input voltage and the vertical axis is the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word are zero. As IN+ gets larger, with respect to IN-, the sign bit is a zero and the data word gets larger. The full scale output code is reached at +4095 when the input [(IN+) - (IN-)] reaches VREF - 1 LSB. When IN- is larger than IN+, the two’s complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table 6-1. TABLE 6-1: BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES. Analog Input Levels Sign Bit 0 0 0 0 0 1 1 1 1 Binary Data 1111 1111 1111 1111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 Decimal DATA +4095 +4094 +2 +1 0 -1 -2 -4095 -4096 Full Scale Positive (IN+)-(IN-) = VREF-1 LSB (IN+)-(IN-) = VREF-2 LSB IN+ = (IN-) +2 LSB IN+ = (IN-) +1 LSB IN+ = ININ+ = (IN-) - 1 LSB IN+ = (IN-) - 2 LSB IN+ ININ= VREF+1 LSB = -VREF Full Scale Negative IN - +  2011 Microchip Technology Inc. DS21700D-page 21 MCP3301 Output Code 0 + 1111 1111 1111 (+4095) 0 + 1111 1111 1110 (+4094) Positive Full Scale Output = VREF -1 LSB 0 + 0000 0000 0011 (+3) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0001 (+1) 0 + 0000 0000 0000 (0) IN+ > IN1 + 1111 1111 1111 (-1) 1 + 1111 1111 1110 (-2) 1 + 1111 1111 1101 (-3) -VREF IN+ < IN- VREF Analog Input Voltage IN+ - IN- 1 + 0000 0000 0001 (-4095) 1 + 0000 0000 0000 (-4096) Negative Full Scale Output = -VREF FIGURE 6-1: Output Code Transfer Function. DS21700D-page 22  2011 Microchip Technology Inc. MCP3301 6.2 Communicating with the MCP3301 Communication with the device is completed using a standard SPI compatible serial interface. Initiating communication with the MCP3301 begins with the CS going low. If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The device will begin to sample the analog input on the first rising edge of CLK after CS goes low. The sample period will end in the falling edge of the second clock, at which time the device will output a low null bit. The next 13 clocks will output the result of the conversion with the sign bit first, followed by the tSAMPLE tCSH 12 remaining data bits, as shown in Figure 6-2. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted and the device continues to receive clocks while the CS is held low, the device will output the conversion result LSB first, as shown in Figure 6-3. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. CS tSUCS Power Down CLK tACQ tCONV NULL BIT tDATA** B5 B4 B3 B2 B1 B0* HI-Z NULL BIT DOUT HI-Z SB B11 B10 B9 B8 B7 B6 SB B11 B10 B9 * After completing the data transfer, if further clocks are applied with CS low, the ADC will output LSB first data, followed by zeros indefinitely. See Figure 6-2 below. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 6-2: Communication with MCP3301 (MSB first Format). tSAMPLE tCSH CS tSUCS Power Down CLK tACQ tCONV NULL BIT SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 tDATA** B5 B6 B7 B8 B9 B10 B11 SB* DOUT HI-Z HI-Z * After completing the data transfer, if further clocks are applied with CS low, the ADC will output zeros indefinitely. ** tDATA: during this time, the bias current and the comparator power down and the reference input becomes a high impedance node, leaving the CLK running to clock out the LSB-first data or zeros. FIGURE 6-3: Communication with MCP3301 (LSB first Format).  2011 Microchip Technology Inc. DS21700D-page 23 MCP3301 6.3 Using the MCP3301 with Microcontroller (MCU) SPI Ports falling edge of the third clock pulse, followed by the remaining 12 data bits (MSB first). Once the first eight clocks have been sent to the device, the microcontroller’s receive buffer will contain two unknown bits (for the first two clocks, the output is high impedance), followed by the null bit, the sign bit and the highest order four bits of the conversion. After the second eight clocks have been sent to the device, the MCU receive register will contain the lowest order 8 data bits. Notice that, on the falling edge of clock 16, the ADC has begun to shift out LSB first data. Figure 6-5 shows the same scenario in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the ADC outputs data on the falling edge of the clock and the MCU latches data from the ADC in on the rising edge of the clock. With most microcontroller SPI ports, it is required to clock out eight bits at a time. Using a hardware SPI port with the MCP3301 is very easy because each conversion requires 16 clocks. For example, Figure 6-4 and Figure 6-5 show how the MCP3301 can be interfaced to a microcontroller with a standard SPI port. Since the MCP3301 always clocks data out on the falling edge of clock, the MCU SPI port must be configured to match this operation. SPI Mode 0,0 (clock idles low) and SPI Mode 1,1 (clock idles high) are both compatible with the MCP3301. Figure 6-4 depicts the operation shown in SPI Mode 0,0, which requires that the CLK from the microcontroller idles in the ‘low’ state. As shown in the diagram, the sign bit is clocked out of the ADC on the CS MCU latches data from ADC on rising edges of SCLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of ADC on falling edges HI-Z NULL SB B11 B10 BIT B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 HI-Z LSB first data begins to come out ? ? 0 SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 X = Don’t Care Bits ? = Unknown Bits DOUT Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits FIGURE 6-4: SPI Communication with the MCP3301 using 8-bit segments (Mode 0,0: SCLK idles low). CS MCU latches data from ADC on rising edges of SCLK CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Data is clocked out of ADC on falling edges HI-Z NULL SB BIT B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 HI-Z LSB first data begins to come out ? ? 0 SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 DOUT Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits X = Don’t Care Bits ? = Unknown Bits FIGURE 6-5: SPI Communication with the MCP3301 using 8-bit segments (Mode 1,1: SCLK idles high). DS21700D-page 24  2011 Microchip Technology Inc. MCP3301 NOTES:  2011 Microchip Technology Inc. DS21700D-page 25 MCP3301 7.0 7.1 PACKAGING INFORMATION Package Marking Information 8-Lead MSOP XXXXXX YWWNNN Example: 3301CI 112256 8-Lead PDIP (300 mil) XXXXXX XXXXNNN YYWW Example: 3301-B I/P e3 256 1112 8-Lead SOIC (150 mil) XXXXXXXX XXXXYYWW NNN Example: 3301-BI SN e3 1112 256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21700D-page 26  2011 Microchip Technology Inc. MCP3301 /HDG 3ODVWLF 0LFUR 6PDOO 2XWOLQH 3DFNDJH 06 >0623@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D N E E1 NOTE 1 1 2 e b A2 c φ A A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII 2YHUDOO :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK )RRW /HQJWK )RRWSULQW )RRW $QJOH /HDG 7KLFNQHVV 1 H $ $ $ ( ( ' / / I F L1 0,//,0(7(56 0,1 120   %6& ±   ±  ±  %6&  %6&  %6&  ƒ    5() ± ± ƒ      0$; L /HDG :LGWK E  ±  1RWHV  3LQ  YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( 3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 2 D 3 E A A2 A1 L c e b1 b 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ † 1 H $ $ $ ( ( ' / F E E H% ±          ± 0,1 eB ,1&+(6 120   %6& ±  ±        ±   ±        0$;  1RWHV  3LQ  YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD  † 6LJQLILFDQW &KDUDFWHULVWLF  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( 62,&@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS21700D-page 32  2011 Microchip Technology Inc. MCP3301 APPENDIX A: REVISION HISTORY Revision D (April 2011) The following is the list of modifications: 1. Updated the content to illustrate that the devices now have tested specifications in the 4.5V to 5.5V supply range. Removed figures 2-4 to 2-6, 2-10 to 2-12, 2-16 and 2-17. 2. Revision C (January 2007) This revision includes updates to the packaging diagrams. Revision B (February 2002) Undocumented changes. Revision A (December 2001) Original Release of this Document.  2011 Microchip Technology Inc. DS21700D-page 33 MCP3301 NOTES: DS21700D-page 34  2011 Microchip Technology Inc. MCP3301 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, contact the local Microchip sales office. PART NO. Device X Grade X Temperature Range /XX Package Examples: a) b) Device: MCP3301: 13-Bit Serial A/D Converter MCP3301T: 13-Bit Serial A/D Converter (Tape and Reel) MCP3301-BI/P: ±1 LSB INL, Industrial Temperature, PDIP package MCP3301-BI/SN: ±1 LSB INL, Industrial Temperature, SOIC package MCP3301-CI/MS: ±2 LSB INL, Industrial Temperature, MSOP package c) Grade: B C = ±1 LSB INL = ±2 LSB INL Temperature Range: I = -40°C to +85°C Package: MS = Plastic MSOP, 8-lead P = Plastic DIP (300 mil Body), 8-lead SN = Plastic SOIC (150 mil Body), 8-lead  2011 Microchip Technology Inc. DS21700D-page 35 MCP3301 NOTES:  2011 Microchip Technology Inc. DS21700D-page 36 Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-002-8 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2011 Microchip Technology Inc. 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