MCP3302_11

MCP3302/04 13-Bit Differential Input, Low Power A/D Converter with SPI Serial Interface Features • • • • • • • • • • • • • Full Differential Inputs 2 Differential or 4 Single-ended inputs (MCP3302) 4 Differential or 8 Single-ended Inputs (MCP3304) ±1 LSB maximum DNL ±1 LSB maximum INL (MCP3302/04-B) ±2 LSB maximum INL (MCP3302/04-C) Single supply operation: 4.5V to 5.5V 100 ksps sampling rate with 5V supply voltage 50 nA typical standby current, 1 µA maximum 450 µA maximum active current at 5V Industrial Temperature Range: -40°C to +85°C 14 and 16-pin PDIP, SOIC, and TSSOP packages Mixed Signal PICtail™ Demo Board (P/N: MXSIGDM) compatible General Description The MCP3302/04 13-bit A/D converter features full differential inputs and low-power consumption in a small package that is ideal for battery-powered systems and remote data acquisition applications. The MCP3302 is user-programmable to provide two differential input pairs or four single-ended inputs. The MCP3304 is also user-programmable to configure into four differential input pairs or eight single-ended inputs. Incorporating a successive approximation architecture with on-board sample and hold circuitry, these 13-bit A/D converters are specified to have ±1 LSB Differential Nonlinearity (DNL); ±1 LSB Integral Nonlinearity (INL) for B-grade and ±2 LSB for C-grade devices. The industry-standard SPI serial interface enables 13-bit A/D converter capability to be added to any PIC® microcontroller. The MCP3302/04 devices feature low current design that permits operation with typical standby and active currents of only 50 nA and 300 µA, respectively. The device is capable of conversion rates of up to 100 ksps with tested specifications over a 4.5V to 5.5V supply range. The reference voltage can be varied from 400 mV to 5V, yielding input-referred resolution between 98 µV and 1.22 mV. The MCP3302 is available in 14-pin PDIP, 150 mil SOIC and TSSOP packages. The MCP3304 is available in 16-pin PDIP and 150 mil SOIC packages. The full differential inputs of these devices enable a wide variety of signals to be used in applications such as remote data acquisition, portable instrumentation, and battery-operated applications. Applications • Remote Sensors • Battery-operated Systems • Transducer Interface Package Types PDIP, SOIC, TSSOP CH0 CH1 CH2 CH3 NC NC DGND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VREF AGND CLK DOUT DIN CS/SHDN PDIP, SOIC MCP3302 CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD VREF AGND CLK DOUT DIN CS/SHDN DGND MCP3304  2011 Microchip Technology Inc. DS21697F-page 1 MCP3302/04 Functional Block Diagram VREF CH0 CH1 VDD AGND DGND Input Channel Mux CDAC Comparator 13-Bit SAR + CH7* Sample & Hold Circuits - Control Logic Shift Register CS/SHDN DIN CLK DOUT * Channels 5-7 available on MCP3304 Only DS21697F-page 2  2011 Microchip Technology Inc. MCP3302/04 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD...................................................................................7.0V All inputs and outputs w.r.t. VSS ............... -0.3V to VDD +0.3V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Maximum Junction Temperature .................................. 150°C ESD protection on all pins (HBM)  4 kV ELECTRICAL SPECIFICATIONS Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Conversion Rate Maximum Sampling Frequency Conversion Time Acquisition Time DC Accuracy Resolution Integral Nonlinearity Differential Nonlinearity Positive Gain Error Negative Gain Error Offset Error Dynamic Performance Total Harmonic Distortion Signal-to-Noise and Distortion Spurious Free Dynamic Range Common Mode Rejection Channel to Channel Crosstalk Power Supply Rejection Reference Input Voltage Range Current Drain Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 0.4 — — — 100 0.001 VDD 150 3 V µA µA CS = VDD = 5V Note 2 THD SINAD SFDR CMRR CT PSR — — — — — — -91 78 92 79 > -110 74 — — — — — — dB dB dB dB dB dB Note 3 Note 3 Note 3 Note 6 Note 6 Note 4 INL DNL — — — -3 -3 -3 12 data bits + sign ±0.5 ±1 ±0.5 -0.75 -0.5 +3 ±1 ±2 ±1 +2 +2 +6 bits LSB LSB LSB LSB LSB LSB MCP3302/04-B MCP3302/04-C Monotonic over temperature FSAMPLE TCONV TACQ — — 13 1.5 100 ksps CLK periods CLK periods See FCLK specification. Note 8 Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance.  2011 Microchip Technology Inc. DS21697F-page 3 MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Analog Inputs Full Scale Input Span Absolute Input Voltage Leakage Current Switch Resistance Sample Capacitor Digital Input/Output Data Coding Format High Level Input Voltage Low Level Input Voltage High Level Output Voltage Low Level Output Voltage Input Leakage Current Output Leakage Current Pin Capacitance Timing Specifications: Clock Frequency (Note 8) Clock High Time Clock Low Time CS Fall To First Rising CLK Edge Data In Setup time Data In Hold Time CLK Fall To Output Data Valid CLK Fall To Output Enable CS Rise To Output Disable CS Disable Time DOUT Rise Time DOUT Fall Time Note 1: 2: 3: 4: 5: 6: 7: 8: 9: FCLK THI TLO TSUCS TSU THD TDO TEN TDIS TCSH TR TF 0.105 210 210 100 50 50 — — — — — 475 — — — — — — — — — — — — — — — — 2.1 — — — — — 125 200 125 200 100 — 100 100 MHz ns ns ns ns ns ns ns ns ns ns ns ns ns See test circuits, Figure 1-2 Note 1 See test circuits, Figure 1-2 Note 1 VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 VDD = 5V, see Figure 1-2 VDD = 2.7V, see Figure 1-2 See test circuits, Figure 1-2 Note 1 VDD = 5V, FSAMPLE = 100 ksps Note 5 Note 5 VIH VIL VOH VOL ILI ILO CIN, COUT Binary Two’s Complement 0.7 VDD — 4.1 — -10 -10 — — — — — — — — — 0.3 VDD — 0.4 10 10 10 V V V V µA µA pF IOH = -1 mA, VDD = 4.5V IOL = 1 mA, VDD = 4.5V VIN = VSS or VDD VOUT = VSS or VDD TA = +25°C, F = 1 MHz, Note 1 RS CSAMPLE CH0 - CH7 CH0 - CH7 -VREF -0.3 — — — — — 0.001 1 25 VREF VDD + 0.3 ±1 — — V V µA kΩ pF See Figure 5-3 See Figure 5-3 Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance. DS21697F-page 4  2011 Microchip Technology Inc. MCP3302/04 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: Unless otherwise noted, all parameters apply at VDD = 5V, VSS = 0V, and VREF = 5V. Full differential input configuration (Figure 1-5) with fixed common mode voltage of 2.5V. All parameters apply over temperature with TA = -40°C to +85°C (Note 7). Conversion speed (FSAMPLE) is 100 ksps with FCLK = 21*FSAMPLE Parameter Power Requirements: Operating Voltage Operating Current Standby Current Note 1: 2: 3: 4: 5: 6: 7: 8: 9: VDD IDD IDDS 4.5 — — — — 300 200 0.05 5.5 450 — 1 V µA µA µA Note 9 VDD, VREF = 5V, DOUT unloaded VDD, VREF = 2.7V, DOUT unloaded CS = VDD = 5.0V Symbol Min Typ Max Units Conditions This specification is established by characterization and not 100% tested. See characterization graphs that relate converter performance to VREF level. VIN = 0.1V to 4.9V @ 1 kHz. VDD =5V DC ±500 mVP-P @ 1 kHz, see test circuit Figure 1-4. Maximum clock frequency specification must be met. VREF = 400 mV, VIN = 0.1V to 4.9V @ 1 kHz. TSSOP devices are only specified at 25°C and +85°C. For slow sample rates, see Section 5.2 “Driving the Analog Input” for limitations on clock frequency. 4.5V - 5.5V is the supply voltage range for specified performance. TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 14L-PDIP Thermal Resistance, 14L-SOIC Thermal Resistance, 14L-TSSOP Thermal Resistance, 16L-PDIP Thermal Resistance, 16L-SOIC JA JA JA JA JA — — — — — 70 95.3 100 70 86.1 — — — — — °C/W °C/W °C/W °C/W °C/W TCSH CS TA TA TA -40 -40 -65 — — — +125 +125 +150 °C °C °C Sym Min Typ Max Units Conditions TSUCS THI TLO CLK TSU DIN THD T Sign BIT MSB IN TEN TDO Null Bit TF LSB TDIS DOUT FIGURE 1-1: Timing Parameters.  2011 Microchip Technology Inc. DS21697F-page 5 MCP3302/04 1.1 Test Circuits VREF = 5V 1.4V MCP330X DOUT 3 kΩ Test Point 5VP-P IN(+) CL = 100 pF 5VP-P IN(-) 1 µF 0.1 µF VDD = 5V 0.1 µF MCP330X VREFVDD VSS FIGURE 1-2: Test Point Load Circuit for TR, TF, TDO. VCM = 2.5V VDD MCP330X DOUT 3 kΩ 100 pF VDD/2 TDIS Waveform 2 TEN Waveform TDIS Waveform 1 FIGURE 1-5: Full Differential Test Configuration Example. VSS VREF = 2.5V 1µF 0.1µF VDD = 5V 0.1µF Voltage Waveforms for TDIS CS DOUT Waveform 1* TDIS DOUT Waveform 2† 10% VIH 90% 5VP-P IN(+) IN(-) MCP330X VREF VDD VSS VCM = 2.5V FIGURE 1-6: Pseudo Differential Test Configuration Example. *Waveform 1 is for an output with internal conditions such that the output is high, unless disabled by the output control. †Waveform 2 is for an output with internal conditions such that the output is low, unless disabled by the output control. FIGURE 1-3: TEN. 1 k Load circuit for TDIS and 1/2 MCP602 + - 20 kΩ 2.63V 1 k To VDD on DUT 5V ±500 mVP-P 5VP-P 1 k FIGURE 1-4: Power Supply Sensitivity Test Circuit (PSRR). DS21697F-page 6  2011 Microchip Technology Inc. MCP3302/04 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VDD = VREF = 5V, full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. . 1 0.8 0.6 0.4 Positive INL 1 0.8 0.6 0.4 Positive INL INL (LSB) 0 -0.2 -0.4 -0.6 -0.8 -1 0 50 100 150 200 Negative INL INL (LSB) 0.2 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 Negative INL Sample Rate (ksps) Temperature(°C) FIGURE 2-1: vs. Sample Rate. 2 1.5 1 Integral Nonlinearity (INL) FIGURE 2-4: vs. Temperature. 1 0.8 0.6 Integral Nonlinearity (INL) DNL (LSB) INL (LSB) 0.5 0 -0.5 -1 -1.5 -2 0 1 Positive INL 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 Positive DNL Negative INL Negative DNL 2 3 4 5 -1 0 50 VREF(V) Sample Rate (ksps) 100 150 200 FIGURE 2-2: vs. VREF. 1 0.8 0.6 0.4 Integral Nonlinearity (INL) FIGURE 2-5: Differential Nonlinearity (DNL) vs. Sample Rate. 2 1.5 1 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 -3072 -2048 -1024 0 1024 2048 3072 4096 DNL(LSB) INL (LSB) 0.2 0.5 0 -0.5 -1 -1.5 -2 0 1 Positive DNL Negative DNL 2 3 4 5 6 Code VREF(V) FIGURE 2-3: Integral Nonlinearity (INL) vs. Code (Representative Part). FIGURE 2-6: (DNL) vs. VREF. Differential Nonlinearity  2011 Microchip Technology Inc. DS21697F-page 7 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 1 0.8 0.6 0.4 20 18 16 14 12 10 8 6 4 2 0 -3072 -2048 -1024 0 1024 2048 3072 4096 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -4096 0 1 2 3 4 5 6 Code VREF(V) FIGURE 2-7: Differential Nonlinearity (DNL) vs. Code (Representative Part). 1 0.8 FIGURE 2-10: Offset Error vs. VREF. 0 -0.2 -0.4 -0.6 -0.8 -1 -1.2 -50 0 0.4 Positive DNL 0.2 0 -0.2 -0.4 -0.6 -0.8 -1 -50 -25 0 25 50 75 100 125 150 Negaitive DNL Positive Gain Error (LSB) 0.6 DNL (LSB) Temperature (°C) Temperature (°C) 50 100 150 FIGURE 2-8: Differential Nonlinearity (DNL) vs. Temperature. 4 3 2 1 0 -1 -2 -3 0 1 2 3 4 5 6 FIGURE 2-11: Temperature. 100 90 80 70 Positive Gain Error vs. Positive Gain Error (LSB) SNR (db) 60 50 40 30 20 10 0 VREF(V) 1 10 100 Input Frequency (kHz) FIGURE 2-9: Positive Gain Error vs. VREF. FIGURE 2-12: Signal-to-Noise Ratio (SNR) vs. Input Frequency. DS21697F-page 8  2011 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 0 -10 -20 -30 60 80 70 SINAD (dB) THD (dB) -40 -50 -60 -70 50 40 30 20 -80 -90 -100 1 10 100 10 0 -40 -30 -20 -10 0 Input Frequency (kHz) Input Signal Level (dB) FIGURE 2-13: Total Harmonic Distortion (THD) vs. Input Frequency. 3.1 3 FIGURE 2-16: Signal-to-Noise and Distortion (SINAD) vs. Input Signal Level. 13 12 11 10 9 Offset Error (LSB) 2.9 2.8 2.7 2.6 ENOB (rms) -50 0 50 100 150 8 2.5 7 0 1 2 3 VREF (V) 4 5 6 Temperature (°C) FIGURE 2-14: Temperature. 79 Offset Error vs. FIGURE 2-17: (ENOB) vs. VREF. 100 Effective Number of Bits 78 77 76 90 80 70 SINAD (dB) SFDR (dB) 1 10 100 75 74 73 72 71 70 69 60 50 40 30 20 10 0 1 10 100 Input Frequency (kHz) Input Frequency (kHz) FIGURE 2-15: Signal-to-Noise and Distortion (SINAD) vs. Input Frequency. FIGURE 2-18: Spurious Free Dynamic Range (SFDR) vs. Input Frequency.  2011 Microchip Technology Inc. DS21697F-page 9 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -130 -140 -150 0 10000 20000 450 400 350 300 Amplitude (dB) IDD (µA) 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Frequency (Hz) 30000 40000 50000 VDD (V) FIGURE 2-19: Frequency Spectrum of 10 kHz Input (Representative Part). 12.85 FIGURE 2-22: IDD vs. VDD. 600 500 400 12.8 ENOB (rms) IDD (µA) 12.75 300 200 12.7 12.65 100 0 1 10 100 0 50 100 150 200 12.6 Input Frequency (kHz) Sample Rate (ksps) FIGURE 2-20: Effective Number of Bits (ENOB) vs. Input Frequency. -30 -35 -40 -45 FIGURE 2-23: IDD vs. Sample Rate. 390 380 370 PSR(dB) IDD (µA) -50 -55 -60 -65 -70 -75 -80 1 10 100 1000 10000 360 350 340 330 320 -50 0 50 100 150 Ripple Frequency (kHz) Temperature (°C) FIGURE 2-21: Power Supply Rejection (PSR) vs. Ripple Frequency. A 0.1 µF bypass capacitor is connected to the VDD pin. FIGURE 2-24: IDD vs. Temperature. DS21697F-page 10  2011 Microchip Technology Inc. MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 120 100 80 80 70 60 IREF (µA) 60 40 20 0 2 2.5 3 3.5 4 4.5 5 5.5 6 IDDS (pA) 50 40 30 20 10 0 2 2.5 3 3.5 4 4.5 5 5.5 6 VDD (V) VDD (V) FIGURE 2-25: IREF vs. VDD. FIGURE 2-28: IDDS vs. VDD. 120 100 80 100 10 IREF (µA) 60 40 20 0 0 50 100 150 200 IDDS (nA) 1 0.1 0.01 0.001 -50 -25 0 25 50 75 100 Sample Rate (ksps) Temperature (°C) FIGURE 2-26: IREF vs. Sample Rate. FIGURE 2-29: IDDS vs. Temperature. 93 4 3.5 Negative Gain Error (LSB) -50 0 50 100 150 92 91 3 2.5 2 1.5 1 0.5 0 -0.5 -1 0 1 2 3 4 5 6 IREF (µA) 90 89 88 87 86 Temperature (°C) VREF (V) FIGURE 2-27: IREF vs. Temperature. FIGURE 2-30: Negative Gain Error vs. Reference Voltage.  2011 Microchip Technology Inc. DS21697F-page 11 MCP3302/04 Note: Unless otherwise indicated, VDD = VREF = 5V, Full differential input configuration, VSS = 0V, FSAMPLE = 100 ksps, FCLK = 21*FSAMPLE, TA = +25°C. 2 80 Common Mode Rejection Ration(dB) 79 78 77 76 75 74 73 72 71 70 1 10 100 Input Frequency (kHz) 1000 Negative Gain Error (LSB) 1.5 1 0.5 0 -0.5 -1 -1.5 -2 -50 0 50 100 150 Temperature (°C) FIGURE 2-31: Temperature. Negative Gain Error vs. FIGURE 2-32: vs. Frequency. Common Mode Rejection DS21697F-page 12  2011 Microchip Technology Inc. MCP3302/04 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE MCP3304 PDIP, SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 — Symbol CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 DGND CS/SHDN DIN DOUT CLK AGND VREF VDD NC Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Analog Input Digital Ground Chip Select / Shutdown Input Serial Data In Serial Data Out Serial Clock Analog Ground Reference Voltage Input +4.5V to 5.5V Power Supply No Connection Description The descriptions of the pins are listed in Table 3-1. TABLE 3-1: MCP3302 PDIP, SOIC, TSSOP 1 2 3 4 — — — — 7 8 9 10 11 12 13 14 5, 6 3.1 Analog Inputs (CH0-CH7) 3.4 Serial Data Input (DIN) Analog input channels. These pins have an absolute voltage range of VSS - 0.3V to VDD+ 0.3V. The full scale differential input range is defined as the absolute value of (IN+) - (IN-). This difference can not exceed the value of VREF - 1 LSB or digital code saturation will occur. The SPI port serial data input pin is used to clock in input channel configuration data. Data is latched on the rising edge of the clock. See Figure 6-2 for serial communication protocol. 3.5 Serial Data Output (DOUT) 3.2 Digital Ground (DGND) Ground connection to internal digital circuitry. To ensure accuracy this pin must be connected to the same ground as AGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. The SPI serial data output pin is used to shift out the results of the A/D conversion. Data will always change on the falling edge of each clock as the conversion takes place. See Figure 6-2 for serial communication protocol. 3.6 Serial Clock (CLK) 3.3 Chip Select/Shutdown (CS/SHDN) The CS/SHDN pin is used to initiate communication with the device when pulled low. This pin will end a conversion and put the device in low-power standby when pulled high. The CS/SHDN pin must be pulled high between conversions and cannot be tied low for multiple conversions. See Figure 6-2 for serial communication protocol. The SPI clock pin is used to initiate a conversion, as well as to clock out each bit of the conversion as it takes place. See Section 5.2 “Driving the Analog Input” for constraints on clock speed, and Figure 6-2 for serial communication protocol.  2011 Microchip Technology Inc. DS21697F-page 13 MCP3302/04 3.7 Analog Ground (AGND) 3.9 Power Supply (VDD) Ground connection to internal analog circuitry. To ensure accuracy, this pin must be connected to the same ground as DGND. If an analog ground plane is available, it is recommended that this device be tied to the analog ground plane in the circuit. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. The device can operate from 2.7V to 5.5V, but the data conversion performance is from 4.5V to 5.5V supply range. To ensure accuracy, a 0.1 µF ceramic bypass capacitor should be placed as close as possible to the pin. See Section 5.6 “Layout Considerations” for more information regarding circuit layout. 3.8 Voltage Reference (VREF) This input pin provides the reference voltage for the device, which determines the maximum range of the analog input signal and the LSB size. The LSB size is determined according to the equation shown below. As the reference input is reduced, the LSB size is reduced accordingly. EQUATION 3-1: LSB Size = 2 x VREF 8192 When using an external voltage reference device, the system designer should always refer to the manufacturer’s recommendations for circuit layout. Any instability in the operation of the reference device will have a direct effect on the accuracy of the ADC conversion results. DS21697F-page 14  2011 Microchip Technology Inc. MCP3302/04 4.0 DEFINITION OF TERMS Bipolar Operation - This applies to either a differential or single-ended input configuration, where both positive and negative codes are output from the A/D converter. Full bipolar range includes all 8192 codes. For bipolar operation on a single-ended input signal, the A/D converter must be configured to operate in pseudo differential mode. Unipolar Operation - This applies to either a singleended or differential input signal where only one side of the device transfer is being used. This could be either the positive or negative side, depending on which input (IN+ or IN-) is being used for the DC bias. Full unipolar operation is equivalent to a 12-bit converter. Full Differential Operation - Applying a full differential signal to both the IN(+) and IN(-) inputs is referred to as full differential operation. This configuration is described in Figure 1-5. Pseudo-Differential Operation - Applying a singleended signal to only one of the input channels with a bipolar output is referred to as pseudo differential operation. To obtain a bipolar output from a singleended input signal the inverting input of the A/D converter must be biased above VSS. This operation is described in Figure 1-6. Integral Nonlinearity - The maximum deviation from a straight line passing through the endpoints of the bipolar transfer function is defined as the maximum integral nonlinearity error. The endpoints of the transfer function are a point 1/2 LSB above the first code transition (0x1000) and 1/2 LSB below the last code transition (0x0FFF). Differential Nonlinearity - The difference between two measured adjacent code transitions and the 1 LSB ideal is defined as differential nonlinearity. Positive Gain Error - This is the deviation between the last positive code transition (0x0FFF) and the ideal voltage level of VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Negative Gain Error - This is the deviation between the last negative code transition (0X1000) and the ideal voltage level of -VREF-1/2 LSB, after the bipolar offset error has been adjusted out. Offset Error - This is the deviation between the first positive code transition (0x0001) and the ideal 1/2 LSB voltage level. Acquisition Time - The acquisition time is defined as the time during which the internal sample capacitor is charging. This occurs for 1.5 clock cycles of the external CLK as defined in Figure 6-2. Conversion Time - The conversion time occurs immediately after the acquisition time. During this time, successive approximation of the input signal occurs as the 13-bit result is being calculated by the internal circuitry. This occurs for 13 clock cycles of the external CLK as defined in Figure 6-2. Signal-to-Noise Ratio - Signal-to-Noise Ratio (SNR) is defined as the ratio of the signal-to-noise measured at the output of the converter. The signal is defined as the rms amplitude of the fundamental frequency of the input signal. The noise value is dependant on the device noise as well as the quantization error of the converter and is directly affected by the number of bits in the converter. The theoretical signal-to-noise ratio limit based on quantization error only for an N-bit converter is defined as: EQUATION 4-1: SNR =  6.02 N + 1.76  dB For a 13-bit converter, the theoretical SNR limit is 80.02 dB. Total Harmonic Distortion - Total Harmonic Distortion (THD) is the ratio of the rms sum of the harmonics to the fundamental, measured at the output of the converter. For the MCP3302/04, it is defined using the first 9 harmonics, as is shown in the following equation: EQUATION 4-2: V 2 + V 3 + V 4 + ..... + V 8 + V 9 THD(-dB) = – 20 log ------------------------------------------------------------------------------2 V1 Here V1 is the rms amplitude of the fundamental and V2 through V9 are the rms amplitudes of the second through ninth harmonics. Signal-to-Noise plus Distortion (SINAD) - Numerically defined, SINAD is the calculated combination of SNR and THD. This number represents the dynamic performance of the converter, including any harmonic distortion. 2 2 2 2 2 EQUATION 4-3: SINAD (dB) = 20 log 10  SNR  10  + 10 –  THD  10  EffectIve Number of Bits - Effective Number of Bits (ENOB) states the relative performance of the ADC in terms of its resolution. This term is directly related to SINAD by the following equation: EQUATION 4-4: SINAD – 1.76 ENOB  N  = ----------------------------------6.02 For SINAD performance of 78 dB, the effective number of bits is 12.66. Spurious Free Dynamic Range - Spurious Free Dynamic Range (SFDR) is the ratio of the rms value of the fundamental to the next largest component in the output spectrum of the ADC. This is, typically, the first harmonic, but could also be a noise peak.  2011 Microchip Technology Inc. DS21697F-page 15 MCP3302/04 NOTES: DS21697F-page 16  2011 Microchip Technology Inc. MCP3302/04 5.0 5.1 APPLICATIONS INFORMATION Conversion Description 5.2 Driving the Analog Input The MCP3302/04 A/D converter employ a conventional SAR architecture. With this architecture, the potential between the IN+ and IN- inputs are simultaneously sampled and stored with the internal sample circuits for 1.5 clock cycles (tACQ). Following this sampling time, the input hold switches of the converter open and the device uses the collected charge to produce a serial 13-bit binary two’s complement output code. This conversion process is driven by the external clock and must include 13 clock cycles, one for each bit. During this process, the most significant bit (MSB) is output first. This bit is the sign bit and indicates whether the IN+ input or the IN- input is at a higher potential. The analog input of the MCP3302/04 is easily driven, either differentially or single ended. Any signal that is common to the two input channels will be rejected by the common mode rejection of the device. During the charging time of the sample capacitor, a small charging current will be required. For low-source impedances, this input can be driven directly. For larger source impedances, a larger acquisition time will be required, due to the RC time constant that includes the source impedance. For the A/D Converter to meet specification, the charge holding capacitor (CSAMPLE) must be given enough time to acquire a 13-bit accurate voltage level during the 1.5 clock cycle acquisition period. An analog input model is shown in Figure 5-3. This model is accurate for an analog input, regardless of whether it is configured as a single-ended input, or the IN+ and IN- input in differential mode. In this diagram, it is shown that the source impedance (RS) adds to the internal sampling switch (RSS) impedance, directly affecting the time that is required to charge the capacitor (CSAMPLE). Consequently, a larger source impedance with no additional acquisition time increases the offset, gain, and integral linearity errors of the conversion. To overcome this, a slower clock speed can be used to allow for the longer charging time. Figure 5-2 shows the maximum clock speed associated with source impedances. IN+ Hold CSAMP CDAC + Comp INHold CSAMP 13-Bit SAR Shift Register DOUT Maximum Clock Frequency (MHz) 2.5 2.0 1.5 1.0 0.5 0.0 100 1000 10000 100000 FIGURE 5-1: Simplified Block Diagram. Source Resistance (ohms) FIGURE 5-2: Maximum Clock Frequency vs. Source Resistance (RS) to maintain ±1 LSB INL.  2011 Microchip Technology Inc. DS21697F-page 17 MCP3302/04 VDD RS CHx VT = 0.6V Sampling Switch SS RSS = 1 k CSAMPLE = DAC capacitance = 25 pF VSS Legend VA RS CHx CPIN VT ILEAKAGE SS RSS CSAMPLE = = = = = = = = = signal source source impedance input channel pad input pin capacitance threshold voltage leakage current at the pindue to various junctions sampling switch sampling switch resistor sample/hold capacitance VA CPIN 7 pF VT = 0.6V ILEAKAGE ±1 nA FIGURE 5-3: 5.2.1 Analog Input Model. Using the values in Figure 5-4, we have a 100 Hz corner frequency. See Figure 5-2 for relation between input impedance and acquisition time. MAINTAINING MINIMUM CLOCK SPEED When the MCP3302/04 initiates, charge is stored on the sample capacitor. When the sample period is complete, the device converts one bit for each clock that is received. It is important for the user to note that a slow clock rate will allow charge to bleed off the sample capacitor while the conversion is taking place. For the MCP330X devices, the recommended minimum clock speed during the conversion cycle (TCONV) is 105 kHz. Failure to meet this criteria may induce linearity errors into the conversion outside the rated specifications. It should be noted that during the entire conversion cycle, the A/D converter does not have requirements for clock speed or duty cycle, as long as all timing specifications are met. VDD = 5V 0.1 µF C 10 µF VIN 1 k R IN+ INMCP330X VREF 5.3 Biasing Solutions VOUT 1 µF VIN 0.1 µF MCP1525 For pseudo-differential bipolar operation, the biasing circuit shown in Figure 5-4 shows a single-ended input AC coupled to the converter. This configuration will give a digital output range of -4096 to +4095. With the 2.5V reference, the LSB size equal to 610 µV. Although the ADC is not production tested with a 2.5V reference as shown, linearity will not change more than 0.1 LSB. See Figure 2-2 and Figure 2-6 for INL and DNL errors versus VREF at VDD = 5V. A trade-off exists between the high-pass corner and the acquisition time. The value of C will need to be quite large in order to bring down the high-pass corner. The value of R needs to be 1 kΩ, or less, since higher input impedances require additional acquisition time. FIGURE 5-4: Pseudo-differential biasing circuit for bipolar operation. DS21697F-page 18  2011 Microchip Technology Inc. MCP3302/04 Using an external operation amplifier on the input allows for gain and also buffers the input signal from the input to the ADC allowing for a higher source impedance. This circuit is shown in Figure 5-5. 5.4 Common Mode Input Range VDD = 5V 10 k 1 k VIN MCP6021 + 0.1 µF IN+ IN- The common mode input range has no restriction and is equal to the absolute input voltage range: VSS -0.3V to VDD + 0.3V. However, for a given VREF, the common mode voltage has a limited swing, if the entire range of the A/D converter is to be used. Figure 5-7 and Figure 5-8 show the relationship between VREF and the common mode voltage swing. A smaller VREF allows for wider flexibility in a common mode voltage. VREF levels, down to 400 mV, exhibit less than 0.1 LSB change in INL and DNL. For characterization graphs that show this performance relationship, see Figure 2-2 and Figure 2-6. VDD = 5V Common Mode Range (V) 1 µF 1 M MCP330X VREF 1 µF VOUT VIN MCP1525 5 4 3 2 1 0 -1 0.25 4.05V 2.8V 2.3V 0.95V 0.1 µF FIGURE 5-5: Adding an amplifier allows for gain and also buffers the input from any highimpedance sources. This circuit shows that some headroom will be lost due to the amplifier output not being able to swing all the way to the rail. An example would be for an output swing of 0V to 5V. This limitation can be overcome by supplying a VREF that is slightly less than the common mode voltage. Using a 2.048V reference for the A/D converter while biasing the input signal at 2.5V solves the problem. This circuit is shown in Figure 5-6. 1.0 VREF(V) 2.5 4.0 5.0 FIGURE 5-7: Common Mode Input Range of Full Differential Input Signal versus VREF. VDD = 5V Common Mode Range (V) VDD = 5V 10 k 1 k MCP606 VIN + 1 µF 1 M 0.1 µF 5 4 3 2 1 0 -1 0.25 4.05V 2.8V 2.3V 0.95V IN+ IN- MCP330X VREF 10 k 2.048V 0.5 1.25 2.0 2.5 VREF (V) 0.1 µF 1 µF VOUT VIN MCP1525 FIGURE 5-8: Common Mode Input Range versus VREF for Pseudo Differential Input. FIGURE 5-6: Circuit solution to overcome amplifier output swing limitation.  2011 Microchip Technology Inc. DS21697F-page 19 MCP3302/04 5.5 Buffering/Filtering the Analog Inputs 5.6 Layout Considerations Inaccurate conversion results may occur if the signal source for the A/D converter is not a low-impedance source. Buffering the input will overcome the impedance issue. It is also recommended that an analog filter be used to eliminate any signals that may be aliased back into the conversion results. This is illustrated in Figure 5-9, where an op amp is used to drive the analog input of the MCP3302/04. This amplifier provides a low-impedance source for the converter input and a low-pass filter, which eliminates unwanted high-frequency noise. Values shown are for a 10 Hz Butterworth Low-Pass filter. Low-pass (anti-aliasing) filters can be designed using Microchip’s interactive FilterLab® software. FilterLab will calculate capacitor and resistor values, as well as determine the number of poles that are required for the application. For more detailed information on filtering signals, see AN699 “Anti-Aliasing, Analog Filters for Data Acquisition Systems”, at www.microchip.com. VDD 4.096V Reference 0.1 µF MCP1541 1 µF CL VREF IN+ MCP330X 7.86 k VIN 2.2 µF MCP601 + INDevice 4 0.1 µF 10 µF When laying out a printed circuit board for use with analog components, care should be taken to reduce noise wherever possible. A bypass capacitor from VDD to ground should always be used with this device and should be placed as close as possible to the device pin. A bypass capacitor value of 0.1 µF is recommended. Digital and analog traces on the board should be separated as much as possible, with no traces running underneath the device or the bypass capacitor. Extra precautions should be taken to keep traces with highfrequency signals (such as clock lines) as far as possible from analog traces. Use of an analog ground plane is recommended in order to keep the ground potential the same for all devices on the board. Providing VDD connections to devices in a “star” configuration can also reduce noise by eliminating current return paths and associated errors (see Figure 5-10). Layout tips for using the MCP3302, MCP3304, or other ADC devices, are available in AN688, “Layout Tips for 12-Bit A/D Converter Applications”, from www.microchip.com. VDD Connection 14.6 k 1 µF Device 1 FIGURE 5-9: The MCP601 Operational Amplifier is used to implement a 2nd order antialiasing filter for the signal being converted by the MCP3302/04. Device 3 Device 2 FIGURE 5-10: VDD traces arranged in a ‘Star’ configuration in order to reduce errors caused by current return paths. DS21697F-page 20  2011 Microchip Technology Inc. MCP3302/04 5.7 Utilizing the Digital and Analog Ground Pins The MCP3302/04 devices provide both digital and analog ground connections to provide another means of noise reduction. As shown in Figure 5-11, the analog and digital circuitry are separated internal to the device. This reduces noise from the digital portion of the device being coupled into the analog portion of the device. The two grounds are connected internally through the substrate which has a resistance of 5 -10Ω. If no ground plane is utilized, then both grounds must be connected to VSS on the board. If a ground plane is available, both digital and analog ground pins should be connected to the analog ground plane. If both an analog and a digital ground plane are available, both the digital and the analog ground pins should be connected to the analog ground plane, as shown in Figure 5-11. Following these steps will reduce the amount of digital noise from the rest of the board being coupled into the A/D Converter. VDD MCP3302/04 Digital Side -SPI Interface -Shift Register -Control Logic Analog Side -Sample Cap -Comparator -Capacitor Array Substrate 5 - 10 DGND AGND 0.1 µF Analog Ground Plane FIGURE 5-11: Separation of Analog and Digital Ground Pins.MCP3302/04.  2011 Microchip Technology Inc. DS21697F-page 21 MCP3302/04 NOTES: DS21697F-page 22  2011 Microchip Technology Inc. MCP3302/04 6.0 6.1 SERIAL COMMUNICATIONS Output Code Format The output code format is a binary two’s complement scheme, with a leading sign bit that indicates the sign of the output. If the IN+ input is higher than the INinput, the sign bit will be a zero. If the IN- input is higher, the sign bit will be a ‘1’. The diagram shown in Figure 6-1 shows the output code transfer function. In this diagram, the horizontal axis is the analog input voltage and the vertical axis is the output code of the ADC. It shows that when IN+ is equal to IN-, both the sign bit and the data word is zero. As IN+ gets larger with respect to IN-, the sign bit is a zero and the data word gets larger. The full scale output code is reached at +4095 when the input [(IN+) - (IN-)] reaches VREF - 1 LSB. When IN- is larger than IN+, the two’s complement output codes will be seen with the sign bit being a one. Some examples of analog input levels and corresponding output codes are shown in Table 6-1. TABLE 6-1: BINARY TWO’S COMPLEMENT OUTPUT CODE EXAMPLES. Analog Input Levels Sign Bit 0 0 0 0 0 1 1 1 1 Binary Data 1111 1111 1111 1111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 0000 0000 0001 0000 0000 0000 Decimal DATA +4095 +4094 +2 +1 0 -1 -2 -4095 -4096 Full Scale Positive (IN+)-(IN-)=VREF-1 LSB (IN+)-(IN-) = VREF-2 LSB IN+ = (IN-) +2 LSB IN+ = (IN-) +1 LSB IN+ = ININ+ = (IN-) - 1 LSB IN+ = (IN-) - 2 LSB IN+ IN= -VREF +1 LSB IN+ - IN- = -VREF Full Scale Negative  2011 Microchip Technology Inc. DS21697F-page 23 MCP3302/04 Output Code 0 + 1111 1111 1111 (+4095) 0 + 1111 1111 1110 (+4094) Positive Full Scale Output = VREF -1 LSB 0 + 0000 0000 0011 (+3) 0 + 0000 0000 0010 (+2) 0 + 0000 0000 0001 (+1) 0 + 0000 0000 0000 (0) IN+ > IN1 + 1111 1111 1111 (-1) 1 + 1111 1111 1110 (-2) 1 + 1111 1111 1101 (-3) -VREF IN+ < IN- VREF Analog Input Voltage IN+ - IN- 1 + 0000 0000 0001 (-4095) Negative Full Scale Output = -VREF 1 + 0000 0000 0000 (-4096) FIGURE 6-1: Output Code Transfer Function. clocks will output the result of the conversion with the sign bit first, followed by the 12 remaining data bits, as shown in Figure 6-2. Note that if the device is operating in the Single-ended mode, the sign bit will always be transmitted as a ‘0’. Data is always output from the device on the falling edge of the clock. If all 13 data bits have been transmitted, and the device continues to receive clocks while the CS is held low, the device will output the conversion result, LSB, first, as shown in Figure 6-3. If more clocks are provided to the device while CS is still low (after the LSB first data has been transmitted), the device will clock out zeros indefinitely. If necessary, it is possible to bring CS low and clock in leading zeros on the DIN line before the start bit. This is often done when dealing with microcontroller-based SPI ports that must send 8 bits at a time. Refer to Section 6.3 “Using the MCP3302/04 with Microcontroller (MCU) SPI Ports” for more details on using the MCP3302/04 devices with hardware SPI ports. 6.2 Communicating with the MCP3302 and MCP3304 Communication with the MCP3302/04 devices is done using a standard SPI-compatible serial interface. Initiating communication with either device is done by bringing the CS line low (see Figure 6-2). If the device was powered up with the CS pin low, it must be brought high and back low to initiate communication. The first clock received with CS low and DIN high will constitute a start bit. The SGL/DIFF bit follows the start bit and will determine if the conversion will be done using singleended or differential input mode. Each channel in Single-ended mode will operate as a 12-bit converter with a unipolar output. No negative codes will be output in Single-ended mode. The next three bits (D0, D1, and D2) are used to select the input channel configuration. Table 6-1 and Table 6-2 show the configuration bits for the MCP3302 and MCP3304, respectively. The device will begin to sample the analog input on the fourth rising edge of the clock after the start bit has been received. The sample period will end on the falling edge of the fifth clock following the start bit. After the D0 bit is input, one more clock is required to complete the sample and hold period (DIN is a “don’t care” for this clock). On the falling edge of the next clock, the device will output a low null bit. The next 13 DS21697F-page 24  2011 Microchip Technology Inc. MCP3302/04 TABLE 6-1: CONFIGURATION BITS FOR THE MCP3302 Input Configuration single ended single ended single ended single ended differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ TABLE 6-2: Control Bit Selections Single /Diff 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 CONFIGURATION BITS FOR THE MCP3304 Input Configuration single ended single ended single ended single ended single ended single ended single ended single ended differential differential differential differential differential differential differential differential Channel Selection CH0 CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH0 = IN+ CH1 = INCH0 = INCH1 = IN+ CH2 = IN+ CH3 = INCH2 = INCH3 = IN+ CH4 = IN+ CH5 = INCH4 = INCH5 = IN+ CH6 = IN+ CH7 = INCH6 = INCH7 = IN+ Control Bit Selections Single D2* D1 /Diff 1 1 1 1 0 0 0 0 X X X X X X X X 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 D1 D0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 *D2 is don’t care for MCP3302  2011 Microchip Technology Inc. DS21697F-page 25 MCP3302/04 TSAMPLE TCSH CS TSUCS CLK TSAMPLE DIN Start SGL/ D2 D1 D0 DIFF Don’t Care Start SGL/ DIFF D2 DOUT HI-Z Null SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 * Bit HI-Z TCONV TACQ TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output LSB first data, followed by zeros indefinitely. See Figure 6-3 below. ** TDATA: during this time, the bias current and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out the LSB-first data or zeros. † When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 6-2: Communication with MCP3302/04 (MSB first Format). TSAMPLE CS TSUCS Power Down TCSH CLK Start DIN D2 D1 D0 SGL/ DIFF Don’t Care DOUT HI-Z TACQ Null Bit SB† B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 SB* HI-Z (MSB) TCONV TDATA ** * After completing the data transfer, if further clocks are applied with CS low, the A/D Converter will output zeros indefinitely. ** TDATA: During this time, the bias circuit and the comparator power down while the reference input becomes a high-impedance node, leaving the CLK running to clock out LSB first data or zeroes. † When operating in Single-ended mode, the sign bit will always be transmitted as a ‘0’. FIGURE 6-3: Communication with MCP3302/04 (LSB first Format). DS21697F-page 26  2011 Microchip Technology Inc. MCP3302/04 6.3 Using the MCP3302/04 with Microcontroller (MCU) SPI Ports With most microcontroller SPI ports, it is required to send groups of eight bits. It is also required that the microcontroller SPI port be configured to clock out data on the falling edge of clock and latch data in on the rising edge. Because communication with the MCP3302 and MCP3304 devices may not need multiples of eight clocks, it will be necessary to provide more clocks than are required. This is usually done by sending ‘leading zeros’ before the start bit. For example, Figure 6-4 and Figure 6-5 show how the MCP3302/04 devices can be interfaced to a MCU with a hardware SPI port. Figure 6-4 depicts the operation shown in SPI Mode 0,0, which requires that the SCLK from the MCU idles in the ‘low’ state, while Figure 6-5 shows the similar case of SPI Mode 1,1, where the clock idles in the ‘high’ state. As shown in Figure 6-4, the first byte transmitted to the A/D Converter contains 6 leading zeros before the start bit. Arranging the leading zeros this way produces the 13 data bits to fall in positions easily manipulated by the MCU. The sign bit is clocked out of the A/D Converter on the falling edge of clock number 11, followed by the remaining data bits (MSB first). After the second eight clocks have been sent to the device, the MCU receive buffer will contain 2 unknown bits (the output is at highimpedance for the first two clocks), the null bit, the sign bit, and the 4 highest order bits of the conversion. After the third byte has been sent to the device, the receive register will contain the lowest order eight bits of the conversion results. Easier manipulation of the converted data can be obtained by using this method. Figure 6-5 shows the same situation in SPI Mode 1,1, which requires that the clock idles in the high state. As with mode 0,0, the A/D Converter outputs data on the falling edge of the clock and the MCU latches data from the A/D Converter in on the rising edge of the clock. CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN DOUT Start SGL/ D2 DIFF D1 D0 Don’t Care NULL SB B11 B10 B9 BIT HI-Z Start B8 B7 B6 B5 B4 B3 B2 B1 B0 Bit MCU Transmitted Data 1 SGL/ D2 D1 (Aligned with falling 0 0 0 0 DIFF edge of clock) MCU Received Data ? ? ? ? ? ? ? ? (Aligned with rising edge of clock) ? = Unknown Bits X = Don’t Care Bits Data stored into MCU receive register after transmission of first 8 bits DO X X X X X X X X X X X X X X X ? 0 ? (Null) SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-4: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 0,0: SCLK idles low).  2011 Microchip Technology Inc. DS21697F-page 27 MCP3302/04 CS SCLK MCU latches data from A/D Converter on rising edges of SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Data is clocked out of A/D Converter on falling edges DIN DOUT MCU Transmitted Data (Aligned with falling 0 edge of clock) MCU Received Data (Aligned with rising edge of clock) ? = Unknown Bits X = Don’t Care Bits ? Start SGL/ DIFF D2 D1 D0 Don’t Care Don’t Care HI-Z Start Bit 0 0 0 1 SGL/ DIFF NULL SB B11 B10 B9 BIT B8 B7 B6 B5 B4 B3 B2 B1 B0 D2 D1 DO X X X X X X X X X X X X X X X ? ? ? ? ? ? ? ? ? 0 (Null) SB B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0 Data stored into MCU receive register after transmission of first 8 bits Data stored into MCU receive register after transmission of second 8 bits Data stored into MCU receive register after transmission of last 8 bits FIGURE 6-5: SPI Communication with the MCP3302/04 using 8-bit segments (Mode 1,1: SCLK idles high). DS21697F-page 28  2011 Microchip Technology Inc. MCP3302/04 7.0 7.1 PACKAGING INFORMATION Package Marking Information 14-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3302-B I/P^^ e3 1112256 14-Lead SOIC (150 mil) Example: XXXXXXXXXXX XXXXXXXXXXX YYWWNNN MCP3302-B e3 I/SL^^ 1112256 14-Lead TSSOP (4.4mm) Example: XXXXXXXX XYWW NNN 3302-C I112 256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2011 Microchip Technology Inc. DS21697F-page 29 MCP3302/04 7.2 Package Marking Information (Continued) 16-Lead PDIP (300 mil) XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example: MCP3304-B I/P e3 1112256 16-Lead SOIC (150 mil) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN MCP3304-B XXXIIXXXXXXX I/SL e3 1112256 DS21697F-page 30  2011 Microchip Technology Inc. MCP3302/04 /HDG 3ODVWLF 'XDO ,Q/LQH 3 ±  PLO %RG\ >3',3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ N NOTE 1 E1 1 2 3 D E A A2 L A1 b b1 e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 1 H $ $ $ ( ( ' / F E E ±          0,1 ,1&+(6 120   %6& ±  ±          ±        0$; c eB 2YHUDOO 5RZ 6SDFLQJ † H% ± ±  1RWHV  3LQ  YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWK WKH KDWFKHG DUHD  † 6LJQLILFDQW &KDUDFWHULVWLF  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60(