MCP3425A3TECH

MCP3425 16-Bit Analog-to-Digital Converter with I2C Interface and On-Board Reference Features • 16-bit ΔΣ ADC in a SOT-23-6 package • Differential input operation • Self calibration of Internal Offset and Gain per each conversion • On-board Voltage Reference: - Accuracy: 2.048V ± 0.05% • On-board Programmable Gain Amplifier (PGA): - Gains of 1,2, 4 or 8 • On-board Oscillator • INL: 10 ppm of FSR (FSR = 4.096V/PGA) • Programmable Data Rate Options: - 15 SPS (16 bits) - 60 SPS (14 bits) - 240 SPS (12 bits) • One-Shot or Continuous Conversion Options • Low current consumption: - 145 µA typical (VDD= 3V, Continuous Conversion) • One-Shot Conversion (1 SPS) with VDD = 3V: - 9.7 µA typical with 16 bit mode - 2.4 µA typical with 14 bit mode - 0.6 µA typical with 12 bit mode • Supports I2C Serial Interface: - Standard, Fast and High Speed Modes • Single Supply Operation: 2.7V to 5.5V • Extended Temperature Range: -40°C to 125°C Description The MCP3425 is a single channel low-noise, high accuracy ΔΣ A/D converter with differential inputs and up to 16 bits of resolution in a small SOT-23-6 package. The on-board precision 2.048V reference voltage enables an input range of ±2.048V differentially (Δ voltage = 4.096V). The device uses a two-wire I2C compatible serial interface and operates from a single 2.7V to 5.5V power supply. The MCP3425 device performs conversion at rates of 15, 60, or 240 samples per second (SPS) depending on the user controllable configuration bit settings using the two-wire I2C serial interface. This device has an onboard programmable gain amplifier (PGA). The user can select the PGA gain of x1, x2, x4, or x8 before the analog-to-digital conversion takes place. This allows the MCP3425 device to convert a smaller input signal with high resolution. The device has two conversion modes: (a) Continuous mode and (b) One-Shot mode. In One-Shot mode, the device enters a low current standby mode automatically after one conversion. This reduces current consumption greatly during idle periods. The MCP3425 device can be used for various high accuracy analog-to-digital data conversion applications where design simplicity, low power, and small footprint are major considerations. Block Diagram VSS VDD Typical Applications • Portable Instrumentation • Weigh Scales and Fuel Gauges • Temperature Sensing with RTD, Thermistor, and Thermocouple • Bridge Sensing for Pressure, Strain, and Force. Voltage Reference (2.048V) Gain = 1, 2, 4, or 8 VIN+ PGA Top View VINΔΣ ADC Converter Clock Oscillator VREF Package Types SOT-23-6 VIN+ VSS SCL 1 2 3 6 5 4 VINVDD SDA I2C Interface SCL SDA © 2007 Microchip Technology Inc. DS22072A-page 1 MCP3425 1.0 1.1 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† VDD...................................................................................7.0V All inputs and outputs w.r.t VSS ............... –0.3V to VDD+0.3V Differential Input Voltage ...................................... |VDD - VSS| Output Short Circuit Current .................................Continuous Current at Input Pins ....................................................±2 mA Current at Output and Supply Pins ............................±10 mA Storage Temperature.....................................-65°C to +150°C Ambient Temp. with power applied ...............-55°C to +125°C ESD protection on all pins ................ ≥ 6 kV HBM, ≥ 400V MM Maximum Junction Temperature (TJ) . .........................+150°C †Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Analog Inputs Differential Input Range Common-Mode Voltage Range (absolute) (Note 1) Differential Input Impedance (Note 2) Sym Min Typ Max Units Conditions — VSS-0.3 ZIND (f) ZINC (f) — — ±2.048/PGA — 2.25/PGA 25 — VDD+0.3 — — V V MΩ MΩ VIN = VIN+ - VIN- During normal mode operation PGA = 1, 2, 4, 8 Common Mode input Impedance System Performance Resolution and No Missing Codes (Note 8) Data Rate (Note 3) 12 14 16 DR 176 44 11 — — — 240 60 15 2.5 10 2.048 0.1 0.1 15 — — — 328 82 20.5 — — — — — — Bits Bits Bits SPS SPS SPS µVRMS DR = 240 SPS DR = 60 SPS DR = 15 SPS S1,S0 = ‘00’, (12 bits mode) S1,S0 = ‘01’, (14 bits mode) S1,S0 = ‘10’, (16 bits mode) TA = 25°C, DR = 15 SPS, PGA = 1, VIN = 0 DR = 15 SPS (Note 6) Output Noise Integral Nonlinearity (Note 4) Internal Reference Voltage Gain Error (Note 5) — INL VREF — — — — — ppm of FSR V % % ppm/°C PGA = 1, DR = 15 SPS Between any 2 PGA gains PGA=1, DR = 15 SPS PGA Gain Error Match (Note 5) Gain Error Drift Note 1: 2: 3: 4: 5: 6: 7: 8: (Note 5) Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. This input impedance is due to 3.2 pF internal input sampling capacitor. The total conversion speed includes auto-calibration of offset and gain. INL is the difference between the endpoints line and the measured code at the center of the quantization band. Includes all errors from on-board PGA and VREF. Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. This parameter is ensured by characterization and not 100% tested. This parameter is ensured by design and not 100% tested. DS22072A-page 2 © 2007 Microchip Technology Inc. MCP3425 ELECTRICAL CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, all parameters apply for TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. All ppm units use 2*VREF as full-scale range. Parameters Offset Error Offset Drift vs. Temperature Common-Mode Rejection Sym VOS Min — — — — Gain vs. VDD Power Supply Rejection at DC Power Requirements Voltage Range Supply Current during Conversion Supply Current during Standby Mode High level input voltage Low level input voltage Low level output voltage Hysteresis of Schmitt Trigger for inputs (Note 7) Supply Current when I2C bus line is active Input Leakage Current 2 Typ 30 300 100 105 5 95 Max — — — — — — Units µV nV/°C dB dB ppm/V dB Conditions Tested at PGA = 1 VDD = 5.0V and DR = 15 SPS VDD = 5.0V at DC and PGA =1, at DC and PGA =8, TA = +25°C TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 TA = +25°C, VDD = 2.7V to 5.5V, PGA = 1 — — VDD IDDA IDDS 2.7 — — — — 155 145 0.1 5.5 190 — 0.5 V µA µA µA VDD = 5.0V VDD = 3.0V I2C Digital Inputs and Digital Outputs VIH VIL VOL VHYST IDDB IILH IILL Pin Capacitance and I C Bus Capacitance Pin capacitance I2C Bus Capacitance Thermal Characteristics Specified Temperature Range Operating Temperature Range Storage Temperature Range Note 1: 2: 3: 4: 5: 6: 7: 8: TA TA TA -40 -40 -65 — — — +85 +125 +150 °C °C °C CPIN Cb — — — — 10 400 pF pF 0.7 VDD — — 0.05VDD — — -1 — — — — — — — VDD 0.3VDD 0.4 — 10 1 — V V V V µA µA µA VIH = 5.5V VIL = GND IOL = 3 mA, VDD = +5.0V fSCL = 100 kHz Any input voltage below or greater than this voltage causes leakage current through the ESD diodes at the input pins. This parameter is ensured by characterization and not 100% tested. This input impedance is due to 3.2 pF internal input sampling capacitor. The total conversion speed includes auto-calibration of offset and gain. INL is the difference between the endpoints line and the measured code at the center of the quantization band. Includes all errors from on-board PGA and VREF. Full Scale Range (FSR) = 2 x 2.048/PGA = 4.096/PGA. This parameter is ensured by characterization and not 100% tested. This parameter is ensured by design and not 100% tested. © 2007 Microchip Technology Inc. DS22072A-page 3 MCP3425 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. 0.005 0.004 0.003 PGA = 1 Integral Nonlinearity (% FSR) 12 10 Noise (µV, rms) 8 PGA = 2 PGA = 1 0.002 0.001 PGA = 4 PGA = 8 6 4 2 PGA = 8 PGA = 4 PGA = 2 0 2.5 3 3.5 4 VDD (V) 4.5 5 5.5 0 -100% -50% 0% 50% 100% Input Voltage (% of Full Scale) FIGURE 2-1: (VDD). 0.005 0.004 INL (FSR %) 0.003 0.002 0.001 2.7V INL vs. Supply Voltage FIGURE 2-4: Noise vs. Input Voltage. 3.0 2.0 Total Error (mV) 1.0 0.0 -1.0 -2.0 5V PGA = 1 PGA = 2 PGA = 4 PGA = 8 0 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) -3.0 -100 -75 -50 -25 0 25 50 75 100 Input Voltage (% of Full-Scale) FIGURE 2-2: INL vs. Temperature. FIGURE 2-5: 0.4 Gain Error (% of FSR) Total Error vs. Input Voltage. 60 Offset Error (µV) 40 20 0 -20 -40 -60 -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (°C ) PGA = 8 PGA = 4 PGA = 2 PGA = 1 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -60 -40 -20 0 20 40 60 PGA = 1 PGA = 2 VDD = 5.0V PGA = 4 PGA = 8 80 100 120 140 Temperature (°C) FIGURE 2-6: FIGURE 2-3: Temperature. Offset Error vs. Gain Error vs. Temperature. DS22072A-page 4 © 2007 Microchip Technology Inc. MCP3425 Note: Unless otherwise indicated, TA = -40°C to +85°C, VDD = +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. 220 200 IDDA (µA) 180 160 140 120 100 -60 -40 -20 0 20 40 60 o 5 VDD = 5V Oscillator Drift (%) 4 3 2 VDD = 2.7V VDD = 2.7V 1 0 -1 -60 -40 -20 0 20 40 60 80 100 120 140 VDD = 5.0V 80 100 120 140 Temperature ( C) Temperature (°C) FIGURE 2-7: IDDA vs. Temperature. FIGURE 2-10: 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 0.1 1 OSC Drift vs. Temperature. 600 Magnitude (dB) Data Rate = 15 SPS 500 IDDS (nA) 400 300 200 100 0 -60 -40 -20 0 20 40 60 80 100 120 140 o VDD = 5V VDD = 2.7V 10 100 1k 1000 10k 10000 Temperature ( C) Input Signal Frequency (Hz) FIGURE 2-8: 9 8 7 6 5 4 3 2 1 0 IDDS vs. Temperature. FIGURE 2-11: Frequency Response. VDD = 5V VDD = 4.5V IDDB (µA) VDD = 3.3V VDD = 2.7V -60 -40 -20 0 20 40 60 80 100 120 140 Temperature (oC) FIGURE 2-9: IDDB vs. Temperature. © 2007 Microchip Technology Inc. DS22072A-page 5 MCP3425 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No 1 2 3 4 5 6 PIN FUNCTION TABLE Sym VIN+ VSS SCL SDA VDD VINNon-Inverting Analog Input Pin Ground Pin Serial Clock Input Pin of the I2C Interface Bidirectional Serial Data Pin of the I2C Interface Positive Supply Voltage Pin Inverting Analog Input Pin (printed circuit board), it is highly recommended that the VSS pin be tied to the analog ground path or isolated within an analog ground plane of the circuit board. Function 3.1 Analog Inputs (VIN+, VIN-) VIN+ and VIN- are differential signal input pins. The MCP3425 device accepts a fully differential analog input signal which is connected on the VIN+ and VINinput pins. The differential voltage that is converted is defined by VIN = (VIN+ - VIN-) where VIN+ is the voltage applied at the VIN+ pin and VIN- is the voltage applied at the VIN- pin. The input signal level is amplified by the programmable gain amplifier (PGA) before the conversion. The differential input voltage should not exceed an absolute of (VREF/PGA) for accurate measurement, where VREF is the internal reference voltage (2.048V) and PGA is the PGA gain setting. The converter output code will saturate if the input range exceeds (VREF/PGA). The absolute voltage range on each of the differential input pins is from VSS-0.3V to VDD+0.3V. Any voltage above or below this range will cause leakage currents through the Electrostatic Discharge (ESD) diodes at the input pins. This ESD current can cause unexpected performance of the device. The common mode of the analog inputs should be chosen such that both the differential analog input range and the absolute voltage range on each pin are within the specified operating range defined in Section 1.0 “Electrical Characteristics” and Section 4.0 “Description of Device Operation”. 3.3 Serial Clock Pin (SCL) SCL is the serial clock pin of the I2C interface. The MCP3425 acts only as a slave and the SCL pin accepts only external serial clocks. The input data from the Master device is shifted into the SDA pin on the rising edges of the SCL clock and output from the MCP3425 occurs at the falling edges of the SCL clock. The SCL pin is an open-drain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SCL pin. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. 3.4 Serial Data Pin (SDA) 3.2 Supply Voltage (VDD, VSS) VDD is the power supply pin for the device. This pin requires an appropriate bypass capacitor of about 0.1 µF (ceramic) to ground. An additional 10 µF capacitor (tantalum) in parallel is also recommended to further attenuate high frequency noise present in some application boards. The supply voltage (VDD) must be maintained in the 2.7V to 5.5V range for specified operation. VSS is the ground pin and the current return path of the device. The user must connect the VSS pin to a ground plane through a low impedance connection. If an analog ground path is available in the application PCB SDA is the serial data pin of the I2C interface. The SDA pin is used for input and output data. In read mode, the conversion result is read from the SDA pin (output). In write mode, the device configuration bits are written (input) though the SDA pin. The SDA pin is an opendrain N-channel driver. Therefore, it needs a pull-up resistor from the VDD line to the SDA pin. Except for start and stop conditions, the data on the SDA pin must be stable during the high period of the clock. The high or low state of the SDA pin can only change when the clock signal on the SCL pin is low. Refer to Section 5.3 “I2C Serial Communications” for more details of I2C Serial Interface communication. DS22072A-page 6 © 2007 Microchip Technology Inc. MCP3425 4.0 4.1 DESCRIPTION OF DEVICE OPERATION General Overview VDD 2.2V 2.0V 300 µS The MCP3425 is a low-power, 16-Bit Delta-Sigma A/D converter with an I2C serial interface. The device contains an on-board voltage reference (2.048V), programmable gain amplifier (PGA), and internal oscillator. The user can select 12, 14, or 16 bit conversion by setting the configuration register bits. The device can be operated in Continuous Conversion or One-Shot Conversion mode. In the Continuous Conversion mode, the device converts the inputs continuously. While in the One-Shot Conversion mode, the device converts the input one time and stays in the low-power standby mode until it receives another command for a new conversion. During the standby mode, the device consumes less than 0.1 µA typical. Reset Start-up Normal Operation Reset Time FIGURE 4-1: POR Operation. 4.3 Internal Voltage Reference The device contains an on-board 2.048V voltage reference. This reference voltage is for internal use only and not directly measurable. The specifications of the reference voltage are part of the device’s gain and drift specifications. Therefore, there is no separate specification for the on-board reference. 4.2 Power-On-Reset (POR) The device contains an internal Power-On-Reset (POR) circuit that monitors power supply voltage (VDD) during operation. This circuit ensures correct device start-up at system power-up and power-down events. The POR has built-in hysteresis and a timer to give a high degree of immunity to potential ripples and noises on the power supply. A 0.1 µF decoupling capacitor should be mounted as close as possible to the VDD pin for additional transient immunity. The threshold voltage is set at 2.2V with a tolerance of approximately ±5%. If the supply voltage falls below this threshold, the device will be held in a reset condition. The typical hysteresis value is approximately 200 mV. The POR circuit is shut-down during the low-power standby mode. Once a power-up event has occurred, the device requires additional delay time (approximately 300 µs) before a conversion can take place. During this time, all internal analog circuitries are settled before the first conversion occurs. Figure 4-1 illustrates the conditions for power-up and power-down events under typical start-up conditions. When the device powers up, it automatically resets and sets the configuration bits to default settings. The default configuration bit conditions are a PGA gain of 1 V/V and a conversion speed of 240 SPS in Continuous Conversion mode. When the device receives an I2C General Call Reset command, it performs an internal reset similar to a Power-On-Reset event. 4.4 Analog Input Channel The differential analog input channel has a switched capacitor structure. The internal sampling capacitor (3.2 pF) is charged and discharged to process a conversion. The charging and discharging of the input sampling capacitor creates dynamic input currents at the VIN+ and VIN- input pins, which is inversely proportional to the internal sampling capacitor and internal frequency. The current is also a function of the differential input voltages. Care must be taken in setting the common-mode voltage and input voltage ranges so that the input limits do not exceed the ranges specified in Section 1.0 “Electrical Characteristics”. 4.5 Digital Output Code The digital output code produced by the MCP3425 is a function of PGA gain, input signal, and internal reference voltage. In a fixed setting, the digital output code is proportional to the voltage difference between the two analog inputs. The output data format is a binary two’s complement. With this code scheme, the MSB can be considered a sign indicator. When the MSB is a logic ‘0’, it indicates a positive value. When the MSB is a logic ‘1’, it indicates a negative value. The following is an example of the output code: (a) for a negative full-scale input voltage: 100...000 (b) for a zero differential input voltage: 000...000 (c) for a positive full-scale input voltage: 011...111. The MSB is always transmitted first through the serial port. The number of data bits for each conversion is 16, 14, or 12 bits depending on the conversion mode selection. © 2007 Microchip Technology Inc. DS22072A-page 7 MCP3425 The output codes will not roll-over if the input voltage exceeds the maximum input range. In this case, the code will be locked at 0111...11 for all voltages greater than +(VREF - 1 LSB) and 1000...00 for voltages less than -VREF. Table 4-2 shows an example of output codes of various input levels using 16 bit conversion mode. Table 4-3 shows an example of minimum and maximum codes for each data rate option. The output code is given by: TABLE 4-3: Number of Bits 12 14 16 Note: MINIMUM AND MAXIMUM CODES Data Rate 240 SPS 60 SPS 15 SPS Minimum Code -2048 -8192 -32768 Maximum Code 2047 8191 32767 Maximum n-bit code = 2n-1 - 1 Minimum n-bit code = -1 x 2n-1 EQUATION 4-1: ( V IN + – V IN -) Output Code = ( Max Code + 1 ) × -------------------------------------2.048V 4.6 Self-Calibration The LSB of the code is given by: EQUATION 4-2: Where: LSB = 2 × 2.048V -------------------------N 2 The device performs a self-calibration of offset and gain for each conversion. This provides reliable conversion results from conversion-to-conversion over variations in temperature as well as power supply fluctuations. 4.7 Input Impedance N = number of bits TABLE 4-1: LSB SIZE OF VARIOUS BIT CONVERSION MODES LSB (V) 1 mV 250 µV 62.5 µV Bit Resolutions 12 bits 14 bits 16 bits The MCP3425 uses a switched-capacitor input stage using a 3.2 pF sampling capacitor. This capacitor is switched (charged and discharged) at a rate of the sampling frequency that is generated by the on-board clock. The differential mode impedance varies with the PGA settings. The typical differential input impedance during a normal mode operation is given by: ZIN(f) = 2.25 MΩ/PGA Since the sampling capacitor is only switching to the input pins during a conversion process, the above input impedance is only valid during conversion periods. In a low power standby mode, the above impedance is not presented at the input pins. Therefore, only a leakage current due to ESD diode is presented at the input pins. The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can increase the system performance errors such as offset, gain, and integral nonlinearity (INL) errors. Ideally, the input source impedance should be zero. This can be achievable by using an operational amplifier with a closed-loop output impedance of tens of ohms. TABLE 4-2: EXAMPLE OF OUTPUT CODE FOR 16 BITS Digital Code 0111111111111111 0111111111111111 0000000000000010 0000000000000001 0000000000000000 1111111111111111 1111111111111110 1000000000000000 1000000000000000 Input Voltage (V) ≥ VREF VREF - 1 LSB 2 LSB 1 LSB 0 -1 LSB -2 LSB - VREF < -VREF DS22072A-page 8 © 2007 Microchip Technology Inc. MCP3425 4.8 Aliasing and Anti-aliasing Filter Aliasing occurs when the input signal contains timevarying signal components with frequency greater than half the sample rate. In the aliasing conditions, the device can output unexpected output codes. For applications that are operating in electrical noise environments, the time-varying signal noise or high frequency interference components can be easily added to the input signals and cause aliasing. Although the MCP3425 device has an internal first order sinc filter, its’ filter response may not give enough attenuation to all aliasing signal components. To avoid the aliasing, an external anti-aliasing filter, which can be accomplished with a simple RC low-pass filter, is typically used at the input pins. The low-pass filter cuts off the high frequency noise components and provides a band-limited input signal to the MCP3425 input pins. © 2007 Microchip Technology Inc. DS22072A-page 9 MCP3425 5.0 5.1 USING THE MCP3425 DEVICE Operating Modes 5.1.2 ONE-SHOT CONVERSION MODE (O/C BIT = 0) The user operates the device by setting up the device configuration register and reads the conversion data using serial I2C interface commands. The MCP3425 operates in two modes: (a) Continuous Conversion Mode or (b) One-Shot Conversion Mode (single conversion). The selection is made by setting the O/C bit in the Configuration Register. Refer to Section 5.2 “Configuration Register” for more information. Once the One-Shot Conversion (single conversion) Mode is selected, the device performs a conversion, updates the Output Data register, clears the data ready flag (RDY = 0), and then enters a low power standby mode. A new One-Shot Conversion is started again when the device receives a new write command with RDY = 1. This One-Shot Conversion Mode is recommended for low power operating applications. During the low current standby mode, the device consumes less than 1 µA typical. For example, if the device converts only one time per second with 16 bit resolution, the total current draw is only about one fourth of the draws in continuous mode. In this example, the device consumes approximately 9.7 µA (= ~145 µA/15 SPS), if the device performs only one conversion per second (1 SPS) in 16-bit conversion mode with 3V power supply. 5.1.1 CONTINUOUS CONVERSION MODE (O/C BIT = 1) The MCP3425 device performs a Continuous Conversion if the O/C bit is set to logic “high”. Once the conversion is completed, the result is placed at the output data register. The device immediately begins another conversion and overwrites the output data register with the most recent data. The device also clears the data ready flag (RDY bit = 0) when the conversion is completed. The device sets the ready flag bit (RDY bit = 1), if the latest conversion result has been read by the Master. DS22072A-page 10 © 2007 Microchip Technology Inc. MCP3425 5.2 Configuration Register The MCP3425 has an 8-bit wide configuration register to select for: PGA gain, conversion rate, and conversion mode. This register allows the user to change the operating condition of the device and check the status of the device operation. The user can rewrite the configuration byte any time during the device operation. Register 5-1 shows the configuration register bits. REGISTER 5-1: R/W-1 RDY 1* bit 7 CONFIGURATION REGISTER R/W-0 C1 0* R/W-0 C0 0* R/W-1 O/C 1* R/W-0 S1 0* R/W-0 S0 0* R/W-0 G1 0* R/W-0 G0 0* bit 0 * Default Configuration after Power-On Reset Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 7 RDY: Ready Bit This bit is the data ready flag. In read mode, this bit indicates if the output register has been updated with a new conversion. In One-Shot Conversion mode, writing this bit to “1” initiates a new conversion. Reading RDY bit with the read command: 1 = Output register has not been updated. 0 = Output register has been updated with the latest conversion data. Writing RDY bit with the write command: Continuous Conversion mode: No effect One-Shot Conversion mode: 1 = Initiate a new conversion. 0 = No effect. bit 6-5 bit 4 C1-C0: Channel Selection Bits These are the Channel Selection bits, but not used in the MCP3425 device. O/C: Conversion Mode Bit 1 = Continuous Conversion Mode. Once this bit is selected, the device performs data conversions continuously. 0 = One-Shot Conversion Mode. The device performs a single conversion and enters a low power standby mode until it receives another write/read command. S1-S0: Sample Rate Selection Bit 00 = 240 SPS (12 bits), 01 = 60 SPS (14 bits), 10 = 15 SPS (16 bits) G1-G0: PGA Gain Selector Bits 00 = 1 V/V, 01 = 2 V/V, 10 = 4 V/V, 11 = 8 V/V bit 3-2 bit 1-0 © 2007 Microchip Technology Inc. DS22072A-page 11 MCP3425 In read mode, the RDY bit in the configuration byte indicates the state of the conversion: (a) RDY = 1 indicates that the data bytes that have just been read were not updated from the previous conversion. (b) RDY = 0 indicates that the data bytes that have just been read were updated. If the configuration byte is read repeatedly by clocking continuously after the first read, the state of the RDY bit indicates whether the device is ready with new conversion data. See Figure 5-2. For example, RDY = 0 means new conversion data is ready for reading. In this case, the user can send a stop bit to exit the current read operation and send a new read command to read out updated conversion data. See Figures 5-2 and 5-2 for reading conversion data. The user can rewrite the configuration byte any time for a new setting. Tables 5-1 and 5-2 show the examples of the configuration bit operation. 5.3 I2C Serial Communications The MCP3425 device communicates with Master (microcontroller) through a serial I2C (Inter-Integrated Circuit) interface and supports standard (100 kbits/ sec), fast (400 kbits/sec) and high-speed (3.4 Mbits/ sec) modes. The serial I2C is a bidirectional 2-wire data bus communication protocol using open-drain SCL and SDA lines. The MCP3425 can only be addressed as a slave. Once addressed, it can receive configuration bits or transmit the latest conversion results. The serial clock pin (SCL) is an input only and the serial data pin (SDA) is bidirectional. An example of a hardware connection diagram is shown in Figure 6-1. The Master starts communication by sending a START bit and terminates the communication by sending a STOP bit. The first byte after the START bit is always the address byte of the device, which includes the device code, the address bits, and the R/W bit. The device code for the MCP3425 device is 1101. The address bits (A2, A1, A0) are pre-programmed at the factory. In general, the address bits are specified by the customer when they order the device. The three address bits are programmed to “000” at the factory, if they are not specified by the customer. Figure 5-1 shows the details of the MCP3425 address byte. During a low power standby mode, SDA and SCL pins remain at a floating condition. More details of the I2C bus characteristic is described in Section 5.6 “I2C Bus Characteristics”. TABLE 5-1: R/W 0 CONFIGURATION BITS FOR WRITING Operation No effect if all other bits remain the same - operation continues with the previous settings Initiate One-Shot Conversion Initiate Continuous Conversion Initiate Continuous Conversion 0 O/C RDY 0 0 0 0 0 1 1 1 0 1 TABLE 5-2: R/W 1 CONFIGURATION BITS FOR READING Operation New conversion data in OneShot conversion mode has been just read. The RDY bit remains low until set by a new write command. One-Shot Conversion is in progress, The conversion data is not updated yet. The RDY bit stays high. New conversion data in Continuous Conversion mode has been just read. The RDY bit changes to high after this read. The conversion data in Continuous Conversion mode was already read. The latest conversion data is not ready. The RDY bit stays high until a new conversion is completed. 0 O/C RDY 0 5.3.1 DEVICE ADDRESSING 1 0 1 1 1 0 1 1 1 The address byte is the first byte received following the START condition from the Master device. The MCP3425 device code is 1101. The device code is followed by three address bits (A2, A1, A0) which are programmed at the factory. The three address bits allow up to eight MCP3425 devices on the same data bus line. The (R/W) bit determines if the Master device wants to read the conversion data or write to the Configuration register. If the (R/W) bit is set (read mode), the MCP3425 outputs the conversion data in the following clocks. If the (R/W) bit is cleared (write mode), the MCP3425 expects a configuration byte in the following clocks. When the MCP3425 receives the correct address byte, it outputs an acknowledge bit after the R/W bit. Figure 5-1 shows the MCP3425 address byte. See Figure 5-2 for the read operation and Figure 5-3 for the write operation of the device. DS22072A-page 12 © 2007 Microchip Technology Inc. MCP3425 Acknowledge bit Start bit Read/Write bit Address Address Byte Address Device Code Address Bits (Note 1) R/W ACK The configuration byte follows the output data byte. The device outputs the configuration byte as long as the SCL pulses are received. The device terminates the current outputs when it receives a Not-Acknowledge (NAK), a repeated start or a stop bit at any time during the output bit stream. It is not required to read the configuration byte. However, the user may read the configuration byte to check the RDY bit condition to confirm whether the just received data bytes are updated conversion data. The user may continuously send clock (SCL) to repeatedly read the configuration bytes to check the RDY bit status. Figures 5-2 and 5-2 show the timing diagrams of the reading. 1 Note 1: 1 0 1 X X X Specified by customer and programmed at the factory. If not specified by the customer, programmed to ‘000’. 5.3.3 WRITING A CONFIGURATION BYTE TO THE DEVICE FIGURE 5-1: 5.3.2 MCP3425 Address Byte. READING DATA FROM THE DEVICE When the Master sends a read command (R/W = 1), the MCP3425 outputs the conversion data bytes and configuration byte. Each byte consists of 8 bits with one acknowledge (ACK) bit. The ACK bit after the address byte is issued by the MCP3425 and the ACK bits after each conversion data bytes are issued by the Master. When the device receives a read command, it outputs two data bytes followed by a configuration register. In 16 bit-conversion mode, the MSB of the first data byte is the MSB (D15) of the conversion data. In 14-bit conversion mode, the first two bits in the first data byte can be ignored (they are the MSB of the conversion data), and the 3rd bit (D13) is the MSB of the conversion data. In 12-bit conversion mode, the first four bits can be ignored (they are the MSB of the conversion data), and the 5th bit (D11) of the byte represents the MSB of the conversion data. Table 5-3 shows an example of the conversion data output of each conversion mode. When the Master sends an address byte with the R/W bit low (R/W = 0), the MCP3425 expects one configuration byte following the address. Any byte sent after this second byte will be ignored. The user can change the operating mode of the device by writing the configuration register bits. If the device receives a write command with a new configuration setting, the device immediately begins a new conversion and updates the conversion data. TABLE 5-3: Conversion Mode EXAMPLE OF CONVERSION DATA OUTPUT OF EACH CONVERSION MODE Conversion Data Output 16-bits MD14~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 14-bits MMMD12~D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte 12-bits MMMMMD10D9D8 (1st data byte) - D7 ~ D0 (2nd data byte) - Configuration byte Note: M is MSB of the data byte. © 2007 Microchip Technology Inc. DS22072A-page 13 1 9 1 1 9 9 1 9 FIGURE 5-2: DS22072A-page 14 0 R/W ACK by MCP3425 2nd Byte Middle Data Byte 3rd Byte Lower Data Byte ACK by Master ACK by Master RDY O/C 1 A2 A1 A0 D 15 D 14 D 13 D 12 D 11 D 10 D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 C 1 C 0 S 1 S 0 G 1 G 0 ACK by Master 4th Byte Configuration Byte (Optional) 1 9 C 1 RDY C 0 O/C Nth Repeated Byte: Configuration Byte (Optional) S 1 S 0 G 1 G 0 NAK by Master Stop Bit by Master MCP3425 SCL SDA 1 1 Start Bit by Master Timing Diagram For Reading From The MCP3425. 1st Byte MCP3425 Address Byte © 2007 Microchip Technology Inc. Note: – MCP3425 device code is 1101. – Address Bits A2- A0 = 000 are programmed at the factory unless customer requests specific codes. – Stop bit or NAK bit can be issued any time during reading. – In 14 - bit mode: D15 and D14 are repeated MSB and can be ignored. – In 12 - bit mode: D15 - D12 are repeated MSB and can be ignored. MCP3425 1 SCL 9 1 9 SDA Start Bit by Master 1 1 0 1 A2 A1 A0 C1 C0 S1 S0 G1 G0 ACK by MCP3425 R/W 1st Byte: MCP3425 Address Byte with Write command ACK by MCP3425 RDY O/C Stop Bit by Master 2nd Byte: Configuration Byte Note: – Stop bit can be issued any time during writing. – MCP3425 device code is 1101. – Address Bits A2- A0 = 000 are programmed at factory unless customer requests different codes. FIGURE 5-3: Timing Diigram For Writing To The MCP3425. 5.4 General Call ACK ACK LSB The MCP3425 acknowledges the general call address (0x00 in the first byte). The meaning of the general call address is always specified in the second byte. Refer to Figure 5-4. The MCP3425 supports the following general calls: 00000000Ax xxxx x x xA 5.4.1 GENERAL CALL RESET The general call reset occurs if the second byte is ‘00000110’ (06h). At the acknowledgement of this byte, the device will abort current conversion and perform an internal reset similar to a power-on-reset (POR). First Byte (General Call Address) Second Byte FIGURE 5-4: Format. General Call Address 5.4.2 GENERAL CALL CONVERSION For more information on the general call, or other I2C modes, please refer to the Phillips I2C specification. The general call conversion occurs if the second byte is ‘00001000’ (08h). All devices on the bus initiate a conversion simultaneously. For the MCP3425 device, the configuration will be set to the One-Shot Conversion mode and a single conversion will be performed. The PGA and data rate settings are unchanged with this general call. Note: The I2C specification does not allow to use “00000000” (00h) in the second byte. © 2007 Microchip Technology Inc. DS22072A-page 15 MCP3425 5.5 High-Speed (HS) Mode 5.6.4 DATA VALID (D) The I2C specification requires that a high-speed mode device must be ‘activated’ to operate in high-speed mode. This is done by sending a special address byte of 00001XXX following the START bit. The XXX bits are unique to the High-Speed (HS) mode Master. This byte is referred to as the High-Speed (HS) Master Mode Code (HSMMC). The MCP3425 device does not acknowledge this byte. However, upon receiving this code, the MCP3425 switches on its HS mode filters and communicates up to 3.4 MHz on SDA and SCL. The device will switch out of the HS mode on the next STOP condition. For more information on the HS mode, or other I2C modes, please refer to the Phillips I2C specification. The state of the data line represents valid data when, after a START condition, the data line is stable for the duration of the HIGH period of the clock signal. The data on the line must be changed during the LOW period of the clock signal. There is one clock pulse per bit of data. Each data transfer is initiated with a START condition and terminated with a STOP condition. 5.6.5 ACKNOWLEDGE 5.6 I2C Bus Characteristics The I2C specification defines the following bus protocol: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is HIGH. Changes in the data line while the clock line is HIGH will be interpreted as a START or STOP condition. Accordingly, the following bus conditions have been defined using Figure 5-5. The Master (microcontroller) and the slave (MCP3425) use an acknowledge pulse as a hand shake of communication for each byte. The ninth clock pulse of each byte is used for the acknowledgement. The acknowledgement is achieved by pulling-down the SDA line “LOW” during the 9th clock pulse. The clock pulse is always provided by the Master (microcontroller) and the acknowledgement is issued by the receiving device of the byte (Note: The transmitting device must release the SDA line (“HIGH”) during the acknowledge pulse.). For example, the slave (MCP3425) issues the acknowledgement (bring down the SDA line “LOW”) after the end of each receiving byte, and the master (microcontroller) issues the acknowledgement when it reads data from the Slave (MCP3425). When the MCP3425 is addressed, it generates an acknowledge after receiving each byte successfully. The Master device (microcontroller) must provide an extra clock pulse (9th pulse of each byte) for the acknowledgement from the MCP3425 (slave). The MCP3425 (slave) pulls-down the SDA line during the acknowledge clock pulse in such a way that the SDA line is stable low during the high period of the acknowledge clock pulse. During reads, the Master (microcontroller) can terminate the current read operation by not providing an acknowledge bit on the last byte that has been clocked out from the MCP3425. In this case, the MCP3425 releases the SDA line to allow the master (microcontroller) to generate a STOP or repeated START condition. 5.6.1 BUS NOT BUSY (A) Both data and clock lines remain HIGH. 5.6.2 START DATA TRANSFER (B) A HIGH to LOW transition of the SDA line while the clock (SCL) is HIGH determines a START condition. All commands must be preceded by a START condition. 5.6.3 STOP DATA TRANSFER (C) A LOW to HIGH transition of the SDA line while the clock (SCL) is HIGH determines a STOP condition. All operations can be ended with a STOP condition. (A) SCL (B) (D) (D) (C) (A) SDA START CONDITION DATA ADDRESS OR ACKNOWLEDGE ALLOWED TO CHANGE VALID STOP CONDITION FIGURE 5-5: Data Transfer Sequence on the Serial Bus. DS22072A-page 16 © 2007 Microchip Technology Inc. MCP3425 TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters Standard Mode Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) Sym Min Typ Max Units Conditions fSCL THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO THD:STD TAA TBUF 0 4000 4700 — — 4000 4700 0 250 4000 4000 0 4700 — — — — — — — — — — — — — 100 — — 1000 300 — — 3450 — — — 3750 — kHz ns ns ns ns ns ns ns ns ns ns ns ns Time between START and STOP conditions. From VIL to VIH From VIH to VIL After this period, the first clock pulse is generated. Only relevant for repeated Start condition SDA and SCL fall time (Note 1) START condition hold time Repeated START condition setup time Data hold time (Note 3) Data input setup time STOP condition setup time STOP condition hold time Output valid from clock (Notes 2 and 3) Bus free time Fast Mode Clock frequency Clock high time Clock low time SDA and SCL rise time (Note 1) SDA and SCL fall time (Note 1) START condition hold time Repeated START condition setup time Data hold time (Note 4) Data input setup time STOP condition setup time STOP condition hold time Output valid from clock (Notes 2 and 3) TSCL THIGH TLOW TR TF THD:STA TSU:STA THD:DAT TSU:DAT TSU:STO THD:STD TAA TBUF TSP 0 600 1300 20 + 0.1Cb 20 + 0.1Cb 600 600 0 100 600 600 0 1300 0 — — — — — — — — — — — — — — 400 — — 300 300 — — 900 — — — 1200 — 50 kHz ns ns ns ns ns ns ns ns ns ns ns ns ns Time between START and STOP conditions. SDA and SCL pins From VIL to VIH From VIH to VIL After this period, the first clock pulse is generated Only relevant for repeated Start condition Bus free time Input filter spike suppression (Note 5) Note 1: 2: 3: 4: 5: This parameter is ensured by characterization and not 100% tested. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. © 2007 Microchip Technology Inc. DS22072A-page 17 MCP3425 TABLE 5-4: I2C SERIAL TIMING SPECIFICATIONS (CONTINUED) Electrical Specifications: Unless otherwise specified, all limits are specified for TA = -40 to +85°C, VDD = +2.7V, +3.3V or +5.0V, VSS = 0V, VIN+ = VIN- = VREF/2. Parameters High-Speed Mode Clock frequency Clock high time Clock low time SCL rise time (Note 1) SCL fall time (Note 1) SDA rise time (Note 1) SDA fall time (Note 1) START condition hold time Repeated START condition setup time Data hold time (Note 4) Data input setup time STOP condition setup time STOP condition hold time Output valid from clock (Notes 2 and 3) Sym Min Typ Max Units Conditions fSCL THIGH TLOW TR TF TR: DAT TF: DATA THD:STA 0 60 120 160 320 — — — — 160 160 0 0 10 160 160 — 160 0 — — — — — — — — — — — — — — — — 3.4 1.7 — — 40 80 40 80 80 160 80 160 — — 70 150 — — — 150 310 — 10 MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Cb = 100 pF Cb = 400 pF Cb = 100 pF Cb = 400 pF Cb = 100 pF Cb = 400 pF From VIL to VIH,Cb = 100 pF Cb = 400 pF From VIH to VIL,Cb = 100 pF Cb = 400 pF From VIL to VIH,Cb = 100 pF Cb = 400 pF From VIH to VIL,Cb = 100 pF Cb = 400 pF After this period, the first clock pulse is generated Only relevant for repeated Start condition Cb = 100 pF Cb = 400 pF TSU:STA THD:DAT TSU:DAT TSU:STO THD:STD TAA TBUF TSP Cb = 100 pF Cb = 400 pF Time between START and STOP conditions. SDA and SCL pins Bus free time Input filter spike suppression (Note 5) Note 1: 2: 3: 4: 5: This parameter is ensured by characterization and not 100% tested. This specification is not a part of the I2C specification. This specification is equivalent to the Data Hold Time (THD:DAT) plus SDA Fall (or rise) time: TAA = THD:DAT + TF (OR TR). If this parameter is too short, it can create an unintended Start or Stop condition to other devices on the bus line. If this parameter is too long, Clock Low time (TLOW) can be affected. For Data Input: This parameter must be longer than tSP. If this parameter is too long, the Data Input Setup (TSU:DAT) or Clock Low time (TLOW) can be affected. For Data Output: This parameter is characterized, and tested indirectly by testing TAA parameter. This parameter is ensured by characterization and not 100% tested. This parameter is not available for Standard Mode. DS22072A-page 18 © 2007 Microchip Technology Inc. MCP3425 TF THIGH TR SCL TSU:STA TLOW THD:DAT TSU:DAT TSU:STO TBUF 0.7 VDD 0.3 VDD SDA TSP THD:STA TAA FIGURE 5-6: I2C Bus Timing Data. © 2007 Microchip Technology Inc. DS22072A-page 19 MCP3425 6.0 BASIC APPLICATION CONFIGURATION I2C bus line. Higher value of pull-up resistor consumes less power, but increases the signal transition time (higher RC time constant) on the bus. Therefore, it can limit the bus operating speed. The lower value of resistor, on the other hand, consumes higher power, but allows higher operating speed. If the bus line has higher capacitance due to long bus line or high number of devices connected to the bus, a smaller pull-up resistor is needed to compensate the long RC time constant. The pull-up resistor is typically chosen between 1 kΩ and 10 kΩ ranges for standard and fast modes, and less than 1 kΩ for high speed mode in high loading capacitance environments. Input Signals VDD VDD The MCP3425 device can be used for various precision analog-to-digital converter applications. The device operates with very simple connections to the application circuit. The following sections discuss the examples of the device connections and applications. 6.1 6.1.1 Connecting to the Application Circuits INPUT VOLTAGE RANGE The fully differential input signals can be connected to the VIN+ and VIN- input pins. The input range should be within absolute common mode input voltage range: VSS - 0.3V to VDD + 0.3V. Outside this limit, the ESD protection diode at the input pin begins to conduct and the error due to input leakage current increases rapidly. Within this limit, the differential input VIN (= VIN+ - VIN-) is boosted by the PGA before a conversion takes place. The MCP3425 can not accept negative input voltages on the input pins. Figure 6-1 and Figure 6-2 show typical connection examples for differential inputs and a single-ended input, respectively. For the single-ended input, the input signal is applied to one of the input pins (typically connected to the VIN+ pin) while the other input pin (typically VIN- pin) is grounded. The input signal range of the single-ended configuration is from 0V to 2.048V. All device characteristics hold for the single-ended configuration, but this configuration loses one bit resolution because the input can only stand in positive half scale. Refer to Section 1.0 “Electrical Characteristics”. MCP3425 1 VIN+ 2 VSS 3 SCL VIN- 6 VDD 5 SDL 4 0.1 µF 10 µF R R Note: R is the pull-up resistor. TO MCU (MASTER) FIGURE 6-1: Typical Connection Example for Differential Inputs. VDD Input Signals VDD 6.1.2 BYPASS CAPACITORS ON VDD PIN MCP3425 1 VIN+ 2 VSS 3 SCL VIN- 6 VDD 5 SDL 4 For accurate measurement, the application circuit needs a clean supply voltage and must block any noise signal to the MCP3425 device. Figure 6-1 shows an example of using two bypass capacitors (a 10 µF tantalum capacitor and a 0.1 µF ceramic capacitor) in parallel on the VDD line. These capacitors are helpful to filter out any high frequency noises on the VDD line and also provide the momentary bursts of extra currents when the device needs from the supply. These capacitors should be placed as close to the VDD pin as possible (within one inch). If the application circuit has separate digital and analog power supplies, the VDD and VSS of the MCP3425 should reside on the analog plane. 0.1 µF 10 µF R R Note: R is the pull-up resistor. TO MCU (MASTER) FIGURE 6-2: Typical Connection Example for Single-Ended Input. The number of devices connected to the bus is limited only by the maximum bus capacitance of 400 pF. The bus loading capacitance affects on the bus operating speed. For example, the highest bus operating speed for the 400 pF bus capacitance is 1.7 MHz, and 3.4 MHz for 100 pF. Figure 6-3 shows an example of multiple device connections. 6.1.3 CONNECTING TO I2C BUS USING PULL-UP RESISTORS The SCL and SDA pins of the MCP3425 are open-drain configurations. These pins require a pull-up resistor as shown in Figure 6-1. The value of these pull-up resistors depends on the operating speed (standard, fast, and high speed) and loading capacitance of the DS22072A-page 20 © 2007 Microchip Technology Inc. MCP3425 6.3 SDA SCL Microcontroller (PIC16F876) EEPROM (24LC01) MCP3425 Temperature Sensor (TC74) Application Examples The MCP3425 device can be used in a broad range of sensor and data acquisition applications. Figure 6-5 shows an example of battery voltage measurement. The circuit uses a voltage divider if the battery voltage is greater than the device’s internal reference voltage (2.048V). The voltage divider circuit is not needed if the input voltage is less than the device’s internal reference voltage (2.048V). The user can adjust the variable resistor (R2) to calibrate the input voltage to be less than the device’s reference voltage (2.046V). The I2C pull-up resistor (Rpull-up) values are in the range of 5 kΩ to 10 kΩ for standard and high speed modes (100 kHz, 400 kHz), and less than 1 kΩ for fast mode (3.4 MHz). Since the ADC conversion is performed by using its internal reference voltage (2.048V), the conversion result is not affected by the VDD changes or Battery voltage changes within its operating voltage range (2.7V - 5.5V). To Load R1 Voltage Divider R2 Battery 4.2V FIGURE 6-3: Example of Multiple Device Connection on I2C Bus. 6.2 Device Connection Test The user can test the presence of the MCP3425 on the I2C bus line without performing an input data conversion. This test can be achieved by checking an acknowledge response from the MCP3425 after sending a read or write command. Here is an example using Figure 6-4: (a) Set the R/W bit “HIGH” in the address byte. (b) The MCP3425 will then acknowledge by pulling SDA bus LOW during the ACK clock and then release the bus back to the I2C Master. (c) A STOP or repeated START bit can then be issued from the Master and I2C communication can continue. Address Byte 700 kΩ Resistor MCP3425 1 VIN+ 2 VSS 3 SCL VIN- 6 VDD 5 SDL 4 0.1 µF VDD Rpull-up 10 µF Rpull-up SCL 1 2 3 4 5 6 7 8 9 TO MCU (MASTER) SDA Start Bit 1 1 0 1 A2 A1 A0 1 Address bits ACK Device bits Start Bit R/W MCP3425 Response FIGURE 6-5: Measurement. Example of Battery Voltage FIGURE 6-4: I2C Bus Connection Test. © 2007 Microchip Technology Inc. DS22072A-page 21 MCP3425 Figure 6-6, shows an example of interfacing with a bridge sensor for pressure measurement. VDD 10 kΩ Resistor 10 kΩ Thermistor VDD VDD MCP3425 MCP3425 1 VIN+ 2 VSS 3 SCL VIN- 6 VDD 5 SDL 4 0.1 µF 10 µF Rpull-up TO MCU (MASTER) TO MCU (MASTER) Rpull-up 1 VIN+ 2 VSS 3 SCL VIN- 6 VDD 5 SDL 4 0.1 µF 10 µF Rpull-up Rpull-up VDD VDD VDD NPP301 FIGURE 6-6: Measurement. Example of Pressure FIGURE 6-7: Measurement. Example of Temperature In this circuit example, the sensor full scale range is ±7.5 mV with a common mode input voltage of VDD / 2. This configuration will provide a full 14-bit resolution across the sensor output range. The alternative circuit for this amount of accuracy would involve an analog gain stage prior to a 16-bit ADC. Figure 6-7 shows an example of temperature measurement using a thermistor. This example can achieve a linear response over a 50°C temperature range. This can be implemented using a standard resistor with 1% tolerance in series with the thermistor. The value of the resistor is selected to be equal to the thermistor value at the mid-point of the desired temperature range. DS22072A-page 22 © 2007 Microchip Technology Inc. MCP3425 7.0 7.1 PACKAGING INFORMATION Package Marking Information 6-Lead SOT-23 Address Option A0 (000) A1 (001) A2 (010) A3 (011) A4 (100) A5 (101) A6 (110) A7 (111) Example Part Number Code CQNN CRNN CSNN CTNN Note 1 Note 1 Note 1 Note 1 1 XXNN 1 MCP3425A0T-E/CH MCP3425A1T-E/CH MCP3425A2T-E/CH MCP3425A3T-E/CH MCP3425A4T-E/CH MCP3425A5T-E/CH MCP3425A6T-E/CH MCP3425A7T-E/CH Note 1: CQ25 Contact Microchip Technology for these address option devices. Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. 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