MCP3901_11

MCP3901 Two-Channel Analog Front End Features • Two Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture • 91 dB SINAD, -104 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 109 dB Spurious-free Dynamic Range (SFDR) for Each Channel • Programmable Data Rate up to 64 ksps • Ultra Low-Power Shutdown mode with 4.5V and 10 MHz otherwise. This input is Schmitt triggered. © 2011 Microchip Technology Inc. DS22192D-page 17 MCP3901 NOTES: DS22192D-page 18 © 2011 Microchip Technology Inc. MCP3901 4.0 TERMINOLOGY AND FORMULAS 4.2 AMCLK – Analog Master Clock This is the clock frequency that is present on the analog portion of the device, after prescaling has occurred via the CONFIG1 PRESCALE register bits. The analog portion includes the PGAs and the two Sigma-Delta modulators. This section defines the terms and formulas used throughout this data sheet. The following terms are defined: MCLK – Master Clock AMCLK – Analog Master Clock DMCLK – Digital Master Clock DRCLK – Data Rate Clock Oversampling Ratio (OSR) Offset Error Gain Error Integral Nonlinearity Error Signal-to-Noise Ratio (SNR) Signal-to-Noise Ratio And Distortion (SINAD) Total Harmonic Distortion (THD) Spurious-Free Dynamic Range (SFDR) MCP3901 Delta-Sigma Architecture Idle Tones Dithering Crosstalk PSRR CMRR ADC Reset Mode Hardware Reset Mode (RESET = 0) ADC Shutdown Mode Full Shutdown Mode EQUATION 4-1: MCLK AMCLK = -----------------------------PRESCALE TABLE 4-1: Config PRE 0 0 1 1 0 1 0 1 MCP3901 OVERSAMPLING RATIO SETTINGS Analog Master Clock Prescale AMCLK = MCLK/1 (default) AMCLK = MCLK/2 AMCLK = MCLK/4 AMCLK = MCLK/8 4.3 DMCLK – Digital Master Clock This is the clock frequency that is present on the digital portion of the device, after prescaling and division by 4. This is also the sampling frequency, which is the rate when the modulator outputs are refreshed. Each period of this clock corresponds to one sample and one modulator output (see Figure 1-5). EQUATION 4-2: AMCLK MCLK DMCLK = -------------------- = --------------------------------------4 4 × PRESCALE 4.1 MCLK – Master Clock 4.4 This is the fastest clock present in the device. This is the frequency of the crystal placed at the OSC1/OSC2 inputs when CLKEXT = 0 or the frequency of the clock input at the OSC1/CLKI when CLKEXT = 1 (see Figure 1-5). DRCLK – Data Rate Clock This is the output data rate (i.e., the rate at which the ADCs output new data). Each new data is signaled by a Data Ready pulse on the DR pin. This data rate is depending on the OSR and the prescaler with the following formula: EQUATION 4-3: DMCLK AMCLK MCLK DRCLK = --------------------- = --------------------- = ---------------------------------------------------------OSR 4 × OSR 4 × OSR × PRESCALE © 2011 Microchip Technology Inc. DS22192D-page 19 MCP3901 Since this is the output data rate, and since the decimation filter is a SINC (or notch) filter, there is a notch in the filter transfer function at each integer multiple of this rate. The following table describes the various combinations of OSR and PRESCALE, and their associated AMCLK, DMCLK and DRCLK rates. TABLE 4-2: PRE 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 Note: 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 DEVICE DATA RATES IN FUNCTION OF MCLK, OSR AND PRESCALE OSR 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 OSR 256 128 64 32 256 128 64 32 256 128 64 32 256 128 64 32 AMCLK MCLK/8 MCLK/8 MCLK/8 MCLK/8 MCLK/4 MCLK/4 MCLK/4 MCLK/4 MCLK/2 MCLK/2 MCLK/2 MCLK/2 MCLK MCLK MCLK MCLK DMCLK MCLK/32 MCLK/32 MCLK/32 MCLK/32 MCLK/16 MCLK/16 MCLK/16 MCLK/16 MCLK/8 MCLK/8 MCLK/8 MCLK/8 MCLK/4 MCLK/4 MCLK/4 MCLK/4 DRCLK MCLK/8192 MCLK/4096 MCLK/2048 MCLK/1024 MCLK/4096 MCLK/2048 MCLK/1024 MCLK/512 MCLK/2048 MCLK/1024 MCLK/512 MCLK/256 MCLK/1024 MCLK/512 MCLK/256 MCLK/128 DRCLK (ksps) 0.4882 0.976 1.95 3.9 0.976 1.95 3.9 7.8125 1.95 3.9 7.8125 15.625 3.9 7.8125 15.625 31.25 SINAD (dB) 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 91.4 86.6 78.7 68.2 ENOB (bits) 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 14.89 14.10 12.78 11.04 For OSR = 32 and 64, DITHER = 0. For OSR = 128 and 256, DITHER = 1. 4.5 Oversampling Ratio (OSR) 4.6 Offset Error The ratio of the sampling frequency to the output data rate is OSR = DMCLK/DRCLK. The default OSR is 64 or with MCLK = 4 MHz and PRESCALE = 1, AMCLK = 4 MHz, fS = 1 MHz, fD = 15.625 ksps. The following bits in the CONFIG1 register are used to change the Oversampling Ratio (OSR). TABLE 4-3: CONFIG OSR 0 0 1 1 0 1 0 1 MCP3901 OVERSAMPLING RATIO SETTINGS OVERSAMPLING RATIO OSR 32 64 (default) 128 256 This is the error induced by the ADC when the inputs are shorted together (VIN = 0V). The specification incorporates both PGA and ADC offset contributions. This error varies with PGA and OSR settings. The offset is different on each channel and varies from chip to chip. This offset error can easily be calibrated out by a MCU with a subtraction. The offset is specified in mV. The offset on the MCP3901 has a low temperature coefficient; see Section 2.0 “Typical Performance Curves”. 4.7 Gain Error This is the error induced by the ADC on the slope of the transfer function. It is the deviation expressed in percent (%) compared to the ideal transfer function defined by Equation 5-3. The specification incorporates both PGA and ADC gain error contributions, but not the VREF contribution (it is measured with an external VREF). This error varies with PGA and OSR settings. The gain error on the MCP3901 has a low temperature coefficient; see the typical performance curves for more information, Figure 2-24 and Figure 2-25. DS22192D-page 20 © 2011 Microchip Technology Inc. MCP3901 4.8 Integral Nonlinearity Error 4.11 Total Harmonic Distortion (THD) Integral nonlinearity error is the maximum deviation of an ADC transition point from the corresponding point of an ideal transfer function, with the offset and gain errors removed, or with the end points equal to zero. It is the maximum remaining error after calibration of offset and gain errors for a DC input signal. The total harmonic distortion is the ratio of the output harmonic’s power to the fundamental signal power for a sinewave input and is defined by Equation 4-7: EQUATION 4-7: HarmonicsPower THD ( dB ) = 10 log ⎛ ----------------------------------------------------⎞ ⎝ FundamentalPower⎠ The THD calculation includes the first 35 harmonics for the MCP3901 specifications. The THD is usually only measured with respect to the 10 first harmonics. THD is sometimes expressed in %. For converting the THD in %, here is the formula: 4.9 Signal-to-Noise Ratio (SNR) For the MCP3901 ADC, the Signal-to-Noise ratio is a ratio of the output fundamental signal power to the noise power (not including the harmonics of the signal), when the input is a sinewave at a predetermined frequency. It is measured in dB. Usually, only the maximum Signal-to-Noise ratio is specified. The SNR calculation mainly depends on the OSR and DITHER settings of the device. EQUATION 4-8: THD ( % ) = 100 × 10 THD ( dB ) -----------------------20 EQUATION 4-4: SIGNAL-TO-NOISE RATIO SignalPower SNR ( dB ) = 10 log ⎛ --------------------------------- ⎞ ⎝ NoisePower ⎠ 4.10 Signal-to-Noise Ratio And Distortion (SINAD) This specification depends mainly on the DITHER setting. The most important figure of merit, for the analog performance of the ADCs present on the MCP3901, is the Signal-to-Noise and Distortion (SINAD) specification. Signal-to-Noise and distortion ratio are similar to the Signal-to-Noise ratio, with the exception that you must include the harmonics power in the noise power calculation. The SINAD specification mainly depends on the OSR and DITHER settings. 4.12 Spurious-Free Dynamic Range (SFDR) EQUATION 4-5: SINAD EQUATION SFDR is the ratio between the output power of the fundamental and the highest spur in the frequency spectrum. The spur frequency is not necessarily a harmonic of the fundamental, even though it is usually the case. This figure represents the dynamic range of the ADC when a full-scale signal is used at the input. This specification depends mainly on the DITHER setting. SignalPower SINAD ( dB ) = 10 log ⎛ --------------------------------------------------------------------⎞ ⎝ Noise + HarmonicsPower⎠ The calculated combination of SNR and THD per the following formula also yields SINAD: EQUATION 4-9: FundamentalPower SFDR ( dB ) = 10 log ⎛ ----------------------------------------------------⎞ ⎝ HighestSpurPower-⎠ EQUATION 4-6: SINAD, THD AND SNR RELATIONSHIP ⎛ SNR⎞ ---------⎝ 10 ⎠ SINAD ( dB ) = 10 log 10 + 10 ⎛ – THD⎞ --------------⎝ 10 ⎠ © 2011 Microchip Technology Inc. DS22192D-page 21 MCP3901 4.13 MCP3901 Delta-Sigma Architecture These Idle tones are residues that are inherent to the quantization process and the fact that the converter is integrating at all times without being reset. They are residues of the finite resolution of the conversion process. They are very difficult to attenuate and they are heavily signal dependent. They can degrade both the SFDR and THD of the converter, even for DC inputs. They can be localized in the baseband of the converter, and thus, difficult to filter from the actual input signal. For power metering applications, Idle tones can be very disturbing because energy can be detected even at the 50 or 60 Hz frequency, depending on the DC offset of the ADCs, while no power is really present at the inputs. The only practical way to suppress or attenuate the Idle tones phenomenon is to apply dithering to the ADC. The Idle tone amplitudes are a function of the order of the modulator, the OSR and the number of levels in the quantizer of the modulator. A higher order, a higher OSR or a higher number of levels for the quantizer will attenuate the Idle tones amplitude. The MCP3901 incorporates two Delta-Sigma ADCs with a multi-bit architecture. A Delta-Sigma ADC is an oversampling converter that incorporates a built-in modulator, which is digitizing the quantity of charge integrated by the modulator loop (see Figure 5-1). The quantizer is the block that is performing the Analog-to-Digital conversion. The quantizer is typically 1 bit, or a simple comparator which helps to maintain the linearity performance of the ADC (the DAC structure, is in this case, inherently linear). Multi-bit quantizers help to lower the quantization error (the error fed back in the loop can be very large with 1-bit quantizers) without changing the order of the modulator or the OSR, which leads to better SNR figures. Typically, however, the linearity of such architectures is more difficult to achieve, since the DAC is no more simple to realize, and its linearity limits the THD of such ADCs. The MCP3901’s 5-level quantizer is a Flash ADC, composed of 4 comparators arranged with equally spaced thresholds and a thermometer coding. The MCP3901 also includes proprietary 5-level DAC architecture that is inherently linear for improved THD figures. 4.15 Dithering 4.14 Idle Tones A Delta-Sigma Converter is an integrating converter. It also has a finite quantization step (LSB) which can be detected by its quantizer. A DC input voltage that is below the quantization step should only provide an all zeros result, since the input is not large enough to be detected. As an integrating device, any Delta-Sigma will show, in this case, Idle tones. This means that the output will have spurs in the frequency content that are depending on the ratio between quantization step voltage and the input voltage. These spurs are the result of the integrated sub-quantization step inputs that will eventually cross the quantization steps after a long enough integration. This will induce an AC frequency at the output of the ADC and can be shown in the ADC output spectrum. In order to suppress or attenuate the Idle tones present in any Delta-Sigma ADCs, dithering can be applied to the ADC. Dithering is the process of adding an error to the ADC feedback loop in order to “decorrelate” the outputs and “break” the Idle tones behavior. Usually, a random or pseudo-random generator adds an analog or digital error to the feedback loop of the Delta-Sigma ADC in order to ensure that no tonal behavior can happen at its outputs. This error is filtered by the feedback loop, and typically, has a zero average value so that the converter static transfer function is not disturbed by the dithering process. However, the dithering process slightly increases the noise floor (it adds noise to the part) while reducing its tonal behavior, and thus, improving SFDR and THD (see Figure 2-10 and Figure 2-14). The dithering process scrambles the Idle tones into baseband white noise and ensures that dynamic specs (SNR, SINAD, THD, SFDR) are less signal dependent. The MCP3901 incorporates a proprietary dithering algorithm on both ADCs in order to remove Idle tones and improve THD, which is crucial for power metering applications. DS22192D-page 22 © 2011 Microchip Technology Inc. MCP3901 4.16 Crosstalk It is defined as: The crosstalk is defined as the perturbation caused by one ADC channel on the other ADC channel. It is a measurement of the isolation between the two ADCs present in the chip. This measurement is a two-step procedure: 1. 2. Measure one ADC input with no perturbation on the other ADC (ADC inputs shorted). Measure the same ADC input with a perturbation sine wave signal on the other ADC at a certain predefined frequency. Where VOUT is the equivalent input voltage that the output code translates to with the ADC transfer function. In the MCP3901 specification, AVDD varies from 4.5V to 5.5V, and for AC PSRR, a 50/60 Hz sinewave is chosen, centered around 5V with a maximum 500 mV amplitude. The PSRR specification is measured with AVDD = DVDD. EQUATION 4-11: Δ V OUT PSRR ( dB ) = 20 log ⎛ ------------------⎞ ⎝ Δ AVDD⎠ The crosstalk is then the ratio between the output power of the ADC when the perturbation is present and when it is not divided by the power of the perturbation signal. A lower crosstalk value implies more independence and isolation between the two channels. The measurement of this signal is performed under the following conditions: • • • • GAIN = 1, PRESCALE = 1, OSR = 256, MCLK = 4 MHz 4.18 CMRR This is the ratio between a change in the common-mode input voltage and the ADC output codes. It measures the influence of the common-mode input voltage on the ADC outputs. The CMRR specification can be DC (the common-mode input voltage is taking multiple DC values) or AC (the common-mode input voltage is a sinewave at a certain frequency with a certain common-mode). In AC, the amplitude of the sinewave is representing the change in the power supply. It is defined as: Step 1 • CH0+ = CH0- = AGND • CH1+ = CH1- = AGND EQUATION 4-12: Δ VOUT CMRR ( dB ) = 20 log ⎛ -----------------⎞ ⎝ Δ VCM ⎠ Where VCM = (CHn+ + CHn-)/2 is the common-mode input voltage and VOUT is the equivalent input voltage, the output code is translated to the ADC transfer function. In the MCP3901 specification, VCM varies from -1V to +1V, and for the AC specification, a 50/ 60 Hz sinewave is chosen, centered around 0V, with a 500 mV amplitude. Step 2 • CH0+ = CH0- = AGND • CH1+ – CH1- = 1 VP-P @ 50/60 Hz (full-scale sine wave) The crosstalk is then calculated with the following formula: EQUATION 4-10: Δ CH0Power CTalk ( dB ) = 10 log ⎛ -------------------------------- ⎞ ⎝ Δ CH1Power⎠ 4.19 ADC Reset Mode 4.17 PSRR This is the ratio between a change in the power supply voltage and the ADC output codes. It measures the influence of the power supply voltage on the ADC outputs. The PSRR specification can be DC (the power supply is taking multiple DC values) or AC (the power supply is a sinewave at a certain frequency with a certain common-mode). In AC, the amplitude of the sinewave is representing the change in the power supply. ADC Reset mode (also called Soft Reset mode) can only be entered through setting the RESET bits high in the Configuration register. This mode is defined as the condition where the converters are active, but their output is forced to ‘0’. The registers are not affected in this Reset mode and retain their values. The ADCs can immediately output meaningful codes after leaving Reset mode (and after the sinc filter settling time of 3/DRCLK). This mode is both entered and exited through the setting of bits in the Configuration register. © 2011 Microchip Technology Inc. DS22192D-page 23 MCP3901 Each converter can be placed in Soft Reset mode independently. The Configuration registers are not modified by the Soft Reset mode. A data ready pulse will not be generated by any ADC while in Reset mode. Reset mode also effects the modulator output block (i.e., the MDAT pin, corresponding to the channel in Reset). If enabled, it provides a bitstream corresponding to a zero output (a series of ‘0011’ bits continuously repeated). When an ADC exits ADC Reset mode, any phase delay present, before Reset was entered, will still be present. If one ADC was not in Reset, the ADC leaving Reset mode will automatically resynchronize the phase delay. The resynchronization is relative to the other ADC channel per the Phase Delay register block and gives DR pulses accordingly. If an ADC is placed in Reset mode while the other is converting, it is not shutting down the internal clock. When going back out of Reset, it will be resynchronized automatically with the clock that did not stop during Reset. If both ADCs are in Soft Reset or Shutdown modes, the clock is no longer distributed to the digital core for lowpower operation. Once any of the ADC is back to normal operation, the clock is automatically distributed again. Each converter can be placed in Shutdown mode, independently. The CONFIG registers are not modified by the Shutdown mode. This mode is only available through programming the SHUTDOWN bits in the CONFIG2 register. The output data is flushed to all zeros while in ADC shutdown. No data ready pulses are generated by any ADC while in ADC Shutdown mode. ADC Shutdown mode also effects the modulator output block (i.e., if MDAT of the channel in Shutdown mode is enabled). This pin will provide a bitstream corresponding to a zero output (series of ‘0011’ bits continuously repeated). When an ADC exits ADC Shutdown mode, any phase delay present before shutdown was entered will still be present. If one ADC was not in shutdown, the ADC leaving Shutdown mode will automatically resynchronize the phase delay relative to the other ADC channel, per the Phase Delay register block, and give DR pulses accordingly. If an ADC is placed in Shutdown mode while the other is converting, it is not shutting down the internal clock. When going back out of shutdown, it will be resynchronized automatically with the clock that did not stop during Reset. If both ADCs are in ADC Reset or ADC Shutdown modes, there is no more distribution of the clock to the digital core for low-power operation. Once any of the ADC is back to normal operation, the clock is automatically distributed again. 4.20 Hard Reset Mode (RESET = 0) This mode is only available during a Power-on-Reset (POR) or when the RESET pin is pulled low. The RESET pin low state places the device in a Hard Reset mode. In this mode, all internal registers are reset to their default state. The DC biases for the analog blocks are still active (i.e., the MCP3901 is ready to convert). However, this pin clears all conversion data in the ADCs. In this mode, the MDAT outputs are in high-impedance. The comparator outputs of both ADCs are forced to their Reset state (‘0011’). The SINC filters are all reset, as well as their double output buffers. See serial timing for minimum pulse low time in Section 1.0 “Electrical Characteristics”. During a Hard Reset, no communication with the part is possible. The digital interface is maintained in a Reset state. 4.22 Full Shutdown Mode The lowest power consumption can be achieved when SHUTDOWN = 11 and VREFEXT = CLKEXT = 1. This mode is called “Full Shutdown mode” and no analog circuitry is enabled. In this mode, the POR AVDD monitoring circuit is also disabled. When the clock is Idle (CLKI = 0 or 1 continuously), no clock is propagated throughout the chip. Both ADCs are in shutdown, the internal voltage reference is disabled and the internal oscillator is disabled. The only circuit that remains active is the SPI interface, but this circuit does not induce any static power consumption. If SCK is Idle, the only current consumption comes from the leakage currents induced by the transistors and is less than 1 µA on each power supply. This mode can be used to power down the chip completely and avoid power consumption when there is no data to convert at the analog inputs. Any SCK or MCLK edge coming while on this mode, will induce dynamic power consumption. Once any of the SHUTDOWN, CLKEXT and VREFEXT bits returns to ‘0’, the POR AVDD monitoring block is back to operation and AVDD monitoring can take place. 4.21 ADC Shutdown Mode ADC Shutdown mode is defined as a state where the converters and their biases are off, consuming only leakage current. After this is removed, start-up delay time (SINC filter settling time) will occur before outputting meaningful codes. The start-up delay is needed to power-up all DC biases in the channel that was in shutdown. This delay is the same as tPOR and any DR pulse coming within this delay should be discarded. DS22192D-page 24 © 2011 Microchip Technology Inc. MCP3901 5.0 5.1 DEVICE OVERVIEW Analog Inputs (CHn+/-) 5.3 5.3.1 Delta-Sigma Modulator ARCHITECTURE The MCP3901 analog inputs can be connected directly to current and voltage transducers (such as shunts, current transformers, or Rogowski coils). Each input pin is protected by specialized ESD structures that are certified to pass 7 kV HBM and 400V MM contact charge. These structures allow bipolar ±6V continuous voltage, with respect to AGND, to be present at their inputs without the risk of permanent damage. Both channels have fully differential voltage inputs for better noise performance. The absolute voltage at each pin, relative to AGND, should be maintained in the ±1V range during operation in order to ensure the specified ADC accuracy. The common-mode signals should be adapted to respect both the previous conditions and the differential input voltage range. For best performance, the common-mode signals should be maintained to AGND. Both ADCs are identical in the MCP3901 and they include a second-order modulator with a multi-bit DAC architecture (see Figure 5-1). The quantizer is a Flash ADC composed of 4 comparators with equally spaced thresholds and a thermometer output coding. The proprietary 5-level architecture ensures minimum quantization noise at the outputs of the modulators without disturbing linearity or inducing additional distortion. The sampling frequency is DMCLK (typically 1 MHz with MCLK = 4 MHz) so the modulator outputs are refreshed at a DMCLK rate. The modulator outputs are available in the MOD register or serially transferred on each MDAT pin. Both modulators also include a dithering algorithm that can be enabled through the DITHER bits in the Configuration register. This dithering process improves THD and SFDR (for high OSR settings) while slightly increasing the noise floor of the ADCs. For power metering applications and applications that are distortion-sensitive, it is recommended to keep DITHER enabled for both ADCs. In the case of power metering applications, THD and SFDR are critical specifications to optimize SNR (noise floor). This is not really problematic due to a large averaging factor at the output of the ADCs; therefore, even for low OSR settings, the dithering algorithm will show a positive impact on the performance of the application. Figure 5-1 represents a simplified block diagram of the Delta-Sigma ADC present on MCP3901. 5.2 Programmable Gain Amplifiers (PGA) The two Programmable Gain Amplifiers (PGAs) reside at the front end of each Delta-Sigma ADC. They have two functions: translate the common-mode of the input from AGND to an internal level between AGND and AVDD, and amplify the input differential signal. The translation of the common-mode does not change the differential signal, but recenters the common-mode so that the input signal can be properly amplified. The PGA block can be used to amplify very low signals, but the differential input range of the Delta-Sigma modulator must not be exceeded. The PGA is controlled by the PGA_CHn bits in the GAIN register. The following table represents the gain settings for the PGA: Loop Filter Differential Voltage Input SecondOrder Integrator Quantizer Output 5-Level Flash ADC Bitstream TABLE 5-1: PGA CONFIGURATION SETTING Gain (V/V) 1 2 4 8 16 32 Gain (dB) 0 6 12 18 24 30 VIN Range (V) ±0.5 ±0.25 ±0.125 ±0.0625 ±0.03125 ±0.015625 Gain PGA_CHn 0 0 0 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 DAC MCP3901 Delta-Sigma Modulator FIGURE 5-1: Block Diagram. Simplified Delta-Sigma ADC © 2011 Microchip Technology Inc. DS22192D-page 25 MCP3901 5.3.2 MODULATOR INPUT RANGE AND SATURATION POINT TABLE 5-2: Comp Code 1111 0111 0011 0001 0000 DELTA-SIGMA MODULATOR CODING Modulator Output Code +2 +1 0 -1 -2 MDAT Serial Stream 1111 0111 0011 0001 0000 For a specified voltage reference value of 2.4V, the modulators’ specified differential input range is ±500 mV. The input range is proportional to VREF and scales according to the VREF voltage. This range ensures the stability of the modulator over amplitude and frequency. Outside of this range, the modulator is still functional, however, its stability is no longer ensured, and therefore, it is not recommended to exceed this limit. The saturation point for the modulator is VREF/3, since the transfer function of the ADC includes a gain of 3 by default (independent from the PGA setting). See Section 5.6 “ADC Output Coding”. COMP COMP COMP COMP AMCLK DMCLK 5.3.3 BOOST MODE The Delta-Sigma modulators also include an independent BOOST mode for each channel. If the corresponding BOOST bits are enabled, the power consumption of the modulator is multiplied by 2. Its bandwidth is increased to be able to sustain AMCLK clock frequencies up to 8.192 MHz, while keeping the ADC accuracy. When disabled, the power consumption is back to normal and the AMCLK clock frequencies can only reach up to 5 MHz without affecting ADC accuracy. MDAT+2 MDAT+1 MDAT+0 5.4 Modulator Output Block If the user wishes to use the modulator output of the device, the appropriate bits to enable the modulator output must be set in the Configuration register. When MODOUT are enabled, the modulator output of the corresponding channel is present at the corresponding MDAT output pin as soon as the command is placed. Since the Delta-Sigma modulators have a 5-level output given by the state of 4 comparators with thermometer coding, their outputs can be represented on 4 bits. Each bit gives the state of the corresponding comparator (see Table 5-2). These bits are present on the MOD register and are updated at the DMCLK rate. In order to output the comparators result on a separate pin (MDAT0 and MDAT1), these comparator output bits have been arranged to be serially output at the AMCLK rate (see Figure 5-2). This 1-bit serial bitstream is the same as what would be produced by a 1-bit DAC modulator with a sampling frequency of AMCLK. The modulator can either be considered as a 5 level-output at DMCLK rate or a 1-bit output at AMCLK rate. These two representations are interchangeable. The MDAT outputs can, therefore, be used in any application that requires 1-bit modulator outputs. These applications will often integrate and filter the 1-bit output with SINC or more complex decimation filters computed by an MCU or a DSP. MDAT-1 MDAT-2 FIGURE 5-2: MDAT Serial Outputs in Function of the Modulator Output Code. Since the Reset and shutdown SPI commands are asynchronous, the MDAT pins are resynchronized with DMCLK after each time the part goes out of Reset and shutdown. This means that the first output of MDAT after Reset is always ‘0011’ after the first DMCLK rising edge. DS22192D-page 26 © 2011 Microchip Technology Inc. MCP3901 5.5 SINC3 Filter Both ADCs present in the MCP3901 include a decimation filter that is a third-order sinc (or notch) filter. This filter processes the multi-bit bitstream into 16 or 24-bit words (depending on the WIDTH Configuration bit). The settling time of the filter is 3 DMCLK periods. It is recommended that unsettled data be discarded to avoid data corruption, which can be done easily by setting the DR_LTY bit high in the STATUS/COM register. The resolution achievable at the output of the sinc filter (the output of the ADC) is dependant on the OSR and is summarized with the following table: The Normal Mode Rejection Ratio (NMRR) or gain of the transfer function is given by the following equation: EQUATION 5-2: MAGNITUDE OF FREQUENCY RESPONSE H(f) 3 f sin c ⎛ π ⋅ ---------------------⎞ ⎝ DMCLK⎠ NMRR ( f ) = --------------------------------------------f sin c ⎛ π ⋅ --------------------⎞ ⎝ DRCLK⎠ or: f sin c ⎛ π ⋅ --- ⎞ ⎝ fS⎠ NMRR ( f ) = ---------------------------f -⎠ sin c ⎛ π ⋅ ----⎞ ⎝ fD where: sin ( x ) sin c ( x ) = -------------x 3 TABLE 5-3: OSR 0 0 1 1 0 1 0 1 ADC RESOLUTION vs. OSR OSR 32 64 128 256 ADC Resolution (bits) No Missing Codes 17 20 23 24 For 24-Bit Output mode (WIDTH = 1), the output of the sinc filter is padded with least significant zeros for any resolution less than 24 bits. For 16-Bit Output modes, the output of the sinc filter is rounded to the closest 16-bit number in order to conserve only 16-bit words and to minimize truncation error. The gain of the transfer function of this filter is 1 at each multiple of DMCLK (typically 1 MHz) so a proper anti-aliasing filter must be placed at the inputs. This will attenuate the frequency content around DMCLK and keep the desired accuracy over the baseband of the converter. This anti-aliasing filter can be a simple, first-order RC network with a sufficiently low time constant to generate high rejection at DMCLK frequency. Figure 5-3 shows the sinc filter frequency response: 20 0 Magnitude (dB) -20 -40 -60 -80 -100 -120 1 10 100 1000 10000 100000 1000000 Input Frequency (Hz) EQUATION 5-1: SINC FILTER TRANSFER FUNCTION H(Z) 3 FIGURE 5-3: SINC Filter Response with MCLK = 4 MHz, OSR = 64, PRESCALE = 1. ⎛ 1 – z – OSR ⎞ H ( z ) = ⎜ -------------------------------- ⎟ ⎝ OSR ( 1 – z –1 )⎠ Where: 2 π fj z = exp ⎛ ---------------------⎞ ⎝ DMCLK⎠ © 2011 Microchip Technology Inc. DS22192D-page 27 MCP3901 5.6 ADC Output Coding The second-order modulator, SINC3 filter, PGA, VREF and analog input structure all work together to produce the device transfer function for the Analog-to-Digital conversion (see Equation 5-3). The channel data is either a 16-bit or 24-bit word, presented in a 23-bit or 15-bit plus sign, two’s complement format, and is MSB (left) justified. The ADC data is two or three bytes wide depending on the WIDTH bit of the associated channel. The 16-bit mode includes a round to the closest 16-bit word (instead of truncation) in order to improve the accuracy of the ADC data. In case of positive saturation (CHn+ – CHn- > VREF/3), the output is locked to 7FFFFF for 24-bit mode (7FFF for 16-bit mode). In case of negative saturation (CHn+ – CHn- < -VREF/3), the output code is locked to 800000 for 24-bit mode (8000 for 16-bit mode). Equation 5-3 is only true for DC inputs. For AC inputs, this transfer function needs to be multiplied by the transfer function of the SINC3 filter (see Equation 5-1 and Equation 5-2). EQUATION 5-3: ( CH n+ – CH n- ) DATA_CHn = ⎛ ------------------------------------ ⎞ × 8,388,608 × G × 3 ⎝ V REF+ – V REF--⎠ ( CH n+ – CH n- ) DATA_CHn = ⎛ ------------------------------------ ⎞ × 32, 768 × G × 3 ⎝ V REF+ – V REF--⎠ 5.6.1 ADC RESOLUTION AS A FUNCTION OF OSR (For 24-Bit Mode or WIDTH = 1) (For 16-Bit Mode or WIDTH = 0) The ADC resolution is a function of the OSR (Section 5.5 “SINC3 Filter”). The resolution is the same for both channels. No matter what the resolution is, the ADC output data is always presented in 24-bit words, with added zeros at the end if the OSR is not large enough to produce 24-bit resolution (left justification). TABLE 5-4: 0111 0111 0000 1111 1000 1000 OSR = 256 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1110 0000 1111 0001 0000 Hexadecimal 0x7FFFFF 0x7FFFFE 0x000000 0xFFFFFF 0x800001 0x800000 Decimal + 8,388,607 + 8,388,606 0 -1 - 8,388,607 - 8,388,608 TABLE 5-5: OSR = 128 OUTPUT CODE EXAMPLES ADC Output Code (MSB First) Hexadecimal 1110 1100 0000 1110 0010 0000 0x7FFFFE 0x7FFFFC 0x000000 0xFFFFFE 0x800002 0x800000 Decimal 23-Bit Resolution + 4,194,303 + 4,194,302 0 -1 - 4,194,303 - 4,194,304 0111 0111 0000 1111 1000 1000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1110 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 DS22192D-page 28 © 2011 Microchip Technology Inc. MCP3901 TABLE 5-6: OSR = 64 OUTPUT CODE EXAMPLES ADC Output code (MSB First) 0111 0111 0000 1111 1000 1000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1110 0000 1111 0001 0000 0000 0000 0000 0000 0000 0000 Hexadecimal 0x7FFFF0 0x7FFFE0 0x000000 0xFFFFF0 0x800010 0x800000 Decimal 20-Bit Resolution + 524, 287 + 524, 286 0 -1 - 524,287 - 524, 288 TABLE 5-7: OSR = 32 OUTPUT CODE EXAMPLES ADC Output code (MSB First) Hexadecimal 0000 0000 0000 0000 0000 0000 0x7FFF80 0x7FFF00 0x000000 0xFFFF80 0x800080 0x800000 Decimal 17-Bit Resolution + 65, 535 + 65, 534 0 -1 - 65,535 - 65, 536 0111 0111 0000 1111 1000 1000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1111 1111 0000 1111 0000 0000 1000 0000 0000 1000 1000 0000 5.7 5.7.1 Voltage Reference INTERNAL VOLTAGE REFERENCE The MCP3901 contains an internal voltage reference source, specially designed to minimize drift over temperature. In order to enable the internal voltage reference, the VREFEXT bit in the Configuration register must be set to ‘0’ (Default mode). This internal VREF supplies reference voltage to both channels. The typical value of this voltage reference is 2.37V ±2%. The internal reference has a very low typical temperature coefficient of ±12 ppm/°C, allowing the output codes to have minimal variation with respect to temperature, since they are proportional to (1/VREF). The noise of the internal voltage reference is low enough not to significantly degrade the SNR of the ADC if compared to a precision, external low noise voltage reference. The output pin for the internal voltage reference is REFIN+/OUT. When the internal voltage reference is enabled, the REFIN- pin should always be connected to AGND. For optimal ADC accuracy, appropriate bypass capacitors should be placed between REFIN+/OUT and AGND. Decoupling at the sampling frequency, around 1 MHz, is important for any noise around this frequency will be aliased back into the conversion data (0.1 µF ceramic and 10 µF tantalum capacitors are recommended). These bypass capacitors are not mandatory for correct ADC operation, but removing these capacitors may degrade the accuracy of the ADC. The bypass capacitors also help the applications where the voltage reference output is connected to other circuits. In this case, additional buffering may be needed as the output drive capability of this output is low. 5.7.2 DIFFERENTIAL EXTERNAL VOLTAGE INPUTS When the VREFEXT bit is high, the two reference pins (REFIN+/OUT, REFIN-) become a differential voltage reference input. The voltage at the REFIN+/OUT pin is noted as VREF+ and the voltage at the REFIN- pin is noted as VREF-. The differential voltage input value is given by the following equation: EQUATION 5-4: VREF = VREF+ – VREFThe specified VREF range is from 2.2V to 2.6V. The REFIN- pin voltage (VREF-) should be limited to ±0.3V. Typically, for single-ended reference applications, the REFIN- pin should be directly connected to AGND. © 2011 Microchip Technology Inc. DS22192D-page 29 MCP3901 5.8 Power-on Reset 5.9 The MCP3901 contains an internal POR circuit that monitors analog supply voltage AVDD during operation. The typical threshold for a power-up event detection is 4.2V ±5%. The POR circuit has a built-in hysteresis for improved transient spikes immunity that has a typical value of 200 mV. Proper decoupling capacitors (0.1 µF ceramic and 10 µF tantalum) should be mounted as close as possible to the AVDD pin, providing additional transient immunity. Figure 5-4 illustrates the different conditions at power-up and a power-down event in the typical conditions. All internal DC biases are not settled until at least 50 µs after system POR. Any DR pulses during this time, after a system Reset, should be ignored. After POR, DR pulses are present at the pin with all the default conditions in the Configuration registers. Both AVDD and DVDD power supplies are independent. Since AVDD is the only power supply that is monitored, it is highly recommended to power up DVDD first as a power-up sequence. If AVDD is powered up first, it is highly recommended to keep the RESET pin low during the whole power-up sequence. RESET Effect on Delta-Sigma Modulator/SINC Filter When the RESET pin is low, both ADCs will be in Reset and output code, 0x0000h. The RESET pin performs a Hard Reset (DC biases still on, part ready to convert) and clears all charges contained in the Delta-Sigma modulators. The comparators’ output is ‘0011’ for each ADC. The SINC filters are all reset, as well as their double output buffers. This pin is independent of the serial interface. It brings the CONFIG registers to the default state. When RESET is low, any write with the SPI interface will be disabled and will have no effect. All output pins (SDO, DR, MDAT0/1) are high-impedance, and no clock is propagated through the chip. 5.10 Phase Delay Block The MCP3901 incorporates a phase delay generator which ensures that the two ADCs are converting the inputs with a fixed delay between them. The two ADCs are synchronously sampling but the averaging of modulator outputs is delayed. Therefore, the SINC filter outputs (thus, the ADC outputs) show a fixed phase delay, as determined by the PHASE register setting. The PHASE register (PHASE) is a 7 bit + sign, MSB first, two’s complement register that indicates how much phase delay there is to be between Channel 0 and Channel 1. The reference channel for the delay is Channel 1 (typically the voltage channel for power metering applications). When PHASE are positive, Channel 0 is lagging versus Channel 1. When PHASE are negative, Channel 0 is leading versus Channel 1. The amount of delay between two ADC conversions is given by the following formula: AVDD 5V 4.2V 4V 50 µs tPOR 0V Device Mode Time Reset Proper Operation Reset EQUATION 5-5: Phase Register Code Delay = ------------------------------------------------DMCLK The timing resolution of the phase delay is 1/DMCLK or 1 µs in the default configuration with MCLK = 4 MHz. The data ready signals are affected by the phase delay settings. Typically, the time difference between the data ready pulses of Channel 0 and Channel 1 is equal to the phase delay setting. Note: A detailed explanation of the Data Ready pin (DR) with phase delay is present in Section 6.10 “Data Ready Latches and Data Ready Modes (DRMODE)”. FIGURE 5-4: Power-on Reset Operation. DS22192D-page 30 © 2011 Microchip Technology Inc. MCP3901 5.10.1 PHASE DELAY LIMITS 5.11 Crystal Oscillator The phase delay can only go from -OSR/2 to +OSR/2 – 1. This sets the fine phase resolution. The PHASE register is coded with two’s complement. If larger delays between the two channels are needed, they can be implemented externally to the chip with an MCU. A FIFO in the MCU can save incoming data from the leading channel for a number N of DRCLK clocks. In this case, DRCLK would represent the coarse timing resolution, and DMCLK, the fine timing resolution. The total delay will then be equal to: Delay = N/DRCLK + PHASE/DMCLK The Phase Delay register can be programmed once with the OSR = 256 setting and will adjust to the OSR automatically afterwards, without the need to change the value of the PHASE register. • OSR = 256: The delay can go from -128 to +127. PHASE is the sign bit, PHASE is the MSB and PHASE is the LSB. • OSR = 128: The delay can go from -64 to +63. PHASE is the sign bit, PHASE is the MSB and PHASE is the LSB. • OSR = 64: The delay can go from -32 to +31. PHASE is the sign bit, PHASE is the MSB and PHASE is the LSB. • OSR = 32: The delay can go from -16 to +15. PHASE is the sign bit, PHASE is the MSB and PHASE is the LSB. The MCP3901 includes a Pierce-type crystal oscillator with very high stability and ensures very low temperature and jitter for the clock generation. This oscillator can handle up to 16.384 MHz crystal frequencies provided that proper load capacitances and the quartz quality factor are used. For keeping specified ADC accuracy, AMCLK should be kept between 1 and 5 MHz with BOOST off or 1 and 8.192 MHz with BOOST on. Larger MCLK frequencies can be used provided the prescaler clock settings allow the AMCLK to respect these ranges. For a proper start-up, the load capacitors of the crystal should be connected between OSC1 and DGND, and between OSC2 and DGND. They should also respect the following equation: EQUATION 5-6: 2 6 1 R M < 1.6 × 10 × ⎛ ------------------------ ⎞ ⎝ f × C LOAD⎠ Where: f CLOAD RM = = = Crystal frequency in MHz Load capacitance in pF including parasitics from the PCB Motional resistance in ohms of the quartz TABLE 5-8: PHASE VALUES WITH MCLK = 4 MHZ, OSR = 256 Hex Delay (CH0 relative to CH1) +127 µs +126 µs +1 µs 0 µs -1 µs -127 µs -128 µs When CLKEXT = 1, the crystal oscillator is bypassed by a digital buffer to allow direct clock input for an external clock (see Figure 1-5). PHASE Register Value 01111111 01111110 00000001 00000000 11111111 10000001 10000000 0x7F 0x7E 0x01 0x00 0xFF 0x81 0x80 © 2011 Microchip Technology Inc. DS22192D-page 31 MCP3901 NOTES: DS22192D-page 32 © 2011 Microchip Technology Inc. MCP3901 6.0 6.1 SERIAL INTERFACE DESCRIPTION Overview A6 A5 A4 A3 A2 A1 A0 R/W Read/ Write Bit The MCP3901 device is compatible with SPI Modes 0,0 and 1,1. Data is clocked out of the MCP3901 on the falling edge of SCK and data is clocked into the MCP3901 on the rising edge of SCK. In these modes, SCK can Idle either high or low. Each SPI communication starts with a CS falling edge and stops with the CS rising edge. Each SPI communication is independent. When CS is high, SDO is in high-impedance, and transitions on SCK and SDI have no effect. Additional controls: RESET, DR and MDAT0/1 are also provided on separate pins for advanced communication. The MCP3901 interface has a simple command structure. The first byte transmitted is always the CONTROL byte and is followed by data bytes that are 8-bit wide. Both ADCs are continuously converting data by default and can be reset or shut down through a CONFIG2 register setting. Since each ADC data is either 16 or 24 bits (depending on the WIDTH bits), the internal registers can be grouped together with various configurations (through the READ bits) in order to allow easy data retrieval within only one communication. For device reads, the internal address counter can be automatically incremented in order to loop through groups of data within the register map. The SDO will then output the data located at the ADDRESS (A) defined in the control byte and then ADDRESS + 1 depending on the READ bits, which select the groups of registers. These groups are defined in Section 7.1 “ADC Channel Data Output Registers” (Register Map). The Data Ready pin (DR) can be used as an interrupt for an MCU and outputs pulses when new ADC channel data is available. The RESET pin acts like a Hard Reset and can reset the part to its default powerup configuration. The MDAT0/1 pins give the modulator outputs (see Section 5.4 “Modulator Output Block”). Device Address Bits Register Address Bits FIGURE 6-1: Control Byte. The default device address bits are ‘00’. Contact the Microchip factory for additional device address bits. For more information, please see the Product Identification System section. A read on undefined addresses will give an all zeros output on the first, and all subsequent transmitted bytes. A write on an undefined address will have no effect and also, will not increment the address counter. The register map is defined in Section 7.1 “ADC Channel Data Output Registers”. 6.3 Reading from the Device The first data byte read is the one defined by the address given in the CONTROL byte. After this first byte is transmitted, if the CS pin is maintained low, the communication continues and the address of the next transmitted byte is determined by the status of the READ bits in the STATUS/COM register. Multiple looping configurations can be defined through the READ bits for the address increment (see Section 6.6 “SPI MODE 0,0 – Clock Idle Low, Read/ Write Examples”). 6.4 Writing to the Device 6.2 Control Byte The control byte of the MCP3901 contains two device Address bits, A, 5 register Address bits, A, and a Read/Write bit (R/W). The first byte transmitted to the MCP3901 is always the control byte. The MCP3901 interface is device addressable (through A) so that multiple MCP3901 chips can be present on the same SPI bus with no data bus contention. This functionality enables three-phase power metering systems, containing three MCP3901 chips, controlled by a single SPI bus (single CS, SCK, SDI and SDO pins). The first data byte written is the one defined by the address given in the control byte. The write communication automatically increments the address for subsequent bytes. The address of the next transmitted byte within the same communication (CS stays low) is the next address defined on the register map. At the end of the register map, the address loops to the beginning of the register map. Writing a non-writable register has no effect. The SDO pin stays in high-impedance during a write communication. 6.5 SPI MODE 1,1 – Clock Idle High, Read/Write Examples In this SPI mode, the clock Idles high. For the MCP3901, this means that there will be a falling edge before there is a rising edge. Note: Changing from an SPI Mode 1,1 to an SPI Mode 0,0 is possible, but needs a Reset pulse in-between to ensure correct communication. © 2011 Microchip Technology Inc. DS22192D-page 33 MCP3901 : CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI A6 A5 A4 A3 A2 A1 A0 R/W SDO HI-Z HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 HI-Z (ADDRESS + 1) DATA (ADDRESS) DATA FIGURE 6-2: CS Device Read (SPI Mode 1,1 – Clock Idles High). Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 (ADDRESS) DATA HI-Z (ADDRESS + 1) DATA HI-Z SDO FIGURE 6-3: Device Write (SPI Mode 1,1 – Clock Idles High). DS22192D-page 34 © 2011 Microchip Technology Inc. MCP3901 6.6 SPI MODE 0,0 – Clock Idle Low, Read/Write Examples In this SPI mode, the clock Idles low. For the MCP3901, this means that there will be a rising edge before there is a falling edge. CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI A6 A5 A4 A3 A2 A1 A0 R/W SDO HI-Z HI-Z D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA HI-Z (ADDRESS) DATA (ADDRESS + 1) DATA FIGURE 6-4: Device Read (SPI Mode 0,0 – Clock Idles Low). CS Data Transitions on the Falling Edge MCU and MCP3901 Latch Bits on the Rising Edge SCK SDI HI-Z A6 A5 A4 A3 A2 A1 A0 R/W D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 OF (ADDRESS + 2) DATA (ADDRESS) DATA HI-Z (ADDRESS + 1) DATA HI-Z SDO FIGURE 6-5: Device Write (SPI Mode 0,0 – Clock Idles Low). © 2011 Microchip Technology Inc. DS22192D-page 35 MCP3901 6.7 Continuous Communication, Looping on Address Sets The STATUS/COM register contains the loop settings for the internal address counter (READ). The internal address counter can either stay constant (READ = 00) and continuously read the same byte, or it can auto-increment and loop through the register groups defined below (READ = 01), register types (READ = 10) or the entire register map (READ = 11). Each channel is configured independently as either a 16-bit or 24-bit data word, depending on the setting of the corresponding WIDTH bit in the CONFIG1 register. For continuous reading, in the case of WIDTH = 0 (16-bit), the lower byte of the ADC data is not accessed and the part jumps automatically to the following address (the user does not have to clock out the lower byte since it becomes undefined for WIDTH = 0). Figure 6-6 represents a typical, continuous read communication with the default settings (DRMODE = 00, READ = 10) for both WIDTH settings. This configuration is typically used for power metering applications. If the user wishes to read back either of the ADC channels continuously, or both channels continuously, the internal address counter of the MCP3901 can be set to loop on specific register sets. In this case, there is only one control byte on SDI to start the communication. The part stays within the same loop until CS returns high. This internal address counter allows the following functionality: • Read one ADC channel’s data continuously • Read both ADC channel’s data continuously (both ADC data can be independent or linked with DRMODE settings) • Continuously read the entire register map • Continuously read each separate register • Continuously read all Configuration registers • Write all Configuration registers in one communication (see Figure 6-7) CS SCK SDI CH0 ADC ADDR/R SDO CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte CH0 ADC CH0 ADC CH0 ADC CH1 ADC CH1 ADC CH1 ADC Upper byte Middle byte Lower byte Upper byte Middle byte Lower byte DR These bytes are not present when WIDTH=0 (16-bit mode) FIGURE 6-6: Typical Continuous Read Communication. DS22192D-page 36 © 2011 Microchip Technology Inc. MCP3901 6.7.1 CONTINUOUS WRITE The following register sets are defined as types: Both ADCs are powered up with their default configurations, and begin to output DR pulses immediately (RESET and SHUTDOWN bits are off by default). The default output codes for both ADCs are all zeros. The default modulator output for both ADCs is ‘0011’ (corresponding to a theoretical zero voltage at the inputs). The default phase is zero between the two channels. It is recommended to enter into ADC Reset mode for both ADCs, just after power-up, because the desired MCP3901 register configuration may not be the default one, and in this case, the ADC would output undesired data. Within the ADC Reset mode (RESET = 11), the user can configure the whole part with a single communication. The write commands automatically increment the address so that the user can start writing the PHASE register and finish with the CONFIG2 register in only one communication (see Figure 6-7). The RESET bits are in the CONFIG2 register to allow exiting the Soft Reset mode, and have the whole part configured and ready to run in only one command. The following register sets are defined as groups: TABLE 6-2: Type ADC DATA (both channels) REGISTER TYPES Addresses 0x00-0x05 0x06-0x0B CONFIGURATION 6.8 Situations that Reset ADC Data Immediately after the following actions, the ADCs are temporarily reset in order to provide proper operation: 1. 2. 3. 4. 5. Change in PHASE register. Change in the OSR setting. Change in the PRESCALE setting. Overwrite of the same PHASE register value. Change in the CLKEXT bit in the CONFIG2 register, modifying internal oscillator state. TABLE 6-1: Group ADC DATA CH0 ADC DATA CH1 REGISTER GROUPS Addresses 0x00-0x02 0x03-0x05 0x06-0x08 0x09-0x0B After these temporary Resets, the ADCs go back to the normal operation with no need for an additional command. These are also the settings where the DR position is affected. The PHASE register can be used to serially Soft Reset the ADCs, without using the RESET bits in the Configuration register, if the same value is written in the PHASE register. MOD, PHASE, GAIN CONFIG, STATUS AVDD CS SCK SDI 00011000 11XXXXXX CONFIG2 00001110 PHASE ADDR/W xxxxxxxx PHASE xxxxxxxx GAIN xxxxxxxx STATUS/COM xxxxxxxx CONFIG1 xxxxxxxx CONFIG2 CONFIG2 ADDR/W Optional Reset of Both ADCs One Command for Writing Complete Configuration FIGURE 6-7: Recommended Configuration Sequence at Power-up. © 2011 Microchip Technology Inc. DS22192D-page 37 MCP3901 6.9 Data Ready Pin (DR) 6.10 To signify when channel data is ready for transmission, the data ready signal is available on the Data Ready pin (DR) through an active-low pulse at the end of a channel conversion. The data ready pin outputs an active-low pulse with a period that is equal to the DRCLK clock period, and with a width equal to one DMCLK period. When not active-low, this pin can either be in highimpedance (when DR_HIZN = 0) or in a defined logic high state (when DR_HIZN = 1). This is controlled through the Configuration registers. This allows multiple devices to share the same data ready pin (with a pull-up resistor connected between DR and DVDD) in 3-phase, energy meter designs to reduce pin count. A single device on the bus does not require a pull-up resistor. After a data ready pulse has occurred, the ADC output data can be read through SPI communication. Two sets of latches at the output of the ADC prevent the communication from outputting corrupted data (see Section 6.10 “Data Ready Latches and Data Ready Modes (DRMODE)”). The CS pin has no effect on the DR pin, which means even if CS is high, data ready pulses will be provided (except when the configuration prevents them from outputting data ready pulses). The DR pin can be used as an interrupt when connected to an MCU or DSP. While the RESET pin is low, the DR pin is not active. Data Ready Latches and Data Ready Modes (DRMODE) To ensure that both channels’ ADC data is present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the ‘read start’ triggers. The first set of latches holds each output when the data is ready and latches both outputs together when DRMODE = 00. When this mode is on, both ADCs work together and produce one set of available data after each data ready pulse (that corresponds to the lagging ADC data ready). The second set of latches ensures that when reading starts on an ADC output, the corresponding data is latched so that no data corruption can occur. If an ADC read has started, in order to read the following ADC output, the current reading needs to be completed (all bits must be read from the ADC Output Data registers). 6.10.1 DATA READY PIN (DR) CONTROL USING DRMODE BITS There are four modes that control the data ready pulses and these modes are set with the DRMODE bits in the STATUS/COM register. For power metering applications, DRMODE = 00 is recommended (Default mode). DS22192D-page 38 © 2011 Microchip Technology Inc. MCP3901 The position of the DR pulses vary, with respect to this mode, to the OSR and to the PHASE settings: • DRMODE = 11: Both data ready pulses from ADC Channel 0 and ADC Channel 1 are output on the DR pin. • DRMODE = 10: Data ready pulses from ADC Channel 1 are output on the DR pin. The DR from ADC Channel 0 is not present on the pin. • DRMODE = 01: Data ready pulses from ADC Channel 0 are output on the DR pin. The DR from ADC Channel 1 is not present on the pin. • DRMODE = 00 (Recommended and Default mode): Data ready pulses from the lagging ADC between the two are output on the DR pin. The lagging ADC depends on the PHASE register and on the OSR. In this mode, the two ADCs are linked together so their data is latched together when the lagging ADC output is ready. 6.10.2 DR PULSES WITH SHUTDOWN OR RESET CONDITIONS There will be no DR pulses if DRMODE = 00 when either one or both of the ADCs are in Reset or shutdown. In Mode 0,0, a DR pulse only happens when both ADCs are ready. Any DR pulse will correspond to one data on both ADCs. The two ADCs are linked together and act as if there was only one channel with the combined data of both ADCs. This mode is very practical when both ADC channels’ data retrieval and processing need to be synchronized, as in power metering applications. Note: If DRMODE = 11, the user will still be able to retrieve the DR pulse for the ADC not in shutdown or Reset (i.e., only 1 ADC channel needs to be awake). Figure 6-8 represents the behavior of the data ready pin with the different DRMODE and DR_LTY configurations, while shutdown or Resets are applied. © 2011 Microchip Technology Inc. DS22192D-page 39 3*DRCLK period DRCLK Period 1 DMCLK Period DRCLK Period Internal reset synchronisation (1 DMCLK period) 3*DRCLK period DRCLK period RESET RESET or SHUTDOWN RESET or SHUTDOWN DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 PHASE > 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 PHASE = 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 PHASE < 0 DRMODE=01; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 MCP3901 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 Data Ready Behavior. D29 D30 D31 D32 D33 D34 DRMODE=00: Select the lagging Data Ready DRMODE=01: Select the Data Ready on channel 0 DRMODE=10: Select the Data Ready on channel 1 DRMODE=11: Select both Data ready Data Ready pulse that appears only when DR_LTY=0 DS22192D-page 40 FIGURE 6-8: © 2011 Microchip Technology Inc. MCP3901 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. A detailed description of the registers follows. All registers are 8-bit long and can be addressed separately. Read modes define the groups and types of registers for continuous read communication or looping on address sets. . TABLE 7-1: Address 0x00 0x03 0x06 0x07 0x08 0x09 0x0A 0x0B REGISTER MAP Name DATA_CH0 DATA_CH1 MOD PHASE GAIN STATUS/COM CONFIG1 CONFIG2 Bits 24 24 8 8 8 8 8 8 R/W R R Description Channel 0 ADC Data , MSB First Channel 1 ADC Data , MSB First R/W Delta-Sigma Modulators Output Register R/W Phase Delay Configuration Register R/W Gain Configuration Register R/W Status/Communication Register R/W Configuration Register 1 R/W Configuration Register 2 TABLE 7-2: REGISTER MAP GROUPING FOR CONTINUOUS READ MODES READ Address = 01 = 10 = 11 GROUP 0x00 Function 0x02 0x03 DATA_CH1 MOD PHASE GAIN STATUS/ COM CONFIG1 CONFIG2 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B © 2011 Microchip Technology Inc. GROUP LOOP ENTIRE REGISTER MAP DATA_CH0 0x01 GROUP GROUP TYPE TYPE DS22192D-page 41 MCP3901 7.1 ADC Channel Data Output Registers ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data is also latched to avoid data corruption issues. The three bytes of each channel are updated synchronously at a DRCLK rate. The three bytes can be accessed separately, if needed, but are refreshed synchronously. The ADC Channel Data Output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ bits). These registers are latched when an REGISTER 7-1: R-0 DATA_CHn bit 23 R-0 DATA_CHn bit 15 R-0 DATA_CHn bit 7 Legend: R = Readable bit -n = Value at POR bit 23-0 CHANNEL OUTPUT REGISTERS: ADDRESS 0x00-0x02: CH0; 0x03-0x05; CH1 R-0 R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn bit 16 R-0 R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn bit 8 R-0 R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn R-0 DATA_CHn bit 0 DATA_CHn DATA_CHn DATA_CHn W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DATA_CHn DS22192D-page 42 © 2011 Microchip Technology Inc. MCP3901 7.2 Modulator Output Register The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on both ADCs. Each bit in this register corresponds to one comparator output on one of the channels. . This register should be used as a read-only register. (Note 1). This register is updated at the refresh rate of DMCLK (typically, 1 MHz with MCLK = 4 MHz). See Section 5.4 “Modulator Output Block” for more details. REGISTER 7-2: R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0 Note 1: MODULATOR OUTPUT REGISTER (MOD): ADDRESS 0x06 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-1 bit 0 COMP3_CH1 COMP2_CH1 COMP1_CH1 COMP0_CH1 COMP3_CH0 COMP2_CH0 COMP1_CH0 COMP0_CH0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown COMPn_CH1: Comparator Outputs from Channel 1 Modulator bits COMPn_CH0: Comparator Outputs from Channel 0 Modulator bits This register can be written in order to overwrite modulator output data, but any writing here will corrupt the ADC_DATA on the next three data ready pulses. © 2011 Microchip Technology Inc. DS22192D-page 43 MCP3901 7.3 PHASE Register 7.3.1 PHASE RESOLUTION FROM OSR The PHASE register (PHASE) is a 7 bits + sign, MSB first, two’s complement register that indicates how much phase delay there should be between Channel 0 and Channel 1. The reference channel for the delay is Channel 1, which typically, is the voltage channel when used in energy metering applications (i.e., when PHASE register code is positive, Channel 0 is lagging Channel 1). When PHASE register code is negative, Channel 0 is leading versus Channel 1. The delay is given by the following formula: The timing resolution of the phase delay is 1/DMCLK, or 1 µs, in the default configuration (MCLK = 4 MHz). The PHASE register coding depends on the OSR setting: • OSR = 256: The delay can go from -128 to +127. PHASE is the sign bit. Phase is the MSB and PHASE the LSB. • OSR = 128: The delay can go from -64 to +63. PHASE is the sign bit. Phase is the MSB and PHASE the LSB. • OSR = 64: The delay can go from -32 to +31. PHASE is the sign bit. Phase is the MSB and PHASE the LSB. • OSR = 32: The delay can go from -16 to +15. PHASE is the sign bit. Phase is the MSB and PHASE the LSB. EQUATION 7-1: Phase Register Code D elay = ------------------------------------------------DMCLK REGISTER 7-3: R/W-0 PHASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 PHASE REGISTER (PHASE): ADDRESS 0x07 R/W-0 R/W-0 PHASE R/W-0 PHASE R/W-0 PHASE R/W-0 PHASE R/W-0 PHASE R/W-0 PHASE bit 0 PHASE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PHASE: CH0 Relative to CH1 Phase Delay bits Delay = PHASE Register’s two’s complement code/DMCLK (Default PHASE = 0). DS22192D-page 44 © 2011 Microchip Technology Inc. MCP3901 7.4 Gain Configuration Register This register contains the settings for the PGA gains for each channel as well as the BOOST options for each channel. REGISTER 7-4: R/W-0 PGA_CH1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 GAIN CONFIGURATION REGISTER (GAIN): ADDRESS 0x08 R/W-0 PGA_CH1 R/W-0 PGA_CH1 R/W-0 BOOST_ CH1 R/W-0 BOOST_ CH0 R/W-0 PGA_CH0 R/W-0 PGA_CH0 R/W-0 PGA_CH0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PGA_CH1: PGA Setting for Channel 1 bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 BOOST_CH Current Scaling for High-Speed Operation bits 11 = Both channels have current x 2 10 = Channel 1 has current x 2 01 = Channel 0 has current x 2 00 = Neither channel has current x 2 PGA_CH0: PGA Setting for Channel 0 bits 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 bit 4-3 bit 2-0 © 2011 Microchip Technology Inc. DS22192D-page 45 MCP3901 7.5 Status and Communication Register This mode is very useful for power metering applications because the data from both ADCs can be retrieved, using this single data ready event, and processed synchronously even in case of a large phase difference. This mode works as if there was one ADC channel and its data would be 48 bits long and contain both channel data. As a consequence, if one channel is in Reset or shutdown when DRMODE = 00, no data ready pulse will be present at the outputs (if both channels are not ready in this mode, the data is not considered ready). See Section 6.9 “Data Ready Pin (DR)” for more details about data ready pin behavior. This register contains all settings related to the communication, including data ready settings and status, and Read mode settings. 7.5.1 DATA READY (DR) LATENCY CONTROL – DR_LTY This bit determines if the first data ready pulses correspond to settled data or unsettled data from each SINC3 filter. Unsettled data will provide DR pulses every DRCLK period. If this bit is set, unsettled data will wait for 3 DRCLK periods before giving DR pulses and will then give DR pulses every DRCLK period. 7.5.4 7.5.2 DATA READY (DR) PIN HIGH Z – DR_HIZN DR STATUS FLAG – DRSTATUS This bit defines the non-active state of the data ready pin (logic 1 or high-impedance). Using this bit, the user can connect multiple chips with the same DR pin with a pull-up resistor (DR_HIZN = 0) or a single chip with no external component (DR_HIZN = 1). These bits indicate the DR status of both channels, respectively. These flags are set to logic high after each read of the STATUS/COM register. These bits are cleared when a DR event has happened on its respective ADC channel. Writing these bits has no effect. Note: These bits are useful if multiple devices share the same DR output pin (DR_HIZN = 0), in order to understand what DR event happened. This configuration can be used for three-phase power metering systems, where all three phases share the same data ready pin. In case the DRMODE = 00 (linked ADCs), these data ready status bits will be updated synchronously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DR pin is not used to save MCU I/O. 7.5.3 DATA READY MODE – DRMODE If one of the channels is in Reset or shutdown, only one of the data ready pulses is present and the situation is similar to DRMODE = 01 or 10. In the ‘01’, ‘10’ and ‘11’ modes, the ADC channel data to be read is latched at the beginning of a reading in order to prevent the case of erroneous data when a DR pulse happens during a read. In these modes, the two channels are independent. When these bits are equal to ‘11’,’10’ or ‘01’, they control which ADC’s data ready is present on the DR pin. When DRMODE = 00, the data ready pin output is synchronized with the lagging ADC channel (defined by the PHASE register) and the ADCs are linked together. In this mode, the output of the two ADCs is latched synchronously at the moment of the DR event. This prevents bad synchronization between the two ADCs. The output is also latched at the beginning of a reading in order not to be updated during a read and not to give erroneous data. DS22192D-page 46 © 2011 Microchip Technology Inc. MCP3901 REGISTER 7-5: R/W-1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 STATUS AND COMMUNICATION REGISTER: ADDRESS 0x09 R/W-1 DR_LTY R/W-0 DR_HIZN R/W-0 R/W-0 R-1 R-1 bit 0 DRMODE DRMODE DRSTATUS_CH1 DRSTATUS_CH0 READ READ READ: Address Loop Setting bits 11 = Address counter loops on entire register map 10 = Address counter loops on register types (default) 01 = Address counter loops on register groups 00 = Address not incremented, continually read same single register DR_LTY: Data Ready Latency Control bit 1 = “No Latency” Conversion, DR pulses after 3 DRCLK periods (default) 0 = Unsettled Data is available after every DRCLK period DR_HIZN: Data Ready Pin Inactive State Control bit 1 = The data ready pin default state is a logic high when data is NOT ready 0 = The data ready pin default state is high-impedance when data is NOT ready (default) DRMODE: Data Ready Pin (DR) Control bits 11 = Both Data Ready pulses from ADC0 and ADC Channel 1 are output on the DR pin. 10 = Data Ready pulses from ADC Channel 1 are output on the DR pin. DR from ADC Channel 0 are not present on the pin. 01 = Data Ready pulses from ADC Channel 0 are output on the DR pin. DR from ADC Channel 1 are not present on the pin. 00 = Data Ready pulses from the lagging ADC between the two are output on the DR pin. The lagging ADC selection depends on the PHASE register and on the OSR (default). DRSTATUS_CH: Data Ready Status bits 11 = ADC Channel 1 and Channel 0 data is not ready (default) 10 = ADC Channel 1 data is not ready, ADC Channel 0 data is ready 01 = ADC Channel 0 data is not ready, ADC Channel 1 data is ready 00 = ADC Channel 1 and Channel 0 data is ready bit 5 bit 4 bit 3-2 bit 1-0 © 2011 Microchip Technology Inc. DS22192D-page 47 MCP3901 7.6 Configuration Registers The Configuration registers contain settings for the internal clock prescaler, the oversampling ratio, the Channel 0 and Channel 1 width settings of 16 or 24 bits, the modulator output control settings, the state of the channel Resets and shutdowns, the dithering algorithm control (for Idle tones suppression), and the control bits for the external VREF and external CLK. REGISTER 7-6: R/W-0 PRESCALE bit 15 R/W-0 RESET _CH1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B R/W-0 R/W-0 OSR R/W-1 OSR R/W-0 WIDTH _CH1 R/W-1 DITHER _CH1 R/W-0 WIDTH _CH0 R/W-1 DITHER _CH0 R/W-0 MODOUT _CH1 R/W-0 VREFEXT R/W-0 MODOUT _CH0 bit 8 R/W-0 RESET _CH0 R/W-0 SHUTDOWN _CH1 R/W-0 SHUTDOWN _CH0 R/W-0 CLKEXT bit 0 PRESCALE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PRESCALE: Internal Master Clock (AMCLK) Prescaler Value bits 11 = AMCLK = MCLK/8 10 = AMCLK = MCLK/4 01 = AMCLK = MCLK/2 00 = AMCLK = MCLK (default) OSR: Oversampling Ratio for Delta-Sigma A/D Conversion bits (all channels, DMCLK/DRCLK) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 WIDTH_CH: ADC Channel Output Data Word Width bits 1 = 24-bit mode 0 = 16-bit mode (default) MODOUT_CH: Modulator Output Setting for MDAT Pins bits 11 = Both CH0 and CH1 modulator outputs present on MDAT1 and MDAT0 pins 10 = CH1 ADC modulator output present on MDAT1 pin 01 = CH0 ADC modulator output present on MDAT0 pin 00 = No modulator output is enabled (default) RESET_CH: Reset Mode Setting for ADCs bits 11 = Both CH0 and CH1 ADC are in Reset mode 10 = CH1 ADC in Reset mode 01 = CH0 ADC in Reset mode 00 = Neither Channel in Reset mode (default) SHUTDOWN_CH: Shutdown Mode Setting for ADCs bits 11 = Both CH0 and CH1 ADC are in Shutdown 10 = CH1ADC is in shutdown 01 = CH0 ADC is in shutdown 00 = Neither Channel is in shutdown (default) DITHER_CH: Control for Dithering Circuit bits 11 = Both CH0 and CH1 ADC have dithering circuit applied (default) 10 = Only CH1 ADC has dithering circuit applied 01 = Only CH0 ADC has dithering circuit applied 00 = Neither Channel has dithering circuit applied bit 13-12 bit 11-10 bit 9-8 bit 7-6 bit 5-4 bit 3-2 DS22192D-page 48 © 2011 Microchip Technology Inc. MCP3901 REGISTER 7-6: bit 1 CONFIGURATION REGISTERS: CONFIG1: ADDRESS 0x0A, CONFIG2: ADDRESS 0x0B (CONTINUED) VREFEXT: Internal Voltage Reference Shutdown Control bit 1 = Internal voltage reference disabled, an external voltage reference must be placed between REFIN+/OUT and REFIN0 = Internal voltage reference enabled (default) CLKEXT: Clock Mode bit 1 = External Clock mode (internal oscillator disabled and bypassed – lower power) 0 = XT mode – A crystal must be placed between OSC1/OSC2 (default) bit 0 © 2011 Microchip Technology Inc. DS22192D-page 49 MCP3901 NOTES: DS22192D-page 50 © 2011 Microchip Technology Inc. MCP3901 8.0 8.1 PACKAGING INFORMATION Package Marking Information 20-Lead SSOP (SS) Example: XXXXXXXX XXXXXXXX YYWWNNN MCP3901A0 e3 I/SS^^ 1049256 MCP3901A0 e3 E/SS^^ 1049256 20-Lead QFN Examples: XXXXXXX XXXXXXX YYWWNNN 39010 I/ML e3 1049256 39010 E/ML e3 1049256 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. 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