MCP3903

MCP3903 Six Channel Delta Sigma A/D Converter Features • Six Synchronous Sampling 16/24-bit Resolution Delta-Sigma A/D Converters with Proprietary Multi-Bit Architecture • 91 dB SINAD, -100 dBc Total Harmonic Distortion (THD) (up to 35th harmonic), 102 dB Spurious-free Dynamic Range (SFDR) for Each Channel • Programmable Data Rate up to 64 ksps • Ultra Low-Power Shutdown Mode with 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 DRMODE=01; DR PHASE = 0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 DRMODE=00; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 DRMODE=10; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 DRMODE=11; DR D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 DRMODE=00 : Select the lagging Data Ready DRMODE=01 : Select the Data Ready on channel 0 DRMODE=10 : Select the Data Ready on channel 1 DRMODE=11 : Select both Data ready Data Ready pulse that appears only when DR_LTY=0 © 2011 Microchip Technology Inc. DRMODE=01; DR PHASE < 0 FIGURE 6-8: Data Ready Behavior. DS25048B-page 35 MCP3903 6.11 DATA READY PULSE WITH PHASE DELAY 6.11.1 DATA READY LINK When DRLINK=0, the three pairs of ADCs are independent from each other. The data readys and the latches for the output data only depend on both ADCs in the pair. When another ADC (not in the pair) is put in SHUTDOWN or RESET, it has no effect. When DRLINK=1, all ADCs are linked together. The DRn_MODE are all set internally to 00. All DRn_MODE bits are not taken into account. All six channel ADC data are latched synchronously with the most lagging ADC channel of the six. All three DRA, DRB and DRC data ready pins are giving the same output that is synchronized with the most lagging ADC of the six channels. Only one pin can be connected to the MCU in this mode, which saves two connection ports on the MCU. In this mode, if any channel is in SHUTDOWN or RESET mode, no data ready is present on any of the DRA/DRB/DRC pins. The part acts as if there was only one ADC channel with 6x24 bits. Depending on the read modes, the ADC data can be retrieved by pair (Read by GROUP) or all together (Read by TYPE). Any time a new read command is performed, the ADC outputs are re-latched. In order to avoid loss of data or bad synchronization, the read mode by TYPES is recommended (READ=10) so that all data can be latched once at the beginning of the read. In the read mode by GROUP (READ=01) mode, the data will be relatched every time the part accesses to each group or pair of ADCs. To ensure that both channel ADC data from the same pair are present at the same time for SPI read, regardless of phase delay settings for either or both channels, there are two sets of latches in series with both the data ready and the reading start triggers. The first latch is set on whichever channel is the lagging channel (relative to the other channel, in a single channel pair). The second latch is set when an ADC output read command is issued, ensuring synchronized data ready pulses. CHn ADC LATCH SPI Serial Interface CHn ADC LATCH Synchronized data ready pulses FIGURE 6-9: Internal Latches Synchronizing Data Ready Pulses with Phase Delay Present (Single Channel Pair Shown). DS25048B-page 36 © 2011 Microchip Technology Inc. MCP3903 7.0 INTERNAL REGISTERS The addresses associated with the internal registers are listed below. All registers are 24 bits long and can be addressed separately. A detailed description of the registers follows. . TABLE 7-1: Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A INTERNAL REGISTER SUMMARY Name CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 MOD PHASE GAIN STATUS/COM CONFIG Bits 24 24 24 24 24 24 24 24 24 24 24 R/W R R R R R R R/W R/W R/W R/W R/W Description Channel 0 ADC Data , MSB first, left justified Channel 1 ADC Data , MSB first, left justified Channel 2 ADC Data , MSB first, left justified Channel 3 ADC Data , MSB first, left justified Channel 4 ADC Data , MSB first, left justified Channel 5 ADC Data , MSB first, left justified Delta Sigma Modulators Output Value Phase Delay Configuration Register Gain Configuration Register Status/Communication Register Configuration Register The following table shows how the internal address counter will loop on specific register groups and types. 7.1 Channel Output Registers ADC OUTPUT REGISTERS Bits 24 24 24 24 24 24 Address Cof R R R R R R TABLE 7-2: CONTINUOUS READ OPTIONS, LOOPING ON INTERNAL ADDRESSES READ Address 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A = “01” = “10” =“11” TABLE 7-3: Name CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 LOOP ENTIRE REGISTER MAP CHANNEL 4 CHANNEL 5 0x00 0x01 0x02 0x03 0x04 0x05 Function CHANNEL 0 CHANNEL 1 CHANNEL 2 CHANNEL 3 CHANNEL 4 CHANNEL 5 MOD PHASE GAIN STATUS/ COM CONFIG GROUP GROUP GROUP GROUP GROUP TYPE The ADC Channel data output registers always contain the most recent A/D conversion data for each channel. These registers are read-only. They can be accessed independently or linked together (with READ bits). These registers are latched when an ADC read communication occurs. When a data ready event occurs during a read communication, the most current ADC data is also latched to avoid data corruption issues. The three bytes of each channel are updated synchronously at a DRCLK rate. The three bytes can be accessed separately if needed, but are refreshed synchronously. The coding is 23-bit + sign two’s complement (see Section 5.5). © 2011 Microchip Technology Inc. TYPE DS25048B-page 37 MCP3903 REGISTER 7-1: R-0 D23 (MSB) bit 23 R-0 D15 bit 15 R-0 D7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23:0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-0 D6 R-0 D5 R-0 D4 R-0 D3 R-0 D2 R-0 D1 R-0 D0 bit 0 R-0 D14 R-0 D13 R-0 D12 R-0 D11 R-0 D10 R-0 D9 CHANNEL REGISTER R-0 D22 R-0 D21 R-0 D20 R-0 D19 R-0 D18 R-0 D17 R-0 D16 bit 16 R-0 D8 bit 8 24-bit ADC output data of the corresponding channel DS25048B-page 38 © 2011 Microchip Technology Inc. MCP3903 7.2 Mod Register MODULATOR OUTPUT REGISTER Bits 24 Address Cof R/W The MOD register contains the most recent modulator data output. The default value corresponds to an equivalent input of 0V on each ADC. Each bit in this register corresponds to one comparator output on one of the channels. This register should be used as a read-only register. (Note 1). This register is updated at the refresh rate of DMCLK (typically 1 MHz with MCLK = 4 MHz). The default state for this register is 001100110011001100110011. TABLE 7-4: Name MOD 0x06 REGISTER 7-2: R/W-0 COMP3_CH5 MOD REGISTER R/W-0 R/W-1 COMP1_CH5 R/W-1 COMP0_CH5 R/W-0 COMP3_CH4 R/W-0 COMP2_CH4 R/W-1 COMP1_CH4 R/W-1 COMP0_CH4 COMP2_CH5 bit 23 R/W-0 COMP3_CH3 bit 16 R/W-0 COMP2_CH3 R/W-1 COMP1_CH3 R/W-1 COMP0_CH3 R/W-0 COMP3_CH2 R/W-0 COMP2_CH2 R/W-1 COMP1_CH2 R/W-1 COMP0_CH2 bit 15 R/W-0 COMP3_CH1 bit 8 R/W-0 COMP2_CH1 R/W-1 COMP1_CH1 R/W-1 COMP0_CH1 R/W-0 COMP3_CH1 R/W-0 COMP2_CH0 R/W-1 COMP1_CH0 R/W-1 COMP0_CH0 bit 7 Legend: R = Readable bit -n = Value at POR bit 23:20 bit 19:16 bit 15:12 bit 11:8 bit 7:4 bit 3:0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 0 COMPn_CH5: Comparator Outputs from ADC Channel 5 COMPn_CH4: Comparator Outputs from ADC Channel 4 COMPn_CH3: Comparator Outputs from ADC Channel 3 COMPn_CH2: Comparator Outputs from ADC Channel 2 COMPn_CH1: Comparator Outputs from ADC Channel 1 COMPn_CH0: Comparator Outputs from ADC Channel 0 © 2011 Microchip Technology Inc. DS25048B-page 39 MCP3903 7.3 Phase Register PHASE REGISTER Bits 24 Address Cof R/W Name PHASE TABLE 7-5: The reference channel is the odd channel (Channel 1/ 3/5). When PHASEn is positive, Channel 0/2/4 is lagging versus channel 1/3/5 otherwise it is leading. The delay is calculated by the following formula: Delay = PHASE Register Code / DMCLK. 0x07 The phase register is composed of three bytes: PHASEC, PHASEB, PHASEA. Each byte is a 7 bit + sign MSB first, two's complement code that represents the amount of delay between each pair of ADCs. The PHASEC byte represents the delay between Channel 4 and Channel 5 (pair C). The PHASEB byte represents the delay between Channel 2 and Channel 3 (pair B). The PHASEA byte represents the delay between Channel 0 and Channel 1 (pair A). REGISTER 7-3: R/W-0 PHASEC7 bit 23 R/W-0 PHASEB7 bit 15 R/W-0 PHASEA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23:16 bit 15:8 bit 7:0 PHASE REGISTER R/W-0 R/W-0 PHASEC5 R/W-0 PHASEC4 R/W-0 PHASEC3 R/W-0 PHASEC2 R/W-0 PHASEC1 R/W-0 PHASEC0 bit 16 R/W-0 R/W-0 PHASEB5 R/W-0 PHASEB4 R/W-0 PHASEB3 R/W-0 PHASEB2 R/W-0 PHASEB1 R/W-0 PHASEB0 bit 8 R/W-0 R/W-0 PHASEA5 R/W-0 PHASEA4 R/W-0 PHASEA3 R/W-0 PHASEA2 R/W-0 PHASEA1 R/W-0 PHASEA0 bit 0 PHASEC6 PHASEB6 PHASEA6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PHASECn: CH4 relative to CH5 phase delay PHASEBn: CH2 relative to CH3 phase delay PHASEAn: CH0 relative to CH1 phase delay DS25048B-page 40 © 2011 Microchip Technology Inc. MCP3903 7.4 Gain Configuration Register GAIN REGISTER Bits 24 Address Cof R/W Name GAIN TABLE 7-6: 0x08 This register contains the gain register REGISTER 7-4: R/W-0 PGA2_CH5 bit 23 R/W-0 PGA2_CH3 bit 15 R/W-0 PGA2_CH1 bit 7 R/W-0 R/W-0 R/W-0 GAIN REGISTER R/W-0 PGA0_CH5 R/W-0 BOOST_ CH5 R/W-0 BOOST_ CH4 R/W-0 PGA2_CH4 R/W-0 PGA1_CH4 R/W-0 PGA0_CH4 bit 16 R/W-0 PGA0_CH3 R/W-0 BOOST_ CH3 R/W-0 BOOST_ CH2 R/W-0 PGA2_CH2 R/W-0 PGA1_CH2 R/W-0 PGA0_CH2 bit 8 R/W-0 PGA0_CH1 R/W-0 BOOST_ CH1 R/W-0 BOOST_ CH0 R/W-0 PGA2_CH0 R/W-0 PGA1_CH0 R/W-0 PGA0_CH0 bit 0 PGA1_CH5 PGA1_CH3 PGA1_CH1 Legend: R = Readable bit -n = Value at POR bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PGA_CHn: PGA Setting for Channel n 111 = Reserved (Gain = 1) 110 = Reserved (Gain = 1) 101 = Gain is 32 100 = Gain is 16 011 = Gain is 8 010 = Gain is 4 001 = Gain is 2 000 = Gain is 1 BOOST_CHn Current Scaling for high speed operation for channel n 1 = Channel has current x 2 0 = Channel has normal current bit © 2011 Microchip Technology Inc. DS25048B-page 41 MCP3903 7.5 STATUS/COM Register - Status and Communication Register STATUS/COM Register Bits 24 Address Cof R/W Name STATUS/COM If one of the channels is in reset or shutdown, only one of the data ready pulses is present and the situation is similar to DRn_MODE = 01 or 10. In the 01,10 and 11 modes, the data is latched at the beginning of a reading, in order to prevent the case of erroneous data when a data ready pulse happens when reading. TABLE 7-7: 0x09 7.5.1 DATA READY LATENCY - DR_LTY 7.5.4 DATA READY STATUS FLAG DRSTATUS_CHN This bit determines if the data ready pulses correspond to settled data or unsettled data from each SINC3 filter. Unsettled data will provide data ready pulses every DRCLK period. Settled data will wait for 3 DRCLK periods before giving data ready pulses and will then give data ready pulses every DRCLK period. These bits indicate the data ready status of each channel. These flags are set to logic high after being the STATUS/COM register has been read. These bits are cleared when a data ready event has happened on its respective ADC. Writing these bits has no effect. Note: These bits are useful if multiple devices share the same DRn output pin (DR_HIZ=0) in order to understand which device the data ready event occured from. In case the DRn_MODE=00 (Linked ADCs), these data ready status bits will be updated synchronously upon the same event (lagging ADC is ready). These bits are also useful in systems where the DRn pins are not used to save MCU I/O. 7.5.2 DATA READY HIGH Z MODE DR_HIZ Using this bit, the user can connect multiple chips with the same data ready pin with a pull up resistor (DR_HIZ=0) or a single chip with no external component (DR_HIZ=1) 7.5.3 DATA READY MODE - DRN_MODE These bits control which ADC data ready is present on the data ready pin. When the bits are set to 00, the output of the two ADCs are latched synchronously at the moment of the data ready event. This prevents bad synchronization between the two ADCs. The output is also latched at the beginning of a reading, in order not to be updated during a read, and not to give erroneous data. REGISTER 7-5: R/W-1 READ1 bit 23 R/W-0 WIDTH_CH0 bit 15 R/W-0 DRA_MODE1 bit 7 R/W-0 DRA_MODE0 R/W-1 DR_LTY R/W-0 READ0 STATUS/COM REGISTER R/W-0 WMODE R/W-0 WIDTH_CH5 R/W-0 WIDTH_CH4 R/W-0 WIDTH_CH3 R/W-0 WIDTH_CH2 R/W-0 WIDTH_CH1 bit 16 R/W-0 DR_HIZ R/W-0 DR_LINK R/W-0 DRC_MODE1 R/W-0 DRC_MODE0 R/W-0 DRB_MODE1 R/W-0 DRB_MODE0 bit 8 R-1 R-1 R-1 R-1 R-1 R-1 bit 0 DRSTATUS_CH5 DRSTATUS_CH4 DRSTATUS_CH3 DRSTATUS_CH2 DRSTATUS_CH1 DRSTATUS_CH0 bit 23:22 READ[1:0]: Address Loop Setting 11 = Address counter incremented, cycle through entire register map 10 = Address counter loops on register TYPES (DEFAULT) 01 = Address counter loops on register GROUPS 00 = Address not incremented, continually read single register WMODE: Write Mode Bit (internal use only) 1 = Static addressing Write Mode 0 = Incremental addressing Write Mode (DEFAULT) bit 21 DS25048B-page 42 © 2011 Microchip Technology Inc. MCP3903 REGISTER 7-5: bit 20:15 STATUS/COM REGISTER (CONTINUED) WIDTH_CHn ADC Channels output data word width control 1 = 24-bit mode for the corresponding channel 0 = 16-bit mode for the corresponding channel (default) DR_LTY: Data Ready Latency Control for DRA, DRB, and DRC pins 1 = True “No Latency” Conversion, data ready pulses after 3 DRCLK periods (DEFAULT) 0 = Unsettled Data is available after every DRCLK period DR_HIZ: Data Ready Pin Inactive State Control for DRA, DRB, and DRC pins 1 = The Default state is a logic high when data is NOT ready 0 = The Default state is high impedance when data is NOT ready (DEFAULT) DR_LINK Data Ready Link Control 1 = Data Ready Link turned ON, all channels linked and data ready pulses from the most lagging ADC are present on each DRn pin 0 = Data Ready Link tunred OFF (DEFAULT) DRC_MODE[1:0] 11 = Both Data Ready pulses from CH4 and CH5 are output on DRC pin. 10 = Data Ready pulses from CH5 are output on DRC pin. Data Ready pulses R from CH4 are not present on the pin. 01 = Data Ready pulses from CH4 are output on DRC pin. Data Ready pulses from CH5 are not present on the pin. 00 = Data Ready pulses from the lagging ADC channel between the two are output on DRC pin. The lagging ADC channel depends on the phase register and on the OSR. (DEFAULT) DRB_MODE[1:0] 11 = Both Data Ready pulses from CH2 and CH3 are output on DRB pin. 10 = Data Ready pulses from CH3 are output on DRB pin. Data Ready pulses from CH2 are not present on the pin. 01 = Data Ready pulses from CH2 are output on DRB pin. Data Ready pulses from CH3 are not present on the pin. 00 = Data Ready pulses from the lagging ADC channel between the two are output on DRB pin. The lagging ADC channel depends on the phase register and on the OSR. (DEFAULT) DRA_MODE[1:0] 11 = Both Data Ready pulses from CH0 and CH1 are output on DRA pin. 10 = Data Ready pulses from CH1 are output on DRA pin. Data Ready pulses from CH0 are not present on the pin. 01 = Data Ready pulses from CH0 are output on DRA pin. Data Ready pulses from CH1 are not present on the pin. 00 = Data Ready pulses from the lagging ADC channel between the two are output on DRA pin. The lagging ADC channel depends on the phase register and on the OSR. (DEFAULT) DRSTATUS_CHn: Data Ready Status 1 = Data Not Ready (default) 0 = Data Ready bit 14 bit 13 bit 12 bit 11:10 bit 9:8 bit 7:6 bit 5:0 © 2011 Microchip Technology Inc. DS25048B-page 43 MCP3903 7.6 Config Register - Configuration Register CONFIG Register Bits 24 Address Cof R/W Name CONFIG TABLE 7-8: 0x0A REGISTER 7-6: R/W-0 RESET_CH5 bit 23 R/W-0 SHUTDOWN_ CH3 bit 15 R/W-1 DITHER_CH1 bit 7 R/W-1 R/W-0 R/W-0 CONFIG REGISTER R/W-0 RESET_CH3 R/W-0 RESET_CH2 R/W-0 R/W-0 R/W-0 R/W-0 SHUTDOWN_CH4 bit 16 R/W-0 SHUTDOWN_CH1 R/W-0 SHUTDOWN_CH0 R/W-1 R/W-1 R/W-1 DITHER_CH3 R/W-1 DITHER_CH2 bit 8 R/W-0 OSR1 R/W-1 OSR0 R/W-0 R/W-0 R/W-0 EXTVREF R/W-0 EXTCLK bit 0 RESET_CH1 RESET_CH0 SHUTDOWN_CH5 RESET_CH4 SHUTDOWN_ CH2 DITHER_CH5 DITHER_CH4 DITHER_CH0 PRESCALE1 PRESCALE0 bit 23:18 RESET_CHn: Reset mode setting for ADCs 1 = Reset mode for the corresponding ADC channel ON 0 = Reset mode for the corresponding ADC chnnel OFF (default) SHUTDOWN_CHn: Shutdown mode setting for ADCs 1 = Shutdown mode for the corresponding ADC channel ON 0 = Shutdown mode for the corresponding ADC channel OFF(default) DITHER_CHn: Control for dithering circuit for idle tones cancellation 1 = Dithering circuit for the corresponding ADC channel ON (default) 0 = Dithering circuit for the corresponding ADC channel OFF OSR[1:0] Oversampling Ratio for Delta Sigma A/D Conversion (ALL CHANNELS, fd / fS) 11 = 256 10 = 128 01 = 64 (default) 00 = 32 PRESCALE[1:0] Internal Master Clock (AMCLK) Prescaler Value 11 = AMCLK = MCLK/ 8 10 = AMCLK = MCLK/ 4 01 = AMCLK = MCLK/ 2 00 = AMCLK = MCLK (DEFAULT) EXTVREF Internal Voltage Reference Shutdown Control 1 = Internal Voltage Reference Disabled 0 = Internal Voltage Reference Enabled (default) EXTCLK Clock Mode 1 = CLOCK Mode (Internal Oscillator Disabled - Lower Power) 0 = XT Mode - A crystal must be placed between OSC1/OSC2 (default) bit 17:12 bit 11:6 bit 5:4 bit 3:2 bit 1 bit 0 DS25048B-page 44 © 2011 Microchip Technology Inc. MCP3903 8.0 8.1 PACKAGING INFORMATION Package Marking Information 28-Lead SSOP (5.30 mm) Example MCP3903 E/SS e3 1124256 28-Lead SSOP (5.30 mm) Example MCP3903 I/SS e3 1124256 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2011 Microchip Technology Inc. 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