MCP3906

MCP3905/06 Energy-Metering ICs with Active (Real) Power Pulse Output Features • Supplies active (real) power measurement for single-phase, residential energy-metering • Supports the IEC 62053 International Energy Metering Specification and legacy IEC 1036/61036/687 Specifications • Two multi-bit, Digital-to-Analog Converters (DACs), second-order, 16-bit, Delta-Sigma Analog-to-Digital Converters (ADCs) • 0.1% typical measurement error over 500:1 dynamic range (MCP3905) • 0.1% typical measurement error over 1000:1 dynamic range (MCP3906) • Programmable Gain Amplifier (PGA) for smallsignal inputs supports low-value shunt current sensor - 16:1 PGA - MCP3905 - 32:1 PGA - MCP3906 • Ultra-low drift on-chip reference: 15 ppm/°C (typ.) • Direct drive for electromagnetic mechanical counter and two-phase stepper motors • Low IDD of 4 mA (typ.) • Tamper output pin for negative power indication • Industrial Temperature Range: -40°C to +85°C • Supplies instantaneous active (real) power on HFOUT for meter calibration Description The MCP3905/06 devices are energy-metering ICs designed to support the IEC 62053 International Metering Standard Specification. They supply a frequency output proportional to the average active (real) power, as well as a higher-frequency output proportional to the instantaneous power for meter calibration. They include two 16-bit, delta-sigma ADCs for a wide range of IB and IMAX currents and/or small shunt (< 200 µOhms) meter designs. It includes an ultra-low drift voltage reference with < 15 ppm/°C through a specially designed band gap temperature curve for the minimum gradient across the industrial temperature range. A fixed-function DSP block is onchip for active (real) power calculation. Strong output drive for mechanical counters are on-chip to reduce field failures and mechanical counter sticking. A noload threshold block prevents any current creep measurements. A Power-On Reset (POR) block restricts meter performance during low-voltage situations. These accurate energy-metering ICs with high field reliability are available in the industry-standard pinout. Package Type 24-Pin SSOP DVDD HPF AVDD NC CH0+ CH0CH1CH1+ MCLR REFIN/OUT AGND F2 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 FOUT0 FOUT1 HFOUT DGND NEG NC OSC2 OSC1 G0 G1 F0 F1 US Patents Pending Functional Block Diagram G0 G1 HPF OSC1 OSC2 HFOUT CH0+ CH0+ PGA – 16-bit Multi-level ΔΣ ADC HPF1 F2 F1 F0 FOUT0 FOUT1 NEG REFIN/ OUT 2.4V Reference X 16-bit Multi-level ΔΣ ADC HPF1 LPF1 E-to-F conversion CH1+ CH1- + – POR MCLR © 2007 Microchip Technology Inc. DS21948D-page 1 MCP3905/06 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under "Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD ...................................................................................7.0V Digital inputs and outputs w.r.t. AGND ........ -0.6V to VDD +0.6V Analog input w.r.t. AGND ..................................... ....-6V to +6V VREF input w.r.t. AGND ............................... -0.6V to VDD +0.6V Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-65°C to +125°C Soldering temperature of leads (10 seconds) ............. +300°C ESD on the analog inputs (HBM,MM) .................5.0 kV, 500V ESD on all other pins (HBM,MM) ........................5.0 kV, 500V ELECTRICAL CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply at AVDD = DVDD = 4.5V – 5.5V, Internal VREF, HPF turned on (AC mode), AGND, DGND = 0V, MCLK = 3.58 MHz; TA = -40°C to +85°C. Parameter Sym Min — — Typ. 0.1 0.1 Max — Units Comment Overall Measurement Accuracy Energy Measurement Error E No-Load Threshold/ NLT — 0.0015 Minimum Load Phase Delay Between — — Channels AC Power Supply AC PSRR — 0.01 Rejection Ratio (Output Frequency Variation) DC Power Supply DC PSRR — 0.01 — % FOUT HPF = 1, Gain = 1 (Note 3) Rejection Ratio (Output Frequency Variation) System Gain Error — 3 10 % FOUT Note 2, Note 5 ADC/PGA Specifications — 2 5 mV Referred to Input Offset Error VOS Gain Error Match — 0.5 — % FOUT Note 8 Internal Voltage Reference Voltage — 2.4 — V Tolerance — ±2 — % Tempco — 15 — ppm/°C Note 1: Measurement error = (Energy Measured By Device - True Energy)/True Energy * 100%. Accuracy is measured with signal (±660 mV) on Channel 1. FOUT0, FOUT1 pulse outputs. Valid from 45 Hz to 65 Hz. See Section 2.0 “Typical Performance Curves” for higher frequencies and increased dynamic range. 2: Does not include internal VREF. Gain = 1, CH0 = 470 mVDC, CH1 = 660 mVDC, difference between measured output frequency and expected transfer function. 3: Percent of HFOUT output frequency variation; Includes external VREF = 2.5V, CH1 = 100 mVRMS @ 50 Hz, CH2 = 100 mVRMS @ 50 Hz, AVDD = 5V + 1Vpp @ 100 Hz. DC PSRR: 5V ±500 mV. 4: Error applies down to 60° lead (PF = 0.5 capacitive) and 60° lag (PF = 0.5 inductive). 5: Refer to Section 4.0 “Device Overview” for complete description. 6: Specified by characterization, not production tested. 7: 1 MCLK period at 3.58 MHz is equivalent to less than