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MCP4024

MCP4024

  • 厂商:

    MICROCHIP

  • 封装:

  • 描述:

    MCP4024 - Low-Cost NV Digital POT with WiperLock™ Technology - Microchip Technology

  • 数据手册
  • 价格&库存
MCP4024 数据手册
MCP4021/2/3/4 Low-Cost NV Digital POT with WiperLock™ Technology Features • Non-volatile Digital Potentiometer in SOT-23, SOIC, MSOP and DFN packages • 64 Taps: 63 Resistors with Taps to terminal A and terminal B • Simple Up/Down (U/D) Protocol • Power-on Recall of Saved Wiper Setting • Resistance Values: 2.1 kΩ, 5 kΩ, 10 kΩ or 50 kΩ • Low Tempco: - Absolute (Rheostat): 50 ppm (0°C to 70°C typ.) - Ratiometric (Potentiometer): 10 ppm (typ.) • Low Wiper Resistance: 75Ω (typ.) • WiperLock™ Technology to Secure the wiper setting in non-volatile memory (EEPROM) • High-Voltage Tolerant Digital Inputs: Up to 12.5V • Low-Power Operation: 1 µA Max Static Current • Wide Operating Voltage: 2.7V to 5.5V • Extended Temperature Range: -40°C to +125°C • Wide Bandwidth (-3 dB) Operation: - 4 MHz (typ.) for 2.1 kΩ device Package Types MCP4021 SOIC, MSOP, DFN Potentiometer VDD 1 VSS 2 A3 W4 A W B 8 U/D 7 NC 6B 5 CS VDD 1 VSS 2 U/D 3 B MCP4022 SOT-23-6 Rheostat A W 6A 5W 4 CS MCP4023 SOT-23-6 Potentiometer VDD 1 VSS 2 U/D 3 B A W 6A 5W 4 CS VDD 1 VSS 2 U/D 3 MCP4024 SOT-23-5 Rheostat W B A 5W 4 CS Block Diagram A VDD Power-Up and Brown-Out Control Wiper Register (Resistor Array) Description The MCP4021/2/3/4 devices are non-volatile, 6-bit digital potentiometers that can be configured as either a potentiometer or rheostat. The wiper setting is controlled through a simple Up/Down (U/D) serial interface. These device’s implement Microchip’s WiperLock technology, which allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. VSS CS U/D 2-Wire Interface and Control Logic W EEPROM and WiperLock™ Technology B Device Features Device Wiper Configuration Memory Type EE EE EE EE Resistance (typical) Options (kΩ) 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 2.1, 5.0, 10.0, 50.0 VDD # of Control WiperLock™ Operating Steps Interface Technology Wiper (Ω) Range 75 75 75 75 64 64 64 64 2.7V - 5.5V 2.7V- 5.5V 2.7V - 5.5V 2.7V - 5.5V U/D U/D U/D U/D Yes Yes Yes Yes MCP4021 Potentiometer (1) MCP4022 MCP4023 MCP4024 Note 1: . Rheostat Potentiometer Rheostat Floating either terminal (A or B) allows the device to be used in Rheostat mode. © 2006 Microchip Technology Inc. DS21945E-page 1 MCP4021/2/3/4 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VDD ............................................................................................................. 6.5V CS and U/D inputs w.r.t VSS.................................... -0.3V to 12.5V A, B and W terminals w.r.t VSS.................... -0.3V to VDD + 0.3V Current at Input Pins ..................................................±10 mA Current at Supply Pins ...............................................±10 mA Current at Potentiometer Pins ...................................±2.5 mA Storage temperature .....................................-65°C to +150°C Ambient temp. with power applied ................-55°C to +125°C ESD protection on all pins ........... ≥ 4 kV (HBM), ≥ 400V (MM) Maximum Junction Temperature (TJ) . .........................+150°C AC/DC CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V, TA = +25°C. Parameters Operating Voltage Range CS Input Voltage Sym VDD VCS Min 2.7 VSS Typ — — Max 5.5 12.5 Units V V The CS pin will be at one of three input levels (VIL, VIH or VIHH). (Note 6) 5.5V, CS = VSS, fU/D = 1 MHz 2.7V, CS = VSS, fU/D = 1 MHz Serial Interface Inactive (CS = VIH, U/D = VIH) EE Write cycle, TA = +25°C -202 devices (Note 1) -502 devices (Note 1) -103 devices (Note 1) -503 devices (Note 1) No Missing Codes Note 6 Conditions Supply Current IDD — — — — 45 15 0.3 0.6 2.1 5 10 50 64 RAB / 63 — — 1 3 2.52 6.0 12.0 60.0 — µA µA µA mA kΩ kΩ kΩ kΩ Taps Ω Resistance (± 20%) RAB 1.68 4.0 8.0 40.0 Resolution Step Resistance Note 1: 2: 3: 4: N RS — Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4022/24 only, test conditions are: Device Resistance 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ Current at Voltage 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA MCP4022 includes VWZSE MCP4024 includes VWFSE Comments 5: 6: 7: 8: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested. DS21945E-page 2 © 2006 Microchip Technology Inc. MCP4021/2/3/4 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V, TA = +25°C. Parameters Wiper Resistance (Note 3, Note 4) Nominal Resistance Tempco Sym RW ΔR/ΔT Min — — — — — Ratiometeric Tempco Full-Scale Error Zero-Scale Error Monotonicity Potentiometer Integral Non-linearity Potentiometer Differential Non-linearity Resistor Terminal Input Voltage Range (Terminals A, B and W) Maximum current through A, W or B Leakage current into A, W or B ΔVWA/ΔT VWFSE VWZSE N INL DNL VA,VW,VB IW IWL -0.5 -0.5 Vss — — — — Capacitance (PA) Capacitance (Pw) Capacitance (PB) Bandwidth -3 dB CAW CW CBW BW — — — — — — — Note 1: 2: 3: 4: — -0.5 -0.5 Typ 70 70 50 100 150 10 -0.1 +0.1 Yes ±0.25 ±0.25 — — 100 100 100 75 120 75 4 2 1 200 +0.5 +0.5 VDD 2.5 — — — — — — — — — — Max 125 325 — — — — +0.5 +0.5 Units Ω Ω ppm/°C ppm/°C ppm/°C ppm/°C LSb LSb Bits LSb LSb V mA nA nA nA pF pF pF MHz MHz MHz kHz MCP4021/23 only (Note 2) MCP4021/23 only (Note 2) Note 5, Note 6 Note 6 MCP4021 A = W = B = VSS MCP4022/23 A = W = VSS MCP4024 W = VSS f =1 MHz, code = 1Fh f =1 MHz, code = 1Fh f =1 MHz, code = 1Fh -202 devices -502 devices -103 devices -503 devices Code = 1F, output load = 30 pF 5.5V 2.7V TA = -20°C to +70°C TA = -40°C to +85°C TA = -40°C to +125°C MCP4021 and MCP4023 only, code = 1Fh Code 3Fh (MCP4021/23 only) Code 00h (MCP4021/23 only) Conditions Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4022/24 only, test conditions are: Device Resistance 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ Current at Voltage 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA MCP4022 includes VWZSE MCP4024 includes VWFSE Comments 5: 6: 7: 8: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested. © 2006 Microchip Technology Inc. DS21945E-page 3 MCP4021/2/3/4 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V, TA = +25°C. Parameters Rheostat Integral Non-linearity MCP4021 (Note 4, Note 8) MCP4022 and MCP4024 (Note 4) Sym R-INL Min -0.5 -8.5 -0.5 -5.5 -0.5 -3 -0.5 -1 Rheostat Differential Non-linearity MCP4021 (Note 4, Note 8) MCP4022 and MCP4024 (Note 4) R-DNL -0.5 -1 -0.5 -1 -0.5 -1 -0.5 -0.5 Note 1: 2: 3: 4: Typ ±0.25 +4.5 ±0.25 +2.5 ±0.25 +1 ±0.25 +0.25 ±0.25 +0.5 ±0.25 +0.25 ±0.25 0 ±0.25 0 Max +0.5 +8.5 +0.5 +5.5 +0.5 +3 +0.5 +1 +0.5 +2 +0.5 +1.25 +0.5 +1 +0.5 +0.5 Units LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb LSb -202 devices (2.1 kΩ) -502 devices (5 kΩ) -103 devices (10 kΩ) -503 devices (50 kΩ) -202 devices (2.1 kΩ) -502 devices (5 kΩ) -103 devices (10 kΩ) -503 devices (50 kΩ) Conditions 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) 5.5V 2.7V (Note 7) Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4022/24 only, test conditions are: Device Resistance 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ Current at Voltage 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA MCP4022 includes VWZSE MCP4024 includes VWFSE Comments 5: 6: 7: 8: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested. DS21945E-page 4 © 2006 Microchip Technology Inc. MCP4021/2/3/4 AC/DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise indicated, all parameters apply across the specified operating ranges. TA = -40°C to +125°C, 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ devices. Typical specifications represent values for VDD = 5.5V, VSS = 0V, TA = +25°C. Parameters Digital Inputs/Outputs (CS, U/D) Input High Voltage Input Low Voltage High-Voltage Input Entry Voltage High-Voltage Input Exit Voltage CS Pull-up/Pull-down Resistance CS Weak Pull-up/Pull-down Current Input Leakage Current CS and U/D Pin Capacitance RAM (Wiper) Value Value Range EEPROM Endurance EEPROM Range Initial Factory Setting Power Requirements Power Supply Sensitivity (MCP4021 and MCP4023 only) PSS — — Note 1: 2: 3: 4: 0.0015 0.0015 0.0035 0.0035 %/% %/% VDD = 4.5V to 5.5V, VA = 4.5V, Code = 1Fh VDD = 2.7V to 4.5V, VA = 2.7V, Code = 1Fh Endurance N N — 0h 1M — 1Fh — 3Fh Cycles hex hex WiperLock Technology = Off N 0h — 3Fh hex VIH VIL VIHH VIHH RCS IPU IIL CIN, COUT 0.7 VDD — 8.5 — — — -1 — — — — — 16 170 — 10 — 0.3 VDD 12.5(6) VDD+0.8(6) — — 1 — V V V V kΩ µA µA pF VDD = 5.5V, VCS = 3V VDD = 5.5V, VCS = 3V VIN = VDD fC = 1 MHz Threshold for WiperLock™ Technology Sym Min Typ Max Units Conditions Resistance is defined as the resistance between terminal A to terminal B. INL and DNL are measured at VW with VA = VDD and VB = VSS. (-202 devices VA = 4V). MCP4021/23 only, test conditions are: IW = 1.9 mA, code = 00h. MCP4022/24 only, test conditions are: Device Resistance 2.1 kΩ 5 kΩ 10 kΩ 50 kΩ Current at Voltage 5.5V 2.25 mA 1.4 mA 450 µA 90 µA 2.7V 1.1 mA 450 µA 210 µA 40 µA MCP4022 includes VWZSE MCP4024 includes VWFSE Comments 5: 6: 7: 8: Resistor terminals A, W and B’s polarity with respect to each other is not restricted. This specification by design Non-linearity is affected by wiper resistance (RW), which changes significantly over voltage and temperature. See Section 6.0 “Resistor” for additional information. The MCP4021 is externally connected to match the configurations of the MCP4022 and MCP4024, and then tested. © 2006 Microchip Technology Inc. DS21945E-page 5 MCP4021/2/3/4 tCSLO CS tLUC U/D tHI tLCUR tS W tS tLCUF tLO 1/fUD tLUC tLCUF tCSHI FIGURE 1-1: Increment Timing Waveform. SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C. Parameters CS Low Time CS High Time U/D to CS Hold Time CS to U/D Low Setup Time CS to U/D High Setup Time U/D High Time U/D Low Time Up/Down Toggle Frequency Wiper Settling Time Sym tCSLO tCSHI tLUC tLCUF tLCUR tHI tLO fUD tS Min 5 500 500 500 3 500 500 — 0.5 1 2 10 Wiper Response on Power-up Internal EEPROM Write Time tPU twc — — — Typ — — — — — — — — — — — 5 200 — — Max — — — — — — — 1 — — — — — 5 10 Units µs ns ns ns µs ns ns MHz µs µs µs µs ns ms ms @25°C -40°C to +125°C 2.1 kΩ, CL = 100 pF 5 kΩ, CL = 100 pF 10 kΩ, CL = 100 pF 50 kΩ, CL = 100 pF Conditions DS21945E-page 6 © 2006 Microchip Technology Inc. MCP4021/2/3/4 tCSLO CS 1/fUD tLUC U/D tLCUR tS W tLO tS tHI tLUC tLCUF tCSHI FIGURE 1-2: Decrement Timing Waveform. SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C. Parameters CS Low Time CS High Time U/D to CS Hold Time CS to U/D Low Setup Time CS to U/D High Setup Time U/D High Time U/D Low Time Up/Down Toggle Frequency Wiper Settling Time Sym tCSLO tCSHI tLUC tLCUF tLCUR tHI tLO fUD tS Min 5 500 500 500 3 500 500 — 0.5 1 2 10 Wiper Response on Power-up Internal EEPROM Write Time tPU twc — — — Typ — — — — — — — — — — — 5 200 — — Max — — — — — — — 1 — — — — — 5 10 Units µs ns ns ns µs ns ns MHz µs µs µs µs ns ms ms @25°C -40°C to +125°C 2.1 kΩ, CL = 100 pF 5 kΩ, CL = 100 pF 10 kΩ, CL = 100 pF 50 kΩ, CL = 100 pF Conditions © 2006 Microchip Technology Inc. DS21945E-page 7 MCP4021/2/3/4 tCSLO 12V CS 5V tHUC U/D tHI tHCUR W tS tS tHCUF tLO 1/fUD tHUC tHCUF tCSHI FIGURE 1-3: High-Voltage Increment Timing Waveform. SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C. Parameters CS Low Time CS High Time U/D High Time U/D Low Time Up/Down Toggle Frequency HV U/D to CS Hold Time HV CS to U/D Low Setup Time HV CS to U/D High Setup Time Wiper Settling Time Sym tCSLO tCSHI tHI tLO fUD tHUC tHCUF tHCUR tS Min 5 500 500 500 — 1.5 8 4.5 0.5 1 2 10 Wiper Response on Power-up Internal EEPROM Write Time tPU twc — — — Typ — — — — — — — — — — — 5 200 — — Max — — — — 1 — — — — — — — — 5 10 Units µs ns ns ns MHz µs µs µs µs µs µs µs ns ms ms @25°C -40°C to +125°C 2.1 kΩ, CL = 100 pF 5 kΩ, CL = 100 pF 10 kΩ, CL = 100 pF 50 kΩ, CL = 100 pF Conditions DS21945E-page 8 © 2006 Microchip Technology Inc. MCP4021/2/3/4 tCSLO CS 12V 5V tHUC U/D tHCUR tS W tLO tS tHI tCSHI 1/fUD tHUC tHCUF FIGURE 1-4: High-Voltage Decrement Timing Waveform. SERIAL TIMING CHARACTERISTICS Electrical Specifications: Unless otherwise noted, all parameters apply across the specified operating ranges. Extended (E): VDD = +2.7V to 5.5V, TA = -40°C to +125°C. Parameters CS Low Time CS High Time U/D High Time U/D Low Time Up/Down Toggle Frequency HV U/D to CS Hold Time HV CS to U/D Low Setup Time HV CS to U/D High Setup Time Wiper Settling Time Sym tCSLO tCSHI tHI tLO fUD tHUC tHCUF tHCUR tS Min 5 500 500 500 — 1.5 8 4.5 0.5 1 2 10 Wiper Response on Power-up Internal EEPROM Write Time tPU twc — — — Typ — — — — — — — — — — — 5 200 — — Max — — — — 1 — — — — — — — — 5 10 Units µs ns ns ns MHz µs µs µs µs µs µs µs ns ms ms @25°C -40°C to +125°C 2.1 kΩ, CL = 100 pF 5 kΩ, CL = 100 pF 10 kΩ, CL = 100 pF 50 kΩ, CL = 100 pF Conditions © 2006 Microchip Technology Inc. DS21945E-page 9 MCP4021/2/3/4 TEMPERATURE CHARACTERISTICS Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND. Parameters Temperature Ranges Specified Temperature Range Operating Temperature Range Storage Temperature Range Thermal Package Resistances Thermal Resistance, 5L-SOT-23 Thermal Resistance, 6L-SOT-23 Thermal Resistance, 8L-DFN (2x3) Thermal Resistance, 8L-MSOP Thermal Resistance, 8L-SOIC θJA θJA θJA θJA θJA — — — — — 255 230 85 206 117 — — — — — °C/W °C/W °C/W °C/W °C/W TA TA TA -40 -40 -65 — — — +125 +125 +150 °C °C °C Sym Min Typ Max Units Conditions DS21945E-page 10 © 2006 Microchip Technology Inc. MCP4021/2/3/4 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 80 250 2.7V -40°C 2.7V 25°C 2.7V 85°C 2.7V 125°C 5.5V -40°C 5.5V 25°C 5.5V 85°C 5.5V 125°C Device Current (IDD) (µA) 70 60 50 40 30 20 10 0 0.20 200 ICS 100 50 RCS 0 0.40 0.60 fU/D (MHz) 0.80 1.00 9 8 7 6 5 4 VCS (V) 3 2 1 FIGURE 2-1: Device Current (IDD) vs. U/D Frequency (fU/D) and Ambient Temperature (VDD = 2.7V and 5.5V). 600.0 FIGURE 2-4: CS Pull-up/Pull-down Resistance (RCS) and Current (ICS) vs. CS Input Voltage (VCS) (VDD = 5.5V). 12 1.8V Entry 2.7V Entry 5.5V Entry 1.8V Exit 2.7V Exit 5.5V Exit Device Current (IDD) (µA) VDD = 5.5V 400.0 300.0 200.0 VDD = 2.7V CS VPP Threshold (V) 500.0 10 8 6 4 2 0 100.0 0.0 -40 25 85 125 Ambient Temperature (°C) -40 -20 0 20 40 60 80 100 Ambient Temperature (°C) 120 FIGURE 2-2: Write Current (IWRITE) vs. Ambient Temperature and VDD. 0.8 FIGURE 2-5: CS High Input Entry/Exit Threshold vs. Ambient Temperature and VDD. Device Current (IDD) (µA) 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 -40 25 VDD = 5.5V VDD = 2.7V 85 125 Ambient Temperature (°C) FIGURE 2-3: Device Current (ISHDN) vs. Ambient Temperature and VDD. (CS = VDD). © 2006 Microchip Technology Inc. DS21945E-page 11 Ics (µA) 150 1000 800 600 400 200 0 -200 -400 -600 -800 -1000 RCS (kOhms) MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 140 120 0.075 0.05 120 100 0.8 0.6 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL Wiper Resistance (Rw)(ohms) Error (LSb) 80 60 40 20 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) RW DNL 0 -0.025 -0.05 -0.075 -0.1 INL 60 40 20 0 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 RW DNL 0.2 0 -0.2 -0.4 FIGURE 2-6: 2.1 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 400 0.1 FIGURE 2-8: 2.1 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 500 400 INL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 10 8 Wiper Resistance (Rw)(ohms) 300 INL 0.05 Wiper Resistance (Rw)(ohms) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL Error (LSb) 300 4 2 0 RW DNL 200 DNL RW 0 200 100 0 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 100 -0.05 0 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 -0.1 -2 FIGURE 2-7: 2.1 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). FIGURE 2-9: 2.1 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). DS21945E-page 12 © 2006 Microchip Technology Inc. Error (LSb) 6 Error (LSb) 100 INL 0.025 Wiper Resistance (Rw)(ohms) 80 0.4 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 2080 2500 2000 VDD = 5.5V -40°C 25°C 85°C 125°C Nominal Resistance (RAB) (Ohms) 2060 RWB (Ohms) 120 1500 1000 500 0 2040 2020 VDD = 2.7V 2000 -40 0 40 80 Ambient Temperature (°C) 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 64 FIGURE 2-10: 2.1 kΩ – Nominal Resistance (Ω) vs. Ambient Temperature and VDD. FIGURE 2-11: 2.1 kΩ – RWB (Ω) vs. Wiper Setting and Ambient Temperature. © 2006 Microchip Technology Inc. DS21945E-page 13 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. WIPER U/D WIPER U/D FIGURE 2-12: 2.1 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V). FIGURE 2-15: 2.1 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V). WIPER WIPER U/D U/D FIGURE 2-13: 2.1 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V). FIGURE 2-16: 2.1 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V). WIPER VDD FIGURE 2-14: Response Time. 2.1 kΩ – Power-Up Wiper DS21945E-page 14 © 2006 Microchip Technology Inc. MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 140 120 0.075 0.05 120 100 0.6 0.4 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL Wiper Resistance (Rw)(ohms) INL DNL Error (LSb) 80 60 40 20 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) RW 0 -0.025 -0.05 -0.075 -0.1 INL 60 40 DNL RW 0 -0.2 -0.4 -0.6 20 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) FIGURE 2-17: 5 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 450 400 350 300 250 200 150 100 50 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) DNL RW -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL FIGURE 2-19: 5 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V) 600 500 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.1 0.075 5 4 Wiper Resistance (Rw)(ohms) INL Wiper Resistance (Rw)(ohms) 0.05 Error (LSb) 0.025 0 -0.025 -0.05 -0.075 -0.1 -0.125 INL 300 200 100 RW 2 1 0 DNL 0 0 8 16 24 32 40 -1 56 48 Wiper Setting (decimal) FIGURE 2-18: 5 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). FIGURE 2-20: 5 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). © 2006 Microchip Technology Inc. DS21945E-page 15 Error (LSb) 400 3 Error (LSb) 100 0.025 Wiper Resistance (Rw)(ohms) 80 0.2 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 4950 6000 5000 -40°C 25°C 85°C 125°C Nominal Resistance (RAB) (Ohms) 4925 4900 4875 VDD = 5.5V 2.7V Vdd 5.5V Vdd RWB (Ohms) 4000 3000 2000 1000 4850 4825 VDD = 2.7V 4800 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) 0 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 64 FIGURE 2-21: 5 kΩ – Nominal Resistance (Ω) vs. Ambient Temperature and VDD. FIGURE 2-22: 5 kΩ – RWB (Ω) vs. Wiper Setting and Ambient Temperature. DS21945E-page 16 © 2006 Microchip Technology Inc. MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. WIPER WIPER U/D U/D FIGURE 2-23: 5 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V). FIGURE 2-25: 5 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V). WIPER WIPER U/D U/D FIGURE 2-24: 5 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V). FIGURE 2-26: 5 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V). © 2006 Microchip Technology Inc. DS21945E-page 17 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 120 100 0.05 0.025 120 100 0.15 0.1 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL Wiper Resistance (Rw)(ohms) DNL Wiper Resistance (Rw)(ohms) INL DNL Error (LSb) 60 40 INL -0.025 -0.05 RW 60 40 RW 0 -0.05 -0.1 -0.15 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 20 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) -0.075 -0.1 20 0 FIGURE 2-27: 10 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 450 400 350 300 250 200 150 100 50 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) RW INL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL FIGURE 2-29: 10 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 500 400 300 200 100 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.05 0.025 2.5 1.5 0.5 Wiper Resistance (Rw)(ohms) Wiper Resistance (Rw)(ohms) DNL -0.025 -0.05 -0.075 -0.1 -0.125 Error (LSb) DNL RW -0.5 -1.5 -2.5 FIGURE 2-28: 10 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). FIGURE 2-30: 10 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). DS21945E-page 18 © 2006 Microchip Technology Inc. Error (LSb) 0 INL Error (LSb) 80 0 80 0.05 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 10250 10230 10210 10190 10170 10150 10130 10110 10090 10070 10050 -40 -20 12000 10000 -40°C 25°C 85°C 125°C Nominal Resistance (RAB) (Ohms) RWB (Ohms) 8000 6000 4000 2000 VDD = 5.5V VDD = 2.7V 0 0 20 40 60 80 100 120 Ambient Temperature (°C) 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 64 FIGURE 2-31: 10 kΩ – Nominal Resistance (Ω) vs. Ambient Temperature and VDD. FIGURE 2-32: 10 kΩ – RWB (Ω) vs. Wiper Setting and Ambient Temperature. © 2006 Microchip Technology Inc. DS21945E-page 19 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. WIPER WIPER U/D U/D FIGURE 2-33: 10 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V). FIGURE 2-35: 10 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V). WIPER WIPER U/D U/D FIGURE 2-34: 10 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V). FIGURE 2-36: 10 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 5.5V). DS21945E-page 20 © 2006 Microchip Technology Inc. MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 200 160 120 INL -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.1 0.05 200 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.15 0.1 0.05 Wiper Resistance (Rw)(ohms) Wiper Resistance (Rw)(ohms) 150 INL Error (LSb) 0 -0.05 RW 100 RW 80 40 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) 0 -0.05 -0.1 -0.1 -0.15 50 DNL 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) FIGURE 2-37: 50 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 600 500 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL FIGURE 2-39: 50 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 5.5V). 600 500 -40C Rw -40C INL -40C DNL 25C Rw 25C INL 25C DNL 85C Rw 85C INL 85C DNL 125C Rw 125C INL 125C DNL 0.05 0.025 1.5 1 Wiper Resistance (Rw)(ohms) Wiper Resistance (Rw)(ohms) DNL RW INL Error (LSb) 300 INL -0.025 -0.05 RW 300 DNL 0 -0.5 -1 -1.5 0 8 16 24 32 40 48 56 Wiper Setting (decimal) 200 100 0 0 8 16 24 32 40 48 56 Wiper Setting (decimal) 200 100 0 -0.075 -0.1 FIGURE 2-38: 50 kΩ Pot Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). FIGURE 2-40: 50 kΩ Rheo Mode – RW (Ω), INL (LSb), DNL (LSb) vs. Wiper Setting and Ambient Temperature (VDD = 2.7V). © 2006 Microchip Technology Inc. DS21945E-page 21 Error (LSb) 400 0 400 0.5 Error (LSb) DNL MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 60000 50000 -40C 25C 85C 125C 49800 Nominal Resistance (RAB) (Ohms) 49600 49400 49200 49000 48800 48600 48400 48200 48000 -40 -20 0 20 40 60 80 100 120 Ambient Temperature (°C) VDD = 2.7V RWB (Ohms) VDD = 5.5V 40000 30000 20000 10000 0 0 8 16 24 32 40 48 Wiper Setting (decimal) 56 64 FIGURE 2-41: 50 kΩ – Nominal Resistance (Ω) vs. Ambient Temperature and VDD. FIGURE 2-42: 50 kΩ – RWB (Ω) vs. Wiper Setting and Ambient Temperature. DS21945E-page 22 © 2006 Microchip Technology Inc. MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. U/D U/D WIPER WIPER FIGURE 2-43: 50 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 2.7V). FIGURE 2-46: 50 kΩ – Low-Voltage Increment Wiper Settling Time (VDD = 2.7V). U/D U/D WIPER WIPER FIGURE 2-44: 50 kΩ – Low-Voltage Decrement Wiper Settling Time (VDD = 5.5V). FIGURE 2-47: 50 kΩ - Low-Voltage Increment Wiper Settling Time (VDD = 5.5V). WIPER VDD FIGURE 2-45: Response Time. 50 kΩ – Power-Up Wiper © 2006 Microchip Technology Inc. DS21945E-page 23 MCP4021/2/3/4 Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V. 4.5 -3dB Frequency (MHz) 4 3.5 3 2.5 2 1.5 1 0.5 0 -40 25 Temperature (°C) 2.1 k A VIN +5V W + VOUT ~ DUT B 5k 10 k 50 k OFFSET GND 2.5V DC 125 FIGURE 2-48: Temperature. -3 dB Bandwidth vs. FIGURE 2-49: Circuit. -3 dB Bandwidth Test DS21945E-page 24 © 2006 Microchip Technology Inc. MCP4021/2/3/4 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: PIN FUNCTION TABLE Pin Type P P I/O I/O I I/O — I Buffer Type — — A A TTL A — TTL Pin Number MCP4021 (SOIC-8) 1 2 3 4 5 6 7 8 MCP4022 MCP4024 Symbol MCP4023 (SOT-23-5) (SOT-23-6) 1 2 6 5 4 — — 3 1 2 — 5 4 — — 3 VDD VSS A W CS B NC U/D Function Positive Power Supply Input Ground Potentiometer Terminal A Potentiometer Wiper Terminal Chip Select Input Potentiometer Terminal B No Connection Increment/Decrement Input Legend: TTL = TTL compatible input I = Input P = Power A = Analog input O = Output 3.1 Positive Power Supply Input (VDD) 3.4 Potentiometer Wiper (W) Terminal The VDD pin is the device’s positive power supply input. The input power supply is relative to VSS and can range from 2.7V to 5.5V. A decoupling capacitor on VDD (to VSS) is recommended to achieve maximum performance. 3.2 Ground (VSS) The terminal W pin is connected to the internal potentiometer’s terminal W (the wiper). The wiper terminal is the adjustable terminal of the digital potentiometer. The terminal W pin does not have a polarity relative to terminals A or B pins. The terminal W pin can support both positive and negative current. The voltage on teminal W must be between VSS and VDD. The VSS pin is the device ground reference. 3.5 Potentiometer Terminal B 3.3 Potentiometer Terminal A The terminal A pin is connected to the internal potentiometer’s terminal A (available on some devices). The potentiometer’s terminal A is the fixed connection to the 0x3F terminal of the digital potentiometer. The terminal A pin is available on the MCP4021, MCP4022 and MCP4023 devices. The terminal A pin does not have a polarity relative to the terminal W or B pins. The terminal A pin can support both positive and negative current. The voltage on teminal A must be between VSS and VDD. The terminal A pin is not available on the MCP4024. The potentiometer’s terminal A is internally floating. The terminal B pin is connected to the internal potentiometer’s terminal B (available on some devices). The potentiometer’s terminal B is the fixed connection to the 0x00 terminal of the digital potentiometer. The terminal B pin is available on the MCP4021 device. The terminal B pin does not have a polarity relative to the terminal W or A pins. The terminal B pin can support both positive and negative current. The voltage on teminal B must be between VSS and VDD. The terminal B pin is not available on the MCP4022, MCP4023 and MCP4024 devices. For the MCP4023 and MCP4024, the internal potentiometer’s terminal B is internally connected to VSS. Terminal B does not have a polarity relative to terminals W or A. Terminal B can support both positive and negative current. For the MCP4022, terminal B is internally floating. © 2006 Microchip Technology Inc. DS21945E-page 25 MCP4021/2/3/4 3.6 Chip Select (CS) 3.7 Increment/Decrement (U/D) The CS pin is the chip select input. Forcing the CS pin to VIL enables the serial commands. These commands can increment and decrement the wiper. Depending on the command, the wiper may (or may not) be saved to non-volatile memeory (EEPROM). Forcing the CS pin to VIHH enables the high-voltage serial commands. These commands can increment and decrement the wiper and enable or disable the WiperLock technology. The wiper is saved to non-volatile memory (EEPROM). The CS pin has an internal pull-up resistor. The resistor will become “disabled” when the voltage on the CS pin is below the VIH level. This means that when the CS pin is “floating”, the CS pin will be pulled to the VIH level (serial communication (the U/D pin) is ignored). And when the CS pin is driven low (VIL), the resistance becomes very large to reduce the device current consumption when serial commands are occurring. See Figure 2-4 for additional information. The U/D pin input is used to increment or decrement the wiper on the digital potentiometer. An increment moves the wiper one step toward terminal A, while a decrement moves the wiper one step toward terminal B. DS21945E-page 26 © 2006 Microchip Technology Inc. MCP4021/2/3/4 4.0 GENERAL OVERVIEW EQUATION 4-1: RS CALCULATION R AB R S = --------63 The MCP402X devices are general purpose digital potentiometers intended to be used in applications where a programmable resistance with moderate bandwidth is desired. Applications generally suited for the MCP402X devices include: • • • • Set point or offset trimming Sensor calibration Selectable gain and offset amplifier designs Cost-sensitive mechanical trim pot replacement EQUATION 4-2: RWB CALCULATION R AB N R WB = ------------- + R W 63 N = 0 to 63 (decimal) 1 LSb is the ideal resistance difference between two successive codes. If we use N = 1 and RW = 0 in Equation 4-2, we can calculate the step size for each increment or decrement command. The MCP4021 device offers a voltage divider (potentiometer) with all terminals available on pins. The MCP4022 is a true rheostat, with terminal A and the wiper (W) of the variable resistor available on pins. The MCP4023 device offers a voltage divider (potentiometer) with terminal B connected to ground. The MCP4024 device is a rheostat device with terminal A of the resistor floating, terminal B connected to ground, and the wiper (W) available on pin. The MCP4021 can be externally configured to implement any of the MCP4022, MCP4023 or MCP4024 configurations. The digital potentiometer is available in four nominal resistances (RAB), where the nominal resistance is defined as the resistance between terminal A and terminal B. The four nominal resistances are 2.1 kΩ, 5 kΩ, 10 kΩ and 50 kΩ. There are 63 resistors in a string between terminal A and terminal B. The wiper can be set to tap onto any of these 63 resistors thus providing 64 possible settings (including terminal A and terminal B). Figure 4-1 shows a block diagram for the resistive network of the device. Equation 4-1 shows the calculation for the step resistance, while Equation 4-2 illustrates the calculation used to determine the resistance between the wiper and terminal B. A N = 63 RS N = 62 RS N = 61 RS RW (1) 3Fh RW (1) 3Eh RW (1) 4.1 Serial Interface 3Dh W N=1 RS N=0 B RW (1) A 2-wire synchronous serial protocol is used to increment or decrement the digital potentiometer’s wiper terminal. The Increment/Decrement (U/D) protocol utilizes the CS and U/D input pins. Both inputs are tolerant of signals up to 12.5V without damaging the device. The CS pin can differenciate between two high-voltage levels, VIH and VIHH. This enables additional commands without requiring additional input pins. The high-voltage commands (VIHH on the CS pin) are similar to the standard commands, except that they control (enable, disable, ...) the state of the non-volatile WiperLock technolgy feature. The simple U/D protocol uses the state of the U/D pin at the falling edge of the CS pin to determine if Increment or Decrement mode is desired. Subsequent rising edges of the U/D pin move the wiper. The wiper value will not underflow or overflow. The new wiper setting can be saved to EEPROM, if desired, by selecting the state of the U/D pin during the rising edge of the CS pin. The non-volatile wiper enables the MCP4021/2/3/4 to operate stand alone (without microcontroller control). 01h RW (1) 00h Analog Mux Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation effects the smaller resistance devices (2.1 kΩ) more. FIGURE 4-1: Resistor Block Diagram. © 2006 Microchip Technology Inc. DS21945E-page 27 MCP4021/2/3/4 4.2 The WiperLock™ Technology The MCP4021/2/3/4 device’s WiperLock technology allows application-specific calibration settings to be secured in the EEPROM without requiring the use of an additional write-protect pin. The WiperLock technology prevents commands from doing the following: the serial The default settings of the MCP4021/2/3/4 device’s from the factory are shown in Table 4-1. TABLE 4-1: DEFAULT FACTORY SETTINGS SELECTION WiperLock™ Technology Setting Typical RAB Value 2.1 kΩ 5.0 kΩ 10.0 kΩ 50.0 kΩ Wiper Code 1Fh 1Fh 1Fh 1Fh Package Code -202 -502 -103 -503 • Incrementing or decrementing the wiper setting • Writing the wiper setting to the non-volatile memory Enabling and disabling the WiperLock technology feature requires high-voltage serial commands (CS = VIHH). Incrementing and decrementing the wiper requires high-voltage commands when the feature is enabled. The high-voltage threshold (VIHH) is intended to prevent the wiper setting from being altered by noise or intentional transitions on the U/D and CS pins, while still providing flexibility for production or calibration environments. Both the CS and U/D input pins are tolerant of signals up to 12V. This allows the flexibility to multiplex the digital pot’s control signals onto application signals for manufacturing/calibration. Default POR Wiper Setting Mid-scale Mid-scale Mid-scale Mid-scale Disabled Disabled Disabled Disabled It is good practice in your manufacturing flow to configure the device to your desired settings. 4.4 Brown Out If the device VDD is below the specified minimum voltage, care must be taken to ensure that the CS and U/D pins do not “create” any of the serial commands. When the device VDD drops below Vmin (2.7V), the electrical performance may not meet the data sheet specifications (see Figure 4-2). The wiper may be unknown or initialized to the value stored in the EEPROM. Also the device may be capable of incrementing, decrementing and writing to its EEPROM if a valid command is detected on the CS and U/D pins. 4.3 Power-up When the device powers up, the last saved wiper setting is restored. While VDD < Vmin (2.7V), the electrical performance may not meet the data sheet specifications (see Figure 4-2). The wiper may be unknown or initialized to the value stored in the EEPROM. Also the device may be capable of incrementing, decrementing and writing to its EEPROM, if a valid command is detected on the CS and U/D pins. 4.5 Serial Interface Inactive The serial interface is inactive any time the CS pin is at VIH and all write cycles are completed. VDD Outside Specified AC/DC Range EEPROM Write Protect 2.7V VWP VSS FIGURE 4-2: Power-up and Brown-out. DS21945E-page 28 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.0 5.1 SERIAL INTERFACE Overview 5.2 Serial Commands The MCP4021/2/3/4 utilizes a simple 2-wire interface to increment or decrement the digital potentiometer’s wiper terminal (W), store the wiper setting in non-volatile memory and turn the WiperLock technology feature on or off. This interface uses the Chip Select (CS) pin, while the U/D pin is the Up/Down input. The Increment/Decrement protocol enables the device to move one step at a time through the range of possible resistance values. The wiper value is initialized with the value stored in the internal EEPROM upon power-up. A wiper value of 00h connects the wiper to terminal B. A wiper value of 3Fh connects the wiper to terminal A. Increment commands move the wiper toward terminal A, but will not increment to a value greater than 3Fh. Decrement commands move the wiper toward terminal B, but will not decrement below 00h. Refer to Section 1.0 “Electrical Characteristics”, AC/DC Electrical Characteristics table for detailed input threshold and timing specifications. Communication is unidirectional. Therefore, the value of the current wiper setting cannot be read out of the MCP402X device. The MCP402X devices support 10 serial commands. The commands can be grouped into the following types: • Serial Commands • High-voltage Serial Commands All the commands are shown in Table 5-1. The command type is determined by the voltage level on the CS pin. The initial state that the CS pin must be driven is VIH. From VIH, the two levels that the CS pin can be driven are: • VIL • VIHH If the CS pin is driven from VIH to VIL, a serial command is selected. If the CS pin is driven from VIH to VIHH, a high-voltage serial command is selected. High-voltage serial commands control the state of the WiperLock technology. This is a unique feature, where the user can determine whether or not to “lock” or “unlock” the wiper state. High-voltage serial commands increment/decrement the wiper regardless of the status of the WiperLock technology. TABLE 5-1: COMMANDS Saves Wiper Value in EEPROM — Yes — Yes Yes Yes Yes Yes Yes Yes Yes High Voltage on CS pin? — — — — — Yes Yes Yes Yes Yes Yes After Command Wiper is “locked”/ ”unlocked” unlocked unlocked unlocked unlocked unlocked unlocked locked unlocked locked unlocked locked Works when Wiper is “locked”? Note 1 Note 1 Note 1 Note 1 Note 1 Yes Yes Yes Yes Yes Yes Command Name Increment without Writing Wiper Setting to EEPROM Increment with Writing Wiper Setting to EEPROM Decrement without Writing Wiper Setting to EEPROM Decrement with Writing Wiper Setting to EEPROM Write Wiper Setting to EEPROM High-Voltage Increment and Disable WiperLock Technology High-Voltage Increment and Enable WiperLock Technology High-Voltage Decrement and Disable WiperLock Technology High-Voltage Decrement and Enable WiperLock Technology Write Wiper Setting to EEPROM and Disable WiperLock Technology Write Wiper Setting to EEPROM and Enable WiperLock Technology Note 1: This command will only complete if wiper is “unlocked” (WiperLock Technology is Disabled). © 2006 Microchip Technology Inc. DS21945E-page 29 MCP4021/2/3/4 5.2.1 INCREMENT WITHOUT WRITING WIPER SETTING TO EEPROM This mode is achieved by initializing the U/D pin to a high state (VIH) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. This is shown in Figure 5-1. After the wiper is incremented to the desired position, the CS pin should be forced to VIH to ensure that “unexpected” transitions (on the U/D pin do not cause the wiper setting to increment. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. The EEPROM value has not been updated to this new wiper value, so if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the EEPROM. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered. This is since an EEPROM write cycle (twc) is not active. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. VIH CS VIL 1 U/D VIL X X X X+1 X X+2 X X+3 X X+4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable Note: If WiperLock technology enabled, wiper will not move. 2 3 4 5 6 VIH EEPROM Wiper FIGURE 5-1: Increment without Writing Wiper Setting to EEPROM. DS21945E-page 30 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.2.2 INCREMENT WITH WRITING WIPER SETTING TO EEPROM This mode is achieved by initializing the U/D pin to a high state (VIH) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. This is shown in Figure 5-2. After the wiper is incremented to the desired position, the U/D pin should be driven low (VIL). Then when the CS pin is forced to VIH, the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM). VIH CS VIH U/D VIL 1 2 3 4 tWC 5 6 VIL X X X X+1 X X+2 X X+3 X X+4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable Note: If WiperLock technology enabled, wiper will not move. To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment, the U/D pin should be driven low and the CS pin forced to VIH as soon as possible (within device specifications) after the last desired increment occurs. After the CS pin is driven to VIH (from VIL), all other serial commands are ignored until the EEPROM write cycle (twc) completes. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. VIH EEPROM X+4 Wiper FIGURE 5-2: Increment with Writing Wiper Setting to EEPROM. © 2006 Microchip Technology Inc. DS21945E-page 31 MCP4021/2/3/4 5.2.3 DECREMENT WITHOUT WRITING WIPER SETTING TO EEPROM This mode is achieved by initializing the U/D pin to a low state (VIL) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin will decrement the wiper setting toward terminal B. This is shown in Figure 5-3. After the wiper is decremented to the desired position, the U/D pin should be forced low (VIL) and the CS pin should be forced to VIH. This will ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to decrement. Driving the CS pin to VIH should occur as soon as possible (within device specifications) after the last desired increment occurs. The EEPROM value has not been updated to this new wiper value, so, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with the wiper setting in the EEPROM. After the CS pin is driven to VIH (from VIL), any other serial command may immediately be entered, since an EEPROM write cycle (tWC) is not started. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. VIH CS VIL 1 U/D VIL X X X X-1 X X-2 X X-3 X X-4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable Note: If WiperLock technology enabled, wiper will not change. 2 3 4 VIH 5 6 VIL EEPROM Wiper FIGURE 5-3: Decrement without Writing Wiper Setting to EEPROM. DS21945E-page 32 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.2.4 DECREMENT WITH WRITING WIPER SETTING TO EEPROM This mode is achieved by initializing the U/D pin to a low state (VIL) prior to achieving a low state (VIL) on the CS pin. Subsequent rising edges of the U/D pin decrement the wiper setting (toward terminal B). This is shown in Figure 5-4. After the wiper is decremented to the desired position, the U/D pin should remain high (VIH). Then when the CS pin is raised to VIH, the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM). To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to decrement, the U/D pin should be driven low (VIL) and the CS pin forced to VIH as soon as possible (within device specifications) after the last desired increment occurs. After the CS pin is driven to VIH (from VIL), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. VIH CS VIL 1 U/D VIL 2 3 4 tWC 5 6 VIH EEPROM X X X X-1 X X-2 X X-3 X X-4 X-4 Wiper WiperLock™ Technology WiperLock Technology Enable WiperLock Technology Disable Note: If WiperLock technology enabled, wiper will not change. FIGURE 5-4: Decrement with Writing Wiper Setting to EEPROM. © 2006 Microchip Technology Inc. DS21945E-page 33 MCP4021/2/3/4 5.2.5 WRITE WIPER SETTING TO EEPROM To write the current wiper setting to EEPROM, force both the CS pin and U/D pin to VIH. Then force the CS pin to VIL. Before there is a rising edge on the U/D pin, force the CS pin to VIH. This causes the wiper setting value to be written to EEPROM. Note: After the U/D pin is forced to VIL, each rising edge on the U/D pin will cause the wiper to increment. This is the same command as the “Increment with Writing Wiper Setting to EEPROM“ command, but the U/D pin is held at VIL, so the wiper is not incremented. VIH CS VIH U/D VIL tWC 5 6 VIL X X+4 When the CS pin is forced to VIH, the wiper value is written to the EEPROM. Therefore, if the device voltage is lowered below the RAM retention voltage of the device, once the device returns to the operating range, the wiper will be loaded with this wiper setting (stored in the EEPROM). To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment, force the CS pin to VIH as soon as possible (within device specifications) after the U/D pin is forced to VIL. After the CS pin is driven to VIH (from VIL), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. VIH EEPROM Wiper WiperLock™ Technology X+4 WiperLock Technology Enable WiperLock Technology Disable FIGURE 5-5: Write Wiper Setting to EEPROM. DS21945E-page 34 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.2.6 HIGH-VOLTAGE INCREMENT AND DISABLE WiperLock TECHNOLOGY This mode is achieved by initializing the U/D pin to a high state (VIH) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the high state (VIH) prior to forcing the CS pin to VIH. This begins a write cycle and disables the WiperLock Technology feature (See Figure 5-6). VIHH VIH CS VIH U/D VIL X X X X+1 X X+2 X X+3 X X+4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable X+4 1 2 3 4 tWC 5 6 VIH VIH After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. EEPROM Wiper FIGURE 5-6: High-Voltage Increment and Disable WiperLock™ Technology. © 2006 Microchip Technology Inc. DS21945E-page 35 MCP4021/2/3/4 5.2.7 HIGH-VOLTAGE INCREMENT AND ENABLE WiperLock TECHNOLOGY This mode is achieved by initializing the U/D pin to a high state (VIH) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin increment the wiper setting toward terminal A. Set the U/D pin to the low state (VIL) prior to forcing the CS pin to VIH. This begins a write cycle and enables the WiperLock Technology feature (See Figure 5-7). VIHH VIH CS VIH U/D VIL X X X X+1 X X+2 X X+3 X X+4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable X+4 1 2 3 4 tWC 5 6 VIL VIH After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. Note: The wiper value will not overflow. That is, once the wiper value equals 0x3F, subsequent increment commands are ignored. EEPROM Wiper FIGURE 5-7: High-Voltage Increment and Enable WiperLock™ Technology. DS21945E-page 36 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.2.8 HIGH-VOLTAGE DECREMENT AND DISABLE WiperLock TECHNOLOGY This mode is achieved by initializing the U/D pin to a low state (VIL) prior to the CS pin being driven to VIHH. Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to the low state (VIL) prior to forcing the CS pin to VIH. This begins a write cycle and disables the WiperLock Technology feature (See Figure 5-8). VIHH VIH CS 1 U/D VIL X X X X-1 X X-2 X X-3 X X-4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable X-4 2 3 4 tWC 5 6 VIH VIL VIH After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. EEPROM Wiper FIGURE 5-8: High-Voltage Decrement and Disable WiperLock™ Technology. © 2006 Microchip Technology Inc. DS21945E-page 37 MCP4021/2/3/4 5.2.9 HIGH-VOLTAGE DECREMENT AND ENABLE WiperLock TECHNOLOGY This mode is achieved by initializing the U/D pin to the low state (VIL) prior to driving the CS pin to VIHH. Subsequent rising edges of the U/D pin decrement the wiper setting toward terminal B. Set the U/D pin to a high state (VIH) prior to forcing the CS pin to VIH. This begins a write cycle and enables the WiperLock Technology feature (See Figure 5-9). After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. Note: The wiper value will not underflow. That is, once the wiper value equals 0x00, subsequent decrement commands are ignored. VIHH VIH CS 1 U/D VIL X X X X-1 X X-2 X X-3 X X-4 WiperLock Technology Enable WiperLock™ Technology WiperLock Technology Disable X-4 2 3 4 tWC VDD 5 6 VIH VIH EEPROM Wiper FIGURE 5-9: High-Voltage Decrement and Enable WiperLock™ Technology. DS21945E-page 38 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.2.10 WRITE WIPER SETTING TO EEPROM AND DISABLE WiperLock TECHNOLOGY To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to change, force the CS pin to VIH as soon as possible (within device specifications) after the CS pin is forced to VIHH. After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. This mode is achieved by keeping the U/D pin static (either at VIL or at VIH), while the CS pin is driven from VIH to VIHH and then returned to VIH. When the falling edge of the CS pin occurs (from VIHH to VIH), the wiper value is written to EEPROM and the WiperLock Technology is disabled (See Figure 5-10). VIHH VIH CS VIH tWC VIH VIL U/D EEPROM X X+4 Wiper WiperLock™ Technology X+4 WiperLock Technology Enable WiperLock Technology Disable FIGURE 5-10: Write Wiper Setting to EEPROM and Disable WiperLock™ Technology. © 2006 Microchip Technology Inc. DS21945E-page 39 MCP4021/2/3/4 5.2.11 WRITE WIPER SETTING TO EEPROM AND ENABLE WiperLock TECHNOLOGY To ensure that “unexpected” transitions on the U/D pin do not cause the wiper setting to increment, force the CS pin to VIH as soon as possible (within device specifications) after the U/D pin is forced to VIL. After the CS pin is driven to VIH (from VIHH), all other serial commands are ignored until the EEPROM write cycle (tWC) completes. This mode is achieved by initializing the U/D and CS pins to a high state (VIH) prior to the CS pin being driven to VIHH (from VIH). Set the U/D pin to a low state (VIL) prior to forcing the CS pin to VIH (from VIHH). This begins a write cycle and enables the WiperLock Technology feature (See Figure 5-11). VIHH VIH CS VIH U/D VIH tWC VIL X X+4 EEPROM Wiper WiperLock™ Technology X+4 WiperLock Technology Enable WiperLock Technology Disable FIGURE 5-11: Write Wiper Setting to EEPROM and Enable WiperLock™ Technology. DS21945E-page 40 © 2006 Microchip Technology Inc. MCP4021/2/3/4 5.3 CS High Voltage Depending on the requirements of the system, the use of high voltage (VIHH) on the CS pin, may or may not be required during system operation. Table 5-2 shows possible system applications, and whether a high voltage (VIHH) is required on the system. The MCP402X supports six high-voltage commands (the CS input voltage must meet the VIHH specification). The circuit in Figure 5-13 shows the method used on the MCP402X Non-volatile Digital Potentiometer Evaluation Board. This method requires that the system voltage be approximately 5V. This ensures that when the PIC10F206 enters a brown-out condition, there is an insufficent voltage level on the CS pin to change the stored value of the wiper. The MCP402X Non-volatile Digital Potentiometer Evaluation Board User’s Guide (DS51546) contains a complete schematic. GP0 is a general purpose I/O pin, while GP2 can either be a general purpose I/O pin or it can output the internal clock. High Voltage From Calibration Unit Not Required Required For the serial commands, configure the GP2 pin as an input (high impedence). The output state of the GP0 pin will determine the voltage on the CS pin (VIL or VIH). For high-voltage serial commands, force the GP0 output pin to output a high level (VOH) and configure the GP2 pin to output the internal clock. This will form a charge pump and increase the voltage on the CS pin (when the system voltage is approximately 5V). PIC10F206 TABLE 5-2: HIGH-VOLTAGE APPLICATIONS System Operation Production calibration only - system should not update wiper setting WiperLock™ Technogy disabled during system operation Wiper setting can be updated and “locked” during system operation 5.3.1 TECHNIQUES TO FORCE THE CS PIN TO VIHH R1 GP0 MCP402X GP2 C1 CS C2 The circuit in Figure 5-12 shows a method using the TC1240A doubling charge pump. When the SHDN pin is high, the TC1240A is off, and the level on the CS pin is controlled by the PIC® microcontrollers (MCUs) IO2 pin. When the SHDN pin is low, the TC1240A is on and the VOUT voltage is 2 * VDD. The resistor R1 allows the CS pin to go higher than the voltage such that the PIC MCU’s IO2 pin “clamps” at approximately VDD. TC1240A C+ VIN CSHDN VOUT R1 C2 MCP402X CS FIGURE 5-13: MCP402X Non-volatile Digital Potentiometer Evaluation Board (MCP402XEV) implementation to generate the VIHH voltage. PIC MCU IO1 ® C1 IO2 FIGURE 5-12: Using the TC1240A to generate the VIHH voltage. © 2006 Microchip Technology Inc. DS21945E-page 41 MCP4021/2/3/4 6.0 RESISTOR Digital potentiometer applications can be divided into two categories: • Rheostat configuration • Potentiometer (or voltage divider) configuration Figure 6-1 shows a block diagram for the MCP402X resistors. A N = 63 RS N = 62 RS N = 61 RS RW (1) RW (1) 3Dh Terminal A and B, as well as the wiper W, do not have a polarity. These terminals can support both positive and negative current. W N=1 RS N=0 B RW (1) Step resistance (RS) is the resistance from one tap setting to the next. This value will be dependent on the RAB value that has been selected. Table 6-1 shows the typical step resistances for each device. The total resistance of the device has minimal variation due to operating voltage (see Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37). TABLE 6-1: Part Number MCP402X-203E TYPICAL STEP RESISTANCES Typical Resistance (Ω) Total (RAB) 2100 5000 10000 50000 Step (RS) 33.33 79.37 158.73 793.65 3Fh RW (1) 3Eh MCP402X-503E MCP402X-104E MCP402X-504E 01h RW (1) 00h Analog Mux Note 1: The wiper resistance is tap dependent. That is, each tap selection resistance has a small variation. This variation effects the smaller resistance devices (2.1 kΩ) more. FIGURE 6-1: Resistor Block Diagram. DS21945E-page 42 © 2006 Microchip Technology Inc. MCP4021/2/3/4 6.1 6.1.1 Resistor Configurations RHEOSTAT CONFIGURATION 6.1.2 POTENTIOMETER CONFIGURATION When used as a rheostat, two of the three digital potentiometer’s terminals are used as a resistive element in the circuit. With terminal W (wiper) and either terminal A or terminal B, a variable resistor is created. The resistance will depend on the tap setting of the wiper and the wiper’s resistance. The resistance is controlled by changing the wiper setting. The unused terminal (B or A) should be left floating. Figure 6-2 shows the two possible resistors that can be used. Reversing the polarity of the A and B terminals will not affect operation. When used as a potentiometer, all three terminals are tied to different nodes in the circuit. This allows the potentiometer to output a voltage proportional to the input voltage. This configuration is sometimes called voltage divider mode. The potentiometer is used to provide a variable voltage by adjusting the wiper position between the two endpoints as shown in Figure 6-3. Reversing the polarity of the A and B terminals will not affect operation. V1 A A W B Resistor RAW or RBW W B V2 V3 FIGURE 6-3: Potentiometer Configuration. FIGURE 6-2: Rheostat Configuration. This allows the control of the total resistance between the two nodes. The total resistance depends on the “starting” terminal to the wiper terminal. At the code 00h, the RBW resistance is minimal (RW), but the RAW resistance in maximized (RAB + RW). Conversely, at the code 3Fh, the RAW resistance is minimal (RW), but the RBW resistance in maximized (RAB + RW). The resistance step size (RS) equates to one LSb of the resistor. Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA. The temperature coefficient of the RAB resistors is minimal by design. In this configuration, the resistors all change uniformally, so minimal variation should be seen. The wiper resistor temperature coefficient is different from the RAB temperature coefficient. The voltage at node V3 (Figure 6-3) is not dependent on this wiper resistance, just the ratio of the RAB resistors, so this temperature coefficient in most cases can be ignored. Note: To avoid damage to the internal wiper circuitry in this configuration, care should be taken to insure the current flow never exceeds 2.5 mA. The change in wiper-to-end terminal resistance over temperature is shown in Figure 2-6, Figure 2-17, Figure 2-27 and Figure 2-37. The most variation over temperature will occur in the first few codes due to the wiper resistance coefficient affecting the total resistance. The remaining codes are dominated by the total resistance tempco RAB. © 2006 Microchip Technology Inc. DS21945E-page 43 MCP4021/2/3/4 6.2 Wiper Resistance Wiper resistance is the series resistance of the wiper. This resistance is typically measured when the wiper is positioned at either zero-scale (00h) or full-scale (3Fh). The wiper resistance in potentiometer-generated voltage divider applications is not a significant source of error. The wiper resistance in rheostat applications can create significant non-linearity as the wiper is moved toward zero-scale (00h). The lower the nominal resistance, the greater the possible error. Wiper resistance is significant depending on the devices operating voltage. As the device voltage decreases, the wiper resistance increases (see Figure 6-4 and Table 6-2). In a rheostat configuration, this change in voltage needs to be taken into account, particularly for the lower resistance devices. For the 2.1 kΩ device, the maximum wiper resistance at 5.5V is approximately 6% of the total resistance, while at 2.7V, it is approximately 15.5% of the total resistance. In a potentiometer configuration, the wiper resistance variation does not effect the output voltage seen on the terminal W pin. RW The slope of the resistance has a linear area (at the higher voltages) and a non-linear area (at the lower voltages), where resistance increases faster than the voltage drop (at low voltages). VDD Note: The slope of the resistance has a linear area (at the higher voltages) and a nonlinear area (at the lower voltages). FIGURE 6-4: Relationship of Wiper Resistance (RW) to Voltage Since there is minimal variation of the total device resistance over voltage, at a constant temperature (see Figure 2-6, Figure 2-17, Figure 2-27 or Figure 2-37), the change in wiper resistance over voltage can have a significant impact on the INL and DNL error. TABLE 6-2: Typical Total (RAB) 2100 5000 10000 50000 Note 1: 2: Step (RS) 33.33 79.37 TYPICAL STEP RESISTANCES AND RELATIONSHIP TO WIPER RESISTANCE Resistance (Ω) Wiper (RW) Typical 75 75 75 75 Max @ Max @ 5.5V 2.7V 125 125 125 125 325 325 325 325 RW = Typical 225.0% 94.5% 47.25% 9.45% RW / RS (%) (1) RW = Max RW = Max @ 5.5V @ 2.7V 375.0% 157.5% 78.75% 15.75% 975.0% 409.5% 204.75% 40.95% RW / RAB (%) (2) RW = Typical 3.57% 1.5% 0.75% 0.15% RW = Max RW = Max @ 5.5V @ 2.7V 5.95% 2.50% 1.25% 0.25% 15.48% 6.50% 3.25% 0.65% 158.73 793.65 RS is the typical value. The variation of this resistance is minimal over voltage. RAB is the typical value. The variation of this resistance is minimal over voltage. DS21945E-page 44 © 2006 Microchip Technology Inc. MCP4021/2/3/4 6.3 Operational Characteristics 6.3.1.2 Differential Non-Linearity (DNL) Understanding the operational characteristics of the device’s resistor components is important to the system design. DNL error is the measure of variations in code widths from the ideal code width. A DNL error of zero would imply that every code is exactly 1 LSb wide. 6.3.1 6.3.1.1 ACCURACY Integral Non-Linearity (INL) 111 110 101 Digital Input Code 100 011 010 001 Actual Transfer Function Ideal Transfer Function INL error for these devices is the maximum deviation between an actual code transition point and its corresponding ideal transition point after offset and gain errors have been removed. These endpoints are from 0x00 to 0x3F. Refer to Figure 6-5. Positive INL means higher resistance than ideal. Negative INL means lower resistance than ideal. Wide Code, > 1 LSb INL < 0 111 110 101 Digital Input Code 100 011 010 001 000 INL < 0 Digital Pot Output Ideal Transfer Function Actual Transfer Function 000 Narrow Code < 1 LSb Digital Pot Output FIGURE 6-6: 6.3.1.3 DNL Accuracy. Ratiometric Temperature Coefficient The ratiometric temperature coefficient quantifies the error in the ratio RAW/RWB due to temperature drift. This is typically the critical error when using a potentiometer device (MCP4021 and MCP4023) in a voltage divider configuration. 6.3.1.4 Absolute Temperature Coefficient FIGURE 6-5: INL Accuracy. The absolute temperature coefficient quantifies the error in the end-to-end resistance (nominal resistance RAB) due to temperature drift. This is typically the critical error when using a rheostat device (MCP4022 and MCP4024) in an adjustable resistor configuration. © 2006 Microchip Technology Inc. DS21945E-page 45 MCP4021/2/3/4 6.3.2 MONOTONIC OPERATION Monotonic operation means that the device’s resistance increases with every step change (from terminal A to terminal B or terminal B to terminal A). The wiper resistance is different at each tap location. When changing from one tap position to the next (either increasing or decreasing), the ΔRW is less than the ΔRS. When this change occurs, the device voltage and temperature are “the same” for the two tap positions. 0x3F 0x3E Digital Input Code 0x3D RS62 RS63 0x03 0x02 0x01 0x00 RS0 RS1 RS3 RW n=? (@ tap) R = RSn + RW(@ Tap n) BW n=0 Resistance (RBW) FIGURE 6-7: Resistance, RBW. DS21945E-page 46 © 2006 Microchip Technology Inc. MCP4021/2/3/4 7.0 DESIGN CONSIDERATIONS 7.2 Layout Considerations In the design of a system with the MCP402X devices, the following considerations should be taken into account: • The Power Supply • The Layout Inductively-coupled AC transients and digital switching noise can degrade the input and output signal integrity, potentially masking the MCP402X’s performance. Careful board layout will minimize these effects and increase the Signal-to-Noise Ratio (SNR). Bench testing has shown that a multi-layer board utilizing a low-inductance ground plane, isolated inputs, isolated outputs and proper decoupling are critical to achieving the performance that the silicon is capable of providing. Particularly harsh environments may require shielding of critical signals. If low noise is desired, breadboards and wire-wrapped boards are not recommended. 7.1 Power Supply Considerations The typical application will require a bypass capacitor in order to filter high-frequency noise, which can be induced onto the power supply's traces. The bypass capacitor helps to minimize the effect of these noise sources on signal integrity. Figure 7-1 illustrates an appropriate bypass strategy. In this example, the recommended bypass capacitor value is 0.1 µF. This capacitor should be placed as close (within 4 mm) to the device power pin (VDD) as possible. The power source supplying these devices should be as clean as possible. If the application circuit has separate digital and analog power supplies, VDD and VSS should reside on the analog plane. VDD 0.1 µF VDD 0.1 µF PIC® Microcontroller VSS MCP4021/2/3/4 A W U/D B CS VSS FIGURE 7-1: Connections. Typical Microcontroller © 2006 Microchip Technology Inc. DS21945E-page 47 MCP4021/2/3/4 8.0 APPLICATIONS EXAMPLES VDD R1 MCP4021 CS U/D B R2 A W VOUT Non-volatile digital potentiometers have a multitude of practical uses in modern electronic circuits. The most popular uses include precision calibration of set point thresholds, sensor trimming, LCD bias trimming, audio attenuation, adjustable power supplies, motor control overcurrent trip setting, adjustable gain amplifiers and offset trimming. The MCP4021/2/3/4 devices can be used to replace the common mechanical trim pot in applications where the operating and terminal voltages are within CMOS process limitations (VDD = 2.7V to 5.5V). 8.1 Set Point Threshold Trimming FIGURE 8-1: Using the Digital Potentiometer to Set a Precise Output Voltage. 8.1.1 TRIMMING A THRESHOLD FOR AN OPTICAL SENSOR Applications that need accurate detection of an input threshold event often need several sources of error eliminated. Use of comparators and operational amplifiers (op amps) with low offset and gain error can help achieve the desired accuracy, but in many applications, the input source variation is beyond the designer’s control. If the entire system can be calibrated after assembly in a controlled environment (like factory test), these sources of error are minimized, if not entirely eliminated. Figure 8-1 illustrates a common digital potentiometer configuration. This configuration is often referred to as a “windowed voltage divider”. Note that R1 and R2 are not necessary to create the voltage divider, but their presence is useful when the desired threshold has limited range. It is “windowed” because R1 and R2 can narrow the adjustable range of VTRIP to a value much less than VDD – VSS. If the output range is reduced, the magnitude of each output step is reduced. This effectively increases the trimming resolution for a fixed digital potentiometer resolution. This technique may allow a lower-cost digital potentiometer to be utilized (64 steps instead of 256 steps). The MCP4021’s and MCP4023’s low DNL performance is critical to meeting calibration accuracy in production without having to use a higher precision digital potentiometer. If the application has to calibrate the threshold of a diode, transistor or resistor, a variation range of 0.1V is common. Often, the desired resolution of 2 mV or better is adequate to accurately detect the presence of a precise signal. A “windowed” voltage divider, utilizing the MCP4021 or MCP4023, would be a potential solution as shown in Figure 8-2. VDD VDD Rsense R1 MCP4021 A CS U/D R2 W B 0.1 µF VTRIP VCC+ Comparator MCP6021 VCC– EQUATION 8-1: CALCULATING THE WIPER SETTING FROM THE DESIRED VTRIP R 2 + R WB = V DD ⎛ ----------------------------------⎞ ⎝ R 1 + R AB + R 2⎠ V TRIP FIGURE 8-2: Calibration. Set Point or Threshold R AB = R Nominal DR WB = R AB • ⎛ -----⎞ ⎝ 63⎠ V TRIP D = ⎛ ⎛ --------------⎞ • ( ( R 1 + R AB + R 2 ) – R 2 )⎞ • 63 ⎝ ⎝ V DD ⎠ ⎠ Where: D = Digital Potentiometer Wiper Setting (0-63) DS21945E-page 48 © 2006 Microchip Technology Inc. MCP4021/2/3/4 8.2 Operational Amplifier Applications VDD R1 MCP4021 A B R2 MCP4022 R3 VIN VW VDD + Op Amp – VOUT MCP6291 Figure 8-3, Figure 8-4 and Figure 8-5 illustrate typical amplifier circuits that could replace fixed resistors with the MCP4021/2/3/4 to achieve digitally-adjustable analog solutions. Figure 8-4 shows a circuit that allows a non-inverting amplifier to have its’ offset and gain to be independently trimmed. The MCP4021 is used along with resistors R1 and R2 to set the offset voltage. The sum of R1 + R2 resistance should be significantly greater (> 100 times) the resistance value of the MCP4021. This allows each increment or decrement in the MCP4021 to be a fine adjustment of the offset voltage. The input voltage of the op amp (VIN) should be centered at the op amps VW voltage. The gain is adjusted by the MCP4022. If the resistance value of the MCP4022 is small compared to the resistance value of R3, then this is a fine adjustment of the gain. If the resistance value of the MCP4022 is equal (or large) compared to the resistance value of R3, then this is a course adjustment of the gain. In gerneral, trim the course adjustments first and then trim the fine adjustments. MCP4021 A W VDD R1 MCP402X A B R2 – Op Amp + MCP6001 W VOUT B W A W FIGURE 8-4: Trimming Offset and Gain in a Non-Inverting Amplifier. R3 MCP4021 A W VDD R1 Pot2 – Op Amp VIN W Pot1 MCP4022 R2 + VOUT MCP6021 B R4 R3 VIN R4 A B 1 fc = ----------------------------- 2 π ⋅ R Eq ⋅ C Thevenin R = ( R 1 + R AB – R WB ) || ( R 2 + R WB ) + R w Equivalent Eq FIGURE 8-5: Programmable Filter. FIGURE 8-3: Trimming Offset and Gain in an Inverting Amplifier. © 2006 Microchip Technology Inc. DS21945E-page 49 MCP4021/2/3/4 8.3 Temperature Sensor Applications Thermistors are resistors with very predictable variation with temperature. Thermistors are a popular sensor choice when a low-cost, temperature-sensing solution is desired. Unfortunately, thermistors have non-linear characteristics that are undesirable, typically requiring trimming in an application to achieve greater accuracy. There are several common solutions to trim and linearize thermistors. Figure 8-6 and Figure 8-7 are simple methods for linearizing a 3-terminal NTC thermistor. Both are simple voltage dividers using a Positive Temperature Coefficient (PTC) resistor (R1) with a transfer function capable of compensating for the lineararity error in the Negative Temperature Coefficient (NTC) thermistor. The circuit, illustrated by Figure 8-6, utilizes a digital rheostat for trimming the offset error caused by the thermistor’s part-to-part variation. This solution puts the digital potentiometer’s RW into the voltage divider calculation. The MCP4021/2/3/4’s RAB temperature coefficient is 50 ppm (-20°C to +70°C). RW’s error is substantially greater than RAB’s error because RW varies with VDD, wiper setting and temperature. For the 50 kΩ devices, the error introduced by RW is, in most cases, insignificant as long as the wiper setting is > 6. For the 2 kΩ devices, the error introduced by RW is significant because it is a higher percentage of RWB. For these reasons, the circuit illustrated in Figure 8-6 is not the most optimum method for “exciting” and linearizing a thermistor. VDD VDD R1 NTC Thermistor MCP4021 VOUT R2 FIGURE 8-7: Thermistor Calibration using a Digital Potentiometer in a Potentiometer Configuration. 8.4 Wheatstone Bridge Trimming Another common configuration to “excite” a sensor (such as a strain gauge, pressure sensor or thermistor) is the wheatstone bridge configuration. The wheatstone bridge provides a differential output instead of a single-ended output. Figure 8-8 illustrates a wheatstone bridge utilizing one to three digital potentiometers. The digital potentiometers in this example are used to trim the offset and gain of the wheatstone bridge. VDD R1 NTC Thermistor VOUT R2 A W MCP4022 VOUT MCP4022 2.1 kΩ FIGURE 8-6: Thermistor Calibration using a Digital Potentiometer in a Rheostat Configuration. The circuit illustrated by Figure 8-7 utilizes a digital potentiometer for trimming the offset error. This solution removes RW from the trimming equation along with the error associated with RW. R2 is not required, but can be utilized to reduce the trimming “window” and reduce variation due to the digital potentiometer’s RAB part-to-part variability. MCP4022 50 kΩ MCP4022 50 kΩ FIGURE 8-8: Trimming. Wheatstone Bridge DS21945E-page 50 © 2006 Microchip Technology Inc. MCP4021/2/3/4 9.0 9.1 DEVELOPMENT SUPPORT Evaluation/Demonstration Boards Currently there are three boards that are available that can be used to evaluate the MCP4021/2/3/4 family of devices. 1. The MCP402X Digital Potentiomenter Evaluation Board kit (MCP402XEV) contains a simple demonstration board utilizing a PIC10F206, the MCP4021 and a blank PCB, which can be populated with any desired MCP4021/2/3/4 device in a SOT-23-5, SOT-23-6 or 150 mil SOIC 8-pin package. This board has two push buttons to control when the PIC® microcontroller generates MCP402X serial commands. The example firmware demonstrates the following commands: • Increment • Decrement • High-Voltage Increment and Enable WiperLock Technology • High-Voltage Decrement and Enable WiperLock Technology • High-Voltage Increment and Disable WiperLock Technology • High-Voltage Decrement and Disable WiperLock Technology The populated board (with the MCP4021) can be used to evaluate the other MCP402X devices by appropriately jumpering the PCB pads. 2. The SOT-23-5/6 Evaluation Board (VSUPEV2) can be used to evaluate the characteristics of the MCP4022, MCP4023 and MCP4024 devices. The 8-pin SOIC/MSOP/TSSOP/DIP Evaluation Board (SOIC8EV) can be used to evaluate the characteristics of the MCP4021 device in either the SOIC or MSOP package. The MCP4XXX Digital Potentiometer Daughter Board allows the system designer to quickly evaluate the operation of Microchip Technology's MCP42XXX and MCP402X Digital Potentiometers. The board supports two MCP42XXX devices and an MCP402X device, which can be replaced with an MCP401X device. The board also has a voltage doubler device (TC1240A), which can be used to show the WiperLock™ Technology feature of the MCP4021. These boards may be purchased directly from the Microchip web site at www.microchip.com. 3. 4. © 2006 Microchip Technology Inc. DS21945E-page 51 MCP4021/2/3/4 10.0 10.1 PACKAGING INFORMATION Package Marking Information 5-Lead SOT-23 (MCP4024) Example: XXNN DP25 Part Number MCP4024T-202E/OT MCP4024T-502E/OT MCP4024T-103E/OT MCP4024T-503E/OT Code DPNN DQNN DRNN DSNN Note: Applies to 5-Lead SOT-23 6-Lead SOT-23 (MCP4022 / MCP4023) Example: XXNN BA25 Part Number MCP402xT-202E/CH MCP402xT-502E/CH MCP402xT-103E/CH MCP402xT-503E/CH Code MCP4022 MCP4023 BANN BBNN BCNN BDNN BENN BFNN BGNN BHNN Note: Applies to 6-Lead SOT-23 Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21945E-page 52 © 2006 Microchip Technology Inc. MCP4021/2/3/4 Package Marking Information 8-Lead DFN (2x3) (MCP4021) Example: XXX YWW NNN AAA 530 256 Part Number MCP4021T-202E/MC MCP4021T-502E/MC MCP4021T-103E/MC MCP4021T-503E/MC Code AAA AAB AAC AAD Note: Applies to 8-Lead DFN 8-Lead MSOP (MCP4021) XXXXXX YWWNNN Example: 402122 530256 8-Lead SOIC (150 mil) (MCP4021) XXXXXXXX XXXXYYWW NNN Example: 402153E e3 SN^^ 0530 256 Part Numbers 8L-MSOP 8L-SOIC Code 22 52 13 53 MCP4021-202E/MS MCP4021-202E/SN MCP4021-502E/MS MCP4021-502E/SN MCP4021-103E/MS MCP4021-103E/SN MCP4021-503E/MS MCP4021-503E/SN Legend: XX...X Y YY WW NNN e3 * Note: Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2006 Microchip Technology Inc. DS21945E-page 53 MCP4021/2/3/4 5-Lead Plastic Small Outline Transistor (OT) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p B p1 D n 1 α c A A2 β Units Dimension Limits Number of Pins Pitch Outside lead pitch (basic) Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L f c B a b φ L A1 INCHES* MIN NOM 5 .038 .075 .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 .006 .017 5 5 .046 .043 .003 .110 .064 .116 .018 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0.90 0.90 0.00 2.60 1.50 2.80 0.35 MAX MIN MILLIMETERS NOM 5 0.95 1.90 1.18 1.10 0.08 2.80 1.63 2.95 0.45 0 0.09 0 0 0.15 0.43 5 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. EIAJ Equivalent: SC-74A Revised 09-12-05 Drawing No. C04-091 DS21945E-page 54 © 2006 Microchip Technology Inc. MCP4021/2/3/4 6-Lead Plastic Small Outline Transistor (CH) (SOT-23) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 B p1 D n 1 α c φ A A2 β L A1 Units Dimension Limits Number of Pins Pitch Outside lead pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n p p1 A A2 A1 E E1 D L φ c B α β .035 .035 .000 .102 .059 .110 .014 0 .004 .014 0 0 MIN INCHES* NOM 6 .038 BSC .075 BSC .046 .043 .003 .110 .064 .116 .018 5 .006 .017 5 5 .057 .051 .006 .118 .069 .122 .022 10 .008 .020 10 10 0.35 0 0 0.90 0.90 0.00 2.60 1.50 2.80 0.35 0 0.09 MAX MIN MILLIMETERS NOM 6 0.95 BSC 1.90 BSC 1.18 1.10 0.08 2.80 1.63 2.95 0.45 5 0.15 0.43 5 5 1.45 1.30 0.15 3.00 1.75 3.10 0.55 10 0.20 0.50 10 10 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .005" (0.127mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEITA (formerly EIAJ) equivalent: SC-74A Drawing No. C04-120 Revised 09-12-05 © 2006 Microchip Technology Inc. DS21945E-page 55 MCP4021/2/3/4 8-Lead Plastic Dual-Flat No-Lead Package (MC) 2x3x0.9 mm Body (DFN) – Saw Singulated Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D b N L e N K E E2 EXPOSED PAD NOTE 1 1 2 D2 2 1 NOTE 1 TOP VIEW BOTTOM VIEW A A3 A1 NOTE 2 MILLIMETERS NOM 8 0.50 BSC 0.90 0.02 0.20 REF 2.00 BSC 3.00 BSC — — 0.25 0.40 — Units Dimension Limits Number of Pins N Pitch e Overall Height A Standoff A1 Contact Thickness A3 Overall Length D Overall Width E Exposed Pad Length D2 Exposed Pad Width E2 Contact Width b Contact Length § L Contact-to-Exposed Pad § K MIN MAX 0.80 0.00 1.00 0.05 1.30 1.50 0.18 0.30 0.20 1.75 1.90 0.30 0.50 — Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package may have one or more exposed tie bars at ends. 3. § Significant Characteristic 4. Package is saw singulated 5. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–123, Sept. 8, 2006 DS21945E-page 56 © 2006 Microchip Technology Inc. MCP4021/2/3/4 8-Lead Plastic Micro Small Outline Package (MS) (MSOP) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D N E E1 NOTE 1 1 2 e b A2 c A ϕ A1 Units Dimension Limits N e A Thickness A2 A1 E Width E1 D L L1 ϕ c b L1 MILLIMETERS NOM 8 0.65 BSC — 0.85 — 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.95 REF — — — L MIN MAX Number of Pins Pitch Overall Height Molded Package Standoff Overall Width Molded Package Overall Length Foot Length Footprint Foot Angle Lead Thickness Lead Width — 0.75 0.00 1.10 0.95 0.15 0.40 0° 0.08 0.22 0.80 8° 0.23 0.40 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side. 3. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing No. C04–111, Sept. 8, 2006 © 2006 Microchip Technology Inc. DS21945E-page 57 MCP4021/2/3/4 8-Lead Plastic Small Outline (SN) – Narrow, 150 mil (SOIC) Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging E E1 p D 2 B n 1 45° h α c A A2 φ β L A1 MAX Number of Pins Pitch Overall Height A .053 .069 1.75 Molded Package Thickness A2 .052 .061 1.55 Standoff § A1 .004 .010 0.25 Overall Width E .228 .244 6.20 Molded Package Width E1 .146 .157 3.99 Overall Length D .189 .197 5.00 Chamfer Distance h .010 .020 0.51 Foot Length L .019 .030 0.76 φ Foot Angle 0 8 8 c Lead Thickness .008 .010 0.25 Lead Width B .013 .020 0.51 α Mold Draft Angle Top 0 15 15 β Mold Draft Angle Bottom 0 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-012 Drawing No. C04-057 Units Dimension Limits n p MIN INCHES* NOM 8 .050 .061 .056 .007 .237 .154 .193 .015 .025 4 .009 .017 12 12 MAX MIN MILLIMETERS NOM 8 1.27 1.35 1.55 1.32 1.42 0.10 0.18 5.79 6.02 3.71 3.91 4.80 4.90 0.25 0.38 0.48 0.62 0 4 0.20 0.23 0.33 0.42 0 12 0 12 DS21945E-page 58 © 2006 Microchip Technology Inc. MCP4021/2/3/4 APPENDIX A: REVISION HISTORY Revision E (December 2006) • Added device designators in conditions column to associate units (MHz) in Bandwidth -3 dB parameter in AC/DC Characteristics table • Added device designations in conditions column for R-INL and R-DNL specifications. • Added disclaimers to package outline drawings. Revision D (October 2006) • Changed the EEPROM write cycle time (TWC) from a maximum of 5 ms to a maximum of 10 ms (overvoltage and temperature) with a typical of 5 ms • For the 10 kΩ device, the rheostat differential non-linearity specification at 2.7V was changed from ±0.5 LSb to ±1.0 LSb • Figure 2-9 in Section 2.0 “Typical Performance Curves” was updated with the correct data. • Added Figure 2-48 for -3 db Bandwidth information. • Updated available Development Tools. • Added disclaimer to package outline drawings. Revision C (November 2005) • Enhanced Descriptions • Reordered Sections • Added 8-lead MSOP and DFN packages Revision B (April 2005) • Updated part numbers in Product Identifcation Section (PIS) • Added Appendix A: Revision History Revision A (April 2005) • Original Release of this Document © 2006 Microchip Technology Inc. DS21945E-page 59 MCP4021/2/3/4 NOTES: DS21945E-page 60 © 2006 Microchip Technology Inc. MCP4021/2/3/4 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device XXX X /XX Examples: a) b) c) d) e) f) g) h) i) j) k) l) m) n) o) p) q) r) s) t) a) b) c) d) a) b) c) d) a) b) c) d) MCP4021-103E/MS: MCP4021-103E/SN: MCP4021T-103E/MC: MCP4021T-103E/MS: MCP4021T-103E/SN: MCP4021-202E/MS: MCP4021-202E/SN: MCP4021T-202E/MC: MCP4021T-202E/MS: MCP4021T-202E/SN: MCP4021-502E/MS: MCP4021-502E/SN: MCP4021T-502E/MC: MCP4021T-502E/MS: MCP4021T-502E/SN: MCP4021-503E/MS: MCP4021-503E/SN: MCP4021T-503E/MC: MCP4021T-503E/MS: MCP4021T-503E/SN: MCP4022T-202E/CH MCP4022T-502E/CH MCP4022T-103E/CH MCP4022T-503E/CH MCP4023T-202E/CH MCP4023T-502E/CH MCP4023T-103E/CH MCP4023T-503E/CH MCP4024T-202E/OT MCP4024T-502E/OT MCP4024T-103E/OT MCP4024T-503E/OT 10 kΩ, 8-LD MSOP 10 kΩ, 8-LD SOIC T/R, 10 kΩ, 8-LD DFN T/R, 10 kΩ, 8-LD MSOP T/R, 10 kΩ, 8-LD SOIC 2.1 kΩ, 8-LD MSOP 2.1 kΩ, 8-LD SOIC T/R, 2.1 kΩ, 8-LD DFN T/R, 2.1 kΩ, 8-LD MSOP T/R, 2.1 kΩ, 8-LD SOIC 5 kΩ, 8-LD MSOP 5 kΩ, 8-LD SOIC T/R, 5 kΩ, 8-LD DFN T/R, 5 kΩ, 8-LD MSOP T/R, 5 kΩ, 8-LD SOIC 50 kΩ, 8-LD MSOP 50 kΩ, 8-LD SOIC T/R, 50 kΩ, 8-LD DFN T/R, 50 kΩ, 8-LD MSOP T/R, 50 kΩ, 8-LD SOIC 2.1 kΩ, 6-LD SOT-23 5 kΩ, 6-LD SOT-23 10 kΩ, 6-LD SOT-23 50 kΩ, 6-LD SOT-23 2.1 kΩ, 6-LD SOT-23 5 kΩ, 6-LD SOT-23 10 kΩ, 6-LD SOT-23 50 kΩ, 6-LD SOT-23 2.1 kΩ, 5-LD SOT-23 5 kΩ, 5-LD SOT-23 10 kΩ, 5-LD SOT-23 50 kΩ, 5-LD SOT-23 Resistance Temperature Package Version Range Device: MCP4021: MCP4021T: MCP4022: MCP4022T: MCP4023: MCP4023T: MCP4024: MCP4024T: Single Potentiometer with U/D Interface Single Potentiometer with U/D Interface (Tape and Reel) (SOIC, MSOP) Single Rheostat with U/D interface Single Rheostat with U/D interface (Tape and Reel) (SOT-23-6) Single Potentiometer to GND with U/D Interface Single Potentiometer to GND with U/D Interface (Tape and Reel) (SOT-23-6) Single Rheostat to GND with U/D Interface Single Rheostat to GND with U/D Interface (Tape and Reel)(SOT-23-5) Resistance Version: 202 = 2.1 kΩ 502 = 5 kΩ 103 = 10 kΩ 503 = 50 kΩ E CH MC MS SN OT = -40°C to +125°C = = = = = Plastic Small Outline Transistor, 6-lead Plastic Dual Flat No Lead (2x3x0.9 mm), 8-lead Plastic MSOP, 8-lead Plastic SOIC, (150 mil Body), 8-lead Plastic Small Outline Transistor, 5-lead Temperature Range: Package: © 2006 Microchip Technology Inc. DS21945E-page 61 MCP4021/2/3/4 NOTES: DS21945E-page 62 © 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. DS21945E-page 63 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Habour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Fuzhou Tel: 86-591-8750-3506 Fax: 86-591-8750-3521 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Shunde Tel: 86-757-2839-5507 Fax: 86-757-2839-5571 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7250 Fax: 86-29-8833-7256 ASIA/PACIFIC India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Gumi Tel: 82-54-473-4301 Fax: 82-54-473-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Penang Tel: 60-4-646-8870 Fax: 60-4-646-5086 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 12/08/06 DS21945E-page 64 © 2006 Microchip Technology Inc.
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