MRF24J40-IMM

MRF24J40 Data Sheet IEEE 802.15.4™ 2.4 GHz RF Transceiver © 2006 Microchip Technology Inc. Advance Information DS39776A Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, Mindi, MiWi, MPASM, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona, Gresham, Oregon and Mountain View, California. The Company’s quality system processes and procedures are for its PIC® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39776A-page ii Advance Information © 2006 Microchip Technology Inc. MRF24J40 IEEE 802.15.4™ 2.4 GHz RF Transceiver Devices Included: • MRF24J40 RF/Analog Features: • ISM Band 2.405-2.48 GHz Operation • -91 dBm Typical Sensitivity and +5 dBm Maximum Input Level • +0 dBm Typical Output Power and 38.75 dB TX Power Control Range • Differential RF Input/Output and Integrated TX/RX Switch • Integrated Low Phase Noise VCO, Frequency Synthesizer and PLL Loop Filter • Digital VCO and Filter Calibration • Integrated RSSI ADC and I/Q DACs • Integrated LDO • High Receiver and RSSI Dynamic Range Features: • Complete IEEE 802.15.4 Specification Compliant • Supports MiWi™, ZigBee™ and Proprietary Protocols • Simple, 4-Wire SPI Interface • Integrated 20 MHz and 32.768 kHz Oscillator Drive • 20 MHz Reference Clock Output: - Available to drive microcontroller oscillator • Supports Power-Saving mode • Low-Current Consumption, Typical 18 mA in RX mode and 22 mA in TX mode • Typical 2 μA Sleep mode • Small, 40-Pin Leadless QFN 6x6 mm2 Package MAC/Baseband Features: • Hardware CSMA-CA Mechanism, Automatic ACK Response and FCS Check • Independent Beacon, Transmit and GTS FIFO • Hardware Security Engine (AES-128) with CTR, CCM and CBC-MAC modes • Supports all CCA modes and RSS/LQI • Automatic Packet Retransmit Capability • Supports In-Line or Stand-Alone modes for both Encryption and Decryption Pin Diagram: LCAP VDD NC VDD GND VDD OSC1 OSC2 VDD VDD 40 39 38 37 36 35 34 33 32 31 VDD RFP RFN VDD VDD GND GPIO0 GPIO1 GPIO5 GPIO4 1 2 3 4 5 6 7 8 9 10 30 29 28 27 26 25 24 23 22 21 RXQP RXIP LPOSC1 LPOSC2 CLKOUT GND GND NC GND VDD 40-Pin QFN MRF24J40 11 12 13 14 15 16 17 18 19 20 GPIO2 GPIO3 RESET GND WAKE INT SDO SDI SCK CS Note: Backside center pad is GND. © 2006 Microchip Technology Inc. Advance Information DS39776A-page 1 MRF24J40 Table of Contents 1.0 Overview ...................................................................................................................................................................................... 3 2.0 External Connections ................................................................................................................................................................... 7 3.0 Memory Organization ................................................................................................................................................................... 9 4.0 Serial Peripheral Interface (SPI)................................................................................................................................................. 13 5.0 IEEE 802.15.4™-2003 ............................................................................................................................................................... 19 6.0 Initialization................................................................................................................................................................................. 21 7.0 Transmitting and Receiving Packets .......................................................................................................................................... 29 8.0 Interrupts .................................................................................................................................................................................... 35 9.0 General Purpose I/O .................................................................................................................................................................. 39 10.0 Electrical Characteristics ............................................................................................................................................................ 41 11.0 Packaging Information................................................................................................................................................................ 45 Appendix A: Layout and Part Selection................................................................................................................................................ 47 Appendix B: MRF24J40 Schematic and Bill of Materials ..................................................................................................................... 55 Index .................................................................................................................................................................................................... 59 The Microchip Web Site ....................................................................................................................................................................... 61 Customer Change Notification Service ................................................................................................................................................ 61 Customer Support ................................................................................................................................................................................ 61 Reader Response ................................................................................................................................................................................ 62 Product Identification System............................................................................................................................................................... 63 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39776A-page 2 Advance Information © 2006 Microchip Technology Inc. MRF24J40 1.0 OVERVIEW Features are summarized in Table 1-1 and the pinout for this device is listed in Table 1-2. The MRF24J40 consists of four major functional blocks: 1. An SPI interface that serves as a communication channel between the host controller and the MRF24J40. Control registers which are used to control and monitor the MRF24J40. The MAC (Medium Access Control) module that implements IEEE 802.3™ compliant MAC logic. The PHY (Physical Layer) driver that encodes and decodes the analog data. The MRF24J40 is an IEEE 802.15.4-2003 compliant transceiver supporting MiWi™, ZigBee™ and other proprietary protocols. The MRF24J40 integrates wireless RF, PHY layer baseband and MAC layer architectures that can be combined with a simple microprocessor to apply low data rate to a multitude of applications that include home automation, consumer electronics, PC peripherals, toys, industrial automation and more. The MRF24J40 device integrates a receiver, transmitter, VCO and PLL into a single integrated circuit. It uses advanced radio architecture to minimize external part count and power consumption. The MRF24J40 MAC/baseband provides hardware architecture for both IEEE 802.15.4 MAC and PHY layers. It mainly consists of TX/RX FIFOs, a CSMA-CA controller, superframe constructor, receive frame filter, security engine and digital signal processing module. The MRF24J40 is fabricated by advanced 0.18 μm CMOS process and is offered in a 40-pin QFN 6x6 mm2 package. 2. 3. 4. The device also contains other support blocks, such as the on-chip voltage regulator, security module and system control logic. TABLE 1-1: DEVICE FEATURES FOR THE MRF24J40 (40-PIN DEVICE) Features MRF24J40 Yes 20 MHz and 32.768 kHz 20 MHz Yes Typical 18 mA in RX and 22 mA in TX 2 μA Typical SPI (4-wire) 40-Pin Leadless QFN 6x6 mm2 IEEE 802.15.4™ Specification Compliant Integrated Oscillator Drive Reference Clock Output Power-Saving Mode Support Current Consumption Sleep Mode Serial Communications Packages © 2006 Microchip Technology Inc. Advance Information DS39776A-page 3 MRF24J40 FIGURE 1-1: MRF24J40 ARCHITECTURE BLOCK DIAGRAM User Application ZigBee™ Protocol or MiWi™ Protocol or Proprietary Protocol Physical Layer Driver Interrupt SPI Interface Reset TX FIFOs Long Control Short Control Registers Registers RX FIFO TX MAC Security Module RX MAC TX PHY RX PHY MRF24J40 DS39776A-page 4 Advance Information © 2006 Microchip Technology Inc. MRF24J40 1.1 Pin Descriptions MRF24J40 PIN DESCRIPTIONS Type Power AIO AIO Power Power Ground DIO DIO DIO DIO DIO DIO DI Ground DI DO DIO DIO DI DI Power Ground — Ground Ground DIO AI AI AO AO Power Power AI AI Power Ground Power — Power — Description RF power supply. Bypass with a capacitor as close to the pin as possible. Differential RF input/output (+). Differential RF input/output (-). RF power supply. Bypass with a capacitor as close to the pin as possible. Guard ring power supply. Bypass with a capacitor as close to the pin as possible. Guard ring ground. General purpose digital I/O, also used as external PA enable. General purpose digital I/O, also used as external TX/RX switch control. General purpose digital I/O. General purpose digital I/O. General purpose digital I/O, also used as external TX/RX switch control. General purpose digital I/O. Global hardware Reset pin active-low. Ground for digital circuit. External wake-up trigger. Interrupt pin to microcontroller. Serial interface data output from MRF24J40. Serial interface data input to MRF24J40. Serial interface clock. Serial interface enable. Digital circuit power supply. Bypass with a capacitor as close to the pin as possible. Ground for digital circuit. No Connection, do not connect anything to this pin. Ground for digital circuit. Ground for digital circuit. 20/10/5/2.5 MHz clock output. 32 kHz crystal input (-). 32 kHz crystal input (+). Analog RX I channel output (+). Analog RX Q channel output (+). Power supply for band gap reference circuit. Bypass with a capacitor as close to the pin as possible. Power supply for analog circuit. Bypass with a capacitor as close to the pin as possible. 20 MHz crystal input (-). 20 MHz crystal input (+). PLL power supply. Bypass with a capacitor as close to the pin as possible. Ground for PLL. Charge pump power supply. Bypass with a capacitor as close to the pin as possible. No Connection. VCO supply. Bypass with a capacitor as close to the pin as possible. PLL loop filter external capacitor. Connected to external 180 pF capacitor. TABLE 1-2: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 VDD RFP RFN VDD VDD GND Symbol GPIO0 GPIO1 GPIO5 GPIO4 GPIO2 GPIO3 RESET GND WAKE INT SDO SDI SCK CS VDD GND NC GND GND CLKOUT LPOSC2 LPOSC1 RXIP RXQP VDD VDD OSC2 OSC1 VDD GND VDD NC VDD LCAP Legend: A = Analog, D = Digital, I = Input, O = Output © 2006 Microchip Technology Inc. Advance Information DS39776A-page 5 MRF24J40 NOTES: DS39776A-page 6 Advance Information © 2006 Microchip Technology Inc. MRF24J40 2.0 2.1 EXTERNAL CONNECTIONS Oscillator 2.2 Oscillator Start-up The MRF24J40 is designed to operate at 20 MHz with a crystal connected to the OSC1 and OSC2 pins. A typical oscillator circuit is shown in Figure 2-1. FIGURE 2-1: CRYSTAL OSCILLATOR OPERATION OSC1 The MRF24J40 PHY has an internal PLL that must lock before the device is capable of transmitting or receiving packets. After a full Power-on Reset, the device requires 2 ms to lock. During this delay, all registers and buffer memory may still be read and written to through the SPI bus. However, software should not attempt to transmit any packets (set the TXRTS (TXNMTRIG)), or access any MAC or PHY registers during this period. 2.3 To Internal Logic CLKOUT Pin C1 XTAL RS(1) C2 Note 1: OSC2 MRF24J40 A series resistor (RS) may be required for AT strip cut crystals. The clock out pin is provided to the system designer for use as the host controller clock or as a clock source for other devices in the system. The CLKOUT has an internal prescaler which can divide the output by 1, 2, 4 or 8. The CLKOUT function is enabled via the CLKCTRL register (Register 2-1) and the prescaler is selected via the RFCTRL7 register (Register 2-2). REGISTER 2-1: R/W-0 r bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 bit 5 CLKCTRL: DIVIDED SLEEP CLOCK (50 kHz) SELECTION REGISTER U-0 — R/W-0 CLKOEN R/W-0 R/W-0 R/W-0 SCLKDIV bit 0 R/W-0 R/W-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Reserved: Maintain as ‘0’ Unimplemented: Read as ‘0’ CLKOEN: 20 MHz Clock Output Enable bit 1 = Disable 0 = Enable SCLKDIV4:SCLKDIV0: Divided SLPCLK Selection bits Divided by 2n. bit 4-0 © 2006 Microchip Technology Inc. Advance Information DS39776A-page 7 MRF24J40 REGISTER 2-2: R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RFCTRL7: RF CONTROL REGISTER 7 R/W-0 U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 bit 0 SLPCLK CLKDIV SLPCLK7:SLPCLK6: Sleep Clock Selection bits 00 = None 01 = External crystal 10 = Internal ring oscillator 11 = Reserved Unimplemented: Read as ‘0’ CLKDIV1:CLKDIV0: MRF24J40 Clock Output Frequency bits 00 = 2.5 MHz 01 = 5 MHz 10 = 10 MHz 11 = 20 MHz bit 5-2 bit 1-0 To create a clean clock signal, the CLKOUT pin is held low for a period when power is first applied. After the Power-on Reset ends, the Oscillator Start-up Timer (OST) will begin counting. When the OST expires, the CLKOUT pin will begin outputting its default frequency of 2.5 MHz (main clock divided by 8). 2.4 RF Output RFP and RFN are the differential RF input/output pins. These pins are connected to the antenna of the system, as seen in the example circuit diagram in Figure A-1. L5 is an RF choke. This inductor filters out non 2.4 GHz voltages. L3, L4, C37 and C43 act as a balun. The balun converts a differential unbalanced input and converts it to a balanced singled-ended output and visa versa. L1, C23 and C38 form a pi-type matching circuit to match the impedance of the balun to the impedance of the antenna. This circuit is not required if the impedance of the balun matches the antenna impedance. Refer to Appendix A.1 “Layout Considerations and RF Measurements” for more details about board layout and part selection concerning the RF output pins. DS39776A-page 8 Advance Information © 2006 Microchip Technology Inc. MRF24J40 3.0 MEMORY ORGANIZATION All memory in the MRF24J40 is implemented as static RAM. There are five types of memory in the MRF24J40: • • • • • Short Address Control Registers Long Address Control Registers Transmit Buffers Receive Buffers Security Buffer The security buffer provides an engine for the MRF24J40 MAC, which is compatible with the IEEE 802.15.4 LR-WPAN (ZigBee). The security buffer contains the following features: • Transmit encryption and receive decryption. • Seven-mode security suite. • 64 x 8-bit security RAM for security suite storing; one receive key and three transmit keys for TX FIFOs. Beacon FIFO and GTS2 FIFO share the same key space since they will not conflict with each other. Normal FIFO and GTS1 FIFO both have their own transmit key. • Security of APL and NWK layers can be achieved using the same engine. The upper layer security function is compliant to the ZigBee V1.0 and ZigBee 2006 specifications. The SPI interface used to write and read these registers is described in Section 4.0 “Serial Peripheral Interface (SPI)”. Figure 3-1 shows the data memory organization for the MRF24J40. The control registers, both long and short, are used for configuration, control, and status retrieval of the MRF24J40. The control registers are directly read and written to by the SPI interface. The transmit and receive buffers contain transmit and receive memory used by the controller to transmit and receive data. FIGURE 3-1: MRF24J40 MEMORY SPACE Short Address Space 00h Short Address Control Registers 3Fh Transmit Buffers 000h TXN FIFO 07Fh 080h TXB FIFO 0FFh 100h GTS1 FIFO 17Fh 180h GTS2 FIFO 1FFh 200h Control Registers 27Fh 280h Security 2BEh 2BFh Unimplemented 2FFh 300h Receive FIFO 38Fh RX FIFO Security Buffer Long Address Control Registers Long Address Space © 2006 Microchip Technology Inc. Advance Information DS39776A-page 9 MRF24J40 3.1 Control Registers The control registers provide the main interface between the host controller and the on-chip RF controller logic. Writing to these registers controls the operation of the interface, while reading the registers allows the host controller to monitor operations. The control register memory is partitioned into the short address control register section and the long address control register section. All reserved registers may be read but their contents must not be changed. When reading and writing to registers which contain reserved bits, any rules stated in the register definition should be observed. FIGURE 3-2: 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh MRF24J40 SHORT ADDRESS CONTROL REGISTER MAPPING RXMCR PANIDL PANIDH SADRL SADRH EADR0 EADR1 EADR2 EADR3 EADR4 EADR5 EADR6 EADR7 RXFLUSH — — 10h 11h 12h 13h 14h 15h 16h 17h 18h 19h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh — — — — — — — — — — — TXNMTRIG — — — — 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh — — — — TXSR — — — — — — — — — — — 30h 31h 32h 33h 34h 35h 36h 37h 38h 39h 3Ah 3Bh 3Ch 3Dh 3Eh 3Fh — ISRSTS INTMSK GPIO TRISGPIO — RFCTL — — — BBREG2 — — — BBREG6 RSSITHCCA FIGURE 3-3: 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh RFCTRL0 — RFCTRL2 RFCTRL3 — — RFCTRL6 RFCTRL7 RFCTRL8 — — — — — — — MRF24J40 LONG ADDRESS CONTROL REGISTER MAPPING 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh — CLKINTCR — — — — — — — — — — — — — — 220h 221h 222h 223h 224h 225h 226h 227h 228h 229h 22Ah 22Bh 22Ch 22Dh 22Eh 22Fh CLKCTRL — — — — — — — — — — — — — — — 230h 231h 232h 233h 234h 235h 236h 237h 238h 239h 23Ah 23Bh 23Ch 23Dh 23Eh 23Fh — — — — — — — — — — — — — — — — 240h 241h 242h 243h 244h 245h 246h 247h 248h 249h 24Ah 24Bh 24Ch — — — — — — — — — — — — — DS39776A-page 10 Advance Information © 2006 Microchip Technology Inc. MRF24J40 3.2 MRF24J40 Address Summary REGISTER FILE SHORT ADDRESS SUMMARY Bit 7 TXCRCEN Bit 6 BBLPBK Bit 5 ACKEN Bit 4 MACLPBK Bit 3 PANCOORD Bit 2 COORD Bit 1 RXCRCEN Bit 0 PROMI Value on POR 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DATAONLY ACKREQ r GTS2TXIF BCNONLY SECEN r GTS1TXIF RXFLUSH -000 0000 TXRTS r TXIF TXMSK GPIO0 ---0 0000 0000 0000 0000 0000 1111 1111 --00 0000 Details on page: 21 26 26 27 27 26 26 26 26 26 26 26 26 34 30 31 36 37 39 40 24 25 25 23 TABLE 3-1: File Name RXMCR PANIDL PANIDH SADRL SADRH EADR0 EADR1 EADR2 EADR3 EADR4 EADR5 EADR6 EADR7 RXFLUSH TXNMTRIG TXSR ISRSTS INTMSK GPIO TRISGPIO RFCTL BBREG2 BBREG6 RSSITHCCA Legend: — — MAC PAN Low Byte (PANL) MAC PAN High Byte (PANH) MAC Short Address Low Byte (SADDRL) MAC Short Address High Byte (SADDRH) LSB of EUI (EADR0) Byte 2 of EUI (EADR1) Byte 3 of EUI (EADR2) Byte 4 of EUI (EADR3) Byte 5 of EUI (EADR4) Byte 6 of EUI (EADR5) Byte 7 of EUI (EADR6) MSB of EUI (EADR7) r — r — CCAFAIL HSYMTMRIF HSYMTMRMSK GPIO5 TRISGP5 — RXWRTBLK PENDACK r SECIF SECMSK GPIO4 TRISGP4 r CMDONLY INDIRECT r RXIF RXMSK GPIO3 TRISGP3 r TXRETRY SLPIF SLPMSK — — r WAKEIF WAKEMSK — — — GTS2TXMSK GTS1TXMSK GPIO2 TRISGP2 RFRST GPIO1 TRISGP1 r — r r TRISGP0 --00 0000 r — 0--0 0000 0000 00-- CCAMODE RSSIREQ RXRSSI r CCATHRES r r RSSIRDY 0000 0001 0000 0000 RSSITHRES - = unimplemented, r = reserved. Shaded cells are unimplemented, read as ‘0’. TABLE 3-2: File Name RFCTRL0 RFCTRL2 RFCTRL3 RFCTRL6 RFCTRL7 RFCTRL8 CLKINTCR CLKCTRL Legend: REGISTER FILE LONG ADDRESS SUMMARY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 — r r Bit 2 — — — r — RF_VCO — BATMONEN — — — — — — — — INTEDGE Bit 1 — — — — Bit 0 — — — — CLKDIV SLPCLKOUT SLPCLKEN Value on POR 0000 ---0000 0--0000 0--0-00 0--00-- --00 ---0 ---0 ---- --00 0-00 0000 Details on page: 24 22 22 23 8 23 38 7 CHANNEL RFPLL r r TXPOWER TXFIL — r — — — CLKOEN SLPCLK — — r — — — SCLKDIV - = unimplemented, r = reserved. Shaded cells are unimplemented, read as ‘0’. © 2006 Microchip Technology Inc. Advance Information DS39776A-page 11 MRF24J40 NOTES: DS39776A-page 12 Advance Information © 2006 Microchip Technology Inc. MRF24J40 4.0 4.1 SERIAL PERIPHERAL INTERFACE (SPI) Overview The MRF24J40 is designed to interface directly with the Serial Peripheral Interface (SPI) port available on many microcontrollers. The implementation used on this device supports SPI mode 0,0 only. In addition, the SPI port requires that SCK be Idle in a low state; selectable clock polarity is not supported. Commands and data are sent to the device via the SDI pin, with data being clocked in on the rising edge of SCK. Data is driven out by the MRF24J40 on the SDO line, on the falling edge of SCK. The CS pin must be held low while any operation is performed and returned high when finished. The MRF24J40 accesses the short and long RAM banks in a slightly different manner. The following sections describe the required waveforms in order to read and write from both short and long RAM addresses. FIGURE 4-1: SPI INPUT TIMING CS SCK SDI MSb In LSb In SDO High-Impedance State FIGURE 4-2: CS SPI OUTPUT TIMING SCK SDO MSb Out LSb Out SDI Don’t Care © 2006 Microchip Technology Inc. Advance Information DS39776A-page 13 MRF24J40 4.2 4.2.1 Short Address Register Interface READING SHORT ADDRESS REGISTERS The short address space is accessed by sending a ‘0’ as the first bit of the SPI transfer. The following 6 bits are the address of the target register. The final bit of the first byte is a ‘0‘ to indicate that the command is a read. On the next clock edge of SCK, the Most Significant bit of the register will shift out, followed by the rest of the bits. FIGURE 4-3: CS SHORT ADDRESS READ SCK SDI SDO 0 A5 A4 A3 A2 A1 A0 0 D7 D6 D5 D4 X D3 D2 D1 D0 EXAMPLE 4-1: SHORT ADDRESS READ EXAMPLE BYTE GetShortRAMAddress(BYTE address) { BYTE toReturn; CSn = 0; SPIPut((address