PIC18LF47J13

PIC18F47J13 Family Data Sheet 28/44-Pin, High-Performance Microcontrollers with nanoWatt XLP Technology  2010 Microchip Technology Inc. Preliminary DS39974A Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-304-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39974A-page 2 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY PIC18F47J13 Family 28/44-Pin, High-Performance Microcontrollers with nanoWatt XLP Technology Power Management Features with nanoWatt XLP for Extreme Low Power: • Deep Sleep mode: CPU Off, Peripherals Off, SRAM Off, Currents Down to 9 nA and 700 nA with RTCC: - Able to wake-up on external triggers, programmable WDT or RTCC alarm - Ultra Low-Power Wake-up (ULPWU) • Sleep mode: CPU Off, Peripherals Off, SRAM On, Fast Wake-up, Currents Down to 0.2 A, 2V Typical • Idle: CPU Off, SRAM On, Currents Down to 1.7 A Typical • Run: CPU On, SRAM On, Currents Down to 5.8 A Typical • Timer1 Oscillator w/RTCC: 0.7 A, 32 kHz Typical • Watchdog Timer: 0.33 A, 2V Typical Peripheral Highlights (cont.): • Seven Capture/Compare/PWM (CCP) modules • Two Master Synchronous Serial Port (MSSP) modules featuring: - 3-wire SPI (all 4 modes) - SPI Direct Memory Access (DMA) channel w/1024 byte count - I2C™ Master and Slave modes • 8-Bit Parallel Master Port/Enhanced Parallel Slave Port • Three Analog Comparators with Input Multiplexing • 12-Bit Analog-to-Digital (A/D) Converter module: - Up to 13 input channels - Auto-acquisition capability - 10-bit mode for 100 ksps conversion speed - Conversion available during Sleep • High/Low-Voltage Detect module • Charge Time Measurement Unit (CTMU): - Provides a precise resolution time measurement for both flow measurement and simple temperature sensing - Supports capacitive touch sensing for touch screens and capacitive switches • Two Enhanced USART modules: - Supports RS-485, RS-232 and LIN/J2602 - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) Flexible Oscillator Structure: • • • • • • • • Two External Clock modes, Up to 48 MHz (12 MIPS) Integrated Crystal/Resonator Driver Low-Power 31 kHz Internal RC Oscillator Tunable Internal Oscillator (31 kHz to 8 MHz, ±0.15% Typical, ±1% Max.) Precision 48 MHz PLL or 4x PLL Options Low-Power Secondary Oscillator using Timer1 @ 32 kHz Fail-Safe Clock Monitor (FSCM): - Allows for safe shutdown if any clock stops Programmable Reference Clock Output Generator Special Microcontroller Features: • • • • • • • • • • • • 5.5V Tolerant Inputs (digital only pins) Low-Power, High-Speed CMOS Flash Technology C Compiler Optimized Architecture for Re-Entrant Code Priority Levels for Interrupts Self-Programmable under Software Control 8 x 8 Single-Cycle Hardware Multiplier Extended Watchdog Timer (WDT): - Programmable period from 4 ms to 131s Single-Supply In-Circuit Serial Programming™ (ICSP™) via Two Pins In-Circuit Debug (ICD) with 3 Breakpoints via Two Pins Operating Voltage Range of 2.0V to 3.6V On-Chip 2.5V Regulator Flash Program Memory of 10,000 Erase/Write Cycles Minimum and 20-Year Data Retention Peripheral Highlights: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • High-Current Sink/Source 25 mA/25mA (PORTB and PORTC) • Four Programmable External Interrupts • Four Input Change Interrupts • Three Enhanced Capture/Compare/PWM (ECCP) modules: - One, two or four PWM outputs - Selectable polarity - Programmable dead time - Auto-shutdown and auto-restart - Pulse steering control  2010 Microchip Technology Inc. Preliminary DS39974A-page 3 PIC18F47J13 FAMILY Deep Sleep ECCP/CCP PMP/PSP EUSART Program Memory (bytes) 12-Bit A/D (ch) MSSP SPI w/DMA I2C™ Comparators Remappable Pins Timers 8/16-Bit SRAM (bytes) CTMU Y Y Y Y Y Y Y Y PIC18F Device PIC18F26J13 PIC18F27J13 PIC18F46J13 PIC18F47J13 PIC18LF26J13 PIC18LF27J13 PIC18LF46J13 PIC18LF47J13 RTCC Y Y Y Y Y Y Y Y Pins 28 28 44 44 28 28 44 44 64K 128K 64K 128K 64K 128K 64K 128K 3760 3760 3760 3760 3760 3760 3760 3760 19 19 25 25 19 19 25 25 4/4 4/4 4/4 4/4 4/4 4/4 4/4 4/4 3/7 3/7 3/7 3/7 3/7 3/7 3/7 3/7 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y 10 10 13 13 10 10 13 13 3 3 3 3 3 3 3 3 Y Y Y Y N N N N N N Y Y N N Y Y DS39974A-page 4 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Diagrams 44-Pin TQFP RC6/CCP9/PMA5/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1/RP15 RD3/PMD3/RP20 RD2/PMD2/RP19 RD1/PMD1/SDA2 RD0/PMD0/SCL2 RC3/SCK1/SCL1/RP14 RC2/AN11/C2IND/CTPLS/RP13 RC1/CCP8/T1OSI/RP12 NC = Pins are up to 5.5V tolerant 44 43 42 41 40 39 38 37 36 35 34 Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”.  2010 Microchip Technology Inc. Preliminary NC NC RB4/CCP4/PMA1/KBI0/RP7 RB5/CCP5/PMA0/KBI1/RP8 RB6/CCP6/KBI2/PGC/RP9 RB7/CCP7/KBI3/PGD/RP10 MCLR RA0/AN0/C1INA/ULPWU/PMA6/RP0 RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/CCP10/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 VSS1 VDD1 RB0/AN12/C3IND/INT0/RP3 RB1/AN10/C3INC/PMBE/RTCC/RP4 RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5 RB3/AN9/C3INA/CTED2/PMA2/RP6 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XJ13 33 32 31 30 29 28 27 26 25 24 23 NC RC0/T1OSO/T1CKI/RP11 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS2 VDD2 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/C1INC/SS1/HLVDIN/RP2 VDDCORE/VCAP DS39974A-page 5 PIC18F47J13 FAMILY Pin Diagrams (Continued) 44-Pin QFN RC6/CCP9/PMA5/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1/RP15 RD3/PMD3/RP20 RD2/PMD2/RP1 RD1/PMD1/SDA2 RD0/PMD0/SCL2 RC3/SCK1/SCL1/RP14 RC2/AN11/C2IND/CTPLS/RP13 RC1/CCP8/T1OSI/RP12 RC0/T1OSO/T1CKI/RP11 = Pins are up to 5.5V tolerant 44 43 42 41 40 39 38 37 36 35 34 Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”. For the QFN package, it is recommended that the bottom pad be connected to VSS. Note: DS39974A-page 6 Preliminary RB3/AN9/C3INA/CTED2/PMA2/RP6 NC RB4/CCP4/PMA1/KBI0/RP7 RB5/CCP5/PMA0/KBI1/RP8 RB6/CCP6/KBI2/PGC/RP9 RB7/CCP7/KBI3/PGD/RP10 MCLR RA0/AN0/C1INA/ULPWU/PMA6/RP0 RA1/AN1/C2INA/VBG/CTDIN/PMA7/RP1 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ 12 13 14 15 16 17 18 19 20 21 22 RC7/CCP10/PMA4/RX1/DT1/RP18 RD4/PMD4/RP21 RD5/PMD5/RP22 RD6/PMD6/RP23 RD7/PMD7/RP24 VSS1 AVDD1 VDD1 RB0/AN12/C3IND/INT0/RP3 RB1/AN10/C3INC/PMBE/RTCC/RP4 RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5 1 2 3 4 5 6 7 8 9 10 11 PIC18F4XJ13 33 32 31 30 29 28 27 26 25 24 23 OSC2/CLKO/RA6 OSC1/CLKI/RA7 VSS2 AVSS1 VDD2 AVDD2 RE2/AN7/PMCS RE1/AN6/PMWR RE0/AN5/PMRD RA5/AN4/C1INC/SS1/HLVDIN/RP2 VDDCORE/VCAP  2010 Microchip Technology Inc. PIC18F47J13 FAMILY Pin Diagrams (Continued) 28-Pin SPDIP/SOIC/SSOP MCLR RA0/AN0/C1INA/ULPWU/RP0 RA1/AN1/C2INA/VBG/CTDIN/RP1 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ VDDCORE/VCAP RA5/AN4/C1INC/SS1/HLVDIN/RP2 VSS1 OSC1/CLKI/RA7 OSC2/CLKO/RA6 RC0/T1OSO/T1CKI/RP11 RC1/CCP8/T1OSI/RP12 RC2/AN11/C2IND/CTPLS/RP13 RC3/SCK1/SCL1/RP14 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 = Pins are up to 5.5V tolerant RB7/CCP7/KBI3/PGD/RP10 RB6/CCP6/KBI2/PGC/RP9 RB5/CCP5/KBI1/SDA2/RP8 RB4/CCP4/KBI0/SCL2/RP7 RB3/AN9/C3INA/CTED2/RP6 RB2/AN8/C2INC/CTED1/REFO/RP5 RB1/AN10/C3INC/RTCC/RP4 RB0/AN12/C3IND/INT0/RP3 VDD VSS2 RC7/CCP10/RX1/DT1/RP18 RC6/CCP9/TX1/CK1/RP17 RC5/SDO1/RP16 RC4/SDI1/SDA1/RP15 RA2/AN2/C1INB/C1IND/C3INB/VREF-/CVREF RA3/AN3/C1INB/VREF+ VDDCORE/VCAP RA5/AN4/C1INC/SS1/HLVDIN/RP2 VSS1 OSC1/CLKI/RA7 OSC2/CLKO/RA6 1 2 3 4 5 6 7 RA1/AN1/C2INA/VBG/CTDIN/RP1 RA0/AN0/C1INA/ULPWU/RP0 MCLR RB7/CCP7/KBI3/PGD/RP10 RB6/CCP6/KBI2/PGC/RP9 RB5/CCP5/KBI1/SDA2/RP8 RB4/CCP4/KBI0/SCL2/RP7 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RB3/AN9/C3INA/CTED2/RP6 RB2/AN8/C2INC/CTED1/REFO/RP5 RB1/AN10/C3INC/RTCC/RP4 RB0/AN12/C3IND/INT0/RP3 VDD VSS2 RC7/CCP10/RX1/DT1/RP18 28-Pin QFN PIC18F2XJ13 8 9 10 11 12 13 14 RC0/T1OSO/T1CKI/RP11 RC1/CCP8/T1OSI/RP12 RC2/AN11/C2IND/CTPLS/RP13 RC3/SCK1/SCL1/RP14 RC4/SDI1/SDA1/RP15 RC5/SDO1/RP16 RC6/CCP9/TX1/CK1/RP17 Legend: RPn represents remappable pins.Some input and output functions are routed through the Peripheral Pin Select (PPS) module and can be dynamically assigned to any of the RPn pins. For a list of the input and output functions, see Table 10-13 and Table 10-14, respectively. For details on configuring the PPS module, see Section 10.7 “Peripheral Pin Select (PPS)”. For the QFN package, it is recommended that the bottom pad be connected to VSS. Note:  2010 Microchip Technology Inc. Preliminary PIC18F2XJ13 DS39974A-page 7 PIC18F47J13 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 31 3.0 Oscillator Configurations ............................................................................................................................................................ 35 4.0 Low-Power Modes...................................................................................................................................................................... 47 5.0 Reset .......................................................................................................................................................................................... 65 6.0 Memory Organization ................................................................................................................................................................. 81 7.0 Flash Program Memory ............................................................................................................................................................ 107 8.0 8 x 8 Hardware Multiplier.......................................................................................................................................................... 117 9.0 Interrupts .................................................................................................................................................................................. 119 10.0 I/O Ports ................................................................................................................................................................................... 139 11.0 Parallel Master Port (PMP)....................................................................................................................................................... 179 12.0 Timer0 Module ......................................................................................................................................................................... 205 13.0 Timer1 Module ......................................................................................................................................................................... 209 14.0 Timer2 Module ......................................................................................................................................................................... 219 15.0 Timer3/5 Module ...................................................................................................................................................................... 221 16.0 Timer4/6/8 Module ................................................................................................................................................................... 233 17.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 237 18.0 Capture/Compare/PWM (CCP) Modules ................................................................................................................................. 257 19.0 Enhanced Capture/Compare/PWM (ECCP) Module................................................................................................................ 269 20.0 Master Synchronous Serial Port (MSSP) Module .................................................................................................................... 291 21.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) ............................................................... 345 22.0 10/12-bit Analog-to-Digital Converter (A/D) Module ................................................................................................................. 367 23.0 Comparator Module.................................................................................................................................................................. 379 24.0 Comparator Voltage Reference Module ................................................................................................................................... 387 25.0 High/Low Voltage Detect (HLVD) ............................................................................................................................................. 391 26.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 397 27.0 Special Features of the CPU .................................................................................................................................................... 415 28.0 Instruction Set Summary .......................................................................................................................................................... 433 29.0 Development Support............................................................................................................................................................... 483 30.0 Electrical Characteristics .......................................................................................................................................................... 487 31.0 Packaging Information.............................................................................................................................................................. 529 Appendix A: Revision History............................................................................................................................................................. 541 Appendix B: Migration From PIC18F46J11 to PIC18F47J13............................................................................................................. 541 The Microchip Web Site ..................................................................................................................................................................... 555 Customer Change Notification Service .............................................................................................................................................. 555 Customer Support .............................................................................................................................................................................. 555 Reader Response .............................................................................................................................................................................. 556 Product Identification System............................................................................................................................................................. 557 DS39974A-page 8 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. Preliminary DS39974A-page 9 PIC18F47J13 FAMILY NOTES: DS39974A-page 10 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 This document contains device-specific information for the following devices: • PIC18F26J13 • PIC18F27J13 • PIC18F46J13 • PIC18F47J13 • PIC18LF26J13 • PIC18LF27J13 • PIC18LF46J13 • PIC18LF47J13 OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F47J13 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. • Two External Clock modes, offering the option of a divide-by-4 clock output. • An internal oscillator block, which provides an 8 MHz clock and an INTRC source (approximately 31 kHz, stable over temperature and VDD), as well as a range of six user selectable clock frequencies, between 125 kHz to 4 MHz, for a total of eight clock frequencies. This option frees an oscillator pin for use as an additional general purpose I/O. • A Phase Lock Loop (PLL) frequency multiplier available to the high-speed crystal, and external and internal oscillators, providing a clock speed up to 48 MHz. The internal oscillator block provides a stable reference source that gives the PIC18F47J13 family additional features for robust operation: • Fail-Safe Clock Monitor: This option constantly monitors the main clock source against a reference signal provided by the internal oscillator. If a clock failure occurs, the controller is switched to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. • Two-Speed Start-up: This option allows the internal oscillator to serve as the clock source from Power-on Reset (POR), or wake-up from Sleep mode, until the primary clock source is available. 1.1 1.1.1 Core Features nanoWatt XLP TECHNOLOGY All of the devices in the PIC18F47J13 family incorporate a range of features that can significantly reduce power consumption during operation. Key features are: • Alternate Run Modes: By clocking the controller from the Timer1 source or the internal RC oscillator, power consumption during code execution can be reduced by as much as 90%. • Multiple Idle Modes: The controller can also run with its CPU core disabled but the peripherals still active. In these states, power consumption can be reduced even further, to as little as 4% of normal operational requirements. • On-the-Fly Mode Switching: The power-managed modes are invoked by user code during operation, allowing the users to incorporate power-saving ideas into their application’s software design. • Deep Sleep: The 2.5V internal core voltage regulator on F parts can be shutdown to cut power consumption to as low as 15 nA (typical). Certain features can remain operating during Deep Sleep, such as the Real-Time Clock Calendar. • Ultra Low Power Wake-Up: Waking from Sleep or Deep Sleep modes after a period of time can be done without an oscillator/clock source, saving power for applications requiring periodic activity.  2010 Microchip Technology Inc. Preliminary DS39974A-page 11 PIC18F47J13 FAMILY 1.1.3 EXPANDED MEMORY The PIC18F47J13 family provides ample room for application code, from 64 Kbytes to 128 Kbytes of code space. The Flash cells for program memory are rated to last in excess of 10000 erase/write cycles. Data retention without refresh is conservatively estimated to be greater than 20 years. The Flash program memory is readable and writable during normal operation. The PIC18F47J13 family also provides plenty of room for dynamic application data with up to 3.8 Kbytes of data RAM. • 10/12-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and thus, reducing code overhead. • Extended Watchdog Timer (WDT): This enhanced version incorporates a 16-bit prescaler, allowing an extended time-out range that is stable across operating voltage and temperature. See Section 30.0 “Electrical Characteristics” for time-out periods. 1.1.4 EXTENDED INSTRUCTION SET 1.3 The PIC18F47J13 family implements the optional extension to the PIC18 instruction set, adding eight new instructions and an Indexed Addressing mode. Enabled as a device configuration option, the extension has been specifically designed to optimize re-entrant application code originally developed in high-level languages, such as C. Details on Individual Family Devices Devices in the PIC18F47J13 family are available in 28-pin and 44-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in two ways: • Flash program memory (two sizes: 64 Kbytes for the PIC18FX6J13 and 128 Kbytes for PIC18FX7J13) • I/O ports (three bidirectional ports on 28-pin devices, five bidirectional ports on 44-pin devices) All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. The pinouts for the PIC18F2XJ13 devices are listed in Table 1-3. The pinouts for the PIC18F4XJ13 devices are shown in Table 1-4. The PIC18F47J13 family of devices provides an on-chip voltage regulator to supply the correct voltage levels to the core. Parts designated with an “F” part number (such as PIC18F47J13) have the voltage regulator enabled. These parts can run from 2.15V-3.6V on VDD, but should have the VDDCORE pin connected to VSS through a low-ESR capacitor. Parts designated with an “LF” part number (such as PIC18LF47J13) do not enable the voltage regulator nor support Deep Sleep mode. For “LF” parts, an external supply of 2.0V-2.7V has to be supplied to the VDDCORE pin while 2.0V-3.6V can be supplied to VDD (VDDCORE should never exceed VDD). For more details about the internal voltage regulator, see Section 27.3 “On-Chip Voltage Regulator”. 1.1.5 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. The PIC18F47J13 family is also pin compatible with other PIC18 families, such as the PIC18F4550, PIC18F2450 and PIC18F46J50. This allows a new dimension to the evolution of applications, allowing developers to select different price points within Microchip’s PIC18 portfolio, while maintaining the same feature set. 1.2 Other Special Features • Communications: The PIC18F47J13 family incorporates a range of serial and parallel communication peripherals. This device includes two independent Enhanced USARTs and two Master Synchronous Serial Port (MSSP) modules, capable of both Serial Peripheral Interface (SPI) and I2C™ (Master and Slave) modes of operation. The device also has a parallel port and can be configured to serve as either a Parallel Master Port (PMP) or as a Parallel Slave Port (PSP). • CCP/ECCP Modules: All devices in the family incorporate seven Capture/Compare/PWM (CCP) modules and three Enhanced Capture/Compare/PWM (ECCP) modules to maximize flexibility in control applications. ECCPs offer up to four PWM output signals each. The ECCPs also offer many beneficial features, including polarity selection, programmable dead time, auto-shutdown and restart and Half-Bridge and Full-Bridge Output modes. DS39974A-page 12 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC18F2XJ13 (28-PIN DEVICES) Features Operating Frequency Program Memory (Kbytes) Program Memory (Instructions) Data Memory (Kbytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10/12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages PIC18F26J13 DC – 48 MHz 64 32,768 3.8 30 Ports A, B, C 8 3 ECCP and 7 CCP MSSP (2), Enhanced USART (2) No 10 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 28-Pin QFN, SOIC, SSOP and SPDIP (300 mil) PIC18F27J13 DC – 48 MHz 128 65,536 3.8 TABLE 1-2: DEVICE FEATURES FOR THE PIC18F4XJ13 (44-PIN DEVICES) Features PIC18F46J13 DC – 48 MHz 64 32,768 3.8 30 Ports A, B, C, D, E 8 3 ECCP and 7 CCP MSSP (2), Enhanced USART (2) Yes 13 Input Channels POR, BOR, RESET Instruction, Stack Full, Stack Underflow, MCLR, WDT (PWRT, OST) 75 Instructions, 83 with Extended Instruction Set Enabled 44-Pin QFN and TQFP PIC18F47J13 DC – 48 MHz 128 65,536 3.8 Operating Frequency Program Memory (Kbytes) Program Memory (Instructions) Data Memory (Kbytes) Interrupt Sources I/O Ports Timers Enhanced Capture/Compare/PWM Modules Serial Communications Parallel Communications (PMP/PSP) 10/12-Bit Analog-to-Digital Module Resets (and Delays) Instruction Set Packages  2010 Microchip Technology Inc. Preliminary DS39974A-page 13 PIC18F47J13 FAMILY FIGURE 1-1: PIC18F2XJ13 (28-PIN) BLOCK DIAGRAM Table Pointer inc/dec logic 21 20 8 PCLATU PCLATH Data Bus Data Latch Data Memory (3.8 Kbytes) Address Latch 12 Data Address 4 BSR 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank 12 PORTC RC0:RC7(1) PORTB RB0:RB7(1) PORTA RA0:RA7(1) 8 PCU PCH PCL Program Counter 31-Level Stack Address Latch Program Memory Data Latch 8 STKPTR Table Latch ROM Latch Instruction Bus IR Address Decode Instruction Decode and Control State Machine Control Signals 8 PRODH PRODL 3 BITOP 8 8 ALU 8 8 x 8 Multiply 8 W 8 8 OSC2/CLKO OSC1/CLKI Timing Generation 8 MHz INTOSC INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset 8 Precision Band Gap Reference Voltage Regulator Watchdog Timer Brown-out Reset(2) VDDCORE/VCAP VDD, VSS MCLR RTCC HLVD ADC Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Timer8 Comparators CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: 2: See Table 1-3 for I/O port pin descriptions. BOR functionality is provided when the on-board voltage regulator is enabled. DS39974A-page 14 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 1-2: PIC18F4XJ13 (44-PIN) BLOCK DIAGRAM Data Bus Table Pointer inc/dec logic 21 20 Data Latch Data Memory (3.8 Kbytes) Address Latch 12 Data Address 4 BSR PORTA RA0:RA7(1) 8 PCLATU PCLATH 8 PCU PCH PCL Program Counter 31-Level Stack PORTB RB0:RB7(1) System Bus Interface Address Latch Program Memory Data Latch 8 Table Latch 12 FSR0 FSR1 FSR2 inc/dec logic 4 Access Bank STKPTR PORTC RC0:RC7(1) 12 PORTD RD0:RD7(1) ROM Latch Instruction Bus IR Address Decode PORTE RE0:RE2(1) 8 AD, A (Multiplexed with PORTD and PORTE) Instruction Decode and Control State Machine Control Signals PRODH PRODL 3 BITOP 8 8 8 x 8 Multiply 8 W 8 8 8 OSC2/CLKO OSC1/CLKI Timing Generation 8 MHz INTOSC INTRC Oscillator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) ALU 8 Precision Band Gap Reference Voltage Regulator VDDCORE/VCAP VDD, VSS MCLR RTCC HLVD ADC Timer0 Timer1 Timer2 Timer3 Timer4 Timer5 Timer6 Timer8 Comparators CTMU ECCP1 ECCP2 ECCP3 CCP4 CCP5 CCP6 CCP7 CCP8 CCP9 CCP10 EUSART1 EUSART2 MSSP1 MSSP2 Note 1: 2: See Table 1-3 for I/O port pin descriptions. The on-chip voltage regulator is always enabled by default.  2010 Microchip Technology Inc. Preliminary DS39974A-page 15 PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC 1(2) 9 26(2) 6 I I ST Description MCLR OSC1/CLKI/RA7 OSC1 Master Clear (Reset) input. This pin is an active-low Reset to the device. CLKI RA7(1) OSC2/CLKO/RA6 OSC2 CLKO 10 7 I I/O O O Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; CMOS otherwise. Main oscillator input connection. CMOS External clock source input; always associated with pin function, OSC1 (see related OSC1/CLKI pins). TTL/DIG Digital I/O. ST Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. DIG Main oscillator feedback output connection. In RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. TTL/DIG Digital I/O. — RA6(1) I/O Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant. DS39974A-page 16 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/RP0 RA0 AN0 C1INA ULPWU RP0 RA1/AN1/C2INA/VBG/CTDIN/ RP1 RA1 AN1 C2INA VBG CTDIN RP1 RA2/AN2/C2INB/C1IND/ C3INB/VREF-/CVREF RA2 AN2 C2INB C1IND C3INB VREFCVREF RA3/AN3/C1INB/VREF+ RA3 AN3 C1INB VREF+ RA5/AN4/C1INC/SS1/ HLVDIN/RP2 RA5 AN4 C1INC SS1 HLVDIN RP2 RA6(1) RA7(1) 2 27 I/O I I I I/O 3 28 I/O O I O I I/O 4 1 I/O I I I I O I 5 2 I/O I I I 7 4 I/O I I I I I/O TTL/DIG Analog Analog TTL Analog ST/DIG Digital I/O. Analog Input 4. Comparator 1 Input C. SPI slave select input. High/Low-Voltage Detect input. Remappable Peripheral Pin 2 input/output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. TTL/DIG Analog Analog Analog Digital I/O. Analog Input 3. Comparator 1 Input B. A/D reference voltage (high) input. TTL/DIG Analog Analog Analog Analog Analog Analog Digital I/O. Analog Input 2. Comparator 2 Input B. Comparator 1 Input D. Comparator 3 Input B. A/D reference voltage (low) input. Comparator reference voltage output. TTL/DIG Analog Analog Analog ST ST/DIG Digital I/O. Analog Input 1. Comparator 2 Input A. Band Gap Reference Voltage (VBG) output. CTMU pulse delay input. Remappable Peripheral Pin 1 input/output. TTL/DIG Analog Analog Analog ST/DIG Digital I/O. Analog Input 0. Comparator 1 Input A. Ultra low-power wake-up input. Remappable Peripheral Pin 0 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 17 PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/C3IND/INT0/RP3 RB0 AN12 C3IND INT0 RP3 RB1/AN10/C3INC/RTCC/RP4 RB1 AN10 C3INC RTCC RP4 RB2/AN8/C2INC/CTED1/ REFO/RP5 RB2 AN8 C2INC CTED1 REFO RP5 RB3/AN9/C3INA/CTED2/ RP6 RB3 AN9 C3INA CTED2 RP6 21 18 I/O I I I I/O 22 19 I/O I I O I/O 23 20 I/O I I I O I/O 24 21 I/O I I I I TTL/DIG Analog Analog ST ST/DIG Digital I/O. Analog Input 9. Comparator 3 Input A. CTMU edge 2 Input. Remappable Peripheral Pin 6 input/output. TTL/DIG Analog Analog ST DIG ST/DIG Digital I/O. Analog Input 8. Comparator 2 Input C. CTMU Edge 1 input. Reference output clock. Remappable Peripheral Pin 5 input/output. TTL/DIG Analog Analog DIG ST/DIG Digital I/O. Analog Input 10. Comparator 3 input. Real-Time Clock Calendar output. Remappable Peripheral Pin 4 input/output. TTL/DIG Analog Analog ST ST/DIG Digital I/O. Analog Input 12. Comparator 3 Input D. External Interrupt 0. Remappable Peripheral Pin 3 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant. DS39974A-page 18 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTB (continued) RB4/CCP4/KBI0/SCL2/RP7 RB4 CCP4 KBI0 SCL2 RP7 RB5/CCP5/KBI1/SDA2/RP8 RB5 CCP5 KBI1 SDA2 RP8 RB6/CCP6/KBI2/PGC/RP9 RB6 CCP6 KBI2 PGC RP9 RB7/CCP7/KBI3/PGD/RP10 RB7 CCP7 KBI3 PGD RP10 25(2) 22 (2) I/O I/O I I/O I/O 26(2) 23(2) I/O I/O I I/O I/O 27(2) 24(2) I/O I/O I I I/O 28(2) 25(2) I/O I/O I I/O I/O TTL/DIG ST/DIG TTL I2C™ ST/DIG TTL/DIG ST/DIG TTL I2C ST/DIG TTL/DIG ST/DIG TTL ST ST/DIG TTL/DIG ST/DIG TTL ST/DIG ST/DIG Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. I2C clock input/output. Remappable Peripheral Pin 7 input/output. Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. I2C data input/output. Remappable Peripheral Pin 8 input/output. Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. ICSP™ clock input. Remappable Peripheral Pin 9 input/output. Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Remappable Peripheral Pin 10 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output I2C™ = Open-Drain, I2C specific Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 19 PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/CCP8/T1OSI/RP12 RC1 CCP8 T1OSI RP12 RC2/AN11/C2IND/CTPLS/RP13 RC2 AN11 C2IND CTPLS RP13 RC3/SCK1/SCL1/RP14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 RC5 SDO1 RP16 RC6/CCP9/TX1/CK1/RP17 RC6 CCP9 TX1 CK1 RP17 RC7/CCP10/RX1/DT1/RP18 RC7 CCP10 RX1 DT1 RP18 18 (2) 11 8 I/O O I I/O ST/DIG Analog ST ST/DIG ST/DIG ST/DIG Analog ST/DIG ST/DIG Analog Analog DIG ST/DIG ST/DIG ST/DIG I2C ST/DIG ST/DIG ST I2C™ ST/DIG ST/DIG DIG ST/DIG ST/DIG ST/DIG DIG ST/DIG ST/DIG ST/DIG ST/DIG ST ST/DIG ST/DIG Digital I/O. Timer1 oscillator output. Timer1 external digital clock input. Remappable Peripheral Pin 11 input/output. Digital I/O. Capture/Compare/PWM input/output. Timer1 oscillator input. Remappable Peripheral Pin 12 input/output. Digital I/O. Analog Input 11. Comparator 2 Input D. CTMU pulse generator output. Remappable Peripheral Pin 13 input/output. Digital I/O. SPI clock input/output. I2C clock input/output. Remappable Peripheral Pin 14 input/output. Digital I/O. SPI data input. I2C data input/output. Remappable Peripheral Pin 15 input/output. Digital I/O. SPI data output. Remappable Peripheral Pin 16 input/output. Digital I/O. Capture/Compare/PWM input/output. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Remappable Peripheral Pin 17 input/output. Digital I/O. Capture/Compare/PWM input/output. Asynchronous serial receive data input. Synchronous serial data output/input. Remappable Peripheral Pin 18 input/output. 12 9 I/O I/O I I/O 13 10 I/O I I O I/O 14 11 I/O I/O I/O I/O 15 12 I/O I I/O I/O 16 13 I/O O I/O 17(2) 14(2) I/O I/O O I/O I/O 15 (2) I/O I/O I I/O I/O Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant. DS39974A-page 20 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-3: PIC18F2XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 28-SPDIP/ SSOP/ 28-QFN Type Type SOIC 8 19 20 6 5 16 17 3 P — P — P P — — — — — — Positive supply for peripheral digital logic and I/O pins. Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Description VSS1 VSS2 VDD VDDCORE/VCAP VDDCORE VCAP Ground reference for logic and I/O pins. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 21 PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP 18(3) 32 18 30 I I ST Description MCLR OSC1/CLKI/RA7 OSC1 Master Clear (Reset) input; this is an active-low Reset to the device. CLKI RA7(1) OSC2/CLKO/RA6 OSC2 CLKO 33 31 I I/O O O Oscillator crystal or external clock input. Oscillator crystal input or external clock source input. ST buffer when configured in RC mode; otherwise CMOS. Main oscillator input connection. CMOS External clock source input; always associated with pin function, OSC1 (see related OSC1/CLKI pins). TTL/DIG Digital I/O. ST Oscillator crystal or clock output. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. — Main oscillator feedback output connection in RC mode, OSC2 pin outputs CLKO, which has 1/4 the frequency of OSC1 and denotes the instruction cycle rate. TTL/DIG Digital I/O. — RA6(1) I/O Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output I2C™ = Open-Drain, I2C specific Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant. DS39974A-page 22 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTA is a bidirectional I/O port. RA0/AN0/C1INA/ULPWU/PMA6/ RP0 RA0 AN0 C1INA ULPWU PMA6 RP0 RA1/AN1/C2INA/VBG/CTDIN/ PMA7/RP1 RA1 AN1 C2INA VBG CTDIN PMA7 RP1 RA2/AN2/C2INB/C1IND/C3INB/ VREF-/CVREF RA2 AN2 C2INB C1IND C3INB VREFCVREF RA3/AN3/C1INB/VREF+ RA3 AN3 C1INB VREF+ RA5/AN4/C1INC/SS1/HLVDIN/RP2 RA5 AN4 C1INC SS1 HLVDIN RP2 RA6(1) RA7(1) 21 21 I/O I I I I I I 22 22 I/O I I I 24 24 I/O I I I I I/O TTL/DIG Analog Analog TTL Analog ST/DIG Digital I/O. Analog Input 4. SPI slave select input. Comparator 1 Input C. High/Low-Voltage Detect input. Remappable Peripheral Pin 2 input/output. See the OSC2/CLKO/RA6 pin. See the OSC1/CLKI/RA7 pin. TTL/DIG Analog Analog Analog Digital I/O. Analog Input 3. Comparator 1 Input B. A/D reference voltage (high) input. TTL/DIG Analog Analog Analog Analog Analog Analog Digital I/O. Analog Input 2. Comparator 2 Input B. Comparator 1 Input D. Comparator 3 Input B. A/D reference voltage (low) input. Comparator reference voltage output. 20 20 I/O O I O I I/O I/O TTL/DIG Analog Analog Analog ST ST/TTL/ DIG ST/DIG Digital I/O. Analog Input 1. Comparator 2 Input A. Band Gap Reference Voltage (VBG) output. CTMU pulse delay input. Parallel Master Port digital I/O. Remappable Peripheral Pin 1 input/output. 19 19 I/O I I I I/O I/O TTL/DIG Analog Analog Analog ST/TTL/ DIG ST/DIG Digital I/O. Analog Input 0. Comparator 1 Input A. Ultra low-power wake-up input. Parallel Master Port digital I/O. Remappable Peripheral Pin 0 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output I2C™ = Open-Drain, I2C specific Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 23 PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs. RB0/AN12/C3IND/INT0/RP3 RB0 AN12 C3IND INT0 RP3 RB1/AN10/C3INC/PMBE/RTCC/ RP4 RB1 AN10 C3INC PMBE(2) RTCC RP4 RB2/AN8/C2INC/CTED1/PMA3/ REFO/RP5 RB2 AN8 C2INC CTED1 PMA3(2) REFO RP5 RB3/AN9/C3INA/CTED2/PMA2/ RP6 RB3 AN9 C3INA CTED2 PMA2(2) RP6 9 8 I/O I I I I/O 10 9 I/O I I O O I/O 11 10 I/O I I I O O I/O 12 11 I/O I I I O I/O TTL/DIG Analog Analog ST DIG ST/DIG Digital I/O. Analog Input 9. Comparator 3 Input A. CTMU Edge 2 input. Parallel Master Port address. Remappable Peripheral Pin 6 input/output. TTL/DIG Analog Analog ST DIG DIG ST/DIG Digital I/O. Analog Input 8. Comparator 2 Input C. CTMU Edge 1 input. Parallel Master Port address. Reference output clock. Remappable Peripheral Pin 5 input/output. TTL/DIG Analog Analog DIG DIG ST/DIG Digital I/O. Analog Input 10. Comparator 3 Input C. Parallel Master Port byte enable. Asynchronous serial transmit data output. Remappable Peripheral Pin 4 input/output. TTL/DIG Analog Analog ST ST/DIG Digital I/O. Analog Input 12. Comparator 3 Input D. External Interrupt 0. Remappable Peripheral Pin 3 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant. DS39974A-page 24 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP (3) (3) Description PORTB (continued) RB4/CCP4/PMA1/KBI0/RP7 RB4 CCP4(2) PMA1(2) KBI0 RP7 RB5/CCP5/PMA0/KBI1/RP8 RB5 CCP5 PMA0(2) KBI1 RP8 RB6/CCP6/KBI2/PGC/RP9 RB6 CCP6 KBI2 PGC RP9 RB7/CCP7/KBI3/PGD/RP10 RB7 CCP7 KBI3 PGD RP10 14 14 I/O I/O I/O I I/O 15(3) 15(3) I/O I/O I/O I I/O 16(3) 16(3) I/O I/O I I I/O 17(3) 17(3) I/O I/O I I/O I/O TTL/DIG ST/DIG ST/TTL/ DIG TTL ST/DIG TTL/DIG ST/DIG ST/TTL/ DIG TTL ST/DIG TTL/DIG ST/DIG TTL ST ST/DIG TTL/DIG ST/DIG TTL ST/DIG ST/DIG Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address. Interrupt-on-change pin. Remappable Peripheral Pin 7 input/output. Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address. Interrupt-on-change pin. Remappable Peripheral Pin 8 input/output. Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. ICSP™ clock input. Remappable Peripheral Pin 9 input/output. Digital I/O. Capture/Compare/PWM input/output. Interrupt-on-change pin. In-Circuit Debugger and ICSP programming data pin. Remappable Peripheral Pin 10 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 25 PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTC is a bidirectional I/O port. RC0/T1OSO/T1CKI/RP11 RC0 T1OSO T1CKI RP11 RC1/CCP8/T1OSI/RP12 RC1 CCP8 T1OSI RP12 RC2/AN11/C2IND/CTPLS/RP13 RC2 AN11 C2IND CTPLS RP13 RC3/SCK1/SCL1/RP14 RC3 SCK1 SCL1 RP14 RC4/SDI1/SDA1/RP15 RC4 SDI1 SDA1 RP15 RC5/SDO1/RP16 RC5 SDO1 RP16 34 32 I/O O I I/O 35 35 I/O I/O I I/O 36 36 I/O I I O I/O 37 37 I/O I/O I/O I/O 42 42 I/O I I/O I/O 43 43 I/O O I/O ST/DIG DIG ST/DIG Digital I/O. SPI data output. Remappable Peripheral Pin 16 input/output. ST/DIG ST I2C™ ST/DIG Digital I/O. SPI data input. I2C data input/output. Remappable Peripheral Pin 15 input/output. ST/DIG ST/DIG I2C ST/DIG Digital I/O. SPI clock input/output. I2C clock input/output. Remappable Peripheral Pin 14 input/output. ST/DIG Analog Analog DIG ST/DIG Digital I/O. Analog Input 11. Comparator 2 Input D. CTMU pulse generator output. Remappable Peripheral Pin 13 input/output. ST/DIG ST/DIG Analog ST/DIG Digital I/O. Capture/Compare/PWM input/output. Timer1 oscillator input. Remappable Peripheral Pin 12 input/output. STDIG Analog ST ST/DIG Digital I/O. Timer1 oscillator output. Timer1/Timer3 external clock input. Remappable Peripheral Pin 11 input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant. DS39974A-page 26 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP (3) (3) Description PORTC (continued) RC6/CCP9/PMA5/TX1/CK1/RP17 RC6 CCP9 PMA5 TX1 CK1 RP17 44 44 I/O I/O I/O O I/O I/O (3) ST/DIG ST/DIG DIG ST/TTL/ DIG ST/DIG ST/DIG ST/DIG ST/DIG ST/TTL/ DIG ST ST/DIG ST/DIG Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address. EUSART1 asynchronous transmit. EUSART1 synchronous clock (see related RX1/DT1). Remappable Peripheral Pin 17 input/output. Digital I/O. Capture/Compare/PWM input/output. Parallel Master Port address. EUSART1 asynchronous receive. EUSART Synchronous data (see related TX1/CK1). Remappable Peripheral Pin 18 input/output. RC7/CCP10/PMA4/RX1/DT1/RP18 1 RC7 CCP10 PMA4 RX1 DT1 RP18 1(3) I/O I/O I/O I I/O I/O Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) DIG = Digital output I2C™ = Open-Drain, I2C specific Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 27 PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP 38(3) (3) Description PORTD is a bidirectional I/O port. RD0/PMD0/SCL2 RD0 PMD0 SCL2 RD1/PMD1/SDA2 RD1 PMD1 SDA2 RD2/PMD2/RP19 RD2 PMD2 RP19 RD3/PMD3/RP20 RD3 PMD3 RP20 RD4/PMD4/RP21 RD4 PMD4 RP21 RD5/PMD5/RP22 RD5 PMD5 RP22 RD6/PMD6/RP23 RD6 PMD6 RP23 RD7/PMD7/RP24 RD7 PMD7 RP24 38 I/O I/O I/O 39(3) 39(3) I/O I/O I/O 40(3) 40(3) I/O I/O I/O 41(3) 41(3) I/O I/O I/O 2(3) 2(3) I/O I/O I/O 3(3) 3(3) I/O I/O I/O 4(3) 4 (3) ST/DIG ST/TTL/ DIG I2C ST/DIG ST/TTL/ DIG I2C ST/DIG ST/TTL/ DIG ST/DIG ST/DIG ST/TTL/ DIG ST/DIG ST/DIG ST/TTL/ DIG ST/DIG ST/DIG ST/TTL/ DIG ST/DIG ST/DIG ST/TTL/ DIG ST/DIG ST/DIG ST/TTL/ DIG ST/DIG Digital I/O. Parallel Master Port data. I2C™ data input/output. Digital I/O. Parallel Master Port data. I2C data input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 19 input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 20 input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 21 input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 22 input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 23 input/output. Digital I/O. Parallel Master Port data. Remappable Peripheral Pin 24 input/output. I/O I/O I/O 5(3) 5(3) I/O I/O I/O Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant. DS39974A-page 28 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 1-4: PIC18F4XJ13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name Pin Buffer 44- 44- Type Type QFN TQFP Description PORTE is a bidirectional I/O port. RE0/AN5/PMRD RE0 AN5 PMRD RE1/AN6/PMWR RE1 AN6 PMWR RE2/AN7/PMCS RE2 AN7 PMCS VSS1 VSS2 AVSS1 VDD1 VDD2 VDDCORE/VCAP VDDCORE VCAP AVDD1 AVDD2 7 28 — — 25 25 I/O I I/O 26 26 I/O I I/O 27 27 I/O I O 6 31 30 8 29 23 6 29 — 7 28 23 P P P — — — — — P — P P P ST/DIG Analog DIG — — — — — Ground reference for analog modules. Positive supply for peripheral digital logic and I/O pins. Core logic power or external filter capacitor connection. Positive supply for microcontroller core logic (regulator disabled). External filter capacitor connection (regulator enabled). Positive supply for analog modules. Positive supply for analog modules. Digital I/O. Analog Input 7. Parallel Master Port byte enable. Ground reference for logic and I/O pins. ST/DIG Analog ST/TTL/ DIG Digital I/O. Analog Input 6. Parallel Master Port write strobe. ST/DIG Analog ST/TTL/ DIG Digital I/O. Analog Input 5. Parallel Master Port input/output. Legend: TTL = TTL compatible input CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input I = Input O = Output P = Power OD = Open-Drain (no P diode to VDD) = Open-Drain, I2C specific DIG = Digital output I2C™ Note 1: RA7 and RA6 will be disabled if OSC1 and OSC2 are used for the clock function. 2: Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 3: 5.5V tolerant.  2010 Microchip Technology Inc. Preliminary DS39974A-page 29 PIC18F47J13 FAMILY NOTES: DS39974A-page 30 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) 2.1 VDD VDD Getting started with the PIC18F47J13 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • VCAP/VDDCORE pins (see Section 2.4 “Voltage Regulator Pins (VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGC/PGD pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins are used when external voltage reference for analog modules is implemented Note: On 44-pin QFN packages, the AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. On other package types, the AVDD and AVSS pins are internally connected to the VDD/VSS pins. R1 R2 MCLR VSS (1) VCAP/VDDCORE C1 PIC18FXXJXX VSS VDD C7 C6(2) AVDD VDD VSS AVSS VDD VSS C3(2) C5(2) C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: See Section 2.4 “Voltage Regulator Pins (VCAP/VDDCORE)” for explanation of VCAP/VDDCORE connections. The example shown is for a PIC18F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 2: The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. Preliminary DS39974A-page 31 PIC18F47J13 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS, is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device, with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: Device Reset, and Device Programming and Debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC18FXXJXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits, including microcontrollers, to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39974A-page 32 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 2.4 Voltage Regulator Pins (VCAP/VDDCORE) 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of ohms, not to exceed 100Ω. Pull-up resistors, series diodes, and capacitors on the PGC and PGD pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits, and pin input voltage high (VIH) and input low (VIL) requirements. For device emulation, ensure that the “Communication Channel Select” (i.e., PGCx/PGDx pins) programmed into the device matches the physical connections for the ICSP to the Microchip debugger/emulator tool. For more information on available Microchip development tools connection requirements, refer to Section 29.0 “Development Support”. On “F” devices, a low-ESR (< 5Ω) capacitor is required on the VCAP/VDDCORE pin to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD and must use a capacitor of 10 F connected to ground. The type can be ceramic or tantalum. A suitable example is the Murata GRM21BF50J106ZE01 (10 F, 6.3V) or equivalent. Designers may use Figure 2-3 to evaluate ESR equivalence of candidate devices. It is recommended that the trace length not exceed 0.25 inch (6 mm). Refer to Section 30.0 “Electrical Characteristics” for additional information. On “LF” devices, the VCAP/VDDCORE pin must be tied to a voltage supply at the VDDCORE level. Refer to Section 30.0 “Electrical Characteristics” for information on VDD and VDDCORE. Note that the “LF” versions of these devices are provided with the voltage regulator permanently disabled; they must always be provided with a supply voltage on the VDDCORE pin. FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP 10 1 ESR () 0.1 0.01 0.001 0.01 0.1 1 10 100 Frequency (MHz) 1000 10,000 Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25°C, 0V DC bias.  2010 Microchip Technology Inc. Preliminary DS39974A-page 33 PIC18F47J13 FAMILY 2.6 External Oscillator Pins FIGURE 2-4: Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0.5 inch (12 mm) between the circuit components and the pins. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate it from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. Layout suggestions are shown in Figure 2-4. In-line packages may be handled with a single-sided layout that completely encompasses the oscillator pins. With fine-pitch packages, it is not always possible to completely surround the pins and components. A suitable solution is to tie the broken guard sections to a mirrored ground layer. In all cases, the guard trace(s) must be returned to ground. In planning the application’s routing and I/O assignments, ensure that adjacent port pins and other signals in close proximity to the oscillator are benign (i.e., free of high frequencies, short rise and fall times, and other similar noise). For additional information and design guidance on oscillator circuits, please refer to these Microchip Application Notes, available at the corporate web site (www.microchip.com): • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC™ and PICmicro® Devices” • AN849, “Basic PICmicro® Oscillator Design” • AN943, “Practical PICmicro® Oscillator Analysis and Design” • AN949, “Making Your Oscillator Work” SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Single-Sided and In-Line Layouts: Copper Pour (tied to ground) Primary Oscillator Crystal DEVICE PINS Primary Oscillator C1 C2 ` OSC1 OSC2 GND ` T1OSO Timer1 Oscillator Crystal T1OS I ` T1 Oscillator: C1 T1 Oscillator: C2 Fine-Pitch (Dual-Sided) Layouts: Top Layer Copper Pour (tied to ground) Bottom Layer Copper Pour (tied to ground) OSCO C2 GND Oscillator Crystal C1 OSCI 2.7 Unused I/Os DEVICE PINS Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1 kΩ to 10 kΩ resistor to VSS on unused pins and drive the output to logic low. DS39974A-page 34 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.0 3.1 OSCILLATOR CONFIGURATIONS Overview TABLE 3-1: Mode ECPLL OSCILLATOR MODES Description External Clock Input mode, the PLL can be enabled or disabled in software, CLKO on RA6, apply external clock signal to RA7. External Clock Input mode, the PLL is always disabled, CLKO on RA6, apply external clock signal to RA7. High-Speed Crystal/Resonator mode, PLL can be enabled or disabled in software, crystal/resonator connected between RA6 and RA7. High-Speed Crystal/Resonator mode, PLL always disabled, crystal/resonator connected between RA6 and RA7. Devices in the PIC18F47J13 family incorporate a different oscillator and microcontroller clock system than general purpose PIC18F devices. The PIC18F47J13 family has additional prescalers and postscalers, which have been added to accommodate a wide range of oscillator frequencies. The PIC18F47J13 provides two PLL circuits: a 4x multiplier PLL and a 96 MHz PLL enabling 48 MHz operation from the 8 MHz internal oscillator. Figure 3-1 provides an overview of the oscillator structure. Other oscillator features used in PIC18 enhanced microcontrollers, such as the internal oscillator block and clock switching, remain the same. They are discussed later in this chapter. EC HSPLL HS 3.1.1 OSCILLATOR CONTROL The operation of the oscillator in PIC18F47J13 family devices is controlled through three Configuration registers and two control registers. Configuration registers, CONFIG1L, CONFIG1H and CONFIG2L, select the oscillator mode, PLL prescaler and CPU divider options. As Configuration bits, these are set when the device is programmed and left in that configuration until the device is reprogrammed. The OSCCON register (Register 3-2) selects the Active Clock mode. It is primarily used in controlling clock switching in power-managed modes. Its use is discussed in Section 3.3.1 “Oscillator Control Register”. The OSCTUNE register (Register 3-1) is used to trim the INTOSC frequency source and select the low-frequency clock source that drives several special features. The OSCTUNE register is also used to activate or disable the Phase Locked Loop (PLL). Its use is described in Section 3.2.5.1 “OSCTUNE Register”. INTOSCPLLO Internal Oscillator mode, PLL can be enabled or disabled in software, CLKO on RA6, port function on RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock. INTOSCPLL Internal Oscillator mode, PLL can be enabled or disabled in software, port function on RA6 and RA7, the internal oscillator block is used to derive both the primary clock source and the postscaled internal clock. INTOSCO Internal Oscillator mode, PLL is always disabled, CLKO on RA6, port function on RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source. Internal Oscillator mode, PLL is always disabled, port function on RA6 and RA7, the output of the INTOSC postscaler serves as both the postscaled internal clock and the primary clock source. INTOSC 3.2.1 OSCILLATOR MODES 3.2 Oscillator Types PIC18F47J13 family devices can be operated in eight distinct oscillator modes. Users can program the FOSC Configuration bits to select one of the modes listed in Table 3-1. For oscillator modes which produce a clock output (CLKO) on pin, RA6, the output frequency will be one fourth of the peripheral clock frequency. The clock output stops when in Sleep mode, but will continue during Idle mode (see Figure 3-1). A network of MUXes, clock dividers and two PLL circuits have been provided, which can be used to derive various microcontroller frequencies. Figure 3-1 helps in understanding the oscillator structure of the PIC18F47J13 family of devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 35 PIC18F47J13 FAMILY FIGURE 3-1: PIC18F47J13 FAMILY CLOCK DIAGRAM PLLDIV  12  10 6 5 4 3 2 1 000 001 010 011 100 101 110 111 PLL Prescaler 4 MHz 96 MHz PLL(1) 2 48 MHz Primary Oscillator OSC2 FOSC OSC1 1 0 1 0 0 FOSC 1 PLLSEL 1 4x PLL(2) 0 PLLEN CFGPLLEN Other Primary Clock Source IDLE CPU 00 Timer1 Clock(3) Postscaled Internal Clock 01 11 4 Peripherals RA6 FOSC 00 Secondary Oscillator T1OSO OSCCON 8 MHz INTOSC Postscaler Internal Oscillator Block 8 MHz INTRC 31 kHz 8 MHz 111 4 MHz 110 2 MHz 101 1 MHz 100 500 kHz 011 250 kHz 010 125 kHz 001 1 31 kHz 000 0 OSCTUNE T1OSI OSCCON CLKO Enabled Modes WDT, PWRT, FSCM and Two-Speed Start-up Note 1: 2: 3: The 96 MHz PLL requires a 4 MHz input and it produces a 96 MHz output. The 96 MHz PLL prescaler enables source clocks of 4, 8, 12, 16, 20, 24, 40 or 48 MHz to provide the 4 MHz input. The 4x PLL requires an input clock source between 4 and 12 MHz. When using INTOSC to provide the 4x PLL input, the INTOSC postscaler must be set to either 8 MHz or 4 MHz. Selecting other INTOSC postscaler settings will operate the PLL outside of the specification. Selecting the Timer1 clock or postscaled internal clock will turn off the primary oscillator (unless required by the reference clock of Section 3.4 “Reference Clock Output”) and PLL. DS39974A-page 36 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.2.2 CRYSTAL OSCILLATOR/CERAMIC RESONATORS TABLE 3-3: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Crystal Freq 4 MHz 8 MHz 16 MHz Typical Capacitor Values Tested: C1 HS 27 pF 22 pF 18 pF C2 27 pF 22 pF 18 pF In HS and HSPLL Oscillator modes, a crystal or ceramic resonator is connected to the OSC1 and OSC2 pins to establish oscillation. Figure 3-2 displays the pin connections. The oscillator design requires the use of a parallel resonant crystal. Note: Use of a series resonant crystal may give a frequency out of the crystal manufacturer’s specifications. Osc Type Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following this table for additional information. Crystals Used: 4 MHz 8 MHz 16 MHz Note 1: Higher capacitance not only increases the stability of oscillator, but also increases the start-up time. 2: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 3: Rs may be required to avoid overdriving crystals with low drive level specification. 4: Always verify oscillator performance over the VDD and temperature range that is expected for the application. An internal postscaler allows users to select a clock frequency other than that of the crystal or resonator. Frequency division is determined by the CPDIV Configuration bits. Users may select a clock frequency of the oscillator frequency, or 1/2, 1/3 or 1/6 of the frequency. FIGURE 3-2: CRYSTAL/CERAMIC RESONATOR OPERATION (HS OR HSPLL CONFIGURATION) OSC1 To Internal Logic Sleep PIC18F47J13 C1(1) XTAL RS(2) C2(1) Note 1: 2: OSC2 See Table 3-2 and Table 3-3 for initial values of C1 and C2. RS may be required to avoid overdriving crystals with low drive level specifications. TABLE 3-2: CAPACITOR SELECTION FOR CERAMIC RESONATORS Typical Capacitor Values Used: Mode HS Freq 8.0 MHz 16.0 MHz OSC1 27 pF 22 pF OSC2 27 pF 22 pF Capacitor values are for design guidance only. These capacitors were tested with the resonators listed below for basic start-up and operation. These values are not optimized. Different capacitor values may be required to produce acceptable oscillator operation. The user should test the performance of the oscillator over the expected VDD and temperature range for the application. See the notes following Table 3-3 for additional information. Resonators Used: 4.0 MHz 8.0 MHz 16.0 MHz  2010 Microchip Technology Inc. Preliminary DS39974A-page 37 PIC18F47J13 FAMILY 3.2.3 EXTERNAL CLOCK INPUT The EC and ECPLL Oscillator modes require an external clock source to be connected to the OSC1 pin. There is no oscillator start-up time required after a Power-on Reset (POR) or after an exit from Sleep mode. In the EC Oscillator mode, the oscillator frequency, divided by 4, is available on the OSC2 pin. In the ECPLL Oscillator mode, the PLL output, divided by 4, is available on the OSC2 pin. This signal may be used for test purposes or to synchronize other logic. Figure 3-3 displays the pin connections for the EC Oscillator mode. The 4x PLL is designed to produce variable reference clocks of 16 to 48 MHz from any input clock between 4 and 12 MHz. The PLLSEL (CONFIG3H) Configuration bit is used to select which PLL circuit will be used by the application. 3.2.5 INTERNAL OSCILLATOR BLOCK The PIC18F47J13 family devices include an internal oscillator block which generates two different clock signals; either can be used as the microcontroller’s clock source. The internal oscillator may eliminate the need for external oscillator circuits on the OSC1 and/or OSC2 pins. The main output (INTOSC) is an 8 MHz clock source which can be used to directly drive the device clock. It also drives the INTOSC postscaler which can provide a range of clock frequencies from 31 kHz to 8 MHz. Additionally, the INTOSC may be used in conjunction with a PLL to generate clock frequencies up to 48 MHz. The other clock source is the internal RC oscillator (INTRC) which provides a nominal 31 kHz output. INTRC is enabled if it is selected as the device clock source. It is also enabled automatically when any of the following are enabled: • • • • Power-up Timer Fail-Safe Clock Monitor Watchdog Timer Two-Speed Start-up FIGURE 3-3: EXTERNAL CLOCK INPUT OPERATION (EC AND ECPLL CONFIGURATION) OSC1/CLKI Clock from Ext. System FOSC/4 PIC18F47J13 OSC2/CLKO 3.2.4 PLL FREQUENCY MULTIPLIER A Phase Locked Loop (PLL) circuit provides an option for users who want to use a low-frequency oscillator circuit or clock the device up to its highest rated frequency from a crystal oscillator. This may be useful for customers who are concerned with EMI due to high-frequency crystals or users who require higher clock speeds from the internal oscillator. PIC18F47J13 family devices include two PLL circuits: a 4x PLL and a 96 MHz PLL. Either PLL can be enabled in HSPLL, ECPLL, INTOSCPLL and INTOSCPLLO Oscillator modes by setting the PLLEN bit (OSCTUNE) or by clearing the CFGPLLEN bit (CONFIG1L). The 96 MHz PLL is designed to produce a fixed 96 MHz reference clock from a fixed 4 MHz input. The output can then be divided and used for producing a 48 MHz microcontroller core clock. Because the PLL has a fixed frequency input and output, there are eight prescaling options to match the oscillator input frequency to the PLL. This prescaler allows the PLL to be used with crystals, resonators and external clocks, which are integer multiple frequencies of 4 MHz. For example, a 12 MHz crystal could be used in a prescaler Divide-by-Three mode to drive the 96 MHz PLL. These features are discussed in larger detail in Section 27.0 “Special Features of the CPU”. The clock source frequency (INTOSC direct, INTRC direct or INTOSC postscaler) is selected by configuring the IRCF bits of the OSCCON register (page 42). DS39974A-page 38 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.2.5.1 OSCTUNE Register 3.2.5.3 Compensating for INTOSC Drift The internal oscillator’s output has been calibrated at the factory but can be adjusted in the user’s application. This is done by writing to the OSCTUNE register (Register 3-1). When the OSCTUNE register is modified, the INTOSC frequency will begin shifting to the new frequency. The INTOSC clock will typically stabilize within 1 s. Code execution continues during this shift. There is no indication that the shift has occurred. The OSCTUNE register also contains the INTSRC bit. The INTSRC bit allows users to select which internal oscillator provides the clock source when the 31 kHz frequency option is selected. This is covered in larger detail in Section 3.3.1 “Oscillator Control Register”. The PLLEN bit, contained in the OSCTUNE register, can be used to enable or disable the internal PLL when running in one of the PLL type oscillator modes (e.g., INTOSCPLL). Oscillator modes that do not contain “PLL” in their name cannot be used with the PLL. In these modes, the PLL is always disabled regardless of the setting of the PLLEN bit. When configured for one of the PLL enabled modes, setting the PLLEN bit does not immediately switch the device clock to the PLL output. The PLL requires up to electrical parameter, trc, to start-up and lock, during which time, the device continues to be clocked. Once the PLL output is ready, the microcontroller core will automatically switch to the PLL derived frequency. It is possible to adjust the INTOSC frequency by modifying the value in the OSCTUNE register. This has no effect on the INTRC clock source frequency. Tuning the INTOSC source requires knowing when to make the adjustment, in which direction it should be made, and in some cases, how large a change is needed. When using the EUSART, for example, an adjustment may be required when it begins to generate framing errors or receives data with errors while in Asynchronous mode. Framing errors indicate that the device clock frequency is too high; to adjust for this, decrement the value in OSCTUNE to reduce the clock frequency. On the other hand, errors in data may suggest that the clock speed is too low; to compensate, increment OSCTUNE to increase the clock frequency. It is also possible to verify device clock speed against a reference clock. Two timers may be used: one timer is clocked by the peripheral clock, while the other is clocked by a fixed reference source, such as the Timer1 oscillator. Both timers are cleared, but the timer clocked by the reference generates interrupts. When an interrupt occurs, the internally clocked timer is read and both timers are cleared. If the internally clocked timer value is greater than expected, then the internal oscillator block is running too fast. To adjust for this, decrement the OSCTUNE register. Finally, an ECCP module can use free-running Timer1 (or Timer3), clocked by the internal oscillator block and an external event with a known period (i.e., AC power frequency). The time of the first event is captured in the CCPRxH:CCPRxL registers and is recorded for use later. When the second event causes a capture, the time of the first event is subtracted from the time of the second event. Since the period of the external event is known, the time difference between events can be calculated. If the measured time is greater than the calculated time, the internal oscillator block is running too fast; to compensate, decrement the OSCTUNE register. If the measured time is less than the calculated time, the internal oscillator block is running too slow; to compensate, increment the OSCTUNE register. 3.2.5.2 Internal Oscillator Output Frequency and Drift The internal oscillator block is calibrated at the factory to produce an INTOSC output frequency of 8.0 MHz. However, this frequency may drift as VDD or temperature changes, which can affect the controller operation in a variety of ways. The low-frequency INTRC oscillator operates independently of the INTOSC source. Any changes in INTOSC across voltage and temperature are not necessarily reflected by changes in INTRC and vice versa.  2010 Microchip Technology Inc. Preliminary DS39974A-page 39 PIC18F47J13 FAMILY REGISTER 3-1: R/W-0 INTSRC bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OSCTUNE: OSCILLATOR TUNING REGISTER (ACCESS F9Bh) R/W-0 PLLEN(1) R/W-0 TUN5 R/W-0 TUN4 R/W-0 TUN3 R/W-0 TUN2 R/W-0 TUN1 R/W-0 TUN0 bit 0 INTSRC: Internal Oscillator Low-Frequency Source Select bit 1 = 31.25 kHz device clock derived from 8 MHz INTOSC source (divide-by-256 enabled) 0 = 31 kHz device clock derived directly from INTRC internal oscillator PLLEN: Frequency Multiplier Enable bit(1) 1 = PLL is enabled 0 = PLL is disabled TUN: Frequency Tuning bits 011111 = Maximum frequency 011110 • • • 000001 000000 = Center frequency; oscillator module is running at the calibrated frequency 111111 • • • 100000 = Minimum frequency When the CFGPLLEN Configuration bit is used to enable the PLL, clearing OSCTUNE will not disable the PLL. bit 6 bit 5-0 Note 1: DS39974A-page 40 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.3 Clock Sources and Oscillator Switching 3.3.1 OSCILLATOR CONTROL REGISTER The OSCCON register (Register 3-2) controls several aspects of the device clock’s operation, both in full-power operation and in power-managed modes. The System Clock Select bits, SCS, select the clock source. The available clock sources are the primary clock (defined by the FOSC Configuration bits), the secondary clock (Timer1 oscillator) and the postscaled internal clock.The clock source changes immediately, after one or more of the bits is written to, following a brief clock transition interval. The SCS bits are cleared on all forms of Reset. The Internal Oscillator Frequency Select bits, IRCF, select the frequency output provided on the postscaled internal clock line. The choices are the INTRC source, the INTOSC source (8 MHz) or one of the frequencies derived from the INTOSC postscaler (31 kHz to 4 MHz). If the postscaled internal clock is supplying the device clock, changing the states of these bits will have an immediate change on the internal oscillator’s output. On device Resets, the default output frequency of the INTOSC postscaler is set at 4 MHz. When an output frequency of 31 kHz is selected (IRCF = 000), users may choose the internal oscillator, which acts as the source. This is done with the INTSRC bit in the OSCTUNE register (OSCTUNE). Setting this bit selects INTOSC as a 31.25 kHz clock source by enabling the divide-by-256 output of the INTOSC postscaler. Clearing INTSRC selects INTRC (nominally 31 kHz) as the clock source. This option allows users to select the tunable and more precise INTOSC as a clock source, while maintaining power savings with a very low clock speed. Regardless of the setting of INTSRC, INTRC always remains the clock source for features such as the WDT and the FSCM. The OSTS and SOSCRUN bits indicate which clock source is currently providing the device clock. The OSTS bit indicates that the Oscillator Start-up Timer (OST) has timed out and the primary clock is providing the device clock in primary clock modes. The SOSCRUN bit (OSCCON2) indicates when the Timer1 oscillator is providing the device clock in secondary clock modes. In power-managed modes, only one of these bits will be set at any time. If none of these bits are set, the INTRC is providing the clock or the internal oscillator block has just started and is not yet stable. The IDLEN bit determines if the device goes into Sleep mode, or one of the Idle modes, when the SLEEP instruction is executed. Like previous PIC18 enhanced devices, the PIC18F47J13 family includes a feature that allows the device clock source to be switched from the main oscillator to an alternate, low-frequency clock source. PIC18F47J13 family devices offer two alternate clock sources. When an alternate clock source is enabled, the various power-managed operating modes are available. Essentially, there are three clock sources for these devices: • Primary Oscillators • Secondary Oscillators • Internal Oscillator Block The Primary Oscillators include the External Crystal and Resonator modes, the External Clock modes and the internal oscillator block. The particular mode is defined by the FOSC Configuration bits. The details of these modes are covered earlier in this chapter. The Secondary Oscillators are external sources that are not connected to the OSC1 or OSC2 pins. These sources may continue to operate even after the controller is placed in a power-managed mode. PIC18F47J13 family devices offer the Timer1 oscillator as a secondary oscillator. This oscillator, in all power-managed modes, is often the time base for functions such as a Real-Time Clock (RTC). Most often, a 32.768 kHz watch crystal is connected between the RC0/T1OSO/T1CKI/RP11 and RC1/CCP8/T1OSI/RP12 pins. Like the HS Oscillator mode circuits, loading capacitors are also connected from each pin to ground. The Timer1 oscillator is discussed in larger detail in Section 13.5 “Timer1 Oscillator”. In addition to being a primary clock source, the postscaled internal clock is available as a power-managed mode clock source. The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor (FSCM).  2010 Microchip Technology Inc. Preliminary DS39974A-page 41 PIC18F47J13 FAMILY The use of the flag and control bits in the OSCCON register is discussed in more detail in Section 4.0 “Low-Power Modes”. Note 1: The Timer1 crystal driver is enabled by setting the T1OSCEN bit in the Timer1 Control register (T1CON). If the Timer1 oscillator is not enabled, then any attempt to select the Timer1 clock source will be ignored, unless the CONFIG2L register’s SOSCSEL bits are set to Digital mode. 2: If Timer1 is driving a crystal, it is recommended that the Timer1 oscillator be operating and stable prior to switching to it as the clock source; otherwise, a very long delay may occur while the Timer1 oscillator starts. 3.3.2 OSCILLATOR TRANSITIONS PIC18F47J13 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Clock transitions are discussed in more detail in Section 4.1.2 “Entering Power-Managed Modes”. REGISTER 3-2: R/W-0 IDLEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 OSCCON: OSCILLATOR CONTROL REGISTER (ACCESS FD3h) R/W-1 IRCF2 R/W-1 IRCF1 R/W-0 IRCF0 R-1(1) OSTS U-1 — R/W-0 SCS1 R/W-0 SCS0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit ‘0’ = Bit is cleared x = Bit is unknown IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction IRCF: Internal Oscillator Frequency Select bits When using INTOSC to drive the 4x PLL, select 8 MHz or 4 MHz only to avoid operating the 4x PLL outside of specification. 111 = 8 MHz (INTOSC drives clock directly) 110 = 4 MHz(2) 101 = 2 MHz 100 = 1 MHz 011 = 500 kHz 010 = 250 kHz 001 = 125 kHz 000 = 31 kHz (from either INTOSC/256 or INTRC directly)(3) OSTS: Oscillator Start-up Time-out Status bit(1) 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running; primary oscillator is not ready Unimplemented: Read as ‘1’ SCS: System Clock Select bits 11 = Postscaled internal clock (INTRC/INTOSC derived) 10 = Reserved 01 = Timer1 oscillator 00 = Primary clock source (INTOSC postscaler output when FOSC = 001 or 000) 00 = Primary clock source (CPU divider output for other values of FOSC) Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. Default output frequency of INTOSC on Reset (4 MHz). Source selected by the INTSRC bit (OSCTUNE). bit 6-4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: DS39974A-page 42 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 3-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h) R-0(2) U-0 — R/W-1 R/W-0(2) R/W-1 — U-0 — U-0 — bit 0 SOSCDRV SOSCGO(3) SOSCRUN Unimplemented: Read as ‘0’ SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator other than SOSC Unimplemented: Read as ‘0’ SOSCDRV: SOSC Drive Control bit 1 = T1OSC/SOSC oscillator drive circuit is selected by Configuration bits, CONFIG2L 0 = Low-power T1OSC/SOSC circuit is selected SOSCGO: Oscillator Start Control bit(3) 1 = Turns on the oscillator, even if no peripherals are requesting it 0 = Oscillator is shut off unless peripherals are requesting it Reserved: Maintain as ‘1’ Unimplemented: Read as ‘0’ Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. Default output frequency of INTOSC on Reset (4 MHz). When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect. bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3:  2010 Microchip Technology Inc. Preliminary DS39974A-page 43 PIC18F47J13 FAMILY 3.4 Reference Clock Output In addition to the peripheral clock/4 output in certain oscillator modes, the device clock in the PIC18F47J13 family can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 3-4). Setting the ROON bit (REFOCON) makes the clock signal available on the REFO (RB2) pin. The RODIV bits enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator is on OSC1 and OSC2, or the current system clock source is used for the reference clock output. The ROSSLP bit determines if the reference source is available on RB2 when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for an EC or HS mode; otherwise, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. REGISTER 3-4: R/W-0 ROON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER (BANKED F3Dh) U-0 — R/W-0 ROSSLP R/W-0 ROSEL R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ROON: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled Unimplemented: Read as ‘0’ ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator crystal/resonator is used as the base clock(1) 0 = System clock (FOSC) is used as the base clock; the base clock reflects any clock switching of the device RODIV: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value The crystal oscillator must be enabled using the FOSC bits; the crystal maintains the operation in Sleep mode. bit 6 bit 5 bit 4 bit 3-0 Note 1: DS39974A-page 44 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 3.5 Effects of Power-Managed Modes on Various Clock Sources 3.6 Power-up Delays Power-up delays are controlled by two timers so that no external Reset circuitry is required for most applications. The delays ensure that the device is kept in Reset until the device power supply is stable under normal circumstances and the primary clock is operating and stable. For additional information on power-up delays, see Section 5.6 “Power-up Timer (PWRT)”. The first timer is the Power-up Timer (PWRT), which provides a fixed delay on power-up (parameter 33, Table 30-14). The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS mode). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device. There is a delay of interval, TCSD (parameter 38, Table 30-14), following POR, while the controller becomes ready to execute instructions. This delay runs concurrently with any other delays. This may be the only delay that occurs when any of the internal oscillator or EC modes are used as the primary clock source. When the PRI_IDLE mode is selected, the designated primary oscillator continues to run without interruption. For all other power-managed modes, the oscillator using the OSC1 pin is disabled. In secondary clock modes (SEC_RUN and SEC_IDLE), the Timer1 oscillator is operating and providing the device clock. The Timer1 oscillator may also run in all power-managed modes if required to clock Timer1, Timer3 or Timer5. In internal oscillator modes (RC_RUN and RC_IDLE), the internal oscillator block provides the device clock source. The 31 kHz INTRC output can be used directly to provide the clock and may be enabled to support various special features regardless of the power-managed mode (see Section 27.2 “Watchdog Timer (WDT)”, Section 27.4 “Two-Speed Start-up” and Section 27.5 “Fail-Safe Clock Monitor” for more information on WDT, FSCM and Two-Speed Start-up). The INTOSC output at 8 MHz may be used directly to clock the device or may be divided down by the postscaler. The INTOSC output is disabled if the clock is provided directly from the INTRC output. If Sleep mode is selected, all clock sources which are no longer required are stopped. Since all the transistor switching currents have been stopped, Sleep mode achieves the lowest current consumption of the device (only leakage currents) outside of Deep Sleep. Enabling any on-chip feature that will operate during Sleep mode increases the current consumed during Sleep mode. The INTRC is required to support WDT operation. The Timer1 oscillator may be operating to support an RTC. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PMP, INTx pins, etc.). Peripherals that may add significant current consumption are listed in Section 30.2 “DC Characteristics: Power-Down and Supply Current PIC18F47J13 Family (Industrial)”.  2010 Microchip Technology Inc. Preliminary DS39974A-page 45 PIC18F47J13 FAMILY NOTES: DS39974A-page 46 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.0 LOW-POWER MODES The PIC18F47J13 family devices can manage power consumption through clocking to the CPU and the peripherals. In general, reducing the clock frequency and number of circuits being clocked reduces power consumption. For managing power in an application, the primary modes of operation are: • • • • Run Mode Idle Mode Sleep Mode Deep Sleep Mode The IDLEN bit (OSCCON) controls CPU clocking and the SCS bits (OSCCON) select the clock source. The individual modes, bit settings, clock sources and affected modules are summarized in Table 4-1. 4.1.1 CLOCK SOURCES The SCS bits allow the selection of one of three clock sources for power-managed modes. They are: • Primary clock source – Defined by the FOSC Configuration bits • Timer1 clock – Provided by the secondary oscillator • Postscaled internal clock – Derived from the internal oscillator block Additionally, there is an Ultra Low-Power Wake-up (ULPWU) mode for generating an interrupt-on-change on RA0. These modes define which portions of the device are clocked and at what speed. • The Run and Idle modes can use any of the three available clock sources (primary, secondary or internal oscillator blocks). • The Sleep mode does not use a clock source. The ULPWU mode on RA0 allows a slow falling voltage to generate an interrupt-on-change on RA0 without excess current consumption. See Section 4.7 “Ultra Low-Power Wake-up”. The power-managed modes include several power-saving features offered on previous PIC® devices, such as clock switching, ULPWU and Sleep mode. In addition, the PIC18F47J13 family devices have added a new power-managed Deep Sleep mode. 4.1.2 ENTERING POWER-MANAGED MODES Switching from one clock source to another begins by loading the OSCCON register. The SCS bits select the clock source. Changing these bits causes an immediate switch to the new clock source, assuming that it is running. The switch also may be subject to clock transition delays. These delays are discussed in Section 4.1.3 “Clock Transitions and Status Indicators” and subsequent sections. Entry to the power-managed Idle or Sleep modes is triggered by the execution of a SLEEP instruction. The actual mode that results depends on the status of the IDLEN bit. Depending on the current mode and the mode being switched to, a change to a power-managed mode does not always require setting all of these bits. Many transitions may be done by changing the oscillator select bits, the IDLEN bit or the DSEN bit prior to issuing a SLEEP instruction. If the IDLEN and DSEN bits are already configured correctly, it may only be necessary to perform a SLEEP instruction to switch to the desired mode. 4.1 Selecting Power-Managed Modes Selecting a power-managed mode requires these decisions: • Will the CPU be clocked? • If so, which clock source will be used?  2010 Microchip Technology Inc. Preliminary DS39974A-page 47 PIC18F47J13 FAMILY TABLE 4-1: Mode Sleep Deep Sleep(3) PRI_RUN SEC_RUN RC_RUN PRI_IDLE SEC_IDLE RC_IDLE Note 1: 2: 3: LOW-POWER MODES OSCCON IDLEN(1) SCS 0 0 N/A N/A N/A 1 1 1 N/A N/A 00 01 11 00 01 11 Module Clocking Available Clock and Oscillator Source CPU Off Powered off(2) Clocked Clocked Clocked Off Off Off Peripherals Off Timer1 oscillator and/or RTCC may optionally be enabled DSEN(1) 0 1 0 0 0 0 0 0 DSCONH Powered off RTCC can run uninterrupted using the Timer1 or internal low-power RC oscillator Clocked Clocked Clocked Clocked Clocked Clocked The normal, full-power execution mode; primary clock source (defined by FOSC) Secondary – Timer1 oscillator Postscaled internal clock Primary clock source (defined by FOSC) Secondary – Timer1 oscillator Postscaled internal clock IDLEN and DSEN reflect their values when the SLEEP instruction is executed. Deep Sleep turns off the internal core voltage regulator to power down core logic. See Section 4.6 “Deep Sleep Mode” for more information. Deep Sleep mode is only available on “F” devices, not “LF” devices. 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS 4.1.4 MULTIPLE SLEEP COMMANDS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its status: OSTS (OSCCON) and SOSCRUN (OSCCON2). In general, only one of these bits will be set in a given power-managed mode. When the OSTS bit is set, the primary clock would be providing the device clock. When the SOSCRUN bit is set, the Timer1 oscillator would be providing the clock. If neither of these bits is set, INTRC would be clocking the device. Note: Executing a SLEEP instruction does not necessarily place the device into Sleep mode. It acts as the trigger to place the controller into either the Sleep or Deep Sleep mode, or one of the Idle modes, depending on the setting of the IDLEN bit. The power-managed mode that is invoked with the SLEEP instruction is determined by the setting of the IDLEN and DSEN bits at the time the instruction is executed. If another SLEEP instruction is executed, the device will enter the power-managed mode specified by IDLEN and DSEN at that time. If IDLEN or DSEN have changed, the device will enter the new power-managed mode specified by the new setting. DS39974A-page 48 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.2 Run Modes Note: In the Run modes, clocks to both the core and peripherals are active. The difference between these modes is the clock source. The Timer1 oscillator should already be running prior to entering SEC_RUN mode. If the T1OSCEN bit is not set when the SCS bits are set to ‘01’, entry to SEC_RUN mode will not occur. If the Timer1 oscillator is enabled, but not yet running, device clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 4.2.1 PRI_RUN MODE The PRI_RUN mode is the normal, full-power execution mode of the microcontroller. This is also the default mode upon a device Reset unless Two-Speed Start-up is enabled (see Section 27.4 “Two-Speed Start-up” for details). In this mode, the OSTS bit is set (see Section 3.3.1 “Oscillator Control Register”). 4.2.2 SEC_RUN MODE The SEC_RUN mode is the compatible mode to the “clock switching” feature offered in other PIC18 devices. In this mode, the CPU and peripherals are clocked from the Timer1 oscillator. This gives users the option of low-power consumption while still using a high-accuracy clock source. SEC_RUN mode is entered by setting the SCS bits to ‘01’. The device clock source is switched to the Timer1 oscillator (see Figure 4-1), the primary oscillator is shut down, the SOSCRUN bit (OSCCON2) is set and the OSTS bit is cleared. On transitions from SEC_RUN mode to PRI_RUN mode, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2). When the clock switch is complete, the SOSCRUN bit is cleared, the OSTS bit is set and the primary clock would be providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run. FIGURE 4-1: TRANSITION TIMING FOR ENTRY TO SEC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3 T1OSI OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-2: TRANSITION TIMING FROM SEC_RUN MODE TO PRI_RUN MODE (HSPLL) Q1 T1OSI OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS Bits Changed Clock Transition PC OSTS Bit Set PC + 2 PC + 4 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  2010 Microchip Technology Inc. Preliminary DS39974A-page 49 PIC18F47J13 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conservation of all the Run modes while still executing code. It works well for user applications, which are not highly timing-sensitive or do not require high-speed clocks at all times. This mode is entered by setting the SCS bits (OSCCON) to ‘11’. When the clock source is switched to the internal oscillator block (see Figure 4-3), the primary oscillator is shut down and the OSTS bit is cleared. On transitions from RC_RUN mode to PRI_RUN mode, the device continues to be clocked from the INTOSC block while the primary clock is started. When the primary clock becomes ready, a clock switch to the primary clock occurs (see Figure 4-4). When the clock switch is complete, the OSTS bit is set and the primary clock is providing the device clock. The IDLEN and SCS bits are not affected by the switch. The INTRC clock source will continue to run if either the WDT or the FSCM is enabled. FIGURE 4-3: TRANSITION TIMING TO RC_RUN MODE Q1 Q2 Q3 Q4 Q1 Q2 1 2 3 Clock Transition n-1 n Q3 Q4 Q1 Q2 Q3 INTRC OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 PC + 4 FIGURE 4-4: TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE Q1 INTRC OSC1 TOST(1) TPLL(1) 1 2 n-1 n Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 PLL Clock Output CPU Clock Peripheral Clock Program Counter SCS Bits Changed PC OSTS Bit Set Clock Transition PC + 2 PC + 4 Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale. DS39974A-page 50 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.3 Sleep Mode The power-managed Sleep mode is identical to the legacy Sleep mode offered in all other PIC devices. It is entered by clearing the IDLEN bit (the default state on device Reset) and executing the SLEEP instruction. This shuts down the selected oscillator (Figure 4-5). All clock source status bits are cleared. Entering the Sleep mode from any other mode does not require a clock switch. This is because no clocks are needed once the controller has entered Sleep mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. When a wake event occurs in Sleep mode (by interrupt, Reset or WDT time-out), the device will not be clocked until the clock source selected by the SCS bits becomes ready (see Figure 4-6), or it will be clocked from the internal oscillator if either the Two-Speed Start-up or the FSCM is enabled (see Section 27.0 “Special Features of the CPU”). In either case, the OSTS bit is set when the primary clock is providing the device clocks. The IDLEN and SCS bits are not affected by the wake-up. FIGURE 4-5: OSC1 CPU Clock Peripheral Clock Sleep Program Counter PC TRANSITION TIMING FOR ENTRY TO SLEEP MODE Q1 Q2 Q3 Q4 Q1 PC + 2 FIGURE 4-6: TRANSITION TIMING FOR WAKE FROM SLEEP (HSPLL) Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 PLL Clock Output CPU Clock Peripheral Clock Program Counter Wake Event PC OSTS Bit Set PC + 2 PC + 4 PC + 6 TOST(1) TPLL(1) Note 1: TOST = 1024 TOSC; TPLL = 2 ms (approx). These intervals are not shown to scale.  2010 Microchip Technology Inc. Preliminary DS39974A-page 51 PIC18F47J13 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to ‘1’ when a SLEEP instruction is executed, the peripherals will be clocked from the clock source selected using the SCS bits; however, the CPU will not be clocked. The clock source status bits are not affected. Setting IDLEN and executing a SLEEP instruction provides a quick method of switching from a given Run mode to its corresponding Idle mode. If the WDT is selected, the INTRC source will continue to operate. If the Timer1 oscillator is enabled, it will also continue to run. Since the CPU is not executing instructions, the only exits from any of the Idle modes are by interrupt, WDT time-out or a Reset. When a wake event occurs, CPU execution is delayed by an interval of TCSD (parameter 38, Table 30-14) while it becomes ready to execute code. When the CPU begins executing code, it resumes with the same clock source for the current Idle mode. For example, when waking from RC_IDLE mode, the internal oscillator block will clock the CPU and peripherals (in other words, RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle or Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS bits. When a wake event occurs, the CPU is clocked from the primary clock source. A delay of interval, TCSD, is required between the wake event and when code execution starts. This is required to allow the CPU to become ready to execute instructions. After the wake-up, the OSTS bit remains set. The IDLEN and SCS bits are not affected by the wake-up (see Figure 4-8). 4.4.2 SEC_IDLE MODE In SEC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the Timer1 oscillator. This mode is entered from SEC_RUN by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set SCS to ‘01’ and execute SLEEP. When the clock source is switched to the Timer1 oscillator, the primary oscillator is shut down, the OSTS bit is cleared and the SOSCRUN bit is set. When a wake event occurs, the peripherals continue to be clocked from the Timer1 oscillator. After an interval of TCSD following the wake event, the CPU begins executing code being clocked by the Timer1 oscillator. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run (see Figure 4-8). Note: The Timer1 oscillator should already be running prior to entering SEC_IDLE mode. If the T1OSCEN bit is not set when the SLEEP instruction is executed, the SLEEP instruction will be ignored and entry to SEC_IDLE mode will not occur. If the Timer1 oscillator is enabled, but not yet running, peripheral clocks will be delayed until the oscillator has started. In such situations, initial oscillator operation is far from stable and unpredictable operation may result. 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “warm up” or transition from another oscillator. PRI_IDLE mode is entered from PRI_RUN mode by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, set IDLEN first, then set the SCS bits to ‘00’ and execute SLEEP. Although the CPU is disabled, the peripherals continue to be clocked from the primary clock source specified by the FOSC Configuration bits. The OSTS bit remains set (see Figure 4-7). DS39974A-page 52 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 4-7: TRANSITION TIMING FOR ENTRY TO IDLE MODE Q1 OSC1 CPU Clock Peripheral Clock Program Counter PC PC + 2 Q2 Q3 Q4 Q1 FIGURE 4-8: TRANSITION TIMING FOR WAKE FROM IDLE TO RUN MODE Q1 Q2 Q3 Q4 OSC1 CPU Clock Peripheral Clock Program Counter Wake Event PC TCSD  2010 Microchip Technology Inc. Preliminary DS39974A-page 53 PIC18F47J13 FAMILY 4.4.3 RC_IDLE MODE In RC_IDLE mode, the CPU is disabled but the peripherals continue to be clocked from the internal oscillator block. This mode allows for controllable power conservation during Idle periods. From RC_RUN, this mode is entered by setting the IDLEN bit and executing a SLEEP instruction. If the device is in another Run mode, first set IDLEN, then clear the SCS bits and execute SLEEP. When the clock source is switched to the INTOSC block, the primary oscillator is shut down and the OSTS bit is cleared. When a wake event occurs, the peripherals continue to be clocked from the internal oscillator block. After a delay of TCSD, following the wake event, the CPU begins executing code being clocked by the INTRC. The IDLEN and SCS bits are not affected by the wake-up. The INTRC source will continue to run if either the WDT or the FSCM is enabled. On all exits from Idle or Sleep modes by interrupt, code execution branches to the interrupt vector if the GIE/GIEH bit (INTCON) is set. Otherwise, code execution continues or resumes without branching (see Section 9.0 “Interrupts”). A fixed delay of interval, TCSD, following the wake event, is required when leaving Sleep mode. This delay is required for the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is, when the time-out occurs. If the device is not executing code (all Idle modes and Sleep mode), the time-out will result in an exit from the power-managed mode (see Section 4.2 “Run Modes” and Section 4.3 “Sleep Mode”). If the device is executing code (all Run modes), the time-out will result in a WDT Reset (see Section 27.2 “Watchdog Timer (WDT)”). The WDT and postscaler are cleared by one of the following events: • Executing a SLEEP or CLRWDT instruction • The loss of a currently selected clock source (if the FSCM is enabled) 4.5 Exiting Idle and Sleep Modes An exit from Sleep mode, or any of the Idle modes, is triggered by an interrupt, a Reset or a WDT time-out. This section discusses the triggers that cause exits from power-managed modes. The clocking subsystem actions are discussed in each of the power-managed modes sections (see Section 4.2 “Run Modes”, Section 4.3 “Sleep Mode” and Section 4.4 “Idle Modes”). 4.5.3 EXIT BY RESET 4.5.1 EXIT BY INTERRUPT Any of the available interrupt sources can cause the device to exit from an Idle mode, or the Sleep mode, to a Run mode. To enable this functionality, an interrupt source must be enabled by setting its enable bit in one of the INTCON or PIE registers. The exit sequence is initiated when the corresponding interrupt flag bit is set. Exiting an Idle or Sleep mode by Reset automatically forces the device to run from the INTRC. DS39974A-page 54 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.5.4 EXIT WITHOUT AN OSCILLATOR START-UP DELAY Certain exits from power-managed modes do not invoke the OST at all. There are two cases: • PRI_IDLE mode (where the primary clock source is not stopped) and the primary clock source is the EC mode • PRI_IDLE mode and the primary clock source is the ECPLL mode In these instances, the primary clock source either does not require an oscillator start-up delay, since it is already running (PRI_IDLE), or normally does not require an oscillator start-up delay (EC). However, a fixed delay of interval, TCSD, following the wake event, is still required when leaving Sleep and Idle modes to allow the CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. In order to minimize the possibility of inadvertently entering Deep Sleep, the DSEN bit is cleared in hardware two instruction cycles after having been set. Therefore, in order to enter Deep Sleep, the SLEEP instruction must be executed in the immediate instruction cycle after setting DSEN. If DSEN is not set when SLEEP is executed, the device will enter conventional Sleep mode instead. During Deep Sleep, the core logic circuitry of the microcontroller is powered down to reduce leakage current. Therefore, most peripherals and functions of the microcontroller become unavailable during Deep Sleep. However, a few specific peripherals and functions are powered directly from the VDD supply rail of the microcontroller, and therefore, can continue to function in Deep Sleep. Entering Deep Sleep mode clears the DSWAKEL register. However, if the Real-Time Clock and Calendar (RTCC) is enabled prior to entering Deep Sleep, it will continue to operate uninterrupted. The device has a dedicated Brown-out Reset (DSBOR) and Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events in Deep Sleep. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Run, Idle and Sleep). When a wake event occurs in Deep Sleep mode (by MCLR Reset, RTCC alarm, INT0 interrupt, ULPWU or DSWDT), the device will exit Deep Sleep mode and perform a Power-on Reset (POR). When the device is released from Reset, code execution will resume at the device’s Reset vector. 4.6 Deep Sleep Mode Deep Sleep mode brings the device into its lowest power consumption state without requiring the use of external switches to remove power from the device. During Deep Sleep, the on-chip VDDCORE voltage regulator is powered down, effectively disconnecting power to the core logic of the microcontroller. Note: Since Deep Sleep mode powers down the microcontroller by turning off the on-chip VDDCORE voltage regulator, Deep Sleep capability is available only on PIC18FXXJ members in the device family. The on-chip voltage regulator is not available in PIC18LFXXJ members of the device family, and therefore, they do not support Deep Sleep. 4.6.1 PREPARING FOR DEEP SLEEP On devices that support it, the Deep Sleep mode is entered by: • • • • • • Setting the REGSLP (WDTCON) bit Clearing the IDLEN bit Clearing the GIE bit Setting the DSEN bit (DSCONH) Executing one single-cycle NOP instruction Executing the SLEEP instruction immediately after setting DSEN and the single NOP (no interrupts in between) Because VDDCORE could fall below the SRAM retention voltage while in Deep Sleep mode, SRAM data could be lost in Deep Sleep. Exiting Deep Sleep mode causes a POR; as a result, most Special Function Registers will reset to their default POR values. Applications needing to save a small amount of data throughout a Deep Sleep cycle can save the data to the general purpose DSGPR0 and DSGPR1 registers. The contents of these registers are preserved while the device is in Deep Sleep, and will remain valid throughout an entire Deep Sleep entry and wake-up sequence.  2010 Microchip Technology Inc. Preliminary DS39974A-page 55 PIC18F47J13 FAMILY 4.6.2 I/O PINS DURING DEEP SLEEP 4.6.3 DEEP SLEEP WAKE-UP SOURCES During Deep Sleep, the general purpose I/O pins will retain their previous states. Pins that are configured as inputs (TRISx bit set) prior to entry into Deep Sleep will remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRISx bit clear) prior to entry into Deep Sleep will remain as output pins during Deep Sleep. While in this mode, they will drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep. When the device wakes back up, the I/O pin behavior depends on the type of wake up source. If the device wakes back up by an RTCC alarm, INT0 interrupt, DSWDT or ULPWU event, all I/O pins will continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep will remain high-impedance, and pins configured as outputs will continue to drive their previous value. After waking up, the TRIS and LAT registers will be reset, but the I/O pins will still maintain their previous states. If firmware modifies the TRIS and LAT values for the I/O pins, they will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCONL), the I/O pins will be “released”. This causes the I/O pins to take the states configured by their respective TRIS and LAT bit values. If the Deep Sleep BOR (DSBOR) circuit is enabled, and VDD drops below the DSBOR and VDD rail POR thresholds, the I/O pins will be immediately released similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. See Section 4.6.5 “Deep Sleep Brown-out Reset (DSBOR)” for additional details regarding this scenario. If a MCLR Reset event occurs during Deep Sleep, the I/O pins will also be released automatically, but in this case, the DSGPR0 and DSGPR1 contents will remain valid. In all other Deep Sleep wake-up cases, application firmware needs to clear the RELEASE bit in order to reconfigure the I/O pins. The device can be awakened from Deep Sleep mode by a MCLR, POR, RTCC, INT0 I/O pin interrupt, DSWDT or ULPWU event. After waking, the device performs a POR. When the device is released from Reset, code execution will begin at the device’s Reset vector. The software can determine if the wake-up was caused from an exit from Deep Sleep mode by reading the DS bit (WDTCON). If this bit is set, the POR was caused by a Deep Sleep exit. The DS bit must be manually cleared by the software. The software can determine the wake event source by reading the DSWAKEH and DSWAKEL registers. When the application firmware is done using the DSWAKEH and DSWAKEL status registers, individual bits do not need to be manually cleared before entering Deep Sleep again. When entering Deep Sleep mode, these registers are automatically cleared. 4.6.3.1 Wake-up Event Considerations Deep Sleep wake-up events are only monitored while the processor is fully in Deep Sleep mode. If a wake-up event occurs before Deep Sleep mode is entered, the event status will not be reflected in the DSWAKE registers. If the wake-up source asserts prior to entering Deep Sleep, the CPU will either go to the interrupt vector (if the wake source has an interrupt bit and the interrupt is fully enabled) or will abort the Deep Sleep entry sequence by executing past the SLEEP instruction, if the interrupt was not enabled. In this case, a wake-up event handler should be placed after the SLEEP instruction to process the event and re-attempt entry into Deep Sleep if desired. When the device is in Deep Sleep with more than one wake-up source simultaneously enabled, only the first wake-up source to assert will be detected and logged in the DSWAKEH/DSWAKEL status registers. 4.6.4 DEEP SLEEP WATCHDOG TIMER (DSWDT) Deep Sleep has its own dedicated WDT (DSWDT) with a postscaler for time-outs of 2.1 ms to 25.7 days, configurable through the bits, DSWDTPS. The DSWDT can be clocked from either the INTRC or the T1OSC/T1CKI input. If the T1OSC/T1CKI source will be used with a crystal, the T1OSCEN bit in the T1CON register needs to be set prior to entering Deep Sleep. The reference clock source is configured through the DSWDTOSC bit. DSWDT is enabled through the DSWDTEN bit. Entering Deep Sleep mode automatically clears the DSWDT. See Section 27.0 “Special Features of the CPU” for more information. DS39974A-page 56 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.6.5 DEEP SLEEP BROWN-OUT RESET (DSBOR) The Deep Sleep module contains a dedicated Deep Sleep BOR (DSBOR) circuit. This circuit may be optionally enabled through the DSBOREN Configuration bit. The DSBOR circuit monitors the VDD supply rail voltage. The behavior of the DSBOR circuit is described in Section 5.4 “Brown-out Reset (BOR)”. 14. Clear the Deep Sleep bit, DS (WDTCON). 15. Determine the wake-up source by reading the DSWAKEH and DSWAKEL registers. 16. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCONL). 17. Read the DSGPR0 and DSGPR1 context save registers (optional). 18. Clear the RELEASE bit (DSCONL). Note 1: DSWDT and DSBOR are enabled through the devices’ Configuration bits. For more information, see Section 27.1 “Configuration Bits”. 2: The DSWDT and RTCC clock sources are selected through the devices’ Configuration bits. For more information, see Section 27.1 “Configuration Bits”. 3: For more information, see Section 17.0 “Real-Time Clock and Calendar (RTCC)”. 4: For more information on configuring this peripheral, see Section 4.7 “Ultra Low-Power Wake-up”. 4.6.6 RTCC PERIPHERAL AND DEEP SLEEP The RTCC can operate uninterrupted during Deep Sleep mode. It can wake the device from Deep Sleep by configuring an alarm. The RTCC clock source is configured with the RTCOSC bit (CONFIG3L). The available reference clock sources are the INTRC and T1OSC/T1CKI. If the INTRC is used, the RTCC accuracy will directly depend on the INTRC tolerance. For more information on configuring the RTCC peripheral, see Section 17.0 “Real-Time Clock and Calendar (RTCC)”. 4.6.7 TYPICAL DEEP SLEEP SEQUENCE This section gives the typical sequence for using the Deep Sleep mode. Optional steps are indicated and additional information is given in notes at the end of the procedure. 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. Enable DSWDT (optional). Configure the DSWDT clock source (optional).(2) Enable DSBOR (optional).(1) Enable RTCC (optional).(3) Configure the RTCC peripheral (optional).(3) Configure the ULPWU peripheral (optional).(4) Enable the INT0 Interrupt (optional). Context save SRAM data by writing to the DSGPR0 and DSGPR1 registers (optional). Set the REGSLP bit (WDTCON) and clear the IDLEN bit (OSCCON). If using an RTCC alarm for wake-up, wait until the RTCSYNC bit (RTCCFG) is clear. Enter Deep Sleep mode by setting the DSEN bit (DSCONH), execute a NOP and issue a SLEEP instruction. The SLEEP instruction must be executed within 2 instruction cycles of setting the DSEN bit. Once a wake-up event occurs, the device will perform a POR Reset sequence. Code execution resumes at the device’s Reset vector. Determine if the device exited Deep Sleep by reading the Deep Sleep bit, DS (WDTCON). This bit will be set if there was an exit from Deep Sleep mode. (1) 4.6.8 DEEP SLEEP FAULT DETECTION If during Deep Sleep, the device is subjected to unusual operating conditions, such as an Electrostatic Discharge (ESD) event, it is possible that internal circuit states used by the Deep Sleep module could become corrupted. If this were to happen, the device may exhibit unexpected behavior, such as a failure to wake back up. In order to prevent this type of scenario from occurring, the Deep Sleep module includes automatic self-monitoring capability. During Deep Sleep, critical internal nodes are continuously monitored in order to detect possible Fault conditions (which would not ordinarily occur). If a Fault condition is detected, the circuitry will set the DSFLT status bit (DSWAKEL) and automatically wake the microcontroller from Deep Sleep, causing a POR Reset. During Deep Sleep, the Fault detection circuitry is always enabled and does not require any specific configuration prior to entering Deep Sleep. 12. 13.  2010 Microchip Technology Inc. Preliminary DS39974A-page 57 PIC18F47J13 FAMILY 4.6.9 DEEP SLEEP MODE REGISTERS provided in Deep Sleep mode registers are Register 4-1 through Register 4-6. REGISTER 4-1: R/W-0 DSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 (1) DSCONH: DEEP SLEEP CONTROL HIGH BYTE REGISTER (BANKED F4Dh) U-0 — U-0 — U-0 — U-0 — R/W-0 r R/W-0 DSULPEN R/W-0 RTCWDIS bit 0 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DSEN: Deep Sleep Enable bit(1) 1 = Deep Sleep mode is entered on a SLEEP command 0 = Sleep mode is entered on a SLEEP command Unimplemented: Read as ‘0’ Reserved: Maintain as ‘0’ DSULPEN: Ultra Low-Power Wake-up Module Enable bit 1 = ULPWU module is enabled in Deep Sleep 0 = ULPWU module is disabled in Deep Sleep RTCWDIS: RTCC Wake-up Disable bit 1 = Wake-up from RTCC is disabled 0 = Wake-up from RTCC is enabled In order to enter Deep Sleep, Sleep must be executed within 2 instruction cycles after setting DSEN. bit 6-3 bit 2 bit 1 bit 0 Note 1: REGISTER 4-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2 DSCONL: DEEP SLEEP LOW BYTE CONTROL REGISTER (BANKED F4Ch) U-0 — U-0 — U-0 — U-0 — R/W-0 ULPWDIS R/W-0(1) DSBOR R/W-0(1) RELEASE bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ ULPWDIS: Ultra Low-Power Wake-up Disable bit 1 = ULPWU wake-up source is disabled 0 = ULPWU wake-up source is enabled (must also set DSULPEN = 1) DSBOR: Deep Sleep BOR Event Status bit 1 = DSBOREN was enabled and VDD dropped below the DSBOR arming voltage during Deep Sleep, but did not fall below VDSBOR 0 = DSBOREN was disabled or VDD did not drop below the DSBOR arming voltage during Deep Sleep RELEASE: I/O Pin State Release bit Upon waking from Deep Sleep, the I/O pins maintain their previous states. Clearing this bit will release the I/O pins and allow their respective TRIS and LAT bits to control their states. This is the value when VDD is initially applied. bit 1 bit 0 Note 1: DS39974A-page 58 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 4-3: DSGPR0: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 0 (BANKED F4Eh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. All register bits are maintained unless VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS. Note 1: REGISTER 4-4: DSGPR1: DEEP SLEEP PERSISTENT GENERAL PURPOSE REGISTER 1 (BANKED F4Fh) R/W-xxxx(1) Deep Sleep Persistent General Purpose bits bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 0 Deep Sleep Persistent General Purpose bits Contents are retained even in Deep Sleep mode. All register bits are maintained unless VDDCORE drops below the normal BOR threshold outside of Deep Sleep, or the device is in Deep Sleep and the dedicated DSBOR is enabled and VDD drops below the DSBOR threshold, or DSBOR is enabled or disabled, but VDD is hard cycled to near VSS. Note 1: REGISTER 4-5: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 DSWAKEH: DEEP SLEEP WAKE HIGH BYTE REGISTER (BANKED F4Bh) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DSINT0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DSINT0: Interrupt-on-Change bit 1 = Interrupt-on-change was asserted during Deep Sleep 0 = Interrupt-on-change was not asserted during Deep Sleep  2010 Microchip Technology Inc. Preliminary DS39974A-page 59 PIC18F47J13 FAMILY REGISTER 4-6: R/W-0 DSFLT bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DSWAKEL: DEEP SLEEP WAKE LOW BYTE REGISTER (BANKED F4Ah) U-0 — R/W-0 DSULP R/W-0 DSWDT R/W-0 DSRTC R/W-0 DSMCLR U-0 — R/W-1 DSPOR bit 0 DSFLT: Deep Sleep Fault Detected bit 1 = A Deep Sleep Fault was detected during Deep Sleep 0 = A Deep Sleep Fault was not detected during Deep Sleep Unimplemented: Read as ‘0’ DSULP: Ultra Low-Power Wake-up Status bit 1 = An ultra low-power wake-up event occurred during Deep Sleep 0 = An ultra low-power wake-up event did not occur during Deep Sleep DSWDT: Deep Sleep Watchdog Timer Time-out bit 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep DSRTC: Real-Time Clock and Calendar Alarm bit 1 = The Real-Time Clock/Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock /Calendar did not trigger an alarm during Deep Sleep DSMCLR: MCLR Event bit 1 = The MCLR pin was asserted during Deep Sleep 0 = The MCLR pin was not asserted during Deep Sleep Unimplemented: Read as ‘0’ DSPOR: Power-on Reset Event bit 1 = The VDD supply POR circuit was active and a POR event was detected(1) 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event Unlike the other bits in this register, this bit can be set outside of Deep Sleep. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39974A-page 60 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 4.7 Ultra Low-Power Wake-up The Ultra Low-Power Wake-up (ULPWU) on RA0 allows a slow falling voltage to generate an interrupt-on-change without excess current consumption. Follow these steps to use this feature: 1. 2. Configure a remappable output pin to output the ULPOUT signal. Map an INTx interrupt-on-change input function to the same pin as used for the ULPOUT output function. Alternatively, in Step 1, configure ULPOUT to output onto a PORTB interrupt-on-change pin. Charge the capacitor on RA0 by configuring the RA0 pin to an output and setting it to ‘1’. Enable interrupt-on-change (PIE bit) for the corresponding pin selected in Step 2. Stop charging the capacitor by configuring RA0 as an input. Discharge the capacitor by setting the ULPEN and ULPSINK bits in the WDTCON register. Configure Sleep mode. Enter Sleep mode. When the voltage on RA0 drops below VIL, an interrupt will be generated, which will cause the device to wake-up and execute the next instruction. This feature provides a low-power technique for periodically waking up the device from Sleep mode. The time-out is dependent on the discharge time of the RC circuit on RA0. When the ULPWU module causes the device to wake-up from Sleep mode, the ULPLVL (WDTCON) bit is set. When the ULPWU module causes the device to wake-up from Deep Sleep, the DSULP (DSWAKEL) bit is set. Software can check these bits upon wake-up to determine the wake-up source. Also in Sleep mode, only the remappable output function, ULPWU, will output this bit value to an RPn pin for externally detecting wake-up events. See Example 4-1 for initializing the ULPWU module. Note: For module related bit definitions, see the WDTCON register in Section 27.2 “Watchdog Timer (WDT)” and the DSWAKEL register (Register 4-6). 3. 4. 5. 6. 7. 8.  2010 Microchip Technology Inc. Preliminary DS39974A-page 61 PIC18F47J13 FAMILY EXAMPLE 4-1: ULTRA LOW-POWER WAKE-UP INITIALIZATION //********************************************************************************* //Configure a remappable output pin with interrupt capability //for ULPWU function (RP21 => RD4/INT1 in this example) //********************************************************************************* RPOR21 = 13;// ULPWU function mapped to RP21/RD4 RPINR1 = 21;// INT1 mapped to RP21 (RD4) //*************************** //Charge the capacitor on RA0 //*************************** TRISAbits.TRISA0 = 0; PORTAbits.RA0 = 1; for(i = 0; i < 10000; i++) Nop(); //********************************** //Stop Charging the capacitor on RA0 //********************************** TRISAbits.TRISA0 = 1; //***************************************** //Enable the Ultra Low Power Wakeup module //and allow capacitor discharge //***************************************** WDTCONbits.ULPEN = 1; WDTCONbits.ULPSINK = 1; //****************************************** //Enable Interrupt for ULPW //****************************************** //For Sleep //(assign the ULPOUT signal in the PPS module to a pin //which has also been assigned an interrupt capability, //such as INT1) INTCON3bits.INT1IF = 0; INTCON3bits.INT1IE = 1; //******************** //Configure Sleep Mode //******************** //For Sleep OSCCONbits.IDLEN = 0; //For Deep Sleep OSCCONbits.IDLEN = 0; // enable deep sleep DSCONHbits.DSEN = 1; // Note: must be set just before executing Sleep(); //**************** //Enter Sleep Mode //**************** Sleep(); // for sleep, execution will resume here // for deep sleep, execution will restart at reset vector (use WDTCONbits.DS to detect) DS39974A-page 62 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY A series resistor between RA0 and the external capacitor provides overcurrent protection for the RA0/AN0/C1INA/ULPWU/RP0 pin and can allow for software calibration of the time-out (see Figure 4-9). 4.8 Peripheral Module Disable FIGURE 4-9: RA0 SERIAL RESISTOR R1 All peripheral modules (except for I/O ports) also have a second control bit that can disable their functionality. These bits, known as the Peripheral Module Disable (PMD) bits, are generically named “xxxMD” (using “xxx” as the mnemonic version of the module’s name). These bits are located in the PMDISx special function registers. In contrast to the module enable bits (generically named “xxxEN” and located in bit position seven of the control registers), the PMD bits must be set (= 1) to disable the modules. While the PMD and module enable bits both disable a peripheral’s functionality, the PMD bit completely shuts down the peripheral, effectively powering down all circuits and removing all clock sources. This has the additional effect of making any of the module’s control and buffer registers, mapped in the SFR space, unavailable for operations. Essentially, the peripheral ceases to exist until the PMD bit is cleared. This differs from using the module enable bit, which allows the peripheral to be reconfigured and buffer registers preloaded, even when the peripheral’s operations are disabled. The PMD bits are most useful in highly power-sensitive applications. In these cases, the bits can be set before the main body of the application to remove peripherals that will not be needed at all. C1 A timer can be used to measure the charge time and discharge time of the capacitor. The charge time can then be adjusted to provide the desired interrupt delay. This technique will compensate for the affects of temperature, voltage and component accuracy. The ULPWU peripheral can also be configured as a simple Programmable Low-Voltage Detect (LVD) or temperature sensor. Note: For more information, refer to AN879, “Using the Microchip Ultra Low-Power Wake-up Module” application note (DS00879). TABLE 4-2: Register PMDIS3 PMDIS2 PMDIS1 PMDIS0 Note 1: 2: Bit 7 LOW-POWER MODE REGISTERS Bit 6 CCP9MD TMR8MD CTMUMD ECCP2MD Bit 5 CCP8MD — RTCCMD(2) ECCP1MD Bit 4 CCP7MD TMR6MD TMR4MD UART2MD Bit 3 CCP6MD TMR5MD TMR3MD UART1MD Bit 2 CCP5MD CMP3MD TMR2MD SPI2MD Bit 1 CCP4MD CMP2MD TMR1MD SP11MD Bit 0 — CMP1MD — ADCMD Value on POR, BOR 0000 000– –0–0 0000 0000 000– 0000 0000 CCP10MD — PSPMD(1) ECCP3MD Not implemented on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). To prevent accidental RTCC changes, the RTCCMD bit is normally locked. Use the following unlock sequence (with interrupts disabled) to successfully modify the RTCCMD bit: 1. Write 55h to EECON2. 2. Write 0AAh to EECON2. 3. Immediately write the modified RTCCMD setting to PMDIS1.  2010 Microchip Technology Inc. Preliminary DS39974A-page 63 PIC18F47J13 FAMILY NOTES: DS39974A-page 64 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 5.0 RESET The PIC18F47J13 family of devices differentiates among various kinds of Reset: a) b) c) d) e) f) g) h) i) j) Power-on Reset (POR) MCLR Reset during normal operation MCLR Reset during power-managed modes Watchdog Timer (WDT) Reset (during execution) Configuration Mismatch (CM) Brown-out Reset (BOR) RESET Instruction Stack Full Reset Stack Underflow Reset Deep Sleep Reset For information on WDT Resets, see Section 27.2 “Watchdog Timer (WDT)”. For Stack Reset events, see Section 6.1.4.4 “Stack Full and Underflow Resets” and for Deep Sleep mode, see Section 4.6 “Deep Sleep Mode”. Figure 5-1 provides a simplified block diagram of the on-chip Reset circuit. 5.1 RCON Register This section discusses Resets generated by MCLR, POR and BOR, and covers the operation of the various start-up timers. Device Reset events are tracked through the RCON register (Register 5-1). The lower five bits of the register indicate that a specific Reset event has occurred. In most cases, these bits can only be set by the event and must be cleared by the application after the event. The state of these flag bits, taken together, can be read to indicate the type of Reset that just occurred. This is described in more detail in Section 5.7 “Reset State of Registers”. The RCON register also has a control bit for setting interrupt priority (IPEN). Interrupt priority is discussed in Section 9.0 “Interrupts”. FIGURE 5-1: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT RESET Instruction Configuration Word Mismatch Stack Full/Underflow Reset Stack Pointer External Reset MCLR ( )_IDLE Deep Sleep Reset Sleep WDT Time-out VDD Rise Detect VDD Brown-out Reset(1) Brown-out Reset(2) S POR Pulse VDDCORE PWRT PWRT INTRC F: 4-Bit Ripple Counter LF: 11-Bit Ripple Counter R Q Chip_Reset Note 1: The VDD monitoring BOR circuit can be enabled or disabled on “LF” devices based on the CONFIG3L Configuration bit. On “F” devices, the VDD monitoring BOR circuit is only enabled during Deep Sleep mode by CONFIG3L. The VDDCORE monitoring BOR circuit is only implemented on “F” devices. It is always used, except while in Deep Sleep mode. The VDDCORE monitoring BOR circuit has a trip point threshold of VBOR (parameter D005). 2:  2010 Microchip Technology Inc. Preliminary DS39974A-page 65 PIC18F47J13 FAMILY REGISTER 5-1: R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RCON: RESET CONTROL REGISTER (ACCESS FD0h) U-0 — R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as ‘0’ CM: Configuration Mismatch Flag bit 1 = A Configuration Mismatch Reset has not occurred 0 = A Configuration Mismatch Reset has occurred (must be set in software after a Configuration Mismatch Reset occurs) RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) 0 = The RESET instruction was executed causing a device Reset (must be set in software after a Brown-out Reset occurs) TO: Watchdog Time-out Flag bit 1 = Set by power-up, CLRWDT instruction or SLEEP instruction 0 = A WDT time-out occurred PD: Power-Down Detection Flag bit 1 = Set by power-up or by the CLRWDT instruction 0 = Set by execution of the SLEEP instruction POR: Power-on Reset Status bit 1 = A Power-on Reset has not occurred (set by firmware only) 0 = A Power-on Reset occurred (must be set in software after a Power-on Reset occurs) BOR: Brown-out Reset Status bit 1 = A Brown-out Reset has not occurred (set by firmware only) 0 = A Brown-out Reset occurred (must be set in software after a Brown-out Reset occurs) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: It is recommended that the POR bit be set after a Power-on Reset has been detected, so that subsequent Power-on Resets may be detected. 2: If the on-chip voltage regulator is disabled, BOR remains ‘0’ at all times. See Section 5.4.1 “Detecting BOR” for more information. 3: Brown-out Reset is said to have occurred when BOR is ‘0’ and POR is ‘1’ (assuming that POR was set to ‘1’ by software immediately after a Power-on Reset). DS39974A-page 66 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 5.2 Master Clear (MCLR) The Master Clear Reset (MCLR) pin provides a method for triggering a hard external Reset of the device. A Reset is generated by holding the pin low. PIC18 extended microcontroller devices have a noise filter in the MCLR Reset path, which detects and ignores small pulses. The MCLR pin is not driven low by any internal Resets, including the WDT. If VDD drops below the VDSBOR threshold, the device will be held in a Reset state similar to POR. All registers will be set back to their POR Reset values and the contents of the DSGPR0 and DSGPR1 holding registers will be lost. Additionally, if any I/O pins had been configured as outputs during Deep Sleep, these pins will be tri-stated and the device will no longer be held in Deep Sleep. Once the VDD voltage recovers back above the VDSBOR threshold, and once the core voltage regulator achieves a VDDCORE voltage above VBOR, the device will begin executing code again normally, but the DS bit in the WDTCON register will not be set. The device behavior will be similar to hard cycling all power to the device. On “LF” devices (ex: PIC18LF47J13), the VDDCORE BOR circuit is always disabled because the internal core voltage regulator is disabled. Instead of monitoring VDDCORE, PIC18LF devices in this family can still use the VDD BOR circuit to monitor VDD excursions below the VDSBOR threshold. The VDD BOR circuit can be disabled by setting the DSBOREN bit = 0. The VDD BOR circuit is enabled when DSBOREN = 1 on “LF” devices, or on “F” devices while in Deep Sleep with DSBOREN = 1. When enabled, the VDD BOR circuit is extremely low power (typ. 200nA) during normal operation above ~2.3V on VDD. If VDD drops below this DSBOR arming level when the VDD BOR circuit is enabled, the device may begin to consume additional current (typ. 50 A) as internal features of the circuit power-up. The higher current is necessary to achieve more accurate sensing of the VDD level. However, the device will not enter Reset until VDD falls below the VDSBOR threshold. 5.3 Power-on Reset (POR) A POR condition is generated on-chip whenever VDD rises above a certain threshold. This allows the device to start in the initialized state when VDD is adequate for operation. To take advantage of the POR circuitry, tie the MCLR pin through a resistor (1 k to 10 k) to VDD. This will eliminate external RC components usually needed to create a POR delay. When the device starts normal operation (i.e., exits the Reset condition), device operating parameters (voltage, frequency, temperature, etc.) must be met to ensure operation. If these conditions are not met, the device must be held in Reset until the operating conditions are met. POR events are captured by the POR bit (RCON). The state of the bit is set to ‘0’ whenever a Power-on Reset occurs; it does not change for any other Reset event. POR is not reset to ‘1’ by any hardware event. To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 5.4 Brown-out Reset (BOR) 5.4.1 DETECTING BOR The “F” devices in the PIC18F47J13 family incorporate two types of BOR circuits: one which monitors VDDCORE and one which monitors VDD. Only one BOR circuit can be active at a time. When in normal Run mode, Idle or normal Sleep modes, the BOR circuit that monitors VDDCORE is active and will cause the device to be held in BOR if VDDCORE drops below VBOR (parameter D005). Once VDDCORE rises back above VBOR, the device will be held in Reset until the expiration of the Power-up Timer, with period, TPWRT (parameter 33). During Deep Sleep operation, the on-chip core voltage regulator is disabled and VDDCORE is allowed to drop to VSS. If the Deep Sleep BOR circuit is enabled by the DSBOREN bit (CONFIG3L = 1), it will monitor VDD. The BOR bit always resets to ‘0’ on any VDDCORE Brown-out Reset or Power-on Reset event. This makes it difficult to determine if a Brown-out Reset event has occurred just by reading the state of BOR alone. A more reliable method is to simultaneously check the state of both POR and BOR. This assumes that the POR bit is reset to ‘1’ in software immediately after any Power-on Reset event. If BOR is ‘0’ while POR is ‘1’, it can be reliably assumed that a Brown-out Reset event has occurred. If the voltage regulator is disabled (LF device), the VDDCORE BOR functionality is disabled. In this case, the BOR bit cannot be used to determine a Brown-out Reset event. The BOR bit is still cleared by a Power-on Reset event.  2010 Microchip Technology Inc. Preliminary DS39974A-page 67 PIC18F47J13 FAMILY 5.5 Configuration Mismatch (CM) 5.6 Power-up Timer (PWRT) The Configuration Mismatch (CM) Reset is designed to detect, and attempt to recover from, random memory corrupting events. These include Electrostatic Discharge (ESD) events, which can cause widespread single bit changes throughout the device and result in catastrophic failure. In PIC18FXXJ Flash devices, the device Configuration registers (located in the configuration memory space) are continuously monitored during operation by comparing their values to complimentary shadow registers. If a mismatch is detected between the two sets of registers, a CM Reset automatically occurs. These events are captured by the CM bit (RCON). The state of the bit is set to ‘0’ whenever a CM event occurs; it does not change for any other Reset event. A CM Reset behaves similarly to MCLR, RESET instruction, WDT time-out or Stack Event Resets. As with all hard and power Reset events, the device Configuration Words are reloaded from the Flash Configuration Words in program memory as the device restarts. PIC18F47J13 family devices incorporate an on-chip PWRT to help regulate the POR process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F47J13 family devices is a counter which uses the INTRC source as the clock input. While the PWRT is counting, the device is held in Reset. The power-up time delay depends on the INTRC clock and will vary from chip-to-chip due to temperature and process variation. See DC parameter 33 (TPWRT) for details. 5.6.1 TIME-OUT SEQUENCE The PWRT time-out is invoked after the POR pulse has cleared. The total time-out will vary based on the status of the PWRT. Figure 5-2, Figure 5-3, Figure 5-4 and Figure 5-5 all depict time-out sequences on power-up with the PWRT. Since the time-outs occur from the POR pulse, if MCLR is kept low long enough, the PWRT will expire. Bringing MCLR high will begin execution immediately if a clock source is available (Figure 5-4). This is useful for testing purposes or to synchronize more than one PIC18F device operating in parallel. FIGURE 5-2: TIME-OUT SEQUENCE ON POWER-UP (MCLR TIED TO VDD, VDD RISE < TPWRT) VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET DS39974A-page 68 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 5-3: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 1 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-4: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED TO VDD): CASE 2 VDD MCLR INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET FIGURE 5-5: SLOW RISE TIME (MCLR TIED TO VDD, VDD RISE > TPWRT) 3.3V VDD MCLR 0V 1V INTERNAL POR TPWRT PWRT TIME-OUT INTERNAL RESET  2010 Microchip Technology Inc. Preliminary DS39974A-page 69 PIC18F47J13 FAMILY 5.7 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation. Status bits from the RCON register (CM, RI, TO, PD, POR and BOR) are set or cleared differently in different Reset situations, as indicated in Table 5-1. These bits are used in software to determine the nature of the Reset. Table 5-2 describes the Reset states for all of the Special Function Registers. These are categorized by POR and BOR, MCLR and WDT Resets and WDT wake-ups. TABLE 5-1: STATUS BITS, THEIR SIGNIFICANCE AND THE INITIALIZATION CONDITION FOR RCON REGISTER Program Counter(1) 0000h 0000h 0000h 0000h 0000h 0000h RCON Register CM 1 u 1 0 u u RI 1 0 1 u u u TO 1 u 1 u 1 1 PD 1 u 1 u u 0 POR 0 u u u u u BOR 0 u 0 u u u STKPTR Register STKFUL STKUNF 0 u u u u u 0 u u u u u Condition Power-on Reset RESET instruction Brown-out Reset Configuration Mismatch Reset MCLR Reset during power-managed Run modes MCLR Reset during power-managed Idle modes and Sleep mode MCLR Reset during full-power execution Stack Full Reset (STVREN = 1) Stack Underflow Reset (STVREN = 1) Stack Underflow Error (not an actual Reset, STVREN = 0) WDT time-out during full-power or power-managed Run modes WDT time-out during power-managed Idle or Sleep modes Interrupt exit from power-managed modes 0000h 0000h 0000h 0000h 0000h PC + 2 u u u u u u u u u u u u u u u u 0 0 u u u u u 0 u u u u u u u u u u u u u 1 u u u u u u 1 1 u u PC + 2 u u u 0 u u u u Legend: u = unchanged Note 1: When the wake-up is due to an interrupt and the GIEH or GIEL bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). DS39974A-page 70 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS Power-on Reset, Brown-out Reset, Wake From Deep Sleep ---0 0000 0000 0000 0000 0000 00-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 000x 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---- 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets ---0 0000 0000 0000 0000 0000 uu-0 0000 ---0 0000 0000 0000 0000 0000 --00 0000 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 000u 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---- 0000 Wake-up via WDT or Interrupt Register Applicable Devices TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 ---u uuuu(1) uuuu uuuu(1) uuuu uuuu(1) uu-u uuuu(1) ---u uuuu uuuu uuuu PC + 2(2) --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu(3) uuuu uuuu(3) uuuu uuuu(3) N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu uuuu uuuu N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 71 PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx ---x xxxx 0000 0000 xxxx xxxx 1111 1111 0110 q100 0001 1111 0001 1111 0-11 11qq xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1qq0 q000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets N/A N/A N/A N/A N/A ---- 0000 uuuu uuuu ---u uuuu 0000 0000 uuuu uuuu 1111 1111 0110 q100 0001 1111 0001 1111 0-qq qquu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 1111 1111 -000 0000 uuuu uuuu 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0000 0000 1qq0 0000 Wake-up via WDT or Interrupt Register Applicable Devices INDF2 POSTINC2 POSTDEC2 PREINC2 PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON CM1CON CM2CON RCON(4) TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 N/A N/A N/A N/A N/A ---- uuuu uuuu uuuu ---u uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0110 q1uu uuuu uuuu uuuu uuuu u-qq qquu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uqqu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices. DS39974A-page 72 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 0-00 0000 0000 00xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 ---- -----00 x001111 1111 0000 0000 0000 0000 111- 1111 000- 0000 000- 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 00-0 0001 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 00-0 0001 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 0-00 0000 0000 00xx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 0000 0000 0000 0000 0000 0000 0000 0000 0000 0010 ---- -----00 q001111 1111 0000 0000 0000 0000 111- 1111 000- 0000 000- 0000 Wake-up via WDT or Interrupt Register Applicable Devices PSTR1CON ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONH CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -----00 u00uuuu uuuu uuuu uuuu(3) uuuu uuuu uuu- uuuu uuu- uuuu(3) uuu- uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 73 PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0x00 0000 0x00 00-- -111 1111 1111 1111 1111 1111 1111 111- 1111 --00 0000 1111 1111 0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 -0-1 01-0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 0100 0-00 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0x00 uuuu uxuu 00-- -111 1111 1111 1111 1111 1111 1111 111- 1111 --00 0000 1111 1111 0000 0000 0000 0000 ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu 0000 0000 -0-1 u1-0000 0000 0000 0000 ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu 0000 0000 0100 0-00 Wake-up via WDT or Interrupt Register Applicable Devices IPR1 PIR1 PIE1 RCSTA2 OSCTUNE T1GCON T3GCON TRISE (5) PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uuuu uuuu uuuu uuuu(3) uuuu uuuu uuuu uuuu uuuu uuuu uuuu uxuu uuuu uxuu uu-- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu --uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu -u-u uu-uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuu- uuuu uuuu uuuu uuuu u-uu TRISD(5) TRISC TRISB TRISA PIE5 IPR4 PIR4 PIE4 LATE(5) LATD(5) LATC LATB LATA DMACON1 OSCCON2 DMACON2 HLVDCON PORTE(5) PORTD(5) PORTC PORTB PORTA SPBRGH1 BAUDCON1 Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices. DS39974A-page 74 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0000 0000 0100 0-00 xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1111 1111 -000 0000 xxxx xxxx 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 ---- -111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0--0 0000 000- 0000 0000 0000 0000 0000 0000 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0000 0000 0100 0-00 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 1111 1111 -000 0000 uuuu uuuu 0000 0000 1111 1111 0000 0000 0000 0000 0000 0000 ---- -111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ---- 0000 0000 0000 ---- 0000 0000 0000 ---- --00 0--0 0000 000- 0000 0000 0000 0000 0000 0000 0000 Wake-up via WDT or Interrupt Register Applicable Devices SPBRGH2 BAUDCON2 TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD SSP2MSK SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH PMADDRL PMDOUT1L PMDIN1H PMDIN1L TXADDRL TXADDRH RXADDRL RXADDRH DMABCL DMABCH PMCONH PMCONL PMMODEH PMMODEL PMDOUT2H (5) PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — — — — — PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — — — PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uuuu uuuu uuuu u-uu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- -uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- uuuu uuuu uuuu ---- --uu u--u uuuu uuu- uuuu uuuu uuuu uuuu uuuu uuuu uuuu PMDOUT1H(5) Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 75 PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00-- 0000 10-- 1111 0000 0000 0000 0000 00-0 -000 ---0 -000 uuuu uuuu uuuu uuuu 0--- -000 ---- -000 ---- ---0 0-00 00-1 00-0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 ---- 0000 0--- --00 0-00 0000 0000 0000 0-00 0000 ---- -000 0xxx xxxx 0xxx xxxx MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00-- 0000 10-- 1111 0000 0000 uuuu uuuu uu-u -uuu ---u -uuu uuuu uuuu uuuu uuuu 0--- -uuu ---- -u00 ---- ---0 0-00 00-0 00-0 0000 0000 0000 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu 0000 0000 ---- 0000 0--- --00 u-uu uuuu uuuu uuuu 0-00 0000 ---- -000 0uuu uuuu 0uuu uuuu Wake-up via WDT or Interrupt Register Applicable Devices PMDOUT2L PMDIN2H PMDIN2L PMEH PMEL PMSTATH PMSTATL CVRCON CCPTMRS0 CCPTMRS1 CCPTMRS2 DSGPR1 (6) — — — — — — — PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uu-- uuuu uu-- uuuu uuuu uuuu uuuu uuuu uu-u -uuu ---u -uuu uuuu uuuu uuuu uuuu u--- -uuu ---- -uuu ---- ---u u-uu uu-u uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu ---- uuuu u--- --uu u-uu uuuu uuuu uuuu u-uu uuuu ---- -uuu 0uuu uuuu 0uuu uuuu DSGPR0(6) DSCONH (6) DSCONL(6) DSWAKEH(6) DSWAKEL(6) ANCON1 ANCON0 ALRMCFG ALRMRPT ALRMVALH ALRMVALL ODCON1 ODCON2 ODCON3 RTCCFG RTCCAL REFOCON PADCFG1 RTCVALH RTCVALL Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices. DS39974A-page 76 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep 0001 1111 xxxx xxxx xxxx xxxx 0000 0000 0000 0x00 0000 0000 1111 1111 -000 0000 0000 0000 1111 1111 -000 0000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets 0001 1111 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uquu 0000 0000 1111 1111 -000 0000 0000 0000 1111 1111 -000 0000 00-0 0001 0000 0000 0000 0000 uuuu uuuu uuuu uuuu 0000 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 Wake-up via WDT or Interrupt Register Applicable Devices CM3CON TMR5H TMR5L T5CON T5GCON TMR6 PR6 T6CON TMR8 PR8 T8CON PSTR3CON ECCP3AS ECCP3DEL CCPR3H CCPR3L CCP3CON CCPR4H CCPR4L CCP4CON CCPR5H CCPR5L CCP5CON CCPR6H CCPR6L CCP6CON CCPR7H CCPR7L CCP7CON CCPR8H CCPR8L CCP8CON PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uquu uuuu uuuu uuuu uuuu -uuu uuuu uuuu uuuu uuuu uuuu -uuu uuuu uu-u uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --uu uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 77 PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets uuuu uuuu uuuu uuuu --00 0000 uuuu uuuu uuuu uuuu --00 0000 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 Wake-up via WDT or Interrupt Register Applicable Devices CCPR9H CCPR9L CCP9CON CCPR10H CCPR10L CCP10CON RPINR24 RPINR23 RPINR22 RPINR21 RPINR17 RPINR16 RPINR14 RPINR13 RPINR12 RPINR9 RPINR8 RPINR7 RPINR15 RPINR6 RPINR4 RPINR3 RPINR2 RPINR1 RPOR24 RPOR23 RPOR22 RPOR21 RPOR20 RPOR19 RPOR18 RPOR17 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 — — — — — — PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 uuuu uuuu uuuu uuuu --uu uuuu uuuu uuuu uuuu uuuu --uu uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices. DS39974A-page 78 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Power-on Reset, Brown-out Reset, Wake From Deep Sleep ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---- ---0 0000 0000 -0-0 0000 0000 0000000 0000 ---- --00 MCLR Resets WDT Reset RESET Instruction Stack Resets CM Resets ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---- ---0 0000 0000 -0-0 0000 0000 0000000 0000 ---- --00 Wake-up via WDT or Interrupt Register Applicable Devices RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 PPSCON PMDIS3 PMDIS2 PMDIS1 PMDIS0 ADCTRIG PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F2XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 PIC18F4XJ13 ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---u uuuu ---- ---u uuuu uuuu -u-u uuuu uuuu uuuuuuu uuuu ---- --uu Legend: u = unchanged, x = unknown, - = unimplemented bit, read as ‘0’, q = value depends on condition. Note 1: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the TOSU, TOSH and TOSL are updated with the current value of the PC. The STKPTR is modified to point to the next location in the hardware stack. 2: When the wake-up is due to an interrupt and the GIEL or GIEH bit is set, the PC is loaded with the interrupt vector (0008h or 0018h). 3: One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for the Reset value for a specific condition. 5: Not implemented on PIC18F2XJ13 devices. 6: Not implemented on “LF” devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 79 PIC18F47J13 FAMILY NOTES: DS39974A-page 80 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.0 MEMORY ORGANIZATION 6.1 Program Memory Organization There are two types of memory in PIC18 Flash microcontrollers: • Program Memory • Data RAM As Harvard architecture devices, the data and program memories use separate busses; this allows for concurrent access of the two memory spaces. Section 7.0 “Flash Program Memory” provides additional information on the operation of the Flash program memory. PIC18 microcontrollers implement a 21-bit program counter, which is capable of addressing a 2-Mbyte program memory space. Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address returns all ‘0’s (a NOP instruction). The PIC18F47J13 family offers a range of on-chip Flash program memory sizes, from 64 Kbytes (up to 32,768 single-word instructions) to 128 Kbytes (65,536 single-word instructions). Figure 6-1 provides the program memory maps for individual family devices. FIGURE 6-1: MEMORY MAPS FOR PIC18F47J13 FAMILY DEVICES PC 21 CALL, CALLW, RCALL, RETURN, RETFIE, RETLW, ADDULNK, SUBULNK Stack Level 1    Stack Level 31 PIC18FX6J13 On-Chip Memory Config. Words PIC18FX7J13 On-Chip Memory 000000h 00FFFFh 01FFFFh Unimplemented Read as ‘0’ Unimplemented Read as ‘0’ 1FFFFFF Note: Sizes of memory areas are not to scale. Sizes of program memory areas are enhanced to show detail.  2010 Microchip Technology Inc. Preliminary User Memory Space Config. Words DS39974A-page 81 PIC18F47J13 FAMILY 6.1.1 HARD MEMORY VECTORS 6.1.2 FLASH CONFIGURATION WORDS All PIC18 devices have a total of three hard-coded return vectors in their program memory space. The Reset vector address is the default value to which the program counter returns on all device Resets; it is located at 0000h. PIC18 devices also have two interrupt vector addresses for handling high-priority and low-priority interrupts. The high-priority interrupt vector is located at 0008h and the low-priority interrupt vector at 0018h. Figure 6-2 provides their locations in relation to the program memory map. Because PIC18F47J13 family devices do not have persistent configuration memory, the top four words of on-chip program memory are reserved for configuration information. On Reset, the configuration information is copied into the Configuration registers. The Configuration Words are stored in their program memory location in numerical order, starting with the lower byte of CONFIG1 at the lowest address and ending with the upper byte of CONFIG4. Table 6-1 provides the actual addresses of the Flash Configuration Word for devices in the PIC18F47J13 family. Figure 6-2 displays their location in the memory map with other memory vectors. Additional details on the device Configuration Words are provided in Section 27.1 “Configuration Bits”. FIGURE 6-2: HARD VECTOR AND CONFIGURATION WORD LOCATIONS FOR PIC18F47J13 FAMILY DEVICES 0000h 0008h 0018h TABLE 6-1: Reset Vector High-Priority Interrupt Vector Low-Priority Interrupt Vector FLASH CONFIGURATION WORD FOR PIC18F47J13 FAMILY DEVICES Program Memory (Kbytes) 64 128 Configuration Word Addresses FFF8h to FFFFh 1FFF8h to 1FFFFh Device PIC18F26J13 PIC18F46J13 On-Chip Program Memory PIC18F27J13 PIC18F47J13 Flash Configuration Words (Top of Memory-7) (Top of Memory) Read as ‘0’ 1FFFFFh Legend: (Top of Memory) represents upper boundary of on-chip program memory space (see Figure 6-1 for device-specific values). Shaded area represents unimplemented memory. Areas are not shown to scale. DS39974A-page 82 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.1.3 PROGRAM COUNTER The Program Counter (PC) specifies the address of the instruction to fetch for execution. The PC is 21 bits wide and is contained in three separate 8-bit registers. The low byte, known as the PCL register, is both readable and writable. The high byte, or PCH register, contains the PC bits; it is not directly readable or writable. Updates to the PCH register are performed through the PCLATH register. The upper byte is called PCU. This register contains the PC bits; it is also not directly readable or writable. Updates to the PCU register are performed through the PCLATU register. The contents of PCLATH and PCLATU are transferred to the program counter by any operation that writes to PCL. Similarly, the upper 2 bytes of the program counter are transferred to PCLATH and PCLATU by an operation that reads PCL. This is useful for computed offsets to the PC (see Section 6.1.6.1 “Computed GOTO”). The PC addresses bytes in the program memory. To prevent the PC from becoming misaligned with word instructions, the Least Significant bit (LSb) of PCL is fixed to a value of ‘0’. The PC increments by two to address sequential instructions in the program memory. The CALL, RCALL, GOTO and program branch instructions write to the program counter directly. For these instructions, the contents of PCLATH and PCLATU are not transferred to the program counter. The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer (SP), STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers (SFRs). Data can also be pushed to, or popped from, the stack using these registers. A CALL type instruction causes a push onto the stack. The Stack Pointer is first incremented and the location pointed to by the Stack Pointer is written with the contents of the PC (already pointing to the instruction following the CALL). A RETURN type instruction causes a pop from the stack. The contents of the location pointed to by the STKPTR are transferred to the PC and then the Stack Pointer is decremented. The Stack Pointer is initialized to ‘00000’ after all Resets. There is no RAM associated with the location corresponding to a Stack Pointer value of ‘00000’; this is only a Reset value. Status bits indicate if the stack is full, has overflowed or has underflowed. 6.1.4.1 Top-of-Stack Access 6.1.4 RETURN ADDRESS STACK The return address stack allows any combination of up to 31 program calls and interrupts to occur. The PC is pushed onto the stack when a CALL or RCALL instruction is executed, or an interrupt is Acknowledged. The PC value is pulled off the stack on a RETURN, RETLW or a RETFIE instruction (and on ADDULNK and SUBULNK instructions if the extended instruction set is enabled). PCLATU and PCLATH are not affected by any of the RETURN or CALL instructions. Only the top of the return address stack (TOS) is readable and writable. A set of three registers, TOSU:TOSH:TOSL, holds the contents of the stack location pointed to by the STKPTR register (Figure 6-3). This allows users to implement a software stack if necessary. After a CALL, RCALL or interrupt (and ADDULNK and SUBULNK instructions if the extended instruction set is enabled), the software can read the pushed value by reading the TOSU:TOSH:TOSL registers. These values can be placed on a user-defined software stack. At return time, the software can return these values to TOSU:TOSH:TOSL and do a return. The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. FIGURE 6-3: RETURN ADDRESS STACK AND ASSOCIATED REGISTERS Return Address Stack 11111 11110 11101 Top-of-Stack Registers TOSU 00h TOSH 1Ah TOSL 34h Stack Pointer STKPTR 00010 Top-of-Stack 001A34h 000D58h 00011 00010 00001 00000  2010 Microchip Technology Inc. Preliminary DS39974A-page 83 PIC18F47J13 FAMILY 6.1.4.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-1) contains the Stack Pointer value, the STKFUL (Stack Full) and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off of the stack. On Reset, the Stack Pointer value will be zero. The user may read and write the Stack Pointer value. This feature can be used by a Real-Time Operating System (RTOS) for return stack maintenance. After the PC is pushed onto the stack 31 times (without popping any values off the stack), the STKFUL bit is set. The STKFUL bit is cleared by software or by a Power-on Reset (POR). The action that takes place when the stack becomes full depends on the state of the Stack Overflow Reset Enable (STVREN) Configuration bit. Refer to Section 27.1 “Configuration Bits” for the device Configuration bits’ description. If STVREN is set (default), the 31st push will push the (PC + 2) value onto the stack, set the STKFUL bit and reset the device. The STKFUL bit will remain set and the Stack Pointer will be set to zero. If STVREN is cleared, the STKFUL bit will be set on the 31st push and the Stack Pointer will increment to 31. Any additional pushes will not overwrite the 31st push and the STKPTR will remain at 31. When the stack has been popped enough times to unload the stack, the next pop will return zero to the PC and set the STKUNF bit, while the Stack Pointer remains at zero. The STKUNF bit will remain set until cleared by software or until a POR occurs. Note: Returning a value of zero to the PC on an underflow has the effect of vectoring the program to the Reset vector, where the stack conditions can be verified and appropriate actions can be taken. This is not the same as a Reset, as the contents of the SFRs are not affected. 6.1.4.3 PUSH and POP Instructions Since the Top-of-Stack (TOS) is readable and writable, the ability to push values onto the stack and pull values off of the stack, without disturbing normal program execution, is necessary. The PIC18 instruction set includes two instructions, PUSH and POP, that permit the TOS to be manipulated under software control. TOSU, TOSH and TOSL can be modified to place data or a return address on the stack. The PUSH instruction places the current PC value onto the stack. This increments the Stack Pointer and loads the current PC value onto the stack. The POP instruction discards the current TOS by decrementing the Stack Pointer. The previous value pushed onto the stack then becomes the TOS value. REGISTER 6-1: R/C-0 STKFUL(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 STKPTR: STACK POINTER REGISTER (ACCESS FFCh) R/C-0 U-0 — R/W-0 SP4 R/W-0 SP3 R/W-0 SP2 R/W-0 SP1 R/W-0 SP0 bit 0 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown STKUNF(1) STKFUL: Stack Full Flag bit(1) 1 = Stack became full or overflowed 0 = Stack has not become full or overflowed STKUNF: Stack Underflow Flag bit(1) 1 = Stack underflow occurred 0 = Stack underflow did not occur Unimplemented: Read as ‘0’ SP: Stack Pointer Location bits Bits 7 and 6 are cleared by user software or by a POR. bit 6 bit 5 bit 4-0 Note 1: DS39974A-page 84 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.1.4.4 Stack Full and Underflow Resets 6.1.6 Device Resets on stack overflow and stack underflow conditions are enabled by setting the STVREN bit in Configuration Register 1L. When STVREN is set, a full or underflow condition sets the appropriate STKFUL or STKUNF bit and then causes a device Reset. When STVREN is cleared, a full or underflow condition sets the appropriate STKFUL or STKUNF bit, but does not cause a device Reset. The STKFUL or STKUNF bits are cleared by the user software or a POR. LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures or look-up tables in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • Computed GOTO • Table Reads 6.1.6.1 Computed GOTO 6.1.5 FAST REGISTER STACK (FRS) A Fast Register Stack (FRS) is provided for the STATUS, WREG and BSR registers to provide a “fast return” option for interrupts. This stack is only one level deep and is neither readable nor writable. It is loaded with the current value of the corresponding register when the processor vectors for an interrupt. All interrupt sources push values into the Stack registers. The values in the registers are then loaded back into the working registers if the RETFIE, FAST instruction is used to return from the interrupt. If both low-priority and high-priority interrupts are enabled, the Stack registers cannot be used reliably to return from low-priority interrupts. If a high-priority interrupt occurs while servicing a low-priority interrupt, the Stack register values stored by the low-priority interrupt will be overwritten. In these cases, users must save the key registers in software during a low-priority interrupt. If interrupt priority is not used, all interrupts may use the FRS for returns from interrupt. If no interrupts are used, the FRS can be used to restore the STATUS, WREG and BSR registers at the end of a subroutine call. To use the Fast Register Stack for a subroutine call, a CALL label, FAST instruction must be executed to save the STATUS, WREG and BSR registers to the Fast Register Stack. A RETURN, FAST instruction is then executed to restore these registers from the FRS. Example 6-1 provides a source code example that uses the FRS during a subroutine call and return. A computed GOTO is accomplished by adding an offset to the PC. An example is shown in Example 6-2. A look-up table can be formed with an ADDWF PCL instruction and a group of RETLW nn instructions. The W register is loaded with an offset into the table before executing a call to that table. The first instruction of the called routine is the ADDWF PCL instruction. The next executed instruction will be one of the RETLW nn instructions that returns the value, ‘nn’, to the calling function. The offset value (in WREG) specifies the number of bytes that the PC should advance and should be multiples of 2 (LSb = 0). In this method, only one byte may be stored in each instruction location, but room on the return address stack is required. EXAMPLE 6-2: MOVF CALL nn00h ADDWF RETLW RETLW RETLW . . . COMPUTED GOTO USING AN OFFSET VALUE OFFSET, W TABLE PCL nnh nnh nnh ORG TABLE 6.1.6.2 Table Reads EXAMPLE 6-1: CALL SUB1, FAST FAST REGISTER STACK CODE EXAMPLE ;STATUS, WREG, BSR ;SAVED IN FAST REGISTER ;STACK A better method of storing data in program memory allows two bytes to be stored in each instruction location. Look-up table data may be stored two bytes per program word while programming. The Table Pointer (TBLPTR) specifies the byte address and the Table Latch (TABLAT) contains the data that is read from the program memory. Data is transferred from program memory, one byte at a time. Table read operation is discussed further Section 7.1 “Table Reads and Table Writes”. in · · SUB1 · · RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK  2010 Microchip Technology Inc. Preliminary DS39974A-page 85 PIC18F47J13 FAMILY 6.2 6.2.1 PIC18 Instruction Cycle CLOCKING SCHEME 6.2.2 INSTRUCTION FLOW/PIPELINING The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the PC is incremented on every Q1; the instruction is fetched from the program memory and latched into the Instruction Register (IR) during Q4. The instruction is decoded and executed during the following Q1 through Q4. Figure 6-4 illustrates the clocks and instruction execution flow. An “Instruction Cycle” consists of four Q cycles, Q1 through Q4. The instruction fetch and execute are pipelined in such a manner that a fetch takes one instruction cycle, while the decode and execute take another instruction cycle. However, due to the pipelining, each instruction effectively executes in one cycle. If an instruction causes the PC to change (e.g., GOTO), then two cycles are required to complete the instruction (Example 6-3). A fetch cycle begins with the PC incrementing in Q1. In the execution cycle, the fetched instruction is latched into the IR in cycle, Q1. This instruction is then decoded and executed during the Q2, Q3 and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write). FIGURE 6-4: OSC1 Q1 Q2 Q3 Q4 PC OSC2/CLKO (RC mode) CLOCK/INSTRUCTION CYCLE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Internal Phase Clock PC PC + 2 PC + 4 Execute INST (PC – 2) Fetch INST (PC) Execute INST (PC) Fetch INST (PC + 2) Execute INST (PC + 2) Fetch INST (PC + 4) EXAMPLE 6-3: INSTRUCTION PIPELINE FLOW TCY0 TCY1 Execute 1 Fetch 2 Execute 2 Fetch 3 Execute 3 Fetch 4 Flush (NOP) Fetch SUB_1 Execute SUB_1 TCY2 TCY3 TCY4 TCY5 1. MOVLW 55h 2. MOVWF LATB 3. BRA SUB_1 4. BSF Fetch 1 LATA, BIT3 (Forced NOP) 5. Instruction @ address SUB_1 Note: All instructions are single-cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS39974A-page 86 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.2.3 INSTRUCTIONS IN PROGRAM MEMORY The program memory is addressed in bytes. Instructions are stored as 2 bytes or 4 bytes in program memory. The Least Significant Byte (LSB) of an instruction word is always stored in a program memory location with an even address (LSB = 0). To maintain alignment with instruction boundaries, the PC increments in steps of 2 and the LSB will always read ‘0’ (see Section 6.1.3 “Program Counter”). Figure 6-5 provides an example of how instruction words are stored in the program memory. The CALL and GOTO instructions have the absolute program memory address embedded into the instruction. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC, which accesses the desired byte address in program memory. Instruction #2 in Figure 6-5 displays how the instruction, GOTO 0006h, is encoded in the program memory. Program branch instructions, which encode a relative address offset, operate in the same manner. The offset value stored in a branch instruction represents the number of single-word instructions that the PC will be offset by. Section 28.0 “Instruction Set Summary” provides further details of the instruction set. FIGURE 6-5: INSTRUCTIONS IN PROGRAM MEMORY LSB = 1 Program Memory Byte Locations Instruction 1: Instruction 2: Instruction 3: MOVLW GOTO MOVFF 055h 0006h 123h, 456h 0Fh EFh F0h C1h F4h 55h 03h 00h 23h 56h LSB = 0 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h 000014h 6.2.4 TWO-WORD INSTRUCTIONS The standard PIC18 instruction set has four, two-word instructions: CALL, MOVFF, GOTO and LSFR. In all cases, the second word of the instructions always has ‘1111’ as its four Most Significant bits (MSbs); the other 12 bits are literal data, usually a data memory address. The use of ‘1111’ in the 4 MSbs of an instruction specifies a special form of NOP. If the instruction is executed in proper sequence immediately after the first word, the data in the second word is accessed and used by the instruction sequence. If the first word is skipped for some reason, and the second word is executed by itself, a NOP is executed instead. This is necessary for cases when the two-word instruction is preceded by a conditional instruction that changes the PC. Example 6-4 illustrates how this works. Note: See Section 6.5 “Program Memory and the Extended Instruction Set” for information on two-word instructions in the extended instruction set. EXAMPLE 6-4: CASE 1: Object Code TWO-WORD INSTRUCTIONS Source Code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 CASE 2: Object Code TSTFSZ MOVFF ADDWF Source Code REG1 ; is RAM location 0? ; Execute this word as a NOP REG1, REG2 ; No, skip this word REG3 ; continue code 0110 0110 0000 0000 1100 0001 0010 0011 1111 0100 0101 0110 0010 0100 0000 0000 TSTFSZ MOVFF ADDWF REG1 ; is RAM location 0? ; 2nd word of instruction REG1, REG2 ; Yes, execute this word REG3 ; continue code  2010 Microchip Technology Inc. Preliminary DS39974A-page 87 PIC18F47J13 FAMILY 6.3 Note: Data Memory Organization The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. 6.3.1 BANK SELECT REGISTER The data memory in PIC18 devices is implemented as static RAM. Each register in the data memory has a 12-bit address, allowing up to 4096 bytes of data memory. The memory space is divided into as many as 16 banks that contain 256 bytes each. The PIC18F47J13 family implements all available banks and provides 3.8 Kbytes of data memory available to the user. Figure 6-6 provides the data memory organization for the devices. The data memory contains Special Function Registers (SFRs) and General Purpose Registers (GPRs). The SFRs are used for control and status of the controller and peripheral functions, while GPRs are used for data storage and scratchpad operations in the user’s application. Any read of an unimplemented location will read as ‘0’s. The instruction set and architecture allow operations across all banks. The entire data memory may be accessed by Direct, Indirect or Indexed Addressing modes. Addressing modes are discussed later in this section. To ensure that commonly used registers (select SFRs and select GPRs) can be accessed in a single cycle, PIC18 devices implement an Access Bank. This is a 256-byte memory space that provides fast access to select SFRs and the lower portion of GPR Bank 0 without using the BSR. Section 6.3.2 “Access Bank” provides a detailed description of the Access RAM. Large areas of data memory require an efficient addressing scheme to make rapid access to any address possible. Ideally, this means that an entire address does not need to be provided for each read or write operation. For PIC18 devices, this is accomplished with a RAM banking scheme. This divides the memory space into 16 contiguous banks of 256 bytes. Depending on the instruction, each location can be addressed directly by its full 12-bit address, or an 8-bit low-order address and a 4-bit Bank Pointer. Most instructions in the PIC18 instruction set make use of the Bank Pointer, known as the Bank Select Register (BSR). This SFR holds the 4 MSbs of a location’s address; the instruction itself includes the 8 LSbs. Only the four lower bits of the BSR are implemented (BSR). The upper four bits are unused; they will always read ‘0’ and cannot be written to. The BSR can be loaded directly by using the MOVLB instruction. The value of the BSR indicates the bank in data memory. The 8 bits in the instruction show the location in the bank and can be thought of as an offset from the bank’s lower boundary. The relationship between the BSR’s value and the bank division in data memory is illustrated in Figure 6-7. Because up to 16 registers can share the same low-order address, the user must always be careful to ensure that the proper bank is selected before performing a data read or write. For example, writing what should be program data to an 8-bit address of F9h, while the BSR is 0Fh, will end up resetting the PC. While any bank can be selected, only those banks that are actually implemented can be read or written to. Writes to unimplemented banks are ignored, while reads from unimplemented banks will return ‘0’s. Even so, the STATUS register will still be affected as if the operation was successful. The data memory map in Figure 6-6 indicates which banks are implemented. In the core PIC18 instruction set, only the MOVFF instruction fully specifies the 12-bit address of the source and target registers. This instruction ignores the BSR completely when it executes. All other instructions include only the low-order address as an operand and must use either the BSR or the Access Bank to locate their target registers. DS39974A-page 88 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 6-6: BSR3:BSR0 00h = 0000 DATA MEMORY MAP FOR PIC18F47J13 FAMILY DEVICES When a = 0: The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The remaining 160 bytes are Special Function Registers (from Bank 15). When a = 1: The BSR specifies the bank used by the instruction. Bank 0 FFh 00h FFh 00h Bank 2 FFh 00h Bank 3 FFh 00h Bank 4 FFh 00h Bank 5 FFh 00h Bank 6 FFh 00h Bank 7 FFh 00h Bank 8 FFh 00h Bank 9 FFh 00h Bank 10 FFh 00h Bank 11 Access RAM GPR GPR = 0001 Bank 1 000h 05Fh 060h 0FFh 100h 1FFh 200h = 0010 GPR 2FFh 300h GPR 3FFh 400h 4FFh 500h GPR 5FFh 600h GPR 6FFh 700h GPR 7FFh 800h GPR 8FFh 900h 9FFh A00h AFFh B00h BFFh C00h CFFh D00h Access Bank 5Fh Access RAM High 60h (SFRs) FFh Access RAM Low 00h = 0011 = 0100 GPR = 0101 = 0110 = 0111 = 1000 = 1001 GPR = 1010 GPR = 1011 GPR FFh 00h FFh 00h = 1100 Bank 12 GPR = 1101 Bank 13 GPR, BDT GPR = 1110 Bank 14 = 1111 Bank 15 DFFh E00h EAFh C0h EB0h Non-Access SFR(1) FFh EFFh F00h 00h Non-Access SFR(1) 60h Access SFRs FFh FFFh F5Fh FFh 00h Note 1: Addresses, EB0h through F5Fh, are not part of the Access Bank. Either the BANKED or the MOVFF instruction should be used to access these SFRs.  2010 Microchip Technology Inc. Preliminary DS39974A-page 89 PIC18F47J13 FAMILY FIGURE 6-7: 7 0 0 0 USE OF THE BANK SELECT REGISTER (DIRECT ADDRESSING) BSR(1) 0 0 0 1 0 0 000h 100h Bank 1 200h 300h Bank 2 Data Memory 00h Bank 0 FFh 00h FFh 00h FFh 00h 7 1 1 1 1 From Opcode(2) 1 1 1 1 1 1 1 1 1 1 0 1 1 Bank Select(2) Bank 3 through Bank 13 E00h Bank 14 F00h FFFh Note 1: 2: Bank 15 FFh 00h FFh 00h FFh The Access RAM bit of the instruction can be used to force an override of the selected bank (BSR) to the registers of the Access Bank. The MOVFF instruction embeds the entire 12-bit address in the instruction. 6.3.2 ACCESS BANK While the use of the BSR with an embedded 8-bit address allows users to address the entire range of data memory, it also means that the user must always ensure that the correct bank is selected. Otherwise, data may be read from, or written to, the wrong location. This can be disastrous if a GPR is the intended target of an operation, but an SFR is written to instead. Verifying and/or changing the BSR for each read or write to data memory can become very inefficient. To streamline access for the most commonly used data memory locations, the data memory is configured with an Access Bank, which allows users to access a mapped block of memory without specifying a BSR. The Access Bank consists of the first 96 bytes of memory (00h-5Fh) in Bank 0 and the last 160 bytes of memory (60h-FFh) in Bank 15. The lower half is known as the Access RAM and is composed of GPRs. The upper half is where the device’s SFRs are mapped. These two areas are mapped contiguously in the Access Bank and can be addressed in a linear fashion by an 8-bit address (Figure 6-6). The Access Bank is used by core PIC18 instructions that include the Access RAM bit (the ‘a’ parameter in the instruction). When ‘a’ is equal to ‘1’, the instruction uses the BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. Using this “forced” addressing allows the instruction to operate on a data address in a single cycle without updating the BSR first. For 8-bit addresses of 60h and above, this means that users can evaluate and operate on SFRs more efficiently. The Access RAM below 60h is a good place for data values that the user might need to access rapidly, such as immediate computational results or common program variables. Access RAM also allows for faster and more code efficient context saving and switching of variables. The mapping of the Access Bank is slightly different when the extended instruction set is enabled (XINST Configuration bit = 1). This is discussed in more detail in Section 6.6.3 “Mapping the Access Bank in Indexed Literal Offset Mode”. 6.3.3 GENERAL PURPOSE REGISTER FILE PIC18 devices may have banked memory in the GPR area. This is data RAM, which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upward toward the bottom of the SFR area. GPRs are not initialized by a POR and are unchanged on all other Resets. DS39974A-page 90 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.3.4 SPECIAL FUNCTION REGISTERS The SFRs are registers used by the CPU and peripheral modules for controlling the desired operation of the device. These registers are implemented as static RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F40h to FFFh). Table 6-2, Table 6-3 and Table 6-4 provide a list of these registers. The SFRs can be classified into two sets: those associated with the “core” device functionality (ALU, Resets and interrupts) and those related to the peripheral functions. The Reset and Interrupt registers are described in their corresponding chapters, while the ALU’s STATUS register is described later in this section. Registers related to the operation of the peripheral features are described in the chapter for that peripheral. The SFRs are typically distributed among the peripherals whose functions they control. Unused SFR locations are unimplemented and read as ‘0’s Note: The SFRs located between EB0h and F5Fh are not part of the Access Bank. Either BANKED instructions (using BSR) or the MOVFF instruction should be used to access these locations. When programming in MPLAB® C18, the compiler will automatically use the appropriate addressing mode. TABLE 6-2: Address FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h ACCESS BANK SPECIAL FUNCTION REGISTER MAP Name TOSU TOSH TOSL Address FDFh FDEh FDDh FDCh FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD4h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC7h (1) (1) Name INDF2 (1) Address FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB2h FB1h FB0h FAFh FAEh FADh FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h Name PSTR1CON ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 Address F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h Name IPR1 PIR1 PIE1 RCSTA2 OSCTUNE T1GCON IPR5 PIR5 T3GCON TRISE TRISD TRISC TRISB TRISA PIE5 IPR4 PIR4 PIE4 LATE (2) (2) Address F7Fh F7Eh F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76h F75h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F65h F64h F63h F62h F61h F60h Name SPBRGH1 BAUDCON1 SPBRGH2 BAUDCON2 TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD(3) SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH(2,4) PMADDRL(2,4) PMDIN1H(2) PMDIN1L(2) TXADDRL TXADDRH RXADDRL RXADDRH DMABCL DMABCH — — — — — — POSTINC2(1) POSTDEC2(1) PREINC2(1) PLUSW2(1) FSR2H FSR2L STATUS TMR0H TMR0L T0CON —(5) OSCCON CM1CON CM2CON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD(3) SSP1STAT SSP1CON1 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0(1) POSTINC0(1) POSTDEC0 PREINC0 PLUSW0 FSR0L WREG INDF1(1) POSTINC1 POSTDEC1(1) PREINC1(1) PLUSW1(1) FSR1H FSR1L BSR FSR0H (1) FB3h CTMUCONH LATD (1) LATC LATB LATA DMACON1 OSCCON2(5) DMACON2 HLVDCON PORTE(2) PORTD(2) PORTC PORTB PORTA FC6h FC5h FC4h FC3h FC2h FC1h FC0h Note 1: 2: 3: 4: 5: This is not a physical register. This register is not available on 28-pin devices. SSPxADD and SSPxMSK share the same address. PMADDRH and PMDOUTH share the same address, and PMADDRL and PMDOUTL share the same address. PMADDRx is used in Master modes and PMDOUTx is used in Slave modes. Reserved; do not write to this location.  2010 Microchip Technology Inc. Preliminary DS39974A-page 91 PIC18F47J13 FAMILY TABLE 6-3: Address F5Fh F5Eh F5Dh F5Ch Name PMCONH PMCONL PMMODEH PMMODEL NON-ACCESS BANK SPECIAL FUNCTION REGISTER MAP Address F3Fh F3Eh F3Dh F3Ch F3Bh F3Ah F39h F38h F37h F36h F35h F34h F33h F32h F31h F30h F2Fh F2Eh F2Dh F2Ch F2Bh F2Ah F29h F28h F27h F26h F25h F24h F23h F22h F21h F20h Name RTCCFG RTCCAL REFOCON PADCFG1 RTCVALH RTCVALL — — — — — — — — — — — — — — — — — — — — CM3CON TMR5H TMR5L T5CON T5GCON TMR6 Address F1Fh F1Eh F1Dh F1Ch F1Bh F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah F09h F08h F07h F06h F05h F04h F03h F02h F01h Name PR6 T6CON TMR8 PR8 T8CON ECCP3AS ECCP3DEL CCPR3H CCPR3L CCP3CON CCPR4H CCPR4L CCP4CON CCPR5H CCPR5L CCP5CON CCPR6H CCPR6L CCP6CON CCPR7H CCPR7L CCP7CON CCPR8H CCPR8L CCP8CON CCPR9H CCPR9L CCP9CON CCPR10H CCPR10L Address EFFh EFEh EFDh EFCh EFBh EFAh EF9h EF8h EF7h EF6h EF5h EF4h EF3h EF2h EF1h EF0h EEFh EEEh EEDh EECh EEBh EEAh EE9h EE8h EE7h EE6h EE5h EE4h EE3h EE2h EE1h EE0h Name RPINR24 RPINR23 RPINR22 RPINR21 — — — RPINR17 RPINR16 — — RPINR14 RPINR13 RPINR12 — — — — — — — RPINR9 RPINR8 RPINR7 RPINR15 RPINR6 — RPINR4 RPINR3 RPINR2 RPINR1 — Address EDFh EDEh EDDh EDCh EDBh EDAh ED9h ED8h ED7h ED6h ED5h ED4h ED3h ED2h ED1h ED0h ECFh ECEh ECDh ECCh ECBh ECAh EC9h EC8h EC7h EC6h EC5h EC4h EC3h EC2h EC1h EC0h Name — — — — — — — RPOR24 RPOR23 RPOR22 RPOR21 RPOR20 RPOR19 RPOR18 RPOR17 RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 Address EBFh EBEh EBDh EBCh EBBh EBAh EB9h EB8h EB7h EB6h EB5h EB4h EB3h EB2h EB1h EB0h Name PPSCON — — PMDIS3 PMDIS2 PMDIS1 PMDIS0 ADCTRIG — — — — — — — — F5Bh PMDOUT2H F5Ah PMDOUT2L F59h F58h F57h F56h F55h F54h F53h PMDIN2H PMDIN2L PMEH PMEL PMSTATH PMSTATL CVRCON F1Ah PSTR3CON F52h CCPTMRS0 F51h CCPTMRS1 F50h CCPTMRS2 F4Fh F4Eh F4Dh F4Ch F4Bh F4Ah F49h F48h F47h F46h F45h F44h F43h F42h F41h F40h DSGPR1 DSGPR0 DSCONH DSCONL DSWAKEH DSWAKEL ANCON1 ANCON0 ALRMCFG ALRMRPT ALRMVALH ALRMVALL — ODCON1 ODCON2 ODCON3 F00h CCP10CON DS39974A-page 92 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.3.4.1 Context Defined SFRs There are several registers that share the same address in the SFR space. The register's definition and usage depends on the operating mode of its associated peripheral. These registers are: • SSPxADD and SSPxMSK: These are two separate hardware registers, accessed through a single SFR address. The operating mode of the MSSP modules determines which register is being accessed. See Section 20.5.3.4 “7-Bit Address Masking Mode” for additional details. • PMADDRH/L and PMDOUT2H/L: In this case, these named buffer pairs are actually the same physical registers. The Parallel Master Port (PMP) module’s operating mode determines what function the registers take on. See Section 11.1.2 “Data Registers” for additional details. TABLE 6-4: Addr. FFFh FFEh FFDh FFCh FFBh FFAh FF9h FF8h FF7h FF6h FF5h FF4h FF3h FF2h FF1h FF0h FEFh FEEh FEDh FECh FEBh FEAh FE9h FE8h FE7h FE6h FE5h FE4h FE3h FE2h FE1h FE0h FDFh FDEh FDDh FDCh Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) Bit 7 — Bit 6 — Bit 5 — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 0000 0000 0000 0000 SP4 SP3 SP2 SP1 SP0 00-0 0000 ---0 0000 0000 0000 0000 0000 — Program Memory Table Pointer Upper Byte (TBLPTR) --00 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx TMR0IE INTEDG1 INT3IE INT0IE INTEDG2 INT2IE RBIE INTEDG3 INT1IE TMR0IF TMR0IP INT3IF INT0IF INT3IP INT2IF RBIF RBIP INT1IF 0000 000x 1111 1111 1100 0000 N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx xxxx xxxx N/A N/A N/A N/A N/A ---- 0000 xxxx xxxx Bank Select Register ---- 0000 N/A N/A N/A N/A Holding Register for PC File Name TOSU TOSH TOSL STKPTR PCLATU PCLATH PCL TBLPTRU TBLPTRH TBLPTRL TABLAT PRODH PRODL INTCON INTCON2 INTCON3 INDF0 POSTINC0 POSTDEC0 PREINC0 PLUSW0 FSR0H FSR0L WREG INDF1 POSTINC1 POSTDEC1 PREINC1 PLUSW1 FSR1H FSR1L BSR INDF2 POSTINC2 POSTDEC2 PREINC2 Top-of-Stack Upper Byte (TOS) Top-of-Stack High Byte (TOS) Top-of-Stack Low Byte (TOS) STKFUL — STKUNF — — — Holding Register for PC PC Low Byte (PC) — — Program Memory Table Pointer High Byte (TBLPTR) Program Memory Table Pointer Low Byte (TBLPTR) Program Memory Table Latch Product Register High Byte Product Register Low Byte GIE/GIEH RBPU INT2IP PEIE/GIEL INTEDG0 INT1IP Uses contents of FSR0 to address data memory – value of FSR0 not changed (not a physical register) Uses contents of FSR0 to address data memory – value of FSR0 post-incremented (not a physical register) Uses contents of FSR0 to address data memory – value of FSR0 post-decremented (not a physical register) Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) Uses contents of FSR0 to address data memory – value of FSR0 pre-incremented (not a physical register) – value of FSR0 offset by W — Working Register Uses contents of FSR1 to address data memory – value of FSR1 not changed (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 post-incremented (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 post-decremented (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) Uses contents of FSR1 to address data memory – value of FSR1 pre-incremented (not a physical register) – value of FSR1 offset by W — — — — — — — — Indirect Data Memory Address Pointer 1 High Byte Indirect Data Memory Address Pointer 1 Low Byte Uses contents of FSR2 to address data memory – value of FSR2 not changed (not a physical register) Uses contents of FSR2 to address data memory – value of FSR2 post-incremented (not a physical register) Uses contents of FSR2 to address data memory – value of FSR2 post-decremented (not a physical register) Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) — — — Indirect Data Memory Address Pointer 0 High Byte Indirect Data Memory Address Pointer 0 Low Byte Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR.  2010 Microchip Technology Inc. Preliminary DS39974A-page 93 PIC18F47J13 FAMILY TABLE 6-4: Addr. FDBh FDAh FD9h FD8h FD7h FD6h FD5h FD3h FD2h FD1h FD0h FCFh FCEh FCDh FCCh FCBh FCAh FC9h FC8h FC8h FC7h FC6h FC5h FC5h FC4h FC3h FC2h FC1h FC0h FBFh FBEh FBDh FBCh FBBh FBAh FB9h FB8h FB7h FB6h FB5h FB4h FB3h FB2h FB1h FB0h FAFh FAEh FADh Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR N/A ---- 0000 xxxx xxxx OV Z DC C ---x xxxx 0000 0000 xxxx xxxx T0CS IRCF1 CPOL CPOL CM T0SE IRCF0 EVPOL1 EVPOL1 RI PSA OSTS EVPOL0 EVPOL0 TO T0PS2 — CREF CREF PD T0PS1 SCS1 CCH1 CCH1 POR T0PS0 SCS0 CCH0 CCH0 BOR 1111 1111 0110 q100 0001 1111 0001 1111 0-11 11qq xxxx xxxx xxxx xxxx T1CKPS1 T1CKPS0 T1OSCEN T1SYNC RD16 TMR1ON 0000 0000 0000 0000 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 xxxx xxxx 0000 0000 MSK0 BF SSPM0 SEN SEN 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx CHS3 ACQT2 ULPLVL — P1DC5 CHS2 ACQT1 VBGOE STRSYNC P1DC4 CHS1 ACQT0 DS STRD PSS1AC1 P1DC3 CHS0 ADCS2 ULPEN STRC PSS1AC0 P1DC2 GO/DONE ADCS1 ULPSINK STRB PSS1BD1 P1DC1 ADON ADCS0 SWDTEN STRA PSS1BD0 P1DC0 0000 0000 0000 0000 1qq0 q000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx DC1B0 STRSYNC P2DC4 CCP1M3 STRD PSS2AC1 P2DC3 CCP1M2 STRC PSS2AC0 P2DC2 CCP1M1 STRB PSS2BD1 P2DC1 CCP1M0 STRA PSS2BD0 P2DC0 0000 0000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx DC2B0 TGEN EDG1POL ITRIM2 CCP2M3 EDGEN EDG1SEL1 ITRIM1 CCP2M2 EDGSEQEN EDG1SEL0 ITRIM0 CCP2M1 IDISSEN EDG2STAT IRNG1 CCP2M0 CTTRIG IRNG0 0000 0000 0-00 0000 MSK4 P CKP ACKEN ADMSK4 MSK3 S SSPM3 RCEN ADMSK3 MSK2 R/W SSPM2 PEN ADMSK2 MSK1 UA SSPM1 RSEN ADMSK1 File Name PLUSW2 FSR2H FSR2L STATUS TMR0H TMR0L T0CON OSCCON CM1CON CM2CON RCON TMR1H TMR1L T1CON TMR2 PR2 T2CON SSP1BUF SSP1ADD SSP1MSK SSP1STAT SSP1CON1 SSP1CON2 SSP1CON2 ADRESH ADRESL ADCON0 ADCON1 WDTCON PSTR1CON ECCP1AS ECCP1DEL CCPR1H CCPR1L CCP1CON PSTR2CON ECCP2AS ECCP2DEL CCPR2H CCPR2L CCP2CON CTMUCONH CTMUCONL CTMUICON SPBRG1 RCREG1 TXREG1 TXSTA1 Uses contents of FSR2 to address data memory – value of FSR2 pre-incremented (not a physical register) – value of FSR2 offset by W — — — — — — — N Indirect Data Memory Address Pointer 2 High Byte Indirect Data Memory Address Pointer 2 Low Byte Timer0 Register High Byte Timer0 Register Low Byte TMR0ON IDLEN CON CON IPEN T08BIT IRCF2 COE COE — Timer1 Register High Byte Timer1 Register Low Bytes TMR1CS1 TMR1CS0 Timer2 Register Timer2 Period Register — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 MSSP1 Receive Buffer/Transmit Register MSSP1 Address Register (I2C™ Slave mode). MSSP1 Baud Rate Reload Register (I2C Master mode). MSK7 SMP WCOL GCEN GCEN MSK6 CKE SSPOV ACKSTAT ACKSTAT MSK5 D/A SSPEN ACKDT ADMSK5 A/D Result Register High Byte A/D Result Register Low Byte VCFG1 ADFM REGSLP CMPL1 ECCP1ASE P1RSEN VCFG0 ADCAL LVDSTAT CMPL0 P1DC6 ECCP1AS2 ECCP1AS1 ECCP1AS0 Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte P1M1 CMPL1 ECCP2ASE P2RSEN P1M0 CMPL0 P2DC6 DC1B1 — P2DC5 ECCP2AS2 ECCP2AS1 ECCP2AS0 Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte P2M1 CTMUEN EDG2POL ITRIM5 P2M0 — ITRIM4 DC2B1 CTMUSIDL ITRIM3 EDG2SEL1 EDG2SEL0 EDG1STAT 0000 00xx 0000 0000 0000 0000 0000 0000 0000 0000 EUSART1 Baud Rate Generator Register Low Byte EUSART1 Receive Register EUSART1 Transmit Register CSRC TX9 TXEN SYNC SENDB BRGH TRMT TX9D 0000 0010 Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR. DS39974A-page 94 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 6-4: Addr. FACh FABh FAAh FA9h FA8h FA7h FA6h FA5h FA4h FA3h FA2h FA1h FA0h F9Fh F9Eh F9Dh F9Ch F9Bh F9Ah F99h F98h F97h F96h F95h F94h F93h F92h F91h F90h F8Fh F8Eh F8Dh F8Ch F8Bh F8Ah F89h F88h F87h F86h F85h F84h F83h F82h F81h F80h F7Fh F7Eh Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 SPEN Bit 6 RX9 Bit 5 SREN Bit 4 CREN Bit 3 ADDEN Bit 2 FERR Bit 1 OERR Bit 0 RX9D Value on POR, BOR 0000 0000 0000 0000 0000 0000 0000 0000 TXEN WPROG RC2IP RC2IF RC2IE CM1IP CM1IF CM1IE RC1IP RC1IF RC1IE SREN TUN5 T1GTM CM3IP CM3IF T3GTM — TRISD5 TRISC5 TRISB5 TRISA5 CM3IE CCP8IP CCP8IF CCP8IE — LATD5 LATC5 LATB5 LATA5 TXINC — DLYCYC1 IRVST — RD5 RC5 RB5 RA5 RXDTP SYNC FREE TX2IP TX2IF TX2IE — — — TX1IP TX1IF TX1IE CREN TUN4 T1GSPM TMR8IP TMR8IF T3GSPM — TRISD4 TRISC4 TRISB4 — TMR8IE CCP7IP CCP7IF CCP7IE — LATD4 LATC4 LATB4 — RXINC SOSCDRV DLYCYC0 HLVDEN — RD4 RC4 RB4 — TXCKP SENDB WRERR TMR4IP TMR4IF TMR4IE BCL1IP BCL1IF BCL1IE SSP1IP SSP1IF SSP1IE ADDEN TUN3 T1GGO/ T1DONE TMR6IP TMR6IF T3GGO/ T3DONE — TRISD3 TRISC3 TRISB3 TRISA3 TMR6IE CCP6IP CCP6IF CCP6IE — LATD3 LATC3 LATB3 LATA3 DUPLEX1 SOSCGO INTLVL3 HLVDL3 — RD3 RC3 RB3 RA3 BRG16 BRGH WREN CTMUIP CTMUIF CTMUIE HLVDIP HLVDIF HLVDIE CCP1IP CCP1IF CCP1IE FERR TUN2 T1GVAL TMR5IP TMR5IF T3GVAL TRISE2 TRISD2 TRISC2 TRISB2 TRISA2 TMR5IE CCP5IP CCP5IF CCP5IE LATE2 LATD2 LATC2 LATB2 LATA2 DUPLEX0 PRISD INTLVL2 HLVDL2 RE2 RD2 RC2 RB2 RA2 — TRMT WR TMR3GIP TMR3GIF TMR3GIE TMR3IP TMR3IF TMR3IE TMR2IP TMR2IF TMR2IE OERR TUN1 T1GSS1 TMR5GIP TMR5GIF T3GSS1 TRISE1 TRISD1 TRISC1 TRISB1 TRISA1 TMR5GIE CCP4IP CCP4IF CCP4IE LATE1 LATD1 LATC1 LATB1 LATA1 DLYINTEN — INTLVL1 HLVDL1 RE1 RD1 RC1 RB1 RA1 WUE TX9D — RTCCIP RTCCIF RTCCIE CCP2IP CCP2IF CCP2IE TMR1IP TMR1IF TMR1IE RX9D TUN0 T1GSS0 TMR1GIP TMR1GIF T3GSS0 TRISE0 TRISD0 TRISC0 TRISB0 TRISA0 TMR1GIE CCP3IP CCP3IF CCP3IE LATE0 LATD0 LATC0 LATB0 LATA0 DMAEN — INTLVL0 HLVDL0 RE0 RD0 RC0 RB0 RA0 ABDEN 0000 0010 ---- -----00 x001111 1111 0000 0000 0000 0000 111- 1111 000- 0000 000- 0000 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0x00 --11 1111 --00 0000 0000 0x00 00-- -111 1111 1111 1111 1111 1111 1111 111- 1111 --00 0000 1111 1111 0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 -0-1 01-0000 0000 0000 0000 ---- -xxx xxxx xxxx xxxx xxxx xxxx xxxx xxx- xxxx 0000 0000 0100 0-00 File Name RCSTA1 SPBRG2 RCREG2 TXREG2 TXSTA2 EECON2 EECON1 IPR3 PIR3 PIE3 IPR2 PIR2 PIE2 IPR1 PIR1 PIE1 RCSTA2 OSCTUNE T1GCON IPR5 PIR5 T3GCON TRISE(2) TRISD(2) TRISC TRISB TRISA PIE5 IPR4 PIR4 PIE4 LATE(2) LATD(2) LATC LATB LATA DMACON1 OSCCON2 DMACON2 HLVDCON PORTE(2) PORTD PORTC PORTB PORTA SPBRGH1 BAUDCON1 EUSART2 Baud Rate Generator Register Low Byte EUSART2 Receive Register EUSART2 Transmit Register CSRC — SSP2IP SSP2IF SSP2IE OSCFIP OSCFIF OSCFIE PMPIP(2) PMPIF(2) PMPIE(2) SPEN INTSRC TMR1GE — — TMR3GE RDPU TRISD7 TRISC7 TRISB7 TRISA7 — CCP10IP CCP10IF CCP10IE — LATD7 LATC7 LATB7 LATA7 SSCON1 — DLYCYC3 VDIRMAG — RD7 RC7 RB7 RA7 ABDOVF TX9 — BCL2IP BCL2IF BCL2IE CM2IP CM2IF CM2IE ADIP ADIF ADIE RX9 PLLEN T1GPOL — — T3GPOL REPU TRISD6 TRISC6 TRISB6 TRISA6 — CCP9IP CCP9IF CCP9IE — LATD6 LATC6 LATB6 LATA6 SSCON0 SOSCRUN DLYCYC2 BGVST — RD6 RC6 RB6 RA6 RCIDL Flash Self-Program Control Register (not a physical register) EUSART1 Baud Rate Generator High Byte Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR.  2010 Microchip Technology Inc. Preliminary DS39974A-page 95 PIC18F47J13 FAMILY TABLE 6-4: Addr. F7Dh F7Ch F7Bh F7Ah F79h F78h F77h F76H F75h F74h F74h F73h F72h F71h F70h F6Fh F6Eh F6Dh F6Ch F6Bh F6Ah F69h F68h F67h F66h F5Fh F5Eh F5Dh F5Ch F5Bh F5Ah F59h F58h F57h F56h F55h F54h F53h F52h F51h F50h F4Fh F4Eh F4Dh F4Ch Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR 0000 0000 TXCKP BRG16 — WUE ABDEN 0100 0-00 xxxx xxxx xxxx xxxx T3CKPS1 T3CKPS0 T3OSCEN T3SYNC RD16 TMR3ON 0000 0000 0000 0000 1111 1111 TMR4ON T4CKPS1 T4CKPS0 -000 0000 xxxx xxxx 0000 0000 MSK0 BF SSPM0 SEN COUT1 1111 1111 0000 0000 0000 0000 0000 0000 ---- -111 -000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — — ADRMUX1 — INCM1 WAITM2 SPI DMA Transmit Data Pointer High Byte SPI DMA Receive Data Pointer High Byte — ADRMUX0 CS1P INCM0 WAITM1 — PTBEEN BEP MODE16 WAITM0 SPI DMA Byte Count High Byte PTWREN WRSP MODE1 WAITE1 PTRDEN RDSP MODE0 WAITE0 ---- 0000 0000 0000 ---- 0000 0000 0000 — — ALP IRQM0 WAITM3 ---- --00 0--0 0000 000- 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PTEN12 PTEN4 — — CVRSS C2TSEL1 C6TSEL0 C10TSEL0 PTEN11 PTEN3 IB3F OB3E CVR3 C2TSEL0 — — PTEN10 PTEN2 IB2F OB2E CVR2 C1TSEL2 C5TSEL0 C9TSEL0 PTEN9 PTEN1 IB1F OB1E CVR1 C1TSEL1 C4TSEL1 C8TSEL1 PTEN8 PTEN0 IB0F OB0E CVR0 C1TSEL0 C4TSEL0 C8TSEL0 0000 0000 0000 0000 00-- 0000 10-- 1111 0000 0000 0000 0000 00-0 -000 ---0 -000 xxxx xxxx xxxx xxxx RTCWDIS RELEASE 0--- -000 ---- -000 MSK4 P CKP ACKEN ADMSK4 — MSK3 S SSPM3 RCEN ADMSK3 — MSK2 R/W SSPM2 PEN ADMSK2 COUT3 MSK1 UA SSPM1 RSEN ADMSK1 COUT2 File Name SPBRGH2 BAUDCON2 TMR3H TMR3L T3CON TMR4 PR4 T4CON SSP2BUF SSP2ADD SSP2MSK SSP2STAT SSP2CON1 SSP2CON2 CMSTAT PMADDRH/ PMDOUT1H(2) PMADDRL/ PMDOUT1L(2) PMDIN1H(2) PMDIN1L(2) TXADDRL TXADDRH RXADDRL RXADDRH DMABCL DMABCH PMCONH(2) PMCONL(2) PMMODEH(2) PMMODEL(2) PMDOUT2L(2) PMDIN2H(2) PMDIN2L(2) PMEH(2) PMEL(2) PMSTATH(2) PMSTATL(2) CVRCON CCPTMRS0 CCPTMRS1 CCPTMRS2 DSGPR1 DSGPR0 DSCONH DSCONL EUSART2 Baud Rate Generator High Byte ABDOVF RCIDL RXDTP Timer3 Register High Byte Timer3 Register Low Byte TMR3CS1 TMR3CS0 Timer4 Register Timer4 Period Register — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 MSSP2 Receive Buffer/Transmit Register MSSP2 Address Register (I2C™ Slave mode)/MSSP2 Baud Rate Reload Register (I2C Master mode) MSK7 SMP WCOL GCEN — — MSK6 CKE SSPOV ACKSTAT — CS1 MSK5 D/A SSPEN ACKDT ADMSK5 — Parallel Master Port Address High Byte Parallel Port Out Data High Byte (Buffer 1) Parallel Master Port Address Low Byte/ Parallel Port Out Data Low Byte (Buffer 1) Parallel Port In Data High Byte (Buffer 1) Parallel Port In Data Low Byte (Buffer 1) SPI DMA Transmit Data Pointer Low Byte — — — PMPEN CSF1 BUSY WAITB1 — — — — CSF0 IRQM1 WAITB0 — — SPI DMA Receive Data Pointer Low Byte SPI DMA Byte Count Low Byte PMDOUT2H(2) Parallel Port Out Data High Byte (Buffer 2) Parallel Port Out Data Low Byte (Buffer 2) Parallel Port In Data High Byte (Buffer 2) Parallel Port In Data Low Byte (Buffer 2) PTEN15 PTEN7 IBF OBE CVREN C3TSEL1 C7TSEL1 — PTEN14 PTEN6 IBOV OBUF CVROE C3TSEL0 C7TSEL0 — PTEN13 PTEN5 — — CVRR C2TSEL2 — — Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) Deep Sleep Persistent General Purpose Register (contents retained even in Deep Sleep) DSEN — — — — — — — — — CFGPER2 ULPWDIS DSULPEN DSBOR Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR. DS39974A-page 96 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 6-4: Addr. F4Bh F4Ah F49h F48h F47h F46h F45h F44h F43h F42h F41h F40h F3Fh F3Eh F3Dh F3Ch F3Bh F3Ah F25h F24h F23h F22h F21h F20h F1Fh F1Eh F1Dh F1Ch F1Bh F1Ah F19h F18h F17h F16h F15h F14h F13h F12h F11h F10h F0Fh F0Eh F0Dh F0Ch F0Bh F0Ah F09h F08h Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 — DSFLT VBGEN PCFG7(2) ALRMEN ARPT7 Bit 6 — — — PCFG6(2) CHIME ARPT6 Bit 5 — DSULP — PCFG5(2) AMASK3 ARPT5 Bit 4 — DSWDT PCFG12 PCFG4 AMASK2 ARPT4 Bit 3 — DSRTC PCFG11 PCFG3 AMASK1 ARPT3 Bit 2 — DSMCLR PCFG10 PCFG2 AMASK0 ARPT2 Bit 1 — — PCFG9 PCFG1 ALRMPTR1 ARPT1 Bit 0 DSINT0 DSPOR PCFG8 PCFG0 ARPT0 Value on POR, BOR ---- ---0 0-00 00-1 0--0 0000 0000 0000 File Name DSWAKEH DSWAKEL ANCON1 ANCON0 ALRMCFG ALRMRPT ALRMVALH ALRMVALL — ODCON1 ODCON2 ODCON3 RTCCFG RTCCAL REFOCON PADCFG1 RTCVALH RTCVALL CM3CON TMR5H TMR5L T5CON T5GCON TMR6 PR6 T6CON TMR8 PR8 T8CON PSTR3CON ECCP3AS ECCP3DEL CCPR3H CCPR3L CCP3CON CCPR4H CCPR4L CCP4CON CCPR5H CCPR5L CCP5CON CCPR6H CCPR6L CCP6CON CCPR7H CCPR7L CCP7CON CCPR8H ALRMPTR0 0000 0000 0000 0000 xxxx xxxx xxxx xxxx Alarm Value High Register Window based on ALRMPTR Alarm Value Low Register Window based on ALRMPTR — CCP8OD — CTMUDS RTCEN CAL7 ROON — — CCP7OD — — — CAL6 — — — CCP6OD — — RTCWREN CAL5 ROSSLP — — CCP5OD — — RTCSYNC CAL4 ROSEL — — CCP4OD CCP10OD — HALFSEC CAL3 RODIV3 — — ECCP3OD CCP9OD — RTCOE CAL2 RODIV2 — ECCP2OD U2OD SPI2OD RTCPTR1 CAL1 RODIV1 — ECCP1OD U1OD SPI1OD RTCPTR0 CAL0 RODIV0 ---- ---0000 0000 ---- 0000 0--- --00 0-00 0000 0000 0000 0-00 0000 RTSECSEL1 RTSECSEL0 PMPTTL(2) ---- -000 0xxx xxxx 0xxx xxxx CREF CCH1 CCH0 0001 1111 xxxx xxxx xxxx xxxx RTCC Value High Register Window based on RTCPTR RTCC Value Low Register Window based on RTCPTR CON COE CPOL EVPOL1 EVPOL0 Timer5 Register High Byte Timer5 Register Low Bytes TMR5CS1 TMR5GE Timer6 Register Timer6 Period Register — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 Timer8 Register Timer8 Period Register — CMPL1 ECCP3ASE P3RSEN T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 CMPL0 P3DC6 — P3DC5 STRSYNC P3DC4 STRD PSS3AC1 P3DC3 ECCP3AS2 ECCP3AS1 ECCP3AS0 TMR8ON STRC PSS3AC0 P3DC2 T8CKPS1 STRB PSS3BD1 P3DC1 T8CKPS0 STRA PSS3BD0 P3DC0 TMR5CS0 T5GPOL T5CKPS1 T5GTM T5CKPS0 T5GSPM T5OSCEN T5GGO/ T5DONE T5SYNC T5GVAL RD16 T5GSS1 TMR5ON T5GSS0 0000 0000 0000 0x00 0000 0000 1111 1111 -000 0000 0000 0000 1111 1111 -000 0000 00-0 0001 0000 0000 0000 0000 xxxx xxxx xxxx xxxx Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 3 Low Byte P3M1 P3M0 DC3B1 DC3B0 CCP3M3 CCP3M2 CCP3M1 CCP3M0 Capture/Compare/PWM Register 4 High Byte Capture/Compare/PWM Register 4 Low Byte — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 Capture/Compare/PWM Register 5 High Byte Capture/Compare/PWM Register 5 Low Byte — — DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Capture/Compare/PWM Register 6 High Byte Capture/Compare/PWM Register 6 Low Byte — — DC6B1 DC6B0 CCP6M3 CCP6M2 CCP6M1 CCP6M0 Capture/Compare/PWM Register 7 High Byte Capture/Compare/PWM Register 7 Low Byte — — DC7B1 DC7B0 CCP7M3 CCP7M2 CCP7M1 CCP7M0 Capture/Compare/PWM Register 8 High Byte 0000 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx xxxx xxxx --00 0000 xxxx xxxx Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR.  2010 Microchip Technology Inc. Preliminary DS39974A-page 97 PIC18F47J13 FAMILY TABLE 6-4: Addr. F07h F06h F05h F04h F03h F02h F01h F00h EFFh EFEh EFDh EFCh EFBh EFAh EF9h EF8h EF7h EF6h EF5h EF4h EF3h EF2h EF1h EF0h EEFh EEEh EEDh EECh EEBh EEAh EE9h EE8h EE7h EE6h EE5h EE4h EE3h EE2h EE1h EE0h EDFh EDEh EDDh EDCh EDBh EDAh ED9h ED8h ED7h Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR xxxx xxxx DC8B0 CCP8M3 CCP8M2 CCP8M1 CCP8M0 --00 0000 xxxx xxxx xxxx xxxx DC9B0 CCP9M3 CCP9M2 CCP9M1 CCP9M0 --00 0000 xxxx xxxx xxxx xxxx CCP10M3 CCP10M2 CCP10M1 CCP10M0 --00 0000 ---1 1111 ---1 1111 ---1 1111 ---1 1111 — — — — — — (3) (3) (3) ---1 1111 ---1 1111 — — — — (3) (3) ---1 1111 ---1 1111 ---1 1111 — — — — — — — (3) (3) (3) (3) (3) (3) (3) ---1 1111 ---1 1111 ---1 1111 ---1 1111 ---1 1111 — (3) ---1 1111 ---1 1111 ---1 1111 ---1 1111 — — — — — — — — (3) (3) (3) (3) (3) (3) (3) (3) ---0 0000 ---0 0000 File Name CCPR8L CCP8CON CCPR9H CCPR9L CCP9CON CCPR10H CCPR10L CCP10CON RPINR24 RPINR23 RPINR22 RPINR21 — — — RPINR17 RPINR16 — — RPINR14 RPINR13 RPINR12 — — — — — — — RPINR9 RPINR8 RPINR7 RPINR15 RPINR6 — RPINR4 RPINR3 RPINR2 RPINR1 — — — — — — — — RPOR24(2) RPOR23(2) Capture/Compare/PWM Register 8 Low Byte — — DC8B1 Capture/Compare/PWM Register 9 High Byte Capture/Compare/PWM Register 9 Low Byte — — DC9B1 Capture/Compare/PWM Register 10 High Byte Capture/Compare/PWM Register 10 Low Byte — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — DC10B1 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — DC10B0 PWM Fault Input (FLT0) to Input Pin Mapping bits SPI2 Slave Select Input (SS2) to Input Pin Mapping bits SPI2 Clock Input (SCK2) to Input Pin Mapping bits SPI2 Data Input (SDI2) to Input Pin Mapping bits — — — — — — — — — EUSART2 Clock Input (CK2) to Input Pin Mapping bits EUSART2 RX2/DT2 to Input Pin Mapping bits — — — — — — Timer5 Gate Input (T5G) to Input Pin Mapping bits Timer3 Gate Input (T3G) to Input Pin Mapping bits Timer1 Gate Input (T1G) to Input Pin Mapping bits — — — — — — — — — — — — — — — — — — — — — — — — — — — — ECCP3 Input Capture (IC3) to Input Pin Mapping bits ECCP2 Input Capture (IC2) to Input Pin Mapping bits ECCP1 Input Capture (IC1) to Input Pin Mapping bits Timer5 External Clock Input (T5CKI) to Input Pin Mapping bits Timer3 External Clock Input (T3CKI) to Input Pin Mapping bits — — — — Timer0 External Clock Input (T0CKI) to Input Pin Mapping bits External Interrupt (INT3) to Input Pin Mapping bits External Interrupt (INT2) to Input Pin Mapping bits External Interrupt (INT1) to Input Pin Mapping bits — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Remappable Pin RP24 Output Signal Select bits Remappable Pin RP23 Output Signal Select bits Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR. DS39974A-page 98 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 6-4: Addr. ED6h ED5h ED4h ED3h ED2h ED1h ED0h ECFh ECEh ECDh ECCh ECBh ECAh EC9h EC8h EC7h EC6h EC5h EC4h EC3h EC2h EC1h EC0h EBFh EBEh EBDh EBCh EBBh EBAh EB9h EB8h EB7h EB6h EB5h EB4h EB3h EB2h EB1h EB0h Note 1: 2: 3: REGISTER FILE SUMMARY (PIC18F47J13 FAMILY) (CONTINUED) Bit 7 — — — — — — — — — — — — — — — — — — — — — — — — — — CCP10MD — PSPMD(2) ECCP3MD — — — — — — — — — Bit 6 — — — — — — — — — — — — — — — — — — — — — — — — — — CCP9MD TMR8MD CTMUMD ECCP2MD — — — — — — — — — Bit 5 — — — — — — — — — — — — — — — — — — — — — — — — — — CCP8MD — RTCCMD ECCP1MD — — — — — — — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on POR, BOR ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 ---0 0000 — — — CCP4MD CMP2MD TMR1MD SPI1MD SRC1 — — — — — — — — IOLOCK — — — CMP1MD — ADCMD SRC0 — — — — — — — — ---- ---0 (3) (3) 0000 000-0-0 0000 0000 0000000 0000 ---- --00 (3) (3) (3) (3) (3) (3) (3) (3) File Name RPOR22(2) RPOR21 (2) Remappable Pin RP22 Output Signal Select bits Remappable Pin RP21 Output Signal Select bits Remappable Pin RP20 Output Signal Select bits Remappable Pin RP19 Output Signal Select bits Remappable Pin RP18 Output Signal Select bits Remappable Pin RP17 Output Signal Select bits Remappable Pin RP16 Output Signal Select bits Remappable Pin RP15 Output Signal Select bits Remappable Pin RP14 Output Signal Select bits Remappable Pin RP13 Output Signal Select bits Remappable Pin RP12 Output Signal Select bits Remappable Pin RP11 Output Signal Select bits Remappable Pin RP10 Output Signal Select bits Remappable Pin RP9 Output Signal Select bits Remappable Pin RP8 Output Signal Select bits Remappable Pin RP7 Output Signal Select bits Remappable Pin RP6 Output Signal Select bits Remappable Pin RP5 Output Signal Select bits Remappable Pin RP4 Output Signal Select bits Remappable Pin RP3 Output Signal Select bits Remappable Pin RP2 Output Signal Select bits Remappable Pin RP1 Output Signal Select bits Remappable Pin RP0 Output Signal Select bits — — — CCP7MD TMR6MD TMR4MD UART2MD — — — — — — — — — — — — CCP6MD TMR5MD TMR3MD UART1MD — — — — — — — — — — — — CCP5MD CMP3MD TMR2MD SPI2MD — — — — — — — — — RPOR20(2) RPOR19(2) RPOR18 RPOR17 RPOR16 RPOR15 RPOR14 RPOR13 RPOR12 RPOR11 RPOR10 RPOR9 RPOR8 RPOR7 RPOR6 RPOR5 RPOR4 RPOR3 RPOR2 RPOR1 RPOR0 PPSCON — — PMDIS3 PMDIS2 PMDIS1 PMDIS0 ADCTRIG — — — — — — — — Applicable for 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). Applicable for 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). Value on POR, BOR.  2010 Microchip Technology Inc. Preliminary DS39974A-page 99 PIC18F47J13 FAMILY 6.3.5 STATUS REGISTER The STATUS register, shown in Register 6-2, contains the arithmetic status of the ALU. The STATUS register can be the operand for any instruction, as with any other register. If the STATUS register is the destination for an instruction that affects the Z, DC, C, OV or N bits, then the write to these five bits is disabled. These bits are set or cleared according to the device logic. Therefore, the result of an instruction with the STATUS register as destination may be different than intended. For example, CLRF STATUS will set the Z bit but leave the other bits unchanged. The STATUS register then reads back as ‘000u u1uu’. It is recommended, therefore, that only BCF, BSF, SWAPF, MOVFF and MOVWF instructions are used to alter the STATUS register because these instructions do not affect the Z, C, DC, OV or N bits in the STATUS register. For other instructions not affecting any Status bits, see the instruction set summary in Table 28-2 and Table 28-3. Note: The C and DC bits operate as Borrow and Digit Borrow bits, respectively in subtraction. REGISTER 6-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 STATUS REGISTER (ACCESS FDBh) U-0 — U-0 — R/W-x N R/W-x OV R/W-x Z R/W-x DC(1) R/W-x C(2) bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ N: Negative bit This bit is used for signed arithmetic (2’s complement). It indicates whether the result was negative (ALU MSB = 1). 1 = Result was negative 0 = Result was positive OV: Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the 7-bit magnitude, which causes the sign bit (Bit 7) to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: Zero bit 1 = The result of an arithmetic or logic operation is zero 0 = The result of an arithmetic or logic operation is not zero DC: Digit Carry/Digit Borrow bit(1) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry out from the 4th low-order bit of the result occurred 0 = No carry out from the 4th low-order bit of the result C: Carry/Borrow bit(2) For ADDWF, ADDLW, SUBLW and SUBWF instructions: 1 = A carry out from the MSb of the result occurred 0 = No carry out from the MSb of the result occurred For Digit Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either bit 4 or bit 3 of the source register. For Borrow, the polarity is reversed. A subtraction is executed by adding the 2’s complement of the second operand. For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39974A-page 100 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.4 Note: Data Addressing Modes The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. Register File”) or a location in the Access Bank (Section 6.3.2 “Access Bank”) as the data source for the instruction. The Access RAM bit, ‘a’, determines how the address is interpreted. When ‘a’ is ‘1’, the contents of the BSR (Section 6.3.1 “Bank Select Register”) are used with the address to determine the complete 12-bit address of the register. When ‘a’ is ‘0’, the address is interpreted as being a register in the Access Bank. Addressing that uses the Access RAM is sometimes also known as Direct Forced Addressing mode. A few instructions, such as MOVFF, include the entire 12-bit address (either source or destination) in their opcodes. In these cases, the BSR is ignored entirely. The destination of the operation’s results is determined by the destination bit, ‘d’. When ‘d’ is ‘1’, the results are stored back in the source register, overwriting its original contents. When ‘d’ is ‘0’, the results are stored in the W register. Instructions without the ‘d’ argument have a destination that is implicit in the instruction; their destination is either the target register being operated on or the W register. While the program memory can be addressed in only one way through the PC, information in the data memory space can be addressed in several ways. For most instructions, the addressing mode is fixed. Other instructions may use up to three modes, depending on which operands are used and whether or not the extended instruction set is enabled. The addressing modes are: • • • • Inherent Literal Direct Indirect An additional addressing mode, Indexed Literal Offset, is available when the extended instruction set is enabled (XINST Configuration bit = 1). Its operation is discussed in more detail in Section 6.6.1 “Indexed Addressing with Literal Offset”. 6.4.3 INDIRECT ADDRESSING 6.4.1 INHERENT AND LITERAL ADDRESSING Many PIC18 control instructions do not need any argument at all; they either perform an operation that globally affects the device, or they operate implicitly on one register. This addressing mode is known as Inherent Addressing. Examples include SLEEP, RESET and DAW. Other instructions work in a similar way, but require an additional explicit argument in the opcode. This is known as Literal Addressing mode, because they require some literal value as an argument. Examples include ADDLW and MOVLW, which respectively, add or move a literal value to the W register. Other examples include CALL and GOTO, which include a 20-bit program memory address. Indirect Addressing allows the user to access a location in data memory without giving a fixed address in the instruction. This is done by using File Select Registers (FSRs) as pointers to the locations to be read or written to. Since the FSRs are themselves located in RAM as SFRs, they can also be directly manipulated under program control. This makes FSRs very useful in implementing data structures such as tables and arrays in data memory. The registers for Indirect Addressing are also implemented with Indirect File Operands (INDFs) that permit automatic manipulation of the pointer value with auto-incrementing, auto-decrementing or offsetting with another value. This allows for efficient code using loops, such as the example of clearing an entire RAM bank in Example 6-5. It also enables users to perform Indexed Addressing and other Stack Pointer operations for program memory in data memory. 6.4.2 DIRECT ADDRESSING EXAMPLE 6-5: Direct Addressing specifies all or part of the source and/or destination address of the operation within the opcode itself. The options are specified by the arguments accompanying the instruction. In the core PIC18 instruction set, bit-oriented and byte-oriented instructions use some version of Direct Addressing by default. All of these instructions include some 8-bit literal address as their LSB. This address specifies either a register address in one of the banks of data RAM (Section 6.3.3 “General Purpose HOW TO CLEAR RAM (BANK 1) USING INDIRECT ADDRESSING FSR0, 0x100 ; POSTINC0 ; ; ; FSR0H, 1 ; ; NEXT ; ; Clear INDF register then inc pointer All done with Bank1? NO, clear next YES, continue NEXT LFSR CLRF BTFSS BRA CONTINUE  2010 Microchip Technology Inc. Preliminary DS39974A-page 101 PIC18F47J13 FAMILY 6.4.3.1 FSR Registers and the INDF Operand (INDF) At the core of Indirect Addressing are three sets of registers: FSR0, FSR1 and FSR2. Each represents a pair of 8-bit registers, FSRnH and FSRnL. The four upper bits of the FSRnH register are not used, so each FSR pair holds a 12-bit value. This represents a value that can address the entire range of the data memory in a linear fashion. The FSR register pairs, then, serve as pointers to data memory locations. Indirect Addressing is accomplished with a set of INDF operands: INDF0 through INDF2. These can be presumed as “virtual” registers; they are mapped in the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L. Instructions that use the INDF registers as operands actually use the contents of their corresponding FSR as a pointer to the instruction’s target. The INDF operand is just a convenient way of using the pointer. Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. FIGURE 6-8: INDIRECT ADDRESSING 000h Bank 0 100h Bank 1 200h Bank 2 Using an instruction with one of the Indirect Addressing registers as the operand.... ADDWF, INDF1, 1 ...uses the 12-bit address stored in the FSR pair associated with that register.... FSR1H:FSR1L 7 0 7 0 300h xxxx1111 11001100 Bank 3 through Bank 13 ...to determine the data memory location to be used in that operation. In this case, the FSR1 pair contains FCCh. This means the contents of location, FCCh, will be added to that of the W register and stored back in FCCh. E00h Bank 14 F00h FFFh Bank 15 Data Memory DS39974A-page 102 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW 6.4.3.3 Operations by FSRs on FSRs In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: • POSTDEC: accesses the FSR value, then automatically decrements it by one thereafter • POSTINC: accesses the FSR value, then automatically increments it by one thereafter • PREINC: increments the FSR value by one, then uses it in the operation • PLUSW: adds the signed value of the W register (range of -128 to +127) to that of the FSR and uses the new value in the operation In this context, accessing an INDF register uses the value in the FSR registers without changing them. Similarly, accessing a PLUSW register gives the FSR value offset by the value in the W register; neither value is actually changed in the operation. Accessing the other virtual registers changes the value of the FSR registers. Operations on the FSRs with POSTDEC, POSTINC and PREINC affect the entire register pair; that is, rollovers of the FSRnL register from FFh to 00h carry over to the FSRnH register. On the other hand, results of these operations do not change the value of any flags in the STATUS register (e.g., Z, N, OV, etc.). The PLUSW register can be used to implement a form of Indexed Addressing in the data memory space. By manipulating the value in the W register, users can reach addresses that are fixed offsets from pointer addresses. In some applications, this can be used to implement some powerful program control structure, such as software stacks, inside of data memory. Indirect Addressing operations that target other FSRs or virtual registers represent special cases. For example, using an FSR to point to one of the virtual registers will not result in successful operations. As a specific case, assume that FSR0H:FSR0L contains FE7h, the address of INDF1. Attempts to read the value of the INDF1, using INDF0 as an operand, will return 00h. Attempts to write to INDF1, using INDF0 as the operand, will result in a NOP. On the other hand, using the virtual registers to write to an FSR pair may not occur as planned. In these cases, the value will be written to the FSR pair but without any incrementing or decrementing. Thus, writing to INDF2 or POSTDEC2 will write the same value to the FSR2H:FSR2L. Since the FSRs are physical registers mapped in the SFR space, they can be manipulated through all direct operations. Users should proceed cautiously when working on these registers, particularly if their code uses Indirect Addressing. Similarly, operations by Indirect Addressing are generally permitted on all other SFRs. Users should exercise appropriate caution that they do not inadvertently change settings that might affect the operation of the device. 6.5 Program Memory and the Extended Instruction Set The operation of program memory is unaffected by the use of the extended instruction set. Enabling the extended instruction set adds five additional two-word commands to the existing PIC18 instruction set: ADDFSR, CALLW, MOVSF, MOVSS and SUBFSR. These instructions are executed as described in Section 6.2.4 “Two-Word Instructions”.  2010 Microchip Technology Inc. Preliminary DS39974A-page 103 PIC18F47J13 FAMILY 6.6 Data Memory and the Extended Instruction Set Under these conditions, the file address of the instruction is not interpreted as the lower byte of an address (used with the BSR in Direct Addressing) or as an 8-bit address in the Access Bank. Instead, the value is interpreted as an offset value to an Address Pointer specified by FSR2. The offset and the contents of FSR2 are added to obtain the target address of the operation. Enabling the PIC18 extended instruction set (XINST Configuration bit = 1) significantly changes certain aspects of data memory and its addressing. Specifically, the use of the Access Bank for many of the core PIC18 instructions is different. This is due to the introduction of a new addressing mode for the data memory space. This mode also alters the behavior of Indirect Addressing using FSR2 and its associated operands. What does not change is just as important. The size of the data memory space is unchanged, as well as its linear addressing. The SFR map remains the same. Core PIC18 instructions can still operate in both Direct and Indirect Addressing mode; inherent and literal instructions do not change at all. Indirect Addressing with FSR0 and FSR1 also remains unchanged. 6.6.2 INSTRUCTIONS AFFECTED BY INDEXED LITERAL OFFSET MODE Any of the core PIC18 instructions that can use Direct Addressing are potentially affected by the Indexed Literal Offset Addressing mode. This includes all byte and bit-oriented instructions, or almost one half of the standard PIC18 instruction set. Instructions that only use Inherent or Literal Addressing modes are unaffected. Additionally, byte and bit-oriented instructions are not affected if they do not use the Access Bank (Access RAM bit is ‘1’) or include a file address of 60h or above. Instructions meeting these criteria will continue to execute as before. A comparison of the different possible addressing modes when the extended instruction set is enabled is provided in Figure 6-9. Those who desire to use byte or bit-oriented instructions in the Indexed Literal Offset mode should note the changes to assembler syntax for this mode. This is described in more detail in Section 28.2.1 “Extended Instruction Syntax”. 6.6.1 INDEXED ADDRESSING WITH LITERAL OFFSET Enabling the PIC18 extended instruction set changes the behavior of Indirect Addressing using the FSR2 register pair and its associated file operands. Under proper conditions, instructions that use the Access Bank, that is, most bit and byte-oriented instructions, can invoke a form of Indexed Addressing using an offset specified in the instruction. This special addressing mode is known as Indexed Addressing with Literal Offset or Indexed Literal Offset mode. When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); and • The file address argument is less than or equal to 5Fh. DS39974A-page 104 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 6-9: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) Example Instruction: ADDWF, f, d, a (Opcode: 0010 01da ffff ffff) When a = 0 and f  60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh. This is the same as locations, F60h to FFFh (Bank 15), of data memory. Locations below 060h are not available in this addressing mode. 000h 060h Bank 0 100h Bank 1 through Bank 14 00h 60h Valid Range for ‘f’ Access RAM Bank 15 F60h SFRs FFFh Data Memory FFh F00h When a = 0 and f  5Fh: The instruction executes in Indexed Literal Offset mode. ‘f’ is interpreted as an offset to the address value in FSR2. The two are added together to obtain the address of the target register for the instruction. The address can be anywhere in the data memory space. Note that in this mode, the correct syntax is: ADDWF [k], d where ‘k’ is the same as ‘f’. 000h Bank 0 060h 100h Bank 1 through Bank 14 FSR2H F00h Bank 15 F60h SFRs FFFh Data Memory FSR2L 001001da ffffffff When a = 1 (all values of f): The instruction executes in Direct mode (also known as Direct Long mode). ‘f’ is interpreted as a location in one of the 16 banks of the data memory space. The bank is designated by the Bank Select Register (BSR). The address can be in any implemented bank in the data memory space. 000h Bank 0 060h 100h Bank 1 through Bank 14 BSR 00000000 001001da ffffffff F00h Bank 15 F60h SFRs FFFh Data Memory  2010 Microchip Technology Inc. Preliminary DS39974A-page 105 PIC18F47J13 FAMILY 6.6.3 MAPPING THE ACCESS BANK IN INDEXED LITERAL OFFSET MODE The use of Indexed Literal Offset Addressing mode effectively changes how the lower part of Access RAM (00h to 5Fh) is mapped. Rather than containing just the contents of the bottom part of Bank 0, this mode maps the contents from Bank 0 and a user-defined “window” that can be located anywhere in the data memory space. The value of FSR2 establishes the lower boundary of the addresses mapped to the window, while the upper boundary is defined by FSR2 plus 95 (5Fh). Addresses in the Access RAM above 5Fh are mapped as previously described (see Section 6.3.2 “Access Bank”). Figure 6-10 provides an example of Access Bank remapping in this addressing mode. Remapping of the Access Bank applies only to operations using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or Indexed Addressing operation that explicitly uses any of the indirect file operands (including FSR2) will continue to operate as standard Indirect Addressing. Any instruction that uses the Access Bank, but includes a register address of greater than 05Fh, will use Direct Addressing and the normal Access Bank map. 6.6.4 BSR IN INDEXED LITERAL OFFSET MODE Although the Access Bank is remapped when the extended instruction set is enabled, the operation of the BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. FIGURE 6-10: Example Situation: REMAPPING THE ACCESS BANK WITH INDEXED LITERAL OFFSET ADDRESSING 000h 05Fh Not Accessible Bank 0 100h 120h 17Fh 200h ADDWF f, d, a FSR2H:FSR2L = 120h Locations in the region from the FSR2 Pointer (120h) to the pointer plus 05Fh (17Fh) are mapped to the bottom of the Access RAM (000h-05Fh). Special Function Registers at F60h through FFFh are mapped to 60h through FFh, as usual. Bank 0 addresses below 5Fh are not available in this mode. They can still be addressed by using the BSR. Window Bank 1 Bank 1 “Window” 00h 5Fh 60h Bank 2 through Bank 14 SFRs FFh Access Bank F00h Bank 15 F60h FFFh SFRs Data Memory DS39974A-page 106 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.0 FLASH PROGRAM MEMORY 7.1 Table Reads and Table Writes The Flash program memory is readable, writable and erasable during normal operation over the entire VDD range. A read from program memory is executed on 1 byte at a time. A write to program memory is executed on blocks of 64 bytes at a time or 2 bytes at a time. Program memory is erased in blocks of 1024 bytes at a time. A bulk erase operation may not be issued from user code. Writing or erasing program memory will cease instruction fetches until the operation is complete. The program memory cannot be accessed during the write or erase, therefore, code cannot execute. An internal programming timer terminates program memory writes and erases. A value written to program memory does not need to be a valid instruction. Executing a program memory location that forms an invalid instruction results in a NOP. In order to read and write program memory, there are two operations that allow the processor to move bytes between the program memory space and the data RAM: • Table Read (TBLRD) • Table Write (TBLWT) The program memory space is 16 bits wide, while the data RAM space is 8 bits wide. Table reads and table writes move data between these two memory spaces through an 8-bit register (TABLAT). Table read operations retrieve data from program memory and place it into the data RAM space. Figure 7-1 illustrates the operation of a table read with program memory and data RAM. Table write operations store data from the data memory space into holding registers in program memory. The procedure to write the contents of the holding registers into program memory is detailed in Section 7.5 “Writing to Flash Program Memory”. Figure 7-2 illustrates the operation of a table write with program memory and data RAM. Table operations work with byte entities. A table block containing data, rather than program instructions, is not required to be word-aligned. Therefore, a table block can start and end at any byte address. If a table write is being used to write executable code into program memory, program instructions will need to be word-aligned. FIGURE 7-1: TABLE READ OPERATION Instruction: TBLRD* Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Program Memory Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory.  2010 Microchip Technology Inc. Preliminary DS39974A-page 107 PIC18F47J13 FAMILY FIGURE 7-2: TABLE WRITE OPERATION Instruction: TBLWT* Program Memory Holding Registers Table Pointer(1) TBLPTRU TBLPTRH TBLPTRL Table Latch (8-bit) TABLAT Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL. The process for physically writing data to the program memory array is discussed in Section 7.5 “Writing to Flash Program Memory”. 7.2 Control Registers Several control registers are used in conjunction with the TBLRD and TBLWT instructions. Those are: • • • • EECON1 register EECON2 register TABLAT register TBLPTR registers The FREE bit, when set, will allow a program memory erase operation. When FREE is set, the erase operation is initiated on the next WR command. When FREE is clear, only writes are enabled. The WREN bit, when set, will allow a write operation. On power-up, the WREN bit is clear. The WRERR bit is set in hardware when the WR bit is set, and cleared when the internal programming timer expires and the write operation is complete. Note: During normal operation, the WRERR is read as ‘1’. This can indicate that a write operation was prematurely terminated by a Reset or a write operation was attempted improperly. 7.2.1 EECON1 AND EECON2 REGISTERS The EECON1 register (Register 7-1) is the control register for memory accesses. The EECON2 register is not a physical register; it is used exclusively in the memory write and erase sequences. Reading EECON2 will read all ‘0’s. The WPROG bit, when set, will allow programming two bytes per word on the execution of the WR command. If this bit is cleared, the WR command will result in programming on a block of 64 bytes. The WR control bit initiates write operations. The bit cannot be cleared, only set, in software. It is cleared in hardware at the completion of the write operation. DS39974A-page 108 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 7-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 S = Settable bit (cannot be cleared in software) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EECON1: EEPROM CONTROL REGISTER 1 (ACCESS FA6h) U-0 — R/W-0 WPROG R/W-0 FREE R/W-x WRERR R/W-0 WREN R/S-0 WR U-0 — bit 0 Unimplemented: Read as ‘0’ WPROG: One Word-Wide Program bit 1 = Program 2 bytes on the next WR command 0 = Program 64 bytes on the next WR command FREE: Flash Erase Enable bit 1 = Perform an erase operation on the next WR command (cleared by hardware after completion of erase) 0 = Perform write-only WRERR: Flash Program Error Flag bit 1 = A write operation is prematurely terminated (any Reset during self-timed programming in normal operation or an improper write attempt) 0 = The write operation completed WREN: Flash Program Write Enable bit 1 = Allows write cycles to Flash program memory 0 = Inhibits write cycles to Flash program memory WR: Write-Control bit 1 = Initiates a program memory erase cycle or write cycle (The operation is self-timed and the bit is cleared by hardware once the write is complete. The WR bit can only be set (not cleared) in software.) 0 = Write cycle is complete Unimplemented: Read as ‘0’ bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 109 PIC18F47J13 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) 7.2.4 TABLE POINTER BOUNDARIES The Table Latch (TABLAT) is an 8-bit register mapped into the Special Function Register (SFR) space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. TBLPTR is used in reads, writes and erases of the Flash program memory. When a TBLRD is executed, all 22 bits of the TBLPTR determine which byte is read from program memory into TABLAT. When a TBLWT is executed, the seven Least Significant bits (LSbs) of the Table Pointer register (TBLPTR) determine which of the 64 program memory holding registers is written to. When the timed write to program memory begins (via the WR bit), the 12 Most Significant bits (MSbs) of the TBLPTR (TBLPTR) determine which program memory block of 1024 bytes is written to. For more information, see Section 7.5 “Writing to Flash Program Memory”. When an erase of program memory is executed, the 12 MSbs of the Table Pointer register point to the 1024-byte block that will be erased. The LSbs are ignored. Figure 7-3 illustrates the relevant boundaries of the TBLPTR based on Flash program memory operations. 7.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory. The TBLPTR comprises three SFR registers: Table Pointer Upper Byte, Table Pointer High Byte and Table Pointer Low Byte (TBLPTRU:TBLPTRH:TBLPTRL). These three registers join to form a 22-bit wide pointer. The low-order 21 bits allow the device to address up to 2 Mbytes of program memory space. The 22nd bit allows access to the Device ID, the User ID and the Configuration bits. The Table Pointer register, TBLPTR, is used by the TBLRD and TBLWT instructions. These instructions can update the TBLPTR in one of four ways based on the table operation. Table 7-1 displays these operations. On the TBLPTRT, these operations only affect the low-order 21 bits. TABLE 7-1: Example TBLRD* TBLWT* TBLRD*+ TBLWT*+ TBLRD*TBLWT*TBLRD+* TBLWT+* TABLE POINTER OPERATIONS WITH TBLRD AND TBLWT INSTRUCTIONS Operation on Table Pointer TBLPTR is not modified TBLPTR is incremented after the read/write TBLPTR is decremented after the read/write TBLPTR is incremented before the read/write FIGURE 7-3: 21 TABLE POINTER BOUNDARIES BASED ON OPERATION TBLPTRU 16 15 TBLPTRH 8 7 TBLPTRL 0 ERASE: TBLPTR TABLE WRITE: TBLPTR TABLE READ: TBLPTR DS39974A-page 110 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.3 Reading the Flash Program Memory The TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, the TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words. The LSb of the address selects between the high and low bytes of the word. Figure 7-4 illustrates the interface between the internal program memory and the TABLAT. The TBLRD instruction is used to retrieve data from program memory and places it into data RAM. Table reads from program memory are performed one byte at a time. FIGURE 7-4: READS FROM FLASH PROGRAM MEMORY Program Memory (Even Byte Address) (Odd Byte Address) TBLPTR = xxxxx1 TBLPTR = xxxxx0 Instruction Register (IR) FETCH TBLRD TABLAT Read Register EXAMPLE 7-1: MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF READ_WORD READING A FLASH PROGRAM MEMORY WORD CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base ; address of the word TBLRD*+ MOVF MOVWF TBLRD*+ MOVF MOVWF TABLAT, W WORD_EVEN TABLAT, W WORD_ODD ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data  2010 Microchip Technology Inc. Preliminary DS39974A-page 111 PIC18F47J13 FAMILY 7.4 Erasing Flash Program Memory 7.4.1 The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the microcontroller itself, a block of 1024 bytes of program memory is erased. The Most Significant 12 bits of the TBLPTR point to the block being erased; TBLPTR are ignored. The EECON1 register commands the erase operation. The WREN bit must be set to enable write operations. The FREE bit is set to select an erase operation. For protection, the write initiate sequence for EECON2 must be used. A long write is necessary for erasing the internal Flash. Instruction execution is Halted while in a long write cycle. The long write will be terminated by the internal programming timer. FLASH PROGRAM MEMORY ERASE SEQUENCE The sequence of events for erasing a block of internal program memory location is: 1. 2. 3. 4. 5. 6. 7. 8. Load Table Pointer register with address of row being erased. Set the WREN and FREE bits (EECON1) to enable the erase operation. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit; this will begin the erase cycle. The CPU will stall for the duration of the erase for TIE (see parameter D133B). Re-enable interrupts. EXAMPLE 7-2: ERASING FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL EECON1, EECON1, INTCON, 0x55 EECON2 0xAA EECON2 EECON1, INTCON, WREN FREE GIE ; load TBLPTR with the base ; address of the memory block ERASE_ROW BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts Required Sequence WR GIE DS39974A-page 112 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.5 Writing to Flash Program Memory The programming block is 32 words or 64 bytes. Programming one word or 2 bytes at a time is also supported. Table writes are used internally to load the holding registers needed to program the Flash memory. There are 64 holding registers used by the table writes for programming. Since the Table Latch (TABLAT) is only a single byte, the TBLWT instruction may need to be executed 64 times for each programming operation (if WPROG = 0). All of the table write operations will essentially be short writes because only the holding registers are written. At the end of updating the 64 holding registers, the EECON1 register must be written to in order to start the programming operation with a long write. The long write is necessary for programming the internal Flash. Instruction execution is Halted while in a long write cycle. The long write will be terminated by the internal programming timer. The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC® devices, devices of the PIC18F47J13 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. 2: To maintain the endurance of the program memory cells, each Flash byte should not be programmed more than once between erase operations. Before attempting to modify the contents of the target cell a second time, an erase of the target page, or a bulk erase of the entire memory, must be performed. FIGURE 7-5: TABLE WRITES TO FLASH PROGRAM MEMORY TABLAT Write Register 8 TBLPTR = xxxxx0 Holding Register TBLPTR = xxxxx1 8 TBLPTR = xxxxx2 8 TBLPTR = xxxx3F 8 Holding Register Holding Register Holding Register Program Memory 7.5.1 FLASH PROGRAM MEMORY WRITE SEQUENCE The sequence of events for programming an internal program memory location should be: 1. 2. 3. 4. 5. 6. 7. Read 1024 bytes into RAM. Update data values in RAM as necessary. Load the Table Pointer register with address being erased. Execute the erase procedure. Load the Table Pointer register with the address of the first byte being written, minus 1. Write the 64 bytes into the holding registers with auto-increment. Set the WREN bit (EECON1) to enable byte writes. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit; this will begin the write cycle. The CPU will stall for the duration of the write for TIW (see parameter D133A). 13. Re-enable interrupts. 14. Repeat Steps 6 through 13 until all 1024 bytes are written to program memory. 15. Verify the memory (table read). An example of the required code is provided in Example 7-3 on the following page. Note: Before setting the WR bit, the Table Pointer address needs to be within the intended address range of the 64 bytes in the holding register. 8. 9. 10. 11. 12.  2010 Microchip Technology Inc. Preliminary DS39974A-page 113 PIC18F47J13 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF ERASE_BLOCK BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF MOVLW MOVWF RESTART_BUFFER MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF FILL_BUFFER ... WRITE_BUFFER MOVLW MOVWF WRITE_BYTE_TO_HREGS MOVFF MOVWF TBLWT+* D'64' COUNTER POSTINC0, WREG TABLAT ; number of bytes in holding register ; read the new data from I2C, SPI, ; PSP, USART, etc. D'64' COUNTER BUFFER_ADDR_HIGH FSR0H BUFFER_ADDR_LOW FSR0L EECON1, WREN EECON1, FREE INTCON, GIE 0x55 EECON2 0xAA EECON2 EECON1, WR INTCON, GIE D'16' WRITE_COUNTER ; enable write to memory ; enable Erase operation ; disable interrupts ; write 55h ; write 0AAh ; start erase (CPU stall) ; re-enable interrupts ; Need to write 16 blocks of 64 to write ; one erase block of 1024 CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL ; Load TBLPTR with the base address ; of the memory block, minus 1 ; point to buffer DECFSZ COUNTER BRA WRITE_BYTE_TO_HREGS PROGRAM_MEMORY BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF EECON1, INTCON, 0x55 EECON2 0xAA EECON2 EECON1, INTCON, EECON1, WREN GIE ; ; ; ; ; get low byte of buffer data present data to table latch write data, perform a short write to internal TBLWT holding register. loop until buffers are full ; enable write to memory ; disable interrupts ; write 55h ; ; ; ; write 0AAh start program (CPU stall) re-enable interrupts disable write to memory Required Sequence WR GIE WREN DECFSZ WRITE_COUNTER BRA RESTART_BUFFER ; done with one write cycle ; if not done replacing the erase block DS39974A-page 114 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 7.5.2 FLASH PROGRAM MEMORY WRITE SEQUENCE (WORD PROGRAMMING) 3. on the second table write.) Set the WREN bit (EECON1) to enable writes and the WPROG bit (EECON1) to select Word Write mode. Disable interrupts. Write 55h to EECON2. Write 0AAh to EECON2. Set the WR bit; this will begin the write cycle. The CPU will stall for the duration of the write for TIW (see parameter D133A). Re-enable interrupts. The PIC18F47J13 family of devices has a feature that allows programming a single word (two bytes). This feature is enabled when the WPROG bit is set. If the memory location is already erased, the following sequence is required to enable this feature: 1. Load the Table Pointer register with the address of the data to be written. (It must be an even address.) Write the 2 bytes into the holding registers by performing table writes. (Do not post-increment 4. 5. 6. 7. 8. 9. 2. EXAMPLE 7-4: SINGLE-WORD WRITE TO FLASH PROGRAM MEMORY MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF MOVLW MOVWF TBLWT*+ MOVLW MOVWF TBLWT* CODE_ADDR_UPPER TBLPTRU CODE_ADDR_HIGH TBLPTRH CODE_ADDR_LOW TBLPTRL DATA0 TABLAT DATA1 TABLAT ; LSB of word to be written ; Load TBLPTR with the base address ; The table pointer must be loaded with an even address ; MSB of word to be written ; The last table write must not increment the table pointer! The table pointer needs to point to the MSB before starting the write operation. PROGRAM_MEMORY BSF BSF BCF MOVLW MOVWF MOVLW MOVWF BSF BSF BCF BCF EECON1, EECON1, INTCON, 0x55 EECON2 0xAA EECON2 EECON1, INTCON, EECON1, EECON1, WPROG WREN GIE ; enable single word write ; enable write to memory ; disable interrupts ; write 55h ; ; ; ; ; write AAh start program (CPU stall) re-enable interrupts disable single word write disable write to memory Required Sequence WR GIE WPROG WREN  2010 Microchip Technology Inc. Preliminary DS39974A-page 115 PIC18F47J13 FAMILY 7.5.3 WRITE VERIFY Depending on the application, good programming practice may dictate that the value written to the memory should be verified against the original value. This should be used in applications where excessive writes can stress bits near the specification limit. reprogrammed if needed. If the write operation is interrupted by a MCLR Reset, or a WDT time-out Reset during normal operation, the user can check the WRERR bit and rewrite the location(s) as needed. 7.6 7.5.4 UNEXPECTED TERMINATION OF WRITE OPERATION Flash Program Operation During Code Protection If a write is terminated by an unplanned event, such as loss of power or an unexpected Reset, the memory location just programmed should be verified and See Section 27.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. TABLE 7-2: Name TBLPTRU TBPLTRH TBLPTRL TABLAT INTCON EECON2 EECON1 REGISTERS ASSOCIATED WITH PROGRAM FLASH MEMORY Bit 7 — Bit 6 — Bit 5 bit 21 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Program Memory Table Pointer Upper Byte (TBLPTR) Program Memory Table Pointer High Byte (TBLPTR) Program Memory Table Pointer Low Byte (TBLPTR) Program Memory Table Latch GIE/GIEH — PEIE/GIEL — TMR0IE WPROG INT0IE FREE RBIE WRERR TMR0IF WREN INT0IF WR RBIF — Program Memory Control Register 2 (not a physical register) Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during Flash program memory access. DS39974A-page 116 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 8.0 8.1 8 x 8 HARDWARE MULTIPLIER Introduction EXAMPLE 8-1: MOVF MULWF ARG1, W ARG2 8 x 8 UNSIGNED MULTIPLY ROUTINE ; ; ARG1 * ARG2 -> ; PRODH:PRODL All PIC18 devices include an 8 x 8 hardware multiplier as part of the ALU. The multiplier performs an unsigned operation and yields a 16-bit result that is stored in the product register pair, PRODH:PRODL. The multiplier’s operation does not affect any flags in the STATUS register. Making multiplication a hardware operation allows it to be completed in a single instruction cycle. This has the advantages of higher computational throughput and reduced code size for multiplication algorithms and allows the PIC18 devices to be used in many applications previously reserved for digital signal processors. Table 8-1 provides a comparison of various hardware and software multiply operations, along with the savings in memory and execution time. EXAMPLE 8-2: MOVF MULWF BTFSC SUBWF MOVF BTFSC SUBWF ARG1, W ARG2 ARG2, SB PRODH, F ARG2, W ARG1, SB PRODH, F 8 x 8 SIGNED MULTIPLY ROUTINE ; ; ; ; ; ARG1 * ARG2 -> PRODH:PRODL Test Sign Bit PRODH = PRODH - ARG1 ; Test Sign Bit ; PRODH = PRODH ; - ARG2 8.2 Operation Example 8-1 provides the instruction sequence for an 8 x 8 unsigned multiplication. Only one instruction is required when one of the arguments is already loaded in the WREG register. Example 8-2 provides the instruction sequence for an 8 x 8 signed multiplication. To account for the sign bits of the arguments, each argument’s Most Significant bit (MSb) is tested and the appropriate subtractions are done. TABLE 8-1: Routine PERFORMANCE COMPARISON FOR VARIOUS MULTIPLY OPERATIONS Multiply Method Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Without hardware multiply Hardware multiply Program Memory (Words) 13 1 33 6 21 28 52 35 Cycles (Max) 69 1 91 6 242 28 254 40 Time @ 48 MHz 5.7 s 83.3 ns 7.5 s 500 ns 20.1 s 2.3 s 21.6 s 3.3 s @ 10 MHz 27.6 s 400 ns 36.4 s 2.4 s 96.8 s 11.2 s 102.6 s 16.0 s @ 4 MHz 69 s 1 s 91 s 6 s 242 s 28 s 254 s 40 s 8 x 8 unsigned 8 x 8 signed 16 x 16 unsigned 16 x 16 signed  2010 Microchip Technology Inc. Preliminary DS39974A-page 117 PIC18F47J13 FAMILY Example 8-3 provides the instruction sequence for a 16 x 16 unsigned multiplication. Equation 8-1 provides the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8-2: 16 x 16 SIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L · ARG2H:ARG2L (ARG1H · ARG2H · 216) + (ARG1H · ARG2L · 28) + (ARG1L · ARG2H · 28) + (ARG1L · ARG2L) + (-1 · ARG2H · ARG1H:ARG1L · 216) + (-1 · ARG1H · ARG2H:ARG2L · 216) RES3:RES0 EQUATION 8-1: 16 x 16 UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L · ARG2H:ARG2L (ARG1H · ARG2H · 216) + (ARG1H · ARG2L · 28) + (ARG1L · ARG2H · 28) + (ARG1L · ARG2L) = = RES3:RES0 = = EXAMPLE 8-4: MOVF MULWF MOVFF MOVFF MOVF MULWF MOVFF MOVFF MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC BTFSS BRA MOVF SUBWF MOVF SUBWFB SIGN_ARG1 BTFSS BRA MOVF SUBWF MOVF SUBWFB CONT_CODE : 16 x 16 SIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L -> ; PRODH:PRODL ; ; EXAMPLE 8-3: MOVF MULWF MOVFF MOVFF MOVF MULWF MOVFF MOVFF MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC MOVF MULWF MOVF ADDWF MOVF ADDWFC CLRF ADDWFC 16 x 16 UNSIGNED MULTIPLY ROUTINE ; ARG1L * ARG2L-> ; PRODH:PRODL ; ; ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG2H, 7 SIGN_ARG1 ARG1L, W RES2 ARG1H, W RES3 ARG1L, W ARG2L PRODH, RES1 PRODL, RES0 ARG1H, W ARG2H PRODH, RES3 PRODL, RES2 ARG1L, W ARG2H PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ARG1H, W ARG2L PRODL, W RES1, F PRODH, W RES2, F WREG RES3, F ; ARG1H * ARG2H-> ; PRODH:PRODL ; ; ; ARG1H * ARG2H -> ; PRODH:PRODL ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H-> PRODH:PRODL Add cross products ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ARG1L * ARG2H -> PRODH:PRODL Add cross products ARG1H * ARG2L -> PRODH:PRODL Add cross products ARG1H * ARG2L-> PRODH:PRODL Add cross products Example 8-4 provides the sequence to do a 16 x 16 signed multiply. Equation 8-2 provides the algorithm used. The 32-bit result is stored in four registers (RES3:RES0). To account for the sign bits of the arguments, the MSb for each argument pair is tested and the appropriate subtractions are done. ; ARG2H:ARG2L neg? ; no, check ARG1 ; ; ; ARG1H, 7 CONT_CODE ARG2L, W RES2 ARG2H, W RES3 ; ARG1H:ARG1L neg? ; no, done ; ; ; DS39974A-page 118 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 9.0 INTERRUPTS Devices of the PIC18F47J13 family have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress. There are 19 registers, which are used to control interrupt operation. These registers are: • • • • • • • RCON INTCON INTCON2 INTCON3 PIR1, PIR2, PIR3, PIR4, PIR5 PIE1, PIE2, PIE3, PIE4, PIE5 IPR1, IPR2, IPR3, IPR4, IPR5 When the IPEN bit is cleared (default state), the interrupt priority feature is disabled and interrupts are compatible with PIC® mid-range devices. In Compatibility mode, the interrupt priority bits for each source have no effect. INTCON is the PEIE bit, which enables/disables all peripheral interrupt sources. INTCON is the GIE bit, which enables/disables all interrupt sources. All interrupts branch to address 0008h in Compatibility mode. When an interrupt is responded to, the global interrupt enable bit is cleared to disable further interrupts. If the IPEN bit is cleared, this is the GIE bit. If interrupt priority levels are used, this will be either the GIEH or GIEL bit. High-priority interrupt sources can interrupt a low-priority interrupt. Low-priority interrupts are not processed while high-priority interrupts are in progress. The return address is pushed onto the stack and the PC is loaded with the interrupt vector address (0008h or 0018h). Once in the Interrupt Service Routine (ISR), the source(s) of the interrupt can be determined by polling the interrupt flag bits. The interrupt flag bits must be cleared in software before re-enabling interrupts to avoid recursive interrupts. The “return from interrupt” instruction, RETFIE, exits the interrupt routine and sets the GIE bit (GIEH or GIEL if priority levels are used), which re-enables interrupts. For external interrupt events, such as the INTx pins or the PORTB input change interrupt, the interrupt latency will be three to four instruction cycles. The exact latency is the same for one or two-cycle instructions. Individual interrupt flag bits are set regardless of the status of their corresponding enable bit or the GIE bit. Note: Do not use the MOVFF instruction to modify any of the Interrupt Control registers while any interrupt is enabled. Doing so may cause erratic microcontroller behavior. It is recommended that the Microchip header files supplied with MPLAB® IDE be used for the symbolic bit names in these registers. This allows the assembler/compiler to automatically take care of the placement of these bits within the specified register. In general, interrupt sources have three bits to control their operation. They are: • Flag bit to indicate that an interrupt event occurred • Enable bit that allows program execution to branch to the interrupt vector address when the flag bit is set • Priority bit to select high priority or low priority The interrupt priority feature is enabled by setting the IPEN bit (RCON). When interrupt priority is enabled, there are two bits which enable interrupts globally. Setting the GIEH bit (INTCON) enables all interrupts that have the priority bit set (high priority). Setting the GIEL bit (INTCON) enables all interrupts that have the priority bit cleared (low priority). When the interrupt flag, enable bit and appropriate global interrupt enable bit are set, the interrupt will vector immediately to address, 0008h or 0018h, depending on the priority bit setting. Individual interrupts can be disabled through their corresponding enable bits.  2010 Microchip Technology Inc. Preliminary DS39974A-page 119 PIC18F47J13 FAMILY FIGURE 9-1: PIC18F47J13 FAMILY INTERRUPT LOGIC TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT0IF INT0IE INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP IPEN IPEN PEIE/GIEL IPEN High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 PIR4 PIE4 IPR4 PIR5 PIE5 IPR5 Wake-up if in Idle or Sleep modes PIR4 PIE4 IPR4 PIR5 PIE5 IPR5 PIR1 PIE1 IPR1 PIR2 PIE2 IPR2 PIR3 PIE3 IPR3 Interrupt to CPU Vector to Location 0008h GIE/GIEH TMR0IF TMR0IE TMR0IP RBIF RBIE RBIP INT1IF INT1IE INT1IP INT2IF INT2IE INT2IP INT3IF INT3IE INT3IP IPEN Interrupt to CPU Vector to Location 0018h GIE/GIEH PEIE/GIEL DS39974A-page 120 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 9.1 INTCON Registers Note: The INTCON registers are readable and writable registers, which contain various enable, priority and flag bits. Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. REGISTER 9-1: R/W-0 GIE/GIEH bit 7 Legend: R = Readable bit -n = Value at POR bit 7 INTCON: INTERRUPT CONTROL REGISTER (ACCESS FF2h) R/W-0 R/W-0 TMR0IE R/W-0 INT0IE R/W-0 RBIE R/W-0 TMR0IF R/W-0 INT0IF R/W-x RBIF(1) bit 0 PEIE/GIEL W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GIE/GIEH: Global Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked interrupts 0 = Disables all interrupts When IPEN = 1: 1 = Enables all high-priority interrupts 0 = Disables all interrupts PEIE/GIEL: Peripheral Interrupt Enable bit When IPEN = 0: 1 = Enables all unmasked peripheral interrupts 0 = Disables all peripheral interrupts When IPEN = 1: 1 = Enables all low-priority peripheral interrupts 0 = Disables all low-priority peripheral interrupts TMR0IE: TMR0 Overflow Interrupt Enable bit 1 = Enables the TMR0 overflow interrupt 0 = Disables the TMR0 overflow interrupt INT0IE: INT0 External Interrupt Enable bit 1 = Enables the INT0 external interrupt 0 = Disables the INT0 external interrupt RBIE: RB Port Change Interrupt Enable bit 1 = Enables the RB port change interrupt 0 = Disables the RB port change interrupt TMR0IF: TMR0 Overflow Interrupt Flag bit 1 = The TMR0 register has overflowed (must be cleared in software) 0 = The TMR0 register did not overflow INT0IF: INT0 External Interrupt Flag bit 1 = The INT0 external interrupt occurred (must be cleared in software) 0 = The INT0 external interrupt did not occur RBIF: RB Port Change Interrupt Flag bit(1) 1 = At least one of the RB pins changed state (must be cleared in software) 0 = None of the RB pins have changed state A mismatch condition will continue to set this bit. Reading PORTB and waiting 1 TCY will end the mismatch condition and allow the bit to be cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 121 PIC18F47J13 FAMILY REGISTER 9-2: R/W-1 RBPU bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown INTCON2: INTERRUPT CONTROL REGISTER 2 (ACCESS FF1h) R/W-1 R/W-1 INTEDG1 R/W-1 INTEDG2 R/W-1 INTEDG3 R/W-1 TMR0IP R/W-1 INT3IP R/W-1 RBIP bit 0 INTEDG0 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG1: External Interrupt 1 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG2: External Interrupt 2 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge INTEDG3: External Interrupt 3 Edge Select bit 1 = Interrupt on rising edge 0 = Interrupt on falling edge TMR0IP: TMR0 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority INT3IP: INT3 External Interrupt Priority bit 1 = High priority 0 = Low priority RBIP: RB Port Change Interrupt Priority bit 1 = High priority 0 = Low priority Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: DS39974A-page 122 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 9-3: R/W-1 INT2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown INTCON3: INTERRUPT CONTROL REGISTER 3 (ACCESS FF0h) R/W-1 INT1IP R/W-0 INT3IE R/W-0 INT2IE R/W-0 INT1IE R/W-0 INT3IF R/W-0 INT2IF R/W-0 INT1IF bit 0 INT2IP: INT2 External Interrupt Priority bit 1 = High priority 0 = Low priority INT1IP: INT1 External Interrupt Priority bit 1 = High priority 0 = Low priority INT3IE: INT3 External Interrupt Enable bit 1 = Enables the INT3 external interrupt 0 = Disables the INT3 external interrupt INT2IE: INT2 External Interrupt Enable bit 1 = Enables the INT2 external interrupt 0 = Disables the INT2 external interrupt INT1IE: INT1 External Interrupt Enable bit 1 = Enables the INT1 external interrupt 0 = Disables the INT1 external interrupt INT3IF: INT3 External Interrupt Flag bit 1 = The INT3 external interrupt occurred (must be cleared in software) 0 = The INT3 external interrupt did not occur INT2IF: INT2 External Interrupt Flag bit 1 = The INT2 external interrupt occurred (must be cleared in software) 0 = The INT2 external interrupt did not occur INT1IF: INT1 External Interrupt Flag bit 1 = The INT1 external interrupt occurred (must be cleared in software) 0 = The INT1 external interrupt did not occur Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note:  2010 Microchip Technology Inc. Preliminary DS39974A-page 123 PIC18F47J13 FAMILY 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). Note 1: Interrupt flag bits are set when an interrupt condition occurs, regardless of the state of its corresponding enable bit or the Global Interrupt Enable bit, GIE (INTCON). 2: User software should ensure the appropriate interrupt flag bits are cleared prior to enabling an interrupt and after servicing that interrupt. REGISTER 9-4: R/W-0 PMPIF(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 (ACCESS F9Eh) R/W-0 ADIF R-0 RC1IF R-0 TX1IF R/W-0 SSP1IF R/W-0 CCP1IF R/W-0 TMR2IF R/W-0 TMR1IF bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMPIF: Parallel Master Port Read/Write Interrupt Flag bit(1) 1 = A read or a write operation has taken place (must be cleared in software) 0 = No read or write has occurred ADIF: A/D Converter Interrupt Flag bit 1 = An A/D conversion completed (must be cleared in software) 0 = The A/D conversion is not complete RC1IF: EUSART1 Receive Interrupt Flag bit 1 = The EUSART1 receive buffer, RCREG1, is full (cleared when RCREG1 is read) 0 = The EUSART1 receive buffer is empty TX1IF: EUSART1 Transmit Interrupt Flag bit 1 = The EUSART1 transmit buffer, TXREG1, is empty (cleared when TXREG1 is written) 0 = The EUSART1 transmit buffer is full SSP1IF: Master Synchronous Serial Port 1 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive CCP1IF: ECCP1 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. TMR2IF: TMR2 to PR2 Match Interrupt Flag bit 1 = TMR2 to PR2 match occurred (must be cleared in software) 0 = No TMR2 to PR2 match occurred TMR1IF: TMR1 Overflow Interrupt Flag bit 1 = TMR1 register overflowed (must be cleared in software) 0 = TMR1 register did not overflow These bits are unimplemented on 28-pin devices. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39974A-page 124 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 9-5: R/W-0 OSCFIF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIR2: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 2 (ACCESS FA1h) R/W-0 CM2IF R/W-0 CM1IF U-0 — R/W-0 BCL1IF R/W-0 HLVDIF R/W-0 TMR3IF R/W-0 CCP2IF bit 0 OSCFIF: Oscillator Fail Interrupt Flag bit 1 = The device oscillator failed, clock input has changed to INTOSC (must be cleared in software) 0 = The device clock operating CM2IF: Comparator 2 Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed CM1IF: Comparator 1 Interrupt Flag bit 1 = The comparator input has changed (must be cleared in software) 0 = The comparator input has not changed Unimplemented: Read as ‘0’ BCL1IF: Bus Collision Interrupt Flag bit (MSSP1 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred HLVDIF: High/Low-Voltage Detect (HLVD) Interrupt Flag bit 1 = A High/Low-Voltage condition occurred (must be cleared in software) 0 = An HLVD event has not occurred TMR3IF: TMR3 Overflow Interrupt Flag bit 1 = The TMR3 register overflowed (must be cleared in software) 0 = The TMR3 register did not overflow CCP2IF: ECCP2 Interrupt Flag bit Capture mode: 1 = A TMR1/TMR3 register capture occurred (must be cleared in software) 0 = No TMR1/TMR3 register capture occurred Compare mode: 1 = A TMR1/TMR3 register compare match occurred (must be cleared in software) 0 = No TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 125 PIC18F47J13 FAMILY REGISTER 9-6: R/W-0 SSP2IF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 (ACCESS FA4h) R/W-0 BCL2IF R-0 RC2IF R-0 TX2IF R/W-0 TMR4IF R/W-0 CTMUIF R/W-0 TMR3GIF R/W-0 RTCCIF bit 0 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) 0 = Waiting to transmit/receive BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module) 1 = A bus collision occurred (must be cleared in software) 0 = No bus collision occurred RC2IF: EUSART2 Receive Interrupt Flag bit 1 = The EUSART2 receive buffer, RCREG2, is full (cleared when RCREG2 is read) 0 = The EUSART2 receive buffer is empty TX2IF: EUSART2 Transmit Interrupt Flag bit 1 = The EUSART2 transmit buffer, TXREG2, is empty (cleared when TXREG2 is written) 0 = The EUSART2 transmit buffer is full TMR4IF: TMR4 to PR4 Match Interrupt Flag bit 1 = A TMR4 to PR4 match occurred (must be cleared in software) 0 = No TMR4 to PR4 match occurred CTMUIF: Charge Time Measurement Unit Interrupt Flag bit 1 = A CTMU event has occurred (must be cleared in software) 0 = A CTMU event has not occurred TMR3GIF: Timer3 Gate Event Interrupt Flag bit 1 = A Timer3 gate event completed (must be cleared in software) 0 = No Timer3 gate event completed RTCCIF: RTCC Interrupt Flag bit 1 = An RTCC interrupt occurred (must be cleared in software) 0 = No RTCC interrupt occurred bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 126 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 9-7: R/W-0 CCP10IF bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIR4: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 4 (ACCESS F8Fh) R/W-0 CCP9IF R/W-0 CCP8IF R/W-0 CCP7IF R/W-0 CCP6IF R/W-0 CCP5IF R/W-0 CCP4IF R/W-0 CCP3IF bit 0 CCP10IF:CCP4IF: CCP Interrupt Flag bits Capture Mode 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Unused in this mode. CCP3IF: ECCP3 Interrupt Flag bit Capture Mode 1 = A TMR register capture occurred (must be cleared in software) 0 = No TMR register capture occurred Compare Mode 1 = A TMR register compare match occurred (must be cleared in software) 0 = No TMR register compare match occurred PWM Mode Unused in this mode. bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 127 PIC18F47J13 FAMILY REGISTER 9-8: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIR5: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 5 (ACCESS F98h) U-0 — R-0 CM3IF R/W-0 TMR8IF R/W-0 TMR6IF R/W-0 TMR5IF R/W-0 TMR5GIF R/W-0 TMR1GIF bit 0 Unimplemented: Read as ‘0’ CM3IF: Comparator Interrupt Flag bit 1 = Comparator 3 input has changed (must be cleared in software) 0 = Comparator 3 input has not changed TMR8IF: TMR8 to PR8 Match Interrupt Flag bit 1 = TMR8 to PR8 match occurred (must be cleared in software) 0 = No TMR8 to PR8 match occurred TMR6IF: TMR6 to PR6 Match Interrupt Flag bit 1 = TMR6 to PR6 match occurred (must be cleared in software) 0 = No TMR6 to PR6 match occurred TMR5IF: TMR3 Overflow Interrupt Flag bit 1 = TMR3 register overflowed (must be cleared in software) 0 = TMR3 register did not overflow TMR5GIF: TMR5 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate interrupt occurred TMR1GIF: TMR5 Gate Interrupt Flag bits 1 = TMR gate interrupt occurred (must be cleared in software) 0 = No TMR gate interrupt occurred bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 128 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 9.3 PIE Registers The PIE registers contain the individual enable bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Enable registers (PIE1, PIE2, PIE3). When IPEN = 0, the PEIE bit must be set to enable any of these peripheral interrupts. REGISTER 9-9: R/W-0 PMPIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 (1) PIE1: PERIPHERAL INTERRUPT ENABLE REGISTER 1 (ACCESS F9Dh) R/W-0 ADIE R/W-0 RC1IE R/W-0 TX1IE R/W-0 SSP1IE R/W-0 CCP1IE R/W-0 TMR2IE R/W-0 TMR1IE bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMPIE: Parallel Master Port Read/Write Interrupt Enable bit(1) 1 = Enables the PMP read/write interrupt 0 = Disables the PMP read/write interrupt ADIE: A/D Converter Interrupt Enable bit 1 = Enables the A/D interrupt 0 = Disables the A/D interrupt RC1IE: EUSART1 Receive Interrupt Enable bit 1 = Enables the EUSART1 receive interrupt 0 = Disables the EUSART1 receive interrupt TX1IE: EUSART1 Transmit Interrupt Enable bit 1 = Enables the EUSART1 transmit interrupt 0 = Disables the EUSART1 transmit interrupt SSP1IE: Master Synchronous Serial Port 1 Interrupt Enable bit 1 = Enables the MSSP1 interrupt 0 = Disables the MSSP1 interrupt CCP1IE: ECCP1 Interrupt Enable bit 1 = Enables the ECCP1 interrupt 0 = Disables the ECCP1 interrupt TMR2IE: TMR2 to PR2 Match Interrupt Enable bit 1 = Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt These bits are unimplemented on 28-pin devices. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 129 PIC18F47J13 FAMILY REGISTER 9-10: R/W-0 OSCFIE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 (ACCESS FA0h) R/W-0 CM1IE U-0 — R/W-0 BCL1IE R/W-0 HLVDIE R/W-0 TMR3IE R/W-0 CCP2IE bit 0 R/W-0 CM2IE OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled CM2IE: Comparator 2 Interrupt Enable bit 1 = Enabled 0 = Disabled CM1IE: Comparator 1 Interrupt Enable bit 1 = Enabled 0 = Disabled Unimplemented: Read as ‘0’ BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) 1 = Enabled 0 = Disabled HLVDIE: High/Low-Voltage Detect Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3IE: TMR3 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled CCP2IE: ECCP2 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 130 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 9-11: R/W-0 SSP2IE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIE3: PERIPHERAL INTERRUPT ENABLE REGISTER 3 (ACCESS FA3h) R/W-0 RC2IE R/W-0 TX2IE R/W-0 TMR4IE R/W-0 CTMUIE R/W-0 TMR3GIE R/W-0 RTCCIE bit 0 R/W-0 BCL2IE SSP2IE: Master Synchronous Serial Port 2 Interrupt Enable bit 1 = Enabled 0 = Disabled BCL2IE: Bus Collision Interrupt Enable bit (MSSP2 module) 1 = Enabled 0 = Disabled RC2IE: EUSART2 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TX2IE: EUSART2 Transmit Interrupt Enable bit 1 = Enabled 0 = Disabled TMR4IE: TMR4 to PR4 Match Interrupt Enable bit 1 = Enabled 0 = Disabled CTMUIE: Charge Time Measurement Unit (CTMU) Interrupt Enable bit 1 = Enabled 0 = Disabled TMR3GIE: Timer3 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled RTCCIE: RTCC Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 131 PIC18F47J13 FAMILY REGISTER 9-12: R/W-0 CCP10IE bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PIE4: PERIPHERAL INTERRUPT ENABLE REGISTER 4 (ACCESS F8Eh) R/W-0 CCP8IE R/W-0 CCP7IE R/W-0 CCP6IE R/W-0 CCP5IE R/W-0 CCP4IE R/W-0 CCP3IE bit 0 R/W-0 CCP9IE CCP10IE:CCP4IE: CCP Interrupt Enable bits 1 = Enabled 0 = Disabled CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 REGISTER 9-13: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 PIE5: PERIPHERAL INTERRUPT ENABLE REGISTER 5 (ACCESS F91h) U-0 — R/W-0 CM3IE R/W-0 TMR8IE R/W-0 TMR6IE R/W-0 TMR5IE R/W-0 TMR5GIE R/W-0 TMR1GIE bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CM3IE: Comparator 3 Receive Interrupt Enable bit 1 = Enabled 0 = Disabled TMR8IE: TMR8 to PR8 Match Interrupt Enable bit 1 = Enabled 0 = Disabled TMR6IE: TMR6 to PR6 Match Interrupt Enable bit 1 = Enabled 0 = Disabled TMR5IE: TMR5 Overflow Interrupt Enable bit 1 = Enabled 0 = Disabled TMR5GIE: TMR5 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled TMR1GIE: TMR1 Gate Interrupt Enable bit 1 = Enabled 0 = Disabled bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 132 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set. REGISTER 9-14: R/W-1 PMPIP(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 IPR1: PERIPHERAL INTERRUPT PRIORITY REGISTER 1 (ACCESS F9Fh) R/W-1 RC1IP R/W-1 TX1IP R/W-1 SSP1IP R/W-1 CCP1IP R/W-1 TMR2IP R/W-1 TMR1IP bit 0 ADIP R/W-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMPIP: Parallel Master Port Read/Write Interrupt Priority bit(1) 1 = High priority 0 = Low priority ADIP: A/D Converter Interrupt Priority bit 1 = High priority 0 = Low priority RC1IP: EUSART1 Receive Interrupt Priority bit 1 = High priority 0 = Low priority TX1IP: EUSART1 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 SSP1IP: Master Synchronous Serial Port Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority CCP1IP: ECCP1 Interrupt Priority bit 1 = High priority 0 = Low priority TMR2IP: TMR2 to PR2 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR1IP: TMR1 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority These bits are unimplemented on 28-pin devices. bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 133 PIC18F47J13 FAMILY REGISTER 9-15: R/W-1 OSCFIP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPR2: PERIPHERAL INTERRUPT PRIORITY REGISTER 2 (ACCESS FA2h) R/W-1 CM1IP U-0 — R/W-1 BCL1IP R/W-1 HLVDIP R/W-1 TMR3IP R/W-1 CCP2IP bit 0 R/W-1 CM2IP OSCFIP: Oscillator Fail Interrupt Priority bit 1 = High priority 0 = Low priority CM2IP: Comparator 2 Interrupt Priority bit 1 = High priority 0 = Low priority C12IP: Comparator 1 Interrupt Priority bit 1 = High priority 0 = Low priority Unimplemented: Read as ‘0’ BCL1IP: Bus Collision Interrupt Priority bit (MSSP1 module) 1 = High priority 0 = Low priority HLVDIP: High/Low-Voltage Detect Interrupt Priority bit 1 = High priority 0 = Low priority TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 134 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 9-16: R/W-1 SSP2IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 (ACCESS FA5h) R/W-1 RC2IP R/W-1 TX2IP R/W-1 TMR4IP R/W-1 CTMUIP R/W-1 TMR3GIP R/W-1 RTCCIP bit 0 R/W-1 BCL2IP SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module) 1 = High priority 0 = Low priority RC2IP: EUSART2 Receive Interrupt Priority bit 1 = High priority 0 = Low priority TX2IP: EUSART2 Transmit Interrupt Priority bit 1 = High priority 0 = Low priority TMR4IE: TMR4 to PR4 Interrupt Priority bit 1 = High priority 0 = Low priority CTMUIP: Charge Time Measurement Unit (CTMU) Interrupt Priority bit 1 = High priority 0 = Low priority TMR3GIP: Timer3 Gate Interrupt Priority bit 1 = High priority 0 = Low priority RTCCIP: RTCC Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 135 PIC18F47J13 FAMILY REGISTER 9-17: R/W-1 CCP10IP bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPR4: PERIPHERAL INTERRUPT PRIORITY REGISTER 4 (ACCESS F90h) R/W-1 CCP8IP R/W-1 CCP7IP R/W-1 CCP6IP R/W-1 CCP5IP R/W-1 CCP4IP R/W-1 CCP3IP bit 0 R/W-1 CCP9IP CCP10IP:CCP4IP: CCP Interrupt Priority bits 1 = High priority 0 = Low priority CCP3IP: ECCP3 Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 REGISTER 9-18: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5 IPR5: PERIPHERAL INTERRUPT PRIORITY REGISTER 5 (ACCESS F99h) U-0 — R/W-1 CM3IP R/W-1 TMR8IP R/W-1 TMR6IP R/W-1 TMR5IP R/W-1 TMR5GIP R/W-1 TMR1GIP bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CM3IP: Comparator 3 Interrupt Priority bit 1 = High priority 0 = Low priority TMR8IP: TMR8 to PR8 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR6IP: TMR6 to PR6 Match Interrupt Priority bit 1 = High priority 0 = Low priority TMR5IP: TMR5 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority TMR5GIP: TMR5 Gate Interrupt Priority bit 1 = High priority 0 = Low priority TMR1GIP: TMR1 Gate Interrupt Priority bit 1 = High priority 0 = Low priority bit 4 bit 3 bit 2 bit 1 bit 0 DS39974A-page 136 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 9.5 RCON Register The RCON register contains bits used to determine the cause of the last Reset or wake-up from Idle or Sleep mode. RCON also contains the bit that enables interrupt priorities (IPEN). REGISTER 9-19: R/W-0 IPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 RCON: RESET CONTROL REGISTER (ACCESS FD0h) U-0 — R/W-1 CM R/W-1 RI R-1 TO R-1 PD R/W-0 POR R/W-0 BOR bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) Unimplemented: Read as ‘0’ CM: Configuration Mismatch Flag bit For details on bit operation, see Register 5-1. RI: RESET Instruction Flag bit For details on bit operation, see Register 5-1. TO: Watchdog Timer Time-out Flag bit For details on bit operation, see Register 5-1. PD: Power-Down Detection Flag bit For details on bit operation, see Register 5-1. POR: Power-on Reset Status bit For details on bit operation, see Register 5-1. BOR: Brown-out Reset Status bit For details on bit operation, see Register 5-1. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 137 PIC18F47J13 FAMILY 9.6 INTx Pin Interrupts External interrupts on the INT0, INT1, INT2 and INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the INTx pin, the corresponding flag bit and INTxIF are set. This interrupt can be disabled by clearing the corresponding enable bit, INTxIE. Flag bit, INTxIF, must be cleared in software in the Interrupt Service Routine before re-enabling the interrupt. All external interrupts (INT0, INT1, INT2 and INT3) can wake up the processor from the Sleep and Idle modes if bit, INTxIE, was set prior to going into the power-managed modes. Deep Sleep mode can wake up from INT0, but the processor will start execution from the Power-on Reset vector rather than branch to the interrupt vector. Interrupt priority for INT1, INT2 and INT3 is determined by the value contained in the Interrupt Priority bits, INT1IP (INTCON3), INT2IP (INTCON3) and INT3IP (INTCON2). There is no priority bit associated with INT0; It is always a high-priority interrupt source. pair (FFFFh  0000h) will set TMR0IF. The interrupt can be enabled/disabled by setting/clearing enable bit, TMR0IE (INTCON). Interrupt priority for Timer0 is determined by the value contained in the interrupt priority bit, TMR0IP (INTCON2). See Section 12.0 “Timer0 Module” for further details on the Timer0 module. 9.8 PORTB Interrupt-on-Change An input change on PORTB sets flag bit, RBIF (INTCON). The interrupt can be enabled/disabled by setting/clearing enable bit, RBIE (INTCON). Interrupt priority for PORTB interrupt-on-change is determined by the value contained in the interrupt priority bit, RBIP (INTCON2). 9.9 Context Saving During Interrupts 9.7 TMR0 Interrupt In 8-bit mode (which is the default), an overflow in the TMR0 register (FFh  00h) will set flag bit, TMR0IF. In 16-bit mode, an overflow in the TMR0H:TMR0L register During interrupts, the return PC address is saved on the stack. Additionally, the WREG, STATUS and BSR registers are saved on the Fast Return Stack. If a fast return from interrupt is not used (see Section 6.3 “Data Memory Organization”), the user may need to save the WREG, STATUS and BSR registers on entry to the Interrupt Service Routine. Depending on the user’s application, other registers may also need to be saved. Example 9-1 saves and restores the WREG, STATUS and BSR registers during an Interrupt Service Routine (ISR). EXAMPLE 9-1: MOVWF MOVFF MOVFF ; ; USER ; MOVFF MOVF MOVFF SAVING STATUS, WREG AND BSR REGISTERS IN RAM ; W_TEMP is in virtual bank ; STATUS_TEMP located anywhere ; BSR_TMEP located anywhere W_TEMP STATUS, STATUS_TEMP BSR, BSR_TEMP ISR CODE BSR_TEMP, BSR W_TEMP, W STATUS_TEMP, STATUS ; Restore BSR ; Restore WREG ; Restore STATUS DS39974A-page 138 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.0 I/O PORTS 10.1 I/O Port Pin Capabilities Depending on the device selected and features enabled, there are up to five ports available. Some pins of the I/O ports are multiplexed with an alternate function from the peripheral features on the device. In general, when a peripheral is enabled, that pin may not be used as a general purpose I/O pin. Each port has three registers for its operation. These registers are: • TRIS register (Data Direction register) • PORT register (reads the levels on the pins of the device) • LAT register (Data Latch) The Data Latch (LAT register) is useful for read-modifywrite operations on the value that the I/O pins are driving. Figure 10-1 displays a simplified model of a generic I/O port, without the interfaces to other peripherals. When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than VDD input levels. 10.1.1 PIN OUTPUT DRIVE The output pin drive strengths vary for groups of pins intended to meet the needs for a variety of applications. PORTB and PORTC are designed to drive higher loads, such as LEDs. All other ports are designed for small loads, typically indication only. Table 10-1 summarizes the output capabilities. Refer to Section 30.0 “Electrical Characteristics” for more details. TABLE 10-1: Port PORTA PORTD PORTE PORTB PORTC OUTPUT DRIVE LEVELS Drive Description Minimum Intended for indication. Suitable for direct LED drive levels. FIGURE 10-1: GENERIC I/O PORT OPERATION High RD LAT Data Bus WR LAT or PORT 10.1.2 D CK Data Latch D Q Q I/O Pin(1) INPUT PINS AND VOLTAGE CONSIDERATIONS WR TRIS CK TRIS Latch Input Buffer RD TRIS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V; a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 10-2 summarizes the input capabilities. Refer to Section 30.0 “Electrical Characteristics” for more details. TABLE 10-2: Q D INPUT VOLTAGE LEVELS Tolerated Input Description Port or Pin EN EN RD PORT PORTA PORTB PORTC PORTE PORTB PORTC PORTD 5.5V Tolerates input levels above VDD, useful for most standard logic. VDD Only VDD input levels are tolerated. Note 1: I/O pins have diode protection to VDD and VSS.  2010 Microchip Technology Inc. Preliminary DS39974A-page 139 PIC18F47J13 FAMILY 10.1.3 INTERFACING TO A 5V SYSTEM Though the VDDMAX of the PIC18F47J13 family is 3.6V, these devices are still capable of interfacing with 5V systems, even if the VIH of the target system is above 3.6V. This is accomplished by adding a pull-up resistor to the port pin (Figure 10-2), clearing the LAT bit for that pin and manipulating the corresponding TRISx bit (Figure 10-1) to either allow the line to be pulled high or to drive the pin low. Only port pins that are tolerant of voltages up to 5.5V can be used for this type of interface (refer to Section 10.1.2 “Input Pins and Voltage Considerations”). the ECCP modules. It is selectively enabled by setting the open-drain control bit for the corresponding module in the ODCON registers (Register 10-1, Register 10-2 and Register 10-3). Their configuration is discussed in more detail with the individual port where these peripherals are multiplexed. Output functions that are routed through the PPS module may also use the open-drain option. The open-drain functionality will follow the I/O pin assignment in the PPS module. When the open-drain option is required, the output pin must also be tied through an external pull-up resistor provided by the user to a higher voltage level, up to 5.5V (Figure 10-3). When a digital logic high signal is output, it is pulled up to the higher voltage level. FIGURE 10-2: +5V SYSTEM HARDWARE INTERFACE +5V +5V Device FIGURE 10-3: PIC18F47J13 USING THE OPEN-DRAIN OUTPUT (USART SHOWN AS EXAMPLE) +5V 3.3V RD7 PIC18F47J13 VDD TXX (at logic ‘1’) 5V EXAMPLE 10-1: BCF LATD, 7 ; ; ; ; ; COMMUNICATING WITH THE +5V SYSTEM set up LAT register so changing TRIS bit will drive line low send a 0 to the 5V system send a 1 to the 5V system 10.1.5 TTL INPUT BUFFER OPTION BCF BSF TRISD, 7 TRISD, 7 10.1.4 OPEN-DRAIN OUTPUTS The output pins for several peripherals are also equipped with a configurable, open-drain output option. This allows the peripherals to communicate with external digital logic operating at a higher voltage level, without the use of level translators. The open-drain option is implemented on port pins specifically associated with the data and clock outputs of the EUSARTs, the MSSP modules (in SPI mode) and Many of the digital I/O ports use Schmitt Trigger (ST) input buffers. While this form of buffering works well with many types of input, some applications may require TTL level signals to interface with external logic devices. This is particularly true for the Parallel Master Port (PMP), which is likely to be interfaced to TTL level logic or memory devices. The inputs for the PMP can be optionally configured for TTL buffers with the PMPTTL bit in the PADCFG1 register (Register 10-4). Setting this bit configures all data and control input pins for the PMP to use TTL buffers. By default, these PMP inputs use the port’s ST buffers. DS39974A-page 140 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-1: R/W-0 CCP8OD bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ODCON1: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 1 (BANKED F42h) R/W-0 CCP6OD R/W-0 CCP5OD R/W-0 CCP4OD R/W-0 ECCP3OD R/W-0 ECCP2OD R/W-0 ECCP1OD bit 0 R/W-0 CCP7OD CCP8OD: CCP8 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled CCP7OD: CCP7 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled CCP6OD: CCP6 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled CCP5OD: CCP5 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled CCP4OD: CCP4 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled ECCP3OD: ECCP3 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled ECCP2OD: ECCP2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled ECCP1OD: ECCP1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. Preliminary DS39974A-page 141 PIC18F47J13 FAMILY REGISTER 10-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ODCON2: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 2 (BANKED F41h) U-0 — U-0 — U-0 — R/W-0 CCP10OD R/W-0 CCP9OD R/W-0 U2OD R/W-0 U1OD bit 0 Unimplemented: Read as ‘0’ CCP10OD: CCP10 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled CCP9OD: CCP9 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled U2OD: USART2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled U1OD: USART1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 2 bit 1 bit 0 REGISTER 10-3: R/W-0 CTMUDS bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-2 bit 1 ODCON3: PERIPHERAL OPEN-DRAIN CONTROL REGISTER 3 (BANKED F40h) U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 SPI2OD R/W-0 SPI1OD bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CTMUDS: CTMU Pulse Delay Enable bit 1 = Pulse delay input for CTMU enabled on pin, RA1 Unimplemented: Read as ‘0’ SPI2OD: SPI2 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled SPI1OD: SPI1 Open-Drain Output Enable bit 1 = Open-drain capability is enabled 0 = Open-drain capability is disabled bit 0 DS39974A-page 142 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-4: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — PADCFG1: PAD CONFIGURATION CONTROL REGISTER 1 (BANKED F3Ch) U-0 — U-0 — U-0 — R/W-0 R/W-0 R/W-0 PMPTTL bit 0 RTSECSEL1(1) RTSECSEL0(1) Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (can be INTRC, T1OSC or T1CKI depending upon the RTCOSC (CONFIG3L) and T1OSCEN (T1CON) bit settings) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RTCCFG) bit needs to be set. All PORTA pins have TTL input levels and full CMOS output drivers. The TRISA register controls the direction of the PORTA pins, even when they are being used as analog inputs. The user must ensure the bits in the TRISA register are maintained set when using them as analog inputs. bit 0 Note 1: 10.2 PORTA, TRISA and LATA Registers PORTA is a 7-bit wide, bidirectional port. It may function as a 5-bit port, depending on the oscillator mode selected. Setting a TRISA bit (= 1) will make the corresponding PORTA pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISA bit (= 0) will make the corresponding PORTA pin an output (i.e., put the contents of the output latch on the selected pin). Reading the PORTA register reads the status of the pins, whereas writing to it, will write to the port latch. The Data Latch (LATA) register is also memory mapped. Read-modify-write operations on the LATA register read and write the latched output value for PORTA. The other PORTA pins are multiplexed with analog inputs, the analog VREF+ and VREF- inputs and the comparator voltage reference output. The operation of pins, RA and RA5, as A/D Converter inputs is selected by clearing or setting the control bits in the ANCON0 register (A/D Port Configuration Register 0). The RAx pins may also be used as comparator inputs by setting the appropriate bits in the CMxCON registers. To use RAx as digital inputs, it is necessary to turn off the comparators. Note: On a Power-on Reset (POR), RA5 and RA are configured as analog inputs and read as ‘0’. EXAMPLE 10-2: CLRF ; ; ; LATA ; ; ; 0x0F ; ; 0x0F ; ANCON0 ; 0xCF ; ; ; TRISA ; ; PORTA INITIALIZING PORTA Initialize PORTA by clearing output data latches Alternate method to clear output data latches ANCONx register not in Access Bank Configure A/D for digital inputs Value used to initialize data direction Set RA as inputs RA as outputs CLRF MOVLB MOVLW MOVWF MOVLW MOVWF  2010 Microchip Technology Inc. Preliminary DS39974A-page 143 PIC18F47J13 FAMILY TABLE 10-3: Pin RA0/AN0/C1INA/ ULPWU/PMA6/ RP0 PORTA I/O SUMMARY Function RA0 AN0 C1INA ULPWU PMA6 (1) TRIS Setting 1 0 1 1 1 x 1 0 1 0 1 1 x 1 1 0 1 0 0 1 I/O I O I I I I/O I O I O I I O I I O I O O I I I O I I I O O I I I I I/O Type TTL DIG ANA ANA ANA Description PORTA data input; disabled when analog input is enabled. LATA data output; not affected by analog input. A/D Input Channel 0 and Comparator C1- input. Default input configuration on POR; does not affect digital output. Comparator 1 Input A. Ultra low-power wake-up input. ST/TTL/ Parallel Master Port digital I/O. DIG ST DIG TTL DIG ANA ANA ANA ST DIG ST DIG DIG TTL ANA ANA ANA ANA ANA ANA ANA DIG TTL ANA ANA ANA Remappable Peripheral Pin 0 input. Remappable Peripheral Pin 0 output. PORTA data input; disabled when analog input is enabled. LATA data output; not affected by analog input. A/D Input Channel 1 and Comparator C2- input. Default input configuration on POR; does not affect digital output. Comparator 1 Input A. Band Gap Voltage Reference output. (Enabled by setting the VBGOE bit (WDTCON.) CTMU pulse delay input. Parallel Master Port address. Remappable Peripheral Pin 1 input. Remappable Peripheral Pin 1 output LATA data output; not affected by analog input. Disabled when CVREF output is enabled. PORTA data input. Disabled when analog functions are enabled; disabled when CVREF output is enabled. A/D Input Channel 2 and Comparator C2+ input. Default input configuration on POR; not affected by analog output. Comparator 2 Input B. CTMU pulse generator charger for the C2INB comparator input. Comparator 1 Input D. Comparator 3 Input B. A/D and comparator voltage reference low input. Comparator voltage reference output. Enabling this feature disables digital I/O. LATA data output; not affected by analog input. PORTA data input; disabled when analog input is enabled. A/D Input Channel 3 and Comparator C1+ input. Default input configuration on POR. Comparator 1 Input B A/D and comparator voltage reference high input. RP0 RA1/AN1/C2INA/ VBG/CTDIN/ PMA7/RP1 RA1 AN1 C2INA VBG CTDIN PMA7(1) RP1 RA2/AN2/C2INB/ C1IND/C3INB/ VREF-/CVREF RA2 ST/TTL Parallel Master Port (io_addr_in[7]). AN2 C2INB 1 1 0 C1IND C3INB VREFCVREF RA3/AN3/C1INB/ VREF+ RA3 AN3 C1INB VREF+ 1 1 1 x 0 1 1 1 1 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). DS39974A-page 144 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-3: Pin RA5/AN4/C1INC/ SS1/HLVDIN/ RP2 PORTA I/O SUMMARY (CONTINUED) Function RA5 AN4 C1INC SS1 HLVDIN RP2 TRIS Setting 0 1 1 0 1 1 1 0 x x 1 0 1 1 1 0 I/O O I I O I I I O O O I O I I I O I/O Type DIG TTL ANA DIG TTL ANA ST DIG ANA DIG TTL DIG ANA ANA TTL DIG Description LATA data output; not affected by analog input. PORTA data input; disabled when analog input is enabled. A/D Input Channel 4. Default configuration on POR. Comparator 1 Input C. Slave select input for MSSP1. High/Low-Voltage Detect external trip point reference input. Remappable Peripheral Pin 2 input. Remappable Peripheral Pin 2 output. Main oscillator feedback output connection (HS mode). System cycle clock output (FOSC/4) in RC and EC Oscillator modes. PORTA data input. LATA data output. Main oscillator input connection. Main clock input connection. PORTA data input. LATA data output. OSC2/CLKO/ RA6 OSC2 CLKO RA6 OSC1/CLKI/RA7 OSC1 CLKI RA7 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). TABLE 10-4: Name PORTA LATA TRISA ANCON0 CMxCON CVRCON WDTCON HLVDCON SUMMARY OF REGISTERS ASSOCIATED WITH PORTA Bit 7 RA7 LAT7 TRIS7 PCFG7(1) CON CVREN REGSLP VDIRMAG Bit 6 RA6 LAT6 TRIS6 PCFG6(1) COE CVROE LVDSTAT BGVST Bit 5 RA5 LAT5 TRISA5 PCFG5(1) CPOL CVRR ULPLVL IRVST Bit 4 — — — PCFG4 EVPOL1 CVRSS VBGOE HLVDEN Bit 3 RA3 LAT3 TRISA3 PCFG3 EVPOL0 CVR3 DS HLVDL3 Bit 2 RA2 LAT2 TRISA2 PCFG2 CREF CVR2 ULPEN HLVDL2 Bit 1 RA1 LAT1 TRISA1 PCFG1 CCH1 CVR1 ULPSINK HLVDL1 Bit 0 RA0 LAT0 TRISA0 PCFG0 CCH0 CVR0 SWDTEN HLVDL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. Note 1: These bits are only available in 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).  2010 Microchip Technology Inc. Preliminary DS39974A-page 145 PIC18F47J13 FAMILY 10.3 PORTB, TRISB and LATB Registers Four of the PORTB pins (RB) have an interrupton-change feature. Only pins configured as inputs can cause this interrupt to occur (i.e., any RB pin configured as an output is excluded from the interrupton-change comparison). The input pins (of RB) are compared with the old value latched on the last read of PORTB. The “mismatch” outputs of RB are ORed together to generate the RB Port Change Interrupt with Flag bit, RBIF (INTCON). This interrupt can wake the device from Sleep mode or any of the Idle modes. Application software can clear the interrupt flag by following these steps: 1. 2. 3. Any read or write of PORTB (except with the MOVFF (ANY), PORTB instruction). Wait one instruction cycle (such as executing a NOP instruction). Clear flag bit, RBIF. PORTB is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATB) is also memory mapped. Read-modify-write operations on the LATB register read and write the latched output value for PORTB. EXAMPLE 10-3: CLRF PORTB INITIALIZING PORTB ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; ; Initialize PORTB by clearing output data latches Alternate method to clear output data latches ANCON1 not in Access Bank Configure as digital I/O pins in this example Value used to initialize data direction Set RB as inputs RB as outputs RB as inputs CLRF LATB A mismatch condition continues to set flag bit, RBIF. Reading PORTB will end the mismatch condition and allow flag bit, RBIF, to be cleared after one instruction cycle of delay. The interrupt-on-change feature is recommended for wake-up on key depression operation and operations where PORTB is only used for the interrupt-on-change feature. Polling of PORTB is not recommended while using the interrupt-on-change feature. The RB5 pin is multiplexed with the Timer0 module clock input and one of the comparator outputs to become the RB5/CCP5/PMA0/KBI1/RP8 pin. MOVLB MOVLW MOVWF MOVLW 0x0F 0x17 ANCON1 0xCF MOVWF TRISB Each of the PORTB pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RBPU (INTCON2). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. The integrated weak pull-ups consist of a semiconductor structure similar to, but somewhat different from, a discrete resistor. On an unloaded I/O pin, the weak pull-ups are intended to provide logic high indication, but will not necessarily pull the pin all the way to VDD levels. Note: On a POR, the RB bits are configured as analog inputs by default and read as ‘0’; RB bits are configured as digital inputs. DS39974A-page 146 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-5: Pin RB0/AN12/ C3IND/INT0/ RP3 PORTB I/O SUMMARY Function RB0 TRIS Setting 1 0 AN12 C3IND INT0 RP3 1 1 1 1 0 1 0 AN10 C3INC PMBE (3) I/O I O I I I I O I O I I O O I O I O I I I O O I O O I I I I O I O I/O Type TTL DIG ANA ANA ST ST DIG TTL DIG ANA ANA DIG DIG ST DIG TTL DIG ANA ANA ST DIG DIG ST DIG DIG TTL ANA ANA ST DIG ST DIG Description PORTB data input; weak pull-up when the RBPU bit is cleared. Disabled when analog input is enabled.(1) LATB data output; not affected by an analog input. A/D Input Channel 12.(1) Comparator 3 Input D. External Interrupt 0 input. Remappable Peripheral Pin 3 input. Remappable Peripheral Pin 3 output. PORTB data input; weak pull-up when the RBPU bit is cleared. Disabled when an analog input is enabled.(1) LATB data output; not affected by an analog input. A/D Input Channel 10.(1) Comparator 3 Input C. Parallel Master Port byte enable. Asynchronous serial transmit data output (USART module). Remappable Peripheral Pin 4 input. Remappable Peripheral Pin 4 output. PORTB data input; weak pull-up when the RBPU bit is cleared. Disabled when an analog input is enabled.(1) LATB data output; not affected by an analog input. A/D Input Channel 8.(1) Comparator 2 Input C. CTMU Edge 1 input. Parallel Master Port address. Reference output clock. Remappable Peripheral Pin 5 input. Remappable Peripheral Pin 5 output. LATB data output; not affected by analog input. PORTB data input; weak pull-up when the RBPU bit is cleared. Disabled when analog input is enabled.(1) A/D Input Channel 9.(1) Comparator 3 Input A. CTMU Edge 2 input. Parallel Master Port address. Remappable Peripheral Pin 6 input. Remappable Peripheral Pin 6 output. RB1/AN10/ C3INC/PMBE/ RTCC/RP4 RB1 1 1 x 0 1 0 1 0 RTCC RP4 RB2/AN8/ C2INC/CTED1/ PMA3/REFO/ RP5 RB2 AN8 C2INC CTED1 PMA3(3) REFO RP5 1 1 1 x 0 1 0 0 1 RB3/AN9/ C3INA/CTED2/ PMA2/RP6 RB3 AN9 C3INA CTED2 PMA2 (3) 1 1 1 x 1 0 RP6 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in the ANCON1 register. 2: All other pin functions are disabled when ICSP™ or ICD is enabled. 3: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 4: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13).  2010 Microchip Technology Inc. Preliminary DS39974A-page 147 PIC18F47J13 FAMILY TABLE 10-5: Pin RB4/CCP4/ PMA1/KBI0/ SCL2(4)/RP7 PORTB I/O SUMMARY (CONTINUED) Function RB4 TRIS Setting 0 1 CCP4(3) PMA1 KBI0 SCL2(4) RP7 1 0 x 1 1 1 0 0 1 CCP5(3) PMA0(3) KBI1 SDA2(4) RP8 1 0 x 1 1 1 0 0 1 CCP6(3) KBI2 PGC RP9 1 0 1 x 1 0 I/O O I I O I/O I I I O O I I O I/O I I I O O I I O I I I O I/O Type DIG TTL ST DIG Description LATB data output; not affected by an analog input. PORTB data input; weak pull-up when the RBPU bit is cleared. Disabled when an analog input is enabled.(1) Capture input. Compare/PWM output. ST/TTL/ Parallel Master Port address. DIG TTL Interrupt-on-change pin. I2C™/ I2C clock input (MSSP2 module). SMBus ST DIG DIG TTL ST DIG Remappable Peripheral Pin 7 input. Remappable Peripheral Pin 7 output. LATB data output. PORTB data input; weak pull-up when the RBPU bit is cleared. Capture input. Compare/PWM output. RB5/CCP5/ PMA0/KBI1/ SDA2(4)/RP8 RB5 ST/TTL/ Parallel Master Port address. DIG TTL I2C™/ SMBus ST DIG DIG TTL ST DIG TTL ST ST DIG Remappable Peripheral Pin 8 input. Remappable Peripheral Pin 8 output. LATB data output. PORTB data input; weak pull-up when the RBPU bit is cleared. Capture input. Compare/PWM output. Interrupt-on-change pin. Serial execution (ICSP™) clock input for ICSP and ICD operation.(2) Remappable Peripheral Pin 9 input. Remappable Peripheral Pin 9 output. Interrupt-on-change pin. I2C data input (MSSP2 module). RB6/CCP6/ KBI2/PGC/RP9 RB6 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in the ANCON1 register. 2: All other pin functions are disabled when ICSP™ or ICD is enabled. 3: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 4: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). DS39974A-page 148 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-5: Pin RB7/CCP7/ KBI3/PGD/ RP10 PORTB I/O SUMMARY (CONTINUED) Function RB7 TRIS Setting 0 1 CCP7 KBI3 PGD RP10 1 0 1 x x 1 0 I/O O I I O O O I I O I/O Type DIG TTL ST DIG TTL DIG ST ST DIG LATB data output. PORTB data input; weak pull-up when the RBPU bit is cleared. Capture input. Compare/PWM output. Interrupt-on-change pin. Serial execution data output for ICSP and ICD operation.(2) Serial execution data input for ICSP and ICD operation.(2) Remappable Peripheral Pin 10 input. Remappable Peripheral Pin 10 output. Description Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: Pins are configured as analog inputs by default on POR. Using these pins for digital inputs requires setting the appropriate bits in the ANCON1 register. 2: All other pin functions are disabled when ICSP™ or ICD is enabled. 3: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). 4: Only on 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF27J13). TABLE 10-6: Name PORTB LATB TRISB INTCON INTCON2 INTCON3 ANCON1 REFOCON CM3CON PADCFG1 RTCCFG SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Bit 7 RB7 LATB7 TRISB7 GIE/GIEH RBPU INT2IP VBGEN ROON CON — RTCEN Bit 6 RB6 LATB6 TRISB6 PEIE/GIEL INTEDG0 INT1IP — — COE — — Bit 5 RB5 LATB5 TRISB5 TMR0IE INTEDG1 INT3IE — ROSSLP CPOL — Bit 4 RB4 LATB4 TRISB4 INT0IE INTEDG2 INT2IE PCFG12 ROSEL EVPOL1 — Bit 3 RB3 LATB3 TRISB3 RBIE INTEDG3 INT1IE PCFG11 RODIV3 EVPOL0 — Bit 2 RB2 LATB2 TRISB2 TMR0IF TMR0IP INT3IF PCFG10 RODIV2 CREF RTCOE Bit 1 RB1 LATB1 TRISB1 INT0IF INT3IP INT2IF PCFG9 RODIV1 CCH1 RTCPTR1 Bit 0 RB0 LATB0 TRISB0 RBIF RBIP INT1IF PCFG8 RODIV0 CCH0 RTCPTR0 RTSECSEL1 RTSECSEL0 PMPTTL RTCWREN RTCSYNC HALFSEC Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTB.  2010 Microchip Technology Inc. Preliminary DS39974A-page 149 PIC18F47J13 FAMILY 10.4 PORTC, TRISC and LATC Registers Note: On a Power-on Reset, PORTC pins (except RC2) are configured as digital inputs. RC2 will default as an analog input (controlled by the ANCON1 register). PORTC is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISC. Setting a TRISC bit (= 1) will make the corresponding PORTC pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISC bit (= 0) will make the corresponding PORTC pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATC) is also memory mapped. Read-modify-write operations on the LATC register read and write the latched output value for PORTC. PORTC is multiplexed with several peripheral functions (see Table 10-7). The pins have Schmitt Trigger input buffers. When enabling peripheral functions, care should be taken in defining TRISx bits for each PORTC pin. Some peripherals override the TRISx bit to make a pin an output, while other peripherals override the TRISx bit to make a pin an input. The user should refer to the corresponding peripheral section for additional information. The contents of the TRISC register are affected by peripheral overrides. Reading TRISC always returns the current contents, even though a peripheral device may be overriding one or more of the pins. EXAMPLE 10-4: CLRF PORTC ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTC Initialize PORTC by clearing output data latches CLRF LATC Alternate method to clear output data latches MOVLW 0x3F Value used to initialize data direction MOVWF TRISC Set RC as inputs RC as outputs MOVLB 0x0F ANCON register is not in Access Bank BSF ANCON1,PCFG11 ;Configure RC2/AN11 as digital input DS39974A-page 150 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-7: Pin RC0/T1OSO/ T1CKI/RP11 PORTC I/O SUMMARY Function RC0 T1OSO T1CKI RP11 TRIS Setting 1 0 x 1 1 0 1 0 CCP8 T1OSI RP12 1 0 x 1 0 1 0 AN11 C2IND CTPLS RP13 1 1 0 1 0 1 0 SCK1 SCL1 1 0 1 0 RP14 1 0 0 1 1 0 RP15 1 0 I/O I O O I I O I O I O I I O I O I I O I O I O I O I O I O O I I O I O I/O Type ST DIG ANA ST ST DIG ST DIG ST DIG ANA ST DIG ST DIG ANA ANA DIG ST DIG ST DIG ST DIG 2C/ Description PORTC data input. LATC data output. Timer1 oscillator output; enabled when Timer1 oscillator is enabled. Disables digital I/O. Timer1 digital clock input. Remappable Peripheral Pin 11 input. Remappable Peripheral Pin 11 output. PORTC data input. LATC data output. Capture input. Compare/PWM output. Timer1 oscillator input; enabled when Timer1 oscillator is enabled. Disables digital I/O. Remappable Peripheral Pin 12 input. Remappable Peripheral Pin 12 output. PORTC data input. PORTC data output. A/D Input Channel 11. Comparator 2 Input D. CTMU pulse generator output. Remappable Peripheral Pin 13 input. Remappable Peripheral Pin 13 output. PORTC data input. PORTC data output. SPI clock input (MSSP1 module). SPI clock output (MSSP1 module). RC1/CCP8/ T1OSI/RP12 RC1 RC2/AN11/ C2IND/CTPLS/ RP13 RC2 RC3/SCK1/ SCL1/RP14 RC3 I2C™ clock input (MSSP1 module). I SMBus DIG ST DIG DIG ST I2C clock output (MSSP1 module). Remappable Peripheral Pin 14 input. Remappable Peripheral Pin 14 output. PORTC data output. SPI data input (MSSP1 module). RC4/SDI1/ SDA1/RP15 RC4 SDI1 SDA1 I2C data input (MSSP1 module). I2C/ SMBus DIG ST DIG I2C data output (MSSP1 module). Remappable Peripheral Pin 15 input. Remappable Peripheral Pin 15 output. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13).  2010 Microchip Technology Inc. Preliminary DS39974A-page 151 PIC18F47J13 FAMILY TABLE 10-7: Pin RC5/SDO1/ RP16 PORTC I/O SUMMARY (CONTINUED) Function RC5 SDO1 RP16 TRIS Setting 0 x 1 0 I/O O O I O I O I O I O O I O I O I O I O I/O I 1 O I O I/O Type DIG DIG ST DIG ST DIG ST DIG DIG DIG ST DIG ST DIG ST DIG ST DIG Description PORTC data output. SPI data output (MSSP1 module). Remappable Peripheral Pin 16 input. Remappable Peripheral Pin 16 output. PORTC data input. LATC data output. Capture input. Compare/PWM output. Parallel Master Port address. Asynchronous serial transmit data output (EUSART module); takes priority over port data. User must configure as an output. Synchronous serial clock input (EUSART module). Synchronous serial clock output (EUSART module); takes priority over port data. Remappable Peripheral Pin 17 input. Remappable Peripheral Pin 17 output. PORTC data input. LATC data output. Capture input. Compare/PWM output. RC6/CCP9/ PMA5/TX1/ CK1/RP17 RC6 CCP9 PMA5(1) TX1 CK1 1 0 1 0 1 0 0 1 0 ST/TTL Parallel Master Port io_addr_in. RP17 RC7/CCP10/ PMA4/RX1/ DT1/RP18 RC7 CCP10 PMA4(1) RX1 DT1 1 0 1 0 1 0 x 1 1 0 ST/TTL/ Parallel Master Port address. DIG ST ST DIG ST DIG Asynchronous serial receive data input (EUSART module). Synchronous serial data input (EUSART module). User must configure as an input. Synchronous serial data output (EUSART module); takes priority over port data. Remappable Peripheral Pin 18 input. Remappable Peripheral Pin 18 output. RP18 1 0 Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option) Note 1: This bit is only available on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). TABLE 10-8: Name PORTC LATC TRISC ANCON1 CM2CON RTCCFG SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Bit 7 RC7 LATC7 TRISC7 VBGEN CON RTCEN Bit 6 RC6 LATC6 TRISC6 — COE — Bit 5 RC5 LATC5 TRISC5 — CPOL Bit 4 RC4 LATC4 TRISC4 PCFG12 EVPOL1 Bit 3 RC3 LATC3 TRISC3 PCFG11 EVPOL0 Bit 2 RC2 LATC2 TRISC2 PCFG10 CREF RTCOE Bit 1 RC1 LATC1 TRISC1 PCFG9 CCH1 RTCPTR1 Bit 0 RC0 LATC0 TRISC0 PCFG8 CCH0 RTCPTR0 RTCWREN RTCSYNC HALFSEC DS39974A-page 152 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.5 Note: PORTD, TRISD and LATD Registers PORTD is available only in 44-pin devices. EXAMPLE 10-5: CLRF PORTD ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTD Initialize PORTD by clearing output data latches Alternate method to clear output data latches Value used to initialize data direction Set RD as inputs RD as outputs RD as inputs PORTD is an 8-bit wide, bidirectional port. The corresponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i.e., put the contents of the output latch on the selected pin). The Data Latch register (LATD) is also memory mapped. Read-modify-write operations on the LATD register read and write the latched output value for PORTD. All pins on PORTD are implemented with Schmitt Trigger input buffers. Each pin is individually configurable as an input or output. On a POR, these pins are configured as digital inputs. CLRF LATD MOVLW 0xCF MOVWF TRISD Note: Each of the PORTD pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, RDPU (TRISE). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. The integrated weak pull-ups consist of a semiconductor structure similar to, but somewhat different from, a discrete resistor. On an unloaded I/O pin, the weak pull-ups are intended to provide logic high indication, but will not necessarily pull the pin all the way to VDD levels. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB.  2010 Microchip Technology Inc. Preliminary DS39974A-page 153 PIC18F47J13 FAMILY TABLE 10-9: Pin RD0/PMD0/ SCL2 PORTD I/O SUMMARY Function RD0 PMD0(1) SCL2(1) TRIS Setting 1 0 1 0 1 0 I/O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I O I/O Type ST DIG DIG I2C/ SMB DIG ST DIG DIG I2C/ SMB DIG ST DIG DIG ST DIG ST DIG DIG ST DIG ST DIG DIG ST DIG ST DIG DIG ST DIG PORTD data input. LATD data output. Parallel Master Port data out. I2C™ clock input (MSSP2 module); input type depends on the module setting. I2C clock output (MSSP2 module); takes priority over port data. PORTD data input. LATD data output. Parallel Master Port data out. I2C data input (MSSP2 module); input type depends on the module setting. I2C data output (MSSP2 module); takes priority over port data. PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 19 input. Remappable Peripheral Pin 19 output. PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 20 input. Remappable Peripheral Pin 20 output. PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 21 input. Remappable Peripheral Pin 21 output. PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 22 input. Remappable Peripheral Pin 22 output. Description ST/TTL Parallel Master Port data in. RD1/PMD1/ SDA2 RD1 PMD1(1) SDA2(1) 1 0 1 0 1 0 ST/TTL Parallel Master Port data in. RD2/PMD2/ RP19 RD2 PMD2 (1) 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 ST/TTL Parallel Master Port data in. RP19 RD3/PMD3/ RP20 RD3 PMD3(1) RP20 RD4/PMD4/ RP21 RD4 PMD4(1) RP21 RD5/PMD5/ RP22 RD5 PMD5(1) RP22 ST/TTL Parallel Master Port data in. ST/TTL Parallel Master Port data in. ST/TTL Parallel Master Port data in. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option). Note 1: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). DS39974A-page 154 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-9: Pin RD6/PMD6/ RP23 PORTD I/O SUMMARY (CONTINUED) Function RD6 PMD6(1) RP23 TRIS Setting 1 0 1 0 1 0 1 0 PMD7(1) RP24 1 0 1 0 I/O I O I O I O I O I O I O I/O Type ST DIG DIG ST DIG ST DIG DIG ST DIG PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 23 input. Remappable Peripheral Pin 23 output. PORTD data input. LATD data output. Parallel Master Port data out. Remappable Peripheral Pin 24 input. Remappable Peripheral Pin 24 output. Description ST/TTL Parallel Master Port data in. RD7/PMD7/ RP24 RD7 ST/TTL Parallel Master Port data in. Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; I2C/SMB = I2C/SMBus input buffer; x = Don’t care (TRISx bit does not affect port direction or is overridden for this option). Note 1: Only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). TABLE 10-10: SUMMARY OF REGISTERS ASSOCIATED WITH PORTD Name PORTD LATD(1) TRISD(1) (1) Bit 7 RD7 LATD7 TRISD7 Bit 6 RD6 LATD6 TRISD6 Bit 5 RD5 LATD5 TRISD5 Bit 4 RD4 LATD4 TRISD4 Bit 3 RD3 LATD3 TRISD3 Bit 2 RD2 LATD2 TRISD2 Bit 1 RD1 LATD1 TRISD1 Bit 0 RD0 LATD0 TRISD0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTD. Note 1: These registers are not available in 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF26J13).  2010 Microchip Technology Inc. Preliminary DS39974A-page 155 PIC18F47J13 FAMILY 10.6 Note: PORTE, TRISE and LATE Registers PORTE is available only in 44-pin devices. EXAMPLE 10-6: CLRF PORTE ; ; ; ; ; ; ; ; ; ; ; ; ; ; INITIALIZING PORTE Initialize PORTE by clearing output data latches Alternate method to clear output data latches Configure REx for digital inputs Value used to initialize data direction Set RE as inputs RE as outputs RE as inputs Depending on the particular PIC18F47J13 family device selected, PORTE is implemented in two different ways. For 44-pin devices, PORTE is a 3-bit wide port. Three pins (RE0/AN5/PMRD, RE1/AN6/PMWR and RE2/ AN7/PMCS) are individually configurable as inputs or outputs. These pins have Schmitt Trigger input buffers. When selected as analog inputs, these pins will read as ‘0’s. The corresponding Data Direction register is TRISE. Setting a TRISE bit (= 1) will make the corresponding PORTE pin an input (i.e., put the corresponding output driver in a High-Impedance mode). Clearing a TRISE bit (= 0) will make the corresponding PORTE pin an output (i.e., put the contents of the output latch on the selected pin). TRISE controls the direction of the RE pins, even when they are being used as analog inputs. The user must make sure to keep the pins configured as inputs when using them as analog inputs. Note: On a POR, RE are configured as analog inputs. CLRF LATE MOVLW MOVWF MOVLW 0xE0 ANCON0 0x03 MOVWF TRISE Each of the PORTE pins has a weak internal pull-up. A single control bit can turn on all the pull-ups. This is performed by clearing bit, REPU (TRISE). The weak pull-up is automatically turned off when the port pin is configured as an output. The pull-ups are disabled on a POR. The integrated weak pull-ups consist of a semiconductor structure similar to, but somewhat different, from a discrete resistor. On an unloaded I/O pin, the weak pull-ups are intended to provide logic high indication, but will not necessarily pull the pin all the way to VDD levels. Note that the pull-ups can be used for any set of features, similar to the pull-ups found on PORTB. The Data Latch register (LATE) is also memory mapped. Read-modify-write operations on the LATE register read and write the latched output value for PORTE. DS39974A-page 156 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 10-11: PORTE I/O SUMMARY Pin RE0/AN5/ PMRD Function RE0 AN5 PMRD RE1/AN6/ PMWR RE1 AN6 PMWR RE2/AN7/ PMCS RE2 AN7 PMCS TRIS Setting 1 0 1 1 0 1 0 1 1 0 1 0 1 0 I/O I O I I O I O I I O I O I O I/O Type ST DIG ANA DIG ST DIG ANA DIG ST DIG ANA DIG Description PORTE data input; disabled when analog input is enabled. LATE data output; not affected by analog input. A/D Input Channel 5; default input configuration on POR. Parallel Master Port read strobe. PORTE data input; disabled when analog input is enabled. LATE data output; not affected by analog input. A/D Input Channel 6; default input configuration on POR. Parallel Master Port write strobe. PORTE data input; disabled when analog input is enabled. LATE data output; not affected by an analog input. A/D Input Channel 7; default input configuration on POR. Parallel Master Port byte enable. ST/TTL Parallel Master Port (io_rd_in). ST/TTL Parallel Master Port (io_wr_in). Legend: DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level I = Input; O = Output; P = Power TABLE 10-12: SUMMARY OF REGISTERS ASSOCIATED WITH PORTE Name PORTE LATE(1) TRISE(1) ANCON0 (1) Bit 7 — — RDPU PCFG7(1) Bit 6 — — REPU PCFG6(1) Bit 5 — — — PCFG5(1) Bit 4 — — — PCFG4 Bit 3 — — — PCFG3 Bit 2 RE2 LATE2 TRISE2 PCFG2 Bit 1 RE1 LATE1 TRISE1 PCFG1 Bit 0 RE0 LATE0 TRISE0 PCFG0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTE. Note 1: These registers and/or bits are not available in 28-pin devices (PIC18F26J13, PIC18F27J13, PIC18LF26J13 and PIC18LF26J13). Note: bit 7 RDPU: PORTD Pull-up Enable bit 0 = All PORTD pull-ups are disabled 1 = PORTD pull-ups are enabled for any input pad bit 6 REPU: PORTE Pull-up Enable bit 0 = All PORTE pull-ups are disabled 1 = PORTE pull-ups are enabled for any input pad  2010 Microchip Technology Inc. Preliminary DS39974A-page 157 PIC18F47J13 FAMILY 10.7 Peripheral Pin Select (PPS) 10.7.2 AVAILABLE PERIPHERALS A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin count devices similar to the PIC18F47J13 family. In an application that needs to use more than one peripheral, multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option. The Peripheral Pin Select (PPS) feature provides an alternative to these choices by enabling the user’s peripheral set selection and its placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The PPS feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/ or output of any one of the many digital peripherals to any one of these I/O pins. PPS is performed in software, and generally, does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. The peripherals managed by the PPS are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. The PPS module is not applied to I2C, change notification inputs, RTCC alarm outputs or peripherals with analog inputs. Additionally, the MSSP1 and EUSART1 modules are not routed through the PPS module. A key difference between pin select and non-pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.7.2.1 Peripheral Pin Select Function Priority 10.7.1 AVAILABLE PINS The PPS feature is used with a range of up to 22 pins. The number of available pins is dependent on the particular device and its pin count. Pins that support the PPS feature include the designation “RPn” in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable pin number. See Table 1-3 and Table 1-4 for pinout options in each package offering. When a pin selectable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Pin select peripherals never take priority over any analog functions associated with the pin. 10.7.3 CONTROLLING PERIPHERAL PIN SELECT PPS features are controlled through two sets of Special Function Registers (SFRs): one to map peripheral inputs and the other to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on whether an input or an output is being mapped. DS39974A-page 158 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.7.3.1 Input Mapping The inputs of the PPS options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-6 through Register 10-23). Each register contains a 5-bit field which is associated with one of the pin selectable peripherals. Programming a given peripheral’s bit field with an appropriate 5-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin Selections supported by the device. TABLE 10-13: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Input Name Function Name Register Configuration Bits INTR1R INTR2R INTR3R T0CKR T3CKR T5CKR IC1R IC2R IC3R T1GR T3GR T5GR RX2DT2R CK2R SDI2R SCK2R SS2R OCFAR External Interrupt 1 INT1 RPINR1 External Interrupt 2 INT2 RPINR2 External Interrupt 3 INT3 RPINR3 Timer0 External Clock Input T0CKI RPINR4 Timer3 External Clock Input T3CKI RPINR6 Timer5 External Clock Input T5CKI RPINR15 Input Capture 1 CCP1 RPINR7 Input Capture 2 CCP2 RPINR8 Input Capture 3 CCP3 RPINR9 Timer1 Gate Input T1G RPINR12 Timer3 Gate Input T3G RPINR13 Timer5 Gate Input T5G RPINR14 EUSART2 Asynchronous Receive/Synchronous RX2/DT2 RPINR16 Receive EUSART2 Asynchronous Clock Input CK2 RPINR17 SPI2 Data Input SDI2 RPINR21 SPI2 Clock Input SCK2IN RPINR22 SPI2 Slave Select Input SS2IN RPINR23 PWM Fault Input FLT0 RPINR24 Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers.  2010 Microchip Technology Inc. Preliminary DS39974A-page 159 PIC18F47J13 FAMILY 10.7.3.2 Output Mapping In contrast to inputs, the outputs of the PPS options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-14). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘00000’. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals. TABLE 10-14: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Function Output Function Number(1) Output Name NULL 0 NULL(2) C1OUT 1 Comparator 1 Output C2OUT 2 Comparator 2 Output C3OUT 3 Comparator 3 Output TX2/CK2 6 EUSART2 Asynchronous Transmit/Asynchronous Clock Output DT2 7 EUSART2 Synchronous Transmit SDO2 10 SPI2 Data Output SCK2 11 SPI2 Clock Output SSDMA 12 SPI DMA Slave Select ULPOUT 13 Ultra Low-Power Wake-up Event CCP1/P1A 14 ECCP1 Compare or PWM Output Channel A P1B 15 ECCP1 Enhanced PWM Output, Channel B P1C 16 ECCP1 Enhanced PWM Output, Channel C P1D 17 ECCP1 Enhanced PWM Output, Channel D CCP2/P2A 18 ECCP2 Compare or PWM Output P2B 19 ECCP2 Enhanced PWM Output, Channel B P2C 20 ECCP2 Enhanced PWM Output, Channel C P2D 21 ECCP2 Enhanced PWM Output, Channel D CCP3/P3A 22 ECCP3 Compare or PWM Output P3B 23 ECCP3 Enhanced PWM Output, Channel B P3C 24 ECCP3 Enhanced PWM Output, Channel C P3D 25 ECCP3 Enhanced PWM Output, Channel D Note 1: Value assigned to the RP pins corresponds to the peripheral output function number. 2: The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. DS39974A-page 160 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.7.3.3 Mapping Limitations 10.7.4.3 Configuration Bit Pin Select Lock The control schema of the PPS is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lockouts. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CONFIG3H) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the PPS Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the PPS registers. 10.7.4 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC18F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock 10.7.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION 10.7.4.1 Control Register Lock Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (PPSCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 55h to EECON2. Write AAh to EECON2. Clear (or set) IOLOCK as a single operation. The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the PPS is not available on default pins in the device’s default (Reset) state. Since all RPINRx registers reset to ‘11111’ and all RPORx registers reset to ‘00000’, all PPS inputs are tied to RP31 and all PPS outputs are disconnected. Note: In tying PPS inputs to RP31, RP31 does not have to exist on a device for the registers to be reset to it. IOLOCK remains in one state until changed. This allows all of the PPS registers to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. The unlock sequence is timing-critical. Therefore, it is recommended that the unlock sequence be executed as an assembly language routine with interrupts temporarily disabled. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing in-line assembly. 10.7.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered.  2010 Microchip Technology Inc. Preliminary DS39974A-page 161 PIC18F47J13 FAMILY Choosing the configuration requires the review of all PPSs and their pin assignments, especially those that will not be used in the application. In all cases, unused pin selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that the PPS functions neither override analog inputs nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a PPS. Example 10-7 provides a configuration for bidirectional communication with flow control using EUSART2. The following input and output functions are used: • Input Function RX2 • Output Function TX2 EXAMPLE 10-7: CONFIGURING EUSART2 INPUT AND OUTPUT FUNCTIONS ;************************************* ; Unlock Registers ;************************************* MOVLB 0x0E ; PPS registers in BANK 14 BCF INTCON, GIE ; Disable interrupts MOVLW 0x55 MOVWF EECON2, 0 MOVLW 0xAA MOVWF EECON2, 0 ; Turn off PPS Write Protect BCF PPSCON, IOLOCK, BANKED ;*************************** ; Configure Input Functions ; (See Table 10-13) ;*************************** ;*************************** ; Assign RX2 To Pin RP0 ;*************************** MOVLW 0x00 MOVWF RPINR16, BANKED ;*************************** ; Configure Output Functions ; (See Table 10-14) ;*************************** ;*************************** ; Assign TX2 To Pin RP1 ;*************************** MOVLW 0x06 MOVWF RPOR1, BANKED ;************************************* ; Lock Registers ;************************************* BCF INTCON, GIE MOVLW 0x55 MOVWF EECON2, 0 MOVLW 0xAA MOVWF EECON2, 0 ; Write Protect PPS BSF PPSCON, IOLOCK, BANKED Note: If the Configuration bit, IOL1WAY = 1, once the IOLOCK bit is set, it cannot be cleared, preventing any future RP register changes. The IOLOCK bit is cleared back to ‘0’ on any device Reset. DS39974A-page 162 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 10.7.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC18F47J13 family of devices implements a total of 37 registers for remappable peripheral configuration of 44-pin devices. The 28-pin devices have 31 registers for remappable peripheral configuration. Input and output register values can only be changed if IOLOCK (PPSCON) = 0. See Example 10-7 for a specific command sequence. REGISTER 10-5: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-1 bit 0 PPSCON: PERIPHERAL PIN SELECT INPUT REGISTER 0 (BANKED EBFh)(1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 IOLOCK bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IOLOCK: I/O Lock Enable bit 1 = I/O lock is active, RPORx and RPINRx registers are write-protected 0 = I/O lock is not active, pin configurations can be changed Register values can only be changed if IOLOCK (PPSCON) = 0. Note 1: REGISTER 10-6: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 (BANKED EE1h) U-0 — U-0 — R/W-1 INTR1R4 R/W-1 INTR1R3 R/W-1 INTR1R2 R/W-1 INTR1R1 R/W-1 INTR1R0 bit 0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ INTR1R: Assign External Interrupt 1 (INT1) to the Corresponding RPn Pin bits REGISTER 10-7: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 (BANKED EE2h) U-0 — U-0 — R/W-1 INTR2R4 R/W-1 INTR2R3 R/W-1 INTR2R2 R/W-1 INTR2R1 R/W-1 INTR2R0 bit 0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ INTR2R: Assign External Interrupt 2 (INT2) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. Preliminary DS39974A-page 163 PIC18F47J13 FAMILY REGISTER 10-8: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 (BANKED EE3h) U-0 — U-0 — R/W-1 INTR3R4 R/W-1 INTR3R3 R/W-1 INTR3R2 R/W-1 INTR3R1 R/W-1 INTR3R0 bit 0 Unimplemented: Read as ‘0’ INTR3R: Assign External Interrupt 3 (INT3) to the Corresponding RPn Pin bits REGISTER 10-9: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 (BANKED EE4h) U-0 — U-0 — R/W-1 T0CKR4 R/W-1 T0CKR3 R/W-1 T0CKR2 R/W-1 T0CKR1 R/W-1 T0CKR0 bit 0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ T0CKR: Timer0 External Clock Input (T0CKI) to the Corresponding RPn Pin bits REGISTER 10-10: RPINR6: PERIPHERAL PIN SELECT INPUT REGISTER 6 (BANKED EE6h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T3CKR4 R/W-1 T3CKR3 R/W-1 T3CKR2 R/W-1 T3CKR1 R/W-1 T3CKR0 bit 0 Unimplemented: Read as ‘0’ T3CKR: Timer3 External Clock Input (T3CKI) to the Corresponding RPn Pin bits DS39974A-page 164 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-11: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 (BANKED EE8h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 IC1R4 R/W-1 IC1R3 R/W-1 IC1R2 R/W-1 IC1R1 R/W-1 IC1R0 bit 0 Unimplemented: Read as ‘0’ IC1R: Assign Input Capture 1 (ECCP1) to the Corresponding RPn Pin bits REGISTER 10-12: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 (BANKED EE9h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 IC2R4 R/W-1 IC2R3 R/W-1 IC2R2 R/W-1 IC2R1 R/W-1 IC2R0 bit 0 Unimplemented: Read as ‘0’ IC2R: Assign Input Capture 2 (ECCP2) to the Corresponding RPn Pin bits REGISTER 10-13: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 (BANKED EEAh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 IC3R4 R/W-1 IC3R3 R/W-1 IC3R2 R/W-1 IC3R1 R/W-1 IC3R0 bit 0 Unimplemented: Read as ‘0’ IC3R: Assign Input Capture 3 (ECCP3) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. Preliminary DS39974A-page 165 PIC18F47J13 FAMILY REGISTER 10-14: RPINR12: PERIPHERAL PIN SELECT INPUT REGISTER 12 (BANKED EF2h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T1GR4 R/W-1 T1GR3 R/W-1 T1GR2 R/W-1 T1GR1 R/W-1 T1GR0 bit 0 Unimplemented: Read as ‘0’ T1GR: Timer1 Gate Input (T1G) to the Corresponding RPn Pin bits REGISTER 10-15: RPINR13: PERIPHERAL PIN SELECT INPUT REGISTER 13 (BANKED EF3h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T3GR4 R/W-1 T3GR3 R/W-1 T3GR2 R/W-1 T3GR1 R/W-1 T3GR0 bit 0 Unimplemented: Read as ‘0’ T3GR: Timer3 Gate Input (T3G) to the Corresponding RPn Pin bits REGISTER 10-16: RPINR14: PERIPHERAL PIN SELECT INPUT REGISTER 14 (BANKED EF4h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T5GR4 R/W-1 T5GR3 R/W-1 T5GR2 R/W-1 T5GR1 R/W-1 T5GR0 bit 0 Unimplemented: Read as ‘0’ T5GR: Timer5 Gate Input (T5G) to the Corresponding RPn Pin bits DS39974A-page 166 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-17: RPINR16: PERIPHERAL PIN SELECT INPUT REGISTER 16 (BANKED EF7h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 RX2DT2R4 R/W-1 RX2DT2R3 R/W-1 RX2DT2R2 R/W-1 RX2DT2R1 R/W-1 RX2DT2R0 bit 0 Unimplemented: Read as ‘0’ RX2DT2R: EUSART2 Synchronous/Asynchronous Receive (RX2/DT2) to the Corresponding RPn Pin bits REGISTER 10-18: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 (BANKED EE7h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T5CKR4 R/W-1 T5CKR3 R/W-1 T5CKR2 R/W-1 T5CKR1 R/W-1 T5CKR0 bit 0 Unimplemented: Read as ‘0’ T5CKR: Timer5 External Clock Input (T5CKI) to the Corresponding RPn Pin bits REGISTER 10-19: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 (BANKED EF8h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 CK2R4 R/W-1 CK2R3 R/W-1 CK2R2 R/W-1 CK2R1 R/W-1 CK2R0 bit 0 Unimplemented: Read as ‘0’ CK2R: EUSART2 Clock Input (CK2) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. Preliminary DS39974A-page 167 PIC18F47J13 FAMILY REGISTER 10-20: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 (BANKED EFCh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SDI2R4 R/W-1 SDI2R3 R/W-1 SDI2R2 R/W-1 SDI2R1 R/W-1 SDI2R0 bit 0 Unimplemented: Read as ‘0’ SDI2R: Assign SPI2 Data Input (SDI2) to the Corresponding RPn Pin bits REGISTER 10-21: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 (BANKED EFDh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SCK2R4 R/W-1 SCK2R3 R/W-1 SCK2R2 R/W-1 SCK2R1 R/W-1 SCK2R0 bit 0 Unimplemented: Read as ‘0’ SCK2R: Assign SPI2 Clock Input (SCK2) to the Corresponding RPn Pin bits REGISTER 10-22: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 (BANKED EFEh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SS2R4 R/W-1 SS2R3 R/W-1 SS2R2 R/W-1 SS2R1 R/W-1 SS2R0 bit 0 Unimplemented: Read as ‘0’ SS2R: Assign SPI2 Slave Select Input (SS2) to the Corresponding RPn Pin bits DS39974A-page 168 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-23: RPINR24: PERIPHERAL PIN SELECT INPUT REGISTER 24 (BANKED EFFh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 OCFAR4 R/W-0 OCFAR3 R/W-0 OCFAR2 R/W-0 OCFAR1 R/W-0 OCFAR0 bit 0 Unimplemented: Read as ‘0’ OCFAR: Assign PWM Fault Input (FLT0) to the Corresponding RPn Pin bits  2010 Microchip Technology Inc. Preliminary DS39974A-page 169 PIC18F47J13 FAMILY REGISTER 10-24: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 (BANKED EC1h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP0R4 R/W-0 RP0R3 R/W-0 RP0R2 R/W-0 RP0R1 R/W-0 RP0R0 bit 0 Unimplemented: Read as ‘0’ RP0R: Peripheral Output Function is Assigned to RP0 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-25: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 (BANKED EC7h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP1R4 R/W-0 RP1R3 R/W-0 RP1R2 R/W-0 RP1R1 R/W-0 RP1R0 bit 0 Unimplemented: Read as ‘0’ RP1R: Peripheral Output Function is Assigned to RP1 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-26: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 (BANKED EC3h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP2R4 R/W-0 RP2R3 R/W-0 RP2R2 R/W-0 RP2R1 R/W-0 RP2R0 bit 0 Unimplemented: Read as ‘0’ RP2R: Peripheral Output Function is Assigned to RP2 Output Pin bits (see Table 10-14 for peripheral function numbers) DS39974A-page 170 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-27: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 (BANKED EC3h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP3R4 R/W-0 RP3R3 R/W-0 RP3R2 R/W-0 RP3R1 R/W-0 RP3R0 bit 0 Unimplemented: Read as ‘0’ RP3R: Peripheral Output Function is Assigned to RP3 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-28: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 (BANKED EC4h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP4R4 R/W-0 RP4R3 R/W-0 RP4R2 R/W-0 RP4R1 R/W-0 RP4R0 bit 0 Unimplemented: Read as ‘0’ RP4R: Peripheral Output Function is Assigned to RP4 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-29: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 (BANKED EC5h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP5R4 R/W-0 RP5R3 R/W-0 RP5R2 R/W-0 RP5R1 R/W-0 RP5R0 bit 0 Unimplemented: Read as ‘0’ RP5R: Peripheral Output Function is Assigned to RP5 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. Preliminary DS39974A-page 171 PIC18F47J13 FAMILY REGISTER 10-30: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 (BANKED EC6h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP6R4 R/W-0 RP6R3 R/W-0 RP6R2 R/W-0 RP6R1 R/W-0 RP6R0 bit 0 Unimplemented: Read as ‘0’ RP6R: Peripheral Output Function is Assigned to RP6 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-31: RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 (BANKED EC7h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP7R4 R/W-0 RP7R3 R/W-0 RP7R2 R/W-0 RP7R1 R/W-0 RP7R0 bit 0 Unimplemented: Read as ‘0’ RP7R: Peripheral Output Function is Assigned to RP7 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-32: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 (BANKED EC8h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP8R4 R/W-0 RP8R3 R/W-0 RP8R2 R/W-0 RP8R1 R/W-0 RP8R0 bit 0 Unimplemented: Read as ‘0’ RP8R: Peripheral Output Function is Assigned to RP8 Output Pin bits (see Table 10-14 for peripheral function numbers) DS39974A-page 172 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-33: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 (BANKED EC9h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP9R4 R/W-0 RP9R3 R/W-0 RP9R2 R/W-0 RP9R1 R/W-0 RP9R0 bit 0 Unimplemented: Read as ‘0’ RP9R: Peripheral Output Function is Assigned to RP9 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-34: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 (BANKED ECAh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP10R4 R/W-0 RP10R3 R/W-0 RP10R2 R/W-0 RP10R1 R/W-0 RP10R0 bit 0 Unimplemented: Read as ‘0’ RP10R: Peripheral Output Function is Assigned to RP10 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-35: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 (BANKED ECBh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP11R4 R/W-0 RP11R3 R/W-0 RP11R2 R/W-0 RP11R1 R/W-0 RP11R0 bit 0 Unimplemented: Read as ‘0’ RP11R: Peripheral Output Function is Assigned to RP11 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. Preliminary DS39974A-page 173 PIC18F47J13 FAMILY REGISTER 10-36: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 (BANKED ECCh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP12R4 R/W-0 RP12R3 R/W-0 RP12R2 R/W-0 RP12R1 R/W-0 RP12R0 bit 0 Unimplemented: Read as ‘0’ RP12R: Peripheral Output Function is Assigned to RP12 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-37: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 (BANKED ECDh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP13R4 R/W-0 RP13R3 R/W-0 RP13R2 R/W-0 RP13R1 R/W-0 RP13R0 bit 0 Unimplemented: Read as ‘0’ RP13R: Peripheral Output Function is Assigned to RP13 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-38: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 (BANKED ECEh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP14R4 R/W-0 RP14R3 R/W-0 RP14R2 R/W-0 RP14R1 R/W-0 RP14R0 bit 0 Unimplemented: Read as ‘0’ RP14R: Peripheral Output Function is Assigned to RP14 Output Pin bits (see Table 10-14 for peripheral function numbers) DS39974A-page 174 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-39: RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 (BANKED ECFh) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP15R4 R/W-0 RP15R3 R/W-0 RP15R2 R/W-0 RP15R1 R/W-0 RP15R0 bit 0 Unimplemented: Read as ‘0’ RP15R: Peripheral Output Function is Assigned to RP15 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-40: RPOR16: PERIPHERAL PIN SELECT OUTPUT REGISTER 16 (BANKED ED0h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP16R4 R/W-0 RP16R3 R/W-0 RP16R2 R/W-0 RP16R1 R/W-0 RP16R0 bit 0 Unimplemented: Read as ‘0’ RP16R: Peripheral Output Function is Assigned to RP16 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-41: RPOR17: PERIPHERAL PIN SELECT OUTPUT REGISTER 17 (BANKED ED1h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP17R4 R/W-0 RP17R3 R/W-0 RP17R2 R/W-0 RP17R1 R/W-0 RP17R0 bit 0 Unimplemented: Read as ‘0’ RP17R: Peripheral Output Function is Assigned to RP17 Output Pin bits (see Table 10-14 for peripheral function numbers)  2010 Microchip Technology Inc. Preliminary DS39974A-page 175 PIC18F47J13 FAMILY REGISTER 10-42: RPOR18: PERIPHERAL PIN SELECT OUTPUT REGISTER 18 (BANKED ED2h) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP18R4 R/W-0 RP18R3 R/W-0 RP18R2 R/W-0 RP18R1 R/W-0 RP18R0 bit 0 Unimplemented: Read as ‘0’ RP18R: Peripheral Output Function is Assigned to RP18 Output Pin bits (see Table 10-14 for peripheral function numbers) REGISTER 10-43: RPOR19: PERIPHERAL PIN SELECT OUTPUT REGISTER 19 (BANKED ED3h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP19R4 R/W-0 RP19R3 R/W-0 RP19R2 R/W-0 RP19R1 R/W-0 RP19R0 bit 0 Unimplemented: Read as ‘0’ RP19R: Peripheral Output Function is Assigned to RP19 Output Pin bits (see Table 10-14 for peripheral function numbers) RP19 pins are not available on 28-pin devices. Note 1: REGISTER 10-44: RPOR20: PERIPHERAL PIN SELECT OUTPUT REGISTER 20 (BANKED ED4h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP20R4 R/W-0 RP20R3 R/W-0 RP20R2 R/W-0 RP20R1 R/W-0 RP20R0 bit 0 Unimplemented: Read as ‘0’ RP20R: Peripheral Output Function is Assigned to RP20 Output Pin bits (see Table 10-14 for peripheral function numbers) RP20 pins are not available on 28-pin devices. Note 1: DS39974A-page 176 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 10-45: RPOR21: PERIPHERAL PIN SELECT OUTPUT REGISTER 21 (BANKED ED5h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP21R4 R/W-0 RP21R3 R/W-0 RP21R2 R/W-0 RP21R1 R/W-0 RP21R0 bit 0 Unimplemented: Read as ‘0’ RP21R: Peripheral Output Function is Assigned to RP21 Output Pin bits (see Table 10-14 for peripheral function numbers) RP21 pins are not available on 28-pin devices. Note 1: REGISTER 10-46: RPOR22: PERIPHERAL PIN SELECT OUTPUT REGISTER 22 (BANKED ED6h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP22R4 R/W-0 RP22R3 R/W-0 RP22R2 R/W-0 RP22R1 R/W-0 RP22R0 bit 0 Unimplemented: Read as ‘0’ RP22R: Peripheral Output Function is Assigned to RP22 Output Pin bits (see Table 10-14 for peripheral function numbers) RP22 pins are not available on 28-pin devices. Note 1: REGISTER 10-47: RPOR23: PERIPHERAL PIN SELECT OUTPUT REGISTER 23 (BANKED ED7h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP23R4 R/W-0 RP23R3 R/W-0 RP23R2 R/W-0 RP23R1 R/W-0 RP23R0 bit 0 Unimplemented: Read as ‘0’ RP23R: Peripheral Output Function is Assigned to RP23 Output Pin bits (see Table 10-14 for peripheral function numbers) RP23 pins are not available on 28-pin devices. Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 177 PIC18F47J13 FAMILY REGISTER 10-48: RPOR24: PERIPHERAL PIN SELECT OUTPUT REGISTER 24 (BANKED ED8h)(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4-0 R/W = Readable bit, Writable bit if IOLOCK = 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP24R4 R/W-0 RP24R3 R/W-0 RP24R2 R/W-0 RP24R1 R/W-0 RP24R0 bit 0 Unimplemented: Read as ‘0’ RP24R: Peripheral Output Function is Assigned to RP24 Output Pin bits (see Table 10-14 for peripheral function numbers) RP24 pins are not available on 28-pin devices. Note 1: DS39974A-page 178 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.0 PARALLEL MASTER PORT (PMP) Key features of the PMP module are: • Up to 16 bits of Addressing when using Data/Address Multiplexing • Up to 8 Programmable Address Lines • One Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep, Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels The Parallel Master Port module (PMP) is an 8-bit parallel I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. The PMP module can be configured to serve as either a PMP or as a Parallel Slave Port (PSP). Note: The PMP module is not implemented on 28-pin devices. It is available only on the PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13. FIGURE 11-1: PMP MODULE OVERVIEW Address Bus Data Bus PMA PMALL PMA PMALH PIC18 Parallel Master Port Control Lines Up to 8-Bit Address PMA EEPROM PMCS PMBE PMRD PMRD/PMWR PMWR PMENB PMD PMA PMA Microcontroller LCD FIFO Buffer 8-Bit Data  2010 Microchip Technology Inc. Preliminary DS39974A-page 179 PIC18F47J13 FAMILY 11.1 Module Registers The PMP module has a total of 14 Special Function Registers (SFRs) for its operation, plus one additional register to set configuration options. Of these, eight registers are used for control and six are used for PMP data transfer. The PMCON registers (Register 11-1 and Register 11-2) control basic module operations, including turning the module on or off. They also configure address multiplexing and control strobe configuration. The PMMODE registers (Register 11-3 and Register 11-4) configure the various Master and Slave modes, the data width and interrupt generation. The PMEH and PMEL registers (Register 11-5 and Register 11-6) configure the module’s operation at the hardware (I/O pin) level. The PMSTAT registers (Register 11-5 and Register 11-6) provide status flags for the module’s input and output buffers, depending on the operating mode. 11.1.1 CONTROL REGISTERS The eight PMP Control registers are: • PMCONH and PMCONL • PMMODEH and PMMODEL • PMSTATL and PMSTATH • PMEH and PMEL REGISTER 11-1: R/W-0 PMPEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PMCONH: PARALLEL PORT CONTROL REGISTER HIGH BYTE (BANKED F5Fh)(1) U-0 — U-0 — R/W-0 ADRMUX1 R/W-0 ADRMUX0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as ‘0’ ADRMUX: Address/Data Multiplexing Selection bits 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins (only eight bits of address are available in this mode) 00 = Address and data appear on separate pins (only eight bits of address are available in this mode) PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled This register is only available on 44-pin devices. bit 6-5 bit 4-3 bit 2 bit 1 bit 0 Note 1: DS39974A-page 180 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 11-2: R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMCONL: PARALLEL PORT CONTROL REGISTER LOW BYTE (BANKED F5Eh)(1) R/W-0(2) ALP U-0 — R/W-0(2) CS1P R/W-0 BEP R/W-0 WRSP R/W-0 RDSP bit 0 R/W-0 CSF0 CSF: Chip Select Function bits 11 = Reserved 10 = Chip select function is enabled and PMCS acts as chip select (in Master mode). Up to 13 address bits only can be generated. 01 = Reserved 00 = Chip select function is disabled (in Master mode). All 16 address bits can be generated. ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Unimplemented: Maintain as ‘0’ CS1P: Chip Select Polarity bit(2) 1 = Active-high (PMCS) 0 = Active-low (PMCS) BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master Mode 1 (PMMODEH = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODEH = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master Mode 1 (PMMODEH = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) This register is only available on 44-pin devices. These bits have no effect when their corresponding pins are used as address lines. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2:  2010 Microchip Technology Inc. Preliminary DS39974A-page 181 PIC18F47J13 FAMILY REGISTER 11-3: R-0 BUSY bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMMODEH: PARALLEL PORT MODE REGISTER HIGH BYTE (BANKED F5Dh)(1) R/W-0 IRQM0 R/W-0 INCM1 R/W-0 INCM0 R/W-0 MODE16 R/W-0 MODE1 R/W-0 MODE0 bit 0 R/W-0 IRQM1 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated INCM: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR by 1 every read/write cycle 01 = Increment ADDR by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer MODE: Parallel Port Mode Select bits 11 = Master Mode 1 (PMCS, PMRD/PMWR, PMENB, PMBE, PMA and PMD) 10 = Master Mode 2 (PMCS, PMRD, PMWR, PMBE, PMA and PMD) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS, PMD and PMA) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS and PMD) This register is only available on 44-pin devices. bit 6-5 bit 4-3 bit 2 bit 1-0 Note 1: DS39974A-page 182 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 11-4: R/W-0 WAITB1(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMMODEL: PARALLEL PORT MODE REGISTER LOW BYTE (BANKED F5Ch)(1) R/W-0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1(2) R/W-0 WAITE0(2) bit 0 R/W-0 WAITB0(2) WAITB: Data Setup to Read/Write Wait State Configuration bits(2) 11 = Data Wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data Wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data Wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data Wait of 1 TCY; multiplexed address phase of 1 TCY WAITM: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY . . . 0001 = Wait of additional 1 TCY 0000 = No additional Wait cycles (operation forced into one TCY) WAITE: Data Hold After Strobe Wait State Configuration bits(2) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY This register is only available on 44-pin devices. WAITBx and WAITEx bits are ignored whenever WAITM = 0000. bit 5-2 bit 1-0 Note 1: 2:  2010 Microchip Technology Inc. Preliminary DS39974A-page 183 PIC18F47J13 FAMILY REGISTER 11-5: R/W-0 PTEN15 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMEH: PARALLEL PORT ENABLE REGISTER HIGH BYTE (BANKED F57h)(1) R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 0 R/W-0 PTEN14 PTEN: PMCS Port Enable bits 1 = PMA function as either PMA or PMCS 0 = PMA function as port I/O PTEN: PMP Address Port Enable bits 1 = PMA function as PMP address lines 0 = PMA function as port I/O This register is only available on 44-pin devices. bit 5-0 Note 1: REGISTER 11-6: R/W-0 PTEN7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 PMEL: PARALLEL PORT ENABLE REGISTER LOW BYTE (BANKED F56h)(1) R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 R/W-0 PTEN0 bit 0 R/W-0 PTEN6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PTEN: PMP Address Port Enable bits 1 = PMA function as PMP address lines 0 = PMA function as port I/O PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA function as either PMA or PMALH and PMALL 0 = PMA pads functions as port I/O This register is only available on 44-pin devices. bit 1-0 Note 1: DS39974A-page 184 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 11-7: R-0 IBF bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PMSTATH: PARALLEL PORT STATUS REGISTER HIGH BYTE (BANKED F55h)(1) U-0 — U-0 — R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 0 IBOV R/W-0 IBF: Input Buffer Full Status bit 1 = All writable Input Buffer registers are full 0 = Some or all of the writable Input Buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full Input Byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as ‘0’ IBF: Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading the buffer will clear this bit) 0 = Input buffer does not contain any unread data This register is only available on 44-pin devices. bit 6 bit 5-4 bit 3-0 Note 1: REGISTER 11-8: R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 PMSTATL: PARALLEL PORT STATUS REGISTER LOW BYTE (BANKED F54h)(1) U-0 — U-0 — R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0 R/W-0 OBUF W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OBE: Output Buffer Empty Status bit 1 = All readable Output Buffer registers are empty 0 = Some or all of the readable Output Buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty Output Byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OBE: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted This register is only available on 44-pin devices. bit 6 bit 5-4 bit 3-0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 185 PIC18F47J13 FAMILY 11.1.2 DATA REGISTERS The PMP module uses eight registers for transferring data into and out of the microcontroller. They are arranged as four pairs to allow the option of 16-bit data operations: • • • • PMDIN1H and PMDIN1L PMDIN2H and PMDIN2L PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L PMDOUT2H and PMDOUT2L PMADDRH differs from PMADDRL in that it can also have limited PMP control functions. When the module is operating in select Master mode configurations, the upper two bits of the register can be used to determine the operation of chip select signals. If these are not used, PMADDR simply functions to hold the upper 8 bits of the address. Register 11-9 provides the function of the individual bits in PMADDRH. The PMDOUT2H and PMDOUT2L registers are only used in Buffered Slave modes and serve as a buffer for outgoing data. The PMDIN1 registers are used for incoming data in Slave modes, and both input and output data in Master modes. The PMDIN2 registers are used for buffering input data in select Slave modes. The PMADDR/PMDOUT1 registers are actually a single register pair; the name and function are dictated by the module’s operating mode. In Master modes, the registers function as the PMADDRH and PMADDRL registers, and contain the address of any incoming or outgoing data. In Slave modes, the registers function as PMDOUT1H and PMDOUT1L, and are used for outgoing data. 11.1.3 PAD CONFIGURATION CONTROL REGISTER In addition to the module level configuration options, the PMP module can also be configured at the I/O pin for electrical operation. This option allows users to select either the normal Schmitt Trigger input buffer on digital I/O pins shared with the PMP, or use TTL level compatible buffers instead. Buffer configuration is controlled by the PMPTTL bit in the PADCFG1 register. DS39974A-page 186 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 11-9: U0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared r = Reserved x = Bit is unknown PMADDRH: PARALLEL PORT ADDRESS REGISTER HIGH BYTE (MASTER MODES ONLY) (ACCESS F6Fhh)(1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 CS1 Parallel Master Port Address High Byte R/W-0 Unimplemented: Read as ‘0’ CS1: Chip Select bit If PMCON = 10: 1 = Chip select is active 0 = Chip select is inactive If PMCON = 11 or 00: Bits function as ADDR. Parallel Master Port Address: High Byte bits In Enhanced Slave mode, PMADDRH functions as PMDOUT1H, one of the Output Data Buffer registers. bit 5-0 Note 1: REGISTER 11-10: PMADDRL: PARALLEL PORT ADDRESS REGISTER LOW BYTE (MASTER MODES ONLY) (ACCESS F6Eh)(1) R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared r = Reserved x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 Parallel Master Port Address Low Byte Parallel Master Port Address: Low Byte bits In Enhanced Slave mode, PMADDRL functions as PMDOUT1L, one of the Output Data Buffer registers.  2010 Microchip Technology Inc. Preliminary DS39974A-page 187 PIC18F47J13 FAMILY 11.2 Slave Port Modes The primary mode of operation for the module is configured using the MODE bits in the PMMODEH register. The setting affects whether the module acts as a slave or a master and it determines the usage of the control pins. pins dedicated to the module. In this mode, an external device, such as another microcontroller or microprocessor, can asynchronously read and write data using the 8-bit data bus (PMD), the read (PMRD), write (PMWR) and chip select (PMCS) inputs. It acts as a slave on the bus and responds to the read/write control signals. Figure 11-2 displays the connection of the PSP. When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD is captured into the PMDIN1L register. 11.2.1 LEGACY MODE (PSP) In Legacy mode (PMMODEH = 00 and PMPEN = 1), the module is configured as a Parallel Slave Port (PSP) with the associated enabled module FIGURE 11-2: Master LEGACY PARALLEL SLAVE PORT EXAMPLE PIC18 Slave PMD PMCS PMRD PMWR Address Bus Data Bus Control Lines PMD PMCS PMRD PMWR DS39974A-page 188 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.2.2 WRITE TO SLAVE PORT 11.2.3 READ FROM SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD is captured into the lower PMDIN1L register. The PMPIF and IBF flag bits are set when the write ends.The timing for the control signals in Write mode is displayed in Figure 11-3. The polarity of the control signals are configurable. When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from the PMDOUT1L register (PMDOUT1L) is presented on to PMD. Figure 11-4 provides the timing for the control signals in Read mode. FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD IBF OBE PMPIF FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD IBF OBE PMPIF  2010 Microchip Technology Inc. Preliminary DS39974A-page 189 PIC18F47J13 FAMILY 11.2.4 BUFFERED PARALLEL SLAVE PORT MODE 11.2.4.2 WRITE TO SLAVE PORT Buffered Parallel Slave Port mode is functionally identical to the Legacy PSP mode with one exception, the implementation of 4-level read and write buffers. Buffered PSP mode is enabled by setting the INCM bits in the PMMODEH register. If the INCM bits are set to ‘11’, the PMP module will act as the buffered PSP. When the Buffered PSP mode is active, the PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H registers become the write buffers and the PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H registers become the read buffers. Buffers are numbered, 0 through 3, starting with the lower byte of PMDIN1L to PMDIN2H as the read buffers and PMDOUT1L to PMDOUT2H as the write buffers. For write operations, the data has to be stored sequentially, starting with Buffer 0 (PMDIN1L) and ending with Buffer 3 (PMDIN2H). As with read operations, the module maintains an internal pointer to the buffer that is to be written next. The input buffers have their own write status bits: IBxF in the PMSTATH register. The bit is set when the buffer contains unread incoming data and cleared when the data has been read. The flag bit is set on the write strobe. If a write occurs on a buffer when its associated IBxF bit is set, the Buffer Overflow flag, IBOV, is set; any incoming data in the buffer will be lost. If all four IBxF flags are set, the Input Buffer Full Flag (IBF) is set. In Buffered Slave mode, the module can be configured to generate an interrupt on every read or write strobe (IRQM = 01). It can be configured to generate an interrupt on a read from Read Buffer 3 or a write to Write Buffer 3, which is essentially an interrupt every fourth read or write strobe (RQM = 11). When interrupting every fourth byte for input data, all Input Buffer registers should be read to clear the IBxF flags. If these flags are not cleared, then there is a risk of hitting an overflow condition. 11.2.4.1 READ FROM SLAVE PORT For read operations, the bytes will be sent out sequentially, starting with Buffer 0 (PMDOUT1L) and ending with Buffer 3 (PMDOUT2H) for every read strobe. The module maintains an internal pointer to keep track of which buffer is to be read. Each buffer has a corresponding read status bit, OBxE, in the PMSTATL register. This bit is cleared when a buffer contains data that has not been written to the bus and is set when data is written to the bus. If the current buffer location being read from is empty, a buffer underflow is generated and the Buffer Overflow Flag bit, OBUF, is set. If all four OBxE status bits are set, then the Output Buffer Empty flag (OBE) will also be set. FIGURE 11-5: PARALLEL MASTER/SLAVE CONNECTION BUFFERED EXAMPLE Master PMD PMD Write Address Pointer PIC18 Slave Read Address Pointer PMDOUT1L (0) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMCS PMRD PMWR PMCS PMRD PMWR PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3) Data Bus Control Lines DS39974A-page 190 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.2.5 ADDRESSABLE PARALLEL SLAVE PORT MODE TABLE 11-1: SLAVE MODE BUFFER ADDRESSING Output Register (Buffer) PMDOUT1L (0) PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H((3) Input Register (Buffer) PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) In the Addressable Parallel Slave Port mode (PMMODEH = 01), the module is configured with two extra inputs, PMA, which are the Address Lines 1 and 0. This makes the 4-byte buffer space directly addressable as fixed pairs of read and write buffers. As with Legacy Buffered mode, data is output from PMDOUT1L, PMDOUT1H, PMDOUT2L and PMDOUT2H, and is read in PMDIN1L, PMDIN1H, PMDIN2L and PMDIN2H. Table 11-1 provides the buffer addressing for the incoming address to the input and output registers. PMA 00 01 10 11 FIGURE 11-6: Master PMA PARALLEL MASTER/SLAVE CONNECTION ADDRESSED BUFFER EXAMPLE PMA PMD Write Address Decode PMDOUT1L (0) PIC18F Slave PMD Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMCS PMRD PMWR Address Bus Data Bus Control Lines PMCS PMRD PMWR PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3) 11.2.5.1 READ FROM SLAVE PORT When chip select is active and a read strobe occurs (PMCS = 1 and PMRD = 1), the data from one of the four output bytes is presented onto PMD. Which byte is read depends on the 2-bit address placed on ADDR. Table 11-1 provides the corresponding output registers and their associated address. When an output buffer is read, the corresponding OBxE bit is set. The OBxE flag bit is set when all the buffers are empty. If any buffer is already empty (OBxE = 1), the next read to that buffer will generate an OBUF event. FIGURE 11-7: PARALLEL SLAVE PORT READ WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD PMA OBE PMPIF  2010 Microchip Technology Inc. Preliminary DS39974A-page 191 PIC18F47J13 FAMILY 11.2.5.2 WRITE TO SLAVE PORT When chip select is active and a write strobe occurs (PMCS = 1 and PMWR = 1), the data from PMD is captured into one of the four input buffer bytes. Which byte is written depends on the 2-bit address placed on ADDRL. Table 11-1 provides the corresponding input registers and their associated address. When an input buffer is written, the corresponding IBxF bit is set. The IBF flag bit is set when all the buffers are written. If any buffer is already written (IBxF = 1), the next write strobe to that buffer will generate an OBUF event and the byte will be discarded. FIGURE 11-8: PARALLEL SLAVE PORT WRITE WAVEFORMS | Q4 | Q1 | Q2 | Q3 | Q4 PMCS PMWR PMRD PMD PMA IBF PMPIF DS39974A-page 192 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.3 MASTER PORT MODES In its Master modes, the PMP module provides an 8-bit data bus, up to 16 bits of address, and all the necessary control signals to operate a variety of external parallel devices, such as memory devices, peripherals and slave microcontrollers. To use the PMP as a master, the module must be enabled (PMPEN = 1) and the mode must be set to one of the two possible Master modes (PMMODEH = 10 or 11). Because there are a number of parallel devices with a variety of control methods, the PMP module is designed to be extremely flexible to accommodate a range of configurations. Some of these features include: • • • • • • • 8-Bit and 16-Bit Data modes on an 8-bit data bus Configurable address/data multiplexing Up to two chip select lines Up to 16 selectable address lines Address auto-increment and auto-decrement Selectable polarity on all control lines Configurable Wait states at different stages of the read/write cycle same output pin (for example, PMWR and PMENB) are controlled by the same bit; the configuration depends on which Master Port mode is being used. 11.3.3 DATA WIDTH The PMP supports data widths of both 8 bits and 16 bits. The data width is selected by the MODE16 bit (PMMODEH). Because the data path into and out of the module is only 8 bits wide, 16-bit operations are always handled in a multiplexed fashion, with the Least Significant Byte (LSB) of data being presented first. To differentiate data bytes, the byte enable control strobe, PMBE, is used to signal when the Most Significant Byte (MSB) of data is being presented on the data lines. 11.3.4 ADDRESS MULTIPLEXING In either of the Master modes (PMMODEH = 1x), the user can configure the address bus to be multiplexed together with the data bus. This is accomplished by using the ADRMUX bits (PMCONH). There are three address multiplexing modes available. Typical pinout configurations for these modes are displayed in Figure 11-9, Figure 11-10 and Figure 11-11. In Demultiplexed mode (PMCONH = 00), data and address information are completely separated. Data bits are presented on PMD, and address bits are presented on PMADDRH and PMADDRL. In Partially Multiplexed mode (PMCONH = 01), the lower eight bits of the address are multiplexed with the data pins on PMD. The upper eight bits of the address are unaffected and are presented on PMADDRH. The PMA0 pin is used as an address latch and presents the Address Latch Low (PMALL) enable strobe. The read and write sequences are extended by a complete CPU cycle during which the address is presented on the PMD pins. In Fully Multiplexed mode (PMCONH = 10), the entire 16 bits of the address are multiplexed with the data pins on PMD. The PMA0 and PMA1 pins are used to present Address Latch Low (PMALL) enable and Address Latch High (PMALH) enable strobes, respectively. The read and write sequences are extended by two complete CPU cycles. During the first cycle, the lower eight bits of the address are presented on the PMD pins with the PMALL strobe active. During the second cycle, the upper eight bits of the address are presented on the PMD pins with the PMALH strobe active. In the event the upper address bits are configured as chip select pins, the corresponding address bits are automatically forced to ‘0’. 11.3.1 PMP AND I/O PIN CONTROL Multiple control bits are used to configure the presence or absence of control and address signals in the module. These bits are PTBEEN, PTWREN, PTRDEN and PTEN. They give the user the ability to conserve pins for other functions and allow flexibility to control the external address. When any one of these bits is set, the associated function is present on its associated pin; when clear, the associated pin reverts to its defined I/O port function. Setting a PTENx bit will enable the associated pin as an address pin and drive the corresponding data contained in the PMADDR register. Clearing a PTENx bit will force the pin to revert to its original I/O function. For the pins configured as chip select (PMCS) with the corresponding PTENx bit set, the PTEN0 and PTEN1 bits will also control the PMALL and PMALH signals. When multiplexing is used, the associated address latch signals should be enabled. 11.3.2 READ/WRITE-CONTROL The PMP module supports two distinct read/write signaling methods. In Master Mode 1, read and write strobes are combined into a single control line, PMRD/PMWR. A second control line, PMENB, determines when a read or write action is to be taken. In Master Mode 2, separate read and write strobes (PMRD and PMWR) are supplied on separate pins. All control signals (PMRD, PMWR, PMBE, PMENB, PMAL and PMCS) can be individually configured as either positive or negative polarity. Configuration is controlled by separate bits in the PMCONL register. Note that the polarity of control signals that share the  2010 Microchip Technology Inc. Preliminary DS39974A-page 193 PIC18F47J13 FAMILY FIGURE 11-9: DEMULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMA PMD PMCS PMRD PMWR Address Bus Data Bus Control Lines FIGURE 11-10: PARTIALLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD PMA PMCS PMALL PMRD PMWR Address Bus Multiplexed Data and Address Bus Control Lines FIGURE 11-11: FULLY MULTIPLEXED ADDRESSING MODE (SEPARATE READ AND WRITE STROBES WITH CHIP SELECT) PIC18F PMD PMA PMCS PMALL PMALH PMRD PMWR Multiplexed Data and Address Bus Control Lines DS39974A-page 194 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.3.5 CHIP SELECT FEATURES A chip select line, PMCS, is available for the Master modes of the PMP. The chip select line is multiplexed with the second Most Significant bit (MSb) of the address bus (PMADDRH). When configured for chip select, the PMADDRH bits are not included in any address auto-increment/decrement. The function of the chip select signal is configured using the chip select function bits (PMCONL). If the 16-bit mode is enabled (MODE16 = 1), the read of the low byte of the PMDIN1L register will initiate two bus reads. The first read data byte is placed into the PMDIN1L register and the second read data byte is placed into the PMDIN1H. Note that the read data obtained from the PMDIN1L register is actually the read value from the previous read operation. Hence, the first user read will be a dummy read to initiate the first bus read and fill the read register. Also, the requested read value will not be ready until after the BUSY bit is observed low. Thus, in a back-to-back read operation, the data read from the register will be the same for both reads. The next read of the register will yield the new value. 11.3.6 AUTO-INCREMENT/DECREMENT While the module is operating in one of the Master modes, the INCMx bits (PMMODEH) control the behavior of the address value. The address can be made to automatically increment or decrement after each read and write operation. The address increments once each operation is completed and the BUSY bit goes to ‘0’. If the chip select signals are disabled and configured as address bits, the bits will participate in the increment and decrement operations; otherwise, the CS1 bit values will be unaffected. 11.3.9 WRITE OPERATION 11.3.7 WAIT STATES In Master mode, the user has control over the duration of the read, write and address cycles by configuring the module Wait states. Three portions of the cycle, the beginning, middle and end, are configured using the corresponding WAITBx, WAITMx and WAITEx bits in the PMMODEL register. The WAITBx bits (PMMODEL) set the number of Wait cycles for the data setup prior to the PMRD/PMWT strobe in Mode 10, or prior to the PMENB strobe in Mode 11. The WAITMx bits (PMMODEL) set the number of Wait cycles for the PMRD/PMWT strobe in Mode 10, or for the PMENB strobe in Mode 11. When this Wait state setting is ‘0’, then WAITB and WAITE have no effect. The WAITE bits (PMMODEL) define the number of Wait cycles for the data hold time after the PMRD/PMWT strobe in Mode 10 or after the PMENB strobe in Mode 11. To perform a write onto the parallel bus, the user writes to the PMDIN1L register. This causes the module to first output the desired values on the chip select lines and the address bus. The write data from the PMDIN1L register is placed onto the PMD data bus. Then, the write line (PMWR) is strobed. If the 16-bit mode is enabled (MODE16 = 1), the write to the PMDIN1L register will initiate two bus writes. The first write will consist of the data contained in PMDIN1L and the second write will contain the PMDIN1H. 11.3.10 11.3.10.1 PARALLEL MASTER PORT STATUS The BUSY Bit In addition to the PMP interrupt, a BUSY bit is provided to indicate the status of the module. This bit is used only in Master mode. While any read or write operation is in progress, the BUSY bit is set for all but the very last CPU cycle of the operation. In effect, if a single-cycle read or write operation is requested, the BUSY bit will never be active. This allows back-to-back transfers. While the bit is set, any request by the user to initiate a new operation will be ignored (i.e., writing or reading the lower byte of the PMDIN1L register will neither initiate a read nor a write). 11.3.8 READ OPERATION 11.3.10.2 Interrupts To perform a read on the PMP, the user reads the PMDIN1L register. This causes the PMP to output the desired values on the chip select lines and the address bus. Then, the read line (PMRD) is strobed. The read data is placed into the PMDIN1L register. When the PMP module interrupt is enabled for Master mode, the module will interrupt on every completed read or write cycle; otherwise, the BUSY bit is available to query the status of the module.  2010 Microchip Technology Inc. Preliminary DS39974A-page 195 PIC18F47J13 FAMILY 11.3.11 MASTER MODE TIMING This section contains a number of timing examples that represent the common Master mode configuration options. These options vary from 8-bit to 16-bit data, fully demultiplexed to fully multiplexed address and Wait states. FIGURE 11-12: READ AND WRITE TIMING, 8-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMA PMWR PMRD PMPIF BUSY FIGURE 11-13: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMALL PMPIF BUSY Address Data FIGURE 11-14: READ TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS PMD PMRD PMWR PMALL PMPIF BUSY WAITB = 01 WAITE = 00 WAITM = 0010 Address Data DS39974A-page 196 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 11-15: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMALL PMPIF BUSY Address Data FIGURE 11-16: WRITE TIMING, 8-BIT DATA, WAIT STATES ENABLED, PARTIALLY MULTIPLEXED ADDRESS Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - Q1- - - PMCS PMD PMWR PMRD PMALL PMPIF BUSY WAITB = 01 WAITE = 00 WAITM = 0010 Address Data FIGURE 11-17: READ TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMRD/PMWR PMENB PMALL PMPIF BUSY Address Data  2010 Microchip Technology Inc. Preliminary DS39974A-page 197 PIC18F47J13 FAMILY FIGURE 11-18: WRITE TIMING, 8-BIT DATA, PARTIALLY MULTIPLEXED ADDRESS, ENABLE STROBE Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMRD/PMWR PMENB PMALL PMPIF BUSY Address Data FIGURE 11-19: READ TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMALL PMALH PMPIF BUSY Address Address Data FIGURE 11-20: WRITE TIMING, 8-BIT DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMALL PMALH PMPIF BUSY Address Address Data DS39974A-page 198 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 11-21: READ TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMA PMWR PMRD PMBE PMPIF BUSY LSB MSB FIGURE 11-22: WRITE TIMING, 16-BIT DATA, DEMULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMA PMWR PMRD PMBE PMPIF BUSY LSB MSB FIGURE 11-23: READ TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMBE PMALL PMPIF BUSY Address LSB MSB  2010 Microchip Technology Inc. Preliminary DS39974A-page 199 PIC18F47J13 FAMILY FIGURE 11-24: WRITE TIMING, 16-BIT MULTIPLEXED DATA, PARTIALLY MULTIPLEXED ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMBE PMALL PMPIF BUSY Address LSB MSB FIGURE 11-25: READ TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMBE PMALH PMALL PMPIF BUSY Address Address LSB MSB FIGURE 11-26: WRITE TIMING, 16-BIT MULTIPLEXED DATA, FULLY MULTIPLEXED 16-BIT ADDRESS Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 PMCS PMD PMWR PMRD PMBE PMALH PMALL PMPIF BUSY Address Address LSB MSB DS39974A-page 200 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 11.4 Application Examples 11.4.1 This section introduces some potential applications for the PMP module. MULTIPLEXED MEMORY OR PERIPHERAL Figure 11-27 demonstrates the hookup of a memory or another addressable peripheral in Full Multiplex mode. Consequently, this mode achieves the best pin saving from the microcontroller perspective. However, for this configuration, there needs to be some external latches to maintain the address. FIGURE 11-27: MULTIPLEXED ADDRESSING APPLICATION EXAMPLE 373 A D A A D CE OE WR Address Bus Data Bus Control Lines PIC18F PMD PMALL PMALH PMCS PMRD PMWR 373 11.4.2 PARTIALLY MULTIPLEXED MEMORY OR PERIPHERAL Partial multiplexing implies using more pins; however, for a few extra pins, some extra performance can be achieved. Figure 11-28 provides an example of a memory or peripheral that is partially multiplexed with an external latch. If the peripheral has internal latches, as displayed in Figure 11-29, then no extra circuitry is required except for the peripheral itself. FIGURE 11-28: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION 373 A D A D CE OE WR Address Bus Data Bus Control Lines PIC18F PMD PMALL PMCS PMRD PMWR FIGURE 11-29: PIC18F EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION Parallel Peripheral AD ALE CS RD WR Address Bus Data Bus Control Lines PMD PMALL PMCS PMRD PMWR  2010 Microchip Technology Inc. Preliminary DS39974A-page 201 PIC18F47J13 FAMILY 11.4.3 PARALLEL EEPROM EXAMPLE Figure 11-30 provides an example connecting parallel EEPROM to the PMP. Figure 11-31 demonstrates a slight variation to this, configuring the connection for 16-bit data from a single EEPROM. FIGURE 11-30: PIC18F PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) Parallel EEPROM A D CE OE WR Address Bus Data Bus Control Lines PMA PMD PMCS PMRD PMWR FIGURE 11-31: PIC18F PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) Parallel EEPROM A D A0 CE OE WR Address Bus Data Bus Control Lines PMA PMD PMBE PMCS PMRD PMWR 11.4.4 LCD CONTROLLER EXAMPLE The PMP module can be configured to connect to a typical LCD controller interface, as displayed in Figure 11-32. In this case the PMP module is configured for active-high control signals since common LCD displays require active-high control. FIGURE 11-32: PIC18F LCD CONTROL EXAMPLE (BYTE MODE OPERATION) LCD Controller D RS R/W E PM PMA0 PMRD/PMWR PMCS Address Bus Data Bus Control Lines DS39974A-page 202 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 11-2: Name INTCON PIR1 PIE1 IPR1 PMCONH(2) PMCONL(2) PMADDRH(1,2) / PMDOUT1H(1,2) PMADDRL(1,2)/ PMDOUT1L (1,2) REGISTERS ASSOCIATED WITH PMP MODULE Bit 7 GIE/GIEH PMPIF (2) Bit 6 PEIE/GIEL ADIF ADIE ADIP — CSF0 CS1 Bit 5 TMR0IE RC1IF RC1IE RC1IP — ALP Bit 4 INT0IE TX1IF TX1IE TX1IP ADRMUX1 — Bit 3 RBIE SSP1IF SSP1IE SSP1IP ADRMUX0 CS1P Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP PTBEEN BEP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP PTWREN WRSP Bit 0 RBIF TMR1IF TMR1IE TMR1IP PTRDEN RDSP PMPIE(2) PMPIP(2) PMPEN CSF1 — Parallel Master Port Address High Byte Parallel Port Out Data High Byte (Buffer 1) Parallel Master Port Address Low Byte Parallel Port Out Data Low Byte (Buffer 0) Parallel Port Out Data High Byte (Buffer 3) Parallel Port Out Data Low Byte (Buffer 2) Parallel Port In Data High Byte (Buffer 1) Parallel Port In Data Low Byte (Buffer 0) Parallel Port In Data High Byte (Buffer 3) Parallel Port In Data Low Byte (Buffer 2) BUSY WAITB1 PTEN15 PTEN7 IBF OBE — IRQM1 WAITB0 PTEN14 PTEN6 IBOV OBUF — IRQM0 WAITM3 PTEN13 PTEN5 — — — INCM1 WAITM2 PTEN12 PTEN4 — — — INCM0 WAITM1 PTEN11 PTEN3 IB3F OB3E — MODE16 WAITM0 PTEN10 PTEN2 IB2F OB2E RTSECSEL1 MODE1 WAITE1 PTEN9 PTEN1 IB1F OB1E RTSECSEL0 MODE0 WAITE0 PTEN8 PTEN0 IB0F OB0E PMPTTL PMDOUT2H(2) PMDOUT2L(2) PMDIN1H(2) PMDIN1L(2) PMDIN2H(2) PMDIN2L(2) PMMODEH(2) PMMODEL PMEH(2) PMEL(2) PMSTATH(2) PMSTATL(2) PADCFG1 Legend: Note 1: 2: (2) — = unimplemented, read as ‘0’. Shaded cells are not used during PMP operation. The PMADDRH/PMDOUT1H and PMADDRL/PMDOUT1L register pairs share the physical registers and addresses, but have different functions determined by the module’s operating mode. These bits and/or registers are only available in 44-pin devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 203 PIC18F47J13 FAMILY NOTES: DS39974A-page 204 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 12.0 TIMER0 MODULE The Timer0 module incorporates the following features: • Software selectable operation as a timer or counter in both 8-bit or 16-bit modes • Readable and writable registers • Dedicated 8-bit, software programmable prescaler • Selectable clock source (internal or external) • Edge select for external clock • Interrupt-on-overflow The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection. It is both readable and writable. Figure 12-1 provides a simplified block diagram of the Timer0 module in 8-bit mode. Figure 12-2 provides a simplified block diagram of the Timer0 module in 16-bit mode. REGISTER 12-1: R/W-1 TMR0ON bit 7 Legend: R = Readable bit -n = Value at POR bit 7 T0CON: TIMER0 CONTROL REGISTER (ACCESS FD5h) R/W-1 T0CS R/W-1 T0SE R/W-1 PSA R/W-1 T0PS2 R/W-1 T0PS1 R/W-1 T0PS0 bit 0 R/W-1 T08BIT W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TMR0ON: Timer0 On/Off Control bit 1 = Enables Timer0 0 = Stops Timer0 T08BIT: Timer0 8-Bit/16-Bit Control bit 1 = Timer0 is configured as an 8-bit timer/counter 0 = Timer0 is configured as a 16-bit timer/counter T0CS: Timer0 Clock Source Select bit 1 = Transition on T0CKI pin input edge 0 = Internal clock (FOSC/4) T0SE: Timer0 Source Edge Select bit 1 = Increment on high-to-low transition on T0CKI pin 0 = Increment on low-to-high transition on T0CKI pin PSA: Timer0 Prescaler Assignment bit 1 = Timer0 prescaler is not assigned. Timer0 clock input bypasses prescaler. 0 = Timer0 prescaler is assigned. Timer0 clock input comes from the prescaler output. T0PS: Timer0 Prescaler Select bits 111 = 1:256 Prescale value 110 = 1:128 Prescale value 101 = 1:64 Prescale value 100 = 1:32 Prescale value 011 = 1:16 Prescale value 010 = 1:8 Prescale value 001 = 1:4 Prescale value 000 = 1:2 Prescale value bit 6 bit 5 bit 4 bit 3 bit 2-0  2010 Microchip Technology Inc. Preliminary DS39974A-page 205 PIC18F47J13 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles. The user can work around this by writing an adjusted value to the TMR0 register. The Counter mode is selected by setting the T0CS bit (= 1). In this mode, Timer0 increments either on every rising edge or falling edge of the pin, T0CKI. The incrementing edge is determined by the Timer0 Source Edge Select bit, T0SE (T0CON); clearing this bit selects the rising edge. Restrictions on the external clock input are discussed below. An external clock source can be used to drive Timer0; however, it must meet certain requirements to ensure that the external clock can be synchronized with the internal phase clock (TOSC). There is a delay between synchronization and the onset of incrementing the timer/counter. 12.2 Timer0 Reads and Writes in 16-Bit Mode TMR0H is not the actual high byte of Timer0 in 16-bit mode. It is actually a buffered version of the real high byte of Timer0, which is not directly readable nor writable (refer to Figure 12-2). TMR0H is updated with the contents of the high byte of Timer0 during a read of TMR0L. This provides the ability to read all 16 bits of Timer0 without having to verify that the read of the high and low byte were valid, due to a rollover between successive reads of the high and low byte. Similarly, a write to the high byte of Timer0 must also take place through the TMR0H Buffer register. The high byte is updated with the contents of TMR0H when a write occurs to TMR0L. This allows all 16 bits of Timer0 to be updated at once. FIGURE 12-1: TIMER0 BLOCK DIAGRAM (8-BIT MODE) FOSC/4 0 1 1 Sync with Internal Clocks (2 TCY Delay) 8 8 Internal Data Bus TMR0L Set TMR0IF on Overflow T0CKI Pin T0SE T0CS T0PS PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. FIGURE 12-2: FOSC/4 TIMER0 BLOCK DIAGRAM (16-BIT MODE) 0 1 1 Sync with Internal Clocks (2 TCY Delay) Read TMR0L Write TMR0L 8 8 TMR0H 8 8 Internal Data Bus TMR0L TMR0 High Byte 8 Set TMR0IF on Overflow T0CKI Pin T0SE T0CS T0PS PSA Programmable Prescaler 3 0 Note: Upon Reset, Timer0 is enabled in 8-bit mode with clock input from T0CKI max. prescale. DS39974A-page 206 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 12.3 Prescaler 12.3.1 An 8-bit counter is available as a prescaler for the Timer0 module. The prescaler is not directly readable or writable. Its value is set by the PSA and T0PS bits (T0CON), which determine the prescaler assignment and prescale ratio. Clearing the PSA bit assigns the prescaler to the Timer0 module. When it is assigned, prescale values from 1:2 through 1:256, in power-of-2 increments, are selectable. When assigned to the Timer0 module, all instructions writing to the TMR0 register (e.g., CLRF TMR0, MOVWF TMR0, BSF TMR0, etc.) clear the prescaler count. Note: Writing to TMR0 when the prescaler is assigned to Timer0 will clear the prescaler count but will not change the prescaler assignment. SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution. 12.4 Timer0 Interrupt The TMR0 interrupt is generated when the TMR0 register overflows from FFh to 00h in 8-bit mode, or from FFFFh to 0000h in 16-bit mode. This overflow sets the TMR0IF flag bit. The interrupt can be masked by clearing the TMR0IE bit (INTCON). Before re-enabling the interrupt, the TMR0IF bit must be cleared in software by the Interrupt Service Routine (ISR). Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. TABLE 12-1: Name TMR0L TMR0H INTCON T0CON REGISTERS ASSOCIATED WITH TIMER0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Timer0 Register Low Byte Timer0 Register High Byte GIE/GIEH TMR0ON PEIE/GIEL T08BIT TMR0IE T0CS INT0IE T0SE RBIE PSA TMR0IF T0PS2 INT0IF T0PS1 RBIF T0PS0 Legend: Shaded cells are not used by Timer0.  2010 Microchip Technology Inc. Preliminary DS39974A-page 207 PIC18F47J13 FAMILY NOTES: DS39974A-page 208 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 13.0 TIMER1 MODULE The Timer1 timer/counter module incorporates these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMR1H and TMR1L) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Reset on ECCP Special Event Trigger • Device clock status flag (SOSCRUN) • Timer with gated control Figure 13-1 displays a simplified block diagram of the Timer1 module. The module incorporates its own low-power oscillator to provide an additional clocking option. The Timer1 oscillator can also be used as a low-power clock source for the microcontroller in power-managed operation. Timer1 is controlled through the T1CON Control register (Register 13-1). It also contains the Timer1 Oscillator Enable bit (T1OSCEN). Timer1 can be enabled or disabled by setting or clearing control bit, TMR1ON (T1CON). The FOSC clock source (TMR1CS = 01) should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options. REGISTER 13-1: R/W-0 TMR1CS1 bit 7 T1CON: TIMER1 CONTROL REGISTER (ACCESS FCDh) R/W-0 T1CKPS1 R/W-0 T1CKPS0 R/W-0 T1OSCEN R/W-0 T1SYNC R/W-0 RD16 R/W-0 TMR1ON bit 0 R/W-0 TMR1CS0 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 5-4 bit 3 bit 2 bit 1 bit 0 TMR1CS: Timer1 Clock Source Select bits 10 = Timer1 clock source is the T1OSC or T1CKI pin 01 = Timer1 clock source is the system clock (FOSC)(1) 00 = Timer1 clock source is the instruction clock (FOSC/4) T1CKPS: Timer1 Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value T1OSCEN: Timer1 Oscillator Source Select bit When TMR1CS = 10: 1 = Power up the Timer1 crystal driver and supply the Timer1 clock from the crystal output 0 = Timer1 crystal driver is off, Timer1 clock is from the T1CKI input pin(2) When TMR1CS = 0x: 1 = Power up the Timer1 crystal driver 0 = Timer1 crystal driver is off(2) T1SYNC: Timer1 External Clock Input Synchronization Select bit TMR1CS = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input TMR1CS = 0x: This bit is ignored. Timer1 uses the internal clock when TMR1CS = 0x. RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of Timer1 in one 16-bit operation 0 = Enables register read/write of Timer1 in two 8-bit operations TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. The Timer1 oscillator crystal driver is powered whenever T1OSCEN (T1CON) or T3OSCEN (T3CON) = 1. The circuit is enabled by the logical OR of these two bits. When disabled, the inverter and feedback resistor are disabled to eliminate power drain. The TMR1ON and TMR3ON bits do not have to be enabled to power up the crystal driver. Note 1: 2:  2010 Microchip Technology Inc. Preliminary DS39974A-page 209 PIC18F47J13 FAMILY 13.1 Timer1 Gate Control Register The Timer1 Gate Control register (T1GCON), displayed in Register 13-2, is used to control the Timer1 gate. REGISTER 13-2: R/W-0 TMR1GE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 T1GCON: TIMER1 GATE CONTROL REGISTER (ACCESS F9Ah)(1) R/W-0 T1GTM R/W-0 T1GSPM R/W-0 T1GGO/T1DONE R-x T1GVAL R/W-0 T1GSS1 R/W-0 T1GSS0 bit 0 R/W-0 T1GPOL W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TMR1GE: Timer1 Gate Enable bit If TMR1ON = 0: This bit is ignored. If TMR1ON = 1: 1 = Timer1 counting is controlled by the Timer1 gate function 0 = Timer1 counts regardless of the Timer1 gate function T1GPOL: Timer1 Gate Polarity bit 1 = Timer1 gate is active-high (Timer1 counts when gate is high) 0 = Timer1 gate is active-low (Timer1 counts when gate is low) T1GTM: Timer1 Gate Toggle Mode bit 1 = Timer1 Gate Toggle mode is enabled 0 = Timer1 Gate Toggle mode is disabled and toggle flip-flop is cleared Timer1 gate flip-flop toggles on every rising edge. T1GSPM: Timer1 Gate Single Pulse Mode bit 1 = Timer1 Gate Single Pulse mode is enabled and is controlling the Timer1 gate 0 = Timer1 Gate Single Pulse mode is disabled T1GGO/T1DONE: Timer1 Gate Single Pulse Acquisition Status bit 1 = Timer1 gate single pulse acquisition is ready, waiting for an edge 0 = Timer1 gate single pulse acquisition has completed or has not been started This bit is automatically cleared when T1GSPM is cleared. T1GVAL: Timer1 Gate Current State bit Indicates the current state of the Timer1 gate that could be provided to TMR1H:TMR1L; unaffected by Timer1 Gate Enable (TMR1GE) bit. T1GSS: Timer1 Gate Source Select bits 00 = Timer1 gate pin 01 = TMR2 to match PR2 output 10 = Comparator 1 output 11 = Comparator 2 output Programming the T1GCON prior to T1CON is recommended. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: DS39974A-page 210 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 13.2 Timer1 Operation 13.3.2 EXTERNAL CLOCK SOURCE The Timer1 module is an 8-bit or 16-bit incrementing counter, which is accessed through the TMR1H:TMR1L register pair. When used with an internal clock source, the module is a timer and increments on every instruction cycle. When used with an external clock source, the module can be used as either a timer or counter and increments on every selected edge of the external source. Timer1 is enabled by configuring the TMR1ON and TMR1GE bits in the T1CON and T1GCON registers, respectively. When Timer1 is enabled, the RC1/CCP8/T1OSI/RP12 and RC0/T1OSO/T1CKI/RP11 pins become inputs. This means the values of TRISC are ignored and the pins are read as ‘0’. When the external clock source is selected, the Timer1 module may work as a timer or a counter. When enabled to count, Timer1 is incremented on the rising edge of the external clock input, T1CKI, or the capacitive sensing oscillator signal. Either of these external clock sources can be synchronized to the microcontroller system clock or they can run asynchronously. When used as a timer with a clock oscillator, an external 32.768 kHz crystal can be used in conjunction with the dedicated internal oscillator circuit. Note: In Counter mode, a falling edge must be registered by the counter prior to the first incrementing rising edge after any one or more of the following conditions: • Timer1 enabled after POR Reset • Write to TMR1H or TMR1L • Timer1 is disabled • Timer1 is disabled (TMR1ON = 0) when T1CKI is high, then Timer1 is enabled (TMR1ON = 1) when T1CKI is low. 13.3 Clock Source Selection The TMR1CS and T1OSCEN bits of the T1CON register are used to select the clock source for Timer1. Register 13-1 displays the clock source selections. 13.3.1 INTERNAL CLOCK SOURCE When the internal clock source is selected, the TMR1H:TMR1L register pair will increment on multiples of FOSC as determined by the Timer1 prescaler. TABLE 13-1: TMR1CS1 0 0 1 1 TIMER1 CLOCK SOURCE SELECTION TMR1CS0 1 0 0 0 T1OSCEN x x 0 1 Clock Source Clock Source (FOSC) Instruction Clock (FOSC/4) External Clock on T1CKI Pin Oscillator Circuit on T1OSI/T1OSO Pin  2010 Microchip Technology Inc. Preliminary DS39974A-page 211 PIC18F47J13 FAMILY FIGURE 13-1: T1GSS T1G From Timer2 Match PR2 Comparator 1 Output Comparator 2 Output T1GSPM T1G_IN 10 11 D TMR1ON T1GPOL Set Flag bit TMR1IF on Overflow T1GTM TMR1GE TMR1ON TMR1(2) TMR1H TMR1L Q EN D T1CLK 0 Synchronized Clock Input CK R Q Q 0 Single Pulse 1 Acq. Control T1GGO/T1DONE 1 0 T1GVAL Q1 D EN Interrupt det Q RD T1GCON Set TMR1GIF Data Bus TIMER1 BLOCK DIAGRAM 00 01 1 TMR1CS T1OSO/T1CKI OUT T1OSC T1OSI SOSCGO T1OSCEN T3OSCEN T5OSCEN EN 0 T1OSCEN (1) T1SYNC Prescaler 1, 2, 4, 8 10 Synchronize(3) det 1 FOSC Internal Clock FOSC/4 Internal Clock 01 2 T1CKPS FOSC/2 Internal Clock Sleep Input 00 T1CKI Note 1: 2: 3: ST buffer is high-speed type when using T1CKI. Timer1 register increments on the rising edge. Synchronization does not operate while in Sleep. DS39974A-page 212 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 13.4 Timer1 16-Bit Read/Write Mode TABLE 13-2: Timer1 can be configured for 16-bit reads and writes. When the RD16 control bit (T1CON) is set, the address for TMR1H is mapped to a buffer register for the high byte of Timer1. A read from TMR1L loads the contents of the high byte of Timer1 into the Timer1 High Byte Buffer register. This provides the user with the ability to accurately read all 16 bits of Timer1 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer1 must also take place through the TMR1H Buffer register. The Timer1 high byte is updated with the contents of TMR1H when a write occurs to TMR1L. This allows a user to write all 16 bits to both the high and low bytes of Timer1 at once. The high byte of Timer1 is not directly readable or writable in this mode. All reads and writes must take place through the Timer1 High Byte Buffer register. Writes to TMR1H do not clear the Timer1 prescaler. The prescaler is only cleared on writes to TMR1L. CAPACITOR SELECTION FOR THE TIMER OSCILLATOR(2,3,4,5) Freq. 32 kHz C1 12 pF(1) C2 12 pF(1) Oscillator Type LP Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit. 2: Higher capacitance increases the stability of the oscillator but also increases the start-up time. 3: Since each resonator/crystal has its own characteristics, the user should consult the resonator/crystal manufacturer for appropriate values of external components. 4: Capacitor values are for design guidance only. Values listed would be typical of a CL = 10 pF rated crystal when SOSCSEL = 0b11. 5: Incorrect capacitance value may result in a frequency not meeting the crystal manufacturer’s tolerance specification. The Timer1 crystal oscillator drive level is determined based on the SOSCSEL (CONFIG2L) Configuration bit. The Higher Drive Level mode, SOSCSEL = 0b11, is intended to drive a wide variety of 32.768 kHz crystals with a variety of load capacitance (CL) ratings. The Lower Drive Level mode is highly optimized for extremely low-power consumption. It is not intended to drive all types of 32.768 kHz crystals. In the Low Drive Level mode, the crystal oscillator circuit may not work correctly if excessively large discrete capacitors are placed on the T1OSI and T1OSO pins. This mode is only designed to work with discrete capacitances of approximately 3 pF-10 pF on each pin. Crystal manufacturers usually specify a CL (load capacitance) rating for their crystals. This value is related to, but not necessarily the same as, the values that should be used for C1 and C2 in Figure 13-2. See the crystal manufacturer’s applications information for more details on how to select the optimum C1 and C2 for a given crystal. The optimum value depends in part on the amount of parasitic capacitance in the circuit, which is often unknown. Therefore, after values have been selected, it is highly recommended that thorough testing and validation of the oscillator be performed. 13.5 Timer1 Oscillator An on-chip crystal oscillator circuit is incorporated between pins, T1OSI (input) and T1OSO (amplifier output). It is enabled by setting the Timer1 Oscillator Enable bit, T1OSCEN (T1CON). The oscillator is a low-power circuit rated for 32 kHz crystals. It will continue to run during all power-managed modes. The circuit for a typical LP oscillator is depicted in Figure 13-2. Table 13-2 provides the capacitor selection for the Timer1 oscillator. The user must provide a software time delay to ensure proper start-up of the Timer1 oscillator. FIGURE 13-2: EXTERNAL COMPONENTS FOR THE TIMER1 LP OSCILLATOR PIC18F47J13 T1OSI XTAL 32.768 kHz T1OSO C1 12 pF C2 12 pF Note: See the Notes with Table 13-2 for additional information about capacitor selection.  2010 Microchip Technology Inc. Preliminary DS39974A-page 213 PIC18F47J13 FAMILY 13.5.1 USING TIMER1 AS A CLOCK SOURCE FIGURE 13-3: The Timer1 oscillator is also available as a clock source in power-managed modes. By setting the clock select bits, SCS (OSCCON), to ‘01’, the device switches to SEC_RUN mode. Both the CPU and peripherals are clocked from the Timer1 oscillator. If the IDLEN bit (OSCCON) is cleared and a SLEEP instruction is executed, the device enters SEC_IDLE mode. Additional details are available in Section 4.0 “Low-Power Modes”. Whenever the Timer1 oscillator is providing the clock source, the Timer1 system clock status flag, SOSCRUN (OSCCON2), is set. This can be used to determine the controller’s current clocking mode. It can also indicate the clock source currently being used by the Fail-Safe Clock Monitor. If the Clock Monitor is enabled and the Timer1 oscillator fails while providing the clock, polling the SOSCRUN bit will indicate whether the clock is being provided by the Timer1 oscillator or another source. OSCILLATOR CIRCUIT WITH GROUNDED GUARD RING VDD VSS OSC1 OSC2 RC0 RC1 RC2 Note: Not drawn to scale. 13.5.2 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. This is especially true when the oscillator is configured for extremely Low-Power mode (SOSCSEL = 0b01). The oscillator circuit, displayed in Figure 13-2, should be located as close as possible to the microcontroller. There should be no circuits passing within the oscillator circuit boundaries other than VSS or VDD. If a high-speed circuit must be located near the oscillator (such as the ECCP1 pin in Output Compare or PWM mode, or the primary oscillator using the OSC2 pin), a grounded guard ring around the oscillator circuit, as displayed in Figure 13-3, may be helpful when used on a single-sided PCB or in addition to a ground plane. In the Low Drive Level mode, SOSCSEL = 0b01, it is critical that the RC2 I/O pin signals be kept away from the oscillator circuit. Configuring RC2 as a digital output, and toggling it, can potentially disturb the oscillator circuit, even with relatively good PCB layout. If possible, it is recommended to either leave RC2 unused, or use it as an input pin with a slew rate limited signal source. If RC2 must be used as a digital output, it may be necessary to use the Higher Drive Level Oscillator mode (SOSCSEL = 0b11) with many PCB layouts. Even in the High Drive Level mode, careful layout procedures should still be followed when designing the oscillator circuit. In addition to dV/dt induced noise considerations, it is also important to ensure that the circuit board is clean. Even a very small amount of conductive soldering flux residue can cause PCB leakage currents which can overwhelm the oscillator circuit. 13.6 Timer1 Interrupt The TMR1 register pair (TMR1H:TMR1L) increments from 0000h to FFFFh and rolls over to 0000h. The Timer1 interrupt, if enabled, is generated on overflow which is latched in interrupt flag bit, TMR1IF (PIR1). This interrupt can be enabled or disabled by setting or clearing the Timer1 Interrupt Enable bit, TMR1IE (PIE1). DS39974A-page 214 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 13.7 Resetting Timer1 Using the ECCP Special Event Trigger 13.8 Timer1 Gate The Timer1 can be configured to count freely or the count can be enabled and disabled using the Timer1 gate circuitry. This is also referred to as Timer1 gate count enable. The Timer1 gate can also be driven by multiple selectable sources. If ECCP1 or ECCP2 is configured to use Timer1 and to generate a Special Event Trigger in Compare mode (CCPxM = 1011), this signal will reset Timer3. The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled (see Section 19.3.4 “Special Event Trigger” for more information). The module must be configured as either a timer or a synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a period register for Timer1. If Timer1 is running in Asynchronous Counter mode, this Reset operation may not work. In the event that a write to Timer1 coincides with a Special Event Trigger, the write operation will take precedence. Note: The Special Event Trigger from the ECCPx module will not set the TMR1IF interrupt flag bit (PIR1). 13.8.1 TIMER1 GATE COUNT ENABLE The Timer1 Gate Enable mode is enabled by setting the TMR1GE bit of the T1GCON register. The polarity of the Timer1 Gate Enable mode is configured using the T1GPOL bit of the T1GCON register. When Timer1 Gate Enable mode is enabled, Timer1 will increment on the rising edge of the Timer1 clock source. When Timer1 Gate Enable mode is disabled, no incrementing will occur and Timer1 will hold the current count. See Figure 13-4 for timing details. TABLE 13-3: T1CLK     TIMER1 GATE ENABLE SELECTIONS T1G 0 1 0 1 Timer1 Operation Counts Holds Count Holds Count Counts T1GPOL 0 0 1 1 FIGURE 13-4: TMR1GE T1GPOL T1G_IN TIMER1 GATE COUNT ENABLE MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4  2010 Microchip Technology Inc. Preliminary DS39974A-page 215 PIC18F47J13 FAMILY 13.8.2 TIMER1 GATE SOURCE SELECTION The Timer1 gate source can be selected from one of four different sources. Source selection is controlled by the T1GSSx bits of the T1GCON register. The polarity for each available source is also selectable. Polarity selection is controlled by the T1GPOL bit of the T1GCON register. occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer1 gate circuitry. The pulse remains high for one instruction cycle and returns to low until the next match. When T1GPOL = 1, Timer1 increments for a single instruction cycle following TMR2 matching PR2. With T1GPOL = 0, Timer1 increments except during the cycle following the match. TABLE 13-4: T1GSS 00 01 10 11 TIMER1 GATE SOURCES Timer1 Gate Source Timer1 Gate Pin TMR2 matches PR2 Comparator 1 output Comparator 2 output 13.8.3 TIMER1 GATE TOGGLE MODE When Timer1 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer1 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. See Figure 13-5 for timing details. The T1GVAL bit will indicate when the Toggled mode is active and the timer is counting. The Timer1 Gate Toggle mode is enabled by setting the T1GTM bit of the T1GCON register. When the T1GTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. 13.8.2.1 T1G Pin Gate Operation The T1G pin is one source for Timer1 gate control. It can be used to supply an external source to the Timer1 gate circuitry. 13.8.2.2 Timer2 Match Gate Operation The TMR2 register will increment until it matches the value in the PR2 register. On the very next increment cycle, TMR2 will be reset to 00h. When this Reset FIGURE 13-5: TMR1GE T1GPOL TIMER1 GATE TOGGLE MODE T1GTM T1G_IN T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8 DS39974A-page 216 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 13.8.4 TIMER1 GATE SINGLE PULSE MODE When Timer1 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer1 Gate Single Pulse mode is first enabled by setting the T1GSPM bit in the T1GCON register. Next, the T1GGO/T1DONE bit in the T1GCON register must be set. The Timer1 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the T1GGO/T1DONE bit will automatically be cleared. No other gate events will be allowed to increment Timer1 until the T1GGO/T1DONE bit is once again set in software. Clearing the T1GSPM bit of the T1GCON register will also clear the T1GGO/T1DONE bit. See Figure 13-6 for timing details. Enabling the Toggle mode and the Single Pulse mode, simultaneously, will permit both sections to work together. This allows the cycle times on the Timer1 gate source to be measured. See Figure 13-7 for timing details. 13.8.5 TIMER1 GATE VALUE STATUS When the Timer1 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the T1GVAL bit in the T1GCON register. The T1GVAL bit is valid even when the Timer1 gate is not enabled (TMR1GE bit is cleared). FIGURE 13-6: TIMER1 GATE SINGLE PULSE MODE TMR1GE T1GPOL T1GSPM T1GGO/ T1DONE T1G_IN Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL T1CKI T1GVAL Timer1 N N+1 N+2 Set by Hardware on Falling Edge of T1GVAL Cleared by Software TMR1GIF Cleared by Software  2010 Microchip Technology Inc. Preliminary DS39974A-page 217 PIC18F47J13 FAMILY FIGURE 13-7: TMR1GE T1GPOL T1GSPM T1GTM T1GGO/ T1DONE T1G_IN Set by Software Counting Enabled on Rising Edge of T1G Cleared by Hardware on Falling Edge of T1GVAL TIMER1 GATE SINGLE PULSE AND TOGGLE COMBINED MODE T1CKI T1GVAL Timer1 N N+1 N+2 N+3 N+4 Cleared by Software TMR1GIF Cleared by Software Set by Hardware on Falling Edge of T1GVAL TABLE 13-5: Name INTCON PIR1 PIE1 IPR1 TMR1L TMR1H T1CON T1GCON OSCCON2 REGISTERS ASSOCIATED WITH TIMER1 AS A TIMER/COUNTER Bit 7 Bit 6 PEIE/GIEL ADIF ADIE ADIP Bit 5 TMR0IE RC1IF RC1IE RC1IP Bit 4 INT0IE TX1IF TX1IE TX1IP Bit 3 RBIE SSP1IF SSP1IE SSP1IP Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP Bit 1 INT0IF TMR2IF TMR2IE TMR2IP Bit 0 RBIF TMR1IF TMR1IE TMR1IP GIE/GIEH PMPIF(1) PMPIE(1) PMPIP(1) Timer1 Register Low Byte Timer1 Register High Byte TMR1CS1 TMR1GE — TMR1CS0 T1GPOL SOSCRUN T1CKPS1 T1GTM — T1CKPS0 T1GSPM SOSCDRV T1OSCEN T1GGO/ T1DONE SOSCGO T1SYNC T1GVAL — RD16 T1GSS1 — TMR1ON T1GSS0 — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module. Note 1: These bits are only available in 44-pin devices. DS39974A-page 218 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 14.0 TIMER2 MODULE 14.1 Timer2 Operation The Timer2 module incorporates the following features: • 8-bit Timer and Period registers (TMR2 and PR2, respectively) • Readable and writable (both registers) • Software programmable prescaler (1:1, 1:4 and 1:16) • Software programmable postscaler (1:1 through 1:16) • Interrupt on TMR2 to PR2 match • Optional use as the shift clock for the MSSP modules The module is controlled through the T2CON register (Register 14-1) which enables or disables the timer and configures the prescaler and postscaler. Timer2 can be shut off by clearing control bit, TMR2ON (T2CON), to minimize power consumption. A simplified block diagram of the module is shown in Figure 14-1. In normal operation, TMR2 is incremented from 00h on each clock (FOSC/4). A 4-bit counter/prescaler on the clock input gives direct input, divide-by-4 and divide-by-16 prescale options. These are selected by the prescaler control bits, T2CKPS (T2CON). The value of TMR2 is compared to that of the Period register, PR2, on each clock cycle. When the two values match, the comparator generates a match signal as the timer output. This signal also resets the value of TMR2 to 00h on the next cycle and drives the output counter/postscaler (see Section 14.2 “Timer2 Interrupt”). The TMR2 and PR2 registers are both directly readable and writable. The TMR2 register is cleared on any device Reset, while the PR2 register initializes at FFh. Both the prescaler and postscaler counters are cleared on the following events: • a write to the TMR2 register • a write to the T2CON register • any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) TMR2 is not cleared when T2CON is written. REGISTER 14-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 T2CON: TIMER2 CONTROL REGISTER (ACCESS FCAh) R/W-0 T2OUTPS2 R/W-0 T2OUTPS1 R/W-0 T2OUTPS0 R/W-0 TMR2ON R/W-0 T2CKPS1 R/W-0 T2CKPS0 bit 0 R/W-0 T2OUTPS3 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ T2OUTPS: Timer2 Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale TMR2ON: Timer2 On bit 1 = Timer2 is on 0 = Timer2 is off T2CKPS: Timer2 Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 10 = Prescaler is 16 bit 2 bit 1-0  2010 Microchip Technology Inc. Preliminary DS39974A-page 219 PIC18F47J13 FAMILY 14.2 Timer2 Interrupt 14.3 Timer2 Output Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) provides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 Match Interrupt Flag, which is latched in TMR2IF (PIR1). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1). A range of 16 postscaler options (from 1:1 through 1:16 inclusive) can be selected with the postscaler control bits, T2OUTPS (T2CON). The unscaled output of TMR2 is available primarily to the ECCP modules, where it is used as a time base for operations in PWM mode. Timer2 can be optionally used as the shift clock source for the MSSP modules operating in SPI mode. Additional information is provided in Section 20.0 “Master Synchronous Serial Port (MSSP) Module”. FIGURE 14-1: TIMER2 BLOCK DIAGRAM 4 1:1 to 1:16 Postscaler T2OUTPS T2CKPS 2 Set TMR2IF TMR2 Output (to PWM or MSSPx) FOSC/4 1:1, 1:4, 1:16 Prescaler Reset TMR2 8 TMR2/PR2 Match Comparator PR2 8 8 Internal Data Bus TABLE 14-1: Name INTCON PIR1 PIE1 IPR1 TMR2 T2CON PR2 REGISTERS ASSOCIATED WITH TIMER2 AS A TIMER/COUNTER Bit 7 Bit 6 PEIE/GIEL ADIF ADIE ADIP Bit 5 TMR0IE RC1IF RC1IE RC1IP Bit 4 INT0IE TX1IF TX1IE TX1IP Bit 3 RBIE SSP1IF SSP1IE SSP1IP T2OUTPS0 Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP TMR2ON Bit 1 INT0IF TMR2IF TMR2IE TMR2IP T2CKPS1 Bit 0 RBIF TMR1IF TMR1IE TMR1IP T2CKPS0 GIE/GIEH PMPIF(1) PMPIE(1) PMPIP(1) Timer2 Register — T2OUTPS3 T2OUTPS2 T2OUTPS1 Timer2 Period Register Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer2 module. Note 1: These bits are only available in 44-pin devices. DS39974A-page 220 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 15.0 TIMER3/5 MODULE The Timer3/5 timer/counter modules incorporate these features: • Software selectable operation as a 16-bit timer or counter • Readable and writable 8-bit registers (TMRxH and TMRxL) • Selectable clock source (internal or external) with device clock or Timer1 oscillator internal options • Interrupt-on-overflow • Module Reset on ECCP Special Event Trigger Note: Throughout this section, generic references are used for register and bit names that are the same – except for an ‘x’ variable that indicates the item’s association with the Timer3 or Timer5 module. For example, the control register is named TxCON, and refers to T3CON and T5CON. A simplified block diagram of the Timer3/5 module is shown in Figure 15-1. The Timer3/5 module is controlled through the TxCON register (Register 15-1). It also selects the clock source options for the ECCP modules. (For more information, see Section 19.1.1 “ECCP Module and Timer Resources”.) The FOSC clock source should not be used with the ECCP capture/compare features. If the timer will be used with the capture or compare features, always select one of the other timer clocking options.  2010 Microchip Technology Inc. Preliminary DS39974A-page 221 PIC18F47J13 FAMILY REGISTER 15-1: R/W-0 TMRxCS1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TxCON: TIMER3/5 CONTROL REGISTER (ACCESS F79h, BANKED F22h) R/W-0 TxCKPS1 R/W-0 TxCKPS0 R/W-0 TxOSCEN R/W-0 TxSYNC R/W-0 RD16 R/W-0 TMRxON bit 0 R/W-0 TMRxCS0 TMRxCS: Clock Source Select bits 10 = Clock source is the pin or TxCKI input pin 01 = Clock source is the system clock (FOSC)(1) 00 = Clock source is the instruction clock (FOSC/4) TxCKPS: Timerx Input Clock Prescale Select bits 11 = 1:8 Prescale value 10 = 1:4 Prescale value 01 = 1:2 Prescale value 00 = 1:1 Prescale value TxOSCEN: Timer Oscillator Enable bit 1 = T1OSC/SOSC oscillator used as clock source 0 = TxCKI digital input pin used as clock source TxSYNC: External Clock Input Synchronization Control bit (Not usable if the device clock comes from Timer1/Timer3.) When TMRxCS1:TMRxCS0 = 10: 1 = Do not synchronize external clock input 0 = Synchronize external clock input When TMRxCS1:TMRxCS0 = 0x: This bit is ignored; Timer3 uses the internal clock. RD16: 16-Bit Read/Write Mode Enable bit 1 = Enables register read/write of timer in one 16-bit operation 0 = Enables register read/write of timer in two eight-bit operations TMRxON: Timer On bit 1 = Enables Timer 0 = Stops Timer The FOSC clock source should not be selected if the timer will be used with the ECCP capture/compare features. bit 5-4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39974A-page 222 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 15.1 Timer3/5 Gate Control Register The Timer3/5 Gate Control register (TxGCON), provided in Register 14-2, is used to control the Timerx gate. REGISTER 15-2: R/W-0 TMRxGE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 TxGCON: TIMER3/5 GATE CONTROL REGISTER(1) (ACCESS F97h, BANKED F21h) R/W-0 TxGTM R/W-0 TxGSPM R/W-0 TxGGO/TxDONE R-x TxGVAL R/W-0 TxGSS1 R/W-0 TxGSS0 bit 0 R/W-0 TxGPOL W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TMRxGE: Timer Gate Enable bit If TMRxON = 0: This bit is ignored. If TMRxON = 1: 1 = Timer counting is controlled by the Timerx gate function 0 = Timer counts regardless of the Timerx gate function TxGPOL: Gate Polarity bit 1 = Timer gate is active-high (Timerx counts when the gate is high) 0 = Timer gate is active-low (Timerx counts when the gate is low) TxGTM: Gate Toggle Mode bit 1 = Timer Gate Toggle mode is enabled. 0 = Timer Gate Toggle mode is disabled and toggle flip-flop is cleared Timerx gate flip-flop toggles on every rising edge. TxGSPM: Timer Gate Single Pulse Mode bit 1 = Timer Gate Single Pulse mode is enabled and is controlling Timerx gate 0 = Timer Gate Single Pulse mode is disabled TxGGO/TxDONE: Timer Gate Single Pulse Acquisition Status bit 1 = Timer gate single pulse acquisition is ready, waiting for an edge 0 = Timer gate single pulse acquisition has completed or has not been started This bit is automatically cleared when TxGSPM is cleared. TxGVAL: Timer Gate Current State bit Indicates the current state of the Timer gate that could be provided to TMRxH:TMRxL. Unaffected by the Timer Gate Enable bit (TMRxGE). TxGSS: Timer Gate Source Select bits 11 = Comparator 2 output 10 = Comparator 1 output 01 = TMR4/6 to match PR4/6 output 00 = T3G/T5G gate input pin Programming the TxGCON prior to TxCON is recommended. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 223 PIC18F47J13 FAMILY REGISTER 15-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown OSCCON2: OSCILLATOR CONTROL REGISTER 2 (ACCESS F87h) R-0(2) U-0 — R/W-1 R/W-0(2) R/W-1 PRISD U-0 — U-0 — bit 0 SOSCDRV SOSCGO(3) SOSCRUN Unimplemented: Read as ‘0’ SOSCRUN: SOSC Run Status bit 1 = System clock comes from secondary SOSC 0 = System clock comes from an oscillator other than SOSC Unimplemented: Read as ‘0’ SOSCDRV: SOSC Drive Control bit 1 = T1OSC/SOSC oscillator drive circuit is selected by Configuration bits, CONFIG2L 0 = Low-power T1OSC/SOSC circuit is selected SOSCGO: Oscillator Start Control bit 1 = Turns on the oscillator, even if no peripherals are requesting it 0 = Oscillator is shut off unless peripherals are requesting it PRISD: Primary Oscillator Drive Circuit Shutdown bit 1 = Oscillator drive circuit is on 0 = Oscillator drive circuit is off (zero power) Unimplemented: Read as ‘0’ Reset value is ‘0’ when Two-Speed Start-up is enabled and ‘1’ if disabled. Default output frequency of INTOSC on Reset (4 MHz). When the SOSC is selected to run from a digital clock input, rather than an external crystal, this bit has no effect. bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3: DS39974A-page 224 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 15.2 • • • • Timer3/5 Operation Timer3 and Timer5 can operate in these modes: Timer Synchronous Counter Asynchronous Counter Timer with Gated Control The operating mode is determined by the clock select bits, TMRxCSx (TxCON). When the TMRxCSx bits are cleared (= 00), Timer3/5 increments on every internal instruction cycle (FOSC/4). When TMRxCSx = 01, the Timer3/5 clock source is the system clock (FOSC), and when it is ‘10’, Timer3/5 works as a counter from the external clock from the TxCKI pin (on the rising edge after the first falling edge) or the Timer1 oscillator. FIGURE 15-1: TxGSS TxG From Timer4/6 Match PR4/6 Comparator 1 Output Comparator 2 Output TIMER3/5 BLOCK DIAGRAM 00 01 10 D 11 TMRxON TxGPOL Set Flag bit TMRxIF on Overflow TxGTM CK R Q Q 1 TxG_IN 0 TxGSPM 0 TxGVAL Single Pulse Acq. Control TxGGO/TxDONE 1 Q1 D EN Interrupt det TMRxGE TMRxON TMRx(2) TMRxH TMRxL Q EN D TxCLK 0 Synchronized Clock Input Q Data Bus RD T3GCON Set TMRxGIF 1 TMRxCS T1OSO/T1CKI OUT T1OSC/SOSC 1 T1OSI SOSCGO T1OSCEN T3OSCEN T5OSCEN EN 0 TXOSCEN (1) TxSYNC Prescaler 1, 2, 4, 8 10 2 TxCKPS 01 FOSC/2 Internal Clock Sleep Input Synchronize(3) det FOSC Internal Clock FOSC/4 Internal Clock 00 TxCKI Note 1: 2: 3: ST buffer is a high-speed type when using T1CKI. Timerx registers increment on rising edge. Synchronization does not operate while in Sleep.  2010 Microchip Technology Inc. Preliminary DS39974A-page 225 PIC18F47J13 FAMILY 15.3 Timer3/5 16-Bit Read/Write Mode 15.5 Timer3/5 Gates Timer3/5 can be configured for 16-bit reads and writes (see Figure 15.3). When the RD16 control bit (TxCON) is set, the address for TMRxH is mapped to a buffer register for the high byte of Timer3/5. A read from TMRxL will load the contents of the high byte of Timer3/5 into the Timerx High Byte Buffer register. This provides users with the ability to accurately read all 16 bits of Timer3/5 without having to determine whether a read of the high byte, followed by a read of the low byte, has become invalid due to a rollover between reads. A write to the high byte of Timer3/5 must also take place through the TMRxH Buffer register. The Timer3/5 high byte is updated with the contents of TMRxH when a write occurs to TMRxL. This allows users to write all 16 bits to both the high and low bytes of Timer3/5 at once. The high byte of Timer3/5 is not directly readable or writable in this mode. All reads and writes must take place through the Timerx High Byte Buffer register. Writes to TMRxH do not clear the Timer3/5 prescaler. The prescaler is only cleared on writes to TMRxL. Timer3/5 can be configured to count freely or the count can be enabled and disabled using the Timer3/5 gate circuitry. This is also referred to as the Timer3/5 gate count enable. The Timer3/5 gate can also be driven by multiple selectable sources. 15.5.1 TIMER3/5 GATE COUNT ENABLE The Timerx Gate Enable mode is enabled by setting the TMRxGE bit (TxGCON). The polarity of the Timerx Gate Enable mode is configured using the TxGPOL bit (TxGCON). When Timerx Gate Enable mode is enabled, Timer3/5 will increment on the rising edge of the Timer3/5 clock source. When Timerx Gate Enable mode is disabled, no incrementing will occur and Timer3/5 will hold the current count. See Figure 15-2 for timing details. TABLE 15-1: TxCLK(†)     TIMER3/5 GATE ENABLE SELECTIONS TxG Pin 0 1 0 1 Timerx Operation Counts Holds Count Holds Count Counts 15.4 Using the Timer1 Oscillator as the Timer3/5 Clock Source TxGPOL (TxGCON) 0 0 1 1 The Timer1 internal oscillator may be used as the clock source for Timer3/5. The Timer1 oscillator is enabled by setting the T1OSCEN (T1CON) bit. To use it as the Timer3/5 clock source, the TMRxCS bits must also be set. As previously noted, this also configures Timer3/5 to increment on every rising edge of the oscillator source. The Timer1 oscillator is described in Section 13.0 “Timer1 Module”. † The clock on which TMR3/5 is running. For more information, see TxCLK in Figure 15-1. FIGURE 15-2: TMRxGE TIMER3/5 GATE COUNT ENABLE MODE TxGPOL TxG_IN TxCKI TxGVAL Timer3/5 N N+1 N+2 N+3 N+4 DS39974A-page 226 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 15.5.2 TIMER3/5 GATE SOURCE SELECTION 15.5.2.2 Timer4/6 Match Gate Operation The Timer3/5 gate source can be selected from one of four different sources. Source selection is controlled by the TxGSS bits (TxGCON). The polarity for each available source is also selectable and is controlled by the TxGPOL bit (TxGCON). The TMR4/6 register will increment until it matches the value in the PR4/6 register. On the very next increment cycle, TMR4/6 will be reset to 00h. When this Reset occurs, a low-to-high pulse will automatically be generated and internally supplied to the Timer3/5 gate circuitry. TABLE 15-2: TxGSS 00 01 10 11 TIMER3/5 GATE SOURCES Timerx Gate Source TxG timer gate pin TMR4/6 matches PR4/6 Comparator 1 output Comparator 2 output 15.5.3 TIMER3/5 GATE-TOGGLE MODE When Timer3/5 Gate Toggle mode is enabled, it is possible to measure the full cycle length of a Timer3/5 gate signal, as opposed to the duration of a single level pulse. The Timer1 gate source is routed through a flip-flop that changes state on every incrementing edge of the signal. (For timing details, see Figure 15-3.) The TxGVAL bit will indicate when the Toggled mode is active and the timer is counting. Timer3/5 Gate Toggle mode is enabled by setting the TxGTM bit (TxGCON). When the TxGTM bit is cleared, the flip-flop is cleared and held clear. This is necessary in order to control which edge is measured. 15.5.2.1 TxG Pin Gate Operation The TxG pin is one source for Timer3/5 gate control. It can be used to supply an external source to the gate circuitry. FIGURE 15-3: TMRxGE TxGPOL TIMER3/5 GATE TOGGLE MODE TxGTM TxG_IN TxCKI TxGVAL Timer3/5 N N+1 N+2 N+3 N+4 N+5 N+6 N+7 N+8  2010 Microchip Technology Inc. Preliminary DS39974A-page 227 PIC18F47J13 FAMILY 15.5.4 TIMER3/5 GATE SINGLE PULSE MODE When Timer3/5 Gate Single Pulse mode is enabled, it is possible to capture a single pulse gate event. Timer3/5 Gate Single Pulse mode is first enabled by setting the TxGSPM bit (TxGCON). Next, the TxGGO/TxDONE bit (TxGCON) must be set. The Timer3/5 will be fully enabled on the next incrementing edge. On the next trailing edge of the pulse, the TxGGO/TxDONE bit will automatically be cleared. No other gate events will be allowed to increment Timer3/5 until the TxGGO/TxDONE bit is once again set in software. Clearing the TxGSPM bit TxGGO/TxDONE bit. (For Figure 15-4.) will also clear the timing details, see Simultaneously, enabling the Toggle mode and the Single Pulse mode will permit both sections to work together. This allows the cycle times on the Timer3/5 gate source to be measured. (For timing details, see Figure 15-5.) FIGURE 15-4: TMRxGE TIMER3/5 GATE SINGLE PULSE MODE TxGPOL TxGSPM Cleared by Hardware on Falling Edge of TxGVAL TxGGO/ TxDONE Set by Software Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5 N N+1 N+2 TMRxGIF Cleared by Software Set by Hardware on Falling Edge of TxGVAL Cleared by Software DS39974A-page 228 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 15-5: TMRxGE TIMER3/5 GATE SINGLE PULSE AND TOGGLE COMBINED MODE TxGPOL TxGSPM TxGTM Cleared by Hardware on Falling Edge of TxGVAL TxGGO/ TxDONE Set by Software Counting Enabled on Rising Edge of TxG TxG_IN TxCKI TxGVAL Timer3/5 N N+1 N+2 N+3 N+4 TMRxGIF Cleared by Software Set by Hardware on Falling Edge of TxGVAL Cleared by Software 15.5.5 TIMER3/5 GATE VALUE STATUS 15.5.6 When Timer3/5 gate value status is utilized, it is possible to read the most current level of the gate control value. The value is stored in the TxGVAL bit (TxGCON). The TxGVAL bit is valid even when the Timer3/5 gate is not enabled (TMRxGE bit is cleared). TIMER3/5 GATE EVENT INTERRUPT When the Timer3/5 gate event interrupt is enabled, it is possible to generate an interrupt upon the completion of a gate event. When the falling edge of TxGVAL occurs, the TMRxGIF flag bit in the PIRx register will be set. If the TMRxGIE bit in the PIEx register is set, then an interrupt will be recognized. The TMRxGIF flag bit operates even when the Timer3/5 gate is not enabled (TMRxGE bit is cleared).  2010 Microchip Technology Inc. Preliminary DS39974A-page 229 PIC18F47J13 FAMILY 15.6 Timer3/5 Interrupt 15.7 The TMRx register pair (TMRxH:TMRxL) increments from 0000h to FFFFh and overflows to 0000h. The Timerx interrupt, if enabled, is generated on overflow and is latched in the interrupt flag bit, TMRxIF. Table 15-3 gives each module’s flag bit. Resetting Timer3/5 Using the ECCP Special Event Trigger TABLE 15-3: Timer Module 3 5 TIMER3/5 INTERRUPT FLAG BITS Flag Bit PIR2 PIR5 If the ECCP modules are configured to use Timerx and to generate a Special Event Trigger in Compare mode (CCPxM = 1011), this signal will reset Timerx. The trigger from ECCP2 will also start an A/D conversion if the A/D module is enabled. (For more information, see Section 19.3.4 “Special Event Trigger”.) The module must be configured as either a timer or synchronous counter to take advantage of this feature. When used this way, the CCPRxH:CCPRxL register pair effectively becomes a Period register for TimerX. If Timerx is running in Asynchronous Counter mode, the Reset operation may not work. In the event that a write to Timerx coincides with a Special Event Trigger from an ECCP module, the write will take precedence. Note: The Special Event Triggers from the ECCPx module will only clear the TMR3 register’s content, but not set the TMR3IF interrupt flag bit (PIR1). This interrupt can be enabled or disabled by setting or clearing the TMRxIE bit, respectively. Table 15-4 gives each module’s enable bit. TABLE 15-4: Timer Module 3 5 TIMER3/5 INTERRUPT ENABLE BITS Flag Bit PIE2 PIE5 Note: The CCP and ECCP modules use Timers, 1 through 8, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRSx registers. For more details, see Register 18-3 and Register 19-2. DS39974A-page 230 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 15-5: Name INTCON PIR5 PIE5 PIR2 PIE2 TMR3H TMR3L T3GCON T3CON TMR5H TMR5L T5GCON T5CON OSCCON2 CCPTMRS0 CCPTMRS1 CCPTMRS1 CCPTMRS2 REGISTERS ASSOCIATED WITH TIMER3/5 AS A TIMER/COUNTER Bit 7 GIE/GIEH — — OSCFIF OSCFIE Bit 6 PEIE/GIEL — — CM2IF CM2IE Bit 5 TMR0IE CM3IF CM3IE CM1IF CM1IE Bit 4 INT0IE TMR8IF TMR8IE — — Bit 3 RBIE TMR6IF TMR6IE BCL1IF BCL1IE Bit 2 TMR0IF TMR5IF TMR5IE HLVDIF HLVDIE Bit 1 INT0IF TMR5GIF TMR5GIE TMR3IF TMR3IE Bit 0 RBIF TMR1GIF TMR1GIE CCP2IF CCP2IE Timer3 Register High Byte Timer3 Register Low Byte TMR3GE TMR3CS1 T3GPOL TMR3CS0 T3GTM T3CKPS1 T3GSPM T3CKPS0 T3GGO/ T3DONE T3OSCEN T3GVAL T3SYNC T3GSS1 RD16 T3GSS0 TMR3ON Timer5 Register High Byte Timer5 Register Low Byte TMR5GE TMR5CS1 — C3TSEL1 C7TSEL1 — — T5GPOL TMR5CS0 SOSCRUN C3TSEL0 C7TSEL0 — — T5GTM T5CKPS1 — C2TSEL2 — — — T5GSPM T5CKPS0 C2TSEL1 C6TSEL0 C10TSEL0 C10TSEL0 T5GGO/ T5DONE T5OSCEN C2TSEL0 — — — T5GVAL T5SYNC — C1TSEL2 C5TSEL0 C9TSEL0 C9TSEL0 T5GSS1 RD16 — C1TSEL1 C4TSEL1 C8TSEL1 C8TSEL1 T5GSS0 TMR5ON — C1TSEL0 C4TSEL0 C8TSEL0 C8TSEL0 SOSCDRV SOSCGO Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module.  2010 Microchip Technology Inc. Preliminary DS39974A-page 231 PIC18F47J13 FAMILY NOTES: DS39974A-page 232 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 16.0 TIMER4/6/8 MODULE The Timer4/6/8 timer modules have the following features: • • • • • • Eight-bit Timer register (TMRx) Eight-bit Period register (PRx) Readable and writable (all registers) Software programmable prescaler (1:1, 1:4, 1:16) Software programmable postscaler (1:1 to 1:16) Interrupt on TMRx match of PRx Note: Throughout this section, generic references are used for register and bit names that are the same – except for an ‘x’ variable that indicates the item’s association with the Timer4, Timer6 or Timer8 module. For example, the control register is named TxCON and refers to T4CON, T6CON and T8CON. The Timer4/6/8 modules have a control register shown in Register 16-1. Timer4/6/8 can be shut off by clearing control bit, TMRxON (TxCON), to minimize power consumption. The prescaler and postscaler selection of Timer4/6/8 is also controlled by this register. Figure 16-1 is a simplified block diagram of the Timer4/6/8 modules. 1:1 to 1:16 inclusive scaling) to generate a TMRx interrupt, latched in the flag bit, TMRxIF. Table 16-1 gives each module’s flag bit. TABLE 16-1: 4 6 8 TIMER4/6/8 FLAG BITS Flag Bit PIR3 PIR5 PIR5 Timer Module The interrupt can be enabled or disabled by setting or clearing the Timerx Interrupt Enable bit (TMRxIE), shown in Table 16-2. TABLE 16-2: TIMER4/6/8 INTERRUPT ENABLE BITS Flag Bit PIE3 PIE5 PIE5 Timer Module 4 6 8 The prescaler and postscaler counters are cleared when any of the following occurs: • A write to the TMRx register • A write to the TxCON register • Any device Reset (Power-on Reset (POR), MCLR Reset, Watchdog Timer Reset (WDTR) or Brown-out Reset (BOR)) A TMRx is not cleared when a TxCON is written. Note: The CCP and ECCP modules use Timers, 1 through 8, for some modes. The assignment of a particular timer to a CCP/ECCP module is determined by the Timer to CCP enable bits in the CCPTMRSx registers. For more details, see Register 18-2, Register 18-3 and Register 19-2. 16.1 Timer4/6/8 Operation Timer4/6/8 can be used as the PWM time base for the PWM mode of the ECCP modules. The TMRx registers are readable and writable, and are cleared on any device Reset. The input clock (FOSC/4) has a prescale option of 1:1, 1:4 or 1:16, selected by control bits, TxCKPS (TxCON). The match output of TMRx goes through a four-bit postscaler (that gives a  2010 Microchip Technology Inc. Preliminary DS39974A-page 233 PIC18F47J13 FAMILY REGISTER 16-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-3 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TxCON: TIMER4/6/8 CONTROL REGISTER (ACCESS F76h, BANKED F1Eh, BANKED F1Bh) R/W-0 TxOUTPS2 R/W-0 TxOUTPS1 R/W-0 TxOUTPS0 R/W-0 TMRxON R/W-0 TxCKPS1 R/W-0 TxCKPS0 bit 0 R/W-0 TxOUTPS3 Unimplemented: Read as ‘0’ TxOUTPS: Timerx Output Postscale Select bits 0000 = 1:1 Postscale 0001 = 1:2 Postscale • • • 1111 = 1:16 Postscale TMRxON: Timerx On bit 1 = Timerx is on 0 = Timerx is off TxCKPS: Timerx Clock Prescale Select bits 00 = Prescaler is 1 01 = Prescaler is 4 1x = Prescaler is 16 bit 2 bit 1-0 16.2 Timer4/6/8 Interrupt 16.3 Output of TMRx The Timer4/6/8 modules have 8-bit Period registers, PRx, that are both readable and writable. Timer4/6/8 increment from 00h until they match PR4/6/8 and then reset to 00h on the next increment cycle. The PRx registers are initialized to FFh upon Reset. The outputs of TMRx (before the postscaler) are used only as a PWM time base for the ECCP modules. They are not used as baud rate clocks for the MSSP modules as is the Timer2 output. FIGURE 16-1: TIMER4 BLOCK DIAGRAM 4 2 1:1 to 1:16 Postscaler TxOUTPS TxCKPS Set TMRxIF TMRx Output (to PWM) FOSC/4 1:1, 1:4, 1:16 Prescaler Reset TMRx 8 TMRx/PRx Match Comparator PRx 8 8 Internal Data Bus DS39974A-page 234 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 16-3: Name INTCON IPR5 PIR5 PIE5 TMR4 T4CON PR4 TMR6 T6CON PR6 TMR8 T8CON PR8 CCPTMRS0 CCPTMRS1 CCPTMRS2 REGISTERS ASSOCIATED WITH TIMER4/6/8 AS A TIMER/COUNTER Bit 7 — — — Bit 6 — — — Bit 5 TMR0IE CM3IP CM3IF CM3IE Bit 4 INT0IE TMR8IP TMR8IF TMR8IE Bit 3 RBIE TMR6IP TMR6IF TMR6IE Bit 2 TMR0IF TMR5IP TMR5IF TMR5IE TMR4ON Bit 1 INT0IF TMR5GIP TMR5GIF TMR5GIE T4CKPS1 Bit 0 RBIF TMR1GIP TMR1GIF TMR1GIE T4CKPS0 GIE/GIEH PEIE/GIEL Timer4 Register — T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 Timer4 Period Register Timer6 Register — T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 TMR6ON T6CKPS1 T6CKPS0 Timer6 Period Register Timer8 Register — C3TSEL1 C7TSEL1 — T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 C3TSEL0 C7TSEL0 — C2TSEL2 — — C2TSEL1 C6TSEL0 C10TSEL0 C2TSEL0 — — TMR8ON C1TSEL2 C5TSEL0 C9TSEL0 T8CKPS1 C1TSEL1 C4TSEL1 C8TSEL1 T8CKPS0 C1TSEL0 C4TSEL0 C8TSEL0 Timer8 Period Register Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer4/6/8 modules.  2010 Microchip Technology Inc. Preliminary DS39974A-page 235 PIC18F47J13 FAMILY NOTES: DS39974A-page 236 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.0 REAL-TIME CLOCK AND CALENDAR (RTCC) The RTCC module is intended for applications where accurate time must be maintained for an extended period with minimum to no intervention from the CPU. The module is optimized for low-power usage in order to provide extended battery life while keeping track of time. The module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. Hours are measured in 24-hour (military time) format. The clock provides a granularity of one second with half second visibility to the user. The key features of the Real-Time Clock and Calendar (RTCC) module are: • • • • • • • • • • • • Time: hours, minutes and seconds 24-hour format (military time) Calendar: weekday, date, month and year Alarm configurable Year range: 2000 to 2099 Leap year correction BCD format for compact firmware Optimized for low-power operation User calibration with auto-adjust Calibration range: 2.64 seconds error per month Requirements: external 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin FIGURE 17-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain 32.768 kHz Input from Timer1 Oscillator Internal RC RTCCFG RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALRMRPT YEAR MTHDY WKDYHR MINSEC Comparator ALMTHDY Compare Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2010 Microchip Technology Inc. Preliminary DS39974A-page 237 PIC18F47J13 FAMILY 17.1 RTCC MODULE REGISTERS Alarm Value Registers • ALRMVALH and ALRMVALL – Can access the following registers: - ALRMMNTH - ALRMDAY - ALRMWD - ALRMHR - ALRMMIN - ALRMSEC Note: The RTCVALH and RTCVALL registers can be accessed through RTCRPT. ALRMVALH and ALRMVALL can be accessed through ALRMPTR. The RTCC module registers are divided into following categories: RTCC Control Registers • • • • • RTCCFG RTCCAL PADCFG1 ALRMCFG ALRMRPT RTCC Value Registers • RTCVALH and RTCVALL – Can access the following registers - YEAR - MONTH - DAY - WEEKDAY - HOUR - MINUTE - SECOND DS39974A-page 238 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.1.1 RTCC CONTROL REGISTERS RTCCFG: RTCC CONFIGURATION REGISTER (BANKED F3Fh)(1) U-0 — R/W-0 RTCWREN R-0 R-0 (3) REGISTER 17-1: R/W-0 RTCEN(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 7 R/W-0 RTCOE R/W-0 RTCPTR1 R/W-0 RTCPTR0 bit 0 RTCSYNC HALFSEC W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as ‘0’ RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled 0 = RTCC clock output disabled RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 00 = Minutes 01 = Weekday 10 = Month 11 = Reserved RTCVAL: 00 = Seconds 01 = Hours 10 = Day 11 = Year The RTCCFG register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: 3:  2010 Microchip Technology Inc. Preliminary DS39974A-page 239 PIC18F47J13 FAMILY REGISTER 17-2: R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RTCCAL: RTCC CALIBRATION REGISTER (BANKED F3Eh) R/W-0 CAL6 R/W-0 CAL5 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 bit 0 CAL: RTCC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every minute . . . 00000001 = Minimum positive adjustment; adds four RTCC clock pulses every minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts four RTCC clock pulses every minute . . . 10000000 = Maximum negative adjustment; subtracts 512 RTCC clock pulses every minute REGISTER 17-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-1 — PADCFG1: PAD CONFIGURATION REGISTER 1 (BANKED F3Ch) U-0 U-0 — U-0 — U-0 — R/W-0 R/W-0 R/W-0 bit 0 RTSECSEL1(1) RTSECSEL0(1) PMPTTL(2) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (pin can be INTRC or T1OSC, depending on the RTCOSC (CONFIG3L) setting) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit(2) 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt input buffers To enable the actual RTCC output, the RTCOE (RTCCFG) bit must be set. Available only on 44-pin devices (PIC18F46J13, PIC18F47J13, PIC18LF46J13 and PIC18LF47J13). For 28-pin devices, the bit is U-0. bit 0 Note 1: 2: DS39974A-page 240 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 17-4: R/W-0 ALRMEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ALRMCFG: ALARM CONFIGURATION REGISTER (ACCESS F47h) R/W-0 CHIME R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ALRMPTR0 bit 0 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0000 0000 and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h AMASK: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every four years) 101x = Reserved – do not use 11xx = Reserved – do not use ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 6 bit 5-2 bit 1-0  2010 Microchip Technology Inc. Preliminary DS39974A-page 241 PIC18F47J13 FAMILY REGISTER 17-5: R/W-0 ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ALRMRPT: ALARM REPEAT COUNTER (ACCESS F46h) R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 R/W-0 ARPT0 bit 0 ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. DS39974A-page 242 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.1.2 RTCVALH AND RTCVALL REGISTER MAPPINGS RESERVED REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 REGISTER 17-6: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ REGISTER 17-7: R/W-x YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-0 YEAR: YEAR VALUE REGISTER(1) R/W-x R/W-x YRTEN1 R/W-x YRTEN0 R/W-x YRONE3 R/W-x YRONE2 R/W-x YRONE1 R/W-x YRONE0 bit 0 YRTEN2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. A write to the YEAR register is only allowed when RTCWREN = 1. Note 1: REGISTER 17-8: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3-0 MONTH: MONTH VALUE REGISTER(1) U-0 — U-0 — R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 243 PIC18F47J13 FAMILY REGISTER 17-9: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DAY: DAY VALUE REGISTER(1) U-0 — R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 17-10: WKDY: WEEKDAY VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 0 Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39974A-page 244 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 17-11: HOURS: HOURS VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0 Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 17-12: MINUTES: MINUTES VALUE REGISTER U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 0 Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 17-13: SECONDS: SECONDS VALUE REGISTER U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x SECONE0 bit 0 Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. Preliminary DS39974A-page 245 PIC18F47J13 FAMILY 17.1.3 ALRMVALH AND ALRMVALL REGISTER MAPPINGS REGISTER 17-14: ALRMMNTH: ALARM MONTH VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 0 Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 17-15: ALRMDAY: ALARM DAY VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39974A-page 246 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 17-16: ALRMWD: ALARM WEEKDAY VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 0 Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 17-17: ALRMHR: ALARM HOURS VALUE REGISTER(1) U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 R/W-x HRONE0 bit 0 Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 247 PIC18F47J13 FAMILY REGISTER 17-18: ALRMMIN: ALARM MINUTES VALUE REGISTER U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 0 Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. REGISTER 17-19: ALRMSEC: ALARM SECONDS VALUE REGISTER U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x SECONE0 bit 0 Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9. DS39974A-page 248 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.1.4 RTCEN BIT WRITE 17.2 17.2.1 Operation REGISTER INTERFACE An attempt to write to the RTCEN bit while RTCWREN = 0 will be ignored. RTCWREN must be set before a write to RTCEN can take place. Like the RTCEN bit, the RTCVALH and RTCVALL registers can only be written to when RTCWREN = 1. A write to these registers, while RTCWREN = 0, will be ignored. The register interface for the RTCC and alarm values is implemented using the Binary Coded Decimal (BCD) format. This simplifies the firmware when using the module, as each of the digits is contained within its own 4-bit value (see Figure 17-2 and Figure 17-3). FIGURE 17-2: TIMER DIGIT FORMAT Year Month Day Day of Week 0-9 0-9 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 1/2 Second Bit (binary format) 0-2 0-9 0-5 0-9 0-5 0-9 0/1 FIGURE 17-3: ALARM DIGIT FORMAT Month Day Day of Week 0-1 0-9 0-3 0-9 0-6 Hours (24-hour format) Minutes Seconds 0-2 0-9 0-5 0-9 0-5 0-9  2010 Microchip Technology Inc. Preliminary DS39974A-page 249 PIC18F47J13 FAMILY 17.2.2 CLOCK SOURCE As mentioned earlier, the RTCC module is intended to be clocked by an external Real-Time Clock (RTC) crystal oscillating at 32.768 kHz, but can also be clocked by the INTRC. The RTCC clock selection is decided by the RTCOSC bit (CONFIG3L). Calibration of the crystal can be done through this module to yield an error of 3 seconds or less per month. (For further details, see Section 17.2.9 “Calibration”.) FIGURE 17-4: 32.768 kHz XTAL from T1OSC Internal RC CONFIG 3L CLOCK SOURCE MULTIPLEXING Half Second Clock 1:16384 Clock Prescaler(1) Half Second(1) One Second Clock Second Hour:Minute Day Day of Week Month Year Note 1: Writing to the lower half of the MINSEC register resets all counters, allowing fraction of a second synchronization. The clock prescaler is held in Reset when RTCEN = 0. 17.2.2.1 Real-Time Clock Enable For the day to month rollover schedule, see Table 17-2. Considering that the following values are in BCD format, the carry to the upper BCD digit will occur at a count of 10 and not at 16 (SECONDS, MINUTES, HOURS, WEEKDAY, DAYS and MONTHS). The RTCC module can be clocked by an external, 32.768 kHz crystal (Timer1 oscillator or T1CKI input) or the INTRC oscillator, which can be selected in CONFIG3L. If the Timer1 oscillator will be used as the clock source for the RTCC, make sure to enable it by setting T1CON (T1OSCEN). The selected RTC clock can be brought out to the RTCC pin by the RTSECSEL bits in the PADCFG1 register. TABLE 17-1: DAY OF WEEK SCHEDULE Day of Week 0 1 2 3 4 5 6 Sunday Monday Tuesday Wednesday Thursday Friday Saturday 17.2.3 DIGIT CARRY RULES This section explains which timer values are affected when there is a rollover. • Time of Day: From 23:59:59 to 00:00:00 with a carry to the Day field • Month: From 12/31 to 01/01 with a carry to the Year field • Day of Week: From 6 to 0 with no carry (see Table 17-1) • Year Carry: From 99 to 00; this also surpasses the use of the RTCC DS39974A-page 250 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 17-2: Month 01 (January) 02 (February) 03 (March) 04 (April) 05 (May) 06 (June) 07 (July) 08 (August) 09 (September) 10 (October) 11 (November) 12 (December) Note 1: DAY TO MONTH ROLLOVER SCHEDULE Maximum Day Field 31 28 or 29(1) 31 30 31 30 31 31 30 31 30 31 17.2.6 SAFETY WINDOW FOR REGISTER READS AND WRITES The RTCSYNC bit indicates a time window during which the RTCC Clock Domain registers can be safely read and written without concern about a rollover. When RTCSYNC = 0, the registers can be safely accessed by the CPU. Whether RTCSYNC = 1 or 0, the user should employ a firmware solution to ensure that the data read did not fall on a rollover boundary, resulting in an invalid or partial read. This firmware solution would consist of reading each register twice and then comparing the two values. If the two values matched, then, a rollover did not occur. 17.2.7 WRITE LOCK See Section 17.2.4 “Leap Year”. In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RTCCFG) must be set. To avoid accidental writes to the RTCC Timer register, it is recommended that the RTCWREN bit (RTCCFG) be kept clear at any time other than while writing to it. For the RTCWREN bit to be set, there is only one instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN. For that reason, it is recommended that users follow the code example in Example 17-1. 17.2.4 LEAP YEAR Since the year range on the RTCC module is 2000 to 2099, the leap year calculation is determined by any year divisible by four in the above range. Only February is effected in a leap year. February will have 29 days in a leap year and 28 days in any other year. 17.2.5 GENERAL FUNCTIONALITY EXAMPLE 17-1: movlb bcf movlw movwf movlw movwf bsf All Timer registers containing a time value of seconds or greater are writable. The user configures the time by writing the required year, month, day, hour, minutes and seconds to the Timer registers, via register pointers (see Section 17.2.8 “Register Mapping”). The timer uses the newly written values and proceeds with the count from the required starting point. The RTCC is enabled by setting the RTCEN bit (RTCCFG). If enabled, while adjusting these registers, the timer still continues to increment. However, any time the MINSEC register is written to, both of the timer prescalers are reset to ‘0’. This allows fraction of a second synchronization. The Timer registers are updated in the same cycle as the write instruction’s execution by the CPU. The user must ensure that when RTCEN = 1, the updated registers will not be incremented at the same time. This can be accomplished in several ways: • By checking the RTCSYNC bit (RTCCFG) • By checking the preceding digits from which a carry can occur • By updating the registers immediately following the seconds pulse (or alarm interrupt) The user has visibility to the half second field of the counter. This value is read-only and can be reset only by writing to the lower half of the SECONDS register. SETTING THE RTCWREN BIT 0x0F ;RTCCFG is banked INTCON, GIE ;Disable interrupts 0x55 EECON2 0xAA EECON2 RTCCFG, RTCWREN 17.2.8 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Timer registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RTCCFG) to select the required Timer register pair. By reading or writing to the RTCVALH register, the RTCC Pointer value (RTCPTR) decrements by 1 until it reaches ‘00’. Once it reaches ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed.  2010 Microchip Technology Inc. Preliminary DS39974A-page 251 PIC18F47J13 FAMILY TABLE 17-3: RTCVALH AND RTCVALL REGISTER MAPPING RTCC Value Register Window RTCPTR RTCVAL 00 01 10 11 MINUTES WEEKDAY MONTH — RTCVAL SECONDS HOURS DAY YEAR To calibrate the RTCC module: 1. 2. Use another timer resource on the device to find the error of the 32.768 kHz crystal. Convert the number of error clock pulses per minute (see Equation 17-1). EQUATION 17-1: CONVERTING ERROR CLOCK PULSES (Ideal Frequency (32,768) – Measured Frequency) * 60 = Error Clocks per Minute • If the oscillator is faster than ideal (negative result from Step 2), the RTCCFG register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. • If the oscillator is slower than ideal (positive result from Step 2), the RTCCFG register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. Load the RTCCAL register with the correct value. The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALRMCFG) to select the desired Alarm register pair. By reading or writing to the ALRMVALH register, the Alarm Pointer value, ALRMPTR, decrements by 1 until it reaches ‘00’. Once it reaches ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. TABLE 17-4: ALRMVAL REGISTER MAPPING Alarm Value Register Window 3. ALRMPTR ALRMVAL ALRMVAL 00 01 10 11 ALRMMIN ALRMWD ALRMMNTH — ALRMSEC ALRMHR ALRMDAY — Writes to the RTCCAL register should occur only when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: In determining the crystal’s error value, it is the user’s responsibility to include the crystal’s initial error from drift due to temperature or crystal aging. 17.2.9 CALIBRATION The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than three seconds per month. To perform this calibration, find the number of error clock pulses and store the value in the lower half of the RTCCAL register. The 8-bit, signed value, loaded into RTCCAL, is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. DS39974A-page 252 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.3 Alarm The alarm features and characteristics are: • Configurable from half a second to one year • Enabled using the ALRMEN bit (ALRMCFG, Register 17-4) • Offers one time and repeat alarm options The alarm can also be configured to repeat based on a preconfigured interval. The number of times this occurs, after the alarm is enabled, is stored in the ALRMRPT register. Note: While the alarm is enabled (ALRMEN = 1), changing any of the registers, other than the RTCCAL, ALRMCFG and ALRMRPT registers, and the CHIME bit, can result in a false alarm event leading to a false alarm interrupt. To avoid this, only change the timer and alarm values while the alarm is disabled (ALRMEN = 0). It is recommended that the ALRMCFG and ALRMRPT registers and CHIME bit be changed when RTCSYNC = 0. 17.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. The bit will not be cleared if the CHIME bit = 1 or if ALRMRPT  0. The interval selection of the alarm is configured through the ALRMCFG (AMASK) bits (see Figure 17-5). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. FIGURE 17-5: ALARM MASK SETTINGS Day of the Week Month Day Hours Minutes Seconds Alarm Mask Setting AMASK 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds 0011 – Every minute 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week 1000 – Every month 1001 – Every year(1) s s m m h d d m m d d d h h h h h h h m m m m m m m m m s s s s s s s s s s s s s Note 1: Annually, except when configured for February 29.  2010 Microchip Technology Inc. Preliminary DS39974A-page 253 PIC18F47J13 FAMILY When ALRMCFG = 00 and the CHIME bit = 0 (ALRMCFG), the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading the ALRMRPT register with FFh. After each alarm is issued, the ALRMRPT register is decremented by one. Once the register has reached ‘00’, the alarm will be issued one last time. After the alarm is issued a last time, the ALRMEN bit is cleared automatically and the alarm turned off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. When CHIME = 1, the alarm is not disabled when the ALRMRPT register reaches ‘00’, but it rolls over to FF and continues counting indefinitely. 17.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. Additionally, an alarm pulse output is provided that operates at half the frequency of the alarm. The alarm pulse output is completely synchronous with the RTCC clock and can be used as a trigger clock to other peripherals. This output is available on the RTCC pin. The output pulse is a clock with a 50% duty cycle and a frequency half that of the alarm event (see Figure 17-6). The RTCC pin can also output the seconds clock. The user can select between the alarm pulse, generated by the RTCC module, or the seconds clock output. The RTSECSEL (PADCFG1) bits select between these two outputs: • Alarm pulse – RTSECSEL = 00 • Seconds clock – RTSECSEL = 01 FIGURE 17-6: RTCEN bit TIMER PULSE GENERATION ALRMEN bit RTCC Alarm Event RTCC Pin 17.4 Low-Power Modes 17.5.2 POWER-ON RESET (POR) The timer and alarm can optionally continue to operate while in Sleep, Idle and even Deep Sleep mode. An alarm event can be used to wake-up the microcontroller from any of these Low-Power modes. The RTCCFG and ALRMRPT registers are reset only on a POR. Once the device exits the POR state, the clock registers should be reloaded with the desired values. The timer prescaler values can be reset only by writing to the SECONDS register. No device Reset can affect the prescalers. 17.5 17.5.1 Reset DEVICE RESET When a device Reset occurs, the ALCFGRPT register is forced to its Reset state, causing the alarm to be disabled (if enabled prior to the Reset). If the RTCC was enabled, it will continue to operate when a basic device Reset occurs. DS39974A-page 254 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 17.6 Register Maps Table 17-5, Table 17-6 and Table 17-7 summarize the registers associated with the RTCC module. TABLE 17-5: File Name RTCCFG RTCCAL PADCFG1 ALRMCFG ALRMRPT PIR3 PIE3 IPR3 Legend: RTCC CONTROL REGISTERS Bit 7 Bit 6 — CAL6 — CHIME ARPT6 BCL2IF BCL2IE BCL2IP Bit 5 RTCWREN CAL5 — AMASK3 ARPT5 RC2IF RC2IE RC2IP Bit 4 RTCSYNC CAL4 — AMASK2 ARPT4 TX2IF TX2IE TX2IP Bit 3 HALFSEC CAL3 — AMASK1 ARPT3 TMR4IF TMR4IE TMR4IP Bit 2 RTCOE CAL2 AMASK0 ARPT2 CTMUIF CTMUIE CTMUIP Bit 1 RTCPTR1 CAL1 Bit 0 RTCPTR0 CAL0 PMPTTL ARPT0 RTCCCIF RTCCCIE RTCCCIP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 RTCEN CAL7 — ALRMEN ARPT7 SSP2IF SSP2IE SSP2IP RTSECSEL1 RTSECSEL0 ARPT1 TMR3GIF TMR3GIE TMR3GIP ALRMPTR1 ALRMPTR0 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices. TABLE 17-6: File Name RTCVALH RTCVALL RTCCFG ALRMCFG ALRMVALL Legend: RTCC VALUE REGISTERS Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx RTCPTR1 ALRMPTR1 RTCPTR0 ALRMPTR0 0000 0000 xxxx xxxx RTCC Value Register Window High Byte, Based on RTCPTR RTCC Value Register Window Low Byte, Based on RTCPTR RTCEN ALRMEN — CHIME RTCWREN RTCSYNC HALFSEC AMASK3 AMASK2 AMASK1 RTCOE AMASK0 ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR Alarm Value Register Window Low Byte, Based on ALRMPTR — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices. TABLE 17-7: File Name ALRMRPT ALARM VALUE REGISTERS Bit 7 ARPT7 Bit 6 ARPT6 Bit 5 ARPT5 Bit 4 ARPT4 Bit 3 ARPT3 Bit 2 ARPT2 Bit 1 ARPT1 Bit 0 ARPT0 All Resets 0000 xxxx xxxx CAL2 CAL1 CAL0 0000 xxxx xxxx ALRMVALH Alarm Value Register Window High Byte, Based on ALRMPTR ALRMVALL Alarm Value Register Window Low Byte, Based on ALRMPTR RTCCAL RTCVALH RTCVALL Legend: CAL7 CAL6 CAL5 CAL4 CAL3 RTCC Value Register Window High Byte, Based on RTCPTR RTCC Value Register Window Low Byte, Based on RTCPTR — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 44-pin devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 255 PIC18F47J13 FAMILY NOTES: DS39974A-page 256 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 18.0 CAPTURE/COMPARE/PWM (CCP) MODULES Each CCP module contains a 16-bit register that can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. For the sake of clarity, all CCP module operation in the following sections is described with respect to CCP4, but is equally applicable to CCP5 through CCP10. PIC18F47J13 family devices have seven CCP (Capture/Compare/PWM) modules, designated CCP4 through CCP10. All the modules implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes. Note: Throughout this section, generic references are used for register and bit names that are the same – except for an ‘x’ variable that indicates the item’s association with the specific CCP module. For example, the control register is named CCPxCON and refers to CCP4CON through CCP10CON. REGISTER 18-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 bit 5-4 U-0 — CCPxCON: CCP4-10 CONTROL REGISTER (4, BANKED F12h; 5, F0Fh; 6, F0Ch; 7, F09h; 8, F06h; 9, F03h; 10, F00h) R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3(1) R/W-0 CCPxM2(1) R/W-0 CCPxM1(1) R/W-0 CCPxM0(1) bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DCxB: PWM Duty Cycle Bit 1 and Bit 0 for CCPx Module Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two Least Significant bits (Bit 1 and Bit 0) of the 10-bit PWM duty cycle. The eight Most Significant bits (DCxB) of the duty cycle are found in CCPRxL. CCPxM: CCPx Module Mode Select bits(1) 0000 = Capture/Compare/PWM disabled (resets CCPx module) 0001 = Reserved 0010 = Compare mode, toggle output on match (CCPxIF bit is set) 0011 = Reserved 0100 = Capture mode: every falling edge 0101 = Capture mode: every rising edge 0110 = Capture mode: every 4th rising edge 0111 = Capture mode: every 16th rising edge 1000 = Compare mode: initialize CCPx pin low; on compare match, force CCPx pin high (CCPxIF bit is set) 1001 = Compare mode: initialize CCPx pin high; on compare match, force CCPx pin low (CCPxIF bit is set) 1010 = Compare mode: generate software interrupt on compare match (CCPxIF bit is set, CCPx pin reflects I/O state) 1011 = Compare mode: Special Event Trigger; reset timer on CCPx match (CCPxIF bit is set) 11xx = PWM mode CCPxM = 1011 will only reset the timer and not start an A/D conversion on CCPx match. bit 3-0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 257 PIC18F47J13 FAMILY REGISTER 18-2: R/W-0 C7TSEL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPTMRS1: CCP4-10 TIMER SELECT 1 REGISTER (BANKED F51h) R/W-0 U-0 — R/W-0 C6TSEL0 U-0 — R/W-0 C5TSEL0 R/W-0 C4TSEL1 R/W-0 C4TSEL0 bit 0 C7TSEL0 C7TSEL: CCP7 Timer Selection bit 00 = CCP7 is based off of TMR1/TMR2 01 = CCP7 is based off of TMR5/TMR4 10 = CCP7 is based off of TMR5/TMR6 11 = CCP7 is based off of TMR5/TMR8 Unimplemented: Read as ‘0’ C6TSEL0: CCP6 Timer Selection bit 0 = CCP6 is based off of TMR1/TMR2 1 = CCP6 is based off of TMR5/TMR2 Unimplemented: Read as ‘0’ C5TSEL0: CCP5 Timer Selection bit 0 = CCP5 is based off of TMR1/TMR2 1 = CCP5 is based off of TMR5/TMR4 C4TSEL: CCP4 Timer Selection bits 00 = CCP4 is based off of TMR1/TMR2 01 = CCP4 is based off of TMR3/TMR4 10 = CCP4 is based off of TMR3/TMR6 11 = Reserved; do not use bit 5 bit 4 bit 3 bit 2 bit 1-0 DS39974A-page 258 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 18-3: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 bit 4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPTMRS2: CCP4-10 TIMER SELECT 2 REGISTER (BANKED F50h) U-0 — U-0 — R/W-0 C10TSEL0 U-0 — R/W-0 C9TSEL0 R/W-0 C8TSEL1 R/W-0 C8TSEL0 bit 0 Unimplemented: Read as ‘0’ C10TSEL0: CCP10 Timer Selection bit 0 = CCP10 is based off of TMR1/TMR2 1 = Reserved; do not use Unimplemented: Read as ‘0’ C9TSEL0: CCP9 Timer Selection bit 0 = CCP9 is based off of TMR1/TMR2 1 = CCP9 is based off of TMR1/TMR4 C8TSEL: CCP8 Timer Selection bits 00 = CCP8 is based off of TMR1/TMR2 01 = CCP8 is based off of TMR1/TMR4 10 = CCP8 is based off of TMR1/TMR6 11 = Reserved; do not use bit 3 bit 2 bit 1-0  2010 Microchip Technology Inc. Preliminary DS39974A-page 259 PIC18F47J13 FAMILY REGISTER 18-4: R/W-x CCPRxL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPRxL: CCP4-10 PERIOD LOW BYTE REGISTER (4, BANKED F13h; 5, F10h; 6, F0Dh; 7, F0Ah; 8, F07h; 9, F04h; 10, F01h) R/W-x R/W-x CCPRxL5 R/W-x CCPRxL4 R/W-x CCPRxL3 R/W-x CCPRxL2 R/W-x CCPRxL1 R/W-x CCPRxL0 bit 0 CCPRxL6 CCPRxL: CCPx Period Register Low Byte bits Capture Mode: Capture register low byte Compare Mode: Compare register low byte PWM Mode: PWM Period register low byte REGISTER 18-5: R/W-x CCPRxH7 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-0 CCPRxH: CCP4-10 PERIOD HIGH BYTE REGISTER (4, BANKED F14h; 5, F11h; 6, F0Eh; 7, F0Bh; 8, F08h; 9, F05h; 10, F02h) R/W-x R/W-x CCPRxH5 R/W-x CCPRxH4 R/W-x CCPRxH3 R/W-x CCPRxH2 R/W-x CCPRxH1 R/W-x CCPRxH0 bit 0 CCPRxH6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPRxH: CCPx Period Register High Byte bits Capture Mode: Capture register high byte Compare Mode: Compare register high byte PWM Mode: PWM Period register high byte DS39974A-page 260 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 18.1 CCP Module Configuration TABLE 18-1: CCP Mode Capture Compare PWM Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. CCP MODE – TIMER RESOURCE Timer Resource Timer1, Timer3 or Timer5 Timer2, Timer4, Timer6 or Timer8 18.1.1 CCP MODULES AND TIMER RESOURCES The CCP modules utilize Timers, 1 through 8, varying with the selected mode. Various timers are available to the CCP modules in Capture, Compare or PWM modes, as shown in Table 18-1. The assignment of a particular timer to a module is determined by the Timer to CCP enable bits in the CCPTMRSx registers. (See Register 18-2 and Register 18-3.) All of the modules may be active at once and may share the same timer resource if they are configured to operate in the same mode (Capture/Compare or PWM), at the same time. The CCPTMRS1 register selects the timers for CCP modules, 7, 6, 5 and 4, and the CCPTMRS2 register selects the timers for CCP modules, 10, 9 and 8. The possible configurations are shown in Table 18-2 and Table 18-3. TABLE 18-2: TIMER ASSIGNMENTS FOR CCP MODULES 4, 5, 6 AND 7 CCPTMRS1 Register CCP4 Capture/ C4TSEL Compare Mode 00 01 10 11 Note 1: TMR1 TMR3 TMR3 PWM Mode TMR2 TMR4 TMR6 CCP5 Capture/ C5TSEL0 Compare Mode 0 1 TMR1 TMR5 CCP6 Capture/ PWM C6TSEL0 Compare Mode Mode TMR2 TMR4 0 1 TMR1 TMR5 PWM Mode TMR2 TMR2 CCP7 Capture/ C7TSEL Compare Mode 00 01 10 11 TMR1 TMR5 TMR5 TMR5 PWM Mode TMR2 TMR4 TMR6 TMR8 Reserved(1) Do not use the reserved bit configuration. TABLE 18-3: TIMER ASSIGNMENTS FOR CCP MODULES 8, 9 AND 10 CCPTMRS2 Register CCP8 Capture/ C8TSEL Compare Mode 00 01 10 11 Note 1: TMR1 TMR1 TMR1 CCP8 Devices with 64 Kbyte Capture/ PWM C8TSEL Compare Mode Mode TMR2 TMR4 TMR6 00 01 10 11 TMR1 TMR1 TMR1 CCP9 CCP10 Capture/ PWM C10TSEL0 Compare Mode Mode TMR2 TMR4 0 1 TMR1 PWM Mode TMR2 Capture/ PWM C9TSEL0 Compare Mode Mode TMR2 TMR4 TMR6 0 1 TMR1 TMR1 Reserved(1) Reserved(1) Reserved(1) Do not use the reserved bit configuration.  2010 Microchip Technology Inc. Preliminary DS39974A-page 261 PIC18F47J13 FAMILY 18.1.2 OPEN-DRAIN OUTPUT OPTION When operating in Output mode (the Compare or PWM modes), the drivers for the CCPx pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor and allows the output to communicate with external circuits without the need for additional level shifters. The open-drain output option is controlled by the CCPxOD bits (ODCON1 and ODCON2). Setting the appropriate bit configures the pin for the corresponding module for open-drain operation. The event is selected by the mode select bits, CCP4M (CCP4CON). When a capture is made, the interrupt request flag bit, CCP4IF (PIR4), is set. (It must be cleared in software.) If another capture occurs before the value in register, CCPR4, is read, the old captured value is overwritten by the new captured value. Figure 18-1 shows the Capture mode block diagram. 18.2.1 CCP PIN CONFIGURATION In Capture mode, the appropriate CCPx pin should be configured as an input by setting the corresponding TRISx direction bit. Note: If RB4 is configured as a CCP4 output, a write to the port causes a capture condition. 18.2 Capture Mode In Capture mode, the CCPR4H:CCPR4L register pair captures the 16-bit value of the TMR1 or TMR3 register when an event occurs on the CCP4 pin, RB4. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every 4th rising edge Every 16th rising edge 18.2.2 TIMER1/3/5 MODE SELECTION For the available timers (1/3/5) to be used for the capture feature, the used timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each CCP module is selected in the CCPTMRSx registers. (See Section 18.1.1 “CCP Modules and Timer Resources”.) Details of the timer assignments for the CCP modules are given in Table 18-2 and Table 18-3. FIGURE 18-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP5IF C5TSEL0 TMR5H TMR5 Enable CCPR5H TMR1 Enable TMR1H Set CCP4IF TMR1L CCPR5L TMR5L CCP5 Pin Prescaler  1, 4, 16 and Edge Detect C5TSEL0 CCP5CON Q1:Q4 CCP4CON 4 4 4 C4TSEL1 C4TSEL0 TMR3H TMR3 Enable CCPR4H TMR1 Enable TMR3L CCP4 Pin Prescaler  1, 4, 16 and Edge Detect CCPR4L C4TSEL0 C4TSEL1 TMR1H TMR1L Note: This block diagram uses CCP4 and CCP5, and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table 18-2 and Table 18-3. DS39974A-page 262 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 18.2.3 SOFTWARE INTERRUPT 18.3.1 CCP PIN CONFIGURATION When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCP4IE bit (PIE4) clear to avoid false interrupts and should clear the flag bit, CCP4IF, following any such change in operating mode. The user must configure the CCPx pin as an output by clearing the appropriate TRISx bit. Note: Clearing the CCP4CON register will force the RB4 compare output latch (depending on device configuration) to the default low level. This is not the PORTB I/O data latch. 18.2.4 CCP PRESCALER 18.3.2 There are four prescaler settings in Capture mode. They are specified as part of the operating mode selected by the mode select bits (CCP4M). Whenever the CCP module is turned off, or the CCP module is not in Capture mode, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Doing that also will not clear the prescaler counter – meaning the first capture may be from a non-zero prescaler. Example 18-1 shows the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. TIMER1/3/5 MODE SELECTION If the CCP module is using the compare feature in conjunction with any of the Timer1/3/5 timers, the timers must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the compare operation may not work. Note: Details of the timer assignments for the CCP modules are given in Table 18-2 and Table 18-3. 18.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCP4M = 1010), the CCP4 pin is not affected. Only a CCP interrupt is generated, if enabled, and the CCP4IE bit is set. EXAMPLE 18-1: CLRF MOVLW CHANGING BETWEEN CAPTURE PRESCALERS ; ; ; ; ; ; Turn CCP module off Load WREG with the new prescaler mode value and CCP ON Load CCP4CON with this value 18.3.4 SPECIAL EVENT TRIGGER CCP4CON NEW_CAPT_PS MOVWF CCP4CON Both CCP modules are equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCP4M = 1011). For either CCP module, the Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module’s time base. This allows the CCPRx registers to serve as a programmable period register for either timer. The Special Event Trigger for CCP4 cannot start an A/D conversion. Note: The Special Event Trigger of ECCP1 can start an A/D conversion, but the A/D Converter must be enabled. For more information, see Section 19.0 “Enhanced Capture/Compare/PWM (ECCP) Module”. 18.3 Compare Mode In Compare mode, the 16-bit CCPR4 register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCP4 pin can be: • • • • Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) The action on the pin is based on the value of the mode select bits (CCP4M). At the same time, the interrupt flag bit, CCP4IF, is set. Figure 18-2 gives the Compare mode block diagram  2010 Microchip Technology Inc. Preliminary DS39974A-page 263 PIC18F47J13 FAMILY FIGURE 18-2: COMPARE MODE OPERATION BLOCK DIAGRAM Set CCP5IF Special Event Trigger (Timer1/5 Reset) CCP5 Pin Comparator Compare Match Output Logic 4 CCP5CON TMR1H TMR1L 0 S R TRIS Output Enable Q CCPR5H CCPR5L TMR5H TMR5L 1 C5TSEL0 0 TMR1H TMR1L 1 TMR5H C4TSEL1 C4TSEL0 TMR5L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) Set CCP4IF Comparator Compare Match Output Logic 4 CCP4CON S R Q CCP4 Pin CCPR4H CCPR4L TRIS Output Enable Note: This block diagram uses CCP4 and CCP5 and their appropriate timers as an example. For details on all of the CCP modules and their timer assignments, see Table 18-2 and Table 18-3. DS39974A-page 264 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 18-4: Name INTCON RCON PIR4 PIE4 IPR4 TRISB TRISC TRISE TMR1L TMR1H TMR3L TMR3H TMR5L TMR5H T1CON T3CON T5CON CCPR4L CCPR4H CCPR5L CCPR5H CCPR6L CCPR6H CCPR7L CCPR7H CCPR8L CCPR8H CCPR9L CCPR9H CCPR10L CCPR10H CCP4CON CCP5CON CCP6CON CCP7CON CCP8CON CCP9CON CCP10CON CCPTMRS1 CCPTMRS2 REGISTERS ASSOCIATED WITH CAPTURE, COMPARE, TIMER1/3/5/7 Bit 7 GIE/GIEH IPEN CCP10IF CCP10IE CCP10IP TRISB7 TRISC7 RDPU Bit 6 PEIE/GIEL — CCP9IF CCP9IE CCP9IP TRISB6 TRISC6 REPU Bit 5 TMR0IE CM CCP8IF CCP8IE CCP8IP TRISB5 TRISC5 — Bit 4 INT0IE RI CCP7IF CCP7IE CCP7IP TRISB4 TRISC4 — Bit 3 RBIE TO CCP6IF CCP6IE CCP6IP TRISB3 TRISC3 — Bit 2 TMR0IF PD CCP5IF CCP5IE CCP5IP TRISB2 TRISC2 TRISE2 Bit 1 INT0IF POR CCP4IF CCP4IE CCP4IP TRISB1 TRISC1 TRISE1 Bit 0 RBIF BOR CCP3IF CCP3IE CCP3IP TRISB0 TRISC0 TRISE0 Timer1 Register Low Byte Timer1 Register High Byte Timer3 Register Low Byte Timer3 Register High Byte Timer5 Register Low Byte Timer5 Register High Byte TMR1CS1 TMR1CS0 TMR3CS1 TMR3CS0 TMR5CS1 TMR5CS0 CCPR4L7 CCPR5L7 CCPR6L7 CCPR7L7 CCPR8L7 CCPR9L7 CCPR4L6 CCPR5L6 CCPR6L6 CCPR7L6 CCPR8L6 CCPR9L6 T1CKPS1 T3CKPS1 T5CKPS1 CCPR4L5 CCPR5L5 CCPR6L5 CCPR7L5 CCPR8L5 CCPR9L5 T1CKPS0 T3CKPS0 T5CKPS0 CCPR4L4 CCPR5L4 CCPR6L4 CCPR7L4 CCPR8L4 CCPR9L4 T1OSCEN T3OSCEN T5OSCEN CCPR4L3 CCPR5L3 CCPR6L3 CCPR7L3 CCPR8L3 CCPR9L3 T1SYNC T3SYNC T5SYNC CCPR4L2 CCPR5L2 CCPR6L2 CCPR7L2 CCPR8L2 CCPR9L2 RD16 RD16 RD16 CCPR4L1 CCPR5L1 CCPR6L1 CCPR7L1 CCPR8L1 CCPR9L1 TMR1ON TMR3ON TMR5ON CCPR4L0 CCPR5L0 CCPR6L0 CCPR7L0 CCPR8L0 CCPR9L0 CCPR4H7 CCPR4H6 CCPR4H5 CCPR4H4 CCPR4H3 CCPR4H2 CCPR4H1 CCPR4H0 CCPR5H7 CCPR5H6 CCPR5H5 CCPR5H4 CCPR5H3 CCPR5H2 CCPR5H1 CCPR5H0 CCPR6H7 CCPR6H6 CCPR6H5 CCPR6H4 CCPR6H3 CCPR6H2 CCPR6H1 CCPR6H0 CCPR7H7 CCPR7H6 CCPR7H5 CCPR7H4 CCPR7H3 CCPR7H2 CCPR7H1 CCPR7H0 CCPR8H7 CCPR8H6 CCPR8H5 CCPR8H4 CCPR8H3 CCPR8H2 CCPR8H1 CCPR8H0 CCPR9H7 CCPR9H6 CCPR9H5 CCPR9H4 CCPR9H3 CCPR9H2 CCPR9H1 CCPR9H0 CCPR10L7 CCPR10L6 CCPR10L5 CCPR10L4 CCPR10L3 CCPR10L2 CCPR10L1 CCPR10L0 CCPR10H7 CCPR10H6 CCPR10H5 CCPR10H4 CCPR10H3 CCPR10H2 CCPR10H1 CCPR10H0 — — — — — — — C7TSEL1 — — — — — — — — C7TSEL0 — DC4B1 DC5B1 DC6B1 DC7B1 DC8B1 DC9B1 DC10B1 — — DC4B0 DC5B0 DC6B0 DC7B0 DC8B0 DC9B0 DC10B0 C6TSEL0 C10TSEL0 CCP4M3 CCP5M3 CCP6M3 CCP7M3 CCP8M3 CCP9M3 CCP10M3 — — CCP4M2 CCP5M2 CCP6M2 CCP7M2 CCP8M2 CCP9M2 CCP10M2 C5TSEL0 C9TSEL0 CCP4M1 CCP5M1 CCP6M1 CCP7M1 CCP8M1 CCP9M1 C4TSEL1 C8TSEL1 CCP4M0 CCP5M0 CCP6M0 CCP7M0 CCP8M0 CCP9M0 C4TSEL0 C8TSEL0 CCP10M1 CCP10M0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare or Timer1/3/5.  2010 Microchip Technology Inc. Preliminary DS39974A-page 265 PIC18F47J13 FAMILY 18.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCP4 pin produces up to a 10-bit resolution PWM output. Since the CCP4 pin is multiplexed with a PORTB data latch, the appropriate TRISx bit must be cleared to make the CCP4 pin an output. Figure 18-3 shows a simplified block diagram of the CCP1 module in PWM mode. For a step-by-step procedure on how to set up the CCP module for PWM operation, see Section 18.4.3 “Setup for PWM Operation”. A PWM output (Figure 18-4) has a time base (period) and a time that the output stays high (duty cycle). The frequency of the PWM is the inverse of the period (1/period). FIGURE 18-4: Period PWM OUTPUT Duty Cycle TMR2 = PR2 TMR2 = Duty Cycle TMR2 = PR2 FIGURE 18-3: Duty Cycle Registers CCPR4L SIMPLIFIED PWM BLOCK DIAGRAM(2) CCP4CON 18.4.1 PWM PERIOD The PWM period is specified by writing to the PR2 register. The PWM period can be calculated using the following formula: CCPR4H (Slave) EQUATION 18-1: Comparator R Q RC2 TMR2 (Note 1) S TRISC Clear Timer, CCP1 pin and latch D.C. PWM Period = [(PR2) + 1] • 4 • TOSC • (TMR2 Prescale Value) PWM frequency is defined as 1/[PWM period]. When TMR2 is equal to PR2, the following three events occur on the next increment cycle: • TMR2 is cleared • The CCP4 pin is set (An exception: If the PWM duty cycle = 0%, the CCP4 pin will not be set) • The PWM duty cycle is latched from CCPR4L into CCPR4H Note: The Timer2 postscalers (see Section 14.0 “Timer2 Module”) are not used in the determination of the PWM frequency. The postscaler could be used to have a servo update rate at a different frequency than the PWM output. Comparator PR2 Note 1: 2: The 8-bit TMR2 value is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. CCP4 and its appropriate timers are used as an example. For details on all of the CCP modules and their timer assignments, see Table 18-2 and Table 18-3. DS39974A-page 266 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 18.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR4L register and to the CCP4CON bits. Up to 10-bit resolution is available. The CCPR4L contains the eight MSbs and the CCP4CON contains the two LSbs. This 10-bit value is represented by CCPR4L:CCP4CON. The following equation is used to calculate the PWM duty cycle in time: The CCPR4H register and a two-bit internal latch are used to double-buffer the PWM duty cycle. This double-buffering is essential for glitchless PWM operation. When the CCPR4H and two-bit latch match TMR2, concatenated with an internal two-bit Q clock or two bits of the TMR2 prescaler, the CCP4 pin is cleared. The maximum PWM resolution (bits) for a given PWM frequency is given by the equation: EQUATION 18-2: PWM Duty Cycle = (CCPR4L:CCP4CON) • TOSC • (TMR2 Prescale Value) CCPR4L and CCP4CON can be written to at any time, but the duty cycle value is not latched into CCPR4H until after a match between PR2 and TMR2 occurs (that is, the period is complete). In PWM mode, CCPR4H is a read-only register. EQUATION 18-3: F OSC log  ---------------  F PWM PWM Resolution (max) = -----------------------------bits log  2  Note: If the PWM duty cycle value is longer than the PWM period, the CCP4 pin will not be cleared. TABLE 18-5: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 40 MHz 2.44 kHz 16 FFh 10 9.77 kHz 4 FFh 10 39.06 kHz 1 FFh 10 156.25 kHz 1 3Fh 8 312.50 kHz 1 1Fh 7 416.67 kHz 1 17h 6.58 PWM Frequency Timer Prescaler (1, 4, 16) PR2 Value Maximum Resolution (bits) 18.4.3 1. 2. 3. 4. 5. SETUP FOR PWM OPERATION To configure the CCP module for PWM operation: Set the PWM period by writing to the PR2 register. Set the PWM duty cycle by writing to the CCPR4L register and CCP4CON bits. Make the CCP4 pin an output by clearing the appropriate TRISx bit. Set the TMR2 prescale value, then enable Timer2 by writing to T2CON. Configure the CCP4 module for PWM operation.  2010 Microchip Technology Inc. Preliminary DS39974A-page 267 PIC18F47J13 FAMILY TABLE 18-6: Name INTCON RCON PIR4 PIE4 IPR4 TRISB TRISC TRISE TMR2 TMR4 TMR6 TMR8 PR2 PR4 PR6 PR8 T2CON T4CON T6CON T8CON CCPR4L CCPR4H CCPR5L CCPR5H CCPR6L CCPR6H CCPR7L CCPR7H CCPR8L CCPR8H CCPR9L CCPR9H CCPR10L CCPR10H CCP4CON CCP5CON CCP6CON CCP7CON CCP8CON CCP9CON CCP10CON CCPTMRS1 CCPTMRS2 REGISTERS ASSOCIATED WITH PWM AND TIMERS Bit 7 IPEN CCP10IF CCP10IE CCP10IP TRISB7 TRISC7 RDPU Bit 6 — CCP9IF CCP9IE CCP9IP TRISB6 TRISC6 REPU Bit 5 TMR0IE CM CCP8IF CCP8IE CCP8IP TRISB5 TRISC5 — Bit 4 INT0IE RI CCP7IF CCP7IE CCP7IP TRISB4 TRISC4 — Bit 3 RBIE TO CCP6IF CCP6IE CCP6IP TRISB3 TRISC3 — Bit 2 TMR0IF PD CCP5IF CCP5IE CCP5IP TRISB2 TRISC2 TRISE2 Bit 1 INT0IF POR CCP4IF CCP4IE CCP4IP TRISB1 TRISC1 TRISE1 Bit 0 RBIF BOR CCP3IF CCP3IE CCP3IP TRISB0 TRISC0 TRISE0 GIE/GIEH PEIE/GIEL Timer2 Register Timer4 Register Timer6 Register Timer8 Register Timer2 Period Register Timer4 Period Register Timer6 Period Register Timer8 Period Register — — — — T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0 T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0 T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 TMR2ON TMR4ON TMR6ON TMR8ON T2CKPS1 T4CKPS1 T6CKPS1 T8CKPS1 T2CKPS0 T4CKPS0 T6CKPS0 T8CKPS0 CCPR4L7 CCPR4L6 CCPR4L5 CCPR4L4 CCPR4L3 CCPR4L2 CCPR4L1 CCPR4L0 CCPR4H7 CCPR4H6 CCPR4H5 CCPR4H4 CCPR4H3 CCPR4H2 CCPR4H1 CCPR4H0 CCPR5L7 CCPR5L6 CCPR5L5 CCPR5L4 CCPR5L3 CCPR5L2 CCPR5L1 CCPR5L0 CCPR5H7 CCPR5H6 CCPR5H5 CCPR5H4 CCPR5H3 CCPR5H2 CCPR5H1 CCPR5H0 CCPR6L7 CCPR6L6 CCPR6L5 CCPR6L4 CCPR6L3 CCPR6L2 CCPR6L1 CCPR6L0 CCPR6H7 CCPR6H6 CCPR6H5 CCPR6H4 CCPR6H3 CCPR6H2 CCPR6H1 CCPR6H0 CCPR7L7 CCPR7L6 CCPR7L5 CCPR7L4 CCPR7L3 CCPR7L2 CCPR7L1 CCPR7L0 CCPR7H7 CCPR7H6 CCPR7H5 CCPR7H4 CCPR7H3 CCPR7H2 CCPR7H1 CCPR7H0 CCPR8L7 CCPR8L6 CCPR8L5 CCPR8L4 CCPR8L3 CCPR8L2 CCPR8L1 CCPR8L0 CCPR8H7 CCPR8H6 CCPR8H5 CCPR8H4 CCPR8H3 CCPR8H2 CCPR8H1 CCPR8H0 CCPR9L7 CCPR9L6 CCPR9L5 CCPR9L4 CCPR9L3 CCPR9L2 CCPR9L1 CCPR9L0 CCPR9H7 CCPR9H6 CCPR9H5 CCPR9H4 CCPR9H3 CCPR9H2 CCPR9H1 CCPR9H0 CCPR10L7 CCPR10L6 CCPR10L5 CCPR10L4 CCPR10L3 CCPR10L2 CCPR10L1 CCPR10L0 CCPR10H7 CCPR10H6 CCPR10H5 CCPR10H4 CCPR10H3 CCPR10H2 CCPR10H1 CCPR10H0 — — DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 — — — — — — C7TSEL1 — — — — — — — C7TSEL0 — DC5B1 DC6B1 DC7B1 DC8B1 DC9B1 DC10B1 — — DC5B0 DC6B0 DC7B0 DC8B0 DC9B0 DC10B0 C6TSEL0 C10TSEL0 CCP5M3 CCP6M3 CCP7M3 CCP8M3 CCP9M3 CCP10M3 — — CCP5M2 CCP6M2 CCP7M2 CCP8M2 CCP5M1 CCP6M1 CCP7M1 CCP8M1 CCP5M0 CCP6M0 CCP7M0 CCP8M0 CCP9M2 CCP9M1 CCP9M0 CCP10M2 CCP10M1 CCP10M0 C5TSEL0 C9TSEL0 C4TSEL1 C8TSEL1 C4TSEL0 C8TSEL0 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PWM or Timer2/4/6/8. DS39974A-page 268 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.0 ENHANCED CAPTURE/COMPARE/PWM (ECCP) MODULE The ECCP modules are implemented as standard CCP modules with enhanced PWM capabilities. These include: • • • • • Provision for two or four output channels Output Steering modes Programmable polarity Programmable dead-band control Automatic shutdown and restart PIC18F47J13 family devices have three Enhanced Capture/Compare/PWM (ECCP) modules: ECCP1, ECCP2 and ECCP3. These modules contain a 16-bit register, which can operate as a 16-bit Capture register, a 16-bit Compare register or a PWM Master/Slave Duty Cycle register. These ECCP modules are upwardly compatible with CCP. Note: Throughout this section, generic references are used for register and bit names that are the same – except for an ‘x’ variable that indicates the item’s association with the ECCP1, ECCP2 or ECCP3 module. For example, the control register is named CCPxCON and refers to CCP1CON, CCP2CON and CCP3CON. The enhanced features are discussed in detail in Section 19.4 “PWM (Enhanced Mode)”.  2010 Microchip Technology Inc. Preliminary DS39974A-page 269 PIC18F47J13 FAMILY REGISTER 19-1: R/W-0 PxM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPxCON: ECCP1/2/3 CONTROL (1, ACCESS FBAh; 2, FB4h; 3, BANKED F15h) R/W-0 DCxB1 R/W-0 DCxB0 R/W-0 CCPxM3 R/W-0 CCPxM2 R/W-0 CCPxM1 R/W-0 CCPxM0 bit 0 PxM0 R/W-0 PxM: Enhanced PWM Output Configuration bits If CCPxM = 00, 01, 10: xx = PxA assigned as capture/compare input/output; PxB, PxC and PxD assigned as port pins If CCPxM = 11: 00 = Single output: PxA, PxB, PxC and PxD are controlled by steering (see Section 19.4.7 “Pulse Steering Mode”) 01 = Full-bridge output forward: PxD modulated; PxA active; PxB, PxC inactive 10 = Half-bridge output: PxA, PxB modulated with dead-band control; PxC and PxD assigned as port pins 11 = Full-bridge output reverse: PxB modulated; PxC active; PxA and PxD inactive DCxB: PWM Duty Cycle Bit 1 and Bit 0 Capture mode: Unused. Compare mode: Unused. PWM mode: These bits are the two LSbs of the 10-bit PWM duty cycle. The eight MSbs of the duty cycle are found in ECCPRxL. CCPxM: ECCPx Mode Select bits 0000 = Capture/Compare/PWM off (resets ECCPx module) 0001 = Reserved 0010 = Compare mode; toggle output on match 0011 = Capture mode 0100 = Capture mode; every falling edge 0101 = Capture mode; every rising edge 0110 = Capture mode; every fourth rising edge 0111 = Capture mode; every 16th rising edge 1000 = Compare mode; initialize ECCPx pin low, set output on compare match (set CCPxIF) 1001 = Compare mode; initialize ECCPx pin high, clear output on compare match (set CCPxIF) 1010 = Compare mode; generate software interrupt only, ECCPx pin reverts to I/O state 1011 = Compare mode; trigger special event (ECCPx resets TMR1 or TMR3, starts A/D conversion, sets CCPxIF bit) 1100 = PWM mode; PxA and PxC active-high; PxB and PxD active-high 1101 = PWM mode; PxA and PxC active-high; PxB and PxD active-low 1110 = PWM mode; PxA and PxC active-low; PxB and PxD active-high 1111 = PWM mode; PxA and PxC active-low; PxB and PxD active-low bit 5-4 bit 3-0 DS39974A-page 270 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 19-2: R/W-0 C3TSEL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CCPTMRS0: ECCP1/2/3 TIMER SELECT 0 REGISTER (BANKED F52h) R/W-0 R/W-0 C2TSEL2 R/W-0 C2TSEL1 R/W-0 C2TSEL0 R/W-0 C1TSEL2 R/W-0 C1TSEL1 R/W-0 C1TSEL0 bit 0 C3TSEL0 C3TSEL: ECCP3 Timer Selection bits 00 = ECCP3 is based off of TMR1/TMR2 01 = ECCP3 is based off of TMR3/TMR4 10 = ECCP3 is based off of TMR3/TMR6 11 = ECCP3 is based off of TMR3/TMR8 C2TSEL: ECCP2 Timer Selection bits 000 = ECCP2 is based off of TMR1/TMR2 001 = ECCP2 is based off of TMR3/TMR4 010 = ECCP2 is based off of TMR3/TMR6 011 = ECCP2 is based off of TMR3/TMR8 1xx = Reserved; do not use C1TSEL: ECCP1 Timer Selection bits 000 = ECCP1 is based off of TMR1/TMR2 001 = ECCP1 is based off of TMR3/TMR4 010 = ECCP1 is based off of TMR3/TMR6 011 = ECCP1 is based off of TMR3/TMR8 1xx = Reserved; do not use bit 5-3 bit 2-0 In addition to the expanded range of modes available through the CCPxCON and ECCPxAS registers, the ECCP modules have two additional registers associated with Enhanced PWM operation and auto-shutdown features. They are: • ECCPxDEL – Enhanced PWM Control • PSTRxCON – Pulse Steering Control  2010 Microchip Technology Inc. Preliminary DS39974A-page 271 PIC18F47J13 FAMILY 19.1 ECCP Outputs and Configuration 19.2 Capture Mode The Enhanced CCP module may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are routed through the Peripheral Pin Select (PPS) module. Therefore, individual functions can be mapped to any of the remappable I/O pins (RPn). The outputs that are active depend on the ECCP operating mode selected. The pin assignments are summarized in Table 19-3. To configure the I/O pins as PWM outputs, the proper PWM mode must be selected by setting the PxM and CCPxM bits. The appropriate TRIS direction bits for the port pins must also be set as outputs. In Capture mode, the CCPRxH:CCPRxL register pair captures the 16-bit value of the TMR1 or TMR3 registers when an event occurs on the corresponding ECCPx pin. An event is defined as one of the following: • • • • Every falling edge Every rising edge Every fourth rising edge Every 16th rising edge 19.1.1 ECCP MODULE AND TIMER RESOURCES The event is selected by the mode select bits, CCPxM (CCPxCON register). When a capture is made, the interrupt request flag bit, CCPxIF, is set (see Table 19-2). The flag must be cleared by software. If another capture occurs before the value in the CCPRxH/L register pair is read, the old captured value is overwritten by the new captured value. The ECCP modules use Timer1, 2, 3, 4, 6 or 8, depending on the mode selected. These timers are available to CCP modules in Capture, Compare or PWM modes, as shown in Table 19-1. TABLE 19-2: ECCP Module 1 2 3 ECCP1/2/3 INTERRUPT FLAG BITS Flag-Bit PIR1 PIR2 PIR4 TABLE 19-1: ECCP Mode Capture Compare PWM ECCP MODE – TIMER RESOURCE Timer Resource Timer1 or Timer3 Timer1 or Timer3 Timer2, Timer4, Timer6 or Timer8 19.2.1 ECCP PIN CONFIGURATION In Capture mode, the appropriate ECCPx pin should be configured as an input by setting the corresponding TRISx direction bit. Additionally, the ECCPx input function needs to be assigned to an I/O pin through the Peripheral Pin Select module. For details on setting up the remappable pins, see Section 10.7 “Peripheral Pin Select (PPS)”. Note: If the ECCPx pin is configured as an output, a write to the port can cause a capture condition. The assignment of a particular timer to a module is determined by the Timer to ECCP enable bits in the CCPTMRS0 register (Register 19-2). The interactions between the two modules are depicted in Figure 19-1. Capture operations are designed to be used when the timer is configured for Synchronous Counter mode. Capture operations may not work as expected if the associated timer is configured for Asynchronous Counter mode. DS39974A-page 272 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.2.2 TIMER1/TIMER3 MODE SELECTION The timers that are to be used with the capture feature (Timer1 and/or Timer3) must be running in Timer mode or Synchronized Counter mode. In Asynchronous Counter mode, the capture operation may not work. The timer to be used with each ECCP module is selected in the CCPTMRS0 register (Register 19-2). ECCP module is turned off, or Capture mode is disabled, the prescaler counter is cleared. This means that any Reset will clear the prescaler counter. Switching from one capture prescaler to another may generate an interrupt. Also, the prescaler counter will not be cleared; therefore, the first capture may be from a non-zero prescaler. Example 19-1 provides the recommended method for switching between capture prescalers. This example also clears the prescaler counter and will not generate the “false” interrupt. 19.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode. EXAMPLE 19-1: CLRF MOVLW CHANGING BETWEEN CAPTURE PRESCALERS 19.2.4 ECCP PRESCALER There are four prescaler settings in Capture mode; they are specified as part of the operating mode selected by the mode select bits (CCPxM). Whenever the MOVWF ECCP1CON ; Turn ECCP module off NEW_CAPT_PS ; Load WREG with the ; new prescaler mode ; value and ECCP ON CCP1CON ; Load ECCP1CON with ; this value FIGURE 19-1: CAPTURE MODE OPERATION BLOCK DIAGRAM Set CCP1IF ECCP1 Pin Prescaler  1, 4, 16 and Edge Detect TMR3H C1TSEL0 C1TSEL1 C1TSEL2 TMR3 Enable CCPR1H C1TSEL0 C1TSEL1 C1TSEL2 TMR1 Enable TMR1H TMR3L CCPR1L CCP1CON Q1:Q4 4 4 TMR1L  2010 Microchip Technology Inc. Preliminary DS39974A-page 273 PIC18F47J13 FAMILY 19.3 Compare Mode 19.3.2 TIMER1/TIMER3 MODE SELECTION In Compare mode, the 16-bit CCPRx register pair value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the ECCPx pin can be: • • • • Driven high Driven low Toggled (high-to-low or low-to-high) Unchanged (that is, reflecting the state of the I/O latch) Timer1 and/or Timer3 must be running in Timer mode or Synchronized Counter mode if the ECCP module is using the compare feature. In Asynchronous Counter mode, the compare operation will not work reliably. 19.3.3 SOFTWARE INTERRUPT MODE When the Generate Software Interrupt mode is chosen (CCPxM = 1010), the ECCPx pin is not affected; only the CCPxIF interrupt flag is affected. The action on the pin is based on the value of the mode select bits (CCPxM). At the same time, the interrupt flag bit, CCPxIF, is set. 19.3.4 SPECIAL EVENT TRIGGER 19.3.1 ECCP PIN CONFIGURATION Users must configure the ECCPx pin as an output by clearing the appropriate TRISx bit. Note: Clearing the CCPxCON register will force the ECCPx compare output latch (depending on device configuration) to the default low level. This is not the PORTx I/O data latch. The ECCP module is equipped with a Special Event Trigger. This is an internal hardware signal generated in Compare mode to trigger actions by other modules. The Special Event Trigger is enabled by selecting the Compare Special Event Trigger mode (CCPxM = 1011). The Special Event Trigger resets the Timer register pair for whichever timer resource is currently assigned as the module’s time base. This allows the CCPRx registers to serve as a Programmable Period register for either timer. The Special Event Trigger can also start an A/D conversion. In order to do this, the A/D Converter must already be enabled. FIGURE 19-2: COMPARE MODE OPERATION BLOCK DIAGRAM 0 TMR1H TMR1L 1 TMR3H TMR3L Special Event Trigger (Timer1/Timer3 Reset, A/D Trigger) C1TSEL0 C1TSEL1 C1TSEL2 Set CCP1IF Comparator Compare Match Output Logic 4 CCP1CON S R Q ECCP1 Pin CCPR1H CCPR1L TRIS Output Enable DS39974A-page 274 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.4 PWM (Enhanced Mode) The Enhanced PWM mode can generate a PWM signal on up to four different output pins with up to 10 bits of resolution. It can do this through four different PWM Output modes: • • • • Single PWM mode Half-Bridge PWM mode Full-Bridge PWM, Forward mode Full-Bridge PWM, Reverse mode The PWM outputs are multiplexed with I/O pins and are designated: PxA, PxB, PxC and PxD. The polarity of the PWM pins is configurable and is selected by setting the CCPxM bits in the CCPxCON register appropriately. Table 19-1 provides the pin assignments for each Enhanced PWM mode. Figure 19-3 provides an example of a simplified block diagram of the Enhanced PWM module. Note: To prevent the generation of an incomplete waveform when the PWM is first enabled, the ECCP module waits until the start of a new PWM period before generating a PWM signal. To select an Enhanced PWM mode, the PxM bits of the CCPxCON register must be set appropriately. FIGURE 19-3: SIMPLIFIED BLOCK DIAGRAM OF THE ENHANCED PWM MODE EXAMPLE DC1B PxM 2 CCPxM 4 Duty Cycle Registers CCPR1L ECCPx/PxA TRIS CCPR1H (Slave) R Q PxB Output Controller PxC TMR2 (1) S PxD Clear Timer2, Toggle PWM Pin and Latch Duty Cycle ECCP1DEL TRIS TRIS TRIS ECCPx/Output Pin Output Pin Comparator Output Pin Comparator Output Pin PR2 Note 1: The 8-bit timer, TMR2 register, is concatenated with the 2-bit internal Q clock, or 2 bits of the prescaler, to create the 10-bit time base. Note 1: The TRIS register value for each PWM output must be configured appropriately. 2: Any pin not used by an Enhanced PWM mode is available for alternate pin functions.  2010 Microchip Technology Inc. Preliminary DS39974A-page 275 PIC18F47J13 FAMILY TABLE 19-3: Single Half-Bridge Full-Bridge, Forward Full-Bridge, Reverse Note 1: EXAMPLE PIN ASSIGNMENTS FOR VARIOUS PWM ENHANCED MODES PxM 00 10 01 11 PxA Yes(1) Yes Yes Yes PxB Yes(1) Yes Yes Yes PxC Yes(1) No Yes Yes PxD Yes(1) No Yes Yes ECCP Mode Outputs are enabled by pulse steering in Single mode (see Register 19-5). FIGURE 19-4: PxM PWM (ENHANCED MODE) OUTPUT RELATIONSHIPS (ACTIVE-HIGH STATE) EXAMPLE Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) PxA Modulated Delay(1) PxA Modulated Delay(1) 10 (Half-Bridge) PxB Modulated PxA Active 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL) Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section 19.4.6 “Programmable Dead-Band Delay Mode”). DS39974A-page 276 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 19-5: PxM ENHANCED PWM OUTPUT RELATIONSHIPS (ACTIVE-LOW STATE) EXAMPLE Signal 0 Pulse Width Period PR2 + 1 00 (Single Output) PxA Modulated PxA Modulated 10 (Half-Bridge) Delay(1) PxB Modulated PxA Active Delay(1) 01 (Full-Bridge, Forward) PxB Inactive PxC Inactive PxD Modulated PxA Inactive 11 (Full-Bridge, Reverse) PxB Modulated PxC Active PxD Inactive Relationships: • Period = 4 * TOSC * (PR2 + 1) * (TMR2 Prescale Value) • Pulse Width = TOSC * (CCPRxL:CCPxCON) * (TMR2 Prescale Value) • Delay = 4 * TOSC * (ECCPxDEL) Note 1: Dead-band delay is programmed using the ECCPxDEL register (see Section 19.4.6 “Programmable Dead-Band Delay Mode”).  2010 Microchip Technology Inc. Preliminary DS39974A-page 277 PIC18F47J13 FAMILY 19.4.1 HALF-BRIDGE MODE In Half-Bridge mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the PxA pin, while the complementary PWM output signal is output on the PxB pin (see Figure 19-6). This mode can be used for half-bridge applications, as shown in Figure 19-7, or for full-bridge applications, where four power switches are being modulated with two PWM signals. In Half-Bridge mode, the programmable dead-band delay can be used to prevent shoot-through current in half-bridge power devices. The value of the PxDC bits of the ECCPxDEL register sets the number of instruction cycles before the output is driven active. If the value is greater than the duty cycle, the corresponding output remains inactive during the entire cycle. For more details on the dead-band delay operations, see Section 19.4.6 “Programmable Dead-Band Delay Mode”. Since the PxA and PxB outputs are multiplexed with the port data latches, the associated TRIS bits must be cleared to configure PxA and PxB as outputs. FIGURE 19-6: EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width PxA(2) td PxB(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 19-7: EXAMPLE OF HALF-BRIDGE APPLICATIONS Standard Half-Bridge Circuit (“Push-Pull”) FET Driver PxA + Load FET Driver PxB + - Half-Bridge Output Driving a Full-Bridge Circuit V+ FET Driver PxA Load FET Driver FET Driver PxB FET Driver DS39974A-page 278 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.4.2 FULL-BRIDGE MODE In Full-Bridge mode, all four pins are used as outputs. An example of a full-bridge application is provided in Figure 19-8. In the Forward mode, the PxA pin is driven to its active state and the PxD pin is modulated, while the PxB and PxC pins are driven to their inactive state, as shown in Figure 19-9. In the Reverse mode, the PxC pin is driven to its active state and the PxB pin is modulated, while the PxA and PxD pins are driven to their inactive state, as shown in Figure 19-9. The PxA, PxB, PxC and PxD outputs are multiplexed with the port data latches. The associated TRIS bits must be cleared to configure the PxA, PxB, PxC and PxD pins as outputs. FIGURE 19-8: EXAMPLE OF FULL-BRIDGE APPLICATION V+ FET Driver PxA QA QC FET Driver PxB FET Driver Load FET Driver PxC QB QD VPxD  2010 Microchip Technology Inc. Preliminary DS39974A-page 279 PIC18F47J13 FAMILY FIGURE 19-9: Forward Mode Period PxA (2) EXAMPLE OF FULL-BRIDGE PWM OUTPUT Pulse Width PxB(2) PxC(2) PxD(2) (1) (1) Reverse Mode Period Pulse Width PxA(2) PxB(2) PxC(2) PxD(2) (1) (1) Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. The output signal is shown as active-high. DS39974A-page 280 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.4.2.1 Direction Change in Full-Bridge Mode In the Full-Bridge mode, the PxM1 bit in the CCPxCON register allows users to control the forward/reverse direction. When the application firmware changes this direction control bit, the module will change to the new direction on the next PWM cycle. A direction change is initiated in software by changing the PxM1 bit of the CCPxCON register. The following sequence occurs prior to the end of the current PWM period: • The modulated outputs (PxB and PxD) are placed in their inactive state. • The associated unmodulated outputs (PxA and PxC) are switched to drive in the opposite direction. • PWM modulation resumes at the beginning of the next period. For an illustration of this sequence, see Figure 19-10. The Full-Bridge mode does not provide a dead-band delay. As one output is modulated at a time, a dead-band delay is generally not required. There is a situation where a dead-band delay is required. This situation occurs when both of the following conditions are true: • The direction of the PWM output changes when the duty cycle of the output is at or near 100%. • The turn-off time of the power switch, including the power device and driver circuit, is greater than the turn-on time. Figure 19-11 shows an example of the PWM direction changing from forward to reverse at a near 100% duty cycle. In this example, at time t1, the PxA and PxD outputs become inactive, while the PxC output becomes active. Since the turn-off time of the power devices is longer than the turn-on time, a shoot-through current will flow through power devices, QC and QD (see Figure 19-8), for the duration of ‘t’. The same phenomenon will occur to power devices, QA and QB, for PWM direction change from reverse to forward. If changing PWM direction at high duty cycle is required for an application, two possible solutions for eliminating the shoot-through current are: • Reduce PWM duty cycle for one PWM period before changing directions. • Use switch drivers that can drive the switches off faster than they can drive them on. Other options to prevent shoot-through current may exist. FIGURE 19-10: Signal EXAMPLE OF PWM DIRECTION CHANGE Period(1) Period PxA (Active-High) PxB (Active-High) PxC (Active-High) PxD (Active-High) Pulse Width Note 1: 2: The direction bit, PxM1 of the CCPxCON register, is written any time during the PWM cycle. When changing directions, the PxA and PxC signals switch before the end of the current PWM cycle. The modulated PxB and PxD signals are inactive at this time. The length of this time is: (1/FOSC) • TMR2 Prescale Value. (2) Pulse Width  2010 Microchip Technology Inc. Preliminary DS39974A-page 281 PIC18F47J13 FAMILY FIGURE 19-11: EXAMPLE OF PWM DIRECTION CHANGE AT NEAR 100% DUTY CYCLE Forward Period t1 Reverse Period PxA PxB PxC PxD PW PW TON External Switch C TOFF External Switch D Potential Shoot-Through Current T = TOFF – TON Note 1: 2: 3: All signals are shown as active-high. TON is the turn-on delay of power switch, QC, and its driver. TOFF is the turn-off delay of power switch, QD, and its driver. 19.4.3 START-UP CONSIDERATIONS When any PWM mode is used, the application hardware must use the proper external pull-up and/or pull-down resistors on the PWM output pins. Note: When the microcontroller is released from Reset, all of the I/O pins are in the high-impedance state. The external circuits must keep the power switch devices in the OFF state until the microcontroller drives the I/O pins with the proper signal levels or activates the PWM output(s). pin output drivers. The completion of a full PWM cycle is indicated by the TMR2IF or TMR4IF bit of the PIR1 or PIR3 register being set as the second PWM period begins. 19.4.4 ENHANCED PWM AUTO-SHUTDOWN MODE The PWM mode supports an Auto-Shutdown mode that will disable the PWM outputs when an external shutdown event occurs. Auto-Shutdown mode places the PWM output pins into a predetermined state. This mode is used to help prevent the PWM from damaging the application. The auto-shutdown sources are selected using the ECCPxAS bits (ECCPxAS). A shutdown event may be generated by: • A logic ‘0’ on the pin that is assigned to the FLT0 input function • Comparator C1 • Comparator C2 • Setting the ECCPxASE bit in firmware A shutdown condition is indicated by the ECCPxASE (Auto-Shutdown Event Status) bit (ECCPxAS). If the bit is a ‘0’, the PWM pins are operating normally. If the bit is a ‘1’, the PWM outputs are in the shutdown state. The CCPxM bits of the CCPxCON register allow the user to choose whether the PWM output signals are active-high or active-low for each pair of PWM output pins (PxA/PxC and PxB/PxD). The PWM output polarities must be selected before the PWM pin output drivers are enabled. Changing the polarity configuration while the PWM pin output drivers are enabled is not recommended, since it may result in damage to the application circuits. The PxA, PxB, PxC and PxD output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pin output drivers at the same time as the Enhanced PWM modes may cause damage to the application circuit. The Enhanced PWM modes must be enabled in the proper Output mode and complete a full PWM cycle before enabling the PWM DS39974A-page 282 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY When a shutdown event occurs, two things happen: • The ECCPxASE bit is set to ‘1’. The ECCPxASE will remain set until cleared in firmware or an auto-restart occurs. (See Section 19.4.5 “Auto-Restart Mode”.) • The enabled PWM pins are asynchronously placed in their shutdown states. The PWM output pins are grouped into pairs (PxA/PxC and PxB/PxD). The state of each pin pair is determined by the PSSxAC and PSSxBD bits (ECCPxAS). Each pin pair may be placed into one of three states: • Drive logic ‘1’ • Drive logic ‘0’ • Tri-state (high-impedance) REGISTER 19-3: R/W-0 ECCPxASE bit 7 Legend: R = Readable bit -n = Value at POR bit 7 ECCPxAS: ECCP1/2/3 AUTO-SHUTDOWN CONTROL REGISTER (1, ACCESS FBEh; 2, FB8h; 3, BANKED F19h) R/W-0 R/W-0 ECCPxAS1 R/W-0 ECCPxAS0 R/W-0 PSSxAC1 R/W-0 PSSxAC0 R/W-0 PSSxBD1 R/W-0 PSSxBD0 bit 0 ECCPxAS2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ECCPxASE: ECCP Auto-Shutdown Event Status bit 1 = A shutdown event has occurred; ECCP outputs are in a shutdown state 0 = ECCP outputs are operating ECCPxAS: ECCP Auto-Shutdown Source Select bits 000 = Auto-shutdown is disabled 001 = Comparator, C1OUT, output is high 010 = Comparator, C2OUT, output is high 011 = Either comparator, C1OUT or C2OUT, is high 100 = VIL on FLT0 pin 101 = VIL on FLT0 pin or comparator, C1OUT, output is high 110 = VIL on FLT0 pin or comparator, C2OUT, output is high 111 = VIL on FLT0 pin or comparator, C1OUT, or comparator, C2OUT, is high PSSxAC: PxA and PxC Pins Shutdown State Control bits 00 = Drive pins, PxA and PxC, to ‘0’ 01 = Drive pins, PxA and PxC, to ‘1’ 1x = PxA and PxC pins tri-state PSSxBD: PxB and PxD Pins Shutdown State Control bits 00 = Drive pins, PxB and PxD, to ‘0’ 01 = Drive pins, PxB and PxD, to ‘1’ 1x = PxB and PxD pins tri-state bit 6-4 bit 3-2 bit 1-0 Note 1: The auto-shutdown condition is a level-based signal, not an edge-based signal. As long as the level is present, the auto-shutdown will persist. 2: Writing to the ECCPxASE bit is disabled while an auto-shutdown condition persists. 3: Once the auto-shutdown condition has been removed and the PWM restarted (either through firmware or auto-restart), the PWM signal will always restart at the beginning of the next PWM period.  2010 Microchip Technology Inc. Preliminary DS39974A-page 283 PIC18F47J13 FAMILY FIGURE 19-12: PWM AUTO-SHUTDOWN WITH FIRMWARE RESTART (PxRSEN = 0) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears ECCPxASE Cleared by Firmware PWM Resumes 19.4.5 AUTO-RESTART MODE The Enhanced PWM can be configured to automatically restart the PWM signal once the auto-shutdown condition has been removed. Auto-restart is enabled by setting the PxRSEN bit (ECCPxDEL). If auto-restart is enabled, the ECCPxASE bit will remain set as long as the auto-shutdown condition is active. When the auto-shutdown condition is removed, the ECCPxASE bit will be cleared via hardware and normal operation will resume. The module will wait until the next PWM period begins, however, before re-enabling the output pin. This behavior allows the auto-shutdown with auto-restart features to be used in applications based on the current mode of PWM control. FIGURE 19-13: PWM AUTO-SHUTDOWN WITH AUTO-RESTART ENABLED (PxRSEN = 1) PWM Period Shutdown Event ECCPxASE bit PWM Activity Normal PWM Start of PWM Period Shutdown Event Occurs Shutdown Event Clears PWM Resumes DS39974A-page 284 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.4.6 PROGRAMMABLE DEAD-BAND DELAY MODE FIGURE 19-14: In half-bridge applications, where all power switches are modulated at the PWM frequency, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on and the other turned off), both switches may be on for a short period until one switch completely turns off. During this brief interval, a very high current (shoot-through current) will flow through both power switches, shorting the bridge supply. To avoid this potentially destructive shoot-through current from flowing during switching, turning on either of the power switches is normally delayed to allow the other switch to completely turn off. In Half-Bridge mode, a digitally programmable, dead-band delay is available to avoid shoot-through current from destroying the bridge power switches. The delay occurs at the signal transition from the non-active state to the active state. For an illustration, see Figure 19-14. The lower seven bits of the associated ECCPxDEL register (Register 19-4) set the delay period in terms of microcontroller instruction cycles (TCY or 4 TOSC). EXAMPLE OF HALF-BRIDGE PWM OUTPUT Period Period Pulse Width PxA (2) td PxB(2) (1) td (1) (1) td = Dead-Band Delay Note 1: 2: At this time, the TMR2 register is equal to the PR2 register. Output signals are shown as active-high. FIGURE 19-15: EXAMPLE OF HALF-BRIDGE APPLICATIONS V+ Standard Half-Bridge Circuit (“Push-Pull”) FET Driver PxA + V Load + V - FET Driver PxB V-  2010 Microchip Technology Inc. Preliminary DS39974A-page 285 PIC18F47J13 FAMILY REGISTER 19-4: R/W-0 PxRSEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ECCPxDEL: ECCP1/2/3 ENHANCED PWM CONTROL REGISTER (1, ACCESS FBDh; 2, FB7h; 3, BANKED F18h) R/W-0 R/W-0 PxDC5 R/W-0 PxDC4 R/W-0 PxDC3 R/W-0 PxDC2 R/W-0 PxDC1 R/W-0 PxDC0 bit 0 PxDC6 PxRSEN: PWM Restart Enable bit 1 = Upon auto-shutdown, the ECCPxASE bit clears automatically once the shutdown event goes away; the PWM restarts automatically 0 = Upon auto-shutdown, ECCPxASE must be cleared by software to restart the PWM PxDC: PWM Delay Count bits PxDCn = Number of FOSC/4 (4 * TOSC) cycles between the scheduled time when a PWM signal should transition active and the actual time it does transition active. bit 6-0 19.4.7 PULSE STEERING MODE In Single Output mode, pulse steering allows any of the PWM pins to be the modulated signal. Additionally, the same PWM signal can simultaneously be available on multiple pins. Once the Single Output mode is selected (CCPxM = 11 and PxM = 00 of the CCPxCON register), the user firmware can bring out the same PWM signal to one, two, three or four output pins by setting the appropriate STR bits (PSTRxCON), as provided in Table 19-3. Note: The associated TRIS bits must be set to output (‘0’), to enable the pin output driver, in order to see the PWM signal on the pin. While the PWM Steering mode is active, the CCPxM bits (CCPxCON) select the PWM output polarity for the Px pins. The PWM auto-shutdown operation also applies to PWM Steering mode, as described in Section 19.4.4 “Enhanced PWM Auto-Shutdown Mode”. An auto-shutdown event will only affect pins that have PWM outputs enabled. DS39974A-page 286 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY REGISTER 19-5: R/W-0 CMPL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PSTRxCON: PULSE STEERING CONTROL (1, ACCESS FBFh; 2, FB9h; 3, BANKED F1Ah)(1) R/W-0 U-0 — R/W-0 STRSYNC R/W-0 STRD R/W-0 STRC R/W-0 STRB R/W-1 STRA bit 0 CMPL0 CMPL: Complementary Mode Output Assignment Steering Sync bits 1 = Modulated output pin toggles between PxA and PxB for each period 0 = Complementary output assignment is disabled; the STRD:STRA bits are used to determine Steering mode Unimplemented: Read as ‘0’ STRSYNC: Steering Sync bit 1 = Output steering update occurs on the next PWM period 0 = Output steering update occurs at the beginning of the instruction cycle boundary STRD: Steering Enable D bit 1 = PxD pin has the PWM waveform with polarity control from CCPxM 0 = PxD pin is assigned to a port pin STRC: Steering Enable C bit 1 = PxC pin has the PWM waveform with polarity control from CCPxM 0 = PxC pin is assigned to a port pin STRB: Steering Enable B bit 1 = PxB pin has the PWM waveform with polarity control from CCPxM 0 = PxB pin is assigned to a port pin STRA: Steering Enable A bit 1 = PxA pin has the PWM waveform with polarity control from CCPxM 0 = PxA pin is assigned to a port pin The PWM Steering mode is available only when the CCPxCON register bits, CCPxM = 11 and PxM = 00. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 287 PIC18F47J13 FAMILY FIGURE 19-16: STRA(2) PxA Signal CCPxM1 PORT Data(1) STRB(2) CCPxM0 PORT Data(1) 1 0 Output Pin 1 0 SIMPLIFIED STEERING BLOCK DIAGRAM 19.4.7.1 Steering Synchronization TRIS Output Pin The STRSYNC bit of the PSTRxCON register gives the user two choices for when the steering event will happen. When the STRSYNC bit is ‘0’, the steering event will happen at the end of the instruction that writes to the PSTRxCON register. In this case, the output signal at the Px pins may be an incomplete PWM waveform. This operation is useful when the user firmware needs to immediately remove a PWM signal from the pin. When the STRSYNC bit is ‘1’, the effective steering update will happen at the beginning of the next PWM period. In this case, steering on/off the PWM output will always produce a complete PWM waveform. Figure 19-17 and Figure 19-18 illustrate the timing diagrams of the PWM steering depending on the STRSYNC setting. STRC(2) CCPxM1 PORT Data(1) STRD (2) TRIS 1 0 TRIS Output Pin CCPxM0 PORT Data(1) 1 0 Output Pin TRIS Note 1: 2: Port outputs are configured as displayed when the CCPxCON register bits, PxM = 00 and CCP1M = 11. Single PWM output requires setting at least one of the STR bits. FIGURE 19-17: EXAMPLE OF STEERING EVENT AT END OF INSTRUCTION (STRSYNC = 0) PWM Period PWM STRn P1 PORT Data P1n = PWM PORT Data FIGURE 19-18: PWM STRn EXAMPLE OF STEERING EVENT AT BEGINNING OF INSTRUCTION (STRSYNC = 1) P1 PORT Data P1n = PWM PORT Data DS39974A-page 288 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 19.4.8 OPERATION IN POWER-MANAGED MODES In Sleep mode, all clock sources are disabled. Timer2 will not increment and the state of the module will not change. If the ECCPx pin is driving a value, it will continue to drive that value. When the device wakes up, it will continue from this state. If Two-Speed Start-ups are enabled, the initial start-up frequency from HFINTOSC and the postscaler may not be immediately stable. In PRI_IDLE mode, the primary clock will continue to clock the ECCPx module without change. will be set. The ECCPx will then be clocked from the internal oscillator clock source, which may have a different clock frequency than the primary clock. 19.4.9 EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their Reset states. This forces the ECCP module to reset to a state compatible with previous, non-enhanced CCP modules used on other PIC18 and PIC16 devices. 19.4.8.1 Operation with Fail-Safe Clock Monitor (FSCM) If the Fail-Safe Clock Monitor (FSCM) is enabled, a clock failure will force the device into the power-managed RC_RUN mode and the OSCFIF bit of the PIR2 register TABLE 19-4: File Name INTCON RCON PIR1 PIR2 PIR4 PIE1 PIE2 PIE4 IPR1 IPR2 IPR4 TRISB TRISC TRISE TMR1H TMR1L TMR2 TMR3H TMR3L TMR4 TMR6 TMR8 PR2 PR4 PR6 PR8 T1CON T2CON T3CON T4CON T6CON REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8 Bit 7 GIE/GIEH IPEN PMPIF OSCFIF CCP10IF PMPIE OSCFIE CCP10IE PMPIP OSCFIP CCP10IP TRISB7 TRISC7 Bit 6 PEIE/GIEL — ADIF CM2IF CCP9IF ADIE CM2IE CCP9IE ADIP CM2IP CCP9IP TRISB6 TRISC6 Bit 5 TMR0IE CM RC1IF CM1IF CCP8IF RC1IE CM1IE CCP8IE RC1IP CM1IP CCP8IP TRISB5 — — Bit 4 INT0IE RI TX1IF — CCP7IF TX1IE — CCP7IE TX1IP — CCP7IP TRISB4 — — Bit 3 RBIE TO SSP1IF BCL1IF CCP6IF SSP1IE BCL1IE CCP6IE SSP1IP BCL1IP CCP6IP TRISB3 — — Bit 2 TMR0IF PD CCP1IF HLVDIF CCP5IF CCP1IE HLVDIE CCP5IE CCP1IP HLVDIP CCP5IP TRISB2 TRISC2 TRISE2 Bit 1 INT0IF POR TMR2IF TMR3IF CCP4IF TMR2IE TMR3IE CCP4IE TMR2IP TMR3IP CCP4IP TRISB1 TRISC1 TRISE1 Bit 0 RBIF BOR TMR1IF CCP2IF CCP3IF TMR1IE CCP2IE CCP3IE TMR1IP CCP2IP CCP3IP TRISB0 TRISC0 TRISE0 REPU RDPU Timer1 Register High Byte Timer1 Register Low Byte Timer2 Register Timer3 Register High Byte Timer3 Register Low Byte Timer4 Register Timer6 Register Timer8 Register Timer2 Period Register Timer4 Period Register Timer6 Period Register Timer8 Period Register TMR1CS1 — TMR3CS1 — — TMR1CS0 T1CKPS1 T1CKPS0 T1OSCEN T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0 TMR3CS0 T3CKPS1 T4OUTPS3 T4OUTPS2 T6OUTPS3 T6OUTPS2 T3CKPS0 T3OSCEN T4OUTPS1 T4OUTPS0 T6OUTPS1 T6OUTPS0 T1SYNC TMR2ON T3SYNC TMR4ON TMR6ON RD16 T2CKPS1 RD16 T4CKPS1 T6CKPS1 TMR1ON T2CKPS0 TMR3ON T4CKPS0 T6CKPS0  2010 Microchip Technology Inc. Preliminary DS39974A-page 289 PIC18F47J13 FAMILY TABLE 19-4: File Name T8CON CCPR1H CCPR1L CCPR2H CCPR2L CCPR3H CCPR3L CCP1CON CCP2CON CCP3CON REGISTERS ASSOCIATED WITH ECCP1/2/3 MODULE AND TIMER1/2/3/4/6/8 (CONTINUED) Bit 7 — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TMR8ON Bit 1 T8CKPS1 Bit 0 T8CKPS0 T8OUTPS3 T8OUTPS2 T8OUTPS1 T8OUTPS0 Capture/Compare/PWM Register 1 High Byte Capture/Compare/PWM Register 1 Low Byte Capture/Compare/PWM Register 2 High Byte Capture/Compare/PWM Register 2 Low Byte Capture/Compare/PWM Register 3 High Byte Capture/Compare/PWM Register 3 Low Byte P1M1 P1M0 DC1B1 DC1B0 P2M1 P2M0 DC2B1 DC2B0 P3M1 P3M0 DC3B1 DC3B0 CCP1M3 CCP2M3 CCP3M3 CCP1M2 CCP2M2 CCP3M2 CCP1M1 CCP2M1 CCP3M1 CCP1M0 CCP2M0 CCP3M0 DS39974A-page 290 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.0 MASTER SYNCHRONOUS SERIAL PORT (MSSP) MODULE All of the MSSP1 module related SPI and I2C I/O functions are hard-mapped to specific I/O pins. For MSSP2 functions: • SPI I/O functions (SDO2, SDI2, SCK2 and SS2) are all routed through the Peripheral Pin Select (PPS) module. These functions may be configured to use any of the RPn remappable pins, as described in Section 10.7 “Peripheral Pin Select (PPS)”. • I2C functions (SCL2 and SDA2) have fixed pin locations. On all PIC18F47J13 family devices, the SPI DMA capability can only be used in conjunction with MSSP2. The SPI DMA feature is described in Section 20.4 “SPI DMA Module”. Note: Throughout this section, generic references to an MSSP module in any of its operating modes may be interpreted as being equally applicable to MSSP1 or MSSP2. Register names and module I/O signals use the generic designator ‘x’ to indicate the use of a numeral to distinguish a particular module when required. Control bit names are not individuated. The Master Synchronous Serial Port (MSSP) module is a serial interface, useful for communicating with other peripheral or microcontroller devices. These peripheral devices include serial EEPROMs, shift registers, display drivers and A/D Converters. 20.1 Master SSP (MSSP) Module Overview The MSSP module can operate in one of two modes: • Serial Peripheral Interface (SPI) • Inter-Integrated Circuit (I2C™) - Full Master mode - Slave mode (with general address call) The I2C interface supports the following modes in hardware: • Master mode • Multi-Master mode • Slave mode with 5-bit and 7-bit address masking (with address masking for both 10-bit and 7-bit addressing) All members of the PIC18F47J13 family have two MSSP modules, designated as MSSP1 and MSSP2. The modules operate independently: • PIC18F4XJ13 devices – Both modules can be configured for either I2C or SPI communication • PIC18F2XJ13 devices: - MSSP1 can be used for either I2C or SPI communication - MSSP2 can be used only for SPI communication  2010 Microchip Technology Inc. Preliminary DS39974A-page 291 PIC18F47J13 FAMILY 20.2 Control Registers FIGURE 20-1: Each MSSP module has three associated control registers. These include a status register (SSPxSTAT) and two control registers (SSPxCON1 and SSPxCON2). The use of these registers and their individual Configuration bits differs significantly depending on whether the MSSP module is operated in SPI or I2C mode. Additional details are provided under the individual sections. Note: In devices with more than one MSSP module, it is very important to pay close attention to the SSPxCON register names. SSP1CON1 and SSP1CON2 control different operational aspects of the same module, while SSP1CON1 and SSP2CON1 control the same features for two different modules. MSSPx BLOCK DIAGRAM (SPI MODE) Internal Data Bus Read SSPxBUF reg Write SDIx SSPxSR reg SDOx bit 0 Shift Clock SSx SSx Control Enable Edge Select 2 Clock Select SSPM SMP:CKE 4 (TMR2 Output 2 2 Edge Select 20.3 SPI Mode The SPI mode allows 8 bits of data to be synchronously transmitted and received simultaneously. All four modes of SPI are supported. When MSSP2 is used in SPI mode, it can optionally be configured to work with the SPI DMA submodule described in Section 20.4 “SPI DMA Module”. To accomplish communication, typically three pins are used: • Serial Data Out (SDOx) – RC5/SDO1/RP16 or SDO2/Remappable • Serial Data In (SDIx) – RC4/SDI1/SDA1/RP15 or SDI2/Remappable • Serial Clock (SCKx) – RC3/SCK1/SCL1/RP14 or SCK2/Remappable Additionally, a fourth pin may be used when in a Slave mode of operation: • Slave Select (SSx) – RA5/AN4/C1INC/SS1/ HLVDIN/RP2 or SS2/Remappable Figure 20-1 depicts the block diagram of the MSSP module when operating in SPI mode. SCKx ) Prescaler TOSC 4, 8, 16, 64 Data to TXx/RXx in SSPxSR TRIS bit Note: Only port I/O names are used in this diagram for the sake of brevity. Refer to the text for a full list of multiplexed functions. DS39974A-page 292 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSPx Control Register 1 (SSPxCON1) • MSSPx Status Register (SSPxSTAT) • Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSPx Shift Register (SSPxSR) – Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation. The SSPxCON1 register is readable and writable. The lower six bits of the SSPxSTAT are read-only. The upper two bits of the SSPxSTAT are read/write. SSPxSR is the shift register used for shifting data in or out. SSPxBUF is the buffer register to which data bytes are written to or read from. In receive operations, SSPxSR and SSPxBUF together, create a double-buffered receiver. When SSPxSR receives a complete byte, it is transferred to SSPxBUF and the SSPxIF interrupt is set. During transmission, the SSPxBUF is not double-buffered. A write to SSPxBUF will write to both SSPxBUF and SSPxSR. Note: Because the SSPxBUF register is double-buffered, using read-modify-write instructions such as BCF, COMF, etc., will not work. Similarly, when debugging under an in-circuit debugger, performing actions that cause reads of SSPxBUF (mouse hovering, watch, etc.) can consume data that the application code was expecting to receive. REGISTER 20-1: R/W-1 SMP bit 7 Legend: R = Readable bit -n = Value at POR bit 7 SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE) (ACCESS 1, FC7h; 2, F73h) R-1 D/A R-1 P R-1 S R-1 R/W R-1 UA R-1 BF bit 0 (1) R/W-1 CKE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown SMP: Sample bit SPI Master mode: 1 = Input data sampled at the end of data output time 0 = Input data sampled at the middle of data output time SPI Slave mode: SMP must be cleared when SPI is used in Slave mode. CKE: SPI Clock Select bit(1) 1 = Transmit occurs on transition from active to Idle clock state 0 = Transmit occurs on transition from Idle to active clock state D/A: Data/Address bit Used in I2C™ mode only. P: Stop bit Used in I2C mode only; this bit is cleared when the MSSP module is disabled, SSPEN is cleared. S: Start bit Used in I2C mode only. R/W: Read/Write Information bit Used in I2C mode only. UA: Update Address bit Used in I2C mode only. BF: Buffer Full Status bit 1 = Receive complete, SSPxBUF is full 0 = Receive not complete, SSPxBUF is empty Polarity of the clock state is set by the CKP bit (SSPxCON1). bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. Preliminary DS39974A-page 293 PIC18F47J13 FAMILY REGISTER 20-2: R/W-0 WCOL bit 7 Legend: R = Readable bit -n = Value at POR bit 7 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown SSPxCON1: MSSPx CONTROL REGISTER 1 (SPI MODE) (1, ACCESS FC6h; 2, F72h) R/W-0 SSPEN (2) R/C-0 SSPOV (1) R/W-0 CKP R/W-0 SSPM3 (3) R/W-0 SSPM2 (3) R/W-0 SSPM1 (3) R/W-0 SSPM0(3) bit 0 WCOL: Write Collision Detect bit 1 = The SSPxBUF register is written while it is still transmitting the previous word (must be cleared in software) 0 = No collision SSPOV: Receive Overflow Indicator bit(1) SPI Slave mode: 1 = A new byte is received while the SSPxBUF register is still holding the previous data. In case of overflow, the data in SSPxSR is lost. Overflow can only occur in Slave mode. The user must read the SSPxBUF, even if only transmitting data, to avoid setting overflow (must be cleared in software). 0 = No overflow SSPEN: Master Synchronous Serial Port Enable bit(2) 1 = Enables serial port and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables serial port and configures these pins as I/O port pins CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level 0 = Idle state for clock is a low level SSPM: Master Synchronous Serial Port Mode Select bits(3) 0101 = SPI Slave mode, clock = SCKx pin; SSx pin control disabled, SSx can be used as I/O pin 0100 = SPI Slave mode, clock = SCKx pin; SSx pin control enabled 0011 = SPI Master mode, clock = TMR2 output/2 0010 = SPI Master mode, clock = FOSC/64 0001 = SPI Master mode, clock = FOSC/16 1010 = SPI Master mode, clock = FOSC/8 0000 = SPI Master mode, clock = FOSC/4 In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. When enabled, this pin must be properly configured as input or output. Bit combinations not specifically listed here are either reserved or implemented in I2C™ mode only. bit 6 bit 5 bit 4 bit 3-0 Note 1: 2: 3: DS39974A-page 294 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1 and SSPxSTAT). These control bits allow the following to be specified: • • • • Master mode (SCKx is the clock output) Slave mode (SCKx is the clock input) Clock Polarity (Idle state of SCKx) Data Input Sample Phase (middle or end of data output time) • Clock Edge (output data on rising/falling edge of SCKx) • Clock Rate (Master mode only) • Slave Select mode (Slave mode only) Each MSSP module consists of a Transmit/Receive Shift register (SSPxSR) and a Buffer register (SSPxBUF). The SSPxSR shifts the data in and out of the device, MSb first. The SSPxBUF holds the data that was written to the SSPxSR until the received data is ready. Once the 8 bits of data have been received, that byte is moved to the SSPxBUF register. Then, the Buffer Full (BF) detect bit (SSPxSTAT) and the interrupt flag bit, SSPxIF, are set. This double-buffering of the received data (SSPxBUF) allows the next byte to start reception before reading the data that was just received. Any write to the SSPxBUF register during transmission or reception of data will be ignored and the Write Collision Detect bit, WCOL (SSPxCON1), will be set. User software must clear the WCOL bit so that it can be determined if the following write(s) to the SSPxBUF register completed successfully. Note: When the application software is expecting to receive valid data, the SSPxBUF should be read before the next byte of transfer data is written to the SSPxBUF. Application software should follow this process even when the current contents of SSPxBUF are not important. The Buffer Full bit, BF (SSPxSTAT), indicates when SSPxBUF has been loaded with the received data (transmission is complete). When the SSPxBUF is read, the BF bit is cleared. This data may be irrelevant if the SPI is only a transmitter. Generally, the MSSP interrupt is used to determine when the transmission/reception has completed. If the interrupt method is not going to be used, then software polling can be done to ensure that a write collision does not occur. Example 20-1 provides the loading of the SSPxBUF (SSPxSR) for data transmission. The SSPxSR is not directly readable or writable and can only be accessed by addressing the SSPxBUF register. Additionally, the SSPxSTAT register indicates the various status conditions. 20.3.3 OPEN-DRAIN OUTPUT OPTION The drivers for the SDOx output and SCKx clock pins can be optionally configured as open-drain outputs. This feature allows the voltage level on the pin to be pulled to a higher level through an external pull-up resistor, provided the SDOx or SCKx pin is not multiplexed with an ANx analog function. This allows the output to communicate with external circuits without the need for additional level shifters. For more information, see Section 10.1.4 “Open-Drain Outputs”. The open-drain output option is controlled by the SPI2OD and SPI1OD bits (ODCON3). Setting an SPIxOD bit configures both the SDOx and SCKx pins for the corresponding open-drain operation. EXAMPLE 20-1: LOOP BTFSS BRA MOVF MOVWF MOVF MOVWF LOADING THE SSP1BUF (SSP1SR) REGISTER SSP1STAT, BF LOOP SSP1BUF, W RXDATA TXDATA, W SSP1BUF ;Has data been received (transmit complete)? ;No ;WREG reg = contents of SSP1BUF ;Save in user RAM, if data is meaningful ;W reg = contents of TXDATA ;New data to xmit  2010 Microchip Technology Inc. Preliminary DS39974A-page 295 PIC18F47J13 FAMILY 20.3.4 ENABLING SPI I/O To enable the serial port, MSSP Enable bit, SSPEN (SSPxCON1), must be set. To reset or reconfigure SPI mode, clear the SSPEN bit, re-initialize the SSPxCON1 registers and then set the SSPEN bit. This configures the SDIx, SDOx, SCKx and SSx pins as serial port pins. For the pins to behave as the serial port function, the appropriate TRISx bits, PCFGx bits and Peripheral Pin Select registers (if using MSSP2) should be correctly initialized prior to setting the SSPEN bit. A typical SPI serial port initialization process follows: • Initialize the ODCON3 register (optional open-drain output control) • Initialize the remappable pin functions (if using MSSP2, see Section 10.7 “Peripheral Pin Select (PPS)”) • Initialize the SCKx/LAT value to the desired Idle SCKx level (if master device) • Initialize the SCKx/PCFGx bit (if in Slave mode and multiplexed with the ANx function) • Initialize the SCKx/TRISx bit as an output (Master mode) or input (Slave mode) • Initialize the SDIx/PCFGx bit (if SDIx is multiplexed with the ANx function) • Initialize the SDIx/TRISx bit • Initialize the SSx/PCFG bit (if in Slave mode and multiplexed with the ANx function) • Initialize the SSx/TRISx bit (Slave modes) • Initialize the SDOx/TRISx bit • Initialize the SSPxSTAT register • Initialize the SSPxCON1 register • Set the SSPEN bit to enable the module Any MSSP1 serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. If individual MSSP2 serial port functions will not be used, they may be left unmapped. Note: When MSSP2 is used in SPI Master mode, the SCK2 function must be configured as both an output and an input in the PPS module. SCK2 must be initialized as an output pin (by writing 0x0A to one of the RPORx registers). Additionally, SCK2IN must also be mapped to the same pin by initializing the RPINR22 register. Failure to initialize SCK2/SCK2IN as both output and input will prevent the module from receiving data on the SDI2 pin, as the module uses the SCK2IN signal to latch the received data. 20.3.5 TYPICAL CONNECTION Figure 20-2 illustrates a typical connection between two microcontrollers. The master controller (Processor 1) initiates the data transfer by sending the SCKx signal. Data is shifted out of both shift registers on their programmed clock edge and latched on the opposite edge of the clock. Both processors should be programmed to the same Clock Polarity (CKP), then both controllers would send and receive data at the same time. Whether the data is meaningful (or dummy data) depends on the application software. This leads to three scenarios for data transmission: • Master sends valid data–Slave sends dummy data • Master sends valid data–Slave sends valid data • Master sends dummy data–Slave sends valid data FIGURE 20-2: SPI MASTER/SLAVE CONNECTION SPI Slave SSPM = 010xb SDOx SDIx SPI Master SSPM = 00xxb Serial Input Buffer (SSPxBUF) Serial Input Buffer (SSPxBUF) Shift Register (SSPxSR) MSb LSb SDIx SDOx Shift Register (SSPxSR) MSb LSb SCKx PROCESSOR 1 Serial Clock SCKx PROCESSOR 2 DS39974A-page 296 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.3.6 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 2, Figure 20-2) is to broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be disabled (programmed as an input). The SSPxSR register will continue to shift in the signal present on the SDIx pin at the programmed clock rate. As each byte is received, it will be loaded into the SSPxBUF register as if it is a normal received byte (interrupts and status bits are appropriately set). This could be useful in receiver applications as a “Line Activity Monitor” mode. Note: To avoid lost data in Master mode, a read of the SSPxBUF must be performed to clear the Buffer Full (BF) detect bit (SSPxSTAT) between each transmission. Figure 20-3, Figure 20-5 and Figure 20-6, where the Most Significant Byte (MSB) is transmitted first. In Master mode, the SPI clock rate (bit rate) is user-programmable to be one of the following: • • • • • FOSC/4 (or TCY) FOSC/8 (or 2 • TCY) FOSC/16 (or 4 • TCY) FOSC/64 (or 16 • TCY) Timer2 output/2 When using the Timer2 output/2 option, the Period Register 2 (PR2) can be used to determine the SPI bit rate. However, only PR2 values of 0x01 to 0xFF are valid in this mode. Figure 20-3 illustrates the waveforms for Master mode. When the CKE bit is set, the SDOx data is valid before there is a clock edge on SCKx. The change of the input sample is shown based on the state of the SMP bit. The time when the SSPxBUF is loaded with the received data is shown. The CKP is selected by appropriately programming the CKP bit (SSPxCON1). This then, would give waveforms for SPI communication, as illustrated in FIGURE 20-3: Write to SSPxBUF SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) SDOx (CKE = 0) SDOx (CKE = 1) SDIx (SMP = 0) Input Sample (SMP = 0) SDIx (SMP = 1) Input Sample (SMP = 1) SSPxIF SSPxSR to SSPxBUF SPI MODE WAVEFORM (MASTER MODE) 4 Clock Modes bit 7 bit 7 bit 6 bit 6 bit 5 bit 5 bit 4 bit 4 bit 3 bit 3 bit 2 bit 2 bit 1 bit 1 bit 0 bit 0 bit 7 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2  2010 Microchip Technology Inc. Preliminary DS39974A-page 297 PIC18F47J13 FAMILY 20.3.7 SLAVE MODE In Slave mode, the data is transmitted and received as the external clock pulses appear on SCKx. When the last bit is latched, the SSPxIF interrupt flag bit is set. While in Slave mode, the external clock is supplied by the external clock source on the SCKx pin. This external clock must meet the minimum high and low times as specified in the electrical specifications. While in Sleep mode, the slave can transmit/receive data. When a byte is received, the device can be configured to wake-up from Sleep. transmitted byte and becomes a floating output. External pull-up/pull-down resistors may be desirable depending on the application. Note 1: When the SPI is in Slave mode with p in control enabled the SSx (SSPxCON1 = 0100), the SPI module will reset if the SSx pin is set to VDD. 2: If the SPI is used in Slave mode with CKE set, then the SSx pin control must be enabled. When the SPI module resets, the bit counter is forced to ‘0’. This can be done by either forcing the SSx pin to a high level or clearing the SSPEN bit. To emulate two-wire communication, the SDOx pin can be connected to the SDIx pin. When the SPI needs to operate as a receiver, the SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDIx function) since it cannot create a bus conflict. 20.3.8 SLAVE SELECT SYNCHRONIZATION The SSx pin allows a Synchronous Slave mode. The SPI must be in Slave mode with the SSx pin control enabled (SSPxCON1 = 04h). When the SSx pin is low, transmission and reception are enabled and the SDOx pin is driven. When the SSx pin goes high, the SDOx pin is no longer driven, even if in the middle of a FIGURE 20-4: SSx SLAVE SYNCHRONIZATION WAVEFORM SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 bit 6 bit 7 bit 0 SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 0 bit 7 bit 7 Next Q4 Cycle after Q2 DS39974A-page 298 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY FIGURE 20-5: SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 0) bit 7 bit 0 Next Q4 Cycle after Q2 FIGURE 20-6: SSx Not Optional SCKx (CKP = 0 CKE = 1) SCKx (CKP = 1 CKE = 1) Write to SSPxBUF SDOx SDIx (SMP = 0) Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 0 Next Q4 Cycle after Q2  2010 Microchip Technology Inc. Preliminary DS39974A-page 299 PIC18F47J13 FAMILY 20.3.9 OPERATION IN POWER-MANAGED MODES 20.3.11 BUS MODE COMPATIBILITY In SPI Master mode, module clocks may be operating at a different speed than when in Full-Power mode. In the case of Sleep mode, all clocks are Halted. In Idle modes, a clock is provided to the peripherals. That clock can be from the primary clock source, the secondary clock (Timer1 oscillator) or the INTOSC source. See Section 3.3 “Clock Sources and Oscillator Switching” for additional information. In most cases, the speed that the master clocks SPI data is not important; however, this should be evaluated for each system. If MSSP interrupts are enabled, they can wake the controller from Sleep mode, or one of the Idle modes, when the master completes sending data. If an exit from Sleep or Idle mode is not desired, MSSP interrupts should be disabled. If the Sleep mode is selected, all module clocks are Halted and the transmission/reception will remain in that state until the device wakes. After the device returns to Run mode, the module will resume transmitting and receiving data. In SPI Slave mode, the SPI Transmit/Receive Shift register operates asynchronously to the device. This allows the device to be placed in any power-managed mode and data to be shifted into the SPI Transmit/Receive Shift register. When all 8 bits have been received, the MSSPx interrupt flag bit will be set, and if enabled, will wake the device. Table 20-1 provides the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. TABLE 20-1: SPI BUS MODES Control Bits State CKP 0 0 1 1 CKE 1 0 1 0 Standard SPI Mode Terminology 0, 0 0, 1 1, 0 1, 1 There is also an SMP bit, which controls when the data is sampled. 20.3.12 SPI CLOCK SPEED AND MODULE INTERACTIONS Because MSSP1 and MSSP2 are independent modules, they can operate simultaneously at different data rates. Setting the SSPM bits of the SSPxCON1 register determines the rate for the corresponding module. An exception is when both modules use Timer2 as a time base in Master mode. In this instance, any changes to the Timer2 module’s operation will affect both MSSP modules equally. If different bit rates are required for each module, the user should select one of the other three time base options for one of the modules. 20.3.10 EFFECTS OF A RESET A Reset disables the MSSP modules and terminates the current transfer. DS39974A-page 300 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY TABLE 20-2: Name INTCON PIR1 PIE1 IPR1 PIR3 PIE3 IPR3 TRISB TRISC TRISD SSP1BUF SSPxCON1 SSPxSTAT SSP2BUF ODCON3(1) REGISTERS ASSOCIATED WITH SPI OPERATION Bit 7 GIE/GIEH PMPIF (2) (2) Bit 6 PEIE/GIEL ADIF ADIE ADIP BCL2IF BCL2IE BCL2IP TRISB6 TRISC6 TRISD6 SSPOV CKE — Bit 5 TMR0IE RC1IF RC1IE RC1IP RC2IF RC2IE RC2IP TRISB5 — TRISD5 SSPEN D/A — Bit 4 INT0IE TX1IF TX1IE TX1IP TX2IF TX2IE TX2IP TRISB4 — TRISD4 CKP P — Bit 3 RBIE SSP1IF SSP1IE SSP1IP TMR4IF TMR4IE TMR4IP TRISB3 — TRISD3 SSPM3 S — Bit 2 TMR0IF CCP1IF CCP1IE CCP1IP CTMUIF CTMUIE CTMUIP TRISB2 TRISC2 TRISD2 SSPM2 R/W — Bit 1 INT0IF TMR2IF TMR2IE TMR2IP TMR3GIF TMR3GIE TMR3GIP TRISB1 TRISC1 TRISD1 SSPM1 UA SPI2OD Bit 0 RBIF TMR1IF TMR1IE TMR1IP RTCCIF RTCCIE RTCCIP TRISB0 TRISC0 TRISD0 SSPM0 BF SPI1OD PMPIE PMPIP(2) SSP2IF SSP2IE SSP2IP TRISB7 TRISC7 TRISD7 WCOL SMP CTMUDS MSSP1 Receive Buffer/Transmit Register MSSP2 Receive Buffer/Transmit Register Legend: Shaded cells are not used by the MSSPx module in SPI mode. Note 1: Configuration SFR overlaps with default SFR at this address; available only when WDTCON = 1. 2: These bits are only available on 44-pin devices.  2010 Microchip Technology Inc. Preliminary DS39974A-page 301 PIC18F47J13 FAMILY 20.4 SPI DMA MODULE 20.4.3 The SPI DMA module contains control logic to allow the MSSP2 module to perform SPI direct memory access transfers. This enables the module to quickly transmit or receive large amounts of data with relatively little CPU intervention. When the SPI DMA module is used, MSSP2 can directly read and write to general purpose SRAM. When the SPI DMA module is not enabled, MSSP2 functions normally, but without DMA capability. The SPI DMA module is composed of control logic, a Destination Receive Address Pointer, a Transmit Source Address Pointer, an interrupt manager and a Byte Count register for setting the size of each DMA transfer. The DMA module may be used with all SPI Master and Slave modes, and supports both half-duplex and full-duplex transfers. IDLE AND SLEEP CONSIDERATIONS The SPI DMA module remains fully functional when the microcontroller is in Idle mode. During normal Sleep, the SPI DMA module is not functional and should not be used. To avoid corrupting a transfer, user firmware should be careful to make certain that pending DMA operations are complete by polling the DMAEN bit in the DMACON1 register prior to putting the microcontroller into Sleep. In SPI Slave modes, the MSSP2 module is capable of transmitting and/or receiving one byte of data while in Sleep mode. This allows the SSP2IF flag in the PIR3 register to be used as a wake-up source. When the DMAEN bit is cleared, the SPI DMA module is effectively disabled, and the MSSP2 module functions normally, but without DMA capabilities. If the DMAEN bit is clear prior to entering Sleep, it is still possible to use the SSP2IF as a wake-up source without any data loss. Neither MSSP2 nor the SPI DMA module will provide any functionality in Deep Sleep. Upon exiting from Deep Sleep, all of the I/O pins, MSSP2 and SPI DMA related registers will need to be fully re-initialized before the SPI DMA module can be used again. 20.4.1 I/O PIN CONSIDERATIONS When enabled, the SPI DMA module uses the MSSP2 module. All SPI input and output signals, related to MSSP2, are routed through the Peripheral Pin Select module. The appropriate initialization procedure, as described in Section 20.4.6 “Using the SPI DMA Module”, will need to be followed prior to using the SPI DMA module. The output pins assigned to the SDO2 and SCK2 functions can optionally be configured as open-drain outputs, such as for level shifting operations mentioned in the same section. 20.4.4 REGISTERS 20.4.2 RAM TO RAM COPY OPERATIONS The SPI DMA engine is enabled and controlled by the following Special Function Registers: • DMACON1 • TXADDRH • RXADDRH • DMABCH • DMACON2 • TXADDRL • RXADDRL • DMABCL Although the SPI DMA module is primarily intended to be used for SPI communication purposes, the module can also be used to perform RAM to RAM copy operations. To do this, configure the module for Full-Duplex Master mode operation, but assign the SDO2 output and SDI2 input functions onto the same RPn pin in the PPS module. Also assign SCK2 out and SCK2 in onto the same RPn pin (a different pin than used for SDO2 and SDI2). This will allow the module to operate in Loopback mode, providing RAM copy capability. DS39974A-page 302 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.4.4.1 DMACON1 The DMACON1 register is used to select the main operating mode of the SPI DMA module. The SSCON1 and SSCON0 bits are used to control the slave select pin. When MSSP2 is used in SPI Master mode with the SPI DMA module, SSDMA can be controlled by the DMA module as an output pin. If MSSP2 will be used to communicate with an SPI slave device that needs the SSx pin to be toggled periodically, the SPI DMA hardware can automatically be used to deassert SSx between each byte, every two bytes or every four bytes. Alternatively, user firmware can manually generate slave select signals with normal general purpose I/O pins, if required by the slave device(s). When the TXINC bit is set, the TXADDR register will automatically increment after each transmitted byte. Automatic transmit address increment can be disabled by clearing the TXINC bit. If the automatic transmit address increment is disabled, each byte which is output on SDO2, will be the same (the contents of the SRAM pointed to by the TXADDR register) for the entire DMA transaction. When the RXINC bit is set, the RXADDR register will automatically increment after each received byte. Automatic receive address increment can be disabled by clearing the RXINC bit. If RXINC is disabled in Full-Duplex or Half-Duplex Receive modes, all incoming data bytes on SDI2 will overwrite the same memory location pointed to by the RXADDR register. After the SPI DMA transaction has completed, the last received byte will reside in the memory location pointed to by the RXADDR register. The SPI DMA module can be used for either half-duplex receive only communication, half-duplex transmit only communication or full-duplex simultaneous transmit and receive operations. All modes are available for both SPI master and SPI slave configurations. The DUPLEX0 and DUPLEX1 bits can be used to select the desired operating mode. The behavior of the DLYINTEN bit varies greatly depending on the SPI operating mode. For example behavior for each of the modes, see Figure 20-3 through Figure 20-6. SPI Slave mode, DLYINTEN = 1: In this mode, an SSP2IF interrupt will be generated during a transfer if the time between successful byte transmission events is longer than the value set by the DLYCYC bits in the DMACON2 register. This interrupt allows slave firmware to know that the master device is taking an unusually large amount of time between byte transmissions. For example, this information may be useful for implementing application defined communication protocols involving time-outs if the bus remains Idle for too long. When DLYINTEN = 1, the DLYCYC interrupts occur normally according to the selected setting. SPI Slave mode, DLYINTEN = 0: In this mode, the time-out based interrupt is disabled. No additional SSP2IF interrupt events will be generated by the SPI DMA module, other than those indicated by the INTLVL bits in the DMACON2 register. In this mode, always set DLYCYC = 0000. SPI Master mode, DLYINTEN = 0: The DLYCYC bits in the DMACON2 register determine the amount of additional inter-byte delay, which is added by the SPI DMA module during a transfer. The Master mode SS2 output feature may be used. SPI Master mode, DLYINTEN = 1: The amount of hardware overhead is slightly reduced in this mode, and the minimum inter-byte delay is 8 TCY for FOSC/4, 9 TCY for FOSC/16 and 15 TCY for FOSC/64. This mode can potentially be used to obtain slightly higher effective SPI bandwidth. In this mode, the SS2 control feature cannot be used, and should always be disabled (DMACON1 = 00). Additionally, the interrupt generating hardware (used in Slave mode) remains active. To avoid extraneous SSP2IF interrupt events, set the DMACON2 delay bits, DLYCYC = 1111, and ensure that the SPI serial clock rate is no slower than FOSC/64. In SPI Master modes, the DMAEN bit is used to enable the SPI DMA module and to initiate an SPI DMA transaction. After user firmware sets the DMAEN bit, the DMA hardware will begin transmitting and/or receiving data bytes according to the configuration used. In SPI Slave modes, setting the DMAEN bit will finish the initialization steps needed to prepare the SPI DMA module for communication (which still must be initiated by the master device). To avoid possible data corruption, once the DMAEN bit is set, user firmware should not attempt to modify any of the MSSP2 or SPI DMA related registers, with the exception of the INTLVL bits in the DMACON2 register. If user firmware wants to Halt an ongoing DMA transaction, the DMAEN bit can be manually cleared by the firmware. Clearing the DMAEN bit while a byte is currently being transmitted will not immediately Halt the byte in progress. Instead, any byte currently in progress will be completed before the MSSP2 and SPI DMA modules go back to their Idle conditions. If user firmware clears the DMAEN bit, the TXADDR, RXADDR and DMABC registers will no longer update, and the DMA module will no longer make any additional read or writes to SRAM; therefore, state information can be lost.  2010 Microchip Technology Inc. Preliminary DS39974A-page 303 PIC18F47J13 FAMILY REGISTER 20-3: R/W-0 SSCON1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DMACON1: DMA CONTROL REGISTER 1 (ACCESS F88h) R/W-0 R/W-0 TXINC R/W-0 RXINC R/W-0 DUPLEX1 R/W-0 DUPLEX0 R/W-0 DLYINTEN R/W-0 DMAEN bit 0 SSCON0 SSCON: SSDMA Output Control bits (Master modes only) 11 = SSDMA is asserted for the duration of 4 bytes; DLYINTEN is always reset low 01 = SSDMA is asserted for the duration of 2 bytes; DLYINTEN is always reset low 10 = SSDMA is asserted for the duration of 1 byte; DLYINTEN is always reset low 00 = SSDMA is not controlled by the DMA module; the DLYINTEN bit is software programmable TXINC: Transmit Address Increment Enable bit Allows the transmit address to increment as the transfer progresses. 1 = The transmit address is to be incremented from the initial value of TXADDR 0 = The transmit address is always set to the initial value of TXADDR RXINC: Receive Address Increment Enable bit Allows the receive address to increment as the transfer progresses. 1 = The received address is to be incremented from the intial value of RXADDR 0 = The received address is always set to the initial value of RXADDR DUPLEX: Transmit/Receive Operating Mode Select bits 10 = SPI DMA operates in Full-Duplex mode; data is simultaneously transmitted and received 01 = DMA operates in Half-Duplex mode; data is transmitted only 00 = DMA operates in Half-Duplex mode; data is received only DLYINTEN: Delay Interrupt Enable bit Enables the interrupt to be invoked after the number of TCY cycles specified in DLYCYC has elapsed from the latest completed transfer. 1 = The interrupt is enabled; SSCON must be set to ‘00’ 0 = The interrupt is disabled DMAEN: DMA Operation Start/Stop bit This bit is set by the users’ software to start the DMA operation. It is reset back to zero by the DMA engine when the DMA operation is completed or aborted. 1 = DMA is in session 0 = DMA is not in session bit 5 bit 4 bit 3-2 bit 1 bit 0 DS39974A-page 304 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.4.4.2 DMACON2 The DMACON2 register contains control bits for controlling interrupt generation and inter-byte delay behavior. The INTLVL bits are used to select when an SSP2IF interrupt should be generated. The function of the DLYCYC bits depends on the SPI operating mode (Master/Slave), as well as the DLYINTEN setting. In SPI Master mode, the DLYCYC bits can be used to control how much time the module will Idle between bytes in a transfer. By default, the hardware requires a minimum delay of 8 TCY for FOSC/4, 9 TCY for FOSC/16 and 15 TCY for FOSC/64. An additional delay can be added with the DLYCYC bits. In SPI Slave modes, the DLYCYC bits may optionally be used to trigger an additional time-out based interrupt. REGISTER 20-4: R/W-0 DLYCYC3 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 DMACON2: DMA CONTROL REGISTER 2 (ACCESS F86h) R/W-0 R/W-0 DLYCYC1 R/W-0 DLYCYC0 R/W-0 INTLVL3 R/W-0 INTLVL2 R/W-0 INTLVL1 R/W-0 INTLVL0 bit 0 DLYCYC2 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DLYCYC: Delay Cycle Selection bits When DLYINTEN = 0, these bits specify the additional delay (above the base overhead of the hardware) in number of TCY cycles before the SSP2BUF register is written again for the next transfer. When DLYINTEN = 1, these bits specify the delay in number of TCY cycles from the latest completed transfer before an interrupt to the CPU is invoked. In this case, the additional delay before the SSP2BUF register is written again is 1 TCY + (base overhead of hardware). 1111 = Delay time in number of instruction cycles is 2,048 cycles 1110 = Delay time in number of instruction cycles is 1,024 cycles 1101 = Delay time in number of instruction cycles is 896 cycles 1100 = Delay time in number of instruction cycles is 768 cycles 1011 = Delay time in number of instruction cycles is 640 cycles 1010 = Delay time in number of instruction cycles is 512 cycles 1001 = Delay time in number of instruction cycles is 384 cycles 1000 = Delay time in number of instruction cycles is 256 cycles 0111 = Delay time in number of instruction cycles is 128 cycles 0110 = Delay time in number of instruction cycles is 64 cycles 0101 = Delay time in number of instruction cycles is 32 cycles 0100 = Delay time in number of instruction cycles is 16 cycles 0011 = Delay time in number of instruction cycles is 8 cycles 0010 = Delay time in number of instruction cycles is 4 cycles 0001 = Delay time in number of instruction cycles is 2 cycles 0000 = Delay time in number of instruction cycles is 1 cycle INTLVL: Watermark Interrupt Enable bits These bits specify the amount of remaining data yet to be transferred (transmitted and/or received) upon which an interrupt is generated. 1111 = Amount of remaining data to be transferred is 576 bytes 1110 = Amount of remaining data to be transferred is 512 bytes 1101 = Amount of remaining data to be transferred is 448 bytes 1100 = Amount of remaining data to be transferred is 384 bytes 1011 = Amount of remaining data to be transferred is 320 bytes 1010 = Amount of remaining data to be transferred is 256 bytes 1001 = Amount of remaining data to be transferred is 192 bytes 1000 = Amount of remaining data to be transferred is 128 bytes 0111 = Amount of remaining data to be transferred is 67 bytes 0110 = Amount of remaining data to be transferred is 32 bytes 0101 = Amount of remaining data to be transferred is 16 bytes 0100 = Amount of remaining data to be transferred is 8 bytes 0011 = Amount of remaining data to be transferred is 4 bytes 0010 = Amount of remaining data to be transferred is 2 bytes 0001 = Amount of remaining data to be transferred is 1 byte 0000 = Transfer complete bit 3-0  2010 Microchip Technology Inc. Preliminary DS39974A-page 305 PIC18F47J13 FAMILY 20.4.4.3 DMABCH and DMABCL The DMABCH and DMABCL register pair forms a 10-bit Byte Count register, which is used by the SPI DMA module to send/receive up to 1,024 bytes for each DMA transaction. When the DMA module is actively running (DMAEN = 1), the DMA Byte Count register decrements after each byte is transmitted/received. The DMA transaction will Halt and the DMAEN bit will be automatically cleared by hardware after the last byte has completed. After a DMA transaction is complete, the DMABC register will read 0x000. Prior to initiating a DMA transaction by setting the DMAEN bit, user firmware should load the appropriate value into the DMABCH/DMABCL registers. The DMABC is a “base zero” counter, so the actual number of bytes which will be transmitted follows in Equation 20-1. For example, if user firmware wants to transmit 7 bytes in one transaction, DMABC should be loaded with 006h. Similarly, if user firmware wishes to transmit 1,024 bytes, DMABC should be loaded with 3FFh. The SPI DMA module can write received data to all general purpose memory on the device. The SPI DMA module cannot be used to modify the Special Function Registers contained in Banks 14 and 15. 20.4.5 INTERRUPTS The SPI DMA module alters the behavior of the SSP2IF interrupt flag. In normal non-DMA modes, the SSP2IF is set once after every single byte is transmitted/received through the MSSP2 module. When MSSP2 is used with the SPI DMA module, the SSP2IF interrupt flag will be set according to the user-selected INTLVL value specified in the DMACON2 register. The SSP2IF interrupt condition will also be generated once the SPI DMA transaction has fully completed and the DMAEN bit has been cleared by hardware. The SSP2IF flag becomes set once the DMA byte count value indicates that the specified INTLVL has been reached. For example, if DMACON2 = 0101 (16 bytes remaining), the SSP2IF interrupt flag will become set once DMABC reaches 00Fh. If user firmware then clears the SSP2IF interrupt flag, the flag will not be set again by the hardware until after all bytes have been fully transmitted and the DMA transaction is complete. Note: User firmware may modify the INTLVL bits while a DMA transaction is in progress (DMAEN = 1). If an INTLVL value is selected which is higher than the actual remaining number of bytes (indicated by DMABC + 1), the SSP2IF interrupt flag will immediately become set. EQUATION 20-1: BYTES TRANSMITTED FOR A GIVEN DMABC Bytes XMIT   DMABC + 1  20.4.4.4 TXADDRH and TXADDRL The TXADDRH and TXADDRL registers pair together to form a 12-bit Transmit Source Address Pointer register. In modes that use TXADDR (Full-Duplex and Half-Duplex Transmit), the TXADDR will be incremented after each byte is transmitted. Transmitted data bytes will be taken from the memory location pointed to by the TXADDR register. The contents of the memory locations pointed to by TXADDR will not be modified by the DMA module during a transmission. The SPI DMA module can read from, and transmit data from, all general purpose memory on the device. The SPI DMA module cannot be used to read from the Special Function Registers (SFRs) contained in Banks 14 and 15. For example, if DMABC = 00Fh (implying 16 bytes are remaining) and user firmware writes ‘1111’ to INTLVL (interrupt when 576 bytes remaining), the SSP2IF interrupt flag will immediately become set. If user firmware clears this interrupt flag, a new interrupt condition will not be generated until either: user firmware again writes INTLVL with an interrupt level higher than the actual remaining level, or the DMA transaction completes and the DMAEN bit is cleared. Note: If the INTLVL bits are modified while a DMA transaction is in progress, care should be taken to avoid inadvertently changing the DLYCYC value. 20.4.4.5 RXADDRH and RXADDRL The RXADDRH and RXADDRL registers pair together to form a 12-bit Receive Destination Address Pointer. In modes that use RXADDR (Full-Duplex and Half-Duplex Receive), the RXADDR register will be incremented after each byte is received. Received data bytes will be stored at the memory location pointed to by the RXADDR register. DS39974A-page 306 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY 20.4.6 USING THE SPI DMA MODULE 4. The following steps would typically be taken to enable and use the SPI DMA module: 1. Configure the I/O pins, which will be used by MSSP2. a) Assign SCK2, SDO2, SDI2 and SS2 to the RPn pins as appropriate for the SPI mode which will be used. Only functions which will be used need to be assigned to a pin. b) Initialize the associated LAT registers for the desired Idle SPI bus state. c) If Open-Drain Output mode on SDO2 and SCK2 (Master mode) is desired, set ODCON3. d) Configure the corresponding TRIS bits for each I/O pin used. Configure and enable MSSP2 for the desired SPI operating mode. a) Select the desired operating mode (Master or Slave, SPI Mode 0, 1, 2 and 3) and configure the module by writing to the SSP2STAT and SSP2CON1 registers. b) Enable MSSP2 by setting SSP2CON1 = 1. Configure the SPI DMA engine. a) Select the desired operating mode by writing the appropriate values to DMACON2 and DMACON1. b) Initialize the TXADDRH/TXADDRL Pointer (Full-Duplex or Half-Duplex Transmit Only mode). c) Initialize the RXADDRH/RXADDRL Pointer (Full-Duplex or Half-Duplex Receive Only mode). d) Initialize the DMABCH/DMABCL Byte Count register with the number of bytes to be transferred in the next SPI DMA operation. e) Set the DMAEN bit (DMACON1). In SPI Master modes, this will initiate a DMA transaction. In SPI Slave modes, this will complete the initialization process, and the module will now be ready to begin receiving and/or transmitting data to the master device once the master starts the transaction. Detect the SSP2IF interrupt condition (PIR3 3V VDD < 3.3V 3.3V  VDD 3.6V 0.25 VDD + 0.8V 2.0 0.8 VDD VDD VDD VDD V V V VDD < 3.3V 3.3V < VDD 74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39974A-page 540 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY APPENDIX A: REVISION HISTORY APPENDIX B: Revision A (March 2010) Original data sheet for PIC18F47J13 family devices. MIGRATION FROM PIC18F46J11 TO PIC18F47J13 Code for the devices in the PIC18F46J11 family can be migrated to the PIC18F47J13 without many changes. The differences between the two device families are listed in Table B-1. TABLE B-1: NOTABLE DIFFERENCES BETWEEN PIC18F47J13 AND PIC18F46J11 FAMILIES PIC18F47J13 Family 128 Kbytes PLL can be enabled at start-up with the Configuration bit option. 96 MHz PLL circuit is available via the Configuration bit setting, allowing 48 MHz operation from INTOSC. Default 4x PLL circuit is still available. Low-power oscillator option for SOSC, with run-time switch. T1CKI can be used as a clock input without enabling the Timer1 oscillator. 8 3 7 Yes Yes, all packages. 13 Channel, 10/12-Bit Conversion modes with Special Event Trigger option. Yes, allowing further power reduction. Yes, enabled on pin, RA1, by setting the VBGOE bit (WDTCON). Moved to TRISE register (avoids read, modify, write issues). Three, each with four input pin selections. RA0 through RA5, RDx and REx. F Devices – 500 s LF Devices – 46 ms 18F46J11 Family 64 Kbytes Requires firmware to set the PLLEN bit at run time. 4x PLL circuit only. Maximum operating frequency from INTOSC is 32 MHz. Characteristic Maximum Program Memory Oscillator Options SOSC Oscillator Options T1CKI Clock Input Timers ECCP CCP SPI FOSC/8 Master Clock Option Second I2C™ Port ADC Peripheral Module Disable Bits Band Gap Voltage Reference Output REPU/RDPU Pull-Up Enable Bits Comparators Increased Output Drive Strength PWRT Period Low-power oscillator option for SOSC, only via the Configuration bit setting. No 5 2 0 No Yes, but only on 44-pin devices. 13 Channel, 10-bit only. No No Pull-up bits configured in PORTE register Two, each with two input pin selections. No F Devices – 1 ms LF Devices – 64 ms  2010 Microchip Technology Inc. Preliminary DS39974A-page 541 PIC18F47J13 FAMILY NOTES: DS39974A-page 542 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY INDEX A A/D ................................................................................... 367 A/D Converter Interrupt, Configuring ....................... 373 Acquisition Requirements ........................................ 374 ADCAL Bit ................................................................ 377 ADRESH Register .................................................... 372 Analog Port Pins, Configuring .................................. 375 Associated Registers ............................................... 378 Automatic Acquisition Time ...................................... 375 Calibration ................................................................ 377 Configuring the Module ............................................ 373 Conversion Clock (TAD) ........................................... 375 Conversion Requirements, 10-Bit ............................ 528 Conversion Requirements, 12-Bit ............................ 528 Conversion Status (GO/DONE Bit) .......................... 372 Conversions ............................................................. 376 Converter Characteristics ........................................ 527 Operation in Power-Managed Modes ...................... 378 Use of the Special Event Triggers ........................... 376 Absolute Maximum Ratings ............................................. 487 AC (Timing) Characteristics ............................................. 506 Load Conditions for Device Timing Specifications ................................................... 507 Parameter Symbology ............................................. 506 Temperature and Voltage Specifications ................. 507 Timing Conditions .................................................... 507 ACKSTAT ......................................................................... 335 ACKSTAT Status Flag ..................................................... 335 ADCAL Bit ........................................................................ 377 ADCON0 Register GO/DONE Bit ........................................................... 372 ADDFSR .......................................................................... 476 ADDLW ............................................................................ 439 ADDULNK ........................................................................ 476 ADDWF ............................................................................ 439 ADDWFC ......................................................................... 440 ADRESL Register ............................................................ 372 Analog-to-Digital Converter. See A/D. ANDLW ............................................................................ 440 ANDWF ............................................................................ 441 Assembler MPASM Assembler .................................................. 484 Auto-Wake-up on Sync Break Character ......................... 358 Comparator Voltage Reference Output Buffer Example ........................................................... 389 Compare Mode Operation ................................264, 274 CTMU ...................................................................... 397 CTMU Current Source Calibration Circuit ................ 400 CTMU Typical Connections, Internal Configuration for Pulse Delay Generation ............................. 408 CTMU Typical Connections, Internal Configuration for Time Measurement .................................... 407 Demultiplexed Addressing Mode ............................. 194 Device Clock .............................................................. 36 Enhanced PWM Mode ............................................. 275 EUSART Transmit ................................................... 355 EUSARTx Receive .................................................. 357 Fail-Safe Clock Monitor ........................................... 429 Fully Multiplexed Addressing Mode ......................... 194 Generic I/O Port Operation ...................................... 139 High/Low-Voltage Detect with External Input .......... 392 Interrupt Logic .......................................................... 120 LCD Control, Byte Mode .......................................... 202 Legacy Parallel Slave Port ....................................... 188 MSSPx (I2C Master Mode) ...................................... 330 MSSPx (I2C Mode) .................................................. 310 MSSPx (SPI Mode) .................................................. 292 Multiplexed Addressing Application ......................... 201 On-Chip Reset Circuit ................................................ 65 Parallel EEPROM (Up to 15-Bit Address, 16-Bit Data) ..................................................... 202 Parallel EEPROM (Up to 15-Bit Address, 8-Bit Data) ....................................................... 202 Parallel Master/Slave Connection Addressed Buffer ............................................. 191 Parallel Master/Slave Connection Buffered ............. 190 Partially Multiplexed Addressing Application ........... 201 Partially Multiplexed Addressing Mode .................... 194 PIC18F2XJ13 (28-Pin) ............................................... 14 PIC18F4XJ13 (44-Pin) ............................................... 15 PMP Module Overview ............................................ 179 PWM Operation (Simplified) .................................... 266 Reads From Flash Program Memory ...................... 111 RTCC ....................................................................... 237 Serial Resistor ........................................................... 63 Simplified Steering ................................................... 288 Single Comparator ................................................... 382 Table Read Operation ............................................. 107 Table Write Operation .............................................. 108 Table Writes to Flash Program Memory .................. 113 Timer0 in 16-Bit Mode ............................................. 206 Timer0 in 8-Bit Mode ............................................... 206 Timer1 ..................................................................... 212 Timer2 ..................................................................... 220 Timer3/5 .................................................................. 225 Timer4 ..................................................................... 234 Using the Open-Drain Output .................................. 140 Watchdog Timer ...................................................... 424 BN .................................................................................... 442 BNC ................................................................................. 443 BNN ................................................................................. 443 BNOV ............................................................................... 444 BNZ .................................................................................. 444 BOR. See Brown-out Reset. BOV ................................................................................. 447 BRA ................................................................................. 445 B Baud Rate Generator ....................................................... 331 BC .................................................................................... 441 BCF .................................................................................. 442 BF ..................................................................................... 335 BF Status Flag ................................................................. 335 Block Diagrams +5V System Hardware Interface .............................. 140 8-Bit Multiplexed Address and Data Application ....................................................... 201 A/D ........................................................................... 372 Analog Input Model .................................................. 373 Baud Rate Generator ............................................... 332 Capture Mode Operation ................................. 262, 273 Clock Source Multiplexing ........................................ 250 Comparator Analog Input Model .............................. 382 Comparator Simplified ............................................. 379 Comparator Voltage Reference ............................... 387  2010 Microchip Technology Inc. Preliminary DS39974A-page 543 PIC18F47J13 FAMILY Break Character (12-Bit) Transmit and Receive .............. 360 BRG. See Baud Rate Generator. Brown-out Reset (BOR) ..................................................... 67 and On-Chip Voltage Regulator ............................... 427 Detecting .................................................................... 67 Disabling in Sleep Mode ............................................ 67 BSF .................................................................................. 445 BTFSC ............................................................................. 446 BTFSS .............................................................................. 446 BTG .................................................................................. 447 BZ ..................................................................................... 448 Initializing PORTA .................................................... 143 Initializing PORTB .................................................... 146 Initializing PORTC ................................................... 150 Initializing PORTD ................................................... 153 Initializing PORTE .................................................... 156 Loading the SSP1BUF (SSP1SR) Register ............. 295 Reading a Flash Program Memory Word ................ 111 Saving STATUS, WREG and BSR Registers in RAM ............................................. 138 Setting the RTCWREN Bit ....................................... 251 Setup for CTMU Calibration Routines ..................... 401 Single-Word Write to Flash Program Memory ......... 115 Two-Word Instructions ............................................... 87 Ultra Low-Power Wake-up Initialization ..................... 62 Writing to Flash Program Memory ........................... 114 Code Protection ............................................................... 415 COMF .............................................................................. 450 Comparator ...................................................................... 379 Analog Input Connection Considerations ................ 382 Associated Registers ............................................... 385 Configuration ........................................................... 383 Control ..................................................................... 383 Effects of a Reset .................................................... 385 Enable and Input Selection ...................................... 383 Enable and Output Selection ................................... 383 Interrupts .................................................................. 384 Operation ................................................................. 382 Operation During Sleep ........................................... 385 Registers .................................................................. 379 Response Time ........................................................ 382 Comparator Specifications ............................................... 503 Comparator Voltage Reference ....................................... 387 Accuracy and Error .................................................. 389 Associated Registers ............................................... 389 Configuring .............................................................. 388 Connection Considerations ...................................... 389 Effects of a Reset .................................................... 389 Operation During Sleep ........................................... 389 Compare (CCP Module) .................................................. 263 CCP Pin Configuration ............................................. 263 CCPR4 Register ...................................................... 263 Software Interrupt .................................................... 263 Special Event Trigger .............................................. 263 Timer1/Timer3 Mode Selection ................................ 263 Compare (ECCP Module) ................................................ 274 CCPRx Register ...................................................... 274 Pin Configuration ..................................................... 274 Software Interrupt Mode .......................................... 274 Special Event Trigger .......................................230, 274 Timer1/Timer3 Mode Selection ................................ 274 Computed GOTO ............................................................... 85 Configuration Bits ............................................................ 415 Configuration Mismatch (CM) Reset .................................. 68 Configuration Register Protection .................................... 430 Configuration Registers Bits and Device IDs ................................................. 416 Mapping Flash Configuration Words ....................... 416 Core Features Easy Migration ........................................................... 12 Expanded Memory ..................................................... 12 Extended Instruction Set ............................................ 12 nanoWatt XLP Technology ........................................ 11 Oscillator Options and Features ................................ 11 CPFSEQ .......................................................................... 450 CPFSGT .......................................................................... 451 C C Compilers MPLAB C18 ............................................................. 484 Calibration (A/D Converter) .............................................. 377 CALL ................................................................................ 448 CALLW ............................................................................. 477 Capture (CCP Module) ..................................................... 262 Associated Registers ............................................... 265 CCP Pin Configuration ............................................. 262 CCPR4H:CCPR4L Registers ................................... 262 Software Interrupt ..................................................... 263 Timer1/Timer3 Mode Selection ................................ 262 Capture (ECCP Module) .................................................. 272 CCPRxH:CCPRxL Registers ................................... 272 ECCP Pin Configuration ........................................... 272 Prescaler .................................................................. 273 Software Interrupt ..................................................... 273 Timer1/Timer3 Mode Selection ................................ 273 Capture/Compare/PWM (CCP) ........................................ 257 Capture Mode .......................................................... 262 Capture Mode. See Capture. CCP Mode and Timer Resources ............................ 261 CCPRxH Register .................................................... 261 CCPRxL Register ..................................................... 261 Compare Mode. See Compare. Configuration ............................................................ 261 Open-Drain Output Option ....................................... 262 CCP .................................................................................. 261 Clock Sources .................................................................... 41 Effects of Power-Managed Modes ............................. 45 Selecting the 31 kHz Source ...................................... 41 Selection Using OSCCON Register ........................... 41 CLRF ................................................................................ 449 CLRWDT .......................................................................... 449 Code Examples 16 x 16 Signed Multiply Routine ............................... 118 16 x 16 Unsigned Multiply Routine ........................... 118 512-Byte SPI Master Mode Init and Transfer ........... 308 8 x 8 Signed Multiply Routine ................................... 117 8 x 8 Unsigned Multiply Routine ............................... 117 A/D Calibration Routine ............................................ 378 Calculating Baud Rate Error .................................... 350 Capacitance Calibration Routine .............................. 404 Capacitive Touch Switch Routine ............................ 406 Changing Between Capture Prescalers ........... 263, 273 Communicating with the +5V System ...................... 140 Computed GOTO Using an Offset Value ................... 85 Configuring EUSART2 Input and Output Functions .............................................. 162 Current Calibration Routine ...................................... 402 Erasing Flash Program Memory .............................. 112 Fast Register Stack .................................................... 85 How to Clear RAM (Bank 1) Using Indirect Addressing .......................................... 101 DS39974A-page 544 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY CPFSLT ........................................................................... 451 Crystal Oscillator/Ceramic Resonators .............................. 37 CTMU Associated Registers ............................................... 413 Calibrating ................................................................ 399 Creating a Delay ...................................................... 408 Effects of a Reset ..................................................... 409 Initialization .............................................................. 399 Measuring Capacitance ........................................... 405 Measuring Time ....................................................... 407 Operation ................................................................. 398 Operation During Idle Mode ..................................... 409 Operation During Sleep Mode ................................. 409 CTMU Current Source Specifications .............................. 504 Customer Change Notification Service ............................ 554 Customer Notification Service .......................................... 554 Customer Support ............................................................ 554 Enhanced Capture/Compare/PWM (ECCP) .................... 269 Associated Registers ............................................... 289 Capture Mode. See Capture. Compare Mode. See Compare. ECCP Mode and Timer Resources ......................... 272 Enhanced PWM Mode ............................................. 275 Auto-Restart .................................................... 284 Auto-Shutdown ................................................ 282 Direction Change in Full-Bridge Output Mode ............................................ 281 Full-Bridge Application ..................................... 279 Full-Bridge Mode ............................................. 279 Half-Bridge Application .................................... 278 Half-Bridge Application Examples ................... 285 Half-Bridge Mode ............................................. 278 Output Relationships (Active-High and Active-Low) ....................................... 276 Output Relationships Diagram ......................... 277 Programmable Dead-Band Delay .................... 285 Shoot-Through Current .................................... 285 Start-up Considerations ................................... 282 Outputs and Configuration ....................................... 272 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART). See EUSART. Equations A/D Acquisition Time ............................................... 374 A/D Minimum Charging Time ................................... 374 Bytes Transmitted for a Given DMABC ................... 306 Calculating Output of the Comparator Voltage Reference ........................................... 388 Calculating the Minimum Required Acquisition Time .............................................. 374 Errata ................................................................................... 9 EUSART .......................................................................... 345 Asynchronous Mode ................................................ 355 12-Bit Break Transmit and Receive ................. 360 Associated Registers, Reception ..................... 358 Associated Registers, Transmission ............... 356 Auto-Wake-up on Sync Break ......................... 358 Receiver .......................................................... 357 Setting Up 9-Bit Mode with Address Detect ........................................ 357 Transmitter ...................................................... 355 Baud Rate Generator Operation in Power-Managed Mode ................ 349 Baud Rate Generator (BRG) ................................... 349 Associated Registers ....................................... 350 Auto-Baud Rate Detect .................................... 353 Baud Rates, Asynchronous Modes ................. 351 Formulas .......................................................... 349 High Baud Rate Select (BRGH Bit) ................. 349 Sampling .......................................................... 349 Synchronous Master Mode ...................................... 361 Associated Registers, Reception ..................... 364 Associated Registers, Transmission ............... 362 Reception ........................................................ 363 Transmission ................................................... 361 Synchronous Slave Mode ........................................ 365 Associated Registers, Reception ..................... 366 Associated Registers, Transmission ............... 365 Reception ........................................................ 366 Transmission ................................................... 365 D Data Addressing Modes ................................................... 101 Comparing Addressing Modes with the Extended Instruction Set Enabled .................... 105 Direct ........................................................................ 101 Indexed Literal Offset ............................................... 104 BSR .................................................................. 106 Instructions Affected ........................................ 104 Mapping Access Bank ..................................... 106 Indirect ..................................................................... 101 Inherent and Literal .................................................. 101 Data Memory ...................................................................... 88 Access Bank .............................................................. 90 Bank Select Register (BSR) ....................................... 88 Extended Instruction Set .......................................... 104 General Purpose Registers ........................................ 90 Memory Maps Access Bank Special Function Registers .......... 91 Non-Access Bank Special Function Registers .................................................... 92 PIC18F47J13 Family Devices ............................ 89 Special Function Registers ........................................ 91 Context Defined SFRs ....................................... 93 DAW ................................................................................. 452 DC Characteristics ................................................... 500, 502 Power-Down and Supply Current ............................ 490 Supply Voltage ......................................................... 489 DCFSNZ ........................................................................... 453 DECF ............................................................................... 452 DECFSZ ........................................................................... 453 Development Support ...................................................... 483 Device Migration to PIC18F47J13 ................................... 541 Device Overview ................................................................ 11 Details on Individual Family Members ....................... 12 Features (28-Pin Devices) ......................................... 13 Features (44-Pin Devices) ......................................... 13 Other Special Features .............................................. 12 Direct Addressing ............................................................. 102 E Effect on Standard PIC18 Instructions ............................. 480 Electrical Characteristics .................................................. 487 Absolute Maximum Ratings ..................................... 487 DC Characteristics ........................................... 489–502  2010 Microchip Technology Inc. Preliminary DS39974A-page 545 PIC18F47J13 FAMILY Extended Instruction Set ADDFSR .................................................................. 476 ADDULNK ................................................................ 476 CALLW ..................................................................... 477 MOVSF .................................................................... 477 MOVSS .................................................................... 478 PUSHL ..................................................................... 478 SUBFSR ................................................................... 479 SUBULNK ................................................................ 479 External Clock Input ........................................................... 38 I2C Mode .......................................................................... 310 I2C Mode (MSSP) Acknowledge Sequence Timing .............................. 338 Associated Registers ............................................... 344 Baud Rate Generator ............................................... 331 Bus Collision During a Repeated Start Condition .................. 342 During a Stop Condition ................................... 343 Clock Arbitration ...................................................... 333 Clock Stretching ....................................................... 325 10-Bit Slave Receive Mode (SEN = 1) ............ 325 10-Bit Slave Transmit Mode ............................ 325 7-Bit Slave Receive Mode (SEN = 1) .............. 325 7-Bit Slave Transmit Mode .............................. 325 Clock Synchronization and CKP bit ......................... 326 Effects of a Reset .................................................... 339 General Call Address Support ................................. 329 I2C Clock Rate w/BRG ............................................. 332 Master Mode ............................................................ 329 Operation ......................................................... 331 Reception ........................................................ 335 Repeated Start Condition Timing ..................... 334 Start Condition Timing ..................................... 333 Transmission ................................................... 335 Multi-Master Communication, Bus Collision and Arbitration ................................................. 339 Multi-Master Mode ................................................... 339 Operation ................................................................. 315 Read/Write Bit Information (R/W Bit) ................315, 318 Registers .................................................................. 310 Serial Clock (SCLx Pin) ........................................... 318 Slave Mode .............................................................. 315 Addressing ....................................................... 315 Addressing Masking Modes 5-Bit ......................................................... 316 7-Bit ......................................................... 317 Reception ........................................................ 318 Transmission ................................................... 318 Sleep Operation ....................................................... 339 Stop Condition Timing ............................................. 338 INCF ................................................................................ 454 INCFSZ ............................................................................ 455 In-Circuit Debugger .......................................................... 431 In-Circuit Serial Programming (ICSP) .......................415, 431 Indexed Literal Offset Addressing and Standard PIC18 Instructions ............................. 480 Indexed Literal Offset Mode ............................................. 480 Indirect Addressing .......................................................... 102 INFSNZ ............................................................................ 455 Initialization Conditions for All Registers .......................71–79 Instruction Cycle ................................................................ 86 Clocking Scheme ....................................................... 86 Flow/Pipelining ........................................................... 86 Instruction Set .................................................................. 433 ADDLW .................................................................... 439 ADDWF .................................................................... 439 ADDWF (Indexed Literal Offset Mode) .................... 481 ADDWFC ................................................................. 440 ANDLW .................................................................... 440 ANDWF .................................................................... 441 BC ............................................................................ 441 BCF .......................................................................... 442 BN ............................................................................ 442 BNC ......................................................................... 443 BNN ......................................................................... 443 F Fail-Safe Clock Monitor ............................................ 415, 428 Interrupts in Power-Managed Modes ....................... 430 POR or Wake-up From Sleep .................................. 430 WDT During Oscillator Failure ................................. 429 Fast Register Stack (FSR) ................................................. 85 Firmware Instructions ....................................................... 433 Flash Program Memory Write Sequence ........................................................ 115 Flash Program Memory .................................................... 107 Associated Registers ............................................... 116 Control Registers ..................................................... 108 EECON1 and EECON2 ................................... 108 TABLAT (Table Latch) Register ....................... 110 TBLPTR (Table Pointer) Register .................... 110 Erase Sequence ....................................................... 112 Erasing ..................................................................... 112 Operation During Code-Protect ................................ 116 Reading .................................................................... 111 Table Pointer Boundaries Based on Operation ...................... 110 Table Pointer Boundaries ......................................... 110 Table Reads and Table Writes ................................. 107 Write Sequence ........................................................ 113 Writing ...................................................................... 113 Unexpected Termination .................................. 116 Write Verify ...................................................... 116 FSCM. See Fail-Safe Clock Monitor. G GOTO ............................................................................... 454 H Hardware Multiplier .......................................................... 117 8 x 8 Multiplication Algorithms .................................. 117 Operation ................................................................. 117 Performance Comparison (table) ............................. 117 High/Low-Voltage Detect ................................................. 391 Applications .............................................................. 395 Associated Registers ............................................... 396 Characteristics ......................................................... 505 Current Consumption ............................................... 393 Effects of a Reset ..................................................... 396 Operation ................................................................. 392 During Sleep .................................................... 396 Setup ........................................................................ 393 Start-up Time ........................................................... 393 Typical Application ................................................... 395 I I/O Ports ........................................................................... 139 Open-Drain Outputs ................................................. 140 Pin Capabilities ........................................................ 139 TTL Input Buffer Option ............................................ 140 DS39974A-page 546 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY BNOV ....................................................................... 444 BNZ .......................................................................... 444 BOV ......................................................................... 447 BRA .......................................................................... 445 BSF .......................................................................... 445 BSF (Indexed Literal Offset Mode) .......................... 481 BTFSC ..................................................................... 446 BTFSS ..................................................................... 446 BTG .......................................................................... 447 BZ ............................................................................ 448 CALL ........................................................................ 448 CLRF ........................................................................ 449 CLRWDT .................................................................. 449 COMF ...................................................................... 450 CPFSEQ .................................................................. 450 CPFSGT .................................................................. 451 CPFSLT ................................................................... 451 DAW ......................................................................... 452 DCFSNZ .................................................................. 453 DECF ....................................................................... 452 DECFSZ ................................................................... 453 Extended Instructions .............................................. 475 Considerations when Enabling ........................ 480 Syntax .............................................................. 475 Use with MPLAB IDE Tools ............................. 482 General Format ........................................................ 435 GOTO ...................................................................... 454 INCF ......................................................................... 454 INCFSZ .................................................................... 455 INFSNZ .................................................................... 455 IORLW ..................................................................... 456 IORWF ..................................................................... 456 LFSR ........................................................................ 457 MOVF ....................................................................... 457 MOVFF .................................................................... 458 MOVLB .................................................................... 458 MOVLW ................................................................... 459 MOVWF ................................................................... 459 MULLW .................................................................... 460 MULWF .................................................................... 460 NEGF ....................................................................... 461 NOP ......................................................................... 461 Opcode Field Descriptions ....................................... 434 POP ......................................................................... 462 PUSH ....................................................................... 462 RCALL ..................................................................... 463 RESET ..................................................................... 463 RETFIE .................................................................... 464 RETLW .................................................................... 464 RETURN .................................................................. 465 RLCF ........................................................................ 465 RLNCF ..................................................................... 466 RRCF ....................................................................... 466 RRNCF .................................................................... 467 SETF ........................................................................ 467 SETF (Indexed Literal Offset Mode) ........................ 481 SLEEP ..................................................................... 468 Standard Instructions ............................................... 433 SUBFWB .................................................................. 468 SUBLW .................................................................... 469 SUBWF .................................................................... 469 SUBWFB .................................................................. 470 SWAPF .................................................................... 470 TBLRD ..................................................................... 471 TBLWT ..................................................................... 472 TSTFSZ ................................................................... 473 XORLW ................................................................... 473 XORWF ................................................................... 474 INTCON Registers ............................................ 121, 121–123 Inter-Integrated Circuit. See I2C. Internal Oscillator Frequency Drift. See INTOSC Frequency Drift. Internal Oscillator Block ..................................................... 38 Adjustment ................................................................. 39 OSCTUNE Register ................................................... 39 Internal RC Oscillator Use with WDT .......................................................... 424 Internal Voltage Regulator Specifications ........................ 503 Internet Address .............................................................. 554 Interrupt Sources ............................................................. 415 A/D Conversion Complete ....................................... 373 Capture Complete (CCP) ......................................... 263 Capture Complete (ECCP) ...................................... 273 Compare Complete (CCP) ....................................... 263 Compare Complete (ECCP) .................................... 274 Interrupt-on-Change (RB7:RB4) .............................. 146 TMR0 Overflow ........................................................ 207 TMR1 Overflow ........................................................ 214 TMR2 to PR2 Match (PWM) .................................... 266 TMRx Overflow .................................................221, 230 TMRx to PRx Match ................................................. 234 Interrupts .......................................................................... 119 Control Bits .............................................................. 119 Control Registers. See INTCON Registers. During, Context Saving ............................................ 138 INTx Pin ................................................................... 138 PORTB, Interrupt-on-Change .................................. 138 RCON Register ........................................................ 137 TMR0 ....................................................................... 138 Interrupts, Flag Bits Interrupt-on-Change (RB7:RB4) Flag (RBIF Bit) ......................................................... 146 INTOSC Frequency Drift .................................................... 39 INTOSC, INTRC. See Internal Oscillator Block. IORLW ............................................................................. 456 IORWF ............................................................................. 456 IPR Registers ............................................................133–136 L LFSR ................................................................................ 457 Low-Power Modes ............................................................. 47 Clock Transitions and Status Indicators .................... 48 Deep Sleep Mode ...................................................... 55 and RTCC Peripheral ........................................ 57 Brown-out Reset (DSBOR) ................................ 57 Fault Detection .................................................. 57 Preparation ........................................................ 55 Registers ........................................................... 58 Typical Sequence .............................................. 57 Wake-up Sources .............................................. 56 Watchdog Timer (DSWDT) ................................ 56 Exiting Idle and Sleep Modes .................................... 54 By Interrupt ........................................................ 54 By Reset ............................................................ 54 By WDT Time-out .............................................. 54 Without an Oscillator Start-up Delay ................. 55 Idle Modes ................................................................. 52 PRI_IDLE ........................................................... 52 RC_IDLE ........................................................... 54 SEC_IDLE ......................................................... 52  2010 Microchip Technology Inc. Preliminary DS39974A-page 547 PIC18F47J13 FAMILY Multiple Sleep Commands ......................................... 48 Run Modes ................................................................. 49 PRI_RUN ........................................................... 49 RC_RUN ............................................................ 50 SEC_RUN .......................................................... 49 Sleep Mode ................................................................ 51 Summary (table) ......................................................... 48 Ultra Low-Power Wake-up ......................................... 61 Parallel Master Port (PMP) .............................................. 179 Application Examples .............................................. 201 Associated Registers ............................................... 203 Data Registers ......................................................... 186 Master Port Modes .................................................. 193 Module Registers ..................................................... 180 Slave Port Modes .................................................... 188 Peripheral Module Disable (PMD) ..................................... 63 Peripheral Pin Select (PPS) ............................................. 158 Peripheral Pin Select Registers ................................163–178 PIE Registers ............................................................129–132 Pin Functions AVDD1 ........................................................................ 29 AVDD2 ........................................................................ 29 AVSS1 ........................................................................ 29 MCLR ....................................................................16, 22 OSC1/CLKI/RA7 ...................................................16, 22 OSC2/CLKO/RA6 .................................................16, 22 RA0/AN0/C1INA/ULPWU/PMA6/RP0 ....................... 23 RA0/AN0/C1INA/ULPWU/RP0 .................................. 17 RA1/AN1/C2INA/VBG ................................................. 23 RA1/AN1/C2INA/VBG/CTDIN/RP1 ............................. 17 RA2/AN2/C2INB/C1IND/C3INB/VREF-/CVREF ......17, 23 RA3/AN3/C1INB/VREF+ ........................................17, 23 RA5/AN4/C1INC/SS1/HLVDIN/RP2 .....................17, 23 RA6 .......................................................................17, 23 RA7 .......................................................................17, 23 RB0/AN12/C3IND/INT0/RP3 ................................18, 24 RB1/AN10/C3INC/PMBE/RTCCS/RP4 ..................... 24 RB1/AN10/C3INC/RTCC/RP4 ................................... 18 RB2/AN8/C2INC/CTED1/PMA3/REFO/RP5 ............. 24 RB2/AN8/C2INC/CTED1/REFO/RP5 ........................ 18 RB3/AN9/C3INA/CTED2/PMA2/RP6 ......................... 24 RB3/AN9/C3INA/CTED2/RP6 ................................... 18 RB4/CCP4/KBI0/SCL2/RP7 ...................................... 19 RB4/CCP4/PMA1/KBI0/RP7 ...................................... 25 RB5/CCP5/KBI1/SDA2/RP8 ...................................... 19 RB5/CCP5/PMA0/KBI1/RP8 ...................................... 25 RB6/CCP6/KBI2/PGC/RP9 ...................................19, 25 RB7/CCP7/KBI3/PGD/RP10 .................................19, 25 RC0/T1OSO/T1CKI/RP11 ....................................20, 26 RC1/CCP8/T1OSI/RP12 .......................................20, 26 RC2/AN11/C2IND/CTPLS/RP13 ..........................20, 26 RC3/SCK1/SCL1/RP14 ........................................20, 26 RC4/SDI1/SDA1/RP15 .........................................20, 26 RC5/SDO1/RP16 ..................................................20, 26 RC6/CCP9/PMA5/TX1/CK1/RP17 ............................. 27 RC6/CCP9/TX1/CK1/RP17 ....................................... 20 RC7/CCP10/PMA4/RX1/DT1/RP18 .......................... 27 RC7/CCP10/RX1/DT1/RP18 ..................................... 20 RD0/PMD0/SCL2 ....................................................... 28 RD1/PMD1/SDA2 ...................................................... 28 RD2/PMD2/RP19 ....................................................... 28 RD3/PMD3/RP20 ....................................................... 28 RD4/PMD4/RP21 ....................................................... 28 RD5/PMD5/RP22 ....................................................... 28 RD6/PMD6/RP23 ....................................................... 28 RD7/PMD7/RP24 ....................................................... 28 RE0/AN5/PMRD ........................................................ 29 RE1/AN6/PMWR ....................................................... 29 RE2/AN7/PMCS ........................................................ 29 VDD ............................................................................ 21 VDD1 .......................................................................... 29 VDD2 .......................................................................... 29 VDDCORE/VCAP ......................................................29, 21 M Master Clear (MCLR) ......................................................... 67 Master Synchronous Serial Port (MSSP). See MSSP. Memory Organization ......................................................... 81 Data Memory .............................................................. 88 Program Memory ....................................................... 81 Return Address Stack ................................................ 83 Memory Programming Requirements .............................. 502 Microchip Internet Web Site ............................................. 554 MOVF ............................................................................... 457 MOVFF ............................................................................. 458 MOVLB ............................................................................. 458 MOVLW ............................................................................ 459 MOVSF ............................................................................ 477 MOVSS ............................................................................ 478 MOVWF ........................................................................... 459 MPLAB ASM30 Assembler, Linker, Librarian .................. 484 MPLAB Integrated Development Environment Software ................................................................... 483 MPLAB PM3 Device Programmer .................................... 486 MPLAB REAL ICE In-Circuit Emulator System ................ 485 MPLINK Object Linker/MPLIB Object Librarian ............... 484 MSSP ACK Pulse ........................................................ 315, 318 I2C Mode. See I2C Mode. Module Overview ..................................................... 291 SPI Master/Slave Connection .................................. 296 TMR4/6/8 Output for Clock Shift .............................. 234 MULLW ............................................................................ 460 MULWF ............................................................................ 460 N NEGF ............................................................................... 461 NOP ................................................................................. 461 Notable Differences Between PIC18F47J13 and PIC18F46J11 Families ...................................... 541 O Oscillator Configurations .................................................... 35 Internal Oscillator Block ............................................. 38 Oscillator Control ........................................................ 35 Oscillator Modes ........................................................ 35 Oscillator Types ......................................................... 35 Switching .................................................................... 41 Transitions .................................................................. 42 Oscillator Selection .......................................................... 415 Oscillator Start-up Timer (OST) ......................................... 45 Oscillator, Timer1 ............................................. 209, 213, 226 Oscillator, Timer3 ............................................................. 221 P See Enhanced Capture/Compare/PWM (ECCP). Packaging Details ...................................................................... 531 Marking .................................................................... 529 DS39974A-page 548 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY VSS1 ..................................................................... 21, 29 VSS2 ..................................................................... 21, 29 Pinout I/O Descriptions PIC18F2XJ13 (28-Pin) ............................................... 16 PIC18F4XJ13 (44-Pin) ............................................... 22 PIR Registers ................................................................... 124 PLL Frequency Multiplier ................................................... 38 POP .................................................................................. 462 POR. See Power-on Reset. PORTA Additional Pin Functions Ultra Low-Power Wake-up ................................. 61 Associated Registers ............................................... 145 LATA Register .......................................................... 143 PORTA Register ...................................................... 143 TRISA Register ........................................................ 143 PORTB Associated Registers ............................................... 149 LATB Register .......................................................... 146 PORTB Register ...................................................... 146 RB7:RB4 Interrupt-on-Change Flag (RBIF Bit) ........ 146 TRISB Register ........................................................ 146 PORTC Associated Registers ............................................... 152 LATC Register ......................................................... 150 PORTC Register ...................................................... 150 TRISC Register ........................................................ 150 PORTD Associated Registers ............................................... 155 LATD Register ......................................................... 153 PORTD Register ...................................................... 153 TRISD Register ........................................................ 153 PORTE Associated Registers ............................................... 157 LATE Register .......................................................... 156 PORTE Register ...................................................... 156 TRISE Register ........................................................ 156 Power-Managed Modes and EUSART Operation ........................................... 349 and PWM Operation ................................................ 289 and SPI Operation ................................................... 300 Clock Sources ............................................................ 47 Entering ...................................................................... 47 Selecting .................................................................... 47 Power-on Reset (POR) ...................................................... 67 Power-up Delays ................................................................ 45 Power-up Timer (PWRT) .............................................. 45, 68 Time-out Sequence .................................................... 68 Prescaler, Capture ........................................................... 263 Prescaler, Timer0 ............................................................. 207 Prescaler, Timer2 ............................................................. 267 PRI_IDLE Mode ................................................................. 52 PRI_RUN Mode ................................................................. 49 Product Identification System ........................................... 556 Program Counter ................................................................ 83 PCL, PCH and PCU Registers ................................... 83 PCLATH and PCLATU Registers .............................. 83 Program Memory ALU STATUS ........................................................... 100 Extended Instruction Set .......................................... 103 Flash Configuration Words ........................................ 82 Hard Memory Vectors ................................................ 82 Instructions ................................................................ 87 Two-Word .......................................................... 87 Interrupt Vector .......................................................... 82 Look-up Tables .......................................................... 85 Memory Maps ............................................................ 81 Hard Vectors and Configuration Words ............. 82 Reset Vector .............................................................. 82 Program Verification and Code Protection ...................... 430 Programming, Device Instructions ................................... 433 Pulse Steering ................................................................. 286 Pulse-Width Modulation. See PWM (CCP Module). PUSH ............................................................................... 462 PUSH and POP Instructions .............................................. 84 PUSHL ............................................................................. 478 PWM (CCP Module) Associated Registers ............................................... 268 Duty Cycle ............................................................... 267 Example Frequencies/Resolutions .......................... 267 Period ...................................................................... 266 Setup for PWM Operation ........................................ 267 TMR2 to PR2 Match ................................................ 266 PWM (ECCP Module) Effects of a Reset .................................................... 289 Operation in Power-Managed Modes ...................... 289 Operation with Fail-Safe Clock Monitor ................... 289 Pulse Steering ......................................................... 286 Steering Synchronization ......................................... 288 PWM Mode. See Enhanced Capture/Compare/PWM. Q Q Clock ............................................................................ 267 R RAM. See Data Memory. RBIF Bit ........................................................................... 146 RC_IDLE Mode .................................................................. 54 RC_RUN Mode .................................................................. 50 RCALL ............................................................................. 463 RCON Register Bit Status During Initialization .................................... 70 Reader Response ............................................................ 555 Real-Time Clock and Calendar (RTCC) .......................... 237 Operation ................................................................. 249 Registers ................................................................. 238 Reference Clock Output .................................................... 44 Register File ....................................................................... 90 Registers ADCON0 (A/D Control 0) ......................................... 368 ADCON1 (A/D Control 1) ......................................... 369 ADCTRIG (A/D Trigger) ........................................... 376 ALRMCFG (Alarm Configuration) ............................ 241 ALRMDAY (Alarm Day Value) ................................. 246 ALRMHR (Alarm Hours Value) ................................ 247 ALRMMIN (Alarm Minutes Value) ............................ 248 ALRMMNTH (Alarm Month Value) .......................... 246 ALRMRPT (Alarm Repeat Counter) ........................ 242 ALRMSEC (Alarm Seconds Value) ......................... 248 ALRMWD (Alarm Weekday Value) .......................... 247 ANCON0 (A/D Port Configuration 0) ....................... 371 ANCON1 (A/D Port Configuration 1) ....................... 371 Associated with Comparator .................................... 379 Associated with Program Flash Memory ................. 116 BAUDCONx (Baud Rate Control) ............................ 348  2010 Microchip Technology Inc. Preliminary DS39974A-page 549 PIC18F47J13 FAMILY CCPRxH (CCP4-10 Period High Byte 4) ................. 260 CCPRxL (CCP4-10 Period Low Byte 4) ................... 260 CCPTMRS (CCP4-10 Timer Select 1) ..................... 258 CCPTMRS0 (ECCP1/2/3 Timer Select 0) ................ 271 CCPTMRS2 (CCP4-10 Timer Select 2) ................... 259 CCPxCON (CCPx, CCP4-10 Control) ...................... 257 CCPxCON (ECCP1/2/3 Control) .............................. 270 CMSTAT (Comparator Status) ................................. 381 CMxCON (Comparator Control 1/2/3) ...................... 380 CONFIG1H (Configuration 1 High) .......................... 418 CONFIG1L (Configuration 1 Low) ............................ 417 CONFIG2H (Configuration 2 High) .......................... 419 CONFIG2L (Configuration 2 Low) ............................ 418 CONFIG3H (Configuration 3 High) .................. 370, 421 CONFIG3L (Configuration 3 Low) ............................ 420 CONFIG4H (Configuration 4 High) .......................... 422 CONFIG4L (Configuration 4 Low) ............................ 421 CTMUCONH (CTMU Control High) ......................... 410 CTMUCONL (CTMU Control Low) ........................... 411 CTMUICON (CTMU Current Control) ...................... 412 CVRCON (Comparator Voltage Reference Control) ........................................... 388 DAY (Day Value) ...................................................... 244 DEVID1 (Device ID 1) .............................................. 422 DEVID2 (Device ID 2) .............................................. 423 DMACON1 (DMA Control 1) .................................... 304 DMACON2 (DMA Control 2) .................................... 305 DSCONH (Deep Sleep Control High Byte) ................ 58 DSCONL (Deep Sleep Control Low Byte) .................. 58 DSGPR0 (Deep Sleep Persistent General Purpose 0) ............................................ 59 DSGPR1 (Deep Sleep Persistent General Purpose 1) ............................................ 59 DSWAKEH (Deep Sleep Wake High Byte) ................ 59 DSWAKEL (Deep Sleep Wake Low Byte) ................. 60 ECCPxAS (ECCP1/2/3 Auto-Shutdown Control) ............................................................ 283 ECCPxDEL (ECCP1/2/3 Enhanced PWM Control) ............................................................ 286 EECON1 (EEPROM Control 1) ................................ 109 HLVDCON (High/Low-Voltage Detect Control) ........ 391 HOURS (Hours Value) ............................................. 245 I2C Mode (MSSP) .................................................... 310 INTCON (Interrupt Control) ...................................... 121 INTCON2 (Interrupt Control 2) ................................. 122 INTCON3 (Interrupt Control 3) ................................. 123 IPR1 (Peripheral Interrupt Priority 1) ........................ 133 IPR2 (Peripheral Interrupt Priority 2) ........................ 134 IPR3 (Peripheral Interrupt Priority 3) ........................ 135 IPR4 (Peripheral Interrupt Priority 4) ........................ 136 IPR5 (Peripheral Interrupt Priority 5) ........................ 136 MINUTES (Minutes Value) ....................................... 245 MONTH (Month Value) ............................................ 243 ODCON1 (Peripheral Open-Drain Control 1) ........... 141 ODCON2 (Peripheral Open-Drain Control 2) ........... 142 ODCON3 (Peripheral Open-Drain Control 3) ................................................. 142, 412 OSCCON (Oscillator Control) .................................... 42 OSCCON2 (Oscillator Control 2) ....................... 43, 224 OSCTUNE (Oscillator Tuning) ................................... 40 PADCFG1 (Pad Configuration 1) ............................. 240 PADCFG1 (Pad Configuration Control 1) ................ 143 Parallel Master Port .................................................. 180 PIE1 (Peripheral Interrupt Enable 1) ........................ 129 PIE2 (Peripheral Interrupt Enable 2) ........................ 130 PIE3 (Peripheral Interrupt Enable 3) ........................ 131 PIE4 (Peripheral Interrupt Enable 4) ........................ 132 PIE5 (Peripheral Interrupt Enable 5) ........................ 132 PIR1 (Peripheral Interrupt Request (Flag) 1) ........... 124 PIR2 (Peripheral Interrupt Request (Flag) 2) ........... 125 PIR3 (Peripheral Interrupt Request (Flag) 3) ........... 126 PMADDRH (Parallel Port Address High Byte, Master Modes Only) ........................................ 187 PMADDRL (Parallel Port Address Low Byte, Master Modes Only) ........................................ 187 PMCONH (Parallel Port Control High Byte) ............. 180 PMCONL (Parallel Port Control Low Byte) .............. 181 PMEH (Parallel Port Enable High Byte) ................... 184 PMEL (Parallel Port Enable Low Byte) .................... 184 PMMODEH (Parallel Port Mode High Byte) ............ 182 PMMODEL (Parallel Port Mode Low Byte) .............. 183 PMSTATH (Parallel Port Status High Byte) ............. 185 PMSTATL (Parallel Port Status Low Byte) .............. 185 PPSCON (Peripheral Pin Select Input 0) ................. 163 PSTRxCON (Pulse Steering Control) ...................... 287 RCON (Reset Control) ........................................66, 137 RCSTAx (Receive Status and Control) .................... 347 REF0CON (Reference Oscillator Control) ................. 44 Reserved ................................................................. 243 RPINR1 (Peripheral Pin Select Input 1) ................... 163 RPINR12 (Peripheral Pin Select Input 12) ............... 166 RPINR13 (Peripheral Pin Select Input 13) ............... 166 RPINR14 (Peripheral Pin Select Input 14) ............... 166 RPINR15 (Peripheral Pin Select Input 15) ............... 167 RPINR16 (Peripheral Pin Select Input 16) ............... 167 RPINR17 (Peripheral Pin Select Input 17) ............... 167 RPINR2 (Peripheral Pin Select Input 2) ................... 163 RPINR21 (Peripheral Pin Select Input 21) ............... 168 RPINR22 (Peripheral Pin Select Input 22) ............... 168 RPINR23 (Peripheral Pin Select Input 23) ............... 168 RPINR24 (Peripheral Pin Select Input 24) ............... 169 RPINR3 (Peripheral Pin Select Input 3) ................... 164 RPINR4 (Peripheral Pin Select Input 4) ................... 164 RPINR6 (Peripheral Pin Select Input 6) ................... 164 RPINR7 (Peripheral Pin Select Input 7) ................... 165 RPINR8 (Peripheral Pin Select Input 8) ................... 165 RPINR9 (Peripheral Pin Select Input 9) ................... 165 RPOR0 (Peripheral Pin Select Output 0) ................. 170 RPOR1 (Peripheral Pin Select Output 1) ................. 170 RPOR10 (Peripheral Pin Select Output 10) ............. 173 RPOR11 (Peripheral Pin Select Output 11) ............. 173 RPOR12 (Peripheral Pin Select Output 12) ............. 174 RPOR13 (Peripheral Pin Select Output 13) ............. 174 RPOR14 (Peripheral Pin Select Output 14) ............. 174 RPOR15 (Peripheral Pin Select Output 15) ............. 175 RPOR16 (Peripheral Pin Select Output 16) ............. 175 RPOR17 (Peripheral Pin Select Output 17) ............. 175 RPOR18 (Peripheral Pin Select Output 18) ............. 176 RPOR19 (Peripheral Pin Select Output 19) ............. 176 RPOR2 (Peripheral Pin Select Output 2) ................. 170 RPOR20 (Peripheral Pin Select Output 20) ............. 176 RPOR21 (Peripheral Pin Select Output 21) ............. 177 RPOR22 (Peripheral Pin Select Output 22) ............. 177 RPOR23 (Peripheral Pin Select Output 23) ............. 177 RPOR24 (Peripheral Pin Select Output 24) ............. 178 RPOR3 (Peripheral Pin Select Output 3) ................. 171 RPOR4 (Peripheral Pin Select Output 4) ................. 171 RPOR5 (Peripheral Pin Select Output 5) ................. 171 RPOR6 (Peripheral Pin Select Output 6) ................. 172 RPOR7 (Peripheral Pin Select Output 7) ................. 172 DS39974A-page 550 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY RPOR8 (Peripheral Pin Select Output 8) ................. 172 RPOR9 (Peripheral Pin Select Output 9) ................. 173 RTCCAL (RTCC Calibration) ................................... 240 RTCCFG (RTCC Configuration) .............................. 239 SECONDS (Seconds Value) .................................... 245 SPI Mode (MSSP) .................................................... 293 SSPxCON1 (MSSPx Control 1, I2C Mode) .............. 312 SSPxCON1 (MSSPx Control 1, SPI Mode) ............. 294 SSPxCON2 (MSSPx Control 2, I2C Master Mode) ............................................. 313 SSPxCON2 (MSSPx Control 2, I2C Slave Mode) ............................................... 314 SSPxMSK (I2C Slave Address Mask) ...................... 314 SSPxSTAT (MSSPx Status, I2C Mode) ................... 311 SSPxSTAT (MSSPx Status, SPI Mode) .................. 293 STATUS ................................................................... 100 STKPTR (Stack Pointer) ............................................ 84 T0CON (Timer0 Control) .......................................... 205 T1CON (Timer1 Control) .......................................... 209 T1GCON (Timer1 Gate Control) .............................. 210 T2CON (Timer2 Control) .......................................... 219 TxCON (Timer3/5 Control) ....................................... 222 TxCON (Timer4/6/8 Control) .................................... 234 TxGCON (Timer3/5 Gate Control) ........................... 223 TXSTAx (Transmit Status and Control) ................... 346 WDTCON (Watchdog Timer Control) ....................... 425 WKDY (Weekday Value) .......................................... 244 YEAR (Year Value) .................................................. 243 RESET ............................................................................. 463 Reset .................................................................................. 65 Brown-out Reset ........................................................ 67 Brown-out Reset (BOR) ............................................. 65 Configuration Mismatch (CM) .................................... 65 Configuration Mismatch Reset ................................... 68 Deep Sleep ................................................................ 65 Fast Register Stack (FSR) ......................................... 85 MCLR ......................................................................... 67 MCLR Reset, During Power-Managed Modes ........... 65 MCLR Reset, Normal Operation ................................ 65 Power-on Reset ......................................................... 67 Power-on Reset (POR) .............................................. 65 Power-up Timer ......................................................... 68 RESET Instruction ..................................................... 65 Stack Full Reset ......................................................... 65 Stack Underflow Reset .............................................. 65 State of Registers ...................................................... 70 Watchdog Timer (WDT) Reset ................................... 65 Resets .............................................................................. 415 Brown-out Reset (BOR) ........................................... 415 Oscillator Start-up Timer (OST) ............................... 415 Power-on Reset (POR) ............................................ 415 Power-up Timer (PWRT) ......................................... 415 RETFIE ............................................................................ 464 RETLW ............................................................................. 464 RETURN .......................................................................... 465 Return Address Stack ........................................................ 83 Associated Registers ................................................. 83 Revision History ............................................................... 541 RLCF ................................................................................ 465 RLNCF ............................................................................. 466 RRCF ............................................................................... 466 RRNCF ............................................................................. 467 RTCC Alarm ....................................................................... 253 Configuring ...................................................... 253 Interrupt ........................................................... 254 Mask Settings .................................................. 253 Alarm Value Register Mappings (ALRMVAL) .......... 246 Control Registers ..................................................... 239 Control/Value Register Maps ................................... 255 Low-Power Modes ................................................... 254 Operation Calibration ....................................................... 252 Clock Source ................................................... 250 Digit Carry Rules ............................................. 250 General Functionality ....................................... 251 Leap Year ........................................................ 251 Register Mapping ............................................ 251 ALRMVAL ................................................ 252 RTCVAL .................................................. 252 Safety Window for Register Reads and Writes ............................................... 251 Write Lock ........................................................ 251 Peripheral Module Disable (PMD) Register ............. 255 Register Interface .................................................... 249 Reset ....................................................................... 254 Device .............................................................. 254 Power-on Reset (POR) .................................... 254 Value Register Mappings (RTCVAL) ....................... 243 RTCEN Bit Write .............................................................. 249 S SCKx ................................................................................ 292 SDIx ................................................................................. 292 SDOx ............................................................................... 292 SEC_IDLE Mode ............................................................... 52 SEC_RUN Mode ................................................................ 49 Serial Clock, SCKx .......................................................... 292 Serial Data In (SDIx) ........................................................ 292 Serial Data Out (SDOx) ................................................... 292 Serial Peripheral Interface. See SPI Mode. SETF ................................................................................ 467 Shoot-Through Current .................................................... 285 Slave Select (SSx) ........................................................... 292 SLEEP ............................................................................. 468 Software Simulator (MPLAB SIM) ................................... 485 Special Event Trigger. See Compare (CCP Module). Special Event Trigger. See Compare (ECCP Mode). Special Features of the CPU ........................................... 415 SPI Mode (MSSP) ........................................................... 292 Associated Registers ............................................... 301 Bus Mode Compatibility ........................................... 300 Clock Speed, Interactions ........................................ 300 DMA Module ............................................................ 302 I/O Pin Considerations ..................................... 302 Idle, Sleep Considerations ............................... 302 RAM to RAM Copy .......................................... 302 Registers ......................................................... 302 Effects of a Reset .................................................... 300 Enabling SPI I/O ...................................................... 296 Master Mode ............................................................ 297 Master/Slave Connection ......................................... 296 Operation ................................................................. 295 Open-Drain Output Option ............................... 295  2010 Microchip Technology Inc. Preliminary DS39974A-page 551 PIC18F47J13 FAMILY Operation in Power-Managed Modes ...................... 300 Registers .................................................................. 293 Serial Clock .............................................................. 292 Serial Data In ........................................................... 292 Serial Data Out ......................................................... 292 Slave Mode .............................................................. 298 Slave Select ............................................................. 292 Slave Select Synchronization ................................... 298 SPI Clock ................................................................. 297 SSPxBUF Register ................................................... 297 SSPxSR Register ..................................................... 297 Typical Connection ................................................... 296 SSPOV ............................................................................. 335 SSPOV Status Flag .......................................................... 335 SSPxSTAT Register R/W Bit ............................................................. 315, 318 SSx ................................................................................... 292 Stack Full/Underflow Resets .............................................. 85 SUBFSR ........................................................................... 479 SUBFWB .......................................................................... 468 SUBLW ............................................................................ 469 SUBULNK ........................................................................ 479 SUBWF ............................................................................ 469 SUBWFB .......................................................................... 470 SWAPF ............................................................................ 470 Timer3/5 ........................................................................... 221 16-Bit Read/Write Mode .......................................... 226 Associated Registers ............................................... 231 Gate ......................................................................... 226 Operation ................................................................. 225 Oscillator ...........................................................221, 226 Overflow Interrupt .............................................221, 230 Special Event Trigger (ECCP) ................................. 230 TMRxH Register ...................................................... 221 TMRxL Register ....................................................... 221 Timer4 TMRx to PRx Match Interrupt .................................. 234 Timer4/6/8 ........................................................................ 233 Associated Registers ............................................... 235 Interrupt ................................................................... 234 MSSP Clock Shift .................................................... 234 Operation ................................................................. 233 Output ...................................................................... 234 Postscaler. See Postscaler, Timer4/6/8. Prescaler. See Prescaler, Timer4/6/8. PRx Register ............................................................ 233 TMRx Register ......................................................... 233 TMRx to PRx Match Interrupt .................................. 233 Timing Diagrams A/D Conversion ........................................................ 527 Asynchronous Reception ......................................... 358 Asynchronous Transmission .................................... 356 Asynchronous Transmission (Back-to-Back) ........... 356 Automatic Baud Rate Calculation ............................ 354 Auto-Wake-up Bit (WUE) During Normal Operation ............................................ 359 Auto-Wake-up Bit (WUE) During Sleep ................... 359 Baud Rate Generator with Clock Arbitration ............ 333 BRG Overflow Sequence ......................................... 354 BRG Reset Due to SDAx Arbitration During Start Condition ................................................. 341 Bus Collision During a Repeated Start Condition (Case 1) .................................. 342 Bus Collision During a Repeated Start Condition (Case 2) .................................. 342 Bus Collision During a Start Condition (SCLx = 0) ....................................... 341 Bus Collision During a Stop Condition (Case 1) ...... 343 Bus Collision During a Stop Condition (Case 2) ...... 343 Bus Collision During Start Condition (SDAx Only) ..................................... 340 Bus Collision for Transmit and Acknowledge .......... 339 CLKO and I/O .......................................................... 510 Clock Synchronization ............................................. 326 Clock/Instruction Cycle .............................................. 86 Enhanced Capture/Compare/PWM ......................... 514 Enhanced PWM Output (Active-High) ..................... 276 Enhanced PWM Output (Active-Low) ...................... 277 EUSARTx Synchronous Receive (Master/Slave) .... 526 EUSARTx Synchronous Transmission (Master/Slave) ................................................. 526 Example SPI Master Mode (CKE = 0) ..................... 518 Example SPI Master Mode (CKE = 1) ..................... 519 Example SPI Slave Mode (CKE = 0) ....................... 520 Example SPI Slave Mode (CKE = 1) ....................... 521 External Clock .......................................................... 508 Fail-Safe Clock Monitor ........................................... 429 First Start Bit ............................................................ 333 Full-Bridge PWM Output .......................................... 280 Half-Bridge PWM Output ..................................278, 285 T Table Pointer Operations (table) ...................................... 110 Table Reads/Table Writes .................................................. 85 TAD ................................................................................... 375 TBLRD ............................................................................. 471 TBLWT ............................................................................. 472 Timer0 .............................................................................. 205 Associated Registers ............................................... 207 Operation ................................................................. 206 Overflow Interrupt ..................................................... 207 Prescaler .................................................................. 207 Switching Assignment ...................................... 207 Prescaler Assignment (PSA Bit) .............................. 207 Prescaler Select (T0PS2:T0PS0 Bits) ...................... 207 Reads and Writes in 16-Bit Mode ............................ 206 Source Edge Select (T0SE Bit) ................................ 206 Source Select (T0CS Bit) ......................................... 206 Timer1 .............................................................................. 209 16-Bit Read/Write Mode ........................................... 213 Associated Registers ............................................... 218 Clock Source Selection ............................................ 211 Gate ......................................................................... 215 Interrupt .................................................................... 214 Operation ................................................................. 211 Oscillator .......................................................... 209, 213 Layout Considerations ..................................... 214 Resetting, Using the ECCP Special Event Trigger ....................................... 215 TMR1H Register ...................................................... 209 TMR1L Register ....................................................... 209 Use as a Clock Source ............................................. 214 Timer2 .............................................................................. 219 Associated Registers ............................................... 220 Interrupt .................................................................... 220 Operation ................................................................. 219 Output ...................................................................... 220 PR2 Register ............................................................ 266 TMR2 to PR2 Match Interrupt .................................. 266 DS39974A-page 552 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY High/Low-Voltage Detect Characteristics ................ 505 High-Voltage Detect (VDIRMAG = 1) ....................... 395 I22C Bus Data .......................................................... 522 I2C Acknowledge Sequence .................................... 338 I2C Bus Start/Stop Bits ............................................. 522 I2C Master Mode (7 or 10-Bit Transmission) ............ 336 I2C Master Mode (7-Bit Reception) .......................... 337 I2C Slave Mode (10-Bit Reception, SEN = 0, ADMSK = 01001) ............................. 322 I2C Slave Mode (10-Bit Reception, SEN = 0) .......... 323 I2C Slave Mode (10-Bit Reception, SEN = 1) .......... 328 I2C Slave Mode (10-Bit Transmission) ..................... 324 I2C Slave Mode (7-Bit Reception, SEN = 0, ADMSK = 01011) ............................. 320 I2C Slave Mode (7-Bit Reception, SEN = 0) ............ 319 I2C Slave Mode (7-Bit Reception, SEN = 1) ............ 327 I2C Slave Mode (7-Bit Transmission) ....................... 321 I2C Slave Mode General Call Address Sequence (7 or 10-Bit Addressing Mode) ........ 329 I2C Stop Condition Receive or Transmit Mode ........ 338 Low-Voltage Detect (VDIRMAG = 0) ....................... 394 MSSPx I2C Bus Data ............................................... 524 MSSPx I2C Bus Start/Stop Bits ................................ 524 Parallel Master Port Read ........................................ 515 Parallel Master Port Write ........................................ 516 Parallel Slave Port Read .................................. 189, 191 Parallel Slave Port Write .................................. 189, 192 PWM Auto-Shutdown with Auto-Restart Enabled .... 284 PWM Auto-Shutdown with Firmware Restart ........... 284 PWM Direction Change ........................................... 281 PWM Direction Change at Near 100% Duty Cycle ........................................................ 282 PWM Output ............................................................ 266 Read and Write, 8-Bit Data, Demultiplexed Address ............................................................ 196 Read, 16-Bit Data, Demultiplexed Address ............. 199 Read, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit Address ................................................. 200 Read, 16-Bit Multiplexed Data, Partially Multiplexed Address ......................................... 199 Read, 8-Bit Data, Fully Multiplexed 16-Bit Address ................................................. 198 Read, 8-Bit Data, Partially Multiplexed Address ...... 196 Read, 8-Bit Data, Partially Multiplexed Address, Enable Strobe ................................... 197 Read, 8-Bit Data, Wait States Enabled, Partially Multiplexed Address ........................... 196 Repeated Start Condition ......................................... 334 Reset, Watchdog Timer (WDT), Oscillator Start-up Timer (OST) and Power-up Timer (PWRT) ..... 511 Send Break Character Sequence ............................ 360 Slave Synchronization ............................................. 298 Slow Rise Time (MCLR Tied to VDD, VDD Rise > TPWRT) ............................................ 69 SPI Mode (Master Mode) ......................................... 297 SPI Mode (Slave Mode, CKE = 0) ........................... 299 SPI Mode (Slave Mode, CKE = 1) ........................... 299 Steering Event at Beginning of Instruction (STRSYNC = 1) ............................................... 288 Steering Event at End of Instruction (STRSYNC = 0) ............................................... 288 Synchronous Reception (Master Mode, SREN) ...... 363 Synchronous Transmission ...................................... 361 Synchronous Transmission (Through TXEN) .......... 362 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 1 ......................................... 69 Time-out Sequence on Power-up (MCLR Not Tied to VDD), Case 2 ......................................... 69 Time-out Sequence on Power-up (MCLR Tied to VDD, VDD Rise < TPWRT) ....................... 68 Timer Pulse Generation ........................................... 254 Timer0 and Timer1 External Clock .......................... 512 Timer1 Gate Count Enable Mode ............................ 215 Timer1 Gate Single Pulse Mode .............................. 217 Timer1 Gate Single Pulse/Toggle Combined Mode .............................................. 218 Timer1 Gate Toggle Mode ....................................... 216 Timer3/5 Gate Count Enable Mode ......................... 226 Timer3/5 Gate Single Pulse Mode ........................... 228 Timer3/5 Gate Single Pulse/Toggle Combined Mode .............................................. 229 Timer3/5 Gate Toggle Mode .................................... 227 Transition for Entry to Idle Mode ................................ 53 Transition for Entry to SEC_RUN Mode .................... 49 Transition for Entry to Sleep Mode ............................ 51 Transition for Two-Speed Start-up (INTRC to HSPLL) ........................................... 428 Transition for Wake From Idle to Run Mode .............. 53 Transition for Wake From Sleep (HSPLL) ................. 51 Transition From RC_RUN Mode to PRI_RUN Mode ................................................. 50 Transition From SEC_RUN Mode to PRI_RUN Mode (HSPLL) .................................. 49 Transition to RC_RUN Mode ..................................... 50 Write, 16-Bit Data, Demultiplexed Address ............. 199 Write, 16-Bit Multiplexed Data, Fully Multiplexed 16-Bit Address .............................. 200 Write, 16-Bit Multiplexed Data, Partially Multiplexed Address ........................................ 200 Write, 8-Bit Data, Fully Multiplexed 16-Bit Address ................................................. 198 Write, 8-Bit Data, Partially Multiplexed Address ...... 197 Write, 8-Bit Data, Partially Multiplexed Address, Enable Strobe ................................... 198 Write, 8-Bit Data, Wait States Enabled, Partially Multiplexed Address .......................... 197 Timing Diagrams and Specifications 4x PLL Clock ........................................................... 509 96 MHz PLL Clock ................................................... 509 CLKO and I/O Requirements ................................... 510 Enhanced Capture/Compare/PWM Requirements .................................................. 514 EUSARTx Synchronous Receive Requirements ..... 526 EUSARTx Synchronous Transmission Requirements .................................................. 526 Example SPI Mode Requirements (Master Mode, CKE = 0) .................................. 518 Example SPI Mode Requirements (Master Mode, CKE = 1) .................................. 519 Example SPI Mode Requirements (Slave Mode, CKE = 0) .................................... 520 Example SPI Slave Mode Requirements (CKE = 1) ................................. 521 External Clock Requirements .................................. 508 I2C Bus Data Requirements (Slave Mode) .............. 523 I2C Bus Start/Stop Bits Requirements (Slave Mode) ................................................... 522 Internal RC Accuracy (INTOSC and INTRC Sources) .............................................. 509  2010 Microchip Technology Inc. Preliminary DS39974A-page 553 PIC18F47J13 FAMILY Low-Power Wake-up Time ....................................... 512 MSSPx I2C Bus Data Requirements ........................ 525 MSSPx I2C Bus Start/Stop Bits Requirements ........ 524 Parallel Master Port Read Requirements ................. 515 Parallel Master Port Write Requirements ................. 516 Parallel Slave Port Requirements ............................ 517 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................................................... 511 Timer0 and Timer1 External Clock Requirements ................................................... 513 TSTFSZ ............................................................................ 473 Two-Speed Start-up ................................................. 415, 428 Two-Word Instructions Example Cases .......................................................... 87 TXSTAx Register BRGH Bit .................................................................. 349 V Voltage Reference Specifications .................................... 503 Voltage Regulator (On-Chip) ........................................... 426 Operation in Sleep Mode ......................................... 427 Power-up Requirements .......................................... 427 W Watchdog Timer (WDT) ............................................415, 424 Associated Registers ............................................... 425 Control Register ....................................................... 424 During Oscillator Failure .......................................... 429 Programming Considerations .................................. 424 WCOL ....................................................... 333, 334, 335, 338 WCOL Status Flag .................................... 333, 334, 335, 338 WWW Address ................................................................. 554 WWW, On-Line Support ...................................................... 9 U ULPWU Specifications ..................................................... 504 Ultra Low-Power Wake-up ................................................. 61 X XORLW ............................................................................ 473 XORWF ........................................................................... 474 DS39974A-page 554 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. Preliminary DS39974A-page 555 PIC18F47J13 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39974A FAX: (______) _________ - _________ Device: PIC18F47J13 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39974A-page 556 Preliminary  2010 Microchip Technology Inc. PIC18F47J13 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package XXX Pattern Examples: a) b) PIC18F47J13-I/PT 301 = Industrial temp., TQFP package, QTP pattern #301. PIC18F47J13T-I/PT = Tape and reel, Industrial temp., TQFP package. Device(1,2) PIC18F26J13, PIC18F27J13, PIC18F46J13 and PIC18F47J13 VDD range 2.15V to 3.6V PIC18LF26J13, PIC18LF27J13, PIC18LF46J13 and PIC18LF47J13 VDD range 2.0V to 3.6V I = -40C to E = -40C to ML PT SO SP SS = = = = = +85C +125C (Industrial) (Extended) Note 1: Temperature Range 2: F = Standard Voltage Range with internal 2.5V core voltage regulator LF = Wide Voltage Range with no internal core voltage regulator T = In tape and reel TQFP packages only Package QFN TQFP (Thin Quad Flatpack) SOIC Skinny Plastic DIP SSOP Pattern QTP, SQTP, Code or Special Requirements (blank otherwise)  2010 Microchip Technology Inc. Preliminary DS39974A-page 557 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 DS39974A-page 558 Preliminary  2010 Microchip Technology Inc.