PIC24F04KA200

PIC24FXXKA2XX PIC24FXXKA2XX Flash Programming Specifications 1.0 DEVICE OVERVIEW 2.0 PROGRAMMING OVERVIEW OF THE PIC24FXXKA2XX FAMILY This document defines the programming specifications for the PIC24FXXKA2XX family of 16-bit microcontroller devices. This is required only for developing programming support for the PIC24FXXKA2XX family. Users of any one of these devices should use the development tools that are already supporting the device programming. The programming specifications are specific to the following devices: • PIC24F04KA200 • PIC24F04KA201 PIC24FXXKA2XX family devices are programmed exclusively using In-Circuit Serial Programming™ (ICSP™). This method provides native, low-level programming capability to erase, program and verify the device. Section 3.0 “ICSP Programming” describes the ICSP method. Note: Unlike other PIC24F devices, PIC24FXXKA2XX devices do not support Enhanced ICSP programming. These devices also do not support in-circuit debugging over the ICSP interface. 2.1 Power Requirements All devices in the PIC24FXXKA2XX family are 3.3V supply designs. The core, the peripherals and the I/O pins operate at 3.3V. The device can operate from 1.8V to 3.6V. Table 2-1 provides the pins that are required for programming, which are indicated in Figure 2-1. Refer to the device data sheet for complete pin descriptions. TABLE 2-1: Pin Name PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Pin Name Pin Type P P P I I/O Programming Enable Power Supply Ground Programming Pin Pair: Serial Clock Programming Pin Pair: Serial Data Pin Description MCLR/VPP VDD VSS PGCx PGDx MCLR/VPP VDD VSS PGC PGD Legend: I = Input, O = Output, P = Power  2010 Microchip Technology Inc. DS39991A-page 1 PIC24FXXKA2XX FIGURE 2-1: PIC24FXXKA2XX PIN DIAGRAMS 14-Pin SPDIP, SOIC PIC24F04KA200 MCLR/VPP PGC2 PGD2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VSS PGD3 PGC3 20-Pin SPDIP, SOIC MCLR/VPP PGC2 PGD2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VSS PGD3 PGC3 20 19 18 17 16 15 1 14 2 3 PIC24F04KA201 13 12 4 11 5 6 7 8 9 10 PGD3 PGC3 PGD2 PGC2 MCLR/VPP VDD VSS 20-Pin QFN PIC24XXKA201 DS39991A-page 2  2010 Microchip Technology Inc. PIC24FXXKA2XX 2.2 Memory Map FIGURE 2-2: PROGRAM MEMORY MAP The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map, and supports up to about 1.38 K words of instructions (about 4 Kbytes). Figure 2-2 depicts the memory map. Table 2-2 provides the program memory size and number of program memory rows present in each device variant. The erase operation can be done on one word, half of a row or one row at a time. The program operation can be done only one word at a time. The device Configuration registers are implemented from location, F80000h to F80010h, and can be erased or programmed one register at a time. Table 2-3 provides the implemented Configuration registers and their locations. Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify the device type that is being programmed. See Section 4.0 “Device ID” for more information. The Device ID registers read out normally even after code protection is applied. User Memory Space 000000h User Flash Code Memory (2816 x 24-bit) 000AFEh Reserved 800000h Reserved Diagnostic Words Configuration Memory Space 8007EEh 8007F0h 8007FEh 800800h TABLE 2-2: Device PIC24F04KA200 PIC24F04KA201 PROGRAM MEMORY SIZES Program Memory Upper Address (Instruction Words) AFEh (1.375K) Rows Reserved 44 TABLE 2-3: CONFIGURATION REGISTER LOCATIONS Address F80004 F80006 F80008 F8000A F8000C F8000E F80010 F80000h Configuration Registers F80010h FEFFFEh FF0000h FF0002h FF0004h FFFFFEh Configuration Register FGS FOSCSEL FOSC FWDT FPOR FICD FDS Device ID (2 x 16-bit) Reserved  2010 Microchip Technology Inc. DS39991A-page 3 PIC24FXXKA2XX 3.0 ICSP PROGRAMMING FIGURE 3-1: The ICSP method is a special programming protocol that allows reading and writing to the PIC24FXXKA2XX device family memory. This is accomplished by applying control codes and instructions, serially to the device, using PGCx and PGDx pins. In ICSP mode, the system clock is taken from the PGCx pin, regardless of the device‘s oscillator Configuration bits. All of the instructions are shifted serially to an internal buffer, loaded into the Instruction Register (IR) and then executed. No program is fetched from the internal memory. Instructions are fed in 24 bits at a time. PGDx is used to shift data in, and PGCx is used as both the serial shift clock and the CPU execution clock. Note: During ICSP operation, the operating frequency of PGCx should not exceed 8 MHz. HIGH–LEVEL ICSP™ PROGRAMMING FLOW Start Enter ICSP™ Mode Perform Bulk Erase Program Memory Verify Program Program Configuration Bits 3.1 Overview of the Programming Process Verify Configuration Bits Figure 3-1 illustrates the high-level overview of the programming process. After entering the ICSP mode, perform the following: 1. 2. 3. 4. Bulk Erase the device. Program and verify the code memory. Program and verify the device configuration. Program the code-protect Configuration bits if required. Exit ICSP Mode End TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE Description Shift in 24-bit instruction and execute. Shift out the VISI (0784h) register. This is reserved. 3.2 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. An internal state machine governs the execution of the CPU. A 4-bit control code is clocked in, using PGCx and PGDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution, and the REGOUT control code is used to read data out of the device via the VISI register. 4-Bit Mnemonic Control Code 0000 0001 0010-1111 SIX REGOUT N/A DS39991A-page 4  2010 Microchip Technology Inc. PIC24FXXKA2XX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION For example, MOV #0x0,W0 followed by MOV [W0],W1 must have a NOP inserted in between. If a two-cycle instruction modifies a register, which is used indirectly, it requires two following NOPs; one to execute the second half of the instruction and the other to stall the CPU to correct the pipeline. For example, TBLWTL [W0++],[W1] should be followed by 2 NOPs. • The device Program Counter (PC) continues to automatically increment during the ICSP instruction execution, even though the Flash memory is not being used. As a result, it is possible for the PC to be incremented so that it points to invalid memory locations. Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location 0x0 to 0x1FF). If the PC ever points to these locations, it causes the device to reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200”. The SIX control code allows execution of PIC24FXXKA2XX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). Coming out of Reset, the first 4-bit control code is always forced to SIX and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up; thereby, resulting in a 9-bit SIX command, instead of the normal 4-bit SIX command. After the forced SIX is clocked in, the ICSP operation resumes to normal. That is, the next 24 clock cycles load the first instruction word to the CPU. Note: To account for this forced NOP, all example codes in this specification begin with a NOP to ensure that no data is lost. 3.2.1.1 Differences Between SIX Instruction Execution and Normal Instruction Execution 3.2.2 There are some differences between executing instructions using the SIX ICSP command and normal device instruction execution. As a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. The differences are: • Two-word instructions require 2 SIX operations to clock in all the necessary data. Examples of two-word instructions are: GOTO and CALL. • Two-cycle instructions require 2 SIX operations to complete. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, allows the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are table read and table write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register, which is used by the instruction immediately following the CPU stall for Indirect Addressing. During normal operation, the CPU forces a NOP while the new data is read. To account for this, while using ICSP, any indirect references to a recently modified register should be proceeded with a NOP. REGOUT SERIAL INSTRUCTION EXECUTION The REGOUT control code allows for the data to be extracted from the device in the ICSP mode. It is used to clock the contents of the VISI register out of the device over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After this, an additional 16 cycles are required to clock the data out (see Figure 3-3). The REGOUT code is unique as the PGDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGDx pin becomes an output as the VISI register is shifted out. Note 1: After the contents of VISI are shifted out, the PIC24FXXKA2XX devices maintain PGDx as an output until the first rising edge of the next clock is received. 2: Data changes on the falling edge and latches on the rising edge of PGCx. For all data transmissions, the Least Significant bit (LSb) is transmitted first.  2010 Microchip Technology Inc. DS39991A-page 5 PIC24FXXKA2XX FIGURE 3-2: SIX SERIAL EXECUTION P1 1 PGCx P3 P2 PGDx 0 0 0 0 0 0 0 0 0 LSB X X X X X X X X X X X X X X MSB 0 0 0 0 P4 P1A P1B P4A 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 Execute PC – 1, Fetch SIX Control Code 24-Bit Instruction Fetch Only for Program Memory Entry PGDx = Input Execute 24-Bit Instruction, Fetch Next Control Code FIGURE 3-3: 1 PGCx 2 3 REGOUT SERIAL EXECUTION 4 P4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 P4A 1 2 3 4 P5 PGDx 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0 Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input Shift Out VISI Register No Execution Takes Place, Fetch Next Control Code PGDx = Input PGDx = Output DS39991A-page 6  2010 Microchip Technology Inc. PIC24FXXKA2XX 3.3 3.3.1 Entering ICSP Mode LOW-VOLTAGE ICSP ENTRY As illustrated in Figure 3-4, the following processes are involved in entering ICSP Program/Verify mode using MCLR: 1. 2. 3. MCLR is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGCx before P7 has elapsed would not be interpreted as valid. 3.3.2 HIGH-VOLTAGE ICSP ENTRY The programming voltage, VIH, is applied to MCLR; this is VDD in the case of PIC24FXXKA2XX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001‘ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An Entering the ICSP Program/Verify mode, using the VPP pin is the same as entering the mode using MCLR. The only difference is the programming voltage applied to VPP is VIHH, and before presenting the key sequence on PGDx, an interval of at least P18 should elapse (see Figure 3-5). Once the key sequence is complete, an interval of at least P7 should elapse, and the voltage should remain at VIHH. The voltage, VIHH, must be held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P7 must elapse before presenting the data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. Upon a successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in a high-impedance state. FIGURE 3-4: P6 ENTERING ICSP™ MODE USING LOW-VOLTAGE ENTRY P14 P19 VIH VIH P7 MCLR VDD Program/Verify Entry Code = 4D434851h PGDx PGCx P18 P1A P1B 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 FIGURE 3-5: P6 VPP VDD ENTERING ICSP™ MODE USING HIGH-VOLTAGE ENTRY VIHH P7 VIH Program/Verify Entry Code = 4D434851h PGDx PGCx P18 P1A P1B 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0  2010 Microchip Technology Inc. DS39991A-page 7 PIC24FXXKA2XX 3.4 3.4.1 Flash Memory Programming in ICSP Mode PROGRAMMING OPERATIONS TABLE 3-2: NVMCON Value 4064h NVMCON VALUES FOR ERASE OPERATIONS Erase Operation Erase the code memory and Configuration registers (does not erase programming executive code and Device ID registers). Erase the general segment and Configuration bits associated with it. Erase the boot segment and Configuration bits associated with it. Erase four rows of code memory. Erase two rows of code memory. Erase a row of code memory. Erase all the Configuration registers (except the code-protect fuses). Erase Configuration registers except FBS and FGS. The NVMCON register controls the Flash memory write and erase operations. To program the device, set the NVMCON register to select the type of erase operation (see Table 3-2) or write operation (see Table 3-3). Set the WR control bit (NVMCON) to initiate the program. In ICSP mode, all programming operations are self-timed. There is an internal delay between setting and automatic clearing of the WR control bit when the programming operation is complete. Refer to Section 5.0 “AC/DC Characteristics and Timing Requirements” for information on the delays associated with various programming operations. 404Ch 4068h 405Ah(1) 4059h(1) 4058h(1) 4054h 3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE 4058h(1) Note 1: The WR bit (NVMCON) is used to start an erase or write cycle. Initiate the programming cycle by setting the WR bit. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle is completed. Start a programming cycle as follows: BSET NVMCON, #WR The destination address decides the region (code memory or Configuration register) of the erased rows/words. TABLE 3-3: NVMCON Value 4004h(1) 4004h (1) NVMCON VALUES FOR WRITE OPERATIONS Write Operation Write one Configuration register. Program one row (32 instruction words) of code memory or executive memory. The destination address decides the region (code memory or Configuration register) of the erased rows/words. Note 1: DS39991A-page 8  2010 Microchip Technology Inc. PIC24FXXKA2XX 3.5 Erasing Program Memory FIGURE 3-6: BULK ERASE FLOW Start To erase the program memory (all of code memory, data memory and Configuration bits, including the code-protect bits), set the NVMCON to 4064h and then execute the programming cycle. Figure 3-6 illustrates the ICSP programming process for Bulk Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), LSB first, using the PGCx and PGDx pins (see Figure 3-2). Table 3-4 provides the steps for executing serial instruction for the Bulk Erase mode. Note: Program memory must be erased before writing any data to program memory. Write 4064h to NVMCON SFR Set the WR bit to Initiate Erase Delay P11 + P10 Time End TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 000000 040200 000000 24064A 883B0A 200000 880190 200000 BB0800 000000 000000 A8E761 000000 000000 000000 040200 000000 803B02 883C22 000000 000000 NOP GOTO NOP MOV MOV MOV MOV MOV TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Set the NVMCON to erase the entire program memory. #0x4064, W10 W10, NVMCON #, W0 W0, TBLPAG #0x0000, W0 W0, [W0] Step 3: Set the TBLPAG and perform dummy table write to select the erased memory. Step 4: Initiate the erase cycle. NVMCON, #WR Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. NOP GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out the contents of the VISI register. NOP  2010 Microchip Technology Inc. DS39991A-page 9 PIC24FXXKA2XX 3.6 Writing Code Memory The procedure for writing code memory is the same as writing the Configuration registers. The difference is that the 32 instruction words are programmed one at a time. To facilitate this operation, working registers, W0:W5, are used as temporary holding registers for the data to be programmed. Figure 3-8 illustrates the code memory writing flow. Table 3-5 provides the ICSP programming details, including the serial pattern with the ICSP command code, which must be transmitted, LSB first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-5, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming a full row of code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. The upper byte of the starting destination address is stored in TBLPAG and the lower 16 bits of the destination address are stored in W7. To minimize the programming time, a packed instruction format is used (see Figure 3-7). In Step 4 of Table 3-5, four packed instruction words are stored in working registers, W0:W5, using the MOV instruction; the Read Pointer, W6, is initialized. Figure 3-7 illustrates the contents of W0:W5 holding the packed instruction word data. In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of the code memory. Since code memory is programmed 32 instruction words at a time, Steps 3 to 5 are repeated eight times to load all the write latches (see Step 6). After the write latches are loaded, initiate programming by writing to the NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing to unimplemented memory when large devices are being programmed. Finally, in Step 10, repeat Steps 3 through 9 until all of the code memory is programmed. FIGURE 3-7: PACKED INSTRUCTION WORDS IN W0:W5 87 LSW0 MSB1 LSW1 LSW2 MSB3 LSW3 MSB2 MSB0 0 15 W0 W1 W2 W3 W4 W5 TABLE 3-5: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 24004A 883B0A 200xx0 880190 2xxxx7 NOP GOTO NOP MOV MOV MOV MOV MOV 0x200 Step 2: Set the NVMCON to program 32 instruction words. #0x4004, W10 W10, NVMCON #, W0 W0, TBLPAG #, W7 Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. DS39991A-page 10  2010 Microchip Technology Inc. PIC24FXXKA2XX TABLE 3-5: Command (Binary) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Data (Hex) 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 MOV MOV MOV MOV MOV MOV CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP Description Step 4: Load W0:W5 with the next 4 instruction words to program. #, W0 #, W1 #, W2 #, W3 #, W4 #, W5 W6 [W6++], [W7] Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] Step 6: Repeat Steps 3 though 5, eight times, to load the write latches for 32 instructions. Step 7: Initiate the write cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 040200 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 9: Reset device internal PC. Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed.  2010 Microchip Technology Inc. DS39991A-page 11 PIC24FXXKA2XX FIGURE 3-8: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes N=N+1 Load 2 Bytes to Write Buffer at No All bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared N=1 LoopCount = LoopCount + 1 No All locations done? Yes End DS39991A-page 12  2010 Microchip Technology Inc. PIC24FXXKA2XX 3.7 Writing Configuration Registers TABLE 3-6: The procedure for writing the Configuration registers is the same as for writing code memory. The only difference is that only one word is programmed in each operation. When writing Configuration registers, one word is programmed during each operation. Only working register, W0, is used as a temporary holding register for the data to be programmed. Table 3-6 provides the Configuration registers. Note: default values of the DEFAULT VALUES FOR CONFIGURATION REGISTER SERIAL INSTRUCTION Value 03h 87h FFh DFh FBh C3h FFh Configuration Registers FGS FOSCSEL FOSC FWDT FPOR FICD FDS Note 1: (1) The TBLPAG register is hard-coded to 0xF8 (the upper byte address of all locations of the Configuration registers). Table 3-6 provides the ICSP programming details for programming the Configuration registers, including the serial pattern with the ICSP command code, which must be transmitted, LSB first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-7, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. Note: The TBLPAG register must be loaded with F8h. The Configuration register, FICD, is a reserved location and should be programmed with the default value given above.  2010 Microchip Technology Inc. DS39991A-page 13 PIC24FXXKA2XX TABLE 3-7: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Command (Binary) Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 000000 040200 000000 200007 24004A 883B0A 200F80 880190 2xxxx6 000000 BB1B86 000000 000000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 040200 000000 NOP GOTO NOP MOV MOV MOV MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. #0x0000, W7 #0x4004, W10 W10, NVMCON #0xF8, W6 W0, TBLPAG #, W6 Step 3: Set the NVMCON register to program Configuration registers. Step 4: Initialize the TBLPAG register. Step 5: Load the Configuration register data to W6. Step 6: Write the Configuration register data to the write latch and increment the Write Pointer. W6, [W7++] Step 7: Initiate the write cycle. NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 9: Reset device internal PC. Step 10: Repeat Steps 5 through 9 to write other fuses, Load W6 with their respective values and W7 with their respective addresses. DS39991A-page 14  2010 Microchip Technology Inc. PIC24FXXKA2XX TABLE 3-8: Bit Field BOREN PIC24FXXKA2XX FAMILY CONFIGURATION BITS DESCRIPTION Register FPOR Description Brown-out Reset Enable bits 11 = Brown-out Reset is enabled in hardware; SBOREN bit is disabled 10 = Brown-out Reset is enabled only while device is active and disabled in Sleep; SBOREN bit is disabled 01 = Brown-out Reset controlled with the SBOREN bit setting 00 = Brown-out Reset is disabled in hardware; SBOREN bit is disabled Brown-out Reset Voltage bits 11 = VBOR set to 1.8V min 10 = VBOR set to 2.0V min 01 = VBOR set to 2.7V min 00 = Downside protection on POR enabled – “Zero-power” selected Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) Deep Sleep Zero-Power BOR Enable bit 1 = Zero-Power BOR is enabled in Deep Sleep 0 = Zero-Power BOR is disabled in Deep Sleep (does not affect operation in non Deep Sleep modes) Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled BORV FPOR DSWDTEN FDS DSWDTPS FDS DSZPBOR FDS FCKSM FOSC FNOSC FOSCSEL Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Reserved; do not use 111 = Fast RC Oscillator with divide-by-N (FRCDIV) Note 1: The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry.  2010 Microchip Technology Inc. DS39991A-page 15 PIC24FXXKA2XX TABLE 3-8: Bit Field FWPSA PIC24FXXKA2XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FWDT Description WDT Prescaler 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 Watchdog Timer Enable bit 1 = WDT is enabled 0 = WDT is disabled (control is placed on the SWDTEN bit) General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security is enabled General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected ICD Pin Placement Select bit 11 = Reserved; do not use 10 = PGEC2/PGED2 are used for ICSP programming 01 = PGEC3/PGED3 are used for ICSP programming 00 = Reserved; do not use Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up disabled) MCLR Pin Enable bit(1) 1 = MCLR pin is enabled; RA5 input pin is disabled 0 = RA5 input pin is enabled; MCLR is disabled CLKO Enable Configuration bit 1 = CLKO output signal is active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD = 11 or 00) 0 = CLKO output is disabled Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected (4 MHz-25 MHz) 01 = XT Oscillator mode selected (100 kHz-4 MHz) 00 = External Clock mode selected Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency is greater than 8 MHz 10 = Primary oscillator/external clock input frequency is between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency is less than 100 kHz 00 = Reserved; do not use Power-up Timer Enable bit 0 = PWRT is disabled 1 = PWRT is enabled Secondary Oscillator Select bit 1 = Secondary oscillator is configured for high-power operation 0 = Secondary oscillator is configured for low-power operation FWDTEN FWDT GSS0 FGS GWRP FGS ICS FICD IESO FOSCSEL MCLRE(1) FPOR OSCIOFNC FOSC POSCMD FOSC POSCFREQ FOSC PWRTEN FPOR SOSCSEL FOSC Note 1: The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. DS39991A-page 16  2010 Microchip Technology Inc. PIC24FXXKA2XX TABLE 3-8: Bit Field WDTPS PIC24FXXKA2XX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FWDT Description Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT is disabled 0 = Windowed WDT is enabled WINDIS FWDT Note 1: The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry.  2010 Microchip Technology Inc. DS39991A-page 17 PIC24FXXKA2XX 3.8 Reading Code Memory To read the code memory, execute a series of TBLRD instructions and clock out the data using the REGOUT command. Table 3-9 provides the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and the W6 register. The upper byte of the starting source address is stored in TBLPAG, and the lower 16 bits of the source address are stored in W6. To minimize the reading time, the packed instruction word format, which was used for writing, is also used for reading (see Figure 3-7). In Step 3, the Write Pointer, W7, is initialized. In Step 4, two instruction words are read from code memory, and clocked out of the device through the VISI register, using the REGOUT command. Step 4 is repeated until the required amount of code memory is read. TABLE 3-9: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 200xx0 880190 2xxxx6 207847 000000 NOP GOTO NOP MOV MOV MOV MOV NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. #, W0 W0, TBLPAG #, W6 #VISI, W7 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. Step 4: Read and clock out the contents of the next two locations of code memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 BA1B96 000000 000000 000000 BADBB6 000000 000000 BAD3D6 000000 000000 000000 BA0BB6 000000 000000 000000 040200 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register. NOP TBLRDH [W6++], [W7] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register. NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP GOTO NOP 0x200 Step 5: Reset device internal PC. Step 6: Repeat Steps 4 and 5 until the required code memory is read. DS39991A-page 18  2010 Microchip Technology Inc. PIC24FXXKA2XX 3.9 Reading Configuration Memory The procedure for reading a Configuration register is the same as reading the code memory. The only difference is that the 16-bit data words are read (with the upper byte read being all ‘0‘s) instead of the 24-bit words. There are eight Configuration registers and they are read, one register at a time. Table 3-10 provides the ICSP programming details for reading all of the Configuration registers. Note: The TBLPAG register should be hard-coded to 0xF8 (the upper byte address of the Configuration register) and the Read Pointer, W6, is initialized to 0x00h. TABLE 3-10: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING ALL THE CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 200F80 880190 200007 207847 000000 NOP GOTO NOP MOV MOV MOV MOV NOP 0x200 Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction. #0xF8, W0 W0, TBLPAG #0x0000,W6 #VISI, W7 Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command. 0000 0000 0000 0001 BA0BB6 000000 000000 TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. Step 4: Repeat Step 3 to read other fuses. Load W6 with their respective address. Step 5: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200  2010 Microchip Technology Inc. DS39991A-page 19 PIC24FXXKA2XX 3.10 Verifying Code Memory and Configuration Registers 3.11 Exiting ICSP Mode Exit the Program/Verify mode by removing VIH from MCLR/VPP as illustrated in Figure 3-10. The only requirement to exit is that an interval of P16 should elapse between the last clock and the program signals on PGCx and PGDx before removing VIH. To verify the code memory, read the code memory space and compare it with the copy held in the programmer’s buffer. Figure 3-9 illustrates the verify process flowchart. Memory reads occur 1 byte at a time, hence 2 bytes must be read to compare with the word in the programmer’s buffer. Refer to Section 3.8 “Reading Code Memory” for implementation details of reading code memory. On the same lines, the data EEPROM and Configuration registers can be verified. Note: Code memory should be verified immediately after writing if code protection is enabled. Since Configuration registers include the device code protection bit, the device will not be readable or verifiable if a device Reset occurs after the code-protect bits are set (value = 0). FIGURE 3-10: EXITING ICSP™ MODE P16 P17 VIH/VIHH MCLR/VPP VDD VIH PGDx PGCx FIGURE 3-9: VERIFY CODE MEMORY FLOW Start PGD = Input Set TBLPTR = 0 Read Low Byte with Post-Increment Read High Byte with Post-Increment Does Word = Expect Data? Yes No All code memory verified? Yes End No Failure Report Error DS39991A-page 20  2010 Microchip Technology Inc. PIC24FXXKA2XX 4.0 DEVICE ID 4.1 4.1.1 Checksums CHECKSUM COMPUTATION The Device ID region of memory can be used to determine the mask, variant and manufacturing information about the device. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. Table 4-1 provides the Device ID for each device; Table 4-2 provides the Device ID registers; Table 4-3 describes the bit field of each register. Checksums for the PIC24FXXKA2XX family are 16 bits. The checksum is calculated by summing the following: • Contents of the code memory locations • Contents of the Configuration registers Table 4-4 describes how to calculate the checksum for each device. All memory locations are summed, one byte at a time, using only their native data size. More specifically, Configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored) while the code memory is summed by adding all three bytes of the code memory. TABLE 4-1: Device ID PIC24F04KA200 PIC24F04KA201 DEVICE IDs DEVID 0D02h 0D00h TABLE 4-2: Address FF0000h FF0002h PIC24FXXKA2XX DEVICE ID REGISTERS Bit Name 15 DEVID DEVREV 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAMID — DEV REV TABLE 4-3: Bit Field FAMID DEV REV DEVICE ID BITS DESCRIPTION Register DEVID DEVID DEVREV Description Encodes the family ID of the device. Encodes the individual ID of the device. Encodes the revision number of the device. TABLE 4-4: Device CHECKSUM COMPUTATION Read Code Protection Checksum Computation Erased Checksum Value 0x74B4 0x0000 Chip Checksum with 0xAAAAAA at 0x00 Location and at Last Location 0x72B6 0x0000 PIC24F04KAXXX Disabled Enabled CFGB + SUM (0:000AFE) 0 Description Legend: Item SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked), Byte sum of (FGS & 0x0003 + FOSCSEL & 0x0087 + FOSC & 0x00DF + FWDT & 0x00DF + FPOR & 0x00FB + FICD & 0x00C3 + FDS & 0x00FF)  2010 Microchip Technology Inc. DS39991A-page 21 PIC24FXXKA2XX 5.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS STANDARD OPERATING CONDITIONS TABLE 5-1: Standard Operating Conditions Operating Temperature: 0C to +70C and programming: +25C is recommended. Param Symbol No. D111 D112 D113 D031 D041 D042 D080 D090 D012 P1 P1A P1B P2 P3 P4 P4A P5 VDD IPP IDDP VIL VIH VIHH VOL VOH CIO TPGC TPGCL TPGCH TSET1 THLD1 TDLY1 TDLY1A TDLY2 Characteristic Supply Voltage During Programming Programming Current on MCLR Supply Current During Programming Input Low Voltage Input High Voltage Programing Voltage on VPP Output Low Voltage Output High Voltage Capacitive Loading on I/O Pin (PGDx) Serial Clock (PGCx) Period Serial Clock (PGCx) Low Time Serial Clock (PGCx) High Time Input Data Setup Time to Serial Clock  Input Data Hold Time from PGCx Delay Between 4-Bit Command and Command Operand Delay Between 4-Bit Command Operand and the Next 4-Bit Command Delay Between Last PGCx  of Command Byte and First PGCx  of Read of Data Word VDD Setup Time to MCLR  Input Data Hold Time from MCLR  VPP (from VIHH to VIH) PGCx Low Time After Programming Chip Erase Time Page (4 rows) Erase Time Row Programming Time MCLR Rise Time to Enter ICSP™ mode Data Out Valid from PGCx  Delay Between Last PGCx  and MCLR  MCLR to VDD  Delay Between First MCLR and First PGCx for Key Sequence on PGDx Delay Between Last PGCx for Key Sequence on PGDx and Second MCLR  Min VDDCORE — — VSS 0.8 VDD VDD +1.5 — 1.4 — 125 50 50 15 15 40 40 20 Max 3.60 50 2 0.2 VDD VDD 9 0.4 — 50 — — — — — — — — Units V A mA V V V V V pF ns ns ns ns ns ns ns ns Conditions Normal programming — — — — — IOL = 8.5 mA @ 3.6V IOH = -3.0 mA @ 3.6V To meet AC specifications — — — — — — — — P6 P7 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 TSET2 THLD2 TDLY6 TDLY7 TDLY10 TDLY9 TR TVALID TDLY10 THLD3 TKEY1 TKEY2 100 25 400 5 5 2 — 10 0 — 1 1 — — — — — — 1.0 — — 100 — — ns ms ns ms ms ms s ns s ns ms ms — — — — — — — — — — — — DS39991A-page 22  2010 Microchip Technology Inc. PIC24FXXKA2XX APPENDIX A: REVISION HISTORY Rev A Document (9/2010) Original version of this document; takes all information specific to PIC24XXKA20X family devices, originally found in DS39919, and created a new specification. No technical information regarding the devices or their programming has changed.  2010 Microchip Technology Inc. DS39991A-page 23 PIC24FXXKA2XX NOTES: DS39991A-page 24  2010 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-604-3 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.  2010 Microchip Technology Inc. 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