PIC24F16KA101

PIC24FXXKAXXX PIC24FXXKAXXX Flash Programming Specifications 1.0 DEVICE OVERVIEW FIGURE 2-1: PROGRAMMING SYSTEM OVERVIEW FOR ENHANCED ICSP™ METHOD PIC24FXXKAXXX Programmer Programming Executive This document defines the programming specifications for the PIC24FXXKAXXX family of 16-bit microcontroller devices. This is required only for developing programming support for the PIC24FXXKAXXX family. Users of any one of these devices should use the development tools that are already supporting the device programming. The programming specifications are specific to the following devices: • • • • • • PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 PIC24F04KA200 PIC24F04KA201 On-Chip Memory 2.1 Power Requirements 2.0 PROGRAMMING OVERVIEW OF THE PIC24FXXKAXXX FAMILY All devices in the PIC24FXXKAXXX family are 3.3V supply designs. The core, the peripherals and the I/O pins operate at 3.3V. The device can operate from 1.8V to 3.6V. 2.2 Entering Programming Mode Overview This section describes the two methods of programming the PIC24FXXKAXXX family of devices: • In-Circuit Serial Programming™ (ICSP™) • Enhanced In-Circuit Serial Programming (Enhanced ICSP) The ICSP programming method is the most direct method for programming the device. However, it is also the slower of the two methods. It provides native, low-level programming capability to erase, program, and verify the device. Section 3.0 “Device Programming – ICSP” describes the ICSP method. The Enhanced ICSP method is a faster method, which takes advantage of the programming executive as illustrated in Figure 2-1. The programming executive provides the necessary functionality to erase, program and verify the device through a command set. The command set allows the programmer to program the PIC24FXXKAXXX devices without having to deal with the low-level programming protocols of the device. Section 4.0 “Device Programming – Enhanced ICSP” describes the ICSP method using the programming executive. There are two methods of entering the Programming mode (either ICSP or Enhanced ICSP): • Low-Voltage ICSP Entry When the MCLR/VPP/RA5 pin is used as MCLR by applying VSS on MCLR (low-voltage entry), the device gets reset, and on applying the Programming mode entry sequence on the PGCx and PGDx pins, the device enters the Programming mode. • High-Voltage ICSP Entry To enter the Programming mode, if the MCLR function of the MCLR/VPP/RA5 pin needs to be disabled or is already disabled, a voltage VIHH should be applied on VPP (high-voltage entry). This is equivalent to applying VSS on MCLR; the device gets reset. On applying the Programming mode entry sequence on PGCx and PGDx pins, the device enters the Programming mode. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 1 PIC24FXXKAXXX 2.3 Pin Diagrams pin diagrams for the Figure 2-2 provides the PIC24FXXKAXXX family. Table 2-1 provides the pins that are required for programming (indicated in bold letters in Figure 2-2). Refer to the appropriate device data sheet for pin descriptions. FIGURE 2-2: PIN DIAGRAMS 14-Pin SPDIP, SOIC PIC24F04KA200 MCLR/VPP PGC2 PGD2 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD VSS PGD3 PGC3 20-Pin SPDIP, SOIC MCLR/VPP PGC2 PGD2 PGD1 PGC1 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VSS PGD3 PGC3 28-Pin PDIP, SOIC MCLR/VPP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS PIC24FXXKA102 PGD1 PGC1 PIC24XXKAX01 VSS PGC2 PGD2 VDD PGD3 PGC3 28 27 26 25 24 23 22 PGD1 PGC1 1 2 3 4 5 6 7 21 20 19 18 17 16 15 MCLR/VPP VDD Vss 28-Pin QFN PIC24FXXKA102 PGC2 PGD2 VSS 8 9 10 11 12 13 14 VDD PGD3 PGC3 DS39919A-page 2 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 2-1: Pin Name Pin Name MCLR/VPP VDD VSS PGCx PGDx MCLR/VPP VDD VSS PGC PGD Pin Type P P P I I/O Programming Enable Power Supply Ground Programming Pin Pair: Serial Clock Programming Pin Pair: Serial Data Pin Description PIN DESCRIPTIONS (DURING PROGRAMMING) During Programming Legend: I = Input, O = Output, P = Power 2.4 Memory Map TABLE 2-2: The program memory map extends from 000000h to FFFFFEh. Code storage is located at the base of the memory map, and supports up to 5.5K instruction words (about 16 Kbytes). Table 2-3 provides the program memory size and number of program memory rows present in each device variant. The PIC24FXXKA1XX family devices have an on-chip data EEPROM. This data EEPROM is mapped to the program memory area from location 7FFE00h to 7FFFFEh. Table 2-4 provides the data EEPROM size and the number of rows present in each device variant. The erase operation can be done on one word, half of a row or one row at a time. The program operation can be done only one word at a time. Locations, 800000h through 8007FEh, are reserved for executive code memory. This region stores the programming executive, the debugging executive and the Diagnostic Words. The programming executive is used for device programming, and the debug executive is used for in-circuit debugging. This region of memory cannot be used to store user code. The device Configuration registers are implemented from location F80000h to F80010h, and can be erased or programmed one register at a time. Table 2-2 provides the implemented Configuration registers and their locations. Locations, FF0000h and FF0002h, are reserved for the Device ID registers. These bits can be used by the programmer to identify the device type that is being programmed. See Section 6.0 “Device ID” for more information. The Device ID registers read out normally even after code protection is applied. Figure 2-3 depicts the memory PIC24FXXKAXXX family variants. map for the CONFIGURATION REGISTER LOCATIONS Address F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010 Configuration Register FBS FGS FOSCSEL FOSC FWDT FPOR FICD FDS TABLE 2-3: CODE MEMORY SIZE Memory No. of Address Limit (Instruction Words) 15FE (2.75K) 2BFE (5.5K) 15FE (2.75K) 2BFE (5.5K) AFE (1.375K) AFE (1.375K) No. of Rows 88 176 88 176 44 44 PIC24FXXKAXXX Device User PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 PIC24F04KA200 PIC24F04KA201 Note: An erase operation can be performed on one, two or four rows at a time, and a program operation can be performed on one row at a time. DATA EEPROM MEMORY SIZE Data EEPROM Size in Words 256 256 256 256 No. of Rows 32 32 32 32 TABLE 2-4: PIC24FXXKA1XX Device PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 Note: An erase operation can be performed on one, four or eight words at a time and a program operation can be performed on one word at a time. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 3 PIC24FXXKAXXX FIGURE 2-3: PROGRAM MEMORY MAP 000000h User Flash Code Memory (5632 x 24-bit) User Memory Space AFEh/15FEh/2BFEh(1) Reserved 7FFE00h Data EEPROM(2) Programming Executive Code Memory (1016 x 24-bit) Diagnostic Words 800000h 8007EEh 8007F0h 8007FEh 800800h Configuration Memory Space Reserved F80000h Configuration Registers F80010h Device ID (2 x 16-bit) Reserved FEFFFEh FF0000h FF0002h FF0004h FFFFFEh Note 1: 2: The address boundaries for user Flash code memory are device dependent (see Table 2-3). PIC24F04KA2XX devices have no data EEPROM. DS39919A-page 4 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 3.0 DEVICE PROGRAMMING – ICSP FIGURE 3-1: HIGH–LEVEL ICSP™ PROGRAMMING FLOW Start The ICSP method is a special programming protocol that allows reading and writing to the PIC24FXXKAXXX device family memory. ICSP is the most direct method used to program a device; however, Enhanced ICSP is faster. The ICSP mode also reads the contents of the executive memory to determine if the programming executive is present. This is accomplished by applying control codes and instructions, serially to the device, using PGCx and PGDx pins. In ICSP mode, the system clock is taken from the PGCx pin regardless of the device‘s oscillator Configuration bits. All of the instructions are shifted serially to an internal buffer, loaded into the Instruction Register (IR), and then executed. No program is fetched from the internal memory. Instructions are fed in 24 bits at a time. PGDx is used to shift data in, and PGCx is used as both the serial shift clock and the CPU execution clock. Note: During ICSP operation, the operating frequency of PGCx should not exceed 10 MHz. Enter ICSP™ Mode Perform Bulk Erase Program Memory Verify Program Program Data EEPROM Memory Verify Data EEPROM Memory Program Configuration Bits 3.1 Overview of the Programming Process Verify Configuration Bits Figure 3-1 illustrates the high-level overview of the programming process. After entering the ICSP mode, perform the following: 1. 2. 3. 4. 5. Bulk Erase the device. Program and verify the code memory. Program and verify the data EEPROM memory. Program and verify the device configuration. Program the code-protect Configuration bits if required. Exit ICSP Mode End 3.2 ICSP Operation Upon entry into ICSP mode, the CPU is Idle. An internal state machine governs the execution of the CPU. A 4-bit control code is clocked in, using PGCx and PGDx, and this control code is used to command the CPU (see Table 3-1). The SIX control code is used to send instructions to the CPU for execution, and the REGOUT control code is used to read data out of the device via the VISI register. TABLE 3-1: CPU CONTROL CODES IN ICSP™ MODE Description Shift in 24-bit instruction and execute. Shift out the VISI (0784h) register. This is reserved. 4-Bit Mnemonic Control Code 0000b 0001b SIX REGOUT 0010b-1111b N/A © 2008 Microchip Technology Inc. Advance Information DS39919A-page 5 PIC24FXXKAXXX 3.2.1 SIX SERIAL INSTRUCTION EXECUTION For example, MOV #0x0,W0 followed by MOV [W0],W1 must have a NOP inserted in between. If a two-cycle instruction modifies a register, which is used indirectly, it requires two following NOPs; one to execute the second half of the instruction and the other to stall the CPU to correct the pipeline. For example, TBLWTL [W0++],[W1] should be followed by 2 NOPs. • The device Program Counter (PC) continues to automatically increment during the ICSP instruction execution, even though the Flash memory is not being used. As a result, it is possible for the PC to be incremented so that it points to invalid memory locations. Examples of invalid memory spaces are unimplemented Flash addresses or the vector space (location 0x0 to 0x1FF). If the PC ever points to these locations, it causes the device to reset, possibly interrupting the ICSP operation. To prevent this, instructions should be periodically executed to reset the PC to a safe space. The optimal method of achieving this is to perform a “GOTO 0x200”. The SIX control code allows execution of PIC24FXXKAXXX family assembly instructions. When the SIX code is received, the CPU is suspended for 24 clock cycles as the instruction is then clocked into the internal buffer. Once the instruction is shifted in, the state machine allows it to be executed over the next four PGC clock cycles. While the received instruction is executed, the state machine simultaneously shifts in the next 4-bit command (see Figure 3-2). Coming out of Reset, the first 4-bit control code is always forced to SIX, and a forced NOP instruction is executed by the CPU. Five additional PGCx clocks are needed on start-up; thereby resulting in a 9-bit SIX command, instead of the normal 4-bit SIX command. After the forced SIX is clocked in, the ICSP operation resumes to normal. That is, the next 24 clock cycles load the first instruction word to the CPU. Note: To account for this forced NOP, all example codes in this specification begin with a NOP to ensure that no data is lost. 3.2.1.1 Differences Between SIX Instruction Execution and Normal Instruction Execution 3.2.2 There are some differences between executing instructions using the SIX ICSP command and normal device instruction execution. As a result, the code examples in this specification might not match those required to perform the same operations during normal device operation. The differences are: • Two-word instructions require 2 SIX operations to clock in all the necessary data. Examples of two-word instructions are GOTO and CALL. • Two-cycle instructions require 2 SIX operations to complete. The first SIX operation shifts in the instruction and begins to execute it. A second SIX operation, which should shift in a NOP to avoid losing data, allows the CPU clocks required to finish executing the instruction. Examples of two-cycle instructions are table read and table write instructions. • The CPU does not automatically stall to account for pipeline changes. A CPU stall occurs when an instruction modifies a register, which is used by the instruction immediately following the CPU stall for Indirect Addressing. During normal operation, the CPU forces a NOP while the new data is read. To account for this, while using ICSP, any indirect references to a recently modified register should be proceeded with a NOP. REGOUT SERIAL INSTRUCTION EXECUTION The REGOUT control code allows for the data to be extracted from the device in the ICSP mode. It is used to clock the contents of the VISI register out of the device over the PGDx pin. After the REGOUT control code is received, the CPU is held Idle for 8 cycles. After this, an additional 16 cycles are required to clock the data out (see Figure 3-3). The REGOUT code is unique as the PGDx pin is an input when the control code is transmitted to the device. However, after the control code is processed, the PGDx pin becomes an output as the VISI register is shifted out. Note 1: After the contents of VISI are shifted out, the PIC24FXXKAXXX devices maintain PGDx as an output until the first rising edge of the next clock is received. 2: Data changes on the falling edge and latches on the rising edge of PGCx. For all data transmissions, the Least Significant bit (LSb) is transmitted first. DS39919A-page 6 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 3-2: SIX SERIAL EXECUTION P1 1 PGCx P3 P2 PGDx 0 0 0 0 0 0 0 0 0 LSB X X X X X X X X X X X X X X MSB 0 0 0 0 P4 P1A P1B P4A 2 3 4 5 6 7 8 9 1 2 3 4 5 6 7 8 17 18 19 20 21 22 23 24 1 2 3 4 Execute PC – 1, Fetch SIX Control Code 24-Bit Instruction Fetch Only for Program Memory Entry PGDx = Input Execute 24-Bit Instruction, Fetch Next Control Code FIGURE 3-3: 1 PGCx 2 3 REGOUT SERIAL EXECUTION 4 P4 1 2 7 8 1 2 3 4 5 6 11 12 13 14 15 16 P4A 1 2 3 4 P5 PGDx 1 0 0 0 LSb 1 2 3 4 ... 10 11 12 13 14 MSb 0 0 0 0 Execute Previous Instruction, CPU Held in Idle Fetch REGOUT Control Code PGDx = Input Shift Out VISI Register No Execution Takes Place, Fetch Next Control Code PGDx = Input PGDx = Output © 2008 Microchip Technology Inc. Advance Information DS39919A-page 7 PIC24FXXKAXXX 3.3 3.3.1 Entering ICSP Mode LOW-VOLTAGE ICSP ENTRY As illustrated in Figure 3-4, the following processes are involved in entering ICSP Program/Verify mode using MCLR: 1. 2. 3. MCLR is briefly driven high, then low. A 32-bit key sequence is clocked into PGDx. MCLR is then driven high within a specified period of time and held. interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGCx before P7 has elapsed would not be interpreted as valid. 3.3.2 HIGH-VOLTAGE ICSP ENTRY The programming voltage VIH IS applied to MCLR; this is VDD in the case of PIC24FXXKAXXX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0001‘ (more easily remembered as 4D434851h in hexadecimal). The device will enter Program/Verify mode only if the sequence is valid. The Most Significant bit (MSb) of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An Entering the ICSP Program/Verify mode, using the VPP pin is the same as entering the mode using MCLR. The only difference is the programming voltage applied to VPP is VIHH, and before presenting the key sequence on PGDx, an interval of at least P18 should elapse (see Figure 3-5). Once the key sequence is complete, an interval of at least P7 should elapse, and the voltage should remain at VIHH. The voltage, VIHH, must be held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P7 must elapse before presenting the data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. Upon a successful entry, the program memory can be accessed and programmed in serial fashion. While in ICSP mode, all unused I/Os are placed in a high-impedance state. FIGURE 3-4: P6 ENTERING ICSP™ MODE USING LOW-VOLTAGE ENTRY P14 P19 VIH VIH P7 MCLR VDD Program/Verify Entry Code = 4D434851h PGDx PGCx P18 P1A P1B 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 FIGURE 3-5: P6 VPP VDD ENTERING ICSP™ MODE USING HIGH-VOLTAGE ENTRY P7 VIHH VIH Program/Verify Entry Code = 4D434851h PGDx PGCx P18 P1A P1B 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 1 b0 DS39919A-page 8 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 3.4 3.4.1 Flash Memory Programming in ICSP Mode PROGRAMMING OPERATIONS TABLE 3-3: NVMCON Value 4004h(1) 4004h (1) NVMCON VALUES FOR WRITE OPERATIONS Write Operation The NVMCON register controls the Flash memory write and erase operations. To program the device, set the NVMCON register to select the type of erase operation (see Table 3-2) or write operation (see Table 3-3). Set the WR control bit (NVMCON) to initiate the program. In ICSP mode, all programming operations are self-timed. There is an internal delay between setting and automatic clearing of the WR control bit when the programming operation is complete. Refer to Section 7.0 “AC/DC Characteristics and Timing Requirements” for information on the delays associated with various programming operations. Write one Configuration register. Program one row (32 instruction words) of code memory or executive memory. Program one word of data EEPROM memory. The destination address decides the region (code memory, data EEPROM memory or Configuration register) of the erased rows/words. 4004h(1) Note 1: 3.4.2 STARTING AND STOPPING A PROGRAMMING CYCLE TABLE 3-2: NVMCON Value 4064h NVMCON VALUES FOR ERASE OPERATIONS Erase Operation Erase the code memory and Configuration registers (does not erase programming executive code and Device ID registers). Erase the general segment and Configuration bits associated with it. Erase the boot segment and Configuration bits associated with it. Erase four rows of code memory. Erase two rows of code memory. Erase a row of code memory. Erase the entire data EEPROM memory and Configuration bits associated with it. The WR bit (NVMCON) is used to start an erase or write cycle. Initiate the programming cycle by setting the WR bit. All erase and write cycles are self-timed. The WR bit should be polled to determine if the erase or write cycle is completed. Start a programming cycle as follows: BSET NVMCON, #WR 3.5 Erasing Program Memory 404Ch 4068h 405Ah(1) 4059h(1) 4058h(1) 4050h To erase the program memory (all of code memory, data memory and Configuration bits, including the code-protect bits), set the NVMCON to 4064h and then execute the programming cycle. Figure 3-6 illustrates the ICSP programming process for Bulk Erase. This process includes the ICSP command code, which must be transmitted (for each instruction), LSB first, using the PGCx and PGDx pins (see Figure 3-2). Table 3-4 provides the steps for executing serial instruction for the Bulk Erase mode. Note: Program memory must be erased before writing any data to program memory. 405Ah 4059h (1) Erase eight words of data EEPROM memory. Erase four words of data EEPROM memory. Erase one word of data EEPROM memory. Erase all the Configuration registers (except the code-protect fuses). Erase Configuration registers except FBS and FGS. The destination address decides the region (code memory, data EEPROM memory or Configuration register) of the erased rows/words. (1) 4058h(1) 4054h 4058h(1) Note 1: FIGURE 3-6: BULK ERASE FLOW Start Write 4064h to NVMCON SFR Set the WR bit to Initiate Erase Delay P11 + P10 Time End © 2008 Microchip Technology Inc. Advance Information DS39919A-page 9 PIC24FXXKAXXX TABLE 3-4: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 000000 040200 000000 24064A 883B0A 200000 880190 200000 BB0800 000000 000000 A8E761 000000 000000 000000 040200 000000 803B02 883C22 000000 000000 NOP GOTO NOP MOV MOV MOV MOV MOV TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Set the NVMCON to erase the entire program memory. #0x4064, W10 W10, NVMCON #, W0 W0, TBLPAG #0x0000, W0 W0, [W0] Step 3: Set the TBLPAG and perform dummy table write to select the erased memory. Step 4: Initiate the erase cycle. NVMCON, #WR Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. NOP GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out the contents of the VISI register. NOP 3.6 Writing Code Memory The procedure for writing code memory is the same as writing the Configuration registers. The difference is that the 32 instruction words are programmed one at a time. To facilitate this operation, working registers, W0:W5, are used as temporary holding registers for the data to be programmed. Figure 3-8 illustrates the code memory writing flow. Table 3-5 provides the ICSP programming details, including the serial pattern with the ICSP command code, which must be transmitted LSB first, using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-5, the Reset vector is exited; in Step 2, the NVMCON register is initialized for programming a full row of code memory, and in Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. The upper byte of the starting destination address is stored in TBLPAG and the lower 16 bits of the destination address are stored in W7. To minimize the programming time, a packed instruction format is used (see Figure 3-7). In Step 4 of Table 3-5, four packed instruction words are stored in working registers, W0:W5, using the MOV instruction; the Read Pointer, W6, is initialized. Figure 3-7 illustrates the contents of W0:W5 holding the packed instruction word data. In Step 5, eight TBLWT instructions are used to copy the data from W0:W5 to the write latches of the code memory. Since code memory is programmed 32 instruction words at a time, Steps 3 to 5 are repeated eight times to load all the write latches (see Step 6). After the write latches are loaded, initiate programming by writing to the NVMCON register in Steps 7 and 8. In Step 9, the internal PC is reset to 200h. This is a precautionary measure to prevent the PC from incrementing to unimplemented memory when large devices are being programmed. Finally, in Step 10, repeat Steps 3 through 9 until all of the code memory is programmed. DS39919A-page 10 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 3-7: PACKED INSTRUCTION WORDS IN W0:W5 87 LSW0 MSB1 LSW1 LSW2 MSB3 LSW3 MSB2 MSB0 0 15 W0 W1 W2 W3 W4 W5 TABLE 3-5: Command (Binary) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY Data (Hex) 000000 040200 000000 24004A 883B0A 200xx0 880190 2xxxx7 2xxxx0 2xxxx1 2xxxx2 2xxxx3 2xxxx4 2xxxx5 NOP Description Step 1: Exit the Reset vector. GOTO NOP MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV MOV 0x200 Step 2: Set the NVMCON to program 32 instruction words. #0x4004, W10 W10, NVMCON #, W0 W0, TBLPAG #, W7 #, W0 #, W1 #, W2 #, W3 #, W4 #, W5 Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. Step 4: Load W0:W5 with the next 4 instruction words to program. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 11 PIC24FXXKAXXX TABLE 3-5: Command (Binary) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SERIAL INSTRUCTION EXECUTION FOR WRITING CODE MEMORY (CONTINUED) Data (Hex) EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP W6 [W6++], [W7] Description Step 5: Set the Read Pointer (W6) and load the (next set of) write latches. [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] [W6++], [W7] [W6++], [W7++] [W6++], [++W7] [W6++], [W7++] Step 6: Repeat Steps 3 though 5, eight times, to load the write latches for 32 instructions. Step 7: Initiate the write cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 040200 000000 BSET NOP NOP NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 9: Reset device internal PC. Step 10: Repeat Steps 3 through 9 until the entire code memory is programmed. DS39919A-page 12 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 3-8: PROGRAM CODE MEMORY FLOW Start N=1 LoopCount = 0 Configure Device for Writes N=N+1 Load 2 Bytes to Write Buffer at No All bytes written? Yes Start Write Sequence and Poll for WR bit to be Cleared N=1 LoopCount = LoopCount + 1 No All locations done? Yes End © 2008 Microchip Technology Inc. Advance Information DS39919A-page 13 PIC24FXXKAXXX 3.7 Writing Data EEPROM Figure 3-9 illustrates the flow of programming the data EEPROM memory. The procedure is the same as writing code memory. The only difference is that only one word is programmed in each operation. When writing data EEPROM, one word is programmed during each operation. Working register, W0, is used as a temporary holding register for the data to be programmed. Table 3-6 provides the ICSP programming details for writing data EEPROM. Note: The TBLPAG register is hard-coded to 0x7F (the upper byte address of all locations of data EEPROM). FIGURE 3-9: PROGRAM DATA EEPROM MEMORY FLOW Start LoopCount = 0 Configure Device for Writes Load 2 Bytes to Write Buffer at LoopCount = LoopCount + 1 Start Write Sequence and Poll for WR bit to be Cleared No All locations done? Yes End DS39919A-page 14 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 3-6: Command (Binary) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00001 0000 0000 0000 INSTRUCTION EXECUTION FOR WRITING DATA EEPROM Data (Hex) Description Step 1: Exit the Reset vector. 000000 040200 000000 24004A 883B0A 2007F0 880190 2FExx7 2xxxx0 BB1B80 000000 000000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 040200 000000 NOP GOTO NOP MOV MOV MOV MOV MOV MOV TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Set the NVMCON to program 1 data word. #0x4004, W10 W10, NVMCON #0x7F, W0 W0, TBLPAG #, W7 #, W0 W0, [W7++] Step 3: Initialize the Write Pointer (W7) for TBLWT instruction. Step 4: Load W0 with the data word to program and load the write latch. Step 5: Initiate the write cycle. NVMCON, #WR Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 7: Reset device internal PC. Step 8: Repeat Steps 4 through 7 until the entire data EEPROM memory is programmed. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 15 PIC24FXXKAXXX 3.8 Writing Configuration Registers TABLE 3-7: The procedure for writing the Configuration registers is the same as for writing code memory. The only difference is that, only one word is programmed in each operation. When writing Configuration registers, one word is programmed during each operation, only working register, W0, is used as a temporary holding register for the data to be programmed. Table 3-7 provides the Configuration registers. Note: default values of the DEFAULT VALUES FOR CONFIGURATION REGISTER SERIAL INSTRUCTION Value 0Fh 03h 87h FFh DFh FBh C3h FFh Configuration Registers FBS(3) FGS FOSCSEL FOSC FWDT FPOR(1) FICD(2,3) FDS (4) The TBLPAG register is hard-coded to 0xF8 (the upper byte address of all locations of the Configuration registers). Table 3-7 provides the ICSP programming details for programming the Configuration registers, including the serial pattern with the ICSP command code, which must be transmitted LSB first using the PGCx and PGDx pins (see Figure 3-2). In Step 1 of Table 3-8, the Reset vector is exited. In Step 2, the NVMCON register is initialized for programming code memory. In Step 3, the 24-bit starting destination address for programming is loaded into the TBLPAG register and W7 register. Note: The TBLPAG register must be loaded with F8h. Note 1: 2: 3: 4: The I2C2SEL bit (FPOR) is not implemented on PIC24FXXKAX01 and PIC24FXXKAX00 devices and should be programmed as ‘1’. The FICD bit is a reserved bit and should be programmed as ‘1’. The Configuration registers, FBS and FICD, are reserved locations on PIC24F04KA2XX devices, and should be programmed with the default value given above. The RTCSOSC bit (FDS) is not implemented on PIC24F04KA2XX devices, and should be programmed as ‘1’. DS39919A-page 16 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 3-8: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS Data (Hex) Command (Binary) Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 000000 040200 000000 200007 24004A 883B0A 200F80 880190 2xxxx6 000000 BB1B96 000000 000000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 040200 000000 NOP GOTO NOP MOV MOV MOV MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction. #0x0000, W7 #0x4004, W10 W10, NVMCON #0xF8, W6 W0, TBLPAG #, W6 Step 3: Set the NVMCON register to program Configuration registers. Step 4: Initialize the TBLPAG register. Step 5: Load the Configuration register data to W6. Step 6: Write the Configuration register data to the write latch and increment the Write Pointer. W6, [W7++] Step 7: Initiate the write cycle. NVMCON, #WR Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 9: Reset device internal PC. Step 10: Repeat Steps 5 through 9 to write other fuses, Load W6 with their respective values and W7 with their respective addresses. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 17 PIC24FXXKAXXX 3.9 Reading Code Memory To read the code memory, execute a series of TBLRD instructions and clock out the data using the REGOUT command. Table 3-9 provides the ICSP programming details for reading code memory. In Step 1, the Reset vector is exited. In Step 2, the 24-bit starting source address for reading is loaded into the TBLPAG register and the W6 register. The upper byte of the starting source address is stored in TBLPAG, and the lower 16 bits of the source address are stored in W6. To minimize the reading time, the packed instruction word format, which was used for writing, is also used for reading (see Figure 3-7). In Step 3, the Write Pointer, W7, is initialized. In Step 4, two instruction words are read from code memory, and clocked out of the device through the VISI register, using the REGOUT command. Step 4 is repeated until the required amount of code memory is read. TABLE 3-9: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING CODE MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 200xx0 880190 2xxxx6 207847 000000 NOP GOTO NOP MOV MOV MOV MOV NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. #, W0 W0, TBLPAG #, W6 #VISI, W7 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. Step 4: Read and clock out the contents of the next two locations of code memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 BA1B96 000000 000000 000000 BADBB6 000000 000000 BAD3D6 000000 000000 000000 BA0BB6 000000 000000 000000 040200 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register. NOP TBLRDH [W6++], [W7] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register. NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP GOTO NOP 0x200 Step 5: Reset device internal PC. Step 6: Repeat Steps 4 and 5 until the required code memory is read. DS39919A-page 18 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 3.10 Reading Data EEPROM Memory The procedure for reading data EEPROM memory is the same as reading the code memory. The only difference is that the 16-bit data words are read instead of the 24-bit words. Table 3-10 provides the ICSP programming details for reading data memory. Note: The TBLPAG register is hard-coded to 0x7F (the upper byte address of all locations of data memory). TABLE 3-10: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING DATA EEPROM MEMORY Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 2007F0 880190 2FExx6h 207847 000000 NOP GOTO NOP MOV MOV MOV MOV NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. #0x7F, W0 W0, TBLPAG #, W6;(FExx) #VISI, W7 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. Step 4: Read and clock out the contents of the next location of data EEPROM memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 BA1B96 000000 000000 000000 TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP Step 5: Repeat Step 4 until the required data EEPROM memory is read. Step 6: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 © 2008 Microchip Technology Inc. Advance Information DS39919A-page 19 PIC24FXXKAXXX 3.11 Reading Configuration Memory The procedure for reading a Configuration register is the same as reading the code memory. The only difference is that the 16-bit data words are read (with the upper byte read being all ‘0‘s) instead of the 24-bit words. There are eight Configuration registers and they are read one register at a time. Table 3-11 provides the ICSP programming details for reading all of the Configuration registers. Note: The TBLPAG register should be hard-coded to 0xF8 (the upper byte address of the Configuration register) and the Read Pointer, W6, is initialized to 0x00h. TABLE 3-11: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING ALL THE CONFIGURATION REGISTERS Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 200F80 880190 200007 207847 000000 NOP GOTO NOP MOV MOV MOV MOV NOP 0x200 Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction. #0xF8, W0 W0, TBLPAG #0x0000,W6 #VISI, W7 Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the VISI register using the REGOUT command. 0000 0000 0000 0001 BA0BB6 000000 000000 TBLRDL NOP NOP [W6++], [W7] Clock out contents of VISI register. Step 4: Repeat Step 3 to read other fuses. Load W6 with their respective address. Step 5: Reset device internal PC. 0000 0000 040200 000000 GOTO NOP 0x200 DS39919A-page 20 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 3.12 Verifying Code Memory, Data EEPROM Memory and Configuration Registers 3.13 Reading the Application ID Word The Application ID Word is stored in address 8005BEh in the executive code memory. To read this memory location, use the SIX control code to move this program memory location to the VISI register. Then, the REGOUT control code must be used to clock the contents of the VISI register out of the device. Table 3-12 provides the corresponding control and instruction codes that must be serially transmitted to the device to perform this operation. After the programmer has clocked out the Application ID Word, it must be inspected. If the Application ID has the value, BBh, the programming executive resides in the memory and the device can be programmed using the mechanism described in Section 4.0 “Device Programming – Enhanced ICSP”. However, if the Application ID has any other value, the programming executive does not reside in the memory; it must be loaded to memory before the device can be programmed. Section 5.4 “Programming the Programming Executive to Memory” describes the procedure for loading the programming executive to memory. To verify the code memory, read the code memory space and compare it with the copy held in the programmer’s buffer. To verify the data EEPROM and Configuration registers, follow the similar procedure. Figure 3-10 illustrates the verify process flowchart. Memory reads occur 1 byte at a time, hence 2 bytes must be read to compare with the word in the programmer’s buffer. Refer to Section 3.9 “Reading Code Memory” for implementation details of reading code memory. On the same lines, the data EEPROM and Configuration registers can be verified. Note: Code memory should be verified immediately after writing if code protection is enabled. Since Configuration registers include the device code protection bit, the device will not be readable or verifiable if a device Reset occurs after the code-protect bits are set (value = 0). FIGURE 3-10: VERIFY CODE MEMORY FLOW Start 3.14 Exiting ICSP Mode Set TBLPTR = 0 Exit the Program/Verify mode by removing VIH from MCLR/VPP as illustrated in Figure 3-11. The only requirement to exit is that an interval of P16 should elapse between the last clock and program signals on PGCx and PGDx before removing VIH. FIGURE 3-11: Read Low Byte with Post-Increment MCLR/VPP Read High Byte with Post-Increment VDD EXITING ICSP™ MODE P16 P17 VIH/VIHH VIH Does Word = Expect Data? Yes No All code memory verified? Yes End PGD = Input PGDx No Failure Report Error PGCx © 2008 Microchip Technology Inc. Advance Information DS39919A-page 21 PIC24FXXKAXXX TABLE 3-12: Command (Binary) SERIAL INSTRUCTION EXECUTION FOR READING THE APPLICATION ID WORD Data (Hex) Description Step 1: Exit Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 000000 040200 000000 200800 880190 205BE0 207841 000000 BA0890 000000 000000 000000 NOP GOTO NOP MOV MOV MOV MOV NOP TBLRDL NOP NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction. #0x80, W0 W0, TBLPAG #0x5BE, W0 #VISI, W1 [W0], [W1] Step 3: Output the VISI register using the REGOUT command. Clock out contents of the VISI register. NOP DS39919A-page 22 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 4.0 DEVICE PROGRAMMING – ENHANCED ICSP 4.1 Overview of the Programming Process This section describes the programming of the device through Enhanced ICSP and the programming executive. The programming executive resides in the executive memory (separate from user memory space), and is executed when Enhanced ICSP Programming mode is entered. The programming executive provides the mechanism for the programmer (host device) to program and verify the PIC24FXXKAXXX devices using a simple command set and communication protocol. The basic functions provided by the programming executive are: • • • • Read Memory Program Memory Blank Check Read Executive Firmware Revision Figure 4-1 illustrates the high-level overview of the programming process. Perform the following steps: 1. 2. 3. 4. 5. 6. 7. 8. 9. Enter ICSP mode. Erase the device. Verify the programming executive. Exit ICSP mode. Enter Enhanced ICSP mode. Program the code memory. Verify the code memory. Program the Configuration registers. Verify the Configuration registers. Steps 7 and 9 ensure that the programming was successful. After the programming executive is verified in memory (or loaded if not present), the PIC24FXXKAXXX family can be programmed using the command set provided in Table 4-1. The programming executive performs the low-level tasks required for erasing, programming and verifying a device. This allows the programmer to program the device by issuing the appropriate commands and data. Table 4-1 provides these commands. For detailed descriptions of each command, see Section 5.2 “Programming Executive Commands”. FIGURE 4-1: HIGH-LEVEL ENHANCED ICSP™ PROGRAMMING FLOW Start TABLE 4-1: Command SCHECK READC READD READP PROGC PROGD COMMAND SET SUMMARY Description Sanity check. Read Device ID registers. Read data EEPROM memory. Read Code register. Write User ID. Program and verify one word of data EEPROM memory. Program and verify one row of code memory or one Configuration register. Query if the code memory is blank. Query the software version. Enter ICSP™ Mode Perform Chip Erase Exit ICSP Mode PROGP QBLANK QVER Enter Enhanced ICSP Mode Program and Verify Code Memory Program and Verify Data EEPROM Memory Program and Verify Configuration Bits The programming executive uses the device’s data RAM for variable storage and program execution. After the programming executive is run, no assumptions should be made about the contents of the data RAM. Exit Enhanced ICSP Mode End © 2008 Microchip Technology Inc. Advance Information DS39919A-page 23 PIC24FXXKAXXX 4.2 Confirming the Presence of the Programming Executive 4.3 4.3.1 Entering Enhanced ICSP Mode LOW-VOLTAGE ENTRY Before beginning programming, confirm if the programming executive is stored in the executive memory and perform the following: 1. 2. Enter In-Circuit Serial Programming mode (ICSP). Read the unique Application ID Word stored in the executive memory. Perform the following steps to enter Enhanced ICSP Program/Verify mode using MCLR: 1. 2. 3. Briefly drive the MCLR pin high, and then low. Clock a 32-bit key sequence into PGDx. Drive the MCLR high within a specified period and continue to hold high. Figure 4-2 illustrates this procedure. If the programming executive is resident, the Application ID Word is BBh, which means programming can resume as normal. However, if the Application ID Word is not BBh, the programming executive must be programmed to executive code memory using the method described in Section 5.4 “Programming the Programming Executive to Memory”. Section 3.0 “Device Programming – ICSP” describes the ICSP programming method. Section 3.13 “Reading the Application ID Word” describes the procedure for reading the Application ID Word in ICSP mode. Figure 4-3 illustrates this procedure. The programming voltage applied to MCLR is VIH, which is essentially VDD in the case of PIC24FXXKAXXX devices. There is no minimum time requirement for holding at VIH. After VIH is removed, an interval of at least P18 must elapse before presenting the key sequence on PGDx. The key sequence is a specific 32-bit pattern: ‘0100 1101 0100 0011 0100 1000 0101 0000‘ (more easily remembered as 4D434850h in hexadecimal format). The device will enter Program/Verify mode only if the key sequence is valid. The MSB of the most significant nibble must be shifted in first. Once the key sequence is complete, VIH must be applied to MCLR and held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P19 and P7 must elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. FIGURE 4-2: CONFIRMING PRESENCE OF PROGRAMMING EXECUTIVE Start Enter ICSP™ Mode 4.3.2 HIGH-VOLTAGE ENTRY Read the Application ID from Address 805BEh Is Application ID BBh? Yes Prog. Executive is Resident in Memory No The procedure for entering Enhanced ICSP Program/Verify mode using the VPP pin is the same as entering the mode using MCLR. The only differences are that the programming voltage applied to VPP is VIHH, and before presenting the key sequence on PGDx, an interval of at least P18 should elapse. Figure 4-4 illustrates this procedure. Once the key sequence is complete, an interval of at least P19 should elapse and the VIHH should be reduced to VIH. The voltage, VIH, must be applied to VPP and held at that level for as long as the Program/Verify mode is to be maintained. An interval of at least P19 and P7 should elapse before presenting data on PGDx. Signals appearing on PGDx before P7 has elapsed will not be interpreted as valid. On successful entry, the program memory can be accessed and programmed in serial fashion. While in the Program/Verify mode, all unused I/Os are placed in the high-impedance state. Prog. Executive must be Programmed Finish DS39919A-page 24 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 4-3: ENTERING ENHANCED ICSP™ MODE USING LOW-VOLTAGE ENTRY P6 MCLR P14 VIH P19 VIH P7 VDD Program/Verify Entry Code = 4D434850h PGDx 0 b31 PGCx P18 P1A P1B 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 0 b0 FIGURE 4-4: ENTERING ENHANCED ICSP™ MODE USING HIGH-VOLTAGE ENTRY P6 VIHH VPP VDD Program/Verify Entry Code = 4D434850h PGDx PGCx P18 P1A P1B 0 b31 1 b30 0 b29 0 b28 1 b27 ... 0 b3 0 b2 0 b1 0 b0 P7 4.4 Blank Check The term “Blank Check” implies verifying if the device has been successfully erased and has no programmed memory locations. A blank or erased memory location is always read as ‘1’. The Device ID registers (FF0002h:FF0000h) can be ignored by the Blank Check as this region stores device information that cannot be erased. The device Configuration registers are also ignored by the Blank Check. Additionally, all unimplemented memory space should be ignored by the Blank Check. The QBLANK command is used for the Blank Check. It determines if the code memory is erased by testing these memory regions. A ‘BLANK’ or ‘NOT BLANK’ response is returned. If it is determined that the device is not blank, it must be erased before attempting to program the device. Figure 4-5 illustrates an example flowchart for programming code memory. In this example, all 5.5K instruction words of a PIC24FXXKAXXX device are programmed. • First, the number of commands to send (titled ‘RemainingCmds’ in the flowchart) is set to 176, and the destination address (called ‘BaseAddress’) is set to ‘0’. • Next, one write block in the device is programmed with a PROGP command. Each PROGP command contains data for one row of code memory of the PIC24FXXKAXXX device. • After the first command is processed successfully, ‘RemainingCmds’ is decremented by 1 and compared with 0. Since there are more PROGP commands to be sent, ‘BaseAddress’ is incremented by 40h to point to the next row of memory. On the second PROGP command, the second row is programmed. This process is repeated until the entire device is programmed. Special handling should not be performed when a panel boundary is crossed. 4.5 4.5.1 Code Memory Programming PROGRAMMING METHODOLOGY Code memory is programmed with the PROGP command. PROGP programs one row of code memory, starting from the memory address specified in the command. The number of PROGP commands required to program a device depends on the number of write blocks that must be programmed in the device. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 25 PIC24FXXKAXXX 4.5.2 PROGRAMMING VERIFICATION 4.6 4.6.1 Data EEPROM Programming PROGRAMMING METHODOLOGY After the code memory is programmed, the contents of the memory can be verified to ensure that the programming is successful. Verification requires the code memory to be read back and compared with the copy held in the programmer‘s buffer. The READP command can be used to read back all of the programmed code memory. Alternatively, you can have the programmer perform the verification after the entire device is programmed using a checksum computation. The programming executive uses the PROGD command to program the data EEPROM. Figure 4.7 illustrates this process. • First, the number of words to program (RemainingWords) is based on the device size and the destination address (DestAddress) is set to 0. In this example, 256 words of data EEPROM will be programmed. • The first PROGD command programs the first word of data EEPROM. • Once the command completes successfully, ‘RemainingWords’ is decremented by 1 and compared with 0. • Since there are 255 more words to program, ‘BaseAddress’ is incremented by 02h to point to the next word of data EEPROM. • This process is then repeated until all 256 words of data EEPROM are programmed. FIGURE 4-5: FLOWCHART FOR PROGRAMMING CODE MEMORY Start BaseAddress = 00h RemainingCmds = 176 4.6.2 Send PROGP Command to Program BaseAddress PROGRAMMING VERIFICATION Is PROGP response PASS? Yes RemainingCmds = RemainingCmds – 1 BaseAddress = BaseAddress + 40h No Are RemainingCmds ‘0‘? Yes End No Once the data EEPROM is programmed, the contents of the memory can be verified to ensure if the programming was successful. Verification requires the data EEPROM to be read back and compared with the copy held in the programmer‘s buffer. The READD command reads back the programmed data EEPROM. Alternatively, the programmer can perform the verification once the entire device is programmed using a checksum computation, as described in Section 6.1.1 “Checksum Computation”. Failure Report Error DS39919A-page 26 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 4-6: FLOWCHART FOR PROGRAMMING DATA EEPROM Start RemainingWords = 256 (100h) BaseAddress = 0 4.7.1 PROGRAMMING METHODOLOGY Configuration bits may be programmed, a single byte at a time, using the PROGP command. This command specifies the configuration data and Configuration register address. When Configuration bits are programmed, any unimplemented or reserved bits must be programmed with a ‘1’. Eight PROGP commands are required to program the Configuration bits. Figure 4-7 illustrates the flowchart for Configuration bit programming. Note: If the General Segment Code-Protect bit (GCP) is programmed to ‘0‘, code memory is code-protected and cannot be read. Code memory must be verified before enabling code protection. See Section 4.7.3 “Code-Protect Configuration Bits” for more information on code-protect Configuration bits. Send PROGD Command to Program BaseAddress Is PROGD response PASS? Yes RemainingWords = RemainingWords – 1 BaseAddress = BaseAddress + 02h No Are RemainingWords ‘0’? Yes Finish No 4.7.2 PROGRAMMING VERIFICATION Failure Report Error 4.7 Configuration Bits Programming After the Configuration bits are programmed, the contents of memory should be verified to ensure that the programming was successful. Verification requires the Configuration bits to be read back and compared against the copy held in the programmer‘s buffer. The READP command reads back the programmed Configuration bits and verifies that the programming was successful. The PIC24FXXKAXXX family has eight Configuration registers. The bits of these registers can be set or cleared to select various device configurations. There are three types of Configuration bits: • System Operation Bits These bits determine the power-on settings for system-level components, such as the oscillator and Watchdog Timer. • Code-Protect Bits These bits prevent program memory from being read and written. • Device ID Bits These are read-only bits, which are located from FF0000 to FF0003, and are unique to every device. Table 4-2 provides the Configuration registers. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 27 PIC24FXXKAXXX 4.7.3 CODE-PROTECT CONFIGURATION BITS The FBS and FGS Configuration registers are special Configuration registers which control the code protection for the boot segment and general segment, respectively. For each segment, two forms of code protection are provided. One form prevents code memory from being written (write protection), while the other prevents it from being read (read protection). The BWRP and GWRP bits control write protection and the BSS0 and GSS0 bits control read protection. When write protection is enabled, any programming operation to code memory will fail. When read protection is enabled, any read from code memory will cause a 00h to be read, regardless of the actual contents of code memory. Since the programming executive always verifies what it programs, attempting to program code memory with read protection enabled also results in failure. It is imperative that all code protection bits should be ‘1’ while the device is being programmed, and verified. Only after the device is programmed and verified should any of the above bits be programmed to ‘0’ (see Section 4.7 “Configuration Bits Programming”). Note: All bits in the FBS and FGS Configuration registers can only be programmed to a value of ‘0‘.Bulk Erasing the chip is the only way to reprogram code-protect bits from on (‘0’) to off (‘1’). TABLE 4-2: Bit Field BOREN PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION Register FPOR Description Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled 10 = Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled 01 = Brown-out Reset controlled with the SBOREN bit setting 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled Brown-out Reset Voltage bits 11 = VBOR set to 1.8V min 10 = VBOR set to 2.0V min 01 = VBOR set to 2.7V min 00 = Downside protection on POR enabled – “Zero-power” selected Boot Segment Program Flash Code Protection bit 1 = No protection 0 = Standard security enabled Boot Segment Program Flash Size Selection bits 11 = No boot program Flash segment 10 = Boot program Flash segment starts at 200h, ends at 000AFEh 01 = Boot program Flash segment starts at 200h, ends at 0015FEh 00 = Reserved Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger functions enabled Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock BORV FPOR BSS0 FBS BSZ FBS BWRP FBS DEBUG FICD DSWDTEN FDS DSWCKSEL FDS Note 1: 2: Applies only to the 28-pin device. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. DS39919A-page 28 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 4-2: Bit Field DSWDTPS PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FDS Description Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) Deep Sleep Zero-Power BOR Enable bit 1 = Zero-Power BOR enabled in Deep Sleep 0 = Zero-Power BOR disabled in Deep Sleep (does not affect operation in non Deep Sleep modes) Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled DSZPBOR FDS FCKSM FOSC FNOSC FOSCSEL Oscillator Selection bits 000 = Fast RC Oscillator (FRC) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary Oscillator (XT, HS, EC) 011 = Primary Oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary Oscillator (SOSC) 101 = Low-Power RC Oscillator (LPRC) 110 = Reserved; do not use 111 = Fast RC Oscillator with divide-by-N (FRCDIV) FWDT Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security enabled General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected ICD Pin Placement Select bit 11 = ICD EMUC/EMUD pins are shared with PGEC1/PGED1 10 = ICD EMUC/EMUD pins are shared with PGEC2/PGED2 01 = ICD EMUC/EMUD pins are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN GSS0 FGS GWRP FGS ICS FICD Note 1: 2: Applies only to the 28-pin device. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 29 PIC24FXXKAXXX TABLE 4-2: Bit Field IESO PIC24FXXKAXXX FAMILY CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FOSCSEL Description Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Alternate I2C1 Pin Mapping bit(1) 0 = Alternate location for SCL1/SDA1 pins 1 = Default location for SCL1/SDA1 pins MCLR Pin Enable bit(2) 1 = MCLR pin enabled; RA5 input pin disabled 0 = RA5 input pin enabled; MCLR disabled CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD = 11 or 00) 0 = CLKO output disabled Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected (4 MHz-25 MHz) 01 = XT Oscillator mode selected (100 kHz-4 MHz) 00 = External Clock mode selected Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency greater than 8 MHz 10 = Primary oscillator/external clock input frequency between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency less than 100 kHz 00 = Reserved, do not use Power-up Timer Enable bit 0 = PWRT disabled 1 = PWRT enabled RTCC Reference Clock Select bit 1 = RTCC uses SOSC as reference clock 0 = RTCC uses LPRC as reference clock Secondary Oscillator Select bit 1 = Secondary oscillator configured for high-power operation 0 = Secondary oscillator configured for low-power operation WDT Prescaler 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT disabled 0 = Windowed WDT enabled I2C1SEL(1) FPOR MCLRE(2) FPOR OSCIOFNC FOSC POSCMD FOSC POSCFREQ FOSC PWRTEN FPOR RTCCKSEL FDS SOSCSEL FOSC WDTPRE FWDT WDTPOST FWDT WINDIS FWDT Note 1: 2: Applies only to the 28-pin device. The MCLRE fuse can only be changed when using the VPP-Based Test mode entry. This prevents a user from accidentally locking out the device from low-voltage test entry. DS39919A-page 30 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX FIGURE 4-7: CONFIGURATION BIT PROGRAMMING FLOW Start ConfigAddress = F80000h Send PROGP Command Is PROGP response PASS? Yes Is ConfigAddress F80010h? Yes End No ConfigAddress = ConfigAddress + 2 No Failure Report Error 4.8 Exiting the Enhanced ICSP Mode FIGURE 4-8: To exit the Program/Verify mode, remove VIH from MCLR/VPP, as illustrated in Figure 4-8. For exiting, an interval P16 should elapse between the last clock and program signals on PGCx and PGDx before removing VIH. EXITING ENHANCED ICSP™ MODE P16 P17 VIH/VIHH MCLR/VPP VDD VIH PGDx PGCx PGDx = Input © 2008 Microchip Technology Inc. Advance Information DS39919A-page 31 PIC24FXXKAXXX 5.0 THE PROGRAMMING EXECUTIVE FIGURE 5-1: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA RECEIVED FROM DEVICE P1 1 PGCx P1A P1B P2 PGDx MSb 14 13 12 11 ... 5 4 3 2 1 LSb P3 2 3 4 5 6 11 12 13 14 15 16 This section describes the programming executive communication, programming executive commands, programming responses, programming the programming executive to memory and programming verification. 5.1 Programming Executive Communication The programmer and the programming executive have a master-slave relationship, where the programmer is the master programming device and the programming executive is the slave. Communication is initiated by the programmer in the form of a command. Only one command at a time can be sent to the programming executive. The programming executive, in turn, only sends one response to the programmer after receiving and processing a command. The programming executive command set is described in Section 5.2 “Programming Executive Commands”. The response set is described in Section 5.3 “Programming Executive Responses”. As a 2-wire SPI is used and data transmissions are half-duplex, a simple protocol is used to control the direction of PGDx. When the programmer completes a command transmission, it releases the PGDx line and allows the programming executive to drive this line high. The programming executive keeps the PGDx line high to indicate that it is processing the command. After the programming executive has processed the command, it brings PGDx low for 15 μsec to indicate to the programmer that the response is available to be clocked out. The programmer can begin to clock out the response 23 μsec after PGDx is brought low, and it must provide the necessary amount of clock pulses to receive the entire response from the programming executive. After the entire response is clocked out, the programmer should terminate the clock on PGCx until it is time to send another command to the programming executive; Figure 5.2 displays this protocol. 5.1.1 COMMUNICATION INTERFACE AND PROTOCOL The Enhanced ICSP interface is a two-wire SPI, implemented using the PGCx and PGDx pins. The PGCx pin is used as a clock input pin; the programmer should provide the clock source. The PGDx pin is used to send the command data to, and receive response data from, the programming executive. Data transmits to the device should change on the rising edge and hold on the falling edge of PGCx. Data receives from the device change on the falling edge and holds on the rising edge of PGCx. The data transmissions are sent to the MSB first using 16-bit mode (see Figure 5-1 and Figure 5-2). 5.1.2 SPI RATE In Enhanced ICSP mode, the PIC24FXXKAXXX family devices operate from the internal Fast RC Oscillator, which has a nominal frequency of 8 MHz. This oscillator frequency yields an effective system clock frequency of 4 MHz. To ensure that the programmer does not clock too fast, it is recommended that a 4 MHz clock be provided by the programmer. FIGURE 5-2: PROGRAMMING EXECUTIVE SERIAL TIMING FOR DATA TRANSMITTED TO DEVICE P1 1 PGCx 2 3 4 5 6 11 12 13 14 15 16 P1A P1B PGDx MSb P2 14 13 12 11 ... 5 4 3 2 P3 1 LSb DS39919A-page 32 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 5.1.3 TIME-OUTS The programming executive does not use the Watchdog Timer or time-out for transmitting responses to the programmer. If the programmer does not follow the flow control mechanism using PGCx, as described in Section 5.1.1 “Communication Interface and Protocol”, it is possible that the programming executive will behave unexpectedly while trying to send a response to the programmer. Since the programming executive does not have a time-out, it is imperative that the programmer correctly follow the described communication protocol. As a safety measure, the programmer should use the command time-outs identified and listed in Table 5-1. If the command time-out expires, the programmer should reset the programming executive and start programming the device again. FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL Host Transmits Last Command Word 1 2 15 16 Programming Executive Processes Command 1 2 Host Clocks Out Response 15 16 1 2 15 16 PGCx PGDx MSB X X X LSB P8 1 P9 0 P20 MSB X X X LSB P21 MSB X X X LSB PGCx = Input PGDx = Input PGCx = Input (Idle) PGDx = Output PGCx = Input PGDx = Output 5.2 Programming Executive Commands The programming executive command set is listed in Table 5-1. This table contains the opcode, mnemonic, length, time-out and description for each command. Section 5.2.4 “Command Descriptions” provides functional details on each command. The command opcode must match one of those in the command set. Any command that is received that does not match the list in Table 5-1 returns a “NACK” response (see Section 5.3.1.1 “Opcode Field”). The command length is represented in 16-bit words as the SPI operates in 16-bit mode. The programming executive uses the command length field to determine the number of words to read from the SPI port. If the value of this field is incorrect, the command will not be properly received by the programming executive. 5.2.1 COMMAND FORMAT The programming executive commands have a general format consisting of a 16-bit header and any required data for the command (see Figure 5-4). The 16-bit header consists of a 4-bit opcode field, which is used to identify the command, followed by a 12-bit command length field. FIGURE 5-4: 15 12 11 COMMAND FORMAT 0 Length • • Opcode Command Data First Word (if required) Command Data Last Word (if required) © 2008 Microchip Technology Inc. Advance Information DS39919A-page 33 PIC24FXXKAXXX 5.2.2 PACKED DATA FORMAT 5.2.3 When 24-bit instruction words are transferred across the 16-bit SPI interface, they are packed to conserve space using the format illustrated in Figure 5-5. This format minimizes the traffic over the SPI and provides the programming executive the data that is properly aligned for performing table write operations. PROGRAMMING EXECUTIVE ERROR HANDLING FIGURE 5-5: 15 MSb2 PACKED INSTRUCTION WORD FORMAT 87 LSW1 MSb1 LSW2 0 The programming executive will “NACK” all unsupported commands. Additionally, due to the memory constraints of the programming executive, no checking is performed on the data contained in the programmer command. It is the responsibility of the programmer to command the programming executive with valid command arguments; otherwise, the programming operation might fail. Section 5.3.1.3 “QE_Code Field” provides additional information on error handling. LSWx: Least Significant 16 bits of instruction word MSbx: Most Significant bits of instruction word Note: When the number of instruction words transferred is odd, MSb2 is zero and LSW2 cannot be transmitted. TABLE 5-1: Opcode 0h 1h 2h 3h 4h 5h 6h 7h 8h 9h Ah Bh Ch Dh Eh Fh PROGRAMMING EXECUTIVE COMMAND SET Length (16-bit words) 1 3 4 N/A 4 99 N/A N/A N/A N/A 3 1 N/A N/A 4 19 Time-out 1 msec 1 msec Sanity check. Read up to (256) 8-bit words starting from the specified Device ID register. Description Mnemonic SCHECK READC READP RESERVED PROGC PROGP RESERVED RESERVED RESERVED RESERVED QBLANK QVER RESERVED RESERVED READD PROGD 1 msec/row Read up to 32K instruction words of code memory starting from the specified address.(1) N/A 5 msec 5 msec N/A N/A N/A N/A TBD 1 msec N/A N/A This command is reserved; it returns a NACK. Write an 8-bit word to the specified Device ID registers. Program up to 32 instructions (one row) of code memory at the specified address and then verify.(1) This command is reserved; it returns a NACK. This command is reserved; it returns a NACK. This command is reserved; it returns a NACK. This command is reserved; it returns a NACK. Query if the code memory is blank.(1) Query the programming executive software version. This command is reserved; it returns a NACK. This command is reserved. it returns a NACK. 1 msec/word Read up to (256) 16-bit words starting from the specified address. 5 msec Program one word of data EEPROM memory at the specified address and then verify. Legend: TBD = To Be Determined Note 1: One row of code memory consists of (32) 24-bit words. Refer to Table 2-3 for device-specific information. DS39919A-page 34 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 5.2.4 COMMAND DESCRIPTIONS The commands supported by the programming executive are described in S ection 5.2.5 “SCHECK Command” t hrough S ection 5.2.13 “QVER Command” . When this command is used to read the Device ID registers, the upper byte in every data word returned by the programming executive is 00h and the lower byte contains the Device ID register value. Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1100h 2+N Device ID Register 1 ... Device Register N Note: Reading unimplemented memory will cause the programming executive to reset. Ensure that only memory locations present on a particular device are accessed. 5.2.5 15 SCHECK COMMAND 12 11 0 Length Opcode Field Opcode 0h Description Length 1h The SCHECK command instructs the programming executive to merely generate a response. This command is used as a “Sanity Check” to verify if the programming executive is operational. Expected Response (2 words): 1000h 0002h Note: This instruction is provided for development purposes only; this is not required for programming. 5.2.7 15 Opcode READD COMMAND 12 11 Reserved0 Reserved1 Addr_LS 87 Length N Addr_MSB 0 Field Opcode Eh 4h 0h Description 5.2.6 15 Opcode READC COMMAND 12 11 N Addr_LS 87 Length Addr_MSB 0 Length Reserved0 N Reserved1 Addr_MSB Addr_LS Number of 16-bit words to read (max of 256). 0h MSb of 24-bit source address. Least Significant 16 bits of 24-bit source address. Field Opcode Length N Addr_MSB Addr_LS 1h 3h Description Number of 8-bit Device ID registers to read (max. of 256). MSb of 24-bit source address. Least Significant 16 bits of 24-bit source address. The READD command instructs the programming executive to read N 16-bit words from data EEPROM memory, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: This command can only be used to read 16-bit data. The READC command instructs the programming executive to read N or Device ID registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: This command can only be used to read 8-bit or 16-bit data. Expected Response (N + 2 words): 1E00h 2+N Data word 1 ... Data word N © 2008 Microchip Technology Inc. Advance Information DS39919A-page 35 PIC24FXXKAXXX 5.2.8 15 Opcode N Reserved Addr_LS Field Opcode Length N Reserved Addr_MSB Addr_LS 2h 4h Number of 24-bit instructions to read (max. of 32768). 0h MSb of 24-bit source address. Least Significant 16 bits of 24-bit source address. Data Description Field Opcode Length Reserved Addr_MSB Addr_LS 4h 4h 0h MSb of 24-bit destination address. Least Significant 16 bits of 24-bit destination address. 8-bit data word. Addr_MSB READP COMMAND 12 11 87 Length 0 5.2.9 15 Opcode PROGC COMMAND 12 11 Reserved Addr_LS Data Description 87 Length Addr_MSB 0 The READP command instructs the programming executive to read N 24-bit words of code memory, including Configuration registers, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Note: This command can only be used to read 24-bit data. The PROGC command instructs the programming executive to program a single User ID register located at the specified memory address. After the specified data word has been programmed to code memory, the programming executive verifies the programmed data against the data in the command. Expected Response (2 words): 1400h 0002h The entire data returned in response to this command uses the packed data format described in Section 5.2.2 “Packed Data Format”. Expected Response (2 + 3 * N/2 words for N even): 1200h 2 + 3 * N/2 LSB program memory word 1 ... LSB data word N Expected Response (4 + 3 * (N – 1)/2 words for N odd): 1200h 4 + 3 * (N – 1)/2 LSB program memory word 1 ... MSB of program memory word N (zero-padded) Note: Reading unimplemented memory will cause the programming executive to reset. Ensure that only memory locations present on a particular device are accessed. 5.2.10 15 Opcode PROGD COMMAND 12 11 Reserved Addr_LS D_1 87 Length Addr_MSB 0 Field Opcode Length Reserved Addr_MSB Addr_LS D_1 Fh 4h 0h Description MSB of 24-bit source address. Least Significant 16 bits of 24-bit source address. 16-bit data word. The PROGD command instructs the programming executive to program one word (16-bit) of data EEPROM memory, starting from the 24-bit address specified by Addr_MSB and Addr_LS. Once one word of data EEPROM has been programmed, the programming executive verifies the programmed data against the data in the command. DS39919A-page 36 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX Expected Response (2 words): 1F00h 0002h Note: Refer to Table 2-4 for data EEPROM memory size information. 5.2.12 15 Opcode QBLANK COMMAND 12 11 Length PSize DSize Description Ah 3h Length of program memory to check in 24-bit words (max. of 49152). 0h Length of data memory to check in 16-bit words (max. of 2048). 0 Reserved Field Opcode Length PSize Reserved DSize 5.2.11 15 Opcode PROGP COMMAND 12 11 Reserved Addr_LS D_1 D_2 ... D_48 87 Length Addr_MSB 0 Field Opcode Length Reserved Addr_MSB Addr_LS D_1 D_2 ... D_48 5h 33h 0h Description The QBLANK command queries the programming executive to determine if the contents of code memory and code-protect Configuration bits (GCP and GWRP) are blank (contain all ‘1’s). The size of the code memory to check should be specified in the command. The Blank Check for code memory begins at 0h and advances toward larger addresses for the specified number of instruction words. QBLANK returns a QE_Code of F0h if the specified code memory and code-protect bits are blank; otherwise, it returns a QE_Code of 0Fh. Expected Response (2 words for blank device): 1AF0h 0002h Expected Response (2 words for non-blank device): 1A0Fh 0002h Note: QBLANK does not check the system operation Configuration bits as these bits are not set to ‘1’ when a Chip Erase is performed. MSb of 24-bit destination address. Least Significant 16 bits of 24-bit destination address. 16-bit data word 1. 16-bit data word 2. 16-bit data word 3 through 47. 16-bit data word 48. The PROGP command instructs the programming executive to program one row of code memory to the specified memory address. Programming begins with the row address specified in the command. The destination address should be a multiple of 40h. The data to program to memory, located in command words, D_1 through D_48, should be arranged using the packed instruction word format depicted in Figure 5-5. After the entire data is programmed to code memory, the programming executive verifies the programmed data against the data in the command. The PROGP command is also used to program Configuration Words. While PROGP is used to program Configuration Words, the length in the command should be four. Only one Configuration Word at a time can be programed. The unimplemented bits of the Configuration Word should be stuffed with ‘1’s. Expected Response (2 words): 1500h 0002h Note: Refer to Table 2-3 for code memory size information. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 37 PIC24FXXKAXXX 5.2.13 15 Opcode Field Opcode Length Bh 1h QVER COMMAND 12 11 Length Description 0 5.3.1 RESPONSE FORMAT All programming executive responses have a general format consisting of a two-word header and any required data for the command. 15 Opcode 12 11 87 QE_Code 0 Last_Cmd Length The QVER command queries the version of the programming executive software stored in the test memory. The “version.revision” information is returned in the response‘s QE_Code using a single byte in the following format: Main version in upper nibble and revision in the lower nibble (i.e., 23h stands for version 2.3 of the programming executive software). Expected Response (2 words): 1BMNh (“MN” stands for version M.N) 0002h D_1 (if applicable) ... D_N (if applicable) Field Opcode Last_Cmd QE_Code Length D_1 D_N Description Response opcode. Programmer command that generated the response. Query code or error code. Response length in 16-bit words (includes 2 header words). First 16-bit data word (if applicable). Last 16-bit data word (if applicable). 5.3 Programming Executive Responses The programming executive sends a response to the programmer for each command that it receives. The response indicates if the command was processed correctly. It includes any required response data or error data. The programming executive response set is provided in Table 5-2. This table contains the opcode, mnemonic and description for each response. The response format is described in Section 5.3.1 “Response Format”. 5.3.1.1 Opcode Field TABLE 5-2: Opcode 1h 2h 3h PROGRAMMING EXECUTIVE RESPONSE OPCODES Mnemonic Description Command successfully processed. Command unsuccessfully processed. Command not known. The opcode is a 4-bit field in the first word of the response. The opcode indicates how the command was processed (see Table 5-2). If the command was processed successfully, the response opcode is PASS; if there was an error in processing the command, the response opcode is FAIL and the QE_Code indicates the reason for the failure. If the command sent to the programming executive is not identified, the programming executive returns a NACK response. PASS FAIL NACK 5.3.1.2 Last_Cmd Field The Last_Cmd is a 4-bit field in the first word of the response and it indicates the command that the programming executive processed. As the programming executive can process only one command at a time, this field is technically not required. However, it can be used to verify if the programming executive correctly received the command that the programmer transmitted. DS39919A-page 38 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 5.3.1.3 QE_Code Field The QE_Code is a byte in the first word of the response. This byte is used to return data for query commands and error codes for all of the other commands. When the programming executive processes one of the two query commands (QBLANK or QVER), the returned opcode is always PASS and the QE_Code holds the query response data. Table 5-3 provides the format of the QE_Code for both queries. The response to the READP command uses the packed instruction word format described in Section 5.2.2 “Packed Data Format”. When reading an odd number of program memory words (N odd), the response to the READP command is (3 * (N + 1)/2 + 2) words. When reading an even number of program memory words (N even), the response to the READP command is (3 * N/2 + 2) words. 5.4 Programming the Programming Executive to Memory TABLE 5-3: Query QE_Code FOR QUERIES QE_Code This section describes the programming of the programming executive to memory and also provides the procedure to perform this. QBLANK 0Fh = Code memory is NOT blank F0h = Code memory is blank QVER 0xMN, where programming executive software version = M.N (i.e., 32h stands for version 3.2 of the programming executive software) 5.4.1 OVERVIEW If it is determined that the programming executive is not present in the executive memory (as described in Section 4.2 “Confirming the Presence of the Programming Executive”), it must be programmed into the executive memory using ICSP, as described in Section 3.0 “Device Programming – ICSP”. Storing the programming executive to executive memory is the same as normal programming of code memory: The executive memory should be erased and then the programming executive must be programmed 32 words at a time. Erasing the last eight words causes the device diagnostic data in the Diagnostic Words at addresses 8007F0h to 8007FEh to be erased. In order to retain these, the memory locations should be read and stored, and then be reprogrammed in the last eight words of program memory. Table 5-5 provides this control flow. When the programming executive processes any command other than a query, the QE_Code represents an error code. Table 5-4 provides the supported error codes. If a command is successfully processed, the returned QE_Code is set to 0h, which indicates that there was no error in the command processing. If the verify of the programming for the PROGP or PROGC command fails, the QE_Code is set to 1h. For all other programming executive errors, the QE_Code is 2h. TABLE 5-4: QE_Code 0h 1h 2h QE_Code FOR NON-QUERY COMMANDS Description No error. Verify failed. Other error. 5.3.1.4 Response Length The response length indicates the length of the programming executive’s response in 16-bit words. This field includes the two words of the response header. With the exception of the response for the READP command, the length of each response is only two words. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 39 PIC24FXXKAXXX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE Data (Hex) Description Step 1: Exit Reset vector and erase the executive memory. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 000000 040200 000000 200800 880190 207F00 2000C2 000000 BA1931 000000 000000 2405A0 883B00 200800 880190 200001 000000 BB0881 000000 000000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 000000 NOP GOTO NOP MOV MOV MOV MOV NOP TBLRDL NOP NOP MOV MOV MOV MOV MOV NOP TBLWTL NOP NOP BSET NOP NOP 0x200 Step 2: Initialize pointers to read Diagnostic Words for storage in W6-W13. #0x80, W0 W0, TBLPAG #0x07F0, W1 #0xC, W2 Step 3: Repeat this step eight times to read Diagnostic Words, storing them in W registers, W6-W13. [W1++],[W2++] Step 4: Initialize the NVMCON to erase the executive memory. #0x405A, W0 W0, NVMCON #0x80, W0 W0, TBLPAG #0x00, W1 W1, [W1] Step 5: Initiate the erase cycle. NVMCON, #15 Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP NOP Clock out contents of the VISI register NOP Step 7: Repeat Steps 5 and 6 to erase the rest of the executive memory. W1 should be incremented by 100h each time to point to the next four rows. Step 8: Initialize the NVMCON to program 32 instruction words. 0000 0000 0000 0000 0000 0000 240041 883B01 200800 880190 EB0280 000000 MOV MOV MOV MOV CLR NOP #0x4004, W1 W1, NVMCON #0x80, W0 W0, TBLPAG W5 Step 9: Initialize TBLPAG and the Write Pointer (W2). DS39919A-page 40 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 5-5: Command (Binary) PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) Description Step 10: Load W0:W2 with the next two words of packed programming executive code. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 20 MOV 21 MOV 22 MOV EB0300 000000 BB0BB6 000000 000000 BBDBB6 000000 000000 BBEBB6 000000 000000 BB1BB6 000000 000000 CLR NOP TBLWTL NOP NOP TBLWTH.B NOP NOP TBLWTH.B NOP NOP TBLWTL NOP NOP #, W0 #, W1 #, W2 W4 [W4++], [W5] Step 11: Set the Read Pointer (W6) and load the (next four write) latches. [W4++], [W5++] [W4++], [++W5] [W4++], [W5++] Step 12: Repeat Steps 10 and 11, sixteen times, to load the write latches for the 32 instructions. Step 13: Initiate the programming cycle. 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 A8E761 000000 000000 040200 000000 803B02 883C22 000000 000000 000000 040200 000000 BSET NOP NOP NVMCON, #15 Step 14: Repeatedly read the NVMCON register and poll for WR bit to get cleared. GOTO 0x200 NOP MOV NVMCON, W2 MOV W2, VISI NOP NOP Clock out contents of the VISI register. NOP GOTO NOP 0x200 Step 15: Reset the device internal PC. Step 16: Repeat Steps 8 through 15 until all the last, but one (31) row of executive memory, has been programmed. Step 17: Repeat Steps 10 and 11, 12 times, to load the first 24 write latches. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 41 PIC24FXXKAXXX TABLE 5-5: Command (Binary) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED) Data (Hex) BB1A86 000000 000000 BB1A87 000000 000000 BB1A88 000000 000000 BB1A89 000000 000000 BB1A8A 000000 000000 BB1A8B 000000 000000 BB1A8C 000000 000000 BB1A8D 000000 000000 TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP TBLWTL NOP NOP W6, [W5++] Description Step 18: Load the saved Diagnostic Words in last eight write latches. W7, [W5++] W8, [W5++] W9, [W5++] W10, [W5++] W11, [W5++] W12, [W5++] W13, [W5++] Step 19: Repeat Steps 13 through 15. 5.5 Programming Verification After the programming executive is programmed to the executive memory using ICSP, it must be verified. Verify by reading out the contents of the executive memory and comparing it with the image of the programming executive stored in the programmer. Read the contents of the executive memory using the same method described in Section 3.9 “Reading Code Memory”. Table provides the procedure for reading the executive memory. Note: In Step 2 of Table 5-6, the TBLPAG register is set to 80h, such that the executive memory may be read. DS39919A-page 42 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX TABLE 5-6: Command (Binary) READING EXECUTIVE MEMORY Data (Hex) Description Step 1: Exit the Reset vector. 0000 0000 0000 0000 0000 0000 0000 0000 000000 040200 000000 200800 880190 EB0300 207847 000000 NOP GOTO NOP MOV MOV CLR MOV NOP 0x200 Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction. #0x80, W0 W0, TBLPAG W6 #VISI, W7 Step 3: Initialize the Write Pointer (W7) to point to the VISI register. Step 4: Read and clock out the contents of the next two locations of the executive memory through the VISI register using the REGOUT command. 0000 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0001 0000 0000 0000 0000 0001 0000 0000 0000 BA1B96 000000 000000 000000 BADBB6 000000 000000 BAD3D6 000000 000000 000000 BA0BB6 000000 000000 000000 040200 000000 TBLRDL [W6], [W7] NOP NOP Clock out contents of VISI register. NOP TBLRDH [W6++], [W7] NOP NOP TBLRDH.B [++W6], [W7--] NOP NOP Clock out contents of VISI register. NOP TBLRDL [W6++], [W7] NOP NOP Clock out contents of VISI register. NOP GOTO NOP 0x200 Step 5: Reset the device internal PC. Step 6: Repeat Steps 4 and 5 until the entire executive memory is read. © 2008 Microchip Technology Inc. Advance Information DS39919A-page 43 PIC24FXXKAXXX 6.0 DEVICE ID 6.1 6.1.1 Checksums CHECKSUM COMPUTATION The Device ID region of memory can be used to determine the mask, variant and manufacturing information about the device. The Device ID region is 2 x 16 bits and it can be read using the READC command. This region of memory is read-only and can also be read when code protection is enabled. Table 6-1 provides the Device ID for each device; Table 6-2 provides the Device ID registers; Table 6-3 describes the bit field of each register. Checksums for the PIC24FXXKAXXX family are 16 bits. The checksum is calculated by summing the following: • Contents of the code memory locations • Contents of the Configuration registers Table 6-4 describes how to calculate the checksum for each device. All memory locations are summed, one byte at a time, using only their native data size. More specifically, Configuration registers are summed by adding the lower two bytes of these locations (the upper byte is ignored) while the code memory is summed by adding all three bytes of the code memory. TABLE 6-1: Device ID PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 PIC24F04KA200 PIC24F04KA201 DEVICE IDs DEVID 0D08h 0D01h 0D0Ah 0D03h 0D02h 0D00h TABLE 6-2: Address FF0000h FF0002h PIC24FXXKAXXX DEVICE ID REGISTERS Bit Name 15 DEVID DEVREV 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 FAMID — DEV REV TABLE 6-3: Bit Field FAMID DEV REV DEVICE ID BITS DESCRIPTION Register DEVID DEVID DEVREV Description Encodes the family ID of the device. Encodes the individual ID of the device. Encodes the revision number of the device. TABLE 6-4: Device CHECKSUM COMPUTATION Read Code Protection Checksum Computation Erased Checksum Value 0xC334 0x0000 0xE434 0x0000 0x74B4 0x0000 Chip Checksum with 0xAAAAAA at 0x00 Location and at Last Location 0xC136 0x0000 0xE236 0x0000 0x72B6 0x0000 PIC24F16KAXXX PIC24F08KAXXX PIC24F04KAXXX Disabled Enabled Disabled Enabled Disabled Enabled CFGB + SUM (0:002BFE) 0 CFGB + SUM (0:0015FE) 0 CFGB + SUM (0:000AFE) 0 Description Legend: Item SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory) CFGB = Configuration Block (masked), Byte sum of (FBS & 0x000F + FGS & 0x0003 + FOSCSEL & 0x0087 + FOSC & 0x00DF + FWDT & 0x00DF + FPOR & 0x00FB + FICD & 0x00C3 + FDS & 0x00FF) DS39919A-page 44 Advance Information © 2008 Microchip Technology Inc. PIC24FXXKAXXX 7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS STANDARD OPERATING CONDITIONS TABLE 7-1: Standard Operating Conditions Operating Temperature: 0°C to +70°C and programming: +25°C is recommended. Param Symbol No. D111 D112 D113 D031 D041 D042 D080 D090 D012 P1 P1A P1B P2 P3 P4 P4A P5 VDD IPP IDDP VIL VIH VIHH VOL VOH CIO TPGC TPGCL TPGCH TSET1 THLD1 TDLY1 TDLY1A TDLY2 Characteristic Supply Voltage During Programming Programming Current on MCLR Supply Current During Programming Input Low Voltage Input High Voltage Programing Voltage on VPP Output Low Voltage Output High Voltage Capacitive Loading on I/O pin (PGDx) Serial Clock (PGCx) Period Serial Clock (PGCx) Low Time Serial Clock (PGCx) High Time Input Data Setup Time to Serial Clock ↑ Input Data Hold Time from PGCx ↑ Delay Between 4-Bit Command and Command Operand Delay Between 4-Bit Command Operand and the Next 4-Bit Command Delay Between Last PGCx ↓ of Command Byte and First PGCx ↑ of Read of Data Word VDD ↑ Setup Time to MCLR ↑ Input Data Hold Time from MCLR ↑ VPP↓ (from VIHH to VIH) Delay Between Last PGCx ↓ of Command Byte and PGDx ↑ by Programming Executive Programming Executive Command Processing Time PGCx Low Time After Programming Chip Erase Time Page (4 rows) Erase Time Row Programming Time MCLR Rise Time to Enter ICSP™ mode Data Out Valid from PGCx ↑ Delay Between Last PGCx ↓ and MCLR ↓ MCLR ↓ to VDD ↓ Delay Between First MCLR ↓ and First PGCx ↑ for Key Sequence on PGDx Delay Between Last PGCx ↓ for Key Sequence on PGDx and Second MCLR ↑ Min VDDCORE — — VSS 0.8 VDD VDD +1.5 — 1.4 — 125 50 50 15 15 40 40 20 Max 3.60 50 2 0.2 VDD VDD 9 0.4 — 50 — — — — — — — — Units V μA mA V V V V V pF ns ns ns ns ns ns ns ns Conditions Normal programming — — — — — IOL = 8.5 mA @ 3.6V IOH = -3.0 mA @ 3.6V To meet AC specifications — — — — — — — — P6 P7 P8 TSET2 THLD2 TDLY3 100 25 12 — — — ns ms μs — — — P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 TDLY4 TDLY6 TDLY7 TDLY10 TDLY9 TR TVALID TDLY10 THLD3 TKEY1 TKEY2 40 400 5 5 2 — 10 0 — 40 1 — — — — — 1.0 — — 100 — — μs ns ms ms ms μs ns s ns ns ms — — — — — — — — — — — © 2008 Microchip Technology Inc. Advance Information DS39919A-page 45 PIC24FXXKAXXX TABLE 7-1: STANDARD OPERATING CONDITIONS (CONTINUED) Standard Operating Conditions Operating Temperature: 0°C to +70°C and programming: +25°C is recommended. Param Symbol No. P20 TDLY11 Characteristic Delay Between PGDx ↓ by Programming Executive and First PGCx↑ of Reception of Response Delay Between Programming Executive Command Response Words Min 23 Max — Units μs Conditions — P21 TDLY12 8 — ns — DS39919A-page 46 Advance Information © 2008 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2008 Microchip Technology Inc. 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