PIC24F16KA102

PIC24F16KA102 Family Data Sheet 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology © 2009 Microchip Technology Inc. Preliminary DS39927B Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39927B-page ii Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 20/28-Pin General Purpose, 16-Bit Flash Microcontrollers with nanoWatt XLP™ Technology Power Management Modes: • • • • Run – CPU, Flash, SRAM and Peripherals On Doze – CPU Clock Runs Slower than Peripherals Idle – CPU Off, Flash, SRAM and Peripherals On Sleep – CPU, Flash and Peripherals Off and SRAM On • Deep Sleep – CPU, Flash, SRAM and Most Peripherals Off - Run mode currents down to 8 μA typical - Idle mode currents down to 2 μA typical - Deep Sleep mode currents down to 20 nA typical - RTCC 490 nA, 32 kHz, 1.8V - Watchdog Timer 350 nA, 1.8V typical Analog Features: • 10-Bit, up to 9-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU): - Used for capacitance sensing - Time measurement, down to 1 ns resolution - Delay/pulse generation, down to 1 ns resolution Special Microcontroller Features: • Operating Voltage Range of 1.8V to 3.6V • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Flash Program Memory: - Erase/write cycles: 10,000 minimum - 40-years’ data retention minimum • Data EEPROM: - Erase/write cycles: 100,000 minimum - 40-years’ data retention minimum • Fail-Safe Clock Monitor • System Frequency Range Declaration bits: - Declaring the frequency range optimizes the current consumption. • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via two Pins • Programmable High/Low-Voltage Detect (HLVD) • Brown-out Reset (BOR): - Standard BOR with three programmable trip points; can be disabled in Sleep • Extreme Low-Power DSBOR for Deep Sleep, LPBOR for all other modes High-Performance CPU: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit by 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16-Bit x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture Peripheral Features: • Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions - Can run in Deep Sleep Mode • Programmable Cyclic Redundancy Check (CRC) • Serial Communication modules: - SPI, I2C™ and two UART modules • Three 16-Bit Timers/Counters with Programmable Prescaler • 16-Bit Capture Inputs • 16-Bit Compare/PWM Output • Configurable Open-Drain Outputs on Digital I/O Pins • Up to Three External Interrupt Sources Data EEPROM (bytes) Program Memory (bytes) Capture Input SRAM (bytes) Timers 16-Bit Comparators CTMU (ch) 9 9 9 9 10-Bit A/D (ch) Output Compare/ PWM UART/ IrDA® 08KA101 16KA101 08KA102 16KA102 20 20 28 28 8K 16K 8K 16K 1.5K 1.5K 1.5K 1.5K 512 512 512 512 3 3 3 3 1 1 1 1 1 1 1 1 2 2 2 2 SPI PIC24F Device 1 1 1 1 1 1 1 1 9 9 9 9 2 2 2 2 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 1 RTCC Y Y Y Y I2C™ Pins PIC24F16KA102 FAMILY Pin Diagrams 20-Pin PDIP, SSOP, SOIC(2) MCLR/VPP/RA5 PGC2/AN0/VREF+/CN2/RA0 PGD2/AN1/VREF-/CN3/RA1 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 PGD3/SOSCI/U2RTS/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 U1RTS/SDA1/CN21/RB9 U1CTS/SCL1/CN22/RB8 U1TX/INT0/CN23/RB7 28-Pin SPDIP, SSOP, SOIC(2) MCLR/VPP/RA5 AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 AN4/C1INB/C2IND/U1RX/U1BCLK/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/U2RTS/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 VDD PGD3/SDA1(1)/CN27/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/CTED2/CN14/RB12 PGC2/SCK1/CN15/RB11 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 U1RTS/SDA1/CN21/RB9 U1CTS/SCL1/CN22/RB8 U1TX/INT0/CN23/RB7 PGC3/SCL1(1)/CN24/RB6 PIC24XXKAX01 Note 1: 2: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. All device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39927B-page 2 Preliminary PIC24FXXKAX02 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Pin Diagrams (Continued) 20-Pin QFN(1,2) PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 U1RX/U1BCLK/CN6/RB2 OSCI/CLKI/AN4/C1INB/C2IND/CN30/RA2 OSCO/CLKO/AN5/C1INA/C2INC/CN29/RA3 20 19 18 17 16 15 1 14 2 3 PIC24FXXKA10213 12 4 11 5 6 7 8 9 10 PGD3/SOSCI/U2RTS/CN1/RB4 PGC3/SOSCO/T1CK/U2CTS/CN0/RA4 U1TX/INT0/CN23/RB7 U1CTS/SCL1/CN22/RB8 U1RTS/SDA1/CN21/RB9 PGD2/AN1/VREF-/CN3/RA1 PGC2/AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD VSS REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/SDI1/OCFA/C1OUT/INT1/CN12/RB14 AN11/SDO1/CTPLS/ CN13/RB13 AN12/HLVDIN/SCK1/CTED2/CN14/RB12 OC1/IC1/C2OUT/INT2/CTED1/CN8/RA6 Note 1: 2: The bottom pad of the QFN package should be connected to Vss. All device pins have a maximum voltage of 3.6V and are not 5V tolerant. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 3 PIC24F16KA102 FAMILY Pin Diagrams (Continued) 28-Pin QFN(2,3) AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR/VPP/RA5 VDD Vss REFO/SS1/T2CK/T3CK/CN11/RB15 AN10/CVREF/RTCC/OCFA/C1OUT/INT1/CN12/RB14 PGD1/AN2/C1IND/C2INB/U2TX/CN4/RB0 PGC1/AN3/C1INC/C2INA/U2RX/U2BCLK/CN5/RB1 AN4/C1INB/C2IND/U1RX/U1BCLK/CN6/RB2 AN5/C1INA/C2INC/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 28 27 26 25 24 23 22 1 2 3 4 5 6 7 21 20 19 18 17 16 15 PIC24FXXKA102 8 9 10 11 12 13 14 AN11/SDO1/CTPLS/CN13/RB13 AN12/HLVDIN/CTED2/CN14/RB12 PGC2/SCK1/CN15/RB11 PGD2/SDI1/PMD2/CN16/RB10 OC1/C2OUT/INT2/CTED1/CN8/RA6 IC1/CN9/RA7 U1RTS/SDA1/CN21/RB9 Note 1: 2: 3: Alternative multiplexing for SDA1 and SCL1 when the I2CSEL Configuration bit is set. The bottom pad of the QFN package should be connected to Vss. All device pins have a maximum voltage of 3.6V and are not 5V tolerant. DS39927B-page 4 Preliminary SOSCI/U2RTS/CN1/RB4 SOSCO/T1CK/U2CTS/CN0/RA4 VDD PGD3/SDA1(1)/CN27/RB5 PGC3/SCL1(1)/CN24/RB6 U1TX/INT0/CN23/RB7 U1CTS/SCL1/CN22/RB8 © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU ........................................................................................................................................................................................... 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 43 6.0 Data EEPROM Memory ............................................................................................................................................................. 51 7.0 Resets ........................................................................................................................................................................................ 57 8.0 Interrupt Controller ..................................................................................................................................................................... 63 9.0 Oscillator Configuration .............................................................................................................................................................. 91 10.0 Power-Saving Features............................................................................................................................................................ 101 11.0 I/O Ports ................................................................................................................................................................................... 109 12.0 Timer1 ..................................................................................................................................................................................... 111 13.0 Timer2/3 ................................................................................................................................................................................... 113 14.0 Input Capture............................................................................................................................................................................ 119 15.0 Output Compare....................................................................................................................................................................... 121 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 127 17.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 135 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 143 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 151 20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 163 21.0 High/Low-Voltage Detect (HLVD)............................................................................................................................................. 167 22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 169 23.0 Comparator Module.................................................................................................................................................................. 179 24.0 Comparator Voltage Reference................................................................................................................................................ 183 25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 185 26.0 Special Features ...................................................................................................................................................................... 189 27.0 Development Support............................................................................................................................................................... 199 28.0 Instruction Set Summary .......................................................................................................................................................... 203 29.0 Electrical Characteristics .......................................................................................................................................................... 211 30.0 Packaging Information.............................................................................................................................................................. 231 Appendix A: Revision History............................................................................................................................................................. 243 Index .................................................................................................................................................................................................. 245 The Microchip Web Site ..................................................................................................................................................................... 249 Customer Change Notification Service .............................................................................................................................................. 249 Customer Support .............................................................................................................................................................................. 249 Reader Response .............................................................................................................................................................................. 250 Product Identification System ............................................................................................................................................................ 251 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 5 PIC24F16KA102 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39927B-page 6 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 POWER-SAVING TECHNOLOGY This document contains device-specific information for the following devices: • • • • PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 All of the devices in the PIC24F16KA102 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing users to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: - Idle Mode: The core is shut down while leaving the peripherals active. - Sleep Mode: The core and peripherals that require the system clock are shut down, leaving the peripherals that use their own clock, or the clock from other devices, active. - Deep Sleep Mode: The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down. The PIC24F16KA102 family introduces a new line of extreme low-power Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. It also offers a new migration option for those high-performance applications, which may be outgrowing their 8-bit platforms, but do not require the numerical processing power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32-bit by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as C • Operational performance up to 16 MIPS 1.1.3 OSCILLATOR OPTIONS AND FEATURES The PIC24F16KA102 family offers five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • Two fast internal oscillators (FRCs): One with a nominal 8 MHz output and the other with nominal 500 kHz output. These outputs can also be divided under software control to provide clock speed as low as 31 kHz or 2 kHz. • A Phase Locked Loop (PLL) frequency multiplier, available to the External Oscillator modes and the 8 MHz FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 7 PIC24F16KA102 FAMILY The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.3 Details on Individual Family Members Devices in the PIC24F16KA102 family are available in 20-pin and 28-pin packages. The general block diagram for all devices is displayed in Figure 1-1. The devices are different from each other in two ways: 1. Flash program memory (8 Kbytes for PIC24F08KA devices, 16 Kbytes for PIC24F16KA devices). Available I/O pins and ports (18 pins on two ports for 20-pin devices and 24 pins on two ports for 28-pin devices). Alternate SCL and SDA pins are available only in 28-pin devices and not in 20-pin devices. 1.1.4 EASY MIGRATION Regardless of the memory size, all the devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also helps in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 20-pin to 28-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex. 2. 3. All other features for devices in this family are identical; these are summarized in Table 1-1. A list of the pin features available on the PIC24F16KA102 family devices, sorted by function, is provided in Table 1-2. Note: Table 1-1 provides the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams on pages 2, 3 and 4 of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 1.2 Other Special Features • Communications: The PIC24F16KA102 family incorporates a range of serial communication peripherals to handle a range of application requirements. There is an I2C™ module that supports both the Master and Slave modes of operation. It also comprises UARTs with built-in IrDA® encoders/decoders and an SPI module. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speed. The 16-deep result buffer can be used either in Sleep to reduce power, or in Active mode to improve throughput. • Charge Time Measurement Unit (CTMU) Interface: The PIC24F16KA102 family includes the new CTMU interface module, which can be used for capacitive touch sensing, proximity sensing and also for precision time measurement and pulse generation. DS39927B-page 8 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24F16KA102 FAMILY PIC24F08KA101 PIC24F16KA101 PIC24F08KA102 PIC24F16KA102 16K 5632 24 3 1 1 1 17 2 1 1 9 2 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 20-Pin PDIP/SSOP/SOIC/QFN 28-Pin SPDIP/SSOP/SOIC/QFN 23 DS39927B-page 9 Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Data EEPROM Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and delays) 8K 2816 DC – 32 MHz 16K 5632 1536 512 30 (26/4) PORTA PORTB 18 PORTA PORTB 8K 2816 Instruction Set Packages © 2009 Microchip Technology Inc. Preliminary PIC24F16KA102 FAMILY FIGURE 1-1: PIC24F16KA102 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller 8 PSV and Table Data Access Control Block 16 Data Bus 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU PORTA(1) RA 23 Address Latch Program Memory Data EEPROM Data Latch Address Bus 24 Inst Latch Inst Register Instruction Decode and Control Control Signals Timing OSCO/CLKO OSCI/CLKI Generation FRC/LPRC Oscillators Power-up Timer Start-up Timer PORTB(1) RB EA MUX Literal Data 16 16 16 Divide Support 17x17 Multiplier 16 x 16 W Reg Array Oscillator Power-on Reset Watchdog Timer DSWDT 16-Bit ALU 16 Precision Band Gap Reference BOR , VDDVSS HLVD MCLR Timer1 Timer2/3 CTMU 10-Bit ADC Comparators RTCC REFO IC1 OC1/PWM CN1-22(1) SPI1 I2C1 UART1/2 Note 1: All pins or features are not implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. DS39927B-page 10 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS Pin Number 20-Pin Function PDIP/SSOP/ SOIC AN0 AN1 AN2 AN3 AN4 AN5 AN10 AN11 AN12 U1BCLK U2BCLK C1INA C1INB C1INC C1IND C1OUT C2INA C2INB C2INC C2IND C2OUT CLKI CLKO Legend: Note 1: 2 3 4 5 7 8 17 16 15 6 5 8 7 5 4 17 5 4 8 7 14 7 8 20-Pin QFN 19 20 1 2 4 5 14 13 12 3 2 5 4 2 1 14 2 1 5 4 11 4 5 28-Pin SPDIP/ SSOP/SOIC 2 3 4 5 6 7 25 24 23 6 5 7 6 5 4 25 5 4 7 6 20 9 10 28-Pin QFN 27 28 1 2 3 4 22 21 20 3 2 4 3 2 1 22 2 1 4 3 17 6 7 I/O Input Buffer Description I I I I I I I I I O O I I I I O I I I I O I O ANA ANA ANA ANA ANA ANA ANA ANA ANA — — ANA ANA ANA ANA — ANA ANA ANA ANA — ANA — A/D Analog Inputs UART1 IrDA® Baud Clock UART2 IrDA Baud Clock Comparator 1 Input A (Positive input) Comparator 1 Input B (Negative input option 1) Comparator Input C (Negative input option 2) Comparator Input D (Negative input option 3) Comparator 1 Output Comparator 2 Input A (Positive input) Comparator 2 Input B (Negative input option 1) Comparator 2 Input C (Negative input option 2) Comparator 2 Input D (Negative input option 3) Comparator 2 Output Main Clock Input Connection System Clock Output ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 11 PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function PDIP/SSOP/ SOIC CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN11 CN12 CN13 CN14 CN15 CN16 CN21 CN22 CN23 CN24 CN27 CN29 CN30 CVREF CTED1 CTED2 CTPLS IC1 INT0 INT1 INT2 HLVDIN MCLR OC1 OCFA OSCI OSCO Legend: Note 1: 10 9 2 3 4 5 6 — 14 — 18 17 16 15 — — 13 12 11 — — 8 7 17 14 15 16 14 11 17 14 15 1 14 17 7 8 20-Pin QFN 7 6 19 20 1 2 3 — 11 — 15 14 13 12 — — 10 9 8 — — 5 4 14 11 12 13 11 8 14 11 12 18 11 14 4 5 28-Pin SPDIP/ SSOP/SOIC 12 11 2 3 4 5 6 7 20 19 26 25 24 23 22 21 18 17 16 15 14 10 9 25 20 23 24 19 16 25 20 23 1 20 25 9 10 28-Pin QFN 9 8 27 28 1 2 3 4 17 16 23 22 21 20 19 18 15 14 13 12 11 7 6 22 17 20 21 16 13 22 17 20 26 17 22 6 7 I/O Input Buffer Description I I I I I I I I I I I I I I I I I I I I I I I O I I O I I I I I I O I I O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ST ST — ST ST ST ST ANA ST — — ANA ANA HLVD Voltage Input Master Clear (device Reset) Input Output Compare/PWM Outputs Output Compare Fault A Main Oscillator Input Connection Main Oscillator Output Connection External Interrupt Inputs Comparator Voltage Reference Output CTMU Trigger Edge Input 1 CTMU Trigger Edge Input 2 CTMU Pulse Output Input Capture 1 Input Interrupt-on-Change Inputs ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared. DS39927B-page 12 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function PDIP/SSOP/ SOIC PGC1 PGD1 PGC2 PGD2 PGC3 PGD3 RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 REFO RTCC SCK1 SCL1 SDA1 SDI1 SDO1 SOSCI SOSCO SS1 Legend: Note 1: 5 4 2 3 10 9 2 3 7 8 10 1 14 — 4 5 6 — 9 — — 11 12 13 — — 15 16 17 18 18 17 15 12 13 17 16 9 10 18 20-Pin QFN 2 1 19 20 7 6 19 20 4 5 7 18 11 — 1 2 3 — 6 — — 8 9 10 — — 12 13 14 15 15 14 12 9 10 14 13 6 7 15 28-Pin SPDIP/ SSOP/SOIC 5 4 22 21 15 14 2 3 9 10 12 1 20 19 4 5 6 7 11 14 15 16 17 18 21 22 23 24 25 26 26 25 22 17, 15(1) 18, 14(1) 21 24 11 12 26 28-Pin QFN 2 1 19 18 12 11 27 28 6 7 9 26 17 16 1 2 3 4 8 11 12 13 14 15 18 19 20 21 22 23 23 22 19 14, 12 (1) 15, 11(1) 18 21 8 9 23 I/O Input Buffer Description I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I O I O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — ST I2C I2C ST — ANA ANA ST In-Circuit Debugger and ICSP™ Programming Clock In-Circuit Debugger and ICSP Programming Data In-Circuit Debugger and ICSP Programming Clock In-Circuit Debugger and ICSP Programming Data In-Circuit Debugger and ICSP Programming Clock In-Circuit Debugger and ICSP Programming Data PORTA Digital I/O PORTB Digital I/O Reference Clock Output Real-Time Clock Alarm Output SPI1 Serial Clock Input/Output I2C1 Synchronous Serial Clock Input/Output I2C1 Data Input/Output SPI1 Serial Data Input SPI1 Serial Data Output Secondary Oscillator Input Secondary Oscillator Output Slave Select Input/Frame Select Output (SPI1) ST = Schmitt Trigger input buffer, ANA = Analog level input/output, I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 13 PIC24F16KA102 FAMILY TABLE 1-2: PIC24F16KA102 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 20-Pin Function PDIP/SSOP/ SOIC T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX VDD VPP VREFVREF+ VSS Legend: Note 1: 10 18 18 12 13 6 11 20 1 3 2 19 20-Pin QFN 7 15 15 9 10 3 8 17 18 20 19 16 28-Pin SPDIP/ SSOP/SOIC 12 26 26 17 18 6 16 13, 28 1 3 2 8, 27 28-Pin QFN 9 23 23 14 15 3 13 10, 25 26 28 27 5, 24 I/O Input Buffer Description I I I I O I O P P I I P ST ST ST ST — ST — — — ANA ANA — Timer1 Clock Timer2 Clock Timer3 Clock UART1 Clear to Send Input UART1 Request to Send Output UART1 Receive UART1 Transmit Output Positive Supply for Peripheral Digital Logic and I/O Pins Programming Mode Entry Voltage A/D and Comparator Reference Voltage (low) Input A/D and Comparator Reference Voltage (high) Input Ground Reference for Logic and I/O Pin I2C™ = I2C/SMBus input buffer ST = Schmitt Trigger input buffer, ANA = Analog level input/output, Alternative multiplexing when the I2C1SEL Configuration bit is cleared. DS39927B-page 14 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) 2.1 VDD VDD Getting started with the PIC24F16KA102 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. R1 R2 MCLR VSS (1) (1) (EN/DIS)VREG VCAP/VDDCORE C1 PIC24FXXXX VSS VDD C7 C6(2) AVDD VDD VSS AVSS VDD VSS C3(2) C5(2) C4(2) Key (all values are recommendations): C1 through C6: 0.1 μF, 20V ceramic C7: 10 μF, 16V tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: See Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)” for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 2: The minimum mandatory connections are shown in Figure 2-1. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 15 PIC24F16KA102 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 μF to 0.001 μF. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 μF in parallel with 0.001 μF). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor C1 be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC24FXXXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. R1 ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R2 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39927B-page 16 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) This section applies only to PIC24FJ devices with an on-chip voltage regulator. 2.5 ICSP Pins Note: The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: • For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator • For DISVREG, tie to ground to enable the regulator, or to VDD to disable the regulator Refer to Section 25.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR ( 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data = crc_input data = bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of the VWORD bits (CRCCON) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the Most Significant bit (MSb) is shifted out, the VWORD bits decrement by one. The serial shifter continues shifting until the VWORD bits reach zero. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When the VWORD bits reach 8 (or 16), the CRCFUL bit will be set. When the VWORD bits reach 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. 20.1.2 INTERRUPT OPERATION When the VWORD bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. 20.2 20.2.1 Operation in Power Save Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 20.2.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. DS39927B-page 164 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 20.3 Registers There are four registers used to control programmable CRC operation: • • • • CRCCON CRCXOR CRCDAT CRCWDAT REGISTER 20-1: U-0 — bit 15 R-0, HSC CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 CRCCON: CRC CONTROL REGISTER U-0 — R/W-0 CSIDL R-0, HSC VWORD4 R-0, HSC VWORD3 R-0, HSC VWORD2 R-0, HSC VWORD1 R-0, HSC VWORD0 bit 8 R-1, HSC CRCMPT U-0 — R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 R/W-0 PLEN0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN > 7, or 16 when PLEN ≤ 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as ‘0’ CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 165 PIC24F16KA102 FAMILY REGISTER 20-2: R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 — bit 0 CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14 R/W-0 X: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as ‘0’ DS39927B-page 166 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 21.0 Note: HIGH/LOW-VOLTAGE DETECT (HLVD) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the High/Low-Voltage Detect, refer to the “PIC24F Family Reference Manual”, Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725). An interrupt flag is set if the device experiences an excursion past the trip point in the direction of change. If the interrupt is enabled, the program execution will branch to the interrupt vector address and the software can then respond to the interrupt. The HLVD Control register (see Register 21-1) completely controls the operation of the HLVD module. This allows the circuitry to be “turned off” by the user under software control, which minimizes the current consumption for the device. The High/Low-Voltage Detect module (HLVD) is a programmable circuit that allows the user to specify both the device voltage trip point and the direction of change. FIGURE 21-1: HIGH/LOW-VOLTAGE DETECT (HLVD) MODULE BLOCK DIAGRAM VDD Externally Generated Trip Point HLVDIN VDD HLVDL HLVDEN 16-to-1 MUX VDIR Set HLVDIF Internal Voltage Reference 1.2V Typical HLVDEN © 2009 Microchip Technology Inc. Preliminary DS39927B-page 167 PIC24F16KA102 FAMILY REGISTER 21-1: R/W-0 HLVDEN bit 15 R/W-0 VDIR bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 BGVST R/W-0 IRVST U-0 — R/W-0 HLVDL3 R/W-0 HLVDL2 R/W-0 HLVDL1 HLVDCON: HIGH/LOW-VOLTAGE DETECT CONTROL REGISTER U-0 — R/W-0 HLSIDL U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 HLVDL0 bit 0 HLVDEN: High/Low-Voltage Detect Power Enable bit 1 = HLVD enabled 0 = HLVD disabled Unimplemented: Read as ‘0’ HLSIDL: HLVD Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ VDIR: Voltage Change Direction Select bit 1 = Event occurs when voltage equals or exceeds trip point (HLVDL) 0 = Event occurs when voltage equals or falls below trip point (HLVDL) BGVST: Band Gap Voltage Stable Flag bit 1 = Indicates that the band gap voltage is stable 0 = Indicates that the band gap voltage is unstable IRVST: Internal Reference Voltage Stable Flag bit 1 = Indicates that the internal reference voltage is stable and the high-voltage detect logic generates the interrupt flag at the specified voltage range 0 = Indicates that the internal reference voltage is unstable and the high-voltage detect logic will not generate the interrupt flag at the specified voltage range, and the HLVD interrupt should not be enabled Unimplemented: Read as ‘0’ HLVDL: High/Low-Voltage Detection Limit bits 1111 = External analog input is used (input comes from the HLVDIN pin) 1110 = Trip point 1(1) 1101 = Trip point 2(1) 1100 = Trip point 3(1) . . . 0000 = Trip point 15(1) For actual trip point, refer to Section 29.0 “Electrical Characteristics”. bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 Note 1: DS39927B-page 168 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the 10-Bit High-Speed A/D Converter, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is displayed in Figure 22-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFG, AD1PCFG). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. The 10-bit A/D Converter has the following key features: • • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 9 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. On all PIC24F16KA102 family devices, the 10-bit A/D Converter has nine analog input pins, designated AN0 through AN5 and AN10 through AN12. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 169 PIC24F16KA102 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD VR+ VR Select AVSS VREF+ VREFVINH VINL S/H VR- VR+ DAC 16 VR- Comparator VINH AN0 AN1 AN2 AN3 AN4 AN5 AN1 VINL MUX A 10-Bit SAR Conversion Logic Data Formatting ADC1BUF0: ADC1BUFF AD1CON1 AN10 AN11 AN12 MUX B VBG VBG/2 AN1 VINH AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL VINL Sample Control Input MUX Control Pin Config Control Control Logic Conversion Control DS39927B-page 170 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 22-1: R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 — U-0 — R/W-0 ASAM R/W-0, HSC SAMP AD1CON1: A/D CONTROL REGISTER 1 U-0 — R/W-0 ADSIDL U-0 — U-0 — U-0 — R/W-0 FORM1 R/W-0 FORM0 bit 8 R/W-0, HSC DONE bit 0 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ FORM: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as ‘0’ ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is auto-set 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is not done Values of ADC1BUFn registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. bit 14 bit 13 bit 12-10 bit 9-8 bit 7-5 bit 4-3 bit 2 bit 1 bit 0 Note 1: © 2009 Microchip Technology Inc. Preliminary DS39927B-page 171 PIC24F16KA102 FAMILY REGISTER 22-2: R/W-0 VCFG2 bit 15 R-0, HSC BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG0 R/W-0 OFFCAL(1) U-0 — R/W-0 CSCNA U-0 — U-0 — bit 8 U-0 — R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM R/W-0 ALTS bit 0 R/W-0 VCFG1 HSC = Hardware Settable/Clearable bit W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown VCFG: Voltage Reference Configuration bits VCFG 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD (1) VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 OFFCAL: Offset Calibration bit 1 = Converts to get the offset calibration value 0 = Converts to get the actual input value Unimplemented: Read as ‘0’ CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer, 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer, 00-07, user should access data in 08-0F Unimplemented: Read as ‘0’ SMPI: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence bit 1 bit 0 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer configured as one 16-word buffer (ADC1BUFn) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings When the OFFCAL bit is set, inputs are disconnected and tied to AVSS. This sets the inputs of the A/D to zero. Then, the user can perform a conversion. Use of the Calibration mode is not affected by AD1PCFG contents nor channel input selection. Any analog input switches are disconnected from the A/D converter in this mode. The conversion result is stored by the user software and used to compensate subsequent conversions. This can be done by adding the two’s complement of the result obtained with the OFFCAL bit set to all normal A/D conversions. . . . Note 1: DS39927B-page 172 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 22-3: R/W-0 ADRC bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 AD1CON3: A/D CONTROL REGISTER 3 U-0 — U-0 — R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Unimplemented: Read as ‘0’ SAMC: Auto-Sample Time bits 11111 = 31 TAD bit 14-13 bit 12-8 · · · bit 7-6 bit 5-0 00001 = 1 TAD 00000 = 0 TAD (not recommended) Unimplemented: Read as ‘0’ ADCS: A/D Conversion Clock Select bits 11111 = 64 • TCY 11110 = 63 • TCY · · · 00001 = 3 • TCY 00000 = 2 • TCY © 2009 Microchip Technology Inc. Preliminary DS39927B-page 173 PIC24F16KA102 FAMILY - REGISTER 22-4: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 AD1CHS: A/D INPUT SELECT REGISTER U-0 — U-0 — U-0 — R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0SA0 bit 0 U-0 — U-0 — R/W-0 CH0SA4 R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14-12 bit 11-8 bit 7 bit 6-5 bit 4-0 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SB: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0110 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0010 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SA: Channel 0 Positive Input Select for Sample A bits 1111 = Channel 0 positive input is band gap reference (VBG) 1110 = Channel 0 positive input is band gap, divided by two, reference (VBG/2) 1101 = No channels connected (actual ADC MUX switch activates but input floats); used for CTMU 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 1010 = Channel 0 positive input is AN10 1001 = Reserved 1000 = Reserved 0110 = AVDD 0110 = AVSS 0101 = Channel 0 positive input is AN5 0100 = Channel 0 positive input is AN4 0010 = Channel 0 positive input is AN3 0010 = Channel 0 positive input is AN2 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 DS39927B-page 174 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 22-5: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-10 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 AD1PCFG: A/D PORT CONFIGURATION REGISTER U-0 — U-0 — R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 U-0 — U-0 — bit 8 R/W-0 PCFG0 bit 0 Unimplemented: Read as ‘0’ PCFG: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled; A/D samples pin voltage Unimplemented: Read as ‘0’ PCFG: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled; A/D samples pin voltage bit 9-6 bit 5-0 REGISTER 22-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-10 AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) U-0 — U-0 — R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 U-0 — U-0 — bit 8 U-0 — R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 R/W-0 CSSL0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSSL: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Unimplemented: Read as ‘0’ CSSL: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan bit 9-6 bit 5-0 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 175 PIC24F16KA102 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD ANx VT = 0.6V RIC ≤ 250W Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS ≤ 5 kΩ (Typical) Rs VA CPIN 6-11 pF (Typical) VT = 0.6V ILEAKAGE ±500 nA Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. DS39927B-page 176 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY FIGURE 22-3: Output Code (Binary (Decimal)) A/D TRANSFER FUNCTION 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) 512 * (VR+ – VR-) 1024 1023 * (VR+ – VR-) 1024 VR+ – VR1024 VR+ VR(VINH – VINL) 0 Voltage Level VR- + VR- + © 2009 Microchip Technology Inc. Preliminary DS39927B-page 177 VR- + PIC24F16KA102 FAMILY NOTES: DS39927B-page 178 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 23.0 Note: COMPARATOR MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator module, refer to the “PIC24F Family Reference Manual”, Section 19. “Comparator Module” (DS39710). The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module is displayed in Figure 23-1. Diagrams of the possible individual comparator configurations are displayed in Figure 23-2. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 23-2). The comparator module provides two dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs, as well as a voltage reference input from either the internal band gap reference divided by 2 (VBG/2) or the comparator voltage reference generator. FIGURE 23-1: CCH CREF COMPARATOR MODULE BLOCK DIAGRAM EVPOL Trigger/Interrupt Logic CEVT COE CXINB CXINC CXIND VBG/2 Input Select Logic VINVIN+ C1 CPOL COUT C1OUT Pin EVPOL Trigger/Interrupt Logic CEVT COE CXINA CVREF CPOL VINVIN+ C2 COUT C2OUT Pin © 2009 Microchip Technology Inc. Preliminary DS39927B-page 179 PIC24F16KA102 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH = xx VINVIN+ COE - Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH = 00 VINVIN+ COE Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH = 01 VINVIN+ COE CXINB CXINA - Cx CxOUT Pin CXINC CXINA - Cx CxOUT Pin Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH = 10 VINVIN+ Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH = 11 COE CXIND CXINA Cx VBG/2 CxOUT Pin CXINA VINVIN+ COE Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH = 00 VINVIN+ COE Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH = 01 VINVIN+ COE CXINB CVREF Cx CxOUT Pin CXINC CVREF - Cx CxOUT Pin Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH = 10 VINVIN+ Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH = 11 COE VINVIN+ CXIND CVREF Cx VBG/2 CxOUT Pin CVREF Cx COE CxOUT Pin DS39927B-page 180 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 23-1: R/W-0 CON bit 15 R/W-0 EVPOL1 bit 7 CMxCON: COMPARATOR x CONTROL REGISTERS R/W-0 CPOL R/W-0 CLPWR U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 CCH0 bit 0 R/W-0 COE R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11-10 bit 9 bit 8 bit 7-6 bit 5 bit 4 bit 3-2 bit 1-0 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted CLPWR: Comparator Low-Power Mode Select bit 1 = Comparator operates in Low-Power mode 0 = Comparator does not operate in Low-Power mode Unimplemented: Read as ‘0’ CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as ‘0’ CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CxINA pin Unimplemented: Read as ‘0’ CCH: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin © 2009 Microchip Technology Inc. Preliminary DS39927B-page 181 PIC24F16KA102 FAMILY REGISTER 23-2: R/W-0 CMIDL bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC C2OUT CMSTAT: COMPARATOR MODULE STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC C2EVT R-0, HSC C1EVT bit 8 R-0, HSC C1OUT bit 0 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as ‘0’ C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). Unimplemented: Read as ‘0’ C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). bit 14-10 bit 9 bit 8 bit 7-2 bit 1 bit 0 DS39927B-page 182 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Comparator Voltage Reference, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage Reference Module” (DS39709). 24.1 Configuring the Comparator Voltage Reference The comparator voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 24-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R CVR CVREN R R R 16-to-1 MUX R 16 Steps CVREF R R R CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS © 2009 Microchip Technology Inc. Preliminary DS39927B-page 183 PIC24F16KA102 FAMILY REGISTER 24-1: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as ‘0’ CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR ≤ 15 bits When CVRR = 1 and CVRSS = 0: CVREF = (CVR/24) * (CVRSRC) When CVRR = 0 and CVRSS = 0: CVREF = 1/4 (CVRSRC) + (CVR/32) * (CVRSRC) When CVRR = 1 and CVRSS = 1: CVREF = ((CVR/24) * (CVRSRC)) + VREFWhen CVRR = 0 and CVRSS = 1: CVREF = (1/4 (CVRSRC) + (CVR/32) * (CVRSRC)) + VREF- bit 6 bit 5 bit 4 bit 3-0 DS39927B-page 184 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Charge Measurement Unit, refer to the “PIC24F Family Reference Manual”, Section 11. “CTMU” (DS39724). 25.1 Measuring Capacitance The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: dV C = I ⋅ -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 25-1 displays the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides charge measurement, accurate differential time measurement between pulse sources and asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of one nanosecond Accurate current source suitable for capacitive measurement Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based touch sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register selects the current range of current source and trims the current. FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter ANx ANY Current Source CAPP RPR © 2009 Microchip Technology Inc. Preliminary DS39927B-page 185 PIC24F16KA102 FAMILY 25.2 Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 25-2 displays the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 25-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. 25.3 Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source ANx FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39927B-page 186 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 25-1: R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT CTMUCON: CTMU CONTROL REGISTER U-0 — R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0 EDG1STAT bit 0 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as ‘0’ CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 14 bit 13 bit 12 bit 10 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 187 PIC24F16KA102 FAMILY REGISTER 25-1: bit 3-2 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1SEL: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred bit 1 bit 0 REGISTER 25-2: R/W-0 ITRIM5 bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 R/W-0 ITRIM4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current IRNG: Current Source Range Select bits 11 = 100 × Base current 10 = 10 × Base current 01 = Base current level (0.55 μA nominal) 00 = Current source disabled Unimplemented: Read as ‘0’ bit 9-8 bit 7-0 DS39927B-page 188 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 26.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information on the Watchdog Timer, High-Level Device Integration and Programming Diagnostics, refer to the individual sections of the “PIC24F Family Reference Manual” provided below: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 36. “High-Level Integration with Programmable High/Low-Voltage Detect (HLVD)” (DS39725) • Section 33. “Programming and Diagnostics” (DS39716) 26.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location, F80000h. A complete list is provided in Table 26-1. A detailed explanation of the various bit functions is provided in Register 26-1 through Register 26-8. The address, F80000h, is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh), which can only be accessed using table reads and table writes. TABLE 26-1: Configuration Register FBS FGS FOSCSEL FOSC FWDT FPOR FICD FDS CONFIGURATION REGISTERS LOCATIONS Address F80000 F80004 F80006 F80008 F8000A F8000C F8000E F80010 PIC24F16KA102 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection In-Circuit Serial Programming™ (ICSP™) In-Circuit Emulation REGISTER 26-1: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-4 bit 3-1 FBS: BOOT SEGMENT CONFIGURATION REGISTER U-0 — U-0 — U-0 — R/W-1 BSS2 R/W-1 BSS1 R/W-1 BSS0 R/W-1 BWRP bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ BSS: Boot Segment Program Flash Code Protection bits 111 = No boot program Flash segment 011 = Reserved 110 = Standard security, boot program Flash segment starts at 200h, ends at 000AFEh 010 = High security boot program Flash segment starts at 200h, ends at 000AFEh 101 = Standard security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 001 = High security, boot program Flash segment starts at 200h, ends at 0015FEh(1) 100 = Reserved 000 = Reserved bit 0 BWRP: Boot Segment Program Flash Write Protection bit 1 = Boot segment may be written 0 = Boot segment is write-protected This selection should not be used in PIC24F08KA1XX devices. Note 1: © 2009 Microchip Technology Inc. Preliminary DS39927B-page 189 PIC24F16KA102 FAMILY REGISTER 26-2: U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 7-2 bit 1 C = Clearable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FGS: GENERAL SEGMENT CONFIGURATION REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — R/C-1 GSS0 R/C-1 GWRP bit 0 Unimplemented: Read as ‘0’ GSS0: General Segment Code Flash Code Protection bit 1 = No protection 0 = Standard security enabled GWRP: General Segment Code Flash Write Protection bit 1 = General segment may be written 0 = General segment is write-protected bit 0 REGISTER 26-3: R/P-1 IESO bit 7 Legend: R = Readable bit -n = Value at POR bit 7 FOSCSEL: OSCILLATOR SELECTION CONFIGURATION REGISTER U-0 — U-0 — U-0 — U-0 — R/P-1 FNOSC2 R/P-1 FNOSC1 R/P-1 FNOSC0 bit 0 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IESO: Internal External Switchover bit 1 = Internal External Switchover mode enabled (Two-Speed Start-up enabled) 0 = Internal External Switchover mode disabled (Two-Speed Start-up disabled) Unimplemented: Read as ‘0’ FNOSC: Oscillator Selection bits 000 = Fast RC oscillator (FRC) 001 = Fast RC oscillator with divide-by-N with PLL module (FRCDIV+PLL) 010 = Primary oscillator (XT, HS, EC) 011 = Primary oscillator with PLL module (HS+PLL, EC+PLL) 100 = Secondary oscillator (SOSC) 101 = Low-Power RC oscillator (LPRC) 110 = 500 kHz Low-Power FRC oscillator with divide-by-N (LPFRCDIV) 111 = 8 MHz FRC oscillator with divide-by-N (FRCDIV) bit 6-3 bit 2-0 DS39927B-page 190 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 26-4: R/P-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-6 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FOSC: OSCILLATOR CONFIGURATION REGISTER R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 POSCMD1 R/P-1 POSCMD0 bit 0 SOSCSEL POSCFREQ1 POSCFREQ0 OSCIOFNC R/P-1 FCKSM0 FCKSM: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled SOSCSEL: Secondary Oscillator Select Bit 1 = Secondary oscillator configured for high-power operation 0 = Secondary oscillator configured for low-power operation POSCFREQ: Primary Oscillator Frequency Range Configuration bits 11 = Primary oscillator/external clock input frequency greater than 8 MHz 10 = Primary oscillator/external clock input frequency between 100 kHz and 8 MHz 01 = Primary oscillator/external clock input frequency less than 100 kHz 00 = Reserved; do not use OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output signal active on the OSCO pin; primary oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMD = 11 or 00) 0 = CLKO output disabled POSCMD: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS oscillator mode selected 01 = XT oscillator mode selected 00 = External clock mode selected bit 5 bit 4-3 bit 2 bit 1-0 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 191 PIC24F16KA102 FAMILY REGISTER 26-5: R/P-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FWDT: WATCHDOG TIMER CONFIGURATION REGISTER U-0 — R/P-1 FWPSA R/P-1 WDTPS3 R/P-1 WDTPS2 R/P-1 WDTPS1 R/P-1 WDTPS0 bit 0 R/P-1 WINDIS FWDTEN: Watchdog Timer Enable bit 1 = WDT enabled 0 = WDT disabled (control is placed on the SWDTEN bit) WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard WDT selected; windowed WDT disabled 0 = Windowed WDT enabled Unimplemented: Read as ‘0’ FWPSA: WDT Prescaler bit 1 = WDT prescaler ratio of 1:128 0 = WDT prescaler ratio of 1:32 WDTPS: Watchdog Timer Postscale Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 bit 6 bit 5 bit 4 bit 3-0 DS39927B-page 192 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 26-6: R/P-1 MCLRE(2) bit 7 FPOR: RESET CONFIGURATION REGISTER R/P-1 BORV0(3) R/P-1 I2C1SEL(1) R/P-1 PWRTEN U-0 — R/P-1 BOREN1 R/P-1 BOREN0 bit 0 R/P-1 BORV1(3) Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6-5 bit 4 bit 3 bit 2 bit 1-0 MCLRE: MCLR Pin Enable bit(2) 1 = MCLR pin enabled; RA5 input pin disabled 0 = RA5 input pin enabled; MCLR disabled BORV: Brown-out Reset Enable bits(3) 11 = Brown-out Reset set to lowest voltage 10 = Brown-out Reset 01 = Brown-out Reset set to highest voltage 00 = Low-power Brown-out Reset occurs around 2.0V I2C1SEL: Alternate I2C1 Pin Mapping bit(1) 0 = Alternate location for SCL1/SDA1 pins 1 = Default location for SCL1/SDA1 pins PWRTEN: Power-up Timer Enable bit 0 = PWRT disabled 1 = PWRT enabled Unimplemented: Read as ‘0’ BOREN: Brown-out Reset Enable bits 11 = Brown-out Reset enabled in hardware; SBOREN bit disabled 10 = Brown-out Reset enabled only while device is active and disabled in Sleep; SBOREN bit disabled 01 = Brown-out Reset controlled with the SBOREN bit setting 00 = Brown-out Reset disabled in hardware; SBOREN bit disabled Applies only to 28-pin devices. The MCLRE fuse can only be changed when using the VPP-Based ICSP™ mode entry. This prevents a user from accidentally locking out the device from the low-voltage test entry. Refer to the electrical specifications for BOR voltages. Note 1: 2: 3: REGISTER 26-7: R/P-1 DEBUG bit 7 Legend: R = Readable bit -n = Value at POR bit 7 — FICD: IN-CIRCUIT DEBUGGER CONFIGURATION REGISTER U-0 U-0 — U-0 — U-0 — U-0 — R/P-1 FICD1 R/P-1 FICD0 bit 0 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 6-2 bit 1-0 DEBUG: Background Debugger Enable bit 1 = Background debugger disabled 0 = Background debugger functions enabled Unimplemented: Read as ‘0’ FICD ICD Pin Select bits 11 = PGC1/PGD1 are used for programming and debugging the device 10 = PGC2/PGD2 are used for programming and debugging the device 01 = PGC3/PGD3 are used for programming and debugging the device 00 = Reserved; do not use © 2009 Microchip Technology Inc. Preliminary DS39927B-page 193 PIC24F16KA102 FAMILY REGISTER 26-8: R/P-1 DSWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 7 P = Programmable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FDS: DEEP SLEEP CONFIGURATION REGISTER R/P-1 RTCCKSEL R/P-1 R/P-1 R/P-1 R/P-1 R/P-1 bit 0 DSWCKSEL DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 R/P-1 DSLPBOR DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT enabled 0 = DSWDT disabled DSLPBOR: Deep Sleep/Low-Power BOR Enable bit (does not affect operation in non Deep Sleep modes) 1 = Deep Sleep BOR enabled in Deep Sleep 0 = Deep Sleep BOR disabled in Deep Sleep RTCCKSEL: RTCC Reference Clock Select bit 1 = RTCC uses SOSC as reference clock 0 = RTCC uses LPRC as reference clock DSWCKSEL: DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock DSWDTPS: Deep Sleep Watchdog Timer Postscale Select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) nominal 1110 = 1:536,870,912 (6.4 days) nominal 1101 = 1:134,217,728 (38.5 hours) nominal 1100 = 1:33,554,432 (9.6 hours) nominal 1011 = 1:8,388,608 (2.4 hours) nominal 1010 = 1:2,097,152 (36 minutes) nominal 1001 = 1:524,288 (9 minutes) nominal 1000 = 1:131,072 (135 seconds) nominal 0111 = 1:32,768 (34 seconds) nominal 0110 = 1:8,192 (8.5 seconds) nominal 0101 = 1:2,048 (2.1 seconds) nominal 0100 = 1:512 (528 ms) nominal 0011 = 1:128 (132 ms) nominal 0010 = 1:32 (33 ms) nominal 0001 = 1:8 (8.3 ms) nominal 0000 = 1:2 (2.1 ms) nominal bit 6 bit 5 bit 4 bit 3-0 DS39927B-page 194 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY REGISTER 26-9: U-0 — bit 23 R FAMID7 bit 15 R DEV7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8 DEVID: DEVICE ID REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 Unimplemented: Read as ‘0’ FAMID: Device Family Identifier bits 00001011 = PIC24F16KA102 family DEV: Individual Device Identifier bits 00000011 = PIC24F16KA102 00001010 = PIC24F08KA102 00000001 = PIC24F16KA101 00001000 = PIC24F08KA101 REGISTER 26-10: DEVREV: DEVICE REVISION REGISTER U-0 — bit 23 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 23-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R REV3 R REV2 R REV1 R REV0 bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 U-0 — bit 8 Unimplemented: Read as ‘0’ REV: Minor Revision Identifier bits © 2009 Microchip Technology Inc. Preliminary DS39927B-page 195 PIC24F16KA102 FAMILY 26.2 Watchdog Timer (WDT) For the PIC24F16KA102 family of devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the Configuration bits, WDTPS (FWDT), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 26.2.1 WINDOWED OPERATION The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the Configuration bit, WINDIS (FWDT), to ‘0’. 26.2.2 CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 26-1: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-Bit/7-Bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS39927B-page 196 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 26.3 Deep Sleep Watchdog Timer (DSWDT) 26.5 In-Circuit Serial Programming PIC24F16KA102 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. In PIC24F16KA102 family devices, in addition to the WDT module, a DSWDT module is present which runs while the device is in Deep Sleep, if enabled. It is driven by either the SOSC or LPRC oscillator. The clock source is selected by the Configuration bit, DSWCKSEL (FDS). The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler. The postscaler can be selected by the Configuration bits, DSWDTPS (FDS). When the DSWDT is enabled, the clock source is also enabled. DSWDT is one of the sources that can wake-up the device from Deep Sleep mode. 26.6 In-Circuit Debugger 26.4 Program Verification and Code Protection When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. For all devices in the PIC24F16KA102 family, code protection for the boot segment is controlled by the Configuration bit, BSS0, and the general segment by the Configuration bit, GSS0. These bits inhibit external reads and writes to the program memory space; this has no direct effect in normal execution mode. Write protection is controlled by bit, BWRP, for the boot segment and bit, GWRP, for the general segment in the Configuration Word. When these bits are programmed to ‘0’, internal write and erase operations to program memory are blocked. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 197 PIC24F16KA102 FAMILY NOTES: DS39927B-page 198 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 199 PIC24F16KA102 FAMILY 27.2 MPASM Assembler 27.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 27.6 27.3 MPLAB C18 and MPLAB C30 C Compilers MPLAB SIM Software Simulator The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 27.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39927B-page 200 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 27.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 27.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 27.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 27.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 201 PIC24F16KA102 FAMILY 27.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 27.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 27.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. DS39927B-page 202 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all of the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the Program Counter (PC) is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 28-1 lists the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. Preliminary DS39927B-page 203 PIC24F16KA102 FAMILY TABLE 28-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address ∈ {0000h...1FFFh} 1-bit unsigned literal ∈ {0,1} 4-bit unsigned literal ∈ {0...15} 5-bit unsigned literal ∈ {0...31} 8-bit unsigned literal ∈ {0...255} 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal ∈ {0...16384} 16-bit unsigned literal ∈ {0...65535} 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal ∈ {-512...511} 16-bit signed literal ∈ {-32768...32767} 6-bit signed literal ∈ {-16...16} Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers ∈ {W0..W15} One of 16 destination working registers ∈ {W0..W15} One of 16 source working registers ∈ {W0..W15} W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39927B-page 204 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 28-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG BTSC BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None 1 None (2 or 3) 1 None (2 or 3) © 2009 Microchip Technology Inc. Preliminary DS39927B-page 205 PIC24F16KA102 FAMILY TABLE 28-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CALL CALL CLR CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CP0 CP0 CPB CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if ≠ Wn = Decimal Adjust Wn f = f –1 WREG = f –1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39927B-page 206 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 28-2: Assembly Mnemonic GOTO GOTO GOTO INC INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP NOP NOPR POP POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None None None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None © 2009 Microchip Technology Inc. Preliminary DS39927B-page 207 PIC24F16KA102 FAMILY TABLE 28-2: Assembly Mnemonic PWRSAV RCALL PWRSAV RCALL RCALL REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP TBLRDH TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog to Wd # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None DS39927B-page 208 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 28-2: Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N © 2009 Microchip Technology Inc. Preliminary DS39927B-page 209 PIC24F16KA102 FAMILY NOTES: DS39927B-page 210 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24F16KA102 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24F16KA102 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +5.0V Voltage on any combined analog and digital pin, with respect to VSS ........................................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS ....................................................................... -0.3V to (VDD + 0.3V) Voltage on MCLR/VPP pin with respect to VSS ......................................................................................... -0.3V to +9.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (1) ..........................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (1) ..............................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 29-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 211 PIC24F16KA102 FAMILY 29.1 DC Characteristics PIC24F16KA102 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 29-1: 3.60V 3.00V Voltage (VDD) 3.60V 3.00V 1.80V 8 MHz Frequency Note: 32 MHz For frequencies between 8 MHz and 32 MHz, FMAX = 20 MHz *(VDD – 1.8) + 8 MHz. TABLE 29-1: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA Min -40 -40 Typ — — Max +125 +85 Unit °C °C Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – Σ IOH) I/O Pin Power Dissipation: PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PD PINT + PI/O W PDMAX (TJ – TA)/θJA W TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol θJA θJA θJA θJA θJA θJA θJA θJA Typ 62.4 60 108 71 75 80.2 43 32 Max — — — — — — — — Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Notes 1 1 1 1 1 1 1 1 Package Thermal Resistance, 20-Pin PDIP Package Thermal Resistance, 28-Pin SPDIP Package Thermal Resistance, 20-Pin SSOP Package Thermal Resistance, 28-Pin SSOP Package Thermal Resistance, 20-Pin SOIC Package Thermal Resistance, 28-Pin SOIC Package Thermal Resistance, 20-Pin QFN Package Thermal Resistance, 28-Pin QFN Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations. DS39927B-page 212 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min 1.8 1.5 VSS Typ(1) — — — Max Units 3.6 — 0.7 V V V Conditions DC CHARACTERISTICS Param Symbol No. DC10 DC12 DC16 VDD VDR VPOR Characteristic Supply Voltage RAM Data Retention Voltage(2) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal DC17 SVDD 0.05 — — V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms Note 1: 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. TABLE 29-4: HIGH/LOW–VOLTAGE DETECT CHARACTERISTICS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Symbol No. DC18 VHLVD Characteristic HLVD Voltage on VDD HLVDL = 0000 Transition HLVDL = 0001 HLVDL = 0010 HLVDL = 0011 HLVDL = 0100 HLVDL = 0101 HLVDL = 0110 HLVDL = 0111 HLVDL = 1000 HLVDL = 1001 HLVDL = 1010 HLVDL = 1011 HLVDL = 1100 HLVDL = 1101 HLVDL = 1110 Min — 1.81 1.85 1.90 1.95 2.06 2.12 2.24 2.31 2.47 2.64 2.74 2.85 2.96 3.22 Typ 1.85 1.90 1.95 2.00 2.05 2.17 2.23 2.36 2.43 2.60 2.78 2.88 3.00 3.12 3.39 Max 1.94 2.00 2.05 2.10 2.15 2.28 2.34 2.48 2.55 2.73 2.92 3.02 3.15 3.28 3.56 Units V V V V V V V V V V V V V V V Conditions © 2009 Microchip Technology Inc. Preliminary DS39927B-page 213 PIC24F16KA102 FAMILY TABLE 29-5: BOR TRIP POINTS Standard Operating Conditions (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for industrial Param Sym No. DC19 Characteristic BOR Voltage on VDD Transition BOR = 00 BOR = 01 BOR = 10 BOR = 11 Min 1.85 2.92 2.63 1.75 Typ 2 3 2.7 Max Units 2.15 3.08 2.77 V V V V Conditions Valid for LPBOR and DSBOR 1.82 1.85 TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) IDD Current DC20 330 -40°C DS20a 330 +25°C 195 μA 1.8V DC20b 330 +60°C DC20c 330 +85°C 0.5 MIPS, FOSC = 1 MHz DC20d 540 -40°C DC20e 540 +25°C 365 μA 3.3V DC20f 645 +60°C DC20g 720 +85°C DC22 600 -40°C DC22a 600 +25°C 363 μA 1.8V DC22b 600 +60°C DC22c 600 +85°C 1 MIPS, FOSC = 2 MHz DC22d 1100 -40°C DC22e 1100 +25°C 695 μA 3.3V DC22f 1100 +60°C DC22g 1100 +85°C DC23 18 -40°C DC23a 18 +25°C 16 MIPS, 11 mA 3.3V FOSC = 32 MHz DC23b 18 +60°C DC23c 18 +85°C DC27 3.40 -40°C DC27a 3.40 +25°C 2.25 mA 2.5V DC27b 3.40 +60°C DC27c 3.40 +85°C FRC (4 MIPS), FOSC = 8 MHz DC27d 4.60 -40°C DC27e 4.60 +25°C 3.05 mA 3.3V DC27f 4.60 +60°C DC27g 4.60 +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • EC mode with clock input driven with a square wave rail-to-rail • I/O configured as outputs driven low • MCLR – VDD • WDT FSCM disabled • SRAM, program and data memory active • All PMD bits set except for modules being measured DS39927B-page 214 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-6: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max 28 28 28 28 55 55 55 55 Units -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C Conditions DC CHARACTERISTICS Parameter No. IDD Current DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g Note 1: 2: Typical(1) 8 μA 1.8V LPRC (31 kHz) 3.3V 15 μA Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Operating Parameters: • EC mode with clock input driven with a square wave rail-to-rail • I/O configured as outputs driven low • MCLR – VDD • WDT FSCM disabled • SRAM, program and data memory active • All PMD bits set except for modules being measured © 2009 Microchip Technology Inc. Preliminary DS39927B-page 215 PIC24F16KA102 FAMILY TABLE 29-7: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units (2) DC CHARACTERISTICS Param No. Typical(1) Conditions Idle Current (IIDLE): Core Off, Clock on Base Current, PMD Bits are Set DC40 100 -40°C DC40a 100 +25°C 48 μA 1.8V DC40b 100 +60°C DC40c 100 +85°C 0.5 MIPS, FOSC = 1 MHz DC40d 215 -40°C DC40e 215 +25°C 106 μA 3.3V DC40f 215 +60°C DC40g 215 +85°C DC42 200 -40°C DC42a 200 +25°C 94 μA 1.8V DC42b 200 +60°C DC42c 200 +85°C 1 MIPS, FOSC = 2 MHz DC42d 395 -40°C DC42e 395 +25°C 160 μA 3.3V DC42f 395 +60°C DC42g 395 +85°C DC43 6.0 -40°C DC43a 6.0 +25°C 16 MIPS, 3.1 mA 3.3V FOSC = 32 MHz DC43b 6.0 +60°C DC43c 6.0 +85°C DC44 0.74 -40°C DC44a 0.74 +25°C 0.56 mA 1.8V DC44b 0.74 +60°C DC44c 0.74 +85°C FRC (4 MIPS), FOSC = 8 MHz DC44d 1.50 -40°C DC44e 1.50 +25°C 0.95 mA 3.3V DC44f 1.50 +60°C DC44g 1.50 +85°C DC50 18 -40°C DC50a 18 +25°C 2 μA 1.8V DC50b 18 +60°C DC50c 18 +85°C LPRC (31 kHz) DC50d 40 -40°C DC50e 40 +25°C 4 μA 3.3V DC50f 40 +60°C DC50g 40 +85°C Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 2: Operating Parameters: • Core off • EC mode with clock input driven with a square wave rail-to-rail • I/O configured as outputs driven low • MCLR – VDD • WDT FSCM disabled • SRAM, program and data memory active • All PMD bits set except for modules being measured DS39927B-page 216 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60c DC60d DC60e DC60f DC60g DC70 DC70a DC70b DC70c DC70d DC70e DC70f DC70g DC61 DC61a DC61b DC61c DC61d DC61e DC61f DC61g Note 1: 2: 3: 0.87 0.67 0.035 0.020 0.105 0.025 Typical(1) Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) 0.200 0.200 0.870 1.350 0.540 0.540 1.680 2.450 0.150 0.150 0.430 0.630 0.300 0.300 0.700 0.980 0.65 0.65 0.65 0.65 0.95 0.95 0.95 0.95 μA μA μA μA μA μA -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C 3.3V 1.8V Watchdog Timer Current: WDT(3,4) 3.3V 1.8V Base Deep Sleep Current 3.3V 1.8V Base Power-Down Current (Sleep)(3) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: 5: 6: Current applies to Sleep only. Current applies to Sleep and Deep Sleep. Current applies to Deep Sleep only. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 217 PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC62 DC62a DC62b DC62c DC62d DC62e DC62f DC62g DC64 DC64a DC64b DC64c DC64d DC64e DC64f DC64g DC63 DC63a DC63b DC63c DC62 DC62a DC62b DC62c DC62d DC62e DC62f DC62g Note 1: 2: 3: 0.80 0.49 4.5 6.2 5.5 0.730 0.450 Typical(1) Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) 0.650 0.650 0.650 0.650 0.980 0.980 0.980 0.980 7.10 7.10 7.80 8.30 7.10 7.10 7.80 8.30 6.60 6.60 6.60 6.60 0.65 0.65 0.65 0.65 0.98 0.98 0.98 0.98 μA μA μA μA μA μA μA -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C 3.3V 1.8V 3.3V 3.3V 1.8V HLVD(3,4) 3.3V 1.8V Timer1 w/32 kHz Crystal: T132 (SOSC – LP)(3) BOR(3,4) RTCC(3,5) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: 5: 6: Current applies to Sleep only. Current applies to Sleep and Deep Sleep. Current applies to Deep Sleep only. DS39927B-page 218 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-8: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC70 DC70a DC70b DC70c DC70d DC70e DC70f DC70g DC71 DC71a DC71b DC71c DC71d DC71e DC71f DC71g DC72 DC72a DC72b DC72c DC72d DC72e DC72f DC72g Note 1: 2: 3: 0.010 0.005 0.55 0.35 0.095 0.045 Typical(1) Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.55 0.55 0.55 0.55 0.75 0.75 0.75 0.75 0.200 0.200 0.200 0.200 0.200 0.200 0.200 0.200 μA μA μA μA μA μA -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C 3.3V 1.8V 3.3V 1.8V 3.3V 1.8V LPBOR(3,4) Deep Sleep Watchdog Timer: DSWDT (SOSC – LP)(6) Deep Sleep BOR: DSBOR(3,6) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. 4: 5: 6: Current applies to Sleep only. Current applies to Sleep and Deep Sleep. Current applies to Deep Sleep only. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 219 PIC24F16KA102 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min — VSS VSS VSS VSS VSS VSS — 0.8 VDD 0.8 VDD 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 50 Typ(1) — — — — — — — — — — — — — — — — 250 Max — 0.2 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 — VDD VDD VDD VDD VDD VDD VDD VDD 500 Units — V V V V V V — V V V V V V V V μA 2.5V ≤ VPIN ≤ VDD VDD = 3.3V, VPIN = VSS SMBus disabled SMBus enabled Conditions DC CHARACTERISTICS Param No. DI10 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2C™ Buffer I/O Pins with SMBus Buffer Input High Voltage(4) I/O Pins: with Analog Functions Digital Only MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2C Buffer: with Analog Functions Digital Only I/O Pins with SMBus ICNPU CNx Pull-up Current IIL DI50 DI51 DI55 DI56 Note 1: 2: Input Leakage Current(2,3) I/O Ports VREF+, VREF-, AN0, AN1 MCLR OSCI — — — — 0.050 0.300 — — ±0.100 ±0.500 ±5.0 ±5.0 μA μA μA μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD, XT and HS modes DI25 DI26 DI27 DI28 DI29 DI30 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pin buffer types. DS39927B-page 220 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 DO26 Note 1: Sym VOL Characteristic Output Low Voltage All I/O Pins OSC2/CLKO Output High Voltage All I/O Pins OSC2/CLKO — — — — — 3 1.8 3 1.8 — — — — — — — — — 0.4 0.4 0.4 0.4 — — — — — V V V V — V V V V IOL = 4.0 mA, VDD = 3.6V IOL = 3.5 mA, VDD = 2.0V IOL = 8.0 mA, VDD = 3.6V IOL = 4.5 mA, VDD = 1.8V — IOH = -3.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -2.5 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions Data in “Typ” column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param No. D130 D131 D133A D134 D135 Note 1: 2: Sym Characteristic Program Flash Memory EP VPR TIW Cell Endurance VDD for Read Self-Timed Write Cycle Time 10,000(2) VMIN — 40 — — — 2 — 10 — 3.6 — — — E/W V ms Year mA Provided no other specifications are violated VMIN = Minimum operating voltage Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions TRETD Characteristic Retention IDDP Supply Current During Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Self-write and block erase. TABLE 29-12: DC CHARACTERISTICS: DATA EEPROM MEMORY DC CHARACTERISTICS Param No. D140 D141 D143A D143B D144 D145 Note 1: Sym Characteristic Data EEPROM Memory EPD VPRD TIWD TREF Cell Endurance VDD for Read Self-Timed Write Cycle Time Number of Total Write/Erase Cycles Before Refresh 100,000 VMIN — — 40 — — — 4 10M — 7 — 3.6 — — — — E/W V ms E/W Year mA Provided no other specifications are violated VMIN = Minimum operating voltage Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions TRETDD Characteristic Retention IDDPD Supply Current during Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 221 PIC24F16KA102 FAMILY TABLE 29-13: COMPARATOR DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. D300 D301 D302 Symbol VIOFF VICM CMRR Characteristic Input Offset Voltage* Input Common Mode Voltage* Common Mode Rejection Ratio* Min — 0 55 Typ 20 — — Max 40 VDD — Units mV V dB Comments * Parameters are characterized but not tested. TABLE 29-14: COMPARATOR VOLTAGE REFERENCE DC SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Resolution Absolute Accuracy Unit Resistor Value (R) Min VDD/24 — — Typ — — 2k Max VDD/32 AVDD – 1.5 — Units LSb LSb Ω Comments VRD310 CVRES VRD311 CVRAA VRD312 CVRUR DS39927B-page 222 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24F16KA102 family AC characteristics and timing parameters. TABLE 29-15: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. FIGURE 29-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSCO Load Condition 1 – for all pins except OSCO VDD/2 RL Pin VSS CL Pin VSS CL RL = 464Ω CL = 50 pF for all pins except OSCO 15 pF for OSCO output TABLE 29-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI EC mode In I2C™ mode DO56 DO58 Note 1: CIO CB All I/O Pins and OSCO SCLx, SDAx — — — — 50 400 pF pF Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 223 PIC24F16KA102 FAMILY FIGURE 29-3: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 TABLE 29-17: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 1.8 to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min DC 4 0.2 4 4 31 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — 6 6 Max 32 8 4 25 8 33 — DC — 20 10 10 Units MHz MHz MHz MHz MHz kHz — ns ns ns ns ns EC EC EC ECPLL XT HS HSPLL SOSC See parameter OS10 for FOSC value Conditions FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency OS20 OS25 OS30 OS31 OS40 OS41 TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2) TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time (3) Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39927B-page 224 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 1.8V TO 3.6V) AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range PLL Output Frequency Range Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min 4 16 — -2 Typ(2) — — 1 1 Max 8 32 2 2 Units MHz MHz ms % Conditions ECPLL, HSPLL modes, -40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +85°C — Measured over 100 ms period TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter) These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-19: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 Characteristic Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions Internal FRC Accuracy @ 8 MHz(1) FRC -1 -3 -5 Note 1: — — — +1 +3 +5 % % % +25°C -40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +85°C 3.0V ≤ VDD ≤ 3.6V 1.8V ≤ VDD ≤ 3.6V Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. TABLE 29-20: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -15 -15 — — 15 15 % % +25°C -40°C ≤ TA ≤ +85°C 1.8V ≤ VDD ≤ 3.6V Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions Change of LPRC frequency as VDD changes. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 225 PIC24F16KA102 FAMILY FIGURE 29-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 29-2 for load conditions. New Value TABLE 29-21: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39927B-page 226 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-22: COMPARATOR TIMINGS Param No. 300 301 * Note 1: Symbol TRESP TMC2OV Characteristic Response Time*(1) Comparator Mode Change to Output Valid* Min — — Typ 150 — Max 400 10 Units ns μs Comments Parameters are characterized but not tested. Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-23: COMPARATOR VOLTAGE REFERENCE SETTLING TIME SPECIFICATIONS Param No. VR310 Note 1: Symbol TSET Characteristic Settling Time(1) Min — Typ — Max 10 Units μs Comments Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’. TABLE 29-24: CTMU CURRENT SOURCE SPECIFICATIONS DC CHARACTERISTICS Param Sym No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min — — — Typ(1) 550 5.5 55 Max — — — Units nA μA μA Conditions CTMUICON = 01 CTMUICON = 10 CTMUICON = 11 IOUT1 CTMU Current Source, Base Range IOUT2 CTMU Current Source, 10x Range IOUT3 CTMU Current Source, 100x Range Note 1: Nominal value at center point of current trim range (CTMUICON = 000000) © 2009 Microchip Technology Inc. Preliminary DS39927B-page 227 PIC24F16KA102 FAMILY TABLE 29-25: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Characteristic Min. Typ Max. Units Conditions Symbol Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 1.8 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 V AD02 AD05 AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage Full-Scale Input Span Absolute Input Voltage Absolute VINL Input Voltage Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) — — — — V V V V Reference Inputs Analog Input AD10 AD11 AD12 AD17 VINH-VINL VIN VINL RIN VREFL AVSS – 0.3 AVSS – 0.3 — — — — VREFH AVDD + 0.3 AVDD/2 2.5K V V V Ω 10-bit (Note 2) ADC Accuracy AD20b NR — — — — — — 10 ±1 ±1 ±1 ±1 — — ±2 ±1.5 ±3 ±2 — bits LSb LSb LSb LSb — VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V Guaranteed AD21b INL AD22b DNL AD23b GERR AD24b EOFF AD25b Note 1: 2: The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. DS39927B-page 228 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY TABLE 29-26: ADC CONVERSION TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param No. AD50 AD51 AD55 AD56 AD57 AD58 AD59 AD60 AD61 Note 1: 2: 3: Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Characteristic Min. Typ Max. Units Conditions Symbol Clock Parameters TAD TRC TCONV FCNV TSAMP TACQ TSWC TDIS TPSS ADC Clock Period ADC Internal RC Oscillator Period Conversion Time Throughput Rate Sample Time Acquisition Time Switching Time from Convert to Sample Discharge Time Sample Start Delay from setting Sample bit (SAMP) 75 — — — — 750 — 0.5 2 — 250 12 — 1 — — — — — — — 500 — — (Note 3) — 3 TAD TAD ns ns TAD ksps TAD ns (Note 2) AVDD ≥ 2.7V TCY = 75 ns, AD1CON3 in default state Conversion Rate Clock Parameters Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale after the conversion (VDD to VSS or VSS to VDD). On the following cycle of the device clock. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 229 PIC24F16KA102 FAMILY TABLE 29-27: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY11 SY12 SY13 SY20 SY25 SY35 SY45 TmcL TPWRT TPOR TIOZ TWDT TBOR TFSCM TRST TVREG SY55 SY65 SY75 SY85 Note 1: TLOCK TOST TFRC TLPRC Standard Operating Conditions: 1.8V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Characteristic MCLR Pulse Width (low) Power-up Timer Period Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period Brown-out Reset Pulse Width Fail-Safe Clock Monitor Delay Configuration Update Time On-Chip Voltage Regulator Output Delay PLL Start-up Time Oscillator Start-up Time Fast RC Oscillator Start-up Time Low-Power Oscillator Start-up Time Min. 2 50 1 — 0.85 3.4 1 — — — — — — — Typ(1) — 64 5 — 1.0 4.0 — 2 20 10 1 1024 1 — Max. — 90 10 100 1.15 4.6 — 2.3 — — — — 1.5 100 Units μs ms μs ns ms ms μs μs μs μs ms TOSC μs μs 1.32 prescaler 1:128 prescaler Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39927B-page 230 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 30.0 30.1 PACKAGING INFORMATION Package Marking Information 20-Lead PDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC24F16KA101 -I/P e3 0910017 28-Lead SPDIP XXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXX YYWWNNN Example PIC24F16KA102 -I/SP e3 0910017 20-Lead SSOP XXXXXXXXXXX XXXXXXXXXXX YYWWNNN Example PIC24F16KA 101-I/SS e3 0910017 28-Lead SSOP XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Example PIC24F08KA 102-I/SS e3 0910017 Legend: XX...X Y YY WW NNN e3 * Product-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 231 PIC24F16KA102 FAMILY 20-Lead SOIC (.300”) XXXXXXXXXXXXXX XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN Example PIC24F16KA101 -I/SO e3 0910017 28-Lead SOIC (.300”) XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXXXXXX YYWWNNN Example PIC24F16KA102 -I/SO e3 0910017 20-Lead QFN Example XXXXXX XXXXXX XXXXXX YYWWNNN 28-Lead QFN PIC24F 16KA101 -I/MQ e3 0910017 Example XXXXXXXX XXXXXXXX YYWWNNN 24F16KA 102-I/ML e3 0910017 DS39927B-page 232 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY 30.2 Package Details The following sections give the technical details of the packages. /HDG 3ODVWLF 'XDO ,Q /LQH 3 ± 1RWH PLO %RG\ >3',3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ N NOTE 1 E1 1 2 3 D E A2 L A c A1 b1 b e 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 7RS WR 6HDWLQJ 3ODQH 0ROGHG 3DFNDJH 7KLFNQHVV %DVH WR 6HDWLQJ 3ODQH 6KRXOGHU WR 6KRXOGHU :LGWK 0ROGHG 3DFNDJH :LGWK 2YHUDOO /HQJWK 7LS WR 6HDWLQJ 3ODQH /HDG 7KLFNQHVV 8SSHU /HDG :LGWK /RZHU /HDG :LGWK 2YHUDOO 5RZ 6SDFLQJ † 1 H $ $ $ ( ( ' / F E E H% ± ± ± %6& ± 0,1 ,1&+(6 120 0$; eB ± ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD † 6LJQLILFDQW &KDUDFWHULVWLF 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % © 2009 Microchip Technology Inc. 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Preliminary DS39927B-page 241 PIC24F16KA102 FAMILY NOTES: DS39927B-page 242 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY APPENDIX A: REVISION HISTORY Revision A (November 2008) Original data sheet for the PIC24F16KA102 family of devices. Revision B (March 2009) Section 29.0 “Electrical Characteristics” was revised and minor text edits were made throughout the document. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 243 PIC24F16KA102 FAMILY NOTES: DS39927B-page 244 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY INDEX A A/D 10-Bit High-Speed A/D Converter ............................ 169 Conversion Timing Requirements ............................ 229 Module Specifications .............................................. 228 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Timing Requirements ....................................... 230 A/D Converter Analog Input Model .................................................. 176 Transfer Function ..................................................... 177 AC Characteristics Capacitive Loading Requirements on Output Pins ...................................................... 223 Comparator .............................................................. 227 Comparator Voltage Reference Settling Time ......... 227 CTMU Current Source ............................................. 227 Internal RC Accuracy ............................................... 225 Load Conditions and Requirements ......................... 223 Temperature and Voltage Specifications ................. 223 Assembler MPASM Assembler .................................................. 200 Timer3 (16-Bit Synchronous Mode) ......................... 115 Watchdog Timer (WDT) ........................................... 196 Brown-out Reset Trip Points ............................................................... 214 Brown-out Reset (BOR) ..................................................... 61 C C Compilers MPLAB C18 ............................................................. 200 MPLAB C30 ............................................................. 200 Charge Time Measurement Unit. See CTMU. Code Examples Data EEPROM Bulk Erase ........................................ 55 Data EEPROM Unlock Sequence ............................. 51 Erasing a Program Memory Row, ’C’ Language Code ............................................ 47 Erasing a Program Memory Row, Assembly Language Code ................................ 46 I/O Port Write/Read ................................................. 110 Initiating a Programming Sequence, ’C’ Language Code ............................................ 49 Initiating a Programming Sequence, Assembly Language Code ................................ 49 Loading the Write Buffers, ’C’ Language Code ............................................ 48 Loading the Write Buffers, Assembly Language Code ................................ 48 Programming a Single Word of Flash Program Memory ..................................... 49 PWRSAV Instruction Syntax ................................... 101 Reading the Data EEPROM Using the TBLRD Command ............................................. 56 Sequence for Clock Switching ................................... 98 Setting the RTCWREN Bit ....................................... 152 Single-Word Erase .................................................... 54 Single-Word Write to Data EEPROM ........................ 55 Code Protection ............................................................... 197 Comparator ...................................................................... 179 Comparator Voltage Reference ....................................... 183 Configuration Bits ............................................................ 189 Configuration of Analog, Digital Pins During ICSP Operation .............................................. 18 Core Features ...................................................................... 7 CPU ALU ............................................................................ 23 Control Registers ....................................................... 22 Core Registers ........................................................... 20 Programmer’s Model ................................................. 19 CRC Operation in Power Save Modes ............................. 164 User Interface .......................................................... 164 CTMU Measuring Capacitance ........................................... 185 Measuring Time ....................................................... 186 Pulse Delay and Generation .................................... 186 Customer Change Notification Service ............................ 249 Customer Notification Service ......................................... 249 Customer Support ............................................................ 249 B Basic Connection Requirements ........................................ 15 Baud Rate Generator Setting as a Bus Master ........................................... 137 Block Diagrams 10-Bit High-Speed A/D Converter ............................ 170 16-Bit Timer1 ........................................................... 111 Accessing Program Memory with Table Instructions ............................................. 40 CALL Stack Frame ..................................................... 37 Comparator Module ................................................. 179 Comparator Voltage Reference ............................... 183 CPU Programmer’s Model ......................................... 21 CRC Reconfigured for Polynomial ........................... 164 CRC Shifter Details .................................................. 163 CTMU Connections and Internal Configuration for Capacitance Measurement ......................... 185 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ....... 186 CTMU Typical Connections and Internal Configuration for Time Measurement .............. 186 Data Access From Program Space Address Generation ........................................... 38 High/Low-Voltage Detect (HLVD) ............................ 167 I2C Module ............................................................... 136 Individual Comparator Configurations ...................... 180 Input Capture ........................................................... 119 Output Compare ...................................................... 124 PIC24F CPU Core ..................................................... 20 PIC24F16KA102 Family (General) ............................ 10 PSV Operation ........................................................... 41 Reset System ............................................................. 57 RTCC ....................................................................... 151 Shared I/O Port Structure ........................................ 109 Simplified UART ....................................................... 143 SPI1 Module (Enhanced Buffer Mode) .................... 129 SPI1 Module (Standard Buffer Mode) ...................... 128 System Clock ............................................................. 91 Timer2 (16-Bit Synchronous Mode) ......................... 115 Timer2/3 (32-Bit Mode) ............................................ 114 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 245 PIC24F16KA102 FAMILY D Data EEPROM Erasing ....................................................................... 54 Operations ................................................................. 53 Programming Data EEPROM Bulk Erase ................................ 55 Reading Data EEPROM .................................... 56 Single-Word Write .............................................. 55 Data Memory Address Space ........................................................... 27 Memory Map .............................................................. 27 Near Data Space ....................................................... 28 Organization ............................................................... 28 SFR Space ................................................................. 28 Software Stack ........................................................... 37 Space Width ............................................................... 27 DC Characteristics Comparator .............................................................. 222 Comparator Voltage Reference ............................... 222 Data EEPROM Memory ........................................... 221 I/O Pin Input Specifications ...................................... 220 I/O Pin Output Specifications ................................... 221 Idle Current IIDLE ...................................................... 216 Operating Current IDD .............................................. 214 Power-Down Current IPD ......................................... 217 Program Memory ..................................................... 221 Temperature and Voltage Specifications ................. 213 Deep Sleep BOR (DSBOR) ............................................... 61 Development Support ...................................................... 199 Device Features (Summary) ................................................ 9 Doze Mode ....................................................................... 107 H High/Low-Voltage Detect Characteristics ......................................................... 213 High/Low-Voltage Detect (HLVD) .................................... 167 I I/O Ports Analog Port Configuration ........................................ 110 Input Change Notification ........................................ 110 Open-Drain Configuration ........................................ 110 Parallel (PIO) ........................................................... 109 I2C Clock Rates ............................................................. 137 Communicating as Master in Single Master Environment ........................................ 135 Pin Remapping Options ........................................... 135 Reserved Addresses ............................................... 137 Slave Address Masking ........................................... 137 ICSP Pins .......................................................................... 17 In-Circuit Debugger .......................................................... 197 In-Circuit Serial Programming .......................................... 197 Input Capture ................................................................... 119 Instruction Set Opcode Symbols ..................................................... 204 Overview .................................................................. 205 Summary ................................................................. 203 Inter-Integrated Circuit. See I2C. Internet Address .............................................................. 249 Interrupts Alternate Interrupt Vector Table (AIVT) ..................... 63 Implemented Vectors ................................................. 65 Interrupt Vector Table (IVT) ....................................... 63 Reset Sequence ........................................................ 63 Setup and Service Procedures .................................. 90 Trap Vectors .............................................................. 65 Vector Table .............................................................. 64 E Electrical Characteristics Absolute Maximum Ratings ..................................... 211 Thermal Operating Conditions ................................. 212 V/F Graphs ............................................................... 212 Equations A/D Conversion Clock Period .................................. 176 Baud Rate Reload Calculation ................................. 137 Calculating the PWM Period .................................... 122 Calculation for Maximum PWM Resolution .............. 122 Device and SPI Clock Speed Relationship .............. 134 UART Baud Rate with BRGH = 0 ............................ 144 UART Baud Rate with BRGH = 1 ............................ 144 Errata ................................................................................... 6 External Oscillator Pins ...................................................... 18 M Master Clear (MCLR) Pin .................................................. 16 Microchip Internet Web Site ............................................. 249 MPLAB ASM30 Assembler, Linker, Librarian .................. 200 MPLAB ICD 2 In-Circuit Debugger .................................. 201 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator ................................... 201 MPLAB Integrated Development Environment Software ............................................. 199 MPLAB PM3 Device Programmer ................................... 201 MPLAB REAL ICE In-Circuit Emulator System ............... 201 MPLINK Object Linker/MPLIB Object Librarian ............... 200 F Flash and Data EEPROM Programming Control Registers ....................................................... 51 NVMADR ........................................................... 53 NVMCON ........................................................... 51 NVMKEY ............................................................ 51 Flash Program Memory Control Registers ....................................................... 44 Enhanced ICSP Operation ......................................... 44 Programming Algorithm ............................................. 46 Programming Operations ........................................... 44 RTSP Operation ......................................................... 44 Table Instructions ....................................................... 43 N Near Data Space ............................................................... 28 O Oscillator Configuration Clock Switching ......................................................... 97 Sequence .......................................................... 97 Configuration Values for Clock Selection .................. 92 CPU Clocking Scheme .............................................. 92 Initial Configuration on POR ...................................... 92 Output Compare Continuous Output Pulse Generation ...................... 121 PWM Mode Period and Duty Cycle Calculations ................ 123 Single Output Pulse Generation .............................. 121 DS39927B-page 246 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY P Packaging Details ...................................................................... 233 Marking .................................................................... 231 PICSTART Plus Development Programmer .................... 202 Pinout Descriptions ...................................................... 11–14 Power Supply Pins ............................................................. 16 Power-Saving Features ................................................... 101 Clock Frequency and Clock Switching ..................... 101 Instruction-Based Modes ......................................... 101 Deep Sleep ...................................................... 102 Idle ................................................................... 102 Sleep ................................................................ 101 Product Identification System .......................................... 251 Program and Data Memory Access Using Table Instructions ................................ 39 Program Space Visibility ............................................ 40 Program and Data Memory Spaces Interfacing .................................................................. 37 Program Memory Address Space ........................................................... 25 Memory Map .............................................................. 25 Program Verification ........................................................ 197 Programmable Cyclic Redundancy Check (CRC) Generator .......................................... 163 Pulse-Width Modulation. See PWM. ................................ 122 CMSTAT (Comparator Status) ................................ 182 CMxCON (Comparator x Control) ........................... 181 CORCON (Core Control) ........................................... 68 CORCON (CPU Control) ........................................... 23 CRCCON (CRC Control) ......................................... 165 CRCXOR (CRC XOR Polynomial) .......................... 166 CTMUCON (CTMU Control) .................................... 187 CTMUICON (CTMU Current Control) ...................... 188 CVRCON (Comparator Voltage Reference Control) .......................................... 184 DEVID (Device ID) ................................................... 195 DEVREV (Device Revision) ..................................... 195 DSCON (Deep Sleep Control) ................................. 105 DSWSRC (Deep Sleep Wake-up Source) ............... 106 FBS (Boot Segment Configuration) ......................... 189 FDS (Deep Sleep Configuration) ............................. 194 FGS (General Segment Configuration) ................... 190 FICD (In-Circuit Debugger Configuration) ............... 193 FOSC (Oscillator Configuration) .............................. 191 FOSCSEL (Oscillator Selection Configuration) ....... 190 FPOR (Reset Configuration) ................................... 193 FWDT (Watchdog Timer Configuration) .................. 192 HLVDCON (High/Low-Voltage Detect Control) ....... 168 I2C1CON (I2C1 Control) ......................................... 138 I2C1MSK (I2C1 Slave Mode Address Mask) .......... 142 I2C1STAT (I2C1 Status) .......................................... 140 IC1CON (Input Capture 1 Control) .......................... 120 IEC0 (Interrupt Enable Control 0) .............................. 75 IEC1 (Interrupt Enable Control 1) .............................. 76 IEC3 (Interrupt Enable Control 3) .............................. 77 IEC4 (Interrupt Enable Control 4) .............................. 78 IFS0 (Interrupt Flag Status 0) .................................... 71 IFS1 (Interrupt Flag Status 1) .................................... 72 IFS3 (Interrupt Flag Status 3) .................................... 73 IFS4 (Interrupt Flag Status 4) .................................... 74 INTCON1 (Interrupt Control 1) .................................. 69 INTTREG Interrupt Control and Status ...................... 89 IPC0 (Interrupt Priority Control 0) .............................. 79 IPC1 (Interrupt Priority Control 1) .............................. 80 IPC15 (Interrupt Priority Control 15) .......................... 86 IPC16 (Interrupt Priority Control 16) .......................... 87 IPC18 (Interrupt Priority Control 18) .......................... 88 IPC19 (Interrupt Priority Control 19) .......................... 88 IPC2 (Interrupt Priority Control 2) .............................. 81 IPC3 (Interrupt Priority Control 3) .............................. 82 IPC4 (Interrupt Priority Control 4) .............................. 83 IPC5 (Interrupt Priority Control 5) .............................. 84 IPC7 (Interrupt Priority Control 7) .............................. 85 MINSEC (RTCC Minutes and Seconds Value) ....... 157 MTHDY (RTCC Month and Day Value) ................... 156 NVMCON (Flash Memory Control) ............................ 45 NVMCON (Nonvolatile Memory Control) ................... 52 OC1CON (Output Compare 1 Control) .................... 125 OSCCON (Oscillator Control) .................................... 93 OSCTUN (FRC Oscillator Tune) ............................... 96 PADCFG1 (Pad Configuration Control) ............................................ 126, 142, 154 RCFGCAL (RTCC Calibration and Configuration) .. 153 RCON (Reset Control) ............................................... 58 REFOCON (Reference Oscillator Control) ................ 99 SPI1CON1 (SPI1 Control 1) .................................... 132 SPI1CON2 (SPI1 Control 2) .................................... 133 SPI1STAT (SPI1 Status and Control) ...................... 130 SR (ALU STATUS) .............................................. 22, 67 T1CON (Timer1 Control) ......................................... 112 R Reader Response ............................................................ 250 Reference Clock Output ..................................................... 98 Register Maps A/D Converter (ADC) ................................................. 34 Clock Control ............................................................. 36 CPU Core ................................................................... 29 CRC ........................................................................... 35 CTMU ......................................................................... 34 Deep Sleep ................................................................ 36 Dual Comparator ........................................................ 35 I2C .............................................................................. 32 ICN ............................................................................. 30 Input Capture ............................................................. 31 Interrupt Controller ..................................................... 30 NVM ........................................................................... 36 Output Compare ........................................................ 31 Pad Configuration ...................................................... 33 PMD ........................................................................... 36 PORTA ....................................................................... 33 PORTB ....................................................................... 33 Real-Time Clock and Calendar (RTCC) .................... 35 SPI ............................................................................. 32 Timer .......................................................................... 31 UART ......................................................................... 32 Registers AD1CHS (A/D Input Select) ..................................... 174 AD1CON1 (A/D Control 1) ....................................... 171 AD1CON2 (A/D Control 2) ....................................... 172 AD1CON3 (A/D Control 3) ....................................... 173 AD1CSSL (A/D Input Scan Select, Low) ................. 175 AD1PCFG (A/D Port Configuration) ......................... 175 ALCFGRPT (Alarm Configuration) ........................... 155 ALMINSEC (Alarm Minutes and Seconds Value) ............................................... 159 ALMTHDY (Alarm Month and Day Value) ............... 158 ALWDHR (Alarm Weekday and Hours Value) ......... 158 CLKDIV (Clock Divider) ............................................. 95 © 2009 Microchip Technology Inc. Preliminary DS39927B-page 247 PIC24F16KA102 FAMILY T2CON (Timer2 Control) .......................................... 116 T3CON (Timer3 Control) .......................................... 117 UxMODE (UARTx Mode) ......................................... 146 UxRXREG (UARTx Receive) ................................... 150 UxSTA (UARTx Status and Control) ........................ 148 UxTXREG (UARTx Transmit) .................................. 150 WKDYHR (RTCC Weekday and Hours Value) .................................................... 157 YEAR (RTCC Year Value) ....................................... 156 Resets Clock Source Selection .............................................. 59 Delay Times ............................................................... 60 Device Times ............................................................. 60 RCON Flags Operation .............................................. 59 SFR States ................................................................. 61 Revision History ............................................................... 243 RTCC ............................................................................... 151 Alarm Configuration ................................................. 160 Alarm Mask Settings (figure) .................................... 161 Calibration ................................................................ 160 Register Mapping ..................................................... 152 Selecting Clock Source ............................................ 152 Source Clock ............................................................ 151 Write Lock ................................................................ 152 T Timer1 .............................................................................. 111 Timer2/3 ........................................................................... 113 Timing Diagrams CLKO and I/O Timing .............................................. 226 External Clock .......................................................... 224 Timing Requirements CLKO and I/O .......................................................... 226 External Clock .......................................................... 224 PLL Clock Specifications ......................................... 225 U UART ............................................................................... 143 Baud Rate Generator (BRG) ................................... 144 Break and Sync Transmit Sequence ....................... 145 IrDA Support ............................................................ 145 Operation of UxCTS and UxRTS Control Pins ........ 145 Receiving in 8-Bit or 9-Bit Data Mode ...................... 145 Transmitting in 8-Bit Data Mode .............................. 145 Transmitting in 9-Bit Data Mode .............................. 145 Unused I/Os ....................................................................... 18 V Voltage Regulator Pins ...................................................... 17 S Selective Peripheral Power Control ................................. 107 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 28 Software Simulator (MPLAB SIM) .................................... 200 Software Stack ................................................................... 37 W Watchdog Timer Deep Sleep (DSWDT) ............................................. 197 Watchdog Timer (WDT) ................................................... 196 Windowed Operation ............................................... 196 WWW Address ................................................................ 249 WWW, On-Line Support ...................................................... 6 DS39927B-page 248 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2009 Microchip Technology Inc. Preliminary DS39927B-page 249 PIC24F16KA102 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39927B FAX: (______) _________ - _________ Device: PIC24F16KA102 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39927B-page 250 Preliminary © 2009 Microchip Technology Inc. PIC24F16KA102 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 F 16 KA1 02 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Examples: a) PIC24F16KA102-I/ML: General purpose, 16-Kbyte program memory, 28-pin, Industrial temp.,QFN package. Architecture Flash Memory Family Product Group Pin Count 24 F = 16-bit modified Harvard without DSP = Flash program memory KA1 = General purpose microcontrollers 01 02 I SP SO SS ML P = 20-pin = 28-pin = -40°C to +85°C (Industrial) = = = = = SPDIP SOIC SSOP QFN PDIP Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample © 2009 Microchip Technology Inc. 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