PIC24FJ128GA010_09

PIC24FJ128GA010 Family Data Sheet 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers © 2009 Microchip Technology Inc. DS39747E Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, PIC32 logo, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39747E-page 2 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 64/80/100-Pin General Purpose, 16-Bit Flash Microcontrollers High-Performance CPU: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit x 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Analog Features: • 10-Bit, Up to 16-Channel Analog-to-Digital Converter - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration Peripheral Features: • Two 3-Wire/4-Wire SPI modules, Supporting 4 Frame modes with 8-Level FIFO Buffer • Two I2C™ modules Support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing • Two UART modules: - Supports RS-232, RS-485 and LIN 1.2 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect - 4-level FIFO buffer • Parallel Master Slave Port (PMP/PSP): - Supports 8-bit or 16-bit data - Supports 16 address lines • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • Programmable Cyclic Redundancy Check (CRC) - User-programmable polynomial - 8/16-level FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs • Five 16-Bit Compare/PWM Outputs • High-Current Sink/Source (18 mA/18 mA) on All I/O Pins • Configurable, Open-Drain Output on Digital I/O Pins • Up to 5 External Interrupt Sources • 5.5V Tolerant Input (digital pins only) Special Microcontroller Features: • Operating Voltage Range of 2.0V to 3.6V • Flash Program Memory: - 1000 erase/write cycles - 20-year data retention minimum • Self-Reprogrammable under Software Control • Selectable Power Management modes: - Sleep, Idle and Alternate Clock modes • Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator • On-Chip 2.5V Regulator • JTAG Boundary Scan and Programming Support • Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) • Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Emulation (ICE) via 2 Pins Compare/ PWM Output Comparators Device Pins Program Memory (Bytes) 64K 96K 128K 64K 96K 128K 64K 96K 128K PMP/PSP Y Y Y Y Y Y Y Y Y Capture Input UART SRAM (Bytes) Timers 16-Bit SPI I2C™ 10-Bit A/D (ch) PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ128GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ128GA008 PIC24FJ64GA010 PIC24FJ96GA010 PIC24FJ128GA010 64 64 64 80 80 80 100 100 100 8K 8K 8K 8K 8K 8K 8K 8K 8K 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 © 2009 Microchip Technology Inc. DS39747E-page 3 JTAG Y Y Y Y Y Y Y Y Y PIC24FJ128GA010 FAMILY Pin Diagrams 64-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/IC5/CN13/RD4 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD5/RE5 PMD6/RE6 PMD7/RE7 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/VREF-/AN1/CN3/RB1 PGD1/EMUD1/PMA6/VREF+/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/INT4/RD11 IC3/PMCS2/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/RTCC/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/BCLK1/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PIC24FJXXGA006 PIC24FJXXXGA006 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 AVDD AVSS U2CTS/C1OUT/AN8/RB8 PMA7/C2OUT/AN9/RB9 TMS/PMA13/CVREF/AN10/RB10 TDO/PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 PMA9/U2RX/SDA2/CN17/RF4 PMA8/U2TX/SCL2/CN18/RF5 DS39747E-page 4 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Pin Diagrams (Continued) 80-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T4CK/RC3 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/INT1/RE8 TDO/INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 SDA2/INT4/RA15 SCL2/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PIC24FJXXGA008 PIC24FJXXXGA008 © 2009 Microchip Technology Inc. PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS U2CTS/C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/PMA11/AN12/RB12 TDI/PMA10/AN13/RB13 PMA1/U2RTS/BCLK2/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 DS39747E-page 5 PIC24FJ128GA010 FAMILY Pin Diagrams (Continued)) 100-Pin TQFP 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 RG13 RG12 RG14 PMD1/RE1 PMD0/RE0 RA7 RA6 RG0 RG1 RF1 RF0 ENVREG VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 PMWR/OC5/CN13/RD4 CN19/RD13 IC5/RD12 PMBE/OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/RC4 PMA5/SCK2/CN8/RG6 PMA4/SDI2/CN9/RG7 PMA3/SDO2/CN10/RG8 MCLR PMA2/SS2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 C1IN+/AN5/CN7/RB5 C1IN-/AN4/CN6/RB4 C2IN+/AN3/CN5/RB3 C2IN-/AN2/SS1/CN4/RB2 PGC1/EMUC1/AN1/CN3/RB1 PGD1/EMUD1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC24FJXXGA010 PIC24FJXXXGA010 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/RD0 IC4/PMCS1/RD11 IC3/PMCS2/RD10 IC2/RD9 IC1/RTCC/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PGC2/EMUC2/AN6/OCFA/RB6 PGD2/EMUD2/AN7/RB7 PMA7/VREF-/RA9 PMA6/VREF+/RA10 AVDD AVSS C1OUT/AN8/RB8 C2OUT/AN9/RB9 PMA13/CVREF/AN10/RB10 PMA12/AN11/RB11 VSS VDD TCK/RA1 U2RTS/BCLK2/RF13 U2CTS/RF12 PMA11/AN12/RB12 PMA10/AN13/RB13 PMA1/AN14/RB14 PMA0/AN15/OCFB/CN12/RB15 VSS VDD U1CTS/CN20/RD14 U1RTS/BCLK1/CN21/RD15 PMA9/U2RX/CN17/RF4 PMA8/U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS39747E-page 6 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU............................................................................................................................................................................................ 21 3.0 Memory Organization ................................................................................................................................................................. 27 4.0 Flash Program Memory.............................................................................................................................................................. 47 5.0 Resets ........................................................................................................................................................................................ 53 6.0 Interrupt Controller ..................................................................................................................................................................... 59 7.0 Oscillator Configuration .............................................................................................................................................................. 93 8.0 Power-Saving Features............................................................................................................................................................ 101 9.0 I/O Ports ................................................................................................................................................................................... 103 10.0 Timer1 ...................................................................................................................................................................................... 105 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 107 12.0 Input Capture............................................................................................................................................................................ 113 13.0 Output Compare....................................................................................................................................................................... 115 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 121 15.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 131 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 139 17.0 Parallel Master Port (PMP)....................................................................................................................................................... 147 18.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 157 19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 169 20.0 10-bit High-Speed A/D Converter............................................................................................................................................. 173 21.0 Comparator Module.................................................................................................................................................................. 183 22.0 Comparator Voltage Reference................................................................................................................................................ 187 23.0 Special Features ...................................................................................................................................................................... 189 24.0 Instruction Set Summary .......................................................................................................................................................... 199 25.0 Development Support............................................................................................................................................................... 207 26.0 Electrical Characteristics .......................................................................................................................................................... 211 27.0 Packaging Information.............................................................................................................................................................. 225 Appendix A: Revision History............................................................................................................................................................. 231 Index ................................................................................................................................................................................................. 233 The Microchip Web Site ..................................................................................................................................................................... 237 Customer Change Notification Service .............................................................................................................................................. 237 Customer Support .............................................................................................................................................................................. 237 Reader Response .............................................................................................................................................................................. 238 Product Identification System ............................................................................................................................................................ 239 © 2009 Microchip Technology Inc. DS39747E-page 7 PIC24FJ128GA010 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39747E-page 8 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 1.0 DEVICE OVERVIEW 1.1.2 POWER-SAVING TECHNOLOGY This document contains device-specific information for the following devices: • • • • • • • • • PIC24FJ64GA006 PIC24FJ64GA008 PIC24FJ64GA010 PIC24FJ96GA006 PIC24FJ96GA008 PIC24FJ96GA010 PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 All of the devices in the PIC24FJ128GA010 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ128GA010 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don’t require the numerical processing power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE 1.1.3 OSCILLATOR OPTIONS AND FEATURES Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths, with the ability to move information between data and memory spaces • Linear addressing of up to 8 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’ • Operational performance up to 16 MIPS All of the devices in the PIC24FJ128GA010 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. © 2009 Microchip Technology Inc. DS39747E-page 9 PIC24FJ128GA010 FAMILY 1.1.4 EASY MIGRATION 1.3 Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 64-pin to 80-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. Details on Individual Family Members Devices in the PIC24FJ128GA010 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in two ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GA devices, 96 Kbytes for PIC24FJ96GA devices and 128 Kbytes for PIC24FJ128GA devices). Available I/O pins and ports (53 pins on 6 ports for 64-pin devices, 69 pins on 7 ports for 80-pin devices and 84 pins on 7 ports for 100-pin devices). Note also that, since interrupt-on-change inputs are available on every I/O pin for this family of devices, the number of CN inputs also differs between package sizes. 2. 1.2 Other Special Features • Communications: The PIC24FJ128GA010 family incorporates a range of serial communication peripherals to handle a range of application requirements. All devices are equipped with two independent UARTs with built-in IrDA encoder/decoders. There are also two independent SPI modules, and two independent I2C modules that support both Master and Slave modes of operation. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ128GA010 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. DS39747E-page 10 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ128GA010 FAMILY PIC24FJ128GA006 PIC24FJ128GA008 PIC24FJ128GA010 128K 44,032 PIC24FJ64GA006 PIC24FJ96GA006 PIC24FJ64GA008 PIC24FJ96GA008 PIC24FJ64GA010 PIC24FJ96GA010 96K 32,768 84 100-Pin TQFP Features Operating Frequency Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources (Soft Vectors/NMI Traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Resets (and Delays) Instruction Set Packages 19 Ports B, C, D, E, F, G 53 64K 22,016 96K 32,768 128K 44,032 64K DC – 32 MHz 96K 32,768 8192 43 (39/4) Ports A, B, C, D, E, F, G 69 5 2 5 5 22 Ports A, B, C, D, E, F, G 128K 44,032 64K 22,016 22,016 2 2 2 Yes Yes 16 2 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, Configuration Word Mismatch, Repeat instruction, Hardware Traps (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP 80-Pin TQFP © 2009 Microchip Technology Inc. DS39747E-page 11 PIC24FJ128GA010 FAMILY FIGURE 1-1: PIC24FJ128GA010 FAMILY GENERAL BLOCK DIAGRAM Data Bus PORTA(1) 16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU 16 PORTC RC1:RC4, RC12:RC15 PORTB(1) RB0:RB15 RA0:RA7, RA9:RA10, RA14:15 Interrupt Controller 23 Address Latch Program Memory Data Latch Address Bus 24 Inst Latch Inst Register Instruction Decode & Control Control Signals Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset(2) Literal Data EA MUX 16 16 PORTD(1) RD0:RD15 PORTE(1) RE0:RE9 Divide Support 17x17 Multiplier 16 x 16 W Reg Array PORTF(1) RF0:RF8, RF12:RF13 16-Bit ALU 16 PORTG(1) RG0:RG9, RG12:RG15 OSC2/CLKO OSC1/CLKI VDDCORE/VCAP VDD, VSS MCLR Timer1 Timer2/3 Timer4/5 RTCC 10-Bit ADC Comparators PMP/PSP PWM/ OC1-5 IC1-5 CN1-22(1) SPI1/2 I2C1/2 UART1/2 Note 1: 2: Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. BOR functionality is provided when the on-board voltage regulator is enabled. DS39747E-page 12 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 1-2: Function AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS BCLK1 BCLK2 C1INC1IN+ C1OUT C2INC2IN+ C2OUT CLKI CLKO CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS Pin Number 64-Pin 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 19 20 35 29 12 11 21 14 13 22 39 40 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 80-Pin 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 25 26 38 35 16 15 27 18 17 28 49 50 60 59 20 19 18 17 16 15 6 7 8 10 36 66 67 68 69 39 100-Pin 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 30 31 48 39 21 20 32 23 22 33 63 64 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 I/O I I I I I I I I I I I I I I I I P P O O I I O I I O I O I I I I I I I I I I I I I I I I I I Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA — — — — ANA ANA — ANA ANA — ANA — ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Positive Supply for Analog Modules. Ground Reference for Analog Modules. UART1 IrDA® Baud Clock. UART2 IrDA® Baud Clock. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Main Clock Input Connection. System Clock Output. Interrupt-on-Change Inputs. A/D Analog Inputs. Description TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. DS39747E-page 13 PIC24FJ128GA010 FAMILY TABLE 1-2: Function CN18 CN19 CN20 CN21 CVREF EMUC1 EMUD1 EMUC2 EMUD2 ENVREG IC1 IC2 IC3 IC4 IC5 INT0 INT1 INT2 INT3 INT4 MCLR OC1 OC2 OC3 OC4 OC5 OCFA OCFB OSC1 OSC2 PGC1 PGD1 PGC2 PGD2 Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin 32 — — — 23 15 16 17 18 57 42 43 44 45 52 35 42 43 44 45 7 46 49 50 51 52 17 30 39 40 15 16 17 18 80-Pin 40 65 37 38 29 19 20 21 22 71 54 55 56 57 64 45 13 14 52 53 9 58 61 62 63 66 21 36 49 50 19 20 21 22 100-Pin 50 80 47 48 34 24 25 26 27 86 68 69 70 71 79 55 18 19 66 67 13 72 76 77 78 81 26 44 63 64 24 25 26 27 I/O I I I I O I/O I/O I/O I/O I I I I I I I I I I I I O O O O O I I I O I/O I/O I/O I/O Input Buffer ST ST ST ST ANA ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — — — — ST ST ANA ANA ST ST ST ST Output Compare Fault A Input. Output Compare Fault B Input. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger and ICSP™ Programming Clock. In-Circuit Debugger and ICSP Programming Data. In-Circuit Debugger and ICSP™ Programming Clock. In-Circuit Debugger and ICSP Programming Data. Master Clear (Device Reset) Input. This line is brought low to cause a Reset. Output Compare/PWM Outputs. External Interrupt Inputs. Comparator Voltage Reference Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. Enable for On-Chip Voltage Regulator. Input Capture Inputs. Description Interrupt-on-Change Inputs. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39747E-page 14 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 1-2: Function PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMCS2 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin 30 29 8 6 5 4 16 22 32 31 28 27 24 23 51 45 44 60 61 62 63 64 1 2 3 53 52 80-Pin 36 35 10 8 7 6 24 23 40 39 34 33 30 29 63 57 56 76 77 78 79 80 1 2 3 67 66 100-Pin 44 43 14 12 11 10 29 28 50 49 42 41 35 34 78 71 70 93 94 98 99 100 3 4 5 82 81 I/O I/O I/O O O O O O O O O O O O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST/TTL ST/TTL — — — — — — — — — — — — — ST/TTL — ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe/Address bit 14. Parallel Master Port Chip Select 2 Strobe/Address bit 15. Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Description Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer © 2009 Microchip Technology Inc. DS39747E-page 15 PIC24FJ128GA010 FAMILY TABLE 1-2: Function RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin — — — — — — — — — — — — 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 — — — — 39 47 48 40 80-Pin — — — — — — — — 23 24 52 53 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 4 — 5 — 49 59 60 50 100-Pin 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. PORTA Digital I/O. Description TTL = TTL input buffer ANA = Analog level input/output DS39747E-page 16 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 1-2: Function RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF6 RF7 RF8 RF12 RF13 Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin 46 49 50 51 52 53 54 55 42 43 44 45 — — — — 60 61 62 63 64 1 2 3 — — 58 59 34 33 31 32 35 — — — — 80-Pin 58 61 62 63 66 67 68 69 54 55 56 57 64 65 37 38 76 77 78 79 80 1 2 3 13 14 72 73 42 41 39 40 45 44 43 — — 100-Pin 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 55 54 53 40 39 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTF Digital I/O. PORTE Digital I/O. PORTD Digital I/O. Description TTL = TTL input buffer ANA = Analog level input/output © 2009 Microchip Technology Inc. DS39747E-page 17 PIC24FJ128GA010 FAMILY TABLE 1-2: Function RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RTCC SCK1 SCK2 SCL1 SCL2 SDA1 SDA2 SDI1 SDI2 SDO1 SDO2 SOSCI SOSCO SS1 SS2 T1CK T2CK T3CK T4CK T5CK TCK TDI TDO TMS Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin — — 37 36 4 5 6 8 — — — — 42 35 4 37 32 36 31 34 5 33 6 47 48 14 8 48 — — — — 27 28 24 23 80-Pin 75 74 47 46 6 7 8 10 — — — — 54 45 6 47 52 46 53 44 7 43 8 59 60 18 10 60 4 — 5 — 33 34 14 13 100-Pin 90 89 57 56 10 11 12 14 96 97 95 1 68 55 10 57 58 56 59 54 11 53 12 73 74 23 14 74 6 7 8 9 38 60 61 17 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I I O O I O I/O I/O I I I I I I I O I Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST — — ST I2C I2C I2C IC ST ST — — ANA ANA ST ST ST ST ST ST ST ST ST — ST 2 Description PORTG Digital I/O. Real-Time Clock Alarm Output. SPI1 Serial Clock Output. SPI2 Serial Clock Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. SPI1 Serial Data Input. SPI2 Serial Data Input. SPI1 Serial Data Output. SPI2 Serial Data Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Slave Select Input/Frame Select Output (SPI1). Slave Select Input/Frame Select Output (SPI2). Timer1 Clock. Timer2 External Clock Input. Timer3 External Clock Input. Timer4 External Clock Input. Timer5 External Clock Input. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39747E-page 18 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 1-2: Function U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDD VDDCAP VDDCORE VREFVREF+ VSS Legend: PIC24FJ128GA010 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin 43 35 34 33 21 29 31 32 10, 26, 38 56 56 15 16 9, 25, 41 80-Pin 37 38 42 41 27 35 39 40 12, 32, 48 70 70 23 24 11, 31, 51 100-Pin 47 48 52 51 40 39 49 50 2, 16, 37, 46, 62 85 85 28 29 15, 36, 45, 65, 75 I/O I O I O I O I O P P P I I P Input Buffer ST — ST DIG ST — ST — — — — ANA ANA — Description UART1 Clear to Send Input. UART1 Request to Send Output. UART1 Receive. UART1 Transmit Output. UART2 Clear to Send Input. UART2 Request to Send Output. UART 2 Receive Input. UART2 Transmit Output. Positive Supply for Peripheral Digital Logic and I/O Pins. External Filter Capacitor Connection (regulator enabled). Positive Supply for Microcontroller Core Logic (regulator disabled). A/D and Comparator Reference Voltage (Low) Input. A/D and Comparator Reference Voltage (High) Input. Ground Reference for Logic and I/O Pins. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer © 2009 Microchip Technology Inc. DS39747E-page 19 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 20 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 2.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 2. “CPU” (DS39703) in the “PIC24F Family Reference Manual” for more information. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three-parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports signed, unsigned and Mixed mode 16-bit by 16-bit or 8-bit by 8-bit integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative, non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism, and a selection of iterative divide instructions, to support 32-bit (or 16-bit) divided by 16-bit integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set, and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported either directly or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to 7 addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. 2.1 Programmer’s Model The programmer’s model for the PIC24F is shown in Figure 2-2. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer’s model are memory mapped. © 2009 Microchip Technology Inc. DS39747E-page 21 PIC24FJ128GA010 FAMILY FIGURE 2-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCL PCH Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16 PIC24F CPU CORE BLOCK DIAGRAM 23 Address Latch Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX Instruction Decode & Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS39747E-page 22 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 2-1: W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON CPU CORE REGISTERS Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register Register(s) Name FIGURE 2-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Working/Address Registers Divider Working Registers Multiplier Registers SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL 0 0 0 0 Stack Pointer Limit Program Counter Data Table Page Address 0 Program Space Visibility Page Address Repeat Loop Counter 0 STATUS Register (SR) 0 — — — — — — — DC IPL RA N OV Z C 210 15 0 Core Control Register (CORCON) — — — — — — — — — — — — IPL3 PSV — — Registers or bits shadowed for PUSH.S and POP.S instructions. © 2009 Microchip Technology Inc. DS39747E-page 23 PIC24FJ128GA010 FAMILY 2.2 CPU Control Registers SR: CPU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(1) IPL1(2) R/W-0(1) IPL0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 REGISTER 2-1: U-0 — bit 15 R/W-0(1) IPL2(2) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred IPL2:IPL0: CPU Interrupt Priority Level Status bits(2) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. The value in parentheses indicates the IPL when IPL3 = 1. bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39747E-page 24 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 2-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0 CORCON: CORE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ User interrupts are disabled when IPL3 = 1. bit 2 bit 1-0 Note 1: © 2009 Microchip Technology Inc. DS39747E-page 25 PIC24FJ128GA010 FAMILY 2.3 Arithmetic Logic Unit (ALU) 2.3.2 DIVIDER The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operation with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m+1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2.3.3 MULTI-BIT SHIFT SUPPORT 2.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. TABLE 2-2: Instruction ASR SL LSR INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits. DS39747E-page 26 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 3.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ128GA010 family of devices are shown in Figure 3-1. 3.1 Program Address Space The program address memory space of PIC24FJ128GA010 family devices is 4M instructions. The space is addressable by a 24-bit value derived from FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES PIC24FJ64GA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words PIC24FJ96GA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (32K instructions) PIC24FJ128GA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h User Memory Space User Flash Program Memory (44K instructions) 00ABFEh 00AC00h 00FFFEh 010000h Flash Config Words Flash Config Words Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) 0157FEh 015800h 7FFFFEh 800000h Reserved Reserved Reserved Configuration Memory Space Device Configuration Registers Device Configuration Registers Device Configuration Registers F7FFFEh F80000h F8000Eh F80010h Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) FEFFFEh FF0000h FFFFFEh Note: Memory areas are not shown to scale. © 2009 Microchip Technology Inc. DS39747E-page 27 PIC24FJ128GA010 FAMILY 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ128GA010 family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ128GA010 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 23.1 “Configuration Bits”. 3.1.2 HARD MEMORY VECTORS All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h, with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. TABLE 3-1: FLASH CONFIGURATION WORDS FOR PIC24FJ128GA010 FAMILY DEVICES Program Memory (Words) 22,016 32,768 44,032 Configuration Word Addresses 00ABFCh: 00ABFEh 00FFFCh: 00FFFEh 0157FCh: 0157FEh Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA FIGURE 3-2: msw Address 000001h 000003h 000005h 000007h PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (lsw Address) DS39747E-page 28 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 3.2 Note: Data Address Space This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 3. “Data Memory” (DS39717) in the “PIC24F Family Reference Manual” for more information. memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility”). PIC24FJ128GA010 family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide, and point to bytes within the data space. This gives a data space address range of 64 Kbytes, or 32K words. The lower half of the data 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ128GA010 FAMILY DEVICES MSB Address 0001h 07FFh 0801h MSB SFR Space LSB LSB Address 0000h 07FEh 0800h SFR Space Near Data Space Implemented Data RAM Data RAM 1FFFh 2001h 27FFh 2801h Unimplemented Read as ‘0’ 7FFFh 8001h 7FFFh 8000h 1FFEh 2000h 27FEh 2800h Program Space Visibility Area FFFFh Note: Data memory areas are not shown to scale. FFFEh © 2009 Microchip Technology Inc. DS39747E-page 29 PIC24FJ128GA010 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 NEAR DATA SPACE The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. 3.2.4 SFR SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30. TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 Core Timers I 2C™ xx40 Capture xx60 ICN — SPI — — — — NVM/PMD xx80 Compare — — — — — — xxA0 Interrupts — — — — — — — xxC0 — I/O — — — I/O — xxE0 — — — — — — 000h 100h 200h 300h 400h 500h 600h 700h — — PMP — UART A/D — — RTC/Comp — — — — CRC System Legend: — = No implemented SFRs in this block DS39747E-page 30 © 2009 Microchip Technology Inc. © 2009 Microchip Technology Inc. DS39747E-page 31 TABLE 3-3: File Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Program Counter Low Word — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Repeat Loop Counter DC — IPL2 — IPL1 — IPL0 — RA — N IPL3 OV PSV Z — C — Program Counter High Byte Table Page Address Pointer Program Memory Visibility Page Address Pointer PIC24FJ128GA010 FAMILY 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx Disable Interrupts Counter x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-4: File Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C2 00C4 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT — U2TXIF — — — — U2TXIE — — — — — — — — — — — — — — — — — — — Bit 14 — DISI — U2RXIF — RTCIF — — U2RXIE — RTCIE — T1IP2 T2IP2 — CNIP2 — T4IP2 U2TXIP2 — IC5IP2 — — — — — CRCIP2 Bit 13 — — AD1IF INT2IF PMPIF — — AD1IE INT2IE PMPIE — — T1IP1 T2IP1 — CNIP1 — T4IP1 U2TXIP1 — IC5IP1 — — — — — CRCIP1 Bit 12 — — U1TXIF T5IF — — — U1TXIE T5IE — — — T1IP0 T2IP0 — CNIP0 — T4IP0 U2TXIP0 — IC5IP0 — — — — — CRCIP0 Bit 11 — — U1RXIF T4IF — — — U1RXIE T4IE — — — — — — — — — — — — — — — — — — — Bit 10 — — SPI1IF OC4IF — — — SPI1IE OC4IE — — — OC1IP2 OC2IP2 SPI1IP2 — CMIP2 — OC4IP2 — IC4IP2 — — INT4IP2 RTCIP2 Bit 9 — — SPF1IF OC3IF OC5IF — — SPF1IE OC3IE OC5IE — — OC1IP1 OC2IP1 SPI1IP1 — CMIP1 — OC4IP1 — IC4IP1 — — INT4IP1 RTCIP1 Bit 8 — — T3IF — — — — T3IE — — — — OC1IP0 OC2IP0 SPI1IP0 — CMIP0 — OC4IP0 — IC4IP0 — — INT4IP0 RTCIP0 Bit 7 — — T2IF — IC5IF — — T2IE — IC5IE — — — — — — — — — — — — — — — — — — Bit 6 — — OC2IF — IC4IF INT4IF — OC2IE — IC4IE INT4IE — IC1IP2 IC2IP2 SPF1IP2 AD1IP2 — OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 INT3IP2 — Bit 5 — — IC2IF — IC3IF INT3IF — IC2IE — IC3IE INT3IE — IC1IP1 IC2IP1 SPF1IP1 AD1IP1 — OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 INT3IP1 — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — INT0EP INT0IF SI2C1IF SPF2IF — — INT0IE SI2C1IE SPF2IE — — INT0IP0 — T3IP0 U1TXIP0 INT1IP0 — T5IP0 SPF2IP0 — — — — — — — All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 0004 4440 4444 0044 4440 0040 0040 0440 0440 0400 4440 DS39747E-page 32 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY MATHERR ADDRERR STKERR OSCFAIL INT4EP — INT1IF — — — — INT1IE — — — IC1IP0 IC2IP0 SPF1IP0 AD1IP0 — OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2IP0 INT3IP0 — U1ERIP0 INT3EP T1IF CNIF — — CRCIF T1IE CNIE — — CRCIE — — — — — — — — — — — — — — — — INT2EP OC1IF CMIF — MI2C2IF U2ERIF OC1IE CMIE — MI2C2IE U2ERIE INT0IP2 — T3IP2 U1TXIP2 INT1IP2 — T5IP2 SPF2IP2 — — — — — — — INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 — T3IP1 U1TXIP1 INT1IP1 — T5IP1 SPF2IP1 — — — — — — — U1RXIP2 U1RXIP1 U1RXIP0 MI2C1IP2 MI2C1IP1 MI2C1IP0 SI2C1IP2 SI2C1IP1 SI2C1IP0 U2RXIP2 U2RXIP1 U2RXIP0 MI2C2IP2 MI2C2IP1 MI2C2IP0 SI2C2IP2 SI2C2IP1 IPC15 IPC16 Legend: U2ERIP2 U2ERIP1 U2ERIP0 U1ERIP2 U1ERIP1 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-5: File Name Addr ICN REGISTER MAP Bit 15 CN15IE — — Bit 14 CN14IE — — Bit 13 CN13IE — — Bit 12 CN12IE — — Bit 11 CN11IE — — Bit 10 CN10IE — — Bit 9 CN9IE — — Bit 8 CN8IE — — Bit 7 CN7IE — — Bit 6 CN6IE — — Bit 5 CN5IE CN21IE(1) CN5PUE Bit 4 CN4IE CN20IE(1) CN4PUE Bit 3 CN3IE CN19IE(1) CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 © 2009 Microchip Technology Inc. DS39747E-page 33 CNEN1 0060 CNEN2 0062 CNPU2 006A Legend: Note 1: CNPU1 0068 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal Implemented in 80-pin and 100-pin devices only. CN21PUE(1) CN20PUE(1) CN19PUE(1) CN18PUE CN17PUE CN16PUE TABLE 3-6: File Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 PR5 T4CON T5CON Legend: Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF Timer1 Register Period Register 1 TON — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — Timer2 Register Timer3 Holding Register (For 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON — — TSIDL TSIDL — — — — — — — — — — — — TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 — — — TCS TCS — — PIC24FJ128GA010 FAMILY 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF Timer4 Register Timer5 Holding Register (For 32-bit operations only) Timer5 Register Period Register 4 Period Register 5 TON TON — — TSIDL TSIDL — — — — — — — — — — — — TGATE TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 — — — TCS TCS — — 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-7: File Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON Legend: Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI1 ICI1 ICI1 ICI1 ICI1 ICI0 ICI0 ICI0 ICI0 ICI0 ICOV ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICBNE ICM2 ICM2 ICM2 ICM2 ICM2 ICM1 ICM1 ICM1 ICM1 ICM1 ICM0 ICM0 ICM0 ICM0 ICM0 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 DS39747E-page 34 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY Input 1 Capture Register — — — — — — — — — — ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL — — — — — — — — — — — — — — — — — — — — — — — — — ICTMR ICTMR ICTMR ICTMR ICTMR Input 2 Capture Register Input 3 Capture Register Input 4 Capture Register Input 5 Capture Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-8: File Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON Legend: Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 xxxx xxxx — OCFLT OCTSEL OCM2 OCM1 OCM0 0000 Output Compare 1 Secondary Register Output Compare 1 Register — — OCSIDL — — — — — — — Output Compare 2 Secondary Register Output Compare 2 Register — — OCSIDL — — — — — — — Output Compare 3 Secondary Register Output Compare 3 Register — — OCSIDL — — — — — — — Output Compare 4 Secondary Register Output Compare 4 Register — — OCSIDL — — — — — — — Output Compare 5 Secondary Register Output Compare 5 Register — — OCSIDL — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2009 Microchip Technology Inc. DS39747E-page 35 TABLE 3-9: File Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — ACKDT D/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator ACKEN P RCEN S Address Register Address Mask — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-10: File Name I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Addr 0210 0212 0214 0216 0218 021A 021C I2C2 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2CPOV Bit 8 — — ACKDT D/A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R/W RSEN RBF SEN TBF 1000 0000 0000 0000 S PIC24FJ128GA010 FAMILY Receive Register Transmit Register Baud Rate Generator ACKEN P RCEN Address Register Address Mask — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-11: File Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — TXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 PDSEL1 FERR Bit 1 PDSEL0 OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 DS39747E-page 36 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY URXISEL1 URXISEL0 Transmit Register Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-12: File Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: Addr 0230 0232 0234 0236 0238 UART2 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — TXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 RXINV RIDLE Bit 3 BRGH PERR Bit 2 PDSEL1 FERR Bit 1 PDSEL0 OERR Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 URXISEL1 URXISEL0 Transmit Register Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-13: File Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — SPIFPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN — Bit 6 SPIROV CKP — Bit 5 SRXMPT MSTEN — Bit 4 SISEL2 SPRE2 — Bit 3 SISEL1 SPRE1 — Bit 2 SISEL0 SPRE0 — Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000 SPIBEC2 SPIBEC1 SPIBEC0 MODE16 — SMP — CKE — SPI1 Transmit and Receive Buffer — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-14: File Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: Addr 0260 0262 0264 0268 SPI2 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — SPIFPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN — Bit 6 SPIROV CKP — Bit 5 SRXMPT MSTEN — Bit 4 SISEL2 SPRE2 — Bit 3 SISEL1 SPRE1 — Bit 2 SISEL0 SPRE0 — Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000 SPIBEC2 SPIBEC1 SPIBEC0 MODE16 — SMP — CKE — SPI2 Transmit and Receive Buffer — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-15: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0328 032C 0330 ADC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC1 — ADCS6 — PCFG6 CSSL6 SSRC0 SMPI3 ADCS5 — PCFG5 CSSL5 — SMPI2 ADCS4 — PCFG4 CSSL4 — SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 0000 0000 0000 0000 0000 0000 © 2009 Microchip Technology Inc. DS39747E-page 37 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON VCFG2 ADRC CH0NB PCFG15 CSSL15 — VCFG1 — — PCFG14 CSSL14 ADSIDL VCFG0 — — PCFG13 CSSL13 — r SAMC4 — PCFG12 CSSL12 — — SAMC3 CH0SB3 PCFG11 CSSL11 — CSCNA SAMC2 CH0SB2 PCFG10 CSSL10 FORM1 — SAMC1 CH0SB1 PCFG9 CSSL9 FORM0 — SAMC0 CH0SB0 PCFG8 CSSL8 SSRC2 BUFS ADCS7 CH0NA PCFG7 CSSL7 PIC24FJ128GA010 FAMILY x = unknown value on Reset, — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. TABLE 3-16: File Name TRISA PORTA LATA ODCA Legend: Note 1: 2: Addr 02C0 02C2 02C4 06C0 PORTA REGISTER MAP Bit 15 Bit 14 Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 Bit 9 Bit 8 — — — — Bit 7 TRISA7 RA7 LATA7 ODA7) Bit 6 TRISA6 RA6 LATA6 ODA6 Bit 5 TRISA5(2) RA5 (2) Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets C6FF xxxx xxxx 0000 TRISA15(1) TRISA14(1) RA15(1) LATA15(1) ODA15(1) RA14 (1) TRISA10(1) TRISA9(1) RA10 (1) TRISA4(2) TRISA3(2) TRISA2(2) TRISA1(2) TRISA0(2) RA4(2) LATA4(2) ODA4(2) RA3(2) LATA3(2) ODA3(2) RA2(2) LATA2(2) ODA2(2) RA1(2) LATA1(2) ODA1(2) RA0(2) LATA0(2) ODA0(2) RA9 (1) LATA14(1) ODA14(1) LATA10(1) ODA10(1) LATA9(1) ODA9(1) LATA5(2) ODA5(2) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only. DS39747E-page 38 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 3-17: File Name TRISB PORTB LATB ODCB Legend: Note 1: Addr 02C6 02C8 02CA 06C6 PORTB REGISTER MAP Bit 15 TRISB15 RB15 LATB15 ODB15 Bit 14 TRISB14 RB14 LATB14 ODB14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 TRISB9 RB9 LATB9 ODB9 Bit 8 TRISB8 RB8 LATB8 ODB8 Bit 7 TRISB7 RB7 LATB7 ODB7 Bit 6 TRISB6 RB6 LATB6 ODB6 Bit 5 TRISB5 RB5 LATB5 ODB5 Bit 4 TRISB4 RB4 LATB4 ODB4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 All Resets FFFF xxxx xxxx 0000 TRISB13(1) TRISB12(1) TRISB11(1) TRISB10(1) RB13(1) LATB13(1) ODB13(1) RB12(1) LATB12(1) ODB12(1) RB11(1) LATB11(1) ODB11(1) RB10(1) LATB10(1) ODB10(1) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices Unimplemented when JTAG is enabled. TABLE 3-18: File Name TRISC PORTC LATC ODCC Legend: Note 1: 2: Addr 02CC 02CE 02D0 06CC PORTC REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 — — — — Bit 7 — — — — Bit 6 — — — — Bit 5 — — — — Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — — — — All Resets F01E xxxx xxxx 0000 TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 ODC15 RC14 LATC14 ODC14 RC13 LATC13 ODC13 RC12 LATC12 ODC12 TRISC4(2) TRISC3(1) TRISC2(2) TRISC1(1) RC4(2) LATC4(2) ODC4(2) RC3(1) LATC3(1) ODC3(1) RC2(2) LATC2(2) ODC2(2) RC1(1) LATC1(1) ODC1(1) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. Implemented in 100-pin devices only TABLE 3-19: File Name TRISD PORTD LATD ODCD Legend: Note 1: Addr 02D2 02D4 02D6 06D2 PORTD REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 TRISD11 RD11 LATD11 ODD11 Bit 10 TRISD10 RD10 LATD10 ODD10 Bit 9 TRISD9 RD9 LATD9 ODD9 Bit 8 TRISD8 RD8 LATD8 ODD8 Bit 7 TRISD7 RD7 LATD7 ODD7 Bit 6 TRISD6 RD6 LATD6 ODD6 Bit 5 TRISD5 RD5 LATD5 ODD5 Bit 4 TRISD4 RD4 LATD4 ODD4 Bit 3 TRISD3 RD3 LATD3 ODD3 Bit 2 TRISD2 RD2 LATD2 ODD2 Bit 1 TRISD1 RD1 LATD1 ODD1 Bit 0 TRISD0 RD0 LATD0 ODD0 All Resets FFFF xxxx xxxx 0000 TRISD15(1) TRISD14(1) TRISD13(1) TRISD12(1) RD15(1) LATD15(1) ODD15(1) RD14(1) LATD14(1) ODD14(1) RD13(1) LATD13(1) ODD13(1) RD12(1) LATD12(1) ODD12(1) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. TABLE 3-20: File Name TRISE PORTE LATE ODCE Legend: Note 1: Addr 02D8 02DA 02DC 06D8 PORTE REGISTER MAP Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 Bit 8 Bit 7 TRISE7 RE7 LATE7 ODE7 Bit 6 TRISE6 RE6 LATE6 ODE6 Bit 5 TRISE5 RE5 LATE5 ODE5 Bit 4 TRISE4 RE4 LATE4 ODE4 Bit 3 TRISE3 RE3 LATE3 ODE3 Bit 2 TRISE2 RE2 LATE2 ODE2 Bit 1 TRISE1 RE1 LATE1 ODE1 Bit 0 TRISE0 RE0 LATE0 ODE0 All Resets 03FF xxxx xxxx 0000 © 2009 Microchip Technology Inc. DS39747E-page 39 TRISE9(1) TRISE8(1) RE9(1) LATE9(1) ODE9(1) RE8(1) LATE8(1) ODE8(1) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 80-pin and 100-pin devices only. TABLE 3-21: File Name TRISF PORTF LATF ODCF Legend: Note 1: 2: Addr 02DE 02E0 02E2 06DE PORTF REGISTER MAP Bit 15 — — — — Bit 14 — — — — Bit 13 TRISF13( 1) Bit 12 TRISF12( 1) Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 Bit 7 Bit 6 TRISF6 RF6 LATF6 ODF6 Bit 5 TRISF5 RF5 LATF5 ODF5 Bit 4 TRISF4 RF4 LATF4 ODF4 Bit 3 TRISF3 RF3 LATF3 ODF3 Bit 2 TRISF2 RF2 LATF2 ODF2 Bit 1 TRISF1 RF1 LATF1 ODF1 Bit 0 TRISF0 RF0 LATF0 ODF0 All Resets 31FF xxxx xxxx 0000 TRISF8(2 TRISF7(2 ) ) RG13(1) ODF13(1) RG12(1) ODF12(1) RF8(2) LATF8(2) ODF8(2) RF7(2) LATF7(2) ODF7(2) PIC24FJ128GA010 FAMILY LATF13(1) LATF12(1) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. TABLE 3-22: File Name TRISG PORTG LATG ODCG Legend: Note 1: 2: Addr 02E4 02E6 02E8 06E4 PORTG REGISTER MAP Bit 15 TRISG15 RG15 LATG15 ODG15 Bit 14 Bit 13 Bit 12 Bit 11 — — — — Bit 10 — — — — Bit 9 TRISG9 RG9 LATG9 ODG9 Bit 8 Bit 7 Bit 6 TRISG6 RG6 LATG6 ODG6 Bit 5 — — — — Bit 4 — — — — Bit 3 TRISG3 RG3 LATG3 ODG3 Bit 2 TRISG2 RG2 LATG2 ODG2 Bit 1 Bit 0 All Resets F3CF xxxx xxxx 0000 TRISG14(1) TRISG13(1) TRISG12(1 RG14(1) LATG14(1) ODG14(1) RG13(1) LATG13(1) ODG13(1) RG12(1) LATG12(1) ODG12(1) TRISG8 TRISG7 RG8 LATG8 ODG8 RG7 LATG7 ODG7 TRISG1(2) TRISG0(2) RG1(2) LATG1(2) ODG1(2) RG0(2) LATG0(2) ODG0(2) x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. Implemented in 100-pin devices only. Implemented in 80-pin and 100-pin devices only. TABLE 3-23: File Name PADCFG1 Legend: Addr 02FC PAD CONFIGURATION MAP Bit 15 — Bit 14 — Bit 13 — Bit 12 — Bit 11 — Bit 10 — Bit 9 — Bit 8 — Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 RTSECSEL Bit 0 PMPTTL All Resets 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for 100-pin devices. TABLE 3-24: File Name PMCON PMMODE PMADDR(1) PMDOUT1(1) PMDOUT2 PMDIN1 PMDIN2 PMAEN PMSTAT Legend: Note 1: Addr 0600 0602 0604 0606 0608 060A 060C 060E PARALLEL MASTER/SLAVE PORT REGISTER MAP Bit 15 PMPEN BUSY CS2 Bit 14 — IRQM1 CS1 Bit 13 PSIDL IRQM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CSF1 WAITB1 Bit 6 CSF0 WAITB0 Bit 5 ALP WAITM3 Bit 4 CS2P WAITM2 Bit 3 CS1P WAITM1 Bit 2 BEP WAITM0 Bit 1 WRSP WAITE1 Bit 0 RDSP WAITE0 All Resets 0000 0000 0000 0000 0000 0000 0000 PTEN5 — PTEN4 — PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E 0000 008F DS39747E-page 40 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN INCM1 INCM0 MODE16 MODE1 MODE0 Parallel Port Destination Address (Master modes) Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) PTEN15 IBF PTEN14 IBOV PTEN13 — PTEN12 — PTEN11 IB3F PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 OBE PTEN6 OBUF — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PMADDR and PMDOUT1 share the same physical register. The register functions as PMDOUT1 only in Slave modes, and as PMADDR only in Master modes. TABLE 3-25: File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL(1) Legend: Note 1: Addr 0620 0622 0624 0626 REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ARPT5 CAL5 ARPT4 CAL4 ARPT3 CAL3 ARPT2 CAL2 ARPT1 CAL1 ARPT0 CAL0 0000 xxxx 0000 Alarm Value Register Window Based on ALRMPTR ALRMEN RTCEN CHIME — AMASK3 AMASK2 AMASK1 AMASK0 RTCOE ALRMPTR1 ALRMPTR0 RTCPTR1 RTCPTR0 ARPT7 CAL7 ARPT6 CAL6 RTCC Value Register Window Based on RTCPTR RTCWREN RTCSYNC HALFSEC x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCFGCAL register Reset value dependent on type of Reset. TABLE 3-26: File Name CMCON CVRCON Legend: Addr 0630 0632 DUAL COMPARATOR REGISTER MAP Bit 15 CMIDL — Bit 14 — — Bit 13 C2EVT — Bit 12 C1EVT — Bit 11 C2EN — Bit 10 C1EN — Bit 9 C2OUTEN — Bit 8 C1OUTEN — Bit 7 C2OUT CVREN Bit 6 C1OUT CVROE Bit 5 C2INV CVRR Bit 4 C1INV CVRSS Bit 3 C2NEG CVR3 Bit 2 C2POS CVR2 Bit 1 C1NEG CVR1 Bit 0 C1POS CVR0 All Resets 0000 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-27: File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646 CRC REGISTER MAP Bit 15 — Bit 14 — Bit 13 CSIDL Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — Bit 4 CRCGO Bit 3 PLEN3 Bit 2 PLEN2 Bit 1 PLEN1 Bit 0 PLEN0 All Resets 0000 0000 0000 0000 © 2009 Microchip Technology Inc. DS39747E-page 41 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT CRC XOR Polynomial Register CRC Data Input Register CRC Result Register — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-28: File Name RCON OSCCON CLKDIV OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0748 SYSTEM REGISTER MAP Bit 15 TRAPR — ROI — Bit 14 IOPUWR COSC2 DOZE2 — Bit 13 — COSC1 DOZE1 — Bit 12 — COSC0 DOZE0 — Bit 11 — — DOZEN — Bit 10 — NOSC2 RCDIV2 — Bit 9 CM NOSC1 RCDIV1 — Bit 8 VREGS NOSC0 RCDIV0 — Bit 7 EXTR CLKLOCK — — Bit 6 SWR — — — Bit 5 SWDTEN LOCK — Bit 4 WDTO — — Bit 3 SLEEP CF — Bit 2 IDLE — — Bit 1 BOR SOSCEN — Bit 0 POR OSWEN — All Resets xxxx(1) xxxx(2) 0100 0000 PIC24FJ128GA010 FAMILY TUN x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 3-29: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR — Bit 14 WREN — Bit 13 WRERR — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — Bit 6 ERASE Bit 5 — Bit 4 — Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000 NVMOP3 NVMOP2 NVMOP1 NVMOP0 NVMKEY — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 3-30: File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774 PMD REGISTER MAP Bit 15 T5MD — — Bit 14 T4MD — — Bit 13 T3MD — — Bit 12 T2MD IC5MD — Bit 11 T1MD IC4MD — Bit 10 — IC3MD Bit 9 — IC2MD Bit 8 — IC1MD PMPMD Bit 7 I2C1MD — CRCPMD Bit 6 U2MD — — Bit 5 U1MD — — Bit 4 SPI2MD OC5MD — Bit 3 SPI1MD OC4MD — Bit 2 — OC3MD — Bit 1 — OC2MD I2C2MD Bit 0 ADC1MD OC1MD — All Resets 0000 0000 0000 CMPMD RTCCMD — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24FJ128GA010 FAMILY 3.2.5 SOFTWARE STACK 3.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. 3.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, whereas D refers to a data space word. FIGURE 3-4: 0000h 15 CALL STACK FRAME 0 Stack Grows Towards Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] DS39747E-page 42 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: User 0 0 Program Space Address 0 TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx PSVPAG xxxx xxxx PC 0xx xxxx xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2009 Microchip Technology Inc. DS39747E-page 43 PIC24FJ128GA010 FAMILY 3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P) to a data address. Note that D, the “phantom byte”, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D of the data address, as above. Note that the data will always be ‘0’ when the upper “phantom” byte is selected (byte select = 1). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space, without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P) to a data address (D). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the Table Page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed. FIGURE 3-6: TBLPAG 02 ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA 23 15 0 000000h 00000000 00000000 00000000 00000000 23 16 8 0 020000h 030000h ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 800000h DS39747E-page 44 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. FIGURE 3-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 000000h 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... Data Space 0000h Data EA 8000h PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. FFFFh 800000h © 2009 Microchip Technology Inc. DS39747E-page 45 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 46 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 4.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 4. “Program Memory” (DS39715) in the “PIC24F Family Reference Manual” for more information. controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time. The PIC24FJ128GA010 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in four ways: 1. 2. 3. 4. In-Circuit Serial Programming™ (ICSP™) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP) 4.1 Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ICSP allows a PIC24FJ128GA010 family device to be serially programmed while in the end application circuit. This is simply done with two lines for Programming Clock and Programming Data (which are named PGCx and PGDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the micro- FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits User/Configuration Space Select 24-Bit EA Byte Select © 2009 Microchip Technology Inc. DS39747E-page 47 PIC24FJ128GA010 FAMILY 4.2 RTSP Operation 4.4 The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended. Enhanced In-Circuit Serial Programming Enhanced In-Circuit Serial Programming uses an onboard bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. See the device programming specification for more information on Enhanced ICSP 4.5 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 “Programming Operations” for further details. 4.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or an erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection. As a result, avoid performing page erase operations on the last page of program memory. All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row 4.3 JTAG Operation The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF). DS39747E-page 48 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 4-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable-Only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) NVMOP3 (2) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) NVMOP2 (2) R/W-0(1) NVMOP1 (2) R/W-0(1) NVMOP0(2) bit 0 WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command Unimplemented: Read as ‘0’ NVMOP3:NVMOP0: NVM Operation Select bits(2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) These bits can only be reset on POR. All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSP™ mode only. Refer to device programming specification. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: 3: © 2009 Microchip Technology Inc. DS39747E-page 49 PIC24FJ128GA010 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3. EXAMPLE 4-1: ERASING A PROGRAM MEMORY BLOCK ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (see Section 19.3.2 “Interrupt Operation”). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. 19.3.2 INTERRUPT OPERATION When VWORD4:VWORD0 make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. DS39747E-page 170 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 19-1: U-0 — bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-1 CRCMPT U-0 — R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 U-0 — CRCCON: CRC CONTROL REGISTER R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 R/W-0 PLEN0 bit 0 Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 ≤ 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as ‘0’ CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 19.4 19.4.1 Operation in Power Save Modes SLEEP MODE 19.4.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. © 2009 Microchip Technology Inc. DS39747E-page 171 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 172 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 20.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 17. “10-Bit A/D Converter” (DS39705) in the “PIC24F Family Reference Manual” for more information. A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1. Configure the A/D module: a) Select port pins as analog inputs (AD1PCFG). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. The 10-bit A/D Converter has the following key features: • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps Up to 16 analog input pins External voltage reference input pins Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. Depending on the particular device pinout, the 10-bit A/D Converter can have up to 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device. Refer to the device data sheet for further details. © 2009 Microchip Technology Inc. DS39747E-page 173 PIC24FJ128GA010 FAMILY Figure 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD AVSS VREF+ VREFAN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 MUX B AN10 AN11 AN12 AN13 AN14 AN15 Sample Control Input MUX Control Pin Config. Control VR Select VR+ 16 VRVINH VINL VINH S/H VRVR+ Comparator DAC 10-Bit SAR Conversion Logic MUX A Data Formatting VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL VINL VINH Control Logic Conversion Control DS39747E-page 174 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 20-1: R/W-0 ADON bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit ‘1’ = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 — U-0 — R/W-0 ASAM R/W-0, HCS SAMP U-0 — AD1CON1: A/D CONTROL REGISTER 1 R/W-0 ADSIDL U-0 — U-0 — U-0 — R/W-0 FORM1 R/W-0 FORM0 bit 8 R/C-0, HCS DONE bit 0 ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 10x = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as ‘0’ ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done bit 14 bit 13 bit 12-10 bit 9-8 bit 7-5 bit 4-3 bit 2 bit 1 bit 0 © 2009 Microchip Technology Inc. DS39747E-page 175 PIC24FJ128GA010 FAMILY REGISTER 20-2: R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG0 U-0 r U-0 — R/W-0 CSCNA U-0 — U-0 — bit 8 R/W-0 ALTS bit 0 R/W-0 VCFG1 VCFG2:VCFG0: Voltage Reference Configuration bits: VCFG2:VCFG0 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 Reserved Unimplemented: Read as ‘0’ CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F Unimplemented: Read as ‘0’ SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFx and ADC1BUFx) 0 = Buffer configured as one 16-word buffer (ADC1BUFx) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always use MUX A input multiplexer settings bit 9-8 bit 7 bit 6 bit 5-2 bit 1 bit 0 DS39747E-page 176 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 20-3: R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 U-0 — AD1CON3: A/D CONTROL REGISTER 3 U-0 — R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Unimplemented: Read as ‘0’ SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • TCY ······ 00000001 = 2 * TCY 00000000 = TCY bit 14-13 bit 12-8 bit 7-0 © 2009 Microchip Technology Inc. DS39747E-page 177 PIC24FJ128GA010 FAMILY REGISTER 20-4: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 U-0 — AD1CHS: A/D INPUT SELECT REGISTER U-0 — U-0 — R/W-0 CH0SB3 R/W-0 CH0SB2 R/W-0 CH0SB1 R/W-0 CH0SB0 bit 8 R/W-0 CH0SA0 bit 0 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 ····· 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits 1111 = Channel 0 positive input is AN15 1110 = Channel 0 positive input is AN14 ····· 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 DS39747E-page 178 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 20-5: R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0 R/W-0 PCFG14 PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage REGISTER 20-6: R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 AD1CSSL: A/D INPUT SCAN SELECT REGISTER R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8 R/W-0 CSSL14 R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 R/W-0 CSSL0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan © 2009 Microchip Technology Inc. DS39747E-page 179 PIC24FJ128GA010 FAMILY EQUATION 20-1: A/D CONVERSION CLOCK PERIOD(1) TAD = TCY (ADCS + 1) TAD –1 ADCS = TCY Note 1: Based on TCY = TOSC * 2; Doze mode and PLL are disabled. FIGURE 20-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD ANx VT = 0.6V RIC ≤ 250Ω Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS ≤ 5 kΩ (Typical) Rs VA CPIN 6-11 pF (Typical) VT = 0.6V ILEAKAGE ±500 nA Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. DS39747E-page 180 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY FIGURE 20-3: Output Code (Binary (Decimal)) A/D TRANSFER FUNCTION 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ – VR-) 512*(VR+ – VR-) (VINH – VINL) VR+ – VRVR+ 1024 0 VR- 1024 Voltage Level VR- + VR- + 1024 © 2009 Microchip Technology Inc. DS39747E-page 181 VR- + PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 182 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 21.0 Note: COMPARATOR MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 19. “Comparator Module” (DS39710) in the “PIC24F Family Reference Manual” for more information. The analog comparator module contains two comparators that can be configured in a variety of ways. The inputs can be selected from the analog inputs multiplexed with I/O pins, as well as the on-chip voltage reference. Block diagrams of the various comparator configurations are shown in Figure 21-1. FIGURE 21-1: COMPARATOR I/O OPERATING MODES C1NEG CMCON C1INV C1OUT C1POS C1EN C1IN+ C1IN- VINC1 VIN+ C1OUTEN C1IN+ CVREF C2NEG C2IN+ C2INC2POS C2IN+ CVREF VIN+ C2EN CMCON C2INV C2OUT VINC2 C2OUTEN © 2009 Microchip Technology Inc. DS39747E-page 183 PIC24FJ128GA010 FAMILY REGISTER 21-1: R/W-0 CMIDL bit 15 R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 C2NEG R/W-0 C2POS R/W-0 C1NEG U-0 — CMCON: COMPARATOR CONTROL REGISTER R/C-0 C2EVT R/C-0 C1EVT R/W-0 C2EN R/W-0 C1EN R/W-0 C2OUTEN R/W-0 C1OUTEN bit 8 R/W-0 C1POS bit 0 CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts. Module is still enabled. 0 = Continue normal module operation in Idle mode Unimplemented: Read as ‘0’ C2EVT: Comparator 2 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states C1EVT: Comparator 1 Event bit 1 = Comparator output changed states 0 = Comparator output did not change states C2EN: Comparator 2 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled C1EN: Comparator 1 Enable bit 1 = Comparator is enabled 0 = Comparator is disabled C2OUTEN: Comparator 2 Output Enable bit 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C1OUTEN: Comparator 1 Output Enable bit 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN- bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 DS39747E-page 184 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 21-1: bit 5 CMCON: COMPARATOR CONTROL REGISTER (CONTINUED) C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes. C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes. bit 4 bit 3 bit 2 bit 1 bit 0 © 2009 Microchip Technology Inc. DS39747E-page 185 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 186 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 22.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes features of PIC24F group of devices and is not intended to be a comprehensive reference source. Refer to Section 20. “Comparator Voltage Reference Module” (DS39709) in the “PIC24F Family Reference Manual” for more information. voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/ 32 step size 22.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 22-1). The comparator voltage reference provides two ranges of output FIGURE 22-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R R R R CVR3:CVR0 CVREN 16 Steps 16-to-1 MUX R CVREF R R R CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS © 2009 Microchip Technology Inc. DS39747E-page 187 PIC24FJ128GA010 FAMILY REGISTER 22-1: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 U-0 — CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as ‘0’ CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.72 CVRSRC, with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits When CVRR = 1: CVREF = (CVR/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC) bit 6 bit 5 bit 4 bit 3-0 DS39747E-page 188 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 23.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 32. “High-Level Device Integration” (DS39719) in the “PIC24F Family Reference Manual” for more information. TABLE 23-1: FLASH CONFIGURATION WORDS LOCATIONS Configuration Word Addresses 1 2 00ABFCh 00FFFCh 0157FCh Device PIC24FJ64GA PIC24FJ96GA PIC24FJ128GA 00ABFEh 00FFFEh 0157FEh PIC24FJ128GA010 devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The Configuration bits are reloaded from the Flash Configuration Word on any device Reset. The upper byte of both Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. 23.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A complete list is shown in Table 23-1. A detailed explanation of the various bit functions is provided in Register 23-1 through Register 23-4. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. 23.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ128GA010 FAMILY DEVICES In PIC24FJ128GA010 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the two words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 23-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among five locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device resets. © 2009 Microchip Technology Inc. DS39747E-page 189 PIC24FJ128GA010 FAMILY REGISTER 23-1: U-1 — bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 bit 14 PO = Program-Once bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/PO-1 WINDIS U-1 — R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN (1) FLASH CONFIGURATION WORD 1 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 r U-1 — R/PO-1 ICS bit 8 R/PO-1 WDTPS0 bit 0 U-1 — Unimplemented: Read as ‘1’ Reserved: Program as ‘0’. Read value unknown. JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Program as ‘1’ Unimplemented: Read as ‘1’ ICS: Emulator Pin Placement Select bit 1 = Emulator/debugger uses EMUC2/EMUD2 0 = Emulator/debugger uses EMUC1/EMUD1 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be ‘1’ Unimplemented: Read as ‘1’ FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial Programming™ (ICSP™). bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 Note 1: DS39747E-page 190 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 23-1: bit 3-0 FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 JTAGEN bit can not be modified using JTAG programming. It can only change using In-Circuit Serial Programming™ (ICSP™). Note 1: © 2009 Microchip Technology Inc. DS39747E-page 191 PIC24FJ128GA010 FAMILY REGISTER 23-2: U-1 — bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 PO = Program-Once bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/PO-1 FCKSM0 R/PO-1 OSCIOFCN U-1 — U-1 — U-1 — R/PO-1 POSCMD1 U-1 — U-1 — U-1 — U-1 — R/PO-1 FNOSC2 R/PO-1 FNOSC1 U-1 — FLASH CONFIGURATION WORD 2 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0 Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled Unimplemented: Read as ‘1’ FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSC2 Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSC2/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSC2/CLKO/RC15 functions as port I/O (RC15) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSC2/CLKO/RC15. Unimplemented: Read as ‘1’ POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected bit 14-11 bit 10-8 bit 7-6 bit 5 bit 4-2 bit 1-0 DS39747E-page 192 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY REGISTER 23-3: U — bit 23 U — bit 15 R FAMID1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-14 bit 13-6 bit 5-0 PO = Program-Once bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 U — R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 bit 8 U — DEVID: DEVICE ID REGISTER U — U — U — U — U — U — bit 16 Unimplemented: Read as ‘0’ FAMID7:FAMID0: Device Family Identifier bits 00010000 = PIC24FJ128GA010 family DEV5:DEV0: Individual Device Identifier bits 000101 = PIC24FJ64GA006 000110 = PIC24FJ96GA006 000111 = PIC24FJ128GA006 001000 = PIC24FJ64GA008 001001 = PIC24FJ96GA008 001010 = PIC24FJ128GA008 001011 = PIC24FJ64GA010 001100 = PIC24FJ96GA010 001101 = PIC24FJ128GA010 © 2009 Microchip Technology Inc. DS39747E-page 193 PIC24FJ128GA010 FAMILY REGISTER 23-4: U — bit 23 R r bit 15 R MAJRV1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-12 bit 11-9 bit 8-6 bit 5-3 bit 2-0 PO = Program-Once bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R MAJRV0 U — U — U — R DOT2 R DOT1 R DOT0 bit 0 R r R r R r U — U — U — R MAJRV2 bit 8 U — DEVREV: DEVICE REVISION REGISTER U — U — U — U — U — U — bit 16 Unimplemented: Read as ‘0’ Reserved: For factory use only Unimplemented: Read as ‘0’ MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as ‘0’ DOT2:DOT0: Minor Revision Identifier bits DS39747E-page 194 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 23.2 On-Chip Voltage Regulator FIGURE 23-1: All of the PIC24FJ128GA010 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ128GA010 incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low ESR capacitor (such as tantalum) must be connected to the VDDCORE/VCAP pin (Figure 23-1). This helps to maintain the stability of the regulator. The recommended value for the filer capacitor, CEFC, is provided in Section 26.1 “DC Characteristics”. If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 23-1 for possible configurations. CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP CEFC (10 μF typ) VSS Regulator Disabled (ENVREG tied to ground): 2.5V(1) 3.3V(1) PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP VSS 23.2.1 ON-CHIP REGULATOR AND POR Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ128GA010 VDD ENVREG VDDCORE/VCAP VSS When the voltage regulator is enabled, it takes approximately 20 μs for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up. 23.2.2 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ128GA010 devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage specifications can be found in the PIC24F Family Reference Manual Reset chapter (DS39712). Note 1: These are typical operating voltages. Refer to Section 26.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. 23.2.3 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. © 2009 Microchip Technology Inc. DS39747E-page 195 PIC24FJ128GA010 FAMILY 23.3 Note: Watchdog Timer (WDT) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 9. “Watchdog Timer (WDT)” (DS39697) in the “PIC24F Family Reference Manual” for more information. • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. For PIC24FJ128GA010 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (Flash Configuration Word 1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) 23.3.1 CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN device Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 23-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-bit/7-bit) 32 kHz 1 ms/4 ms WDT Counter WDTPS3:WDTPS0 Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS39747E-page 196 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 23.4 Note: JTAG Interface This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the “PIC24F Family Reference Manual” for more information. 23.6 Note: In-Circuit Serial Programming This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the “PIC24F Family Reference Manual” for more information. PIC24FJ128GA010 family devices implement a JTAG interface, which supports boundary scan device testing as well as in-circuit programming. Refer to the Microchip web site (www.microchip.com) for JTAG support files and additional information. 23.5 Note: Program Verification and Code Protection This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. Refer to Section 33. “Programming and Diagnostics” (DS39716) in the “PIC24F Family Reference Manual” for more information. PIC24FJ128GA010 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. 23.7 In-Circuit Debugger For all devices in the PIC24FJ128GA010 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to 0, internal write and erase operations to program memory are blocked. When MPLAB® ICD 2 is selected as a debugger, the In-Circuit Debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pins. To use the In-Circuit Debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 23.5.1 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the shadow registers which contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Configuration Word Mismatch Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. © 2009 Microchip Technology Inc. DS39747E-page 197 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 198 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 24.0 INSTRUCTION SET SUMMARY The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made doubleword instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. Table 24-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 24-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including simple rotate/ shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2009 Microchip Technology Inc. DS39747E-page 199 PIC24FJ128GA010 FAMILY TABLE 24-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address ∈ {0000h...1FFFh} 1-bit unsigned literal ∈ {0,1} 4-bit unsigned literal ∈ {0...15} 5-bit unsigned literal ∈ {0...31} 8-bit unsigned literal ∈ {0...255} 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal ∈ {0...16384} 16-bit unsigned literal ∈ {0...65535} 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal ∈ {-512...511} 16-bit signed literal ∈ {-32768...32767} 6-bit signed literal ∈ {-16...16} Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (Direct Addressing) One of 16 working registers ∈ {W0..W15} One of 16 destination working registers ∈ {W0..W15} One of 16 source working registers ∈ {W0..W15} W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39747E-page 200 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 24-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSW BTG BTSC BSET BSET BSW.C BSW.Z BTG BTG BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None 1 None (2 or 3) 1 None (2 or 3) © 2009 Microchip Technology Inc. DS39747E-page 201 PIC24FJ128GA010 FAMILY TABLE 24-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CLR CALL CALL CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CPB CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if ≠ Wn = Decimal Adjust Wn f = f –1 WREG = f –1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-Bit Integer Divide Signed 32/16-Bit Integer Divide Unsigned 16/16-Bit Integer Divide Unsigned 32/16-Bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39747E-page 202 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 24-2: Assembly Mnemonic GOTO INC GOTO GOTO INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP POP NOP NOPR POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-Bit Literal to Wn Move 8-Bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None © 2009 Microchip Technology Inc. DS39747E-page 203 PIC24FJ128GA010 FAMILY TABLE 24-2: Assembly Mnemonic PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP TBLRDH SWAP.b SWAP TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog to Wd # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None DS39747E-page 204 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 24-2: Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N © 2009 Microchip Technology Inc. DS39747E-page 205 PIC24FJ128GA010 FAMILY NOTES: DS39747E-page 206 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 25.0 DEVELOPMENT SUPPORT 25.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2009 Microchip Technology Inc. DS39747E-page 207 PIC24FJ128GA010 FAMILY 25.2 MPLAB C Compilers for Various Device Families 25.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 25.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 25.6 MPLAB Assembler, Linker and Librarian for Various Device Families 25.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS39747E-page 208 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 25.7 MPLAB SIM Software Simulator 25.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 25.8 MPLAB REAL ICE In-Circuit Emulator System 25.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2009 Microchip Technology Inc. DS39747E-page 209 PIC24FJ128GA010 FAMILY 25.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 25.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 25.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39747E-page 210 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 26.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ128GA010 electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ128GA010 are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................. .-40°C to +85°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital-only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +2.8V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1) ................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-2). FIGURE 26-1: FREQUENCY/VOLTAGE GRAPH 3.00V 2.75V 2.50V Voltage VDDCORE(1) 2.25V 2.00V 2.75V 16 MHz Frequency Note 1: 32 MHz When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V. †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2009 Microchip Technology Inc. DS39747E-page 211 PIC24FJ128GA010 FAMILY 26.1 DC Characteristics OPERATING MIPS vs. VOLTAGE Temp Range (in °C) -40°C to +85°C Max MIPS PIC24FJ128GA010 Family 16 TABLE 26-1: VDD Range (in Volts) 2.0-3.6V TABLE 26-2: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA Min -40 -40 Typ — — Max +125 +85 Unit °C °C PIC24FJ128GA010 Family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – Σ IOH) I/O Pin Power Dissipation: PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W PD PINT + PI/O W TABLE 26-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ 50 69.4 76.6 Max — — — Unit °C/W °C/W °C/W Notes (Note 1) (Note 1) (Note 1) Package Thermal Resistance, 14x14x1 mm TQFP Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Note 1: θJA θJA θJA Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations. TABLE 26-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal Characteristic 2.7 VDDCORE 2.0 1.5 — — — — — VSS 3.6 3.6 2.75 — — V V V V V Regulator enabled Regulator disabled Regulator disabled DC17 SVDD 0.05 — — V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms Note 1: 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. DS39747E-page 212 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 26-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC20d DC20e DC20f DC23 DC23a DC23b DC23d DC23e DC23f DC24 DC24a DC24b DC24d DC24e DC24f DC31 DC31a DC31b DC31d DC31e DC31f Note 1: 2: Typical(1) Operating Current (IDD)(2) 1.6 1.6 1.6 1.6 1.6 1.6 6.0 6.0 6.0 6.0 6.0 6.0 20 20 20 20 20 20 70 100 200 70 100 200 4.0 4.0 4.0 4.0 4.0 4.0 12 12 12 12 12 12 32 32 32 32 32 32 150 200 400 150 200 400 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.6V(4) 2.5V(3) LPRC (31 kHz) 3.6V(4) 2.5V(3) 16 MIPS 3.6V(4) 2.5V(3) 4 MIPS 3.6V(4) 2.5V(3) 1 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and PMD bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). © 2009 Microchip Technology Inc. DS39747E-page 213 PIC24FJ128GA010 FAMILY TABLE 26-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40d DC40e DC40f DC43 DC43a DC43b DC43d DC43e DC43f DC47 DC47a DC47b DC47c DC47d DC47e DC51 DC51a DC51b DC51d DC51e DC51f Note 1: 2: 3: 4: Typical(1) Idle Current (IIDLE): Core Off, Clock On Base Current(2) 0.7 0.7 0.7 0.7 0.7 0.7 2.1 2.1 2.1 2.1 2.1 2.1 6.8 6.8 6.8 6.8 6.8 6.8 150 150 150 150 150 150 2 2 2 2 2 2 4 4 4 4 4 4 8 8 8 8 8 8 500 500 500 500 500 500 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.6V(4) 2.5V(3) LPRC (31 kHz) 3.6V(4) 2.5V(3) 16 MIPS 3.6V(4) 2.5V(3) 4 MIPS 3.6V(4) 2.5V(3) 1 MIPS Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with core off, clock on, PMD bits set and all modules turned off. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). DS39747E-page 214 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 26-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60f DC60g DC60h DC61 DC61a DC61b DC61f DC61g DC61h DC62 DC62a DC62b DC62f DC62g DC62h Note 1: 2: 3: 4: 5: Typical(1) Power-Down Current (IPD)(2) 3 3 100 20 27 120 10 10 10 10 10 10 8 8 8 8 8 8 25 45 600 40 60 600 25 25 25 25 25 25 15 15 15 15 15 15 μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.6V(4) 2.0V(3) RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC(5) 3.6V(4) 2.0V(3) Watchdog Timer Current: ΔIWDT(5) 3.6V(4) 2.0V(3) Base Power-Down Current(5) Module Differential Current Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. Unused PMD bits are set. VREGS bit is clear. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. © 2009 Microchip Technology Inc. DS39747E-page 215 PIC24FJ128GA010 FAMILY TABLE 26-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O pins with ST buffer: I/O pins with TTL buffer: MCLR OSC1 (XT mode) OSC1 (HS mode) I/O pins with I2C buffer: I/O pins with SMBus buffer: Input High Voltage(4) I/O pins with ST buffer: With Analog Functions Digital-Only I/O pins with TTL buffer: With Analog Functions Digital-Only MCLR OSC1 (XT mode) OSC1 (HS mode) I/O pins with 12C buffer: With Analog Functions Digital-Only I/O pins with SMBUS buffer: VSS VSS VSS VSS VSS VSS VSS — — — — — — — 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled 0.8 VDD 0.8 VDD 0.25 VDD+ 0.8 0.25 VDD+ 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 50 — — — — — — — — — — — — — VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 V V V V V V V V V V V μA μA μA μA μA DI21 DI25 DI26 DI27 DI28 DI29 With Analog Functions Digital-Only ICNPU CNxx Pull-up Current IIL Input Leakage Current(2,3) I/O Ports Analog Input pins MCLR OSC1 2.5V ≤ VPIN ≤ VDD VDD = 3.3V, VPIN = VSS VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD, XT and HS modes DI30 DI50 DI51 DI55 DI56 Note 1: 2: 250 — — — — 400 +1 +1 +1 +1 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pins buffer types. DS39747E-page 216 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 26-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 Sym VOL Characteristic Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSC2/CLKO 2.4 1.4 — — — — — — — — — — — — V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -3.0 mA, VDD = 2.0V IOH = -6.0 mA, VDD = 3.6V IOH = -3.0 mA, VDD = 2.0V — — — — — — — — 0.4 0.4 0.4 0.4 V V V V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-10: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param No. D130 D131 D132B D133A D134 D135 Note 1: Sym Characteristic Program Flash Memory EP VPR Cell Endurance VDD for Read 100 VMIN 2.25 — 20 — 1K — — 3 — 10 — 3.6 3.6 — — — E/W V V ms Year mA Provided no other specifications are violated -40°C to +85°C VMIN = Minimum operating voltage Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions VPEW VDD for Self-Timed Erase/ Write TIW Self-Timed Write Cycle Time TRETD Characteristic Retention IDDP Supply Current during Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2009 Microchip Technology Inc. DS39747E-page 217 PIC24FJ128GA010 FAMILY TABLE 26-11: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. CEFC TVREG TPWRT Characteristics Min — 4.7 — — Typ 2.5 10 10 64 Max — — — — Units V μF μs ms Series resistance < 3 Ohm recommended; < 5 Ohm required. ENVREG = VDD ENVREG = VSS Comments VRGOUT Regulator Output Voltage External Filter Capacitor Value DS39747E-page 218 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY 26.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ128GA010 AC characteristics and timing parameters. TABLE 26-12: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 26.1 “DC Characteristics”. FIGURE 26-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSC2 Load Condition 1 – for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464Ω CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 26-13: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSC2/CLKO pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1. EC mode In I2C™ mode DO56 DO58 Note 1: CIO CB All I/O pins and OSC2 SCLx, SDAx — — — — 50 400 pF pF Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2009 Microchip Technology Inc. DS39747E-page 219 PIC24FJ128GA010 FAMILY FIGURE 26-3: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSC1 OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 TABLE 26-14: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min DC 3 3.5 3.5 10 31 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — 6 6 Max 32 8 10 8 32 33 — DC — 20 10 10 Units MHz MHz MHz MHz MHz kHz — ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS SOSC See parameter OS10 for FOSC value Conditions FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency OS20 OS25 OS30 OS31 OS40 OS41 TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2) TosL, External Clock in (OSC1) TosH High or Low Time TosR, External Clock in (OSC1) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3) Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39747E-page 220 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 26-15: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range(2) On-Chip VCO System Frequency Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min 3 8 — -2 Typ(2) — — — 1 Max 8 32 2 +2 Units MHz MHz ms % Conditions ECPLL, HSPLL, XTPLL modes TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter) These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 26-16: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 FRC Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions Internal FRC Accuracy @ 8 MHz(1) -2 -5 — — +2 +5 % % +25°C -40°C ≤ TA ≤ +85°C Vdd = 3.0 - 3.6V Vdd = 3.0 - 3.6V Legend: TBD = To Be Determined Note 1: Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. TABLE 26-17: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -15 — +15 % -40°C ≤ TA ≤ +85°C VDD = 3.0 - 3.6V Change of LPRC frequency as VDD changes. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions © 2009 Microchip Technology Inc. DS39747E-page 221 PIC24FJ128GA010 FAMILY FIGURE 26-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 26-2 for load conditions. New Value TABLE 26-18: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39747E-page 222 © 2009 Microchip Technology Inc. PIC24FJ128GA010 FAMILY TABLE 26-19: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Param Symbol No. AD01 AVDD Characteristic Min. Typ Max. Units Conditions Device Supply Module VDD Supply Greater of VDD – 0.3 or 2.0 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 V AD02 AD05 AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage — — — — V V V V Reference Inputs Analog Input AD10 AD11 AD12 VINH-VINL Full-Scale Input Span VIN — Absolute Input Voltage Leakage Current VREFL AVSS – 0.3 — ±0.001 VREFH AVDD + 0.3 ±0.610 V V μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 5V, Source Impedance = 2.5 kΩ VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 kΩ See Note 2 AD13 — Leakage Current — ±0.001 ±0.610 μA AD14 AD17 VINL RIN Absolute VINL Input Voltage Recommended Impedance of Analog Voltage Resolution Integral Nonlinearity(2) Differential Nonlinearity(2) Gain Error(2) Offset Error(2) Monotonicity(1) AVSS – 0.3 — — AVDD/2 2.5K V ADC Accuracy AD20a Nr AD21a INL AD22a DNL AD23a GERR AD24a EOFF AD25a — 10 data bits — — — — — +1 +0.5 +1 +1 —