PIC24FJ64GA004 Family Data Sheet
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
© 2008 Microchip Technology Inc.
Preliminary
DS39881C
Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
• •
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS39881C-page ii
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
28/44-Pin General Purpose, 16-Bit Flash Microcontrollers
High-Performance CPU:
• Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 4x PLL Option and Multiple Divide Options • 17-Bit by 17-Bit Single-Cycle Hardware Multiplier • 32-Bit by 16-Bit Hardware Divider • 16-Bit x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory
Analog Features:
• 10-Bit, up to 13-Channel Analog-to-Digital Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Dual Analog Comparators with Programmable Input/Output Configuration
Peripheral Features:
• Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Up to 26 available pins (44-pin devices) - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • 8-Bit Parallel Master/Slave Port (PMP/PSP): - Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices - Programmable polarity on control lines • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • Programmable Cyclic Redundancy Check (CRC) • Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer • Two I2C™ modules support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing • Two UART modules: - Supports RS-485, RS-232, and LIN 1.2 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs • Five 16-Bit Compare/PWM Outputs • Configurable Open-Drain Outputs on Digital I/O Pins • Up to 4 External Interrupt Sources
Special Microcontroller Features:
• • • • Operating Voltage Range of 2.0V to 3.6V 5.5V Tolerant Input (digital pins only) High-Current Sink/Source (18 mA/18 mA) on All I/O Pins Flash Program Memory: - 10,000 erase/write - 20-year data retention minimum Power Management modes: - Sleep, Idle, Doze and Alternate Clock modes - Operating current 650 μA/MIPS typical at 2.0V - Sleep current 150 nA typical at 2.0V Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator On-Chip, 2.5V Regulator with Tracking mode Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip, Low-Power RC Oscillator for Reliable Operation In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support
•
•
• • • • •
Comparators
Remappable Peripherals 10-Bit A/D (ch) Program Memory (bytes) Remappable Pins SRAM (bytes) Compare/ PWM Output UART w/ IrDA® Capture Input Timers 16-Bit PIC24FJ Device I2C™ Pins
PMP/PSP Y Y Y Y Y Y Y Y
16GA002 32GA002 48GA002 64GA002 16GA004 32GA004 48GA004 64GA004
28 28 28 28 44 44 44 44
16K 32K 48K 64K 16K 32K 48K 64K
4K 8K 8K 8K 4K 8K 8K 8K
16 16 16 16 26 26 26 26
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
5 5 5 5 5 5 5 5
2 2 2 2 2 2 2 2
SPI
2 2 2 2 2 2 2 2
2 2 2 2 2 2 2 2
10 10 10 10 13 13 13 13
2 2 2 2 2 2 2 2
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 1
JTAG Y Y Y Y Y Y Y Y
PIC24FJ64GA004 FAMILY
Pin Diagrams
28-Pin SPDIP, SSOP, SOIC
MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 VDD PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS AN9/RP15/CN11/PMCS1/RB15 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN11/RP13/CN13/PMRD/RB13 AN12/RP12/CN14/PMD0/RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9 TCK/RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6
28-Pin QFN(1)
PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1 AN4/C1IN-/RP2/SDA2/CN6/RB2 AN5/C1IN+/RP3/SCL2/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/PMA0/RA3
28 27 26 25 24 23 22 1 21 2 20 3 19 4 PIC24FJXXGA002 18 5 17 6 16 7 15 8 9 10 11 12 13 14 SOSCI/RP4/PMBE/CN1/RB4 SOSCO/T1CK/CN0/PMA1/RA4 VDD PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6 RP7/INT0/CN23/PMD5/RB7 TCK/RP8/SCL1/CN22/PMD4/RB8
AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR VDD VSS AN9/RP15/CN11/PMCS1/RB15 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14
PIC24FJXXGA002
AN11/RP13/CN13/PMRD/RB13 AN12/RP12/CN14/PMD0/RB12 PGC2/EMUC2/TMS/RP11/CN15/PMD1/RB11 PGD2/EMUD2/TDI/RP10/CN16/PMD2/RB10 VCAP/VDDCORE DISVREG TDO/RP9/SDA1/CN21/PMD3/RB9
Legend: Note 1:
RPn represents remappable peripheral pins. Back pad on QFN devices should be connected to Vss.
DS39881C-page 2
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)
RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 VDD VSS RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/T1CK/CN0/RA4 44 43 42 41 40 39 38 37 36 35 34 RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11
44-Pin QFN(1)
PIC24FJXXGA004
Legend: Note 1:
RPn represents remappable peripheral pins. Back pad on QFN devices should be connected to Vss.
© 2008 Microchip Technology Inc.
TMS/PMA10/RA10 TCK/PMA7/RA7 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN9/RP15/CN11/PMCS1/RB15 AVSS AVDD MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
12 13 14 15 16 17 18 19 20 21 22
33 32 31 30 29 28 27 26 25 24 23
SOSCI/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/CN30/RA2 VSS VDD AN8/RP18/CN10/PMA2/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1IN+/RP3/SCL2/CN7/RB3 AN4/C1IN-/RP2/SDA2/CN6/RB2
Preliminary
DS39881C-page 3
PIC24FJ64GA004 FAMILY
Pin Diagrams (Continued)
RP8/SCL1/CN22/PMD4/RB8 RP7/INT0/CN23/PMD5/RB7 PGC3/EMUC3/RP6/ASCL1/CN24/PMD6/RB6 PGD3/EMUD3/RP5/ASDA1/CN27/PMD7/RB5 VDD VSS RP21/CN26/PMA3/RC5 RP20/CN25/PMA4/RC4 RP19/CN28/PMBE/RC3 TDI/PMA9/RA9 SOSCO/T1CK/CN0/RA4 44 43 42 41 40 39 38 37 36 35 34 RP9/SDA1/CN21/PMD3/RB9 RP22/CN18/PMA1/RC6 RP23/CN17/PMA0/RC7 RP24/CN20/PMA5/RC8 RP25/CN19/PMA6/RC9 DISVREG VCAP/VDDCORE PGD2/EMUD2/RP10/CN16/PMD2/RB10 PGC2/EMUC2/RP11/CN15/PMD1/RB11 AN12/RP12/CN14/PMD0/RB12 AN11/RP13/CN13/PMRD/RB13 33 32 31 30 29 28 27 26 25 24 23
44-Pin TQFP
Legend:
RPn represents remappable peripheral pins.
TMS/PMA10/RA10 TCK/PMA7/RA7 AN10/CVREF/RTCC/RP14/CN12/PMWR/RB14 AN9/RP15/CN11/PMCS1/RB15 AVSS AVDD MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/C2IN-/RP0/CN4/RB0 PGC1/EMUC1/AN3/C2IN+/RP1/CN5/RB1
12 13 14 15 16 17 18 19 20 21 22
1 2 3 4 5 6 7 8 9 10 11
PIC24FJXXGA004
SOSCI/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/CN30/RA2 VSS VDD AN8/RP18/CN10/PMA2/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1IN+/RP3/SCL2/CN7/RB3 AN4/C1IN-/RP2/SDA2/CN6/RB2
DS39881C-page 4
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU ........................................................................................................................................................................................... 17 3.0 Memory Organization ................................................................................................................................................................. 23 4.0 Flash Program Memory.............................................................................................................................................................. 41 5.0 Resets ........................................................................................................................................................................................ 47 6.0 Interrupt Controller ..................................................................................................................................................................... 53 7.0 Oscillator Configuration .............................................................................................................................................................. 87 8.0 Power-Saving Features.............................................................................................................................................................. 95 9.0 I/O Ports ..................................................................................................................................................................................... 97 10.0 Timer1 ..................................................................................................................................................................................... 117 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 119 12.0 Input Capture............................................................................................................................................................................ 125 13.0 Output Compare....................................................................................................................................................................... 127 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133 15.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 143 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 151 17.0 Parallel Master Port (PMP)....................................................................................................................................................... 159 18.0 Real-Time Clock And Calendar (RTCC) ................................................................................................................................. 169 19.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 179 20.0 10-Bit High-speed A/D Converter............................................................................................................................................. 183 21.0 Comparator Module.................................................................................................................................................................. 193 22.0 Comparator Voltage Reference................................................................................................................................................ 197 23.0 Special Features ...................................................................................................................................................................... 199 24.0 Development Support............................................................................................................................................................... 209 25.0 Instruction Set Summary .......................................................................................................................................................... 213 26.0 Electrical Characteristics .......................................................................................................................................................... 221 27.0 Packaging Information.............................................................................................................................................................. 239 Appendix A: Revision History............................................................................................................................................................. 251 Appendix B: Additional Guidance for PIC24FJ64GA004 Family Applications ................................................................................... 252 Index ................................................................................................................................................................................................. 253 The Microchip Web Site ..................................................................................................................................................................... 257 Customer Change Notification Service .............................................................................................................................................. 257 Customer Support .............................................................................................................................................................................. 257 Reader Response .............................................................................................................................................................................. 258 Product Identification System ............................................................................................................................................................ 259
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 5
PIC24FJ64GA004 FAMILY
TO OUR VALUED CUSTOMERS
It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback.
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Errata
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DS39881C-page 6
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
1.0 DEVICE OVERVIEW
1.1.2 POWER-SAVING TECHNOLOGY
This document contains device-specific information for the following devices: • • • • • • • • PIC24FJ16GA002 PIC24FJ32GA002 PIC24FJ48GA002 PIC24FJ64GA002 PIC24FJ16GA004 PIC24FJ32GA004 PIC24FJ48GA004 PIC24FJ64GA004 All of the devices in the PIC24FJ64GA004 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software.
This family introduces a new line of Microchip devices: a 16-bit microcontroller family with a broad peripheral feature set and enhanced computational performance. The PIC24FJ64GA004 family offers a new migration option for those high-performance applications which may be outgrowing their 8-bit platforms, but don’t require the numerical processing power of a digital signal processor.
1.1
1.1.1
Core Features
16-BIT ARCHITECTURE
1.1.3
OSCILLATOR OPTIONS AND FEATURES
Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’ • Operational performance up to 16 MIPS
All of the devices in the PIC24FJ64GA004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the External Oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 7
PIC24FJ64GA004 FAMILY
1.1.4 EASY MIGRATION
1.3
Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating to the next larger device. This is true when moving between devices with the same pin count, or even jumping from 28-pin to 44-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.
Details on Individual Family Members
Devices in the PIC24FJ64GA004 family are available in 28-pin and 44-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in two ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GA devices, 48 Kbytes for PIC24FJ48GA devices, 32 Kbytes for PIC24FJ32GA devices and 16 Kbytes for PIC24FJ16GA devices). Internal SRAM memory (4k for PIC24FJ16GA devices, 8k for all other devices in the family). Available I/O pins and ports (21 pins on 2 ports for 28-pin devices and 35 pins on 3 ports for 44-pin devices).
2. 3.
1.2
Other Special Features
• Communications: The PIC24FJ64GA004 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, two independent UARTs with built-in IrDA encoder/decoders and two SPI modules. • Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. • 10-Bit A/D Converter: This module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds.
All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ64GA004 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first.
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© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA004 FAMILY
16GA002 32GA002 48GA002 64GA002 16GA004 32GA004 48GA004 Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators Remappable Pins Resets (and delays) 16 10 2 26 POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 28-Pin SPDIP/SSOP/SOIC/QFN Peripherals are accessible through remappable pins. 44-Pin QFN/TQFP 2(1) 2(1) 2 Yes Yes 13 21 5(1) 2 5(1) 5(1) 30 Ports A, B 21 16K 5,504 4096 32K 11,008 48K 16,512 8192 64GA004 64K 22,016
DC – 32 MHz 64K 22,016 16K 5,504 4096 43 (39/4) Ports A, B, C 35 32K 11,008 48K 16,512 8192
Instruction Set Packages Note 1:
© 2008 Microchip Technology Inc.
Preliminary
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PIC24FJ64GA004 FAMILY
FIGURE 1-1: PIC24FJ64GA004 FAMILY GENERAL BLOCK DIAGRAM
Data Bus
16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU PORTA(1) RA0:RA9
Interrupt Controller
23 Address Latch Program Memory Data Latch
PORTB RB0:RB15
Address Bus
24 Inst Latch Inst Register Instruction Decode & Control Control Signals Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference DISVREG Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD(2) Literal Data
EA MUX 16 16
16 PORTC(1) RC0:RC9
RP(1) Divide Support 17x17 Multiplier RP0:RP25 16 x 16 W Reg Array
OSCO/CLKO OSCI/CLKI
16-Bit ALU 16
VDDCORE/VCAP
VDD, VSS
MCLR
Timer1
Timer2/3(3)
Timer4/5(3)
RTCC
10-Bit ADC
Comparators(3)
PMP/PSP PWM/ OC1-5(3)
IC1-5(3)
CN1-22(1)
SPI1/2(3)
I2C1/2
UART1/2(3)
Note
1: 2: 3:
Not all pins or features are implemented on all device pinout configurations. See Table 1-2 for I/O port pin descriptions. BOR and LVD functionality is provided when the on-board voltage regulator is enabled. Peripheral I/Os are accessible through remappable pins.
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© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 2 3 4 5 6 7 — — — 26 25 24 23 15 14 — — 6 7 4 5 9 10
28-Pin QFN 27 28 1 2 3 4 — — — 23 22 21 20 12 11 — — 3 4 1 2 6 7
44-Pin QFN/TQFP 19 20 21 22 23 24 25 26 27 15 14 11 10 42 41 17 16 23 24 21 22 30 31
AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 ASCL1 ASDA1 AVDD AVSS C1INC1IN+ C2INC2IN+ CLKI CLKO Legend: Note 1:
I I I I I I I I I I I I I I/O I/O P P I I I I I O
ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA I2C IC — — ANA ANA ANA ANA ANA —
2
A/D Analog Inputs.
Alternate I2C1 Synchronous Serial Clock Input/Output.(1) Alternate I2C2 Synchronous Serial Clock Input/Output. (1) Positive Supply for Analog Modules. Ground Reference for Analog Modules. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 2 Negative Input. Comparator 2 Positive Input. Main Clock Input Connection. System Clock Output.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 11
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TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 12 11 2 3 4 5 6 7 — — — 26 25 24 23 22 21 — — — — 18 17 16 15 — — 14 — 10 9 25 19 5 4 22 21 15 14 16 1
28-Pin QFN 9 8 27 28 1 2 3 4 — — — 23 22 21 20 19 18 — — — — 15 14 13 12 — — 11 — 7 6 22 16 2 1 19 18 12 11 13 26
44-Pin QFN/TQFP 34 33 19 20 21 22 23 24 25 26 27 15 14 11 10 9 8 3 2 5 4 1 44 43 42 37 38 41 36 31 30 14 6 21 22 9 8 42 41 43 18
CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CVREF DISVREG EMUC1 EMUD1 EMUC2 EMUD2 EMUC3 EMUD3 INT0 MCLR Legend: Note 1:
I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O I I/O I/O I/O I/O I/O I/O I I
ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ST ST ST ST ST ST ST ST ST
Interrupt-on-Change Inputs.
Comparator Voltage Reference Output. Voltage Regulator Disable. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. In-Circuit Emulator Clock Input/Output. In-Circuit Emulator Data Input/Output. External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
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TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 9 10 5 4 22 21 14 15 10 12 — — — — — — — — — — — — 11 26 23 22 21 18 17 16 15 14 24 25
28-Pin QFN 6 7 2 1 19 18 12 11 7 9 — — — — — — — — — — — — 8 23 20 19 18 15 14 13 12 11 21 22
44-Pin QFN/TQFP 30 31 22 21 9 8 42 41 3 2 27 38 37 4 5 13 32 35 12 — — — 36 15 10 9 8 1 44 43 42 41 11 14
OSCI OSCO PGC1 PGD1 PGC2 PGD2 PGC3 PGD3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMBE PMCS1 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend: Note 1:
I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O
ANA ANA ST ST ST ST ST ST ST/TTL ST/TTL — — — — — — — — — — — — — — ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL — —
Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger and ICSP™ Programming Clock In-Circuit Debugger and ICSP Programming Data. In-Circuit Debugger and ICSP Programming Clock. In-Circuit Debugger and ICSP Programming Data. In-Circuit Debugger and ICSP Programming Clock. In-Circuit Debugger and ICSP Programming Data. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes).
Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe/Address Bit 14. Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes).
Parallel Master Port Read Strobe. Parallel Master Port Write Strobe.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 13
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TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 2 3 9 10 12 — — — — 4 5 6 7 11 14 15 16 17 18 21 22 23 24 25 26 — — — — — — — — — —
28-Pin QFN 27 28 6 7 9 — — — — 1 2 3 4 8 11 12 13 14 15 18 19 20 21 22 23 — — — — — — — — — —
44-Pin QFN/TQFP 19 20 30 31 34 13 32 35 12 21 22 23 24 33 41 42 43 44 1 8 9 10 11 14 15 25 26 27 36 37 38 2 3 4 5
RA0 RA1 RA2 RA3 RA4 RA7 RA8 RA9 RA10 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 Legend: Note 1:
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST
PORTA Digital I/O.
PORTB Digital I/O.
PORTC Digital I/O.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
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TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 4 5 6 7 11 14 15 16 17 18 21 22 23 24 25 26 — — — — — — — — — — 25 17 7 18 6 11 12
28-Pin QFN 1 2 3 4 8 11 12 13 14 15 18 19 20 21 22 23 — — — — — — — — — — 22 14 4 15 3 8 9
44-Pin QFN/TQFP 21 22 23 24 33 41 42 43 44 1 8 9 10 11 14 15 25 26 27 36 37 38 2 3 4 5 14 44 24 1 23 33 34
RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RTCC SCL1 SCL2 SDA1 SDA2 SOSCI SOSCO Legend: Note 1:
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I O
ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — I2C I2C I2C I2C ANA ANA
Remappable Peripheral.
Real-Time Clock Alarm Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 15
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TABLE 1-2:
Function
PIC24FJ64GA004 FAMILY PINOUT DESCRIPTIONS (CONTINUED)
Pin Number I/O Input Buffer Description
28-Pin SPDIP/ SSOP/SOIC 12 17 21 18 22 13, 28 20 20 3 2 8, 27
28-Pin QFN 9 14 18 15 19 10, 25 17 17 28 27 5, 24
44-Pin QFN/TQFP 34 13 35 32 12 28, 40 7 7 20 19 29, 39
T1CK TCK TDI TDO TMS VDD VDDCAP VDDCORE VREFVREF+ VSS Legend: Note 1:
I I I O I P P P I I P
ST ST ST — ST — — — ANA ANA —
Timer1 Clock. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. Positive Supply for Peripheral Digital Logic and I/O Pins. External Filter Capacitor Connection (regulator enabled). Positive Supply for Microcontroller Core Logic (regulator disabled). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins.
TTL = TTL input buffer ST = Schmitt Trigger input buffer ANA = Analog level input/output I2C™ = I2C/SMBus input buffer Alternative multiplexing when the I2C1SEL Configuration bit is cleared.
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Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
2.0
Note:
CPU
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 2. CPU” (DS39703).
For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1.
The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements.
2.1
Programmer’s Model
The programmer’s model for the PIC24F is shown in Figure 2-2. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer’s model are memory mapped.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 17
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FIGURE 2-1:
PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16
PIC24F CPU CORE BLOCK DIAGRAM
23
Address Latch
Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX
Instruction Decode & Control
Instruction Reg
Control Signals to Various Blocks
Hardware Multiplier Divide Support
16 x 16 W Register Array 16
16-Bit ALU 16
To Peripheral Modules
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Preliminary
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TABLE 2-1:
W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON
CPU CORE REGISTERS
Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register
Register(s) Name
FIGURE 2-2:
PROGRAMMER’S MODEL
15 0 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers
Divider Working Registers
Multiplier Registers
SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL
0 0 0 0
0
0
0 ALU STATUS Register (SR)
— — — — — — — DC
IPL RA N OV Z C 210
15
0 CPU Control Register (CORCON)
— — — — — — — — — — — — IPL3 PSV — —
Registers or bits shadowed for PUSH.S and POP.S instructions.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 19
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2.2 CPU Control Registers
SR: ALU STATUS REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(1) IPL1
(2)
REGISTER 2-1:
U-0 — bit 15 R/W-0(1) IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8
(2)
R/W-0(1) IPL0
(2)
R-0 RA
R/W-0 N
R/W-0 OV
R/W-0 Z
R/W-0 C bit 0
W = Writable bit ‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown
Unimplemented: Read as ‘0’ DC: ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th or 8th low-order bit of the result has occurred IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1.
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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REGISTER 2-2:
U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/C-0 IPL3
(1)
CORCON: CPU CONTROL REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PSV U-0 — U-0 — bit 0
Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ User interrupts are disabled when IPL3 = 1.
bit 2
bit 1-0 Note 1:
2.3
Arithmetic Logic Unit (ALU)
The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location.
The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division.
2.3.1
MULTIPLIER
The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 21
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2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT
The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2.
The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
TABLE 2-2:
Instruction ASR SL LSR
INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION
Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits.
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Preliminary
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3.0 MEMORY ORGANIZATION
As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ64GA004 family of devices are shown in Figure 3-1.
3.1
Program Address Space
The program address memory space of the PIC24FJ64GA004 family devices is 4M instructions. The space is addressable by a 24-bit value derived
FIGURE 3-1:
PROGRAM SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ32GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ16GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (5.5K instructions) Flash Config Words User Memory Space
PIC24FJ48GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
PIC24FJ64GA
GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h
User Flash Program Memory (11K instructions)
User Flash Program Memory (16K instructions) User Flash Program Memory (22K instructions)
002BFEh 002C00h
Flash Config Words Flash Config Words
0057FEh 005800h 0083FEh 008400h Flash Config Words Unimplemented Read ‘0’ Unimplemented Read ‘0’ 7FFFFFh 800000h 00ABFEh 00AC00h
Unimplemented Read ‘0’
Unimplemented Read ‘0’
Reserved Configuration Memory Space
Reserved
Reserved
Reserved
Device Config Registers
Device Config Registers
Device Config Registers
Device Config Registers
F7FFFEh F80000h F8000Eh F80010h
Reserved
Reserved
Reserved
Reserved
DEVID (2)
DEVID (2)
DEVID (2)
DEVID (2)
FEFFFEh FF0000h FFFFFFh
Note:
Memory areas are not shown to scale.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 23
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3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS
The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ64GA004 family devices, the top two words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ64GA004 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 23.1 “Configuration Bits”.
3.1.2
HARD MEMORY VECTORS
All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”.
TABLE 3-1:
FLASH CONFIGURATION WORDS FOR PIC24FJ64GA004 FAMILY DEVICES
Program Memory (K words) 5.5 11 16 22 Configuration Word Addresses 002BFCh: 002BFEh 0057FCh: 0057FEh 0083FCh: 0083FEh 00ABFCh: 00ABFEh
Device
PIC24FJ16GA PIC24FJ32GA PIC24FJ48GA PIC24FJ64GA
FIGURE 3-2:
msw Address 000001h 000003h 000005h 000007h
PROGRAM MEMORY ORGANIZATION
most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (lsw Address)
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3.2 Data Address Space
The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the program space visibility area (see Section 3.3.3 “Reading Data From Program Memory Using Program Space Visibility”). PIC24FJ64GA family devices implement a total of 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned.
3.2.1
DATA SPACE WIDTH
The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses.
FIGURE 3-3:
DATA SPACE MEMORY MAP FOR PIC24FJ64GA004 FAMILY DEVICES(1)
MSB Address 0001h 07FFh 0801h LSB Address 0000h 07FEh 0800h SFR Space Near Data Space
MSB SFR Space
LSB
Implemented Data RAM
Data RAM 1FFFh 2001h 27FFh(2) 2801h Unimplemented Read as ‘0’ 7FFFh 8001h 7FFFh 8000h 1FFEh 2000h 27FEh(2) 2800h
Program Space Visibility Area
FFFFh Note 1: 2:
FFFEh
Data memory areas are not shown to scale. Upper memory limit for PIC24FJ16GAXXX devices is 17FFh.
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 25
PIC24FJ64GA004 FAMILY
3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address (EA) calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words.
3.2.3
NEAR DATA SPACE
The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field.
3.2.4
SFR SPACE
The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-24.
TABLE 3-2:
IMPLEMENTED REGIONS OF SFR DATA SPACE
SFR Space Address xx00 xx20 Core Timers I
2C™
xx40 Capture
xx60 ICN — SPI — — — — NVM/PMD
xx80 Compare — — — — —
xxA0 Interrupts — — — — — PPS —
xxC0 — I/O — — — —
xxE0 — — — — — —
000h 100h 200h 300h 400h 500h 600h 700h — — PMP —
UART A/D — — RTC/Comp — — — — CRC System
Legend: — = No implemented SFRs in this block
DS39881C-page 26
Preliminary
© 2008 Microchip Technology Inc.
TABLE 3-3:
Bit 13 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Value Register Program Counter Low Byte Register — — — — — — — — — — — — — — DC — — — — — Repeat Loop Counter Register IPL2 — IPL1 — IPL0 — Disable Interrupts Counter Register RA — N IPL3 OV PSV Z — C — — — — — — — — — — — Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU CORE REGISTERS MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
File Name
Addr
Bit 15
Bit 14
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
© 2008 Microchip Technology Inc.
Bit 13 CN13IE CN29IE CN12PUE CN28IE
(1)
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
PCL
002E
PIC24FJ64GA004 FAMILY
Preliminary
Bit 12 CN12IE CN27IE CN26IE CN11IE CN10IE(1)
(1)
PCH
0030
—
—
TBLPAG
0032
—
—
PSVPAG
0034
—
—
RCOUNT
0036
SR
0042
—
—
CORCON
0044
—
—
DISICNT
0052
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-4:
Bit 11 Bit 10 Bit 9
ICN REGISTER MAP
Bit 8 CN9IE(1) CN25IE
(1)
File Addr Name
Bit 15
Bit 14
Bit 7 CN8IE(1) CN24IE CN7IE CN23IE
Bit 6 CN6IE CN22IE CN6PUE
Bit 5 CN5IE CN21IE CN5PUE
Bit 4 CN4IE CN20IE(1) CN4PUE
Bit 3 CN3IE CN19IE(1) CN3PUE
Bit 2 CN2IE CN18IE(1) CN2PUE
Bit 1 CN1IE CN17IE(1) CN1PUE
Bit 0 CN0IE CN16IE CN0PUE
All Resets 0000 0000 0000 0000
CNEN1 0060
CN15IE
CN14IE
CNEN2 0062
—
CN30IE
CNPU1 0068 CN15PUE CN14PUE CN13PUE
CN11PUE CN10PUE(1) CN9PUE(1) CN8PUE(1) CN7PUE
CNPU2 006A
—
CN30PUE CN29PUE CN28PUE(1) CN27PUE CN26PUE(1) CN25PUE(1) CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE(1) CN19PUE(1) CN18PUE(1) CN17PUE(1) CN16PUE
DS39881C-page 27
Legend: Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are not available on 28-pin devices; read as ‘0’.
TABLE 3-5:
Bit 13 — — AD1IF INT2IF — — — LVDIF T3IE — — — LVDIE OC1IP0 OC2IP0 SPI1IP0 — CMIP0 — OC4IP0 — — — — — — — — — — INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 — — — IC4IP0 — — RTCIP0 — OC3IP2 — — — OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 — U1ERIP2 U1ERIP1 — — MI2C1P2 MI2C1P1 — AD1IP2 AD1IP1 — SPF1IP2 SPF1IP1 — IC2IP2 IC2IP1 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 — OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 — U1ERIP0 — — IC1IP2 IC1IP1 IC1IP0 — — — — — — — — — CRCIE — — — — — — — — — — — — — — — — IC5IE IC4IE IC3IE — — — — — INT1IE CNIE T2IE OC2IE IC2IE — T1IE OC1IE CMIE — MI2C2IE U2ERIE INT0IP2 — T3IP2 U1TXIP2 SI2C1P2 INT1IP2 — T5IP2 SPF2IP2 — — — — — — LVDIP2 — — — — CRCIF U2ERIF — — — — — MI2C2IF IC5IF IC4IF IC3IF — — — SPI2IF SI2C2IF U1ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE INT0IP1 — T3IP1 U1TXIP1 SI2C1P1 INT1IP1 — T5IP1 SPF2IP1 — — — — — — LVDIP1 — — — INT1IF CNIF CMIF MI2C1IF PMPIF — — AD1IE INT2IE PMPIE — — T1IP1 T2IP1 — — — — — — — — — — — — — — — — RTCIP2 RTCIP1 U2ERIP2 U2ERIP1 U2ERIP0 MI2C2P2 MI2C2P1 MI2C2P0 — — — — IC4IP2 IC4IP1 — — U2RXIP2 U2RXIP1 U2RXIP0 OC4IP2 OC4IP1 — — CMIP2 CMIP1 — — SPI1IP2 SPI1IP1 — CNIP1 — T4IP1 U2TXIP1 — IC5IP1 — — — — CRCIP1 — — CRCIP0 — — — — IC5IP0 — U2TXIP0 T4IP0 — CNIP0 — T2IP0 — OC2IP2 OC2IP1 T1IP0 — OC1IP2 OC1IP1 — — — — — — — — — — — OC5IE T5IE T4IE OC4IE OC3IE U1TXIE U1RXIE SPI1IE SPF1IE — — — — — — — — — — — OC5IF T5IF T4IF OC4IF OC3IF U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF — — — — — — — — — — INT2EP INT1EP INT0EP INT0IF SI2C1IF SPF2IF — — INT0IE SI2C1IE SPF2IE — — INT0IP0 — T3IP0 U1TXIP0 SI2C1P0 INT1IP0 — T5IP0 SPF2IP0 — — — — — — LVDIP0 — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444 4444
INTERRUPT CONTROLLER REGISTER MAP
File Name
Addr
Bit 15
Bit 14
INTCON1
0080
NSTDIS
—
DS39881C-page 28
INTCON2
0082
ALTIVT
DISI
IFS0
0084
—
—
IFS1
0086
U2TXIF
U2RXIF
IFS2
0088
—
—
IFS3
008A
—
RTCIF
IFS4
008C
—
—
IEC0
0094
—
—
IEC1
0096
U2TXIE
U2RXIE
IEC2
0098
—
—
IEC3
009A
—
RTCIE
IEC4
009C
—
—
IPC0
00A4
—
T1IP2
IPC1
00A6
—
T2IP2
IPC2
00A8
—
U1RXIP2 U1RXIP1 U1RXIP0
IPC3
00AA
—
—
IPC4
00AC
—
CNIP2
IPC5
00AE
—
—
PIC24FJ64GA004 FAMILY
Preliminary
IPC6
00B0
—
T4IP2
IPC7
00B2
—
U2TXIP2
IPC8
00B4
—
—
IPC9
00B6
—
IC5IP2
IPC10
00B8
—
—
IPC11
00BA
—
—
IPC12
00BC
—
—
IPC15
00C2
—
—
IPC16
00C4
—
CRCIP2
IPC18
00C8
—
—
© 2008 Microchip Technology Inc.
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-6:
Bit 13 Timer1 Register Timer1 Period Register TSIDL Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register TSIDL TSIDL Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register TSIDL TSIDL — — — — — — TGATE — — — — — — TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 — — — TCS TCS — — — — — — — — TGATE TCKPS1 TCKPS0 — — — — — — — TGATE TCKPS1 TCKPS0 T32 — — TCS TCS — — — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
TIMER REGISTER MAP
All Resets 0000 FFFF 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000
File Name
Addr
Bit 15
Bit 14
TMR1
0100
PR1
0102
T1CON
0104
TON
—
TMR2
0106
TMR3HLD
0108
TMR3
010A
© 2008 Microchip Technology Inc.
Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Input 1 Capture Register ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL — — — — — — — — — — — — — — — — — — — — — — — — — ICTMR ICTMR Input 3 Capture Register ICTMR Input 4 Capture Register ICTMR Input 5 Capture Register ICTMR ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 ICI1 ICI1 ICI0 ICI0 ICOV ICOV ICBNE ICBNE ICM2 ICM2 ICM1 ICM1 ICM0 ICM0 Input 2 Capture Register
PR2
010C
PR3
010E
T2CON
0110
TON
—
T3CON
0112
TON
—
TMR4
0114
TMR5HLD
0116
TMR5
0118
PR4
011A
PR5
011C
T4CON
011E
TON
—
T5CON
0120
TON
—
PIC24FJ64GA004 FAMILY
Preliminary
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-7:
INPUT CAPTURE REGISTER MAP
All Resets FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000 FFFF 0000
File Name
Addr
Bit 15
Bit 14
IC1BUF
0140
IC1CON
0142
—
—
IC2BUF
0144
IC2CON
0146
—
—
IC3BUF
0148
IC3CON
014A
—
—
IC4BUF
014C
IC4CON
014E
—
—
IC5BUF
0150
IC5CON
0152
—
—
DS39881C-page 29
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-8:
Bit 13 Output Compare 1 Secondary Register Output Compare 1 Register OCSIDL Output Compare 2 Secondary Register Output Compare 2 Register OCSIDL Output Compare 3 Secondary Register Output Compare 3 Register OCSIDL Output Compare 4 Secondary Register Output Compare 4 Register OCSIDL Output Compare 5 Secondary Register Output Compare 5 Register OCSIDL — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 — — — — — — — — OCFLT OCTSEL OCM2 OCM1 OCM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000 FFFF FFFF 0000
OUTPUT COMPARE REGISTER MAP
File Name
Addr
Bit 15
Bit 14
OC1RS
0180
DS39881C-page 30
Bit 13 — — — I2CSIDL — — — — — — I2CSIDL — — — — — — — — — SCLREL IPMIEN A10M BCL — — AMSK9 AMSK8 AMSK7 AMSK6 — — — — — — — — — — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV — — — AMSK9 — — — AMSK8 — — ACKDT D/A AMSK5 AMSK7 AMSK6 — — BCL GCSTAT ADD10 SCLREL IPMIEN A10M DISSLW SMEN — — — — GCEN IWCOL STREN I2COV — — — — — ACKDT D/A AMSK5 — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Receive Register 1 Transmit Register 1 Baud Rate Generator Register 1 ACKEN P Address Register 1 AMSK4 AMSK3 Receive Register 2 Transmit Register 2 Baud Rate Generator Register 2 ACKEN P Address Register 2 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 RCEN S PEN R/W RSEN RBF SEN TBF AMSK2 AMSK1 AMSK0 RCEN S PEN R/W RSEN RBF SEN TBF Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000 — — — — — — — — — — — —
OC1R
0182
OC1CON
0184
—
—
OC2RS
0186
OC2R
0188
OC2CON
018A
—
—
OC3RS
018C
OC3R
018E
OC3CON
0190
—
—
OC4RS
0192
OC4R
0194
OC4CON
0196
—
—
OC5RS
0198
OC5R
019A
OC5CON
019C
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ64GA004 FAMILY
Preliminary
TABLE 3-9:
I2C™ REGISTER MAP
File Name
Addr
Bit 15
Bit 14
I2C1RCV
0200
—
I2C1TRN
0202
—
I2C1BRG
0204
—
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT
TRSTAT
I2C1ADD
020A
—
I2C1MSK
020C
—
I2C2RCV
0210
—
I2C2TRN
0212
—
I2C2BRG
0214
—
I2C2CON
0216
I2CEN
I2C2STAT
0218
ACKSTAT
TRSTAT
I2C2ADD
021A
—
I2C2MSK
021C
—
© 2008 Microchip Technology Inc.
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-10:
Bit 13 USIDL — — — Baud Rate Generator Prescaler Register USIDL — — — Baud Rate Generator Prescaler — — — URX8 URX7 URX6 URX5 URX4 URX3 — — — UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTXBRK UTXEN UTXBF TRMT URCISEL1 URCISEL0 ADDEN RIDLE PERR — — IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 FERR UTX2 URX2 PDSEL0 OERR UTX1 URX1 STSEL URXDA UTX0 URX0 — — — URX8 URX7 URX6 URX5 URX4 URX3 URX2 — — — UTX8 UTX7 UTX6 UTX5 UTX4 UTX3 UTX2 UTX1 URX1 UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR — — IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL URXDA UTX0 URX0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
UART REGISTER MAP
All Resets 0000 0110 0000 0000 0000 0000 0110 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
U1MODE
0220
UARTEN
—
U1STA
0222
UTXISEL1 UTXINV UTXISEL0
U1TXREG
0224
—
—
U1RXREG
0226
—
—
U1BRG
0228
© 2008 Microchip Technology Inc.
Bit 13 SPISIDL — SPIFPOL — SPI1 Transmit/Receive Buffer SPISIDL — SPIFPOL — — — — — DISSCK DISSDO MODE16 SMP CKE — — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SSEN SPIROV CKP — SRXMPT MSTEN — SISEL2 SPRE2 — SISEL1 SPRE1 — SISEL0 SPRE0 — SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN — — — — — — DISSCK DISSDO MODE16 SMP CKE SSEN CKP — — SPIBEC2 SPIBEC1 SPIBEC0 SRMPT SPIROV Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 SRXMPT MSTEN — Bit 4 SISEL2 SPRE2 — Bit 3 SISEL1 SPRE1 — Bit 2 SISEL0 SPRE0 — Bit 1 SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN SPI2 Transmit/Receive Buffer
U2MODE
0230
UARTEN
—
U2STA
0232
UTXISEL1 UTXINV UTXISEL0
U2TXREG
0234
—
—
U2RXREG
0236
—
—
U2BRG
0238
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-11:
SPI REGISTER MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
SPI1STAT
0240
SPIEN
—
SPI1CON1
0242
—
—
PIC24FJ64GA004 FAMILY
Preliminary
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
SPI2STAT
0260
SPIEN
—
SPI2CON1
0262
—
—
SPI2CON2
0264
FRMEN
SPIFSD
SPI2BUF
0268
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS39881C-page 31
TABLE 3-12:
Bit 13 — — — — — — ODA10(1) — — ODA4 ODA1 ODA9(1) ODA8(1) ODA7(1) ODA3(2) ODA2(3) — — LATA10(1) — — LATA4 LATA1 LATA9(1) LATA8(1) LATA7(1) LATA3(2) LATA2(3) — — RA10(1) — — RA4 RA1 RA9(1) RA8(1) RA7(1) RA3(2) RA2(3) RA0 LATA0 ODA0 — — TRISA10(1) TRISA9(1) TRISA8(1) TRISA7(1) — — TRISA4 TRISA1 TRISA0 TRISA3(2) TRISA2(3) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 079F 0000 0000 0000
PORTA REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISA
02C0
—
—
DS39881C-page 32
Bit 13 TRISB10 RB10 LATB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 LATB9 LATB8 LATB7 LATB6 LATB5 RB9 RB8 RB7 RB6 RB5 RB4 LATB4 ODB4 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 All Resets FFFF 0000 0000 0000 RB13 LATB13 ODB13 ODB12 ODB11 LATB12 LATB11 RB12 RB11 Bit 13 — — — — — — — ODC9 OSC8 — — — LATC9 LATC8 — — — RC9 RC8 RC7 LATC7 ODC7 — — — TRISC9 TRISC8 TRISC7 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISC6 RC6 LATC6 ODC6 Bit 5 TRISC5 RC5 LATC5 ODC5 Bit 4 TRISC4 RC4 LATC4 ODC4 Bit 3 TRISC3 RC3 LATC3 ODC3 Bit 2 TRISC2 RC2 LATC2 ODC2 Bit 1 TRISC1 RC1 LATC1 ODC1 Bit 0 TRISC0 RC0 LATC0 ODC0 All Resets 03FF 0000 0000 0000 Bit 13 — — — — Bit 12 Bit 11 Bit 10 Bit 9 — Bit 8 — Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 Bit 0 RTSECSEL PMPTTL All Resets 0000
PORTA
02C2
—
—
LATA
02C4
—
—
ODCA
02C6
—
—
Legend: Note 1: 2: 3:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are not available on 28-pin devices; read as ‘0’. Bits are available only when the primary oscillator is disabled (POSCMD = 00); otherwise read as ‘0’. Bits are available only when the primary oscillator is disabled or EC mode is selected (POSCMD = 00 or 11) and CLKO is disabled (OSCIOFNC = 0); otherwise, read as ‘0’.
TABLE 3-13:
PORTB REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISB
02C8
TRISB15 TRISB14 TRISB13 TRISB12 TRISB11
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODB15
ODB14
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24FJ64GA004 FAMILY
Preliminary
TABLE 3-14:
PORTC REGISTER MAP
File Name
Addr
Bit 15
Bit 14
TRISC(1)
02D0
—
—
PORTC(1)
02D2
—
—
LATC(1)
02D4
—
—
ODCC(1)
02D6
—
—
Legend: Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are not available on 28-pin devices; read as ‘0’.
TABLE 3-15:
PAD CONFIGURATION REGISTER MAP
File Name
Addr
Bit 15
Bit 14
PADCFG1
02FC
—
—
© 2008 Microchip Technology Inc.
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-16:
Bit 13 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 — VCFG0 — — — — CSSL12 CSSL11 CSSL10 CSSL9 PCFG12 PCFG11 PCFG10 PCFG9 — CH0SB3 CH0SB2 CH0SB1 CH0SB0 CH0NA — SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS7 ADCS6 — — CSCNA — — BUFS — — — — — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 — PCFG5 CSSL5 — SMPI2 ADCS4 — PCFG4 CSSL4 — SMPI1 ADCS3 CH0SA3 PCFG3 CSSL3 ASAM SMPI0 ADCS2 CH0SA2 PCFG2 CSSL2 SAMP BUFM ADCS1 CH0SA1 PCFG1 CSSL1 DONE ALTS ADCS0 CH0SA0 PCFG0 CSSL0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC REGISTER MAP
All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
© 2008 Microchip Technology Inc.
PCFG8(1) PCFG7(1) PCFG6(1) CSSL8(1) CSSL7(1) CSSL6(1) Bit 13 PSIDL IRQM0 — — — ADDR10 INCM1 INCM0 MODE16 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CSF1 MODE0 ADDR9 ADDR8 WAITB1 ADDR7 Bit 6 CSF0 WAITB0 ADDR6 Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) — — — — — IB3F PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 OBE PTEN6 OBUF PTEN5 — PTEN4 — PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E Bit 5 ALP WAITM3 ADDR5 Bit 4 — WAITM2 ADDR4 Bit 3 CS1P WAITM1 ADDR3 Bit 2 BEP WAITM0 ADDR2 Bit 1 WRSP WAITE1 ADDR1 Bit 0 RDSP WAITE0 ADDR0 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN MODE1
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
AD1CON1
0320
ADON
AD1CON2
0322
VCFG2
VCFG1
AD1CON3
0324
ADRC
AD1CHS
0328
CH0NB
PIC24FJ64GA004 FAMILY
Preliminary
AD1PCFG
032C
PCFG15
AD1CSSL
0330
CSSL15
Legend: Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are not available on 28-pin devices; read as ‘0’.
TABLE 3-17:
PARALLEL MASTER/SLAVE PORT REGISTER MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
PMCON
0600
PMPEN
—
PMMODE
0602
BUSY
IRQM1
PMADDR
0604
—
CS1
PMDOUT1
PMDOUT2 0606
PMDIN1
0608
PMDIN2
060A
PMAEN
060C
—
PTEN14
PMSTAT
060E
IBF
IBOV
DS39881C-page 33
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-18:
Bit 13 Alarm Value Register Window Based on ALRMPTR AMASK3 RTCC Value Register Window Based on RTCPTR RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx 0000 xxxx 0000
REAL-TIME CLOCK AND CALENDAR REGISTER MAP
File Name
Addr
Bit 15
Bit 14
ALRMVAL
0620
ALCFGRPT
0622
ALRMEN
CHIME
DS39881C-page 34
Bit 13 C2EVT — — — — — — CVREN CVROE CVRR CVRSS CVR3 C1EVT C2EN C1EN C2OUTEN C1OUTEN C2OUT C1OUT C2INV C1INV C2NEG Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C2POS CVR2 Bit 1 C1NEG CVR1 Bit 0 C1POS CVR0 All Resets 0000 0000 Bit 13 CSIDL X13 CRC Data Input Register CRC Result Register X12 X11 X10 X9 X8 X7 X6 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT — X5 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 CRCGO X4 Bit 3 PLEN3 X3 Bit 2 PLEN2 X2 Bit 1 PLEN1 X1 Bit 0 PLEN0 — All Resets 0040 0000 0000 0000 —
RTCVAL
0624
RCFGCAL
0626
RTCEN
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-19:
DUAL COMPARATOR REGISTER MAP
File Name
Addr
Bit 15
Bit 14
CMCON
0630
CMIDL
—
CVRCON
0632
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-20:
CRC REGISTER MAP
File Name
Addr
Bit 15
Bit 14
CRCCON
0640
—
PIC24FJ64GA004 FAMILY
Preliminary
CRCXOR
0642
X15
X14
CRCDAT
0644
CRCWDAT
0646
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc.
TABLE 3-21:
Bit 13 — — — — — — — — — — — — — — — — — — — — — — — — — — — RP19R4(1) RP19R3(1) RP19R2(1) RP19R1(1) RP19R0(1) RP21R4(1) RP21R3(1) RP21R2(1) RP21R1(1) RP21R0(1) RP23R4(1) RP23R3(1) RP23R2(1) RP23R1(1) RP23R0(1) RP25R4(1) RP25R3(1) RP25R2(1) RP25R1(1) RP25R0(1) RP17R4(1) RP17R3(1) RP17R2(1) RP17R1(1) RP17R0(1) RP15R4 RP15R3 RP15R2 RP15R1 RP15R0 — — — — — — RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 — RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 — RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 — — — — — — — — — — RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 — — RP5R4 RP5R3 RP5R2 RP5R1 RP5R0 — — RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — — — — — — — — — — — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — — — — — — — — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — — SDI2R4 SS2R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 — — — — — — — — SS1R4 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — — SDI1R4 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 — — — U2RXR4 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 — — — U1RXR4 U1RXR3 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — — OCFAR4 OCFAR3 — — — — — — — — IC5R4 IC5R3 IC5R2 OCFAR2 U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — — IC3R4 IC3R3 IC3R2 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — — IC1R4 IC1R3 IC1R2 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — — T4CKR4 T4CKR3 T4CKR2 IC1R1 IC3R1 IC5R1 OCFAR1 U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — — T2CKR4 T2CKR3 T2CKR2 T2CKR1 T4CKR1 — — — — — — — — INT2R4 INT2R3 INT2R2 INT2R1 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — INT2R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 OCFAR0 U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R4(1) RP16R3(1) RP16R2(1) RP16R1(1) RP16R0(1) RP18R4(1) RP18R3(1) RP18R2(1) RP18R1(1) RP18R0(1) RP20R4(1) RP20R3(1) RP20R2(1) RP20R1(1) RP20R0(1) RP22R4(1) RP22R3(1) RP22R2(1) RP22R1(1) RP22R0(1) RP24R4(1) RP24R3(1) RP24R2(1) RP24R1(1) RP24R0(1) Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PERIPHERAL PIN SELECT REGISTER MAP
All Resets 1F00 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 001F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
RPINR0
0680
—
—
RPINR1
0682
—
—
RPINR3
0686
—
—
RPINR4
0688
—
—
RPINR7
068E
—
—
RPINR8
0690
—
—
© 2008 Microchip Technology Inc.
RPINR9
0692
—
—
RPINR11
0696
—
—
RPINR18
06A4
—
—
RPINR19
06A6
—
—
RPINR20
06A8
—
—
RPINR21
06AA
—
—
RPINR22
06AC
—
—
RPINR23
06AE
—
—
RPOR0
06C0
—
—
RPOR1
06C2
—
—
RPOR2
06C4
—
—
RPOR3
06C6
—
—
PIC24FJ64GA004 FAMILY
Preliminary
RPOR4
06C8
—
—
RPOR5
06CA
—
—
RPOR6
06CC
—
—
RPOR7
06CE
—
—
RPOR8
06D0
—
—
RPOR9
06D2
—
—
RPOR10
06D4
—
—
RPOR11
06D6
—
—
RPOR12
06D8
—
—
Legend: Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are only available on the 44-pin devices; otherwise, they read as ‘0’.
DS39881C-page 35
TABLE 3-22:
Bit 13 — COSC1 DOZE1 — — — TUN5 TUN4 TUN3 TUN2 TUN1 — — — — — — — — — — — — DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 — TUN0 COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF — SOSCEN — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets (Note 1) 3140 0000
CLOCK CONTROL REGISTER MAP
File Name
Addr
Bit 15
Bit 14
RCON
0740
TRAPR
IOPUWR
OSCCON
0742
—
COSC2
OSWEN (Note 2)
DS39881C-page 36
Bit 13 WRERR — — — — — — — — — — — — ERASE — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000 NVMKEY Bit 13 T3MD — — — — CMPMD RTCCMD PMPMD CRCPMD IC5MD IC4MD IC3MD IC2MD IC1MD — T2MD T1MD — — — I2C1MD U2MD — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 U1MD — — Bit 4 SPI2MD OC5MD — Bit 3 SPI1MD OC4MD — Bit 2 — OC3MD — Bit 1 — OC2MD I2C2MD Bit 0 ADC1MD OC1MD — All Resets 0000 0000 0000
CLKDIV
0744
ROI
DOZE2
OSCTUN
0748
—
—
Legend: Note 1: 2:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values are dependent on type of Reset. OSCCON register Reset values are dependent on configuration fuses and by type of Reset.
TABLE 3-23:
NVM REGISTER MAP
File Name
Addr
Bit 15
Bit 14
NVMCON
0760
WR
WREN
NVMKEY
0766
—
—
Legend: Note 1:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 3-24:
PMD REGISTER MAP
PIC24FJ64GA004 FAMILY
Preliminary
File Name
Addr
Bit 15
Bit 14
PMD1
0770
T5MD
T4MD
PMD2
0772
—
—
PMD3
0774
—
—
Legend:
— = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.2.5 SOFTWARE STACK
3.3
In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push.
Interfacing Program and Data Memory Spaces
The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (program space visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word.
The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.
3.3.1
ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-25 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, whereas D refers to a data space word.
FIGURE 3-4:
0000h 15
CALL STACK FRAME
0
Stack Grows Towards Higher Address
PC 000000000 PC
W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++]
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 37
PIC24FJ64GA004 FAMILY
TABLE 3-25: PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: User 0 0 Program Space Address 0 TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx PSVPAG xxxx xxxx PC 0xx xxxx xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG.
FIGURE 3-5:
DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter 23 Bits EA
0
1/0
Table Operations(2)
1/0
TBLPAG 8 Bits 24 Bits 16 Bits
Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 Bits
1
EA
0
15 Bits 23 Bits
User/Configuration Space Select
Byte Select
Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.
DS39881C-page 38
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom’ byte, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1).
The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P) to a data address (D). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’.
In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed.
FIGURE 3-6:
TBLPAG 02
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
Data EA 23 15 0 000000h
00000000 00000000 00000000 00000000
23
16
8
0
020000h 030000h
‘Phantom’ Byte
TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.
800000h
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 39
PIC24FJ64GA004 FAMILY
3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes.
The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’, and program space visibility is enabled by setting the PSV bit in the CPU Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the
For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG 02 23 15 0 000000h 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space....
Data Space
0000h Data EA
8000h
PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.
FFFFh
800000h
DS39881C-page 40
Preliminary
© 2008 Microchip Technology Inc.
PIC24FJ64GA004 FAMILY
4.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 4. Program Memory” (DS39715).
RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time.
4.1
Table Instructions and Flash Programming
The PIC24FJ64GA004 family of devices contains internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable when operating with VDD over 2.25V. Flash memory can be programmed in four ways: • • • • In-Circuit Serial Programming™ (ICSP™) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming (Enhanced ICSP)
Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
ICSP allows a PIC24FJ64GA004 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGCx and PGDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
FIGURE 4-1:
ADDRESSING FOR TABLE REGISTERS
24 Bits Using Program Counter 0 Program Counter 0
Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits
User/Configuration Space Select
24-Bit EA
Byte Select
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 41
PIC24FJ64GA004 FAMILY
4.2 RTSP Operation 4.4
The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing it is not recommended.
Enhanced In-Circuit Serial Programming
Enhanced In-Circuit Serial Programming uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification.
4.5
Control Registers
There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 “Programming Operations” for further details.
4.6
Programming Operations
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation and the WR bit is automatically cleared when the operation is finished. Configuration Word values are stored in the last two locations of program memory. Performing a page erase operation on the last page of program memory clears these values and enables code protection. As a result, avoid performing page erase operations on the last page of program memory.
All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row.
4.3
JTAG Operation
The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin to PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF).
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REGISTER 4-1:
R/SO-0 WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Set Only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ERASE U-0 — U-0 — R/W-0 NVMOP3
(1)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0 WREN R/W-0 WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 NVMOP2
(1)
R/W-0 NVMOP1
(1)
R/W-0 NVMOP0(1) bit 0
WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command Unimplemented: Read as ‘0’ NVMOP3:NVMOP0: NVM Operation Select bits(1) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(2) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSP™ mode only. Refer to device programming specification.
bit 14
bit 13
bit 12-7 bit 6
bit 5-4 bit 3-0
Note 1: 2:
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4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-1). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.
6.
For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.
EXAMPLE 4-1:
ERASING A PROGRAM MEMORY BLOCK
; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ;
; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO.
19.1.2
INTERRUPT OPERATION
When the VWORD4:VWORD0 bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated.
19.2
19.2.1
Operation in Power Save Modes
SLEEP MODE
If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes.
19.2.2
IDLE MODE
To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available.
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19.3 Registers
There are four registers used to control programmable CRC operation: • • • • CRCCON CRCXOR CRCDAT CRCWDAT
REGISTER 19-1:
U-0 — bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13
CRCCON: CRC CONTROL REGISTER
U-0 — R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 R-1 U-0 — R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 R/W-0 PLEN0 bit 0
CRCMPT
W = Writable bit ‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown
Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 ≤ 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as ‘0’ CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1.
bit 12-8
bit 7
bit 6
bit 5 bit 4
bit 3-0
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REGISTER 19-2:
R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 — bit 0
CRCXOR: CRC XOR POLYNOMIAL REGISTER
R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14
R/W-0
X15:X1: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as ‘0’
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20.0
Note:
10-BIT HIGH-SPEED A/D CONVERTER
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 17. 10-Bit A/D Converter” (DS39705).
A block diagram of the A/D Converter is shown in Figure 20-1. To perform an A/D conversion: 1. Configure the A/D module: a) Select port pins as analog inputs (AD1PCFG). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority.
The 10-bit A/D Converter has the following key features: • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps Up to 13 analog input pins External voltage reference input pins Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes
2.
Depending on the particular device pinout, the 10-bit A/D Converter can have up to three analog input pins, designated AN0 through AN12. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins. The actual number of analog input pins and external voltage reference input configuration will depend on the specific device.
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FIGURE 20-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM
Internal Data Bus AVDD AVSS VREF+ VREFVR Select VR+
16
VRVINH VINL VINH
S/H VRVR+
Comparator DAC
AN0 AN1 MUX A AN2 AN3 AN4 AN5 AN6(1) AN7(1) MUX B AN8(1) AN9 AN10 AN11 AN12 VBG(2) VINH
10-Bit SAR
Conversion Logic
Data Formatting
VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS AD1PCFG AD1CSSL
VINL
Sample Control Input MUX Control Pin Config. Control
Control Logic
Conversion Control
Note 1: 2:
Analog channels AN6 through AN8 are available on 28-pin devices only. Band gap voltage reference (VBG) is internally connected to analog channel AN15, which does not appear on any pin.
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REGISTER 20-1:
R/W-0 ADON bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit ‘1’ = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 — U-0 — R/W-0 ASAM R/W-0, HCS SAMP
AD1CON1: A/D CONTROL REGISTER 1
U-0 — R/C-0 ADSIDL U-0 — U-0 — U-0 — R/W-0 FORM1 R/W-0 FORM0 bit 8 R/W-0, HCS DONE bit 0
ADON: A/D Operating Mode bit 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 10x = Reserved 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as ‘0’ ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done
bit 14 bit 13
bit 12-10 bit 9-8
bit 7-5
bit 4-3 bit 2
bit 1
bit 0
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REGISTER 20-2:
R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM
AD1CON2: A/D CONTROL REGISTER 2
R/W-0 VCFG0 R/W-0 — U-0 — R/W-0 CSCNA U-0 — U-0 — bit 8 R/W-0 ALTS bit 0
R/W-0 VCFG1
VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 000 001 010 011 1xx * VR+ AVDD* External VREF+ pin AVDD* External VREF+ pin AVDD* VRAVSS* AVSS* External VREF- pin External VREF- pin AVSS*
AVDD and AVSS inputs are tied to VDD and VSS on 28-pin devices.
bit 12-11 bit 10
Unimplemented: Read as ‘0’ CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F Unimplemented: Read as ‘0’ SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer configured as one 16-word buffer (ADC1BUFn) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings
bit 9-8 bit 7
bit 6 bit 5-2
bit 1
bit 0
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REGISTER 20-3:
R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1
AD1CON3: A/D CONTROL REGISTER 3
U-0 — U-0 — R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0
ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Unimplemented: Read as ‘0’ SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • TCY ······ 00000001 = 2 • TCY 00000000 = TCY
bit 14-13 bit 12-8
bit 7-0
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REGISTER 20-4:
R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/W-0 CH0SA3
(1,2)
AD1CHS: A/D INPUT SELECT REGISTER
U-0 — U-0 — U-0 — R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 CH0SA2
(1,2)
CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2)
R/W-0 CH0SA1
(1,2)
R/W-0 CH0SA0(1,2) bit 0
CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SB3:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2) 1111 = Channel 0 positive input is AN15 (band gap voltage reference) 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 ····· 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SA3:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits(1,2) 1111 = Channel 0 positive input is AN15 (band gap voltage reference) 1100 = Channel 0 positive input is AN12 1011 = Channel 0 positive input is AN11 ····· 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 Combinations ‘1101’ and ‘1110’ are unimplemented; do not use. Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; do not use.
bit 14-12 bit 11-8
bit 7
bit 6-4 bit 3-0
Note 1: 2:
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REGISTER 20-5:
R/W-0 PCFG15 bit 15 R/W-0 PCFG7(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PCFG6(1) R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1
AD1PCFG: A/D PORT CONFIGURATION REGISTER
U-0 — U-0 — R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8(1) bit 8 R/W-0 PCFG0 bit 0
PCFG15: Analog Input Pin Configuration Control bits 1 = Band gap voltage reference is disabled 0 = Band gap voltage reference enabled Unimplemented: Read as ‘0’ PCFG12:PCFG0: Analog Input Pin Configuration Control bits(1) 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits set.
bit 14-13 bit 12-0
Note 1:
REGISTER 20-6:
R/W-0 CSSL15 bit 15 R/W-0 CSSL7(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15
AD1CSSL: A/D INPUT SCAN SELECT REGISTER
U-0 — U-0 — R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8(1) bit 8
R/W-0 CSSL6(1)
R/W-0 CSSL5
R/W-0 CSSL4
R/W-0 CSSL3
R/W-0 CSSL2
R/W-0 CSSL1
R/W-0 CSSL0 bit 0
W = Writable bit ‘1’ = Bit is set
U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown
CSSL15: Band Gap Reference Input Pin Scan Selection bits 1 = Band gap voltage reference channel selected for input scan 0 = Band gap voltage reference channel omitted from input scan Unimplemented: Read as ‘0’ CSSL12:CSSL0: A/D Input Pin Scan Selection bits(1) 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan Analog channels AN6, AN7 and AN8 are unavailable on 28-pin devices; leave these corresponding bits cleared.
bit 14-13 bit 12-0
Note 1:
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EQUATION 20-1: A/D CONVERSION CLOCK PERIOD(1)
TAD = TCY • (ADCS +1) TAD –1 TCY
ADCS =
Note 1:
Based on TCY = 2 * TOSC; Doze mode and PLL are disabled.
FIGURE 20-2:
10-BIT A/D CONVERTER ANALOG INPUT MODEL
VDD ANx VT = 0.6V RIC ≤ 250Ω Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS ≤ 5 kΩ (Typical)
Rs VA
CPIN 6-11 pF (Typical)
VT = 0.6V
ILEAKAGE ±500 nA
Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD
Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ.
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FIGURE 20-3:
Output Code (Binary (Decimal))
A/D TRANSFER FUNCTION
11 1111 1111 (1023) 11 1111 1110 (1022)
10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509)
00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ – VR-) 512*(VR+ – VR-) (VINH – VINL) VR+ – VRVR+ 1024 0 VR-
1024
Voltage Level
VR- +
VR- +
1024
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VR- +
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NOTES:
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21.0
Note:
COMPARATOR MODULE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 16. Output Compare” (DS39706).
FIGURE 21-1:
COMPARATOR I/O OPERATING MODES
C1NEG
C1EN
CMCON C1INV C1OUT(1)
C1IN+ C1INC1POS C1IN+ CVREF
VINC1
VIN+ C1OUTEN
C2NEG C2IN+ C2INC2POS C2IN+ CVREF VIN+
C2EN
CMCON C2INV C2OUT(1)
VINC2
C2OUTEN
Note 1:
This peripheral’s outputs must be assigned to an available RPn pin before use. Please see Section 9.4 “Peripheral Pin Select” for more information.
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REGISTER 21-1:
R/W-0 CMIDL bit 15 R-0 C2OUT bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-0 C1OUT R/W-0 C2INV R/W-0 C1INV R/W-0 C2NEG R/W-0 C2POS R/W-0 C1NEG
CMCON: COMPARATOR CONTROL REGISTER
U-0 — R/C-0 C2EVT R/C-0 C1EVT R/W-0 C2EN R/W-0 C1EN R/W-0 R/W-0 bit 8 R/W-0 C1POS bit 0 C2OUTEN(1) C1OUTEN(2)
CMIDL: Stop in Idle Mode bit 1 = When device enters Idle mode, module does not generate interrupts; module is still enabled 0 = Continue normal module operation in Idle mode Unimplemented: Read as ‘0’ C2EVT: Comparator 2 Event 1 = Comparator output changed states 0 = Comparator output did not change states C1EVT: Comparator 1 Event 1 = Comparator output changed states 0 = Comparator output did not change states C2EN: Comparator 2 Enable 1 = Comparator is enabled 0 = Comparator is disabled C1EN: Comparator 1 Enable 1 = Comparator is enabled 0 = Comparator is disabled C2OUTEN: Comparator 2 Output Enable(1) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C1OUTEN: Comparator 1 Output Enable(2) 1 = Comparator output is driven on the output pad 0 = Comparator output is not driven on the output pad C2OUT: Comparator 2 Output bit When C2INV = 0: 1 = C2 VIN+ > C2 VIN0 = C2 VIN+ < C2 VINWhen C2INV = 1: 0 = C2 VIN+ > C2 VIN1 = C2 VIN+ < C2 VINC1OUT: Comparator 1 Output bit When C1INV = 0: 1 = C1 VIN+ > C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VIN-
bit 14 bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
bit 7
bit 6
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REGISTER 21-1:
bit 5
CMCON: COMPARATOR CONTROL REGISTER (CONTINUED)
C2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes. C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the Comparator modes. C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the Comparator modes. If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information. If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPn pin. See Section 9.4 “Peripheral Pin Select” for more information.
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: 2:
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NOTES:
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22.0
Note:
COMPARATOR VOLTAGE REFERENCE
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 20. Comparator Voltage Reference Module” (DS39709).
voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output.
22.1
Configuring the Comparator Voltage Reference
The voltage reference module is controlled through the CVRCON register (Register 22-1). The comparator voltage reference provides two ranges of output
FIGURE 22-1:
COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM
VREF+ AVDD CVRSS = 1
CVRSS = 0
8R R R R
CVR3:CVR0
CVREN
16 Steps
16-to-1 MUX
R
CVREF
R R R CVRR VREFCVRSS = 1
8R
CVRSS = 0 AVSS
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REGISTER 22-1:
U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1
CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CVR0 bit 0
Unimplemented: Read as ‘0’ CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits When CVRR = 1: CVREF = (CVR/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC)
bit 6
bit 5
bit 4
bit 3-0
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23.0
Note:
SPECIAL FEATURES
This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716)
23.1.1
CONSIDERATIONS FOR CONFIGURING PIC24FJ64GA004 FAMILY DEVICES
PIC24FJ64GA004 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation
In PIC24FJ64GA004 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the two words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 23-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among five locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets.
TABLE 23-1:
FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GA004 FAMILY DEVICES
Configuration Word Addresses 1 2 002BFCh 0057FCh 0083FCh 00ABFCh
Device
23.1
Configuration Bits
PIC24FJ16GA PIC24FJ32GA PIC24FJ48GA PIC24FJ64GA
The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A complete list is shown in Table 23-1. A detailed explanation of the various bit functions is provided in Register 23-1 through Register 23-4. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes.
002BFEh 0057FEh 0083FEh 00ABFEh
When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The Configuration bits are reloaded from the Flash Configuration Word on any device Reset. The upper byte of both Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation.
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REGISTER 23-1:
U-1 — bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit r = Reserved bit PO = Program Once bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/PO-1 WINDIS U-1 — R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 r R/PO-1 ICS1
CW1: FLASH CONFIGURATION WORD 1
U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0
-n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 Unimplemented: Read as ‘1’
Reserved: The value is unknown; program as ‘0’ JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Always maintain as ‘1’ ICS1:ICS0: Emulator Pin Placement Select bits 11 = Emulator EMUC1/EMUD1 pins are shared with PGC1/PGD1 10 = Emulator EMUC2/EMUD2 pins are shared with PGC2/PGD2 01 = Emulator EMUC3/EMUD3 pins are shared with PGC3/PGD3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be ‘1’ Unimplemented: Read as ‘1’ FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32
bit 13
bit 12
bit 11
bit 10 bit 9-8
bit 7
bit 6
bit 5 bit 4
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REGISTER 23-1:
bit 3-0
CW1: FLASH CONFIGURATION WORD 1 (CONTINUED)
WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1
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REGISTER 23-2:
U-1 — bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7
CW2: FLASH CONFIGURATION WORD 2
U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0
U-1 —
U-1 —
U-1 —
U-1 —
R/PO-1 FNOSC2
R/PO-1 FNOSC1
R/PO-1 FCKSM0
R/PO-1 OSCIOFCN
R/PO-1 IOL1WAY
U-1 —
R/PO-1 I2C1SEL
R/PO-1 POSCMD1
Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15
U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared
bit 14-11 bit 10-8
bit 7-6
bit 5
bit 4
bit 3 bit 2
bit 1-0
Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled Unimplemented: Read as ‘1’ FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RA3 functions as port I/O (RA3) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RA3. IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The OSCCON bit can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The OSCCON bit can be set and cleared as needed, provided the unlock sequence has been completed Unimplemented: Read as ‘1’ I2C1SEL: I2C1 Pin Select bit 1 = Use default SCL1/SDA1 pins 0 = Use alternate SCL1/SDA1 pins POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected
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REGISTER 23-3:
U — bit 23 U — bit 15 R FAMID1 bit 7
DEVID: DEVICE ID REGISTER
U — U — U — U — U — U — U — bit 16 R FAMID2 bit 8 R DEV0 bit 0
U —
R FAMID7
R FAMID6
R FAMID5
R FAMID4
R FAMID3
R FAMID0
R DEV5
R DEV4
R DEV3
R DEV2
R DEV1
Legend: R = Read-only bit bit 23-14 bit 13-6 bit 5-0
U = Unimplemented bit
Unimplemented: Read as ‘1’ FAMID7:FAMID0: Device Family Identifier bits 00010001 = PIC24FJ64GA004 family DEV5:DEV0: Individual Device Identifier bits 000100 = PIC24FJ16GA002 000101 = PIC24FJ32GA002 000110 = PIC24FJ48GA002 000111 = PIC24FJ64GA002 001100 = PIC24FJ16GA004 001101 = PIC24FJ32GA004 001110 = PIC24FJ48GA004 001111 = PIC24FJ64GA004
REGISTER 23-4:
U — bit 23 U — bit 15 R MAJRV1 bit 7
DEVREV: DEVICE REVISION REGISTER
U — U — U — U — U — U — U — bit 16 R MAJRV2 bit 8 R DOT0 bit 0
U —
U —
U —
U —
U —
U —
R MAJRV0
U —
U —
U —
R DOT2
R DOT1
Legend: R = Read-only bit bit 23-9 bit 8-6 bit 5-3 bit 2-0
U = Unimplemented bit
Unimplemented: Read as ‘0’ MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as ‘0’ DOT2:DOT0: Minor Revision Identifier bits
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23.2 On-Chip Voltage Regulator
FIGURE 23-1:
All of the PIC24FJ64GA004 family of devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ64GA004 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the DISVREG pin. Tying VSS to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 23-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 26.1 “DC Characteristics”. If DISVREG is tied to VDD, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 23-1 for possible configurations.
CONNECTIONS FOR THE ON-CHIP REGULATOR
Regulator Enabled (DISVREG tied to VSS): 3.3V PIC24FJ64GA VDD DISVREG VDDCORE/VCAP CEFC (10 μF typ) VSS
Regulator Disabled (DISVREG tied to VDD): 2.5V(1) 3.3V(1) PIC24FJ64GA VDD DISVREG VDDCORE/VCAP VSS
23.2.1
VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION
Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ64GA VDD DISVREG VDDCORE/VCAP VSS
When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent “brown out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled.
Note 1:
These are typical operating voltages. Refer to Section 26.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE.
23.2.2
ON-CHIP REGULATOR AND POR
When the voltage regulator is enabled, it takes approximately 20 μs for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up.
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23.2.3 ON-CHIP REGULATOR AND BOR
23.3
Watchdog Timer (WDT)
When the on-chip regulator is enabled, PIC24FJ64GA004 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage levels are specified in Section 26.1 “DC Characteristics”.
For PIC24FJ64GA004 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (Flash Configuration Word 1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed.
23.2.4
POWER-UP REQUIREMENTS
The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: For more information, see Section 26.0 “Electrical Characteristics”.
23.2.5
VOLTAGE REGULATOR STANDBY MODE
When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON). By default, this bit is cleared, which enables Standby mode. When waking up from Standby mode, the regulator will require around 190 μS to wake-up. This extra time is needed to ensure that the regulator can source enough current to power the Flash memory. For applications which require a faster wake-up time, it is possible to disable regulator Standby mode. The VREGS bit (RCON) can be set to turn off Standby mode so that the Flash stays powered when in Sleep mode and the device can wake-up in 10 μS. When VREGS is set, the power consumption while in Sleep mode, will be approximately 40 μA higher than power consumption when the regulator is allowed to enter Standby mode.
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23.3.1 WINDOWED OPERATION 23.3.2 CONTROL REGISTER
The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings.
FIGURE 23-2:
SWDTEN FWDTEN
WDT BLOCK DIAGRAM
LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS3:WDTPS0 Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep
LPRC Input
All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode
23.4
JTAG Interface
23.5.1
PIC24FJ64GA004 family devices implement a JTAG interface, which supports boundary scan device testing as well as in-circuit programming.
CONFIGURATION REGISTER PROTECTION
23.5
Program Verification and Code Protection
The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence.
For all devices in the PIC24FJ64GA004 family of devices, the on-chip program memory space is treated as a single block. Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked.
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23.6 In-Circuit Serial Programming 23.7 In-Circuit Debugger
PIC24FJ64GA004 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGCx) and data (PGDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the EMUCx (Emulation/Debug Clock) and EMUDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, PGCx, PGDx and the EMUDx/EMUCx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins.
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24.0 DEVELOPMENT SUPPORT
24.1
The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits
MPLAB Integrated Development Environment Software
The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.
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24.2 MPASM Assembler 24.5
The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process
MPLAB ASM30 Assembler, Linker and Librarian
MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility
24.6
MPLAB SIM Software Simulator
24.3
MPLAB C18 and MPLAB C30 C Compilers
The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger.
The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool.
24.4
MPLINK Object Linker/ MPLIB Object Librarian
The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction
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24.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 24.9 MPLAB ICD 2 In-Circuit Debugger
Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices.
The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application.
24.10 MPLAB PM3 Device Programmer
The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications.
24.8
MPLAB REAL ICE In-Circuit Emulator System
MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.
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24.11 PICSTART Plus Development Programmer
The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant.
24.13 Demonstration, Development and Evaluation Boards
A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits.
24.12 PICkit 2 Development Programmer
The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers.
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25.0
Note:
INSTRUCTION SET SUMMARY
This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source.
The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles.
The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations
Table 25-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 25-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple
• The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)
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TABLE 25-1:
Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address ∈ {0000h...1FFFh} 1-bit unsigned literal ∈ {0,1} 4-bit unsigned literal ∈ {0...15} 5-bit unsigned literal ∈ {0...31} 8-bit unsigned literal ∈ {0...255} 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal ∈ {0...16384} 16-bit unsigned literal ∈ {0...65535} 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal ∈ {-512...511} 16-bit signed literal ∈ {-32768...32767} 6-bit signed literal ∈ {-16...16} Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers ∈ {W0..W15} One of 16 destination working registers ∈ {W0..W15} One of 16 source working registers ∈ {W0..W15} W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] }
SYMBOLS USED IN OPCODE DESCRIPTIONS
Description
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TABLE 25-2:
Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSW BTG BTSC BSET BSET BSW.C BSW.Z BTG BTG BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4
INSTRUCTION SET OVERVIEW
Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None
1 None (2 or 3) 1 None (2 or 3)
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TABLE 25-2:
Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CLR CALL CALL CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CPB CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if ≠ Wn = Decimal Adjust Wn f = f –1 WREG = f –1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected
1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z
1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C
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TABLE 25-2:
Assembly Mnemonic GOTO INC GOTO GOTO INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP POP NOP NOPR POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None
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TABLE 25-2:
Assembly Mnemonic PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP TBLRDH SWAP.b SWAP TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog to Wd # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None
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TABLE 25-2:
Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd
INSTRUCTION SET OVERVIEW (CONTINUED)
Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N
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NOTES:
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26.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC24FJ64GA004 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ64GA004 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied.
Absolute Maximum Ratings(†)
Ambient temperature under bias.............................................................................................................-40°C to +135°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1) ................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 26-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.
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26.1 DC Characteristics
PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 26-1:
3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.25V 2.00V PIC24FJ64GA004/32GA004/64GA002/32GA002 2.35V 2.75V
16 MHz Frequency
32 MHz
For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V.
FIGURE 26-2:
PIC24FJ64GA004 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE)
3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.25V 2.00V PIC24FJ64GA004/32GA004/64GA002/32GA002 2.35V 2.75V
16 MHz Frequency
24 MHz
For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V.
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TABLE 26-1: THERMAL OPERATING CONDITIONS
Rating PIC24FJ64GA004 Family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – Σ IOH) I/O Pin Power Dissipation: PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W TJ TA -40 -40 — — +140 +125 °C °C Symbol Min Typ Max Unit
PD
PINT + PI/O
W
TABLE 26-2:
THERMAL PACKAGING CHARACTERISTICS
Characteristic Symbol θJA θJA θJA θJA Typ 49 33.7 28 39.3 Max — — — — Unit °C/W °C/W °C/W °C/W Notes (Note 1) (Note 1) (Note 1) (Note 1)
Package Thermal Resistance, 300 mil SOIC Package Thermal Resistance, 6x6x0.9 mm QFN Package Thermal Resistance, 8x8x1 mm QFN Package Thermal Resistance, 10x10x1 mm TQFP Note 1:
Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations.
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TABLE 26-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal 2.2 VDDCORE 2.0 1.5 — — — — — VSS 3.6 3.6 2.75 — — V V V V V Regulator enabled Regulator disabled Regulator disabled Characteristic
DC17
SVDD
0.05
—
—
V/ms
0-3.3V in 0.1s 0-2.5V in 60 ms
Note 1: 2:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data.
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TABLE 26-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Set(2) mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA μA μA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS 0.850 0.850 0.850 0.850 1.6 1.6 1.6 1.6 3.4 3.4 3.4 3.4 5.4 5.4 5.4 5.4 17.6 17.6 17.6 17.6 20 20 20 20 17 17 26 50 70 70 124 260 Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC20c DC20d DC20e DC20f DC20g DC23 DC23a DC23b DC23c DC23d DC23e DC23f DC23g DC24 DC24a DC24b DC24c DC24d DC24e DC24f DC24g DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g Note 1: 2: Typical(1) 0.650 0.650 0.650 0.650 1.2 1.2 1.2 1.2 2.6 2.6 2.6 2.6 4.1 4.1 4.1 4.1 13.5 13.5 13.5 13.5 15 15 15 15 13 13 20 40 54 54 95 120
Operating Current (IDD): PMD Bits are
3: 4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.
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TABLE 26-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40c DC40d DC40e DC40f DC40g DC43 DC43a DC43b DC43c DC43d DC43e DC43f DC43g DC47 DC47a DC47b DC47c DC47d DC47e DC47f DC47g DC50 DC50a DC50b DC50c DC50d DC50e DC50f DC50g Note 1: 2: Typical(1)
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2) 150 150 150 165 250 250 250 275 0.55 0.55 0.55 0.60 0.82 0.82 0.82 0.91 3 3 3 3.3 3.5 3.5 3.5 3.9 0.85 0.85 0.85 0.94 1.2 1.2 1.2 1.3 200 200 200 220 325 325 325 360 0.72 0.72 0.72 0.8 1.1 1.1 1.1 1.2 4 4 4 4.4 4.6 4.6 4.6 5.1 1.1 1.1 1.1 1.2 1.6 1.6 1.6 1.8 μA μA μA μA μA μA μA μA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V(4) 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS
3: 4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.
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TABLE 26-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC51 DC51a DC51b DC51c DC51d DC51e DC51f DC51g Note 1: 2: Typical(1)
Idle Current (IIDLE): Core Off, Clock On Base Current, PMD Bits are Set(2) 4 4 7 14 42 42 70 100 6 6 9 18 55 55 91 180 μA μA μA μA μA μA μA μA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V(4) 2.0V(3) LPRC (31 kHz)
3: 4:
Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The test conditions for all IIDLE measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.
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TABLE 26-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions
DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60j DC60c DC60d DC60e DC60k DC60f DC60g DC60h DC60l DC61 DC61a DC61b DC61j DC61c DC61d DC61e DC61k DC61f DC61g DC61h DC61l Note 1: 2: 3: 4: 5: Typical(1)
Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is ‘0’(2) 0.1 0.15 3.7 15 0.2 0.25 4.2 16 3.3 3.5 9 36 1.75 1.75 1.75 3.5 2.4 2.4 2.4 4.8 2.8 2.8 2.8 5.6 1 1 12 50 1 1 25 100 9 10 30 120 3 3 3 6 4 4 4 8 5 5 5 10 μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V(4) 2.5V(3) Watchdog Timer Current: ΔIWDT(5) 2.0V(3) 3.3V(4) 2.5V(3) Base Power-Down Current(5) 2.0V(3)
Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
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TABLE 26-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC62 DC62a DC62b DC62j DC62c DC62d DC62e DC62k DC62f DC62g DC62h DC62l Note 1: 2: 3: 4: 5: Typical(1)
Power-Down Current (IPD): PMD Bits are Set, VREGS Bit is ‘0’(2) 8 12 12 18 9 12 12.5 20 10.3 13.4 14.2 23 16 16 16 23 16 16 16 25 18 18 18 28 μA μA μA μA μA μA μA μA μA μA μA μA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V(4) 2.5V(3) RTCC + Timer1 w/32 kHz Crystal: ΔRTCC ΔITI32(5) 2.0V(3)
Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.
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TABLE 26-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial
-40°C ≤ TA ≤ +125°C for Extended
DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins PMP Pins MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I
2C™
Min
Typ(1)
Max
Units
Conditions
VSS VSS VSS VSS VSS Buffer VSS VSS
— — — — — — —
0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8
V V V V V V V SMBus disabled SMBus enabled PMPTTL = 1
I/O Pins with SMBus Buffer Input High Voltage(4) I/O Pins: with Analog Functions Digital Only PMP Pins: with Analog Functions Digital Only MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I Buffer: with Analog Functions Digital Only I/O Pins with SMBus Buffer: with Analog Functions Digital Only ICNPU CNxx Pull-up Current IIL Input Leakage Current(2,3) I/O Ports Analog Input Pins MCLR OSCI
2C
0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD
— — — — — — — — —
VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5
V V V V V V V V V PMPTTL = 1
DI21
DI25 DI26 DI27 DI28
DI29
2.1 2.1 50 — — — —
— — 250 — — — —
VDD 5.5 400 +1 +1 +1 +1
V v μA μA μA μA μA
2.5V ≤ VPIN ≤ VDD VDD = 3.3V, VPIN = VSS VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD, XT and HS modes
DI30 DI50 DI51 DI55 DI56 Note 1: 2:
3: 4:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pin buffer types.
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TABLE 26-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 DO26 Note 1:
Sym VOL
Characteristic Output Low Voltage All I/O pins All I/O pins Output High Voltage All I/O pins All I/O pins
— — — — 3 1.8 3 1.8
— — — — — — — —
0.4 0.4 0.4 0.4 — — — —
V V V V V V V V
IOL = 8.5 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.0V IOL = 8.0 mA, VDD = 3.6V, 125°C IOL = 4.5 mA, VDD = 2.0V, 125°C IOH = -3.0 mA, VDD = 3.6V IOH = -1.5 mA, VDD = 2.0V IOH = -2.5 mA, VDD = 3.6V, 125°C IOH = -1.0 mA, VDD = 2.0V, 125°C
Data in “Typ” column is at 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-9:
DC CHARACTERISTICS: PROGRAM MEMORY
Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ(1) Max Units Conditions
DC CHARACTERISTICS Param No. D130 D131 D132B D133A D134 D135 Note 1:
Sym
Characteristic Program Flash Memory
EP VPR VPEW TIW
Cell Endurance VDD for Read VDDCORE for Self-Timed Write Self-Timed Write Cycle Time
10000 VMIN 2.25 — 20 —
— — — 3 — 7
— 3.6 2.75 — — —
E/W V V ms Year mA
-40°C to +125°C VMIN = Minimum operating voltage
TRETD Characteristic Retention IDDP Supply Current during Programming
Provided no other specifications are violated
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
TABLE 26-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS
Operating Conditions: -40°C < TA < +125°C (unless otherwise stated) Param No. Symbol VRGOUT CEFC Characteristics Regulator Output Voltage External Filter Capacitor Value Min — 4.7 Typ 2.5 10 Max — — Units V μF Series resistance < 3 Ohm recommended; < 5 Ohm required. DISVREG = VSS DISVREG = VDD Comments
TVREG TPWRT
— —
10 64
— —
μs ms
© 2008 Microchip Technology Inc.
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26.2 AC Characteristics and Timing Parameters
The information contained in this section defines the PIC24FJ64GA004 family AC characteristics and timing parameters.
TABLE 26-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC
AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Section 26.1 “DC Characteristics”.
FIGURE 26-3:
LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS
Load Condition 2 – for OSCO
Load Condition 1 – for all pins except OSCO VDD/2 RL
Pin VSS
CL
Pin VSS
CL
RL = 464Ω CL = 50 pF for all pins except OSCO 15 pF for OSCO output
TABLE 26-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS
Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI. EC mode. In I2C™ mode.
DO56 DO58 Note 1:
CIO CB
All I/O Pins and OSCO SCLx, SDAx
— —
— —
50 400
pF pF
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
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FIGURE 26-4:
Q4
EXTERNAL CLOCK TIMING
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3
OSCI
OS20 OS25 OS30 OS30 OS31 OS31
CLKO
OS40 OS41
TABLE 26-13: EXTERNAL CLOCK TIMING REQUIREMENTS
AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.0 to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min DC 4 DC 4 3 3 10 31 3 10 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — — — — — 6 6 Max 32 8 24 6 10 8 32 33 6 24 — DC — 20 10 10 Units MHz MHz MHz MHz MHz MHz MHz kHz MHz MHz — ns ns ns ns ns EC EC Conditions EC, -40°C ≤ TA ≤ +85°C ECPLL, -40°C ≤ TA ≤ +85°C EC, -40°C ≤ TA ≤ +125°C ECPLL, -40°C ≤ TA ≤ +125°C XT XTPLL, -40°C ≤ TA ≤ +85°C HS, -40°C ≤ TA ≤ +85°C SOSC XTPLL, -40°C ≤ TA ≤ +125°C HS, -40°C ≤ TA ≤ +125°C See parameter OS10 for FOSC value
FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency
OS20 OS25 OS30 OS31 OS40 OS41
TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2)
TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3)
Note 1: 2:
3:
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY).
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TABLE 26-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V)
AC CHARACTERISTICS Param No. OS50 Sym FPLLI Characteristic(1) PLL Input Frequency Range Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min 3 3 OS51 OS52 OS53 Note 1: 2: FSYS PLL Output Frequency Range 8 8 — -2 Typ(2) — — — — — 1 Max 8 6 32 24 2 2 Units MHz MHz MHz MHz ms % Measured over 100 ms period Conditions ECPLL, HSPLL, XTPLL modes, -40°C ≤ TA ≤ +85°C ECPLL, HSPLL, XTPLL modes, -40°C ≤ TA ≤ +125°C -40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +125°C
TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter)
These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.
TABLE 26-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F20 Note 1: FRC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions
Characteristic
Internal FRC Accuracy @ 8 MHz(1) -2 -5 — — 2 5 % % 25°C -40°C ≤ TA ≤ +125°C 3.0V ≤ VDD ≤ 3.6V
Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift.
TABLE 26-16: INTERNAL RC ACCURACY
AC CHARACTERISTICS Param No. F21 Characteristic LPRC @ 31 kHz(1) -15 -15 -20 Note 1: — — — 15 15 20 % % % 25°C -40°C ≤ TA ≤ +85°C 125°C 3.0V ≤ VDD ≤ 3.6V Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions
Change of LPRC frequency as VDD changes.
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FIGURE 26-5: CLKO AND I/O TIMING CHARACTERISTICS
I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 26-3 for load conditions. New Value
TABLE 26-17: CLKO AND I/O TIMING REQUIREMENTS
AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions
Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.
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TABLE 26-18: ADC MODULE SPECIFICATIONS
AC CHARACTERISTICS Param No. AD01 Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min. Typ Max. Units Conditions
Symbol
Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 V
AD02 AD05 AD06 AD07
AVSS VREFH VREFL VREF
Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage
— — — —
V V V V
Reference Inputs
Analog Input AD10 AD11 AD12 AD17 VINH-VINL Full-Scale Input Span VIN VINL RIN Absolute Input Voltage Absolute VINL Input Voltage Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) VREFL AVSS – 0.3 AVSS – 0.3 — — — — VREFH AVDD + 0.3 AVDD/2 2.5K V V V Ω 10-bit (Note 2) —
ADC Accuracy AD20b Nr AD21b INL AD22b DNL AD23b GERR AD24b EOFF AD25b — Note 1: 2: — — — — — — 10 ±1 ±1 ±1 ±1 — — 4)1@ ZLWK PP &RQWDFW /HQJWK
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APPENDIX A: REVISION HISTORY
Revision A (March 2007)
Original data sheet for the PIC24FJ64GA004 family of devices.
Revision B (March 2007)
Changes to Table 26-8; packaging diagrams updated.
Revision C (January 2008)
• Update of electrical specifications to include DC characteristics for Extended Temperature devices. • Update for A/D converter chapter to include information on internal band gap voltage reference. • Added “Appendix B: “Additional Guidance for PIC24FJ64GA004 Family Applications”. • General revisions to incorporate corrections included in document errata to date (DS80333).
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APPENDIX B: ADDITIONAL GUIDANCE FOR PIC24FJ64GA004 FAMILY APPLICATIONS
FIGURE B-1: POWER REDUCTION EXAMPLE FOR CONSTANT VOLTAGE SUPPLIES
PIC24FJ64GA VDD
B.1
Additional Methods for Power Reduction
DISVREG 3.0V Coin Cell D1 2.3V VDDCORE VSS
Devices in the PIC24FJ64GA004 family include a number of core features to significantly reduce the application’s power requirements. For truly power-sensitive applications, it is possible to further reduce the application’s power demands by taking advantage of the device’s regulator architecture. These methods help decrease power in two ways: by disabling the internal voltage regulator to eliminate its power consumption, and by reducing the voltage on VDDCORE to lower the device’s dynamic current requirements. Using these methods, it is possible to reduce Sleep currents (IPD) from 3.5 μA to 250 nA (typical values, refer to specifications DC60d and DC60g in Table 26-6). For dynamic power consumption, the reduction in VDDCORE from 2.5V, provided by the regulator, to 2.0V can provide a power reduction of about 30%. When using a regulated power source or a battery with a constant output voltage, it is possible to decrease power consumption by disabling the regulator. In this case (Figure B-1), a simple diode can be used to reduce the voltage from 3V or greater to the 2V-2.5V required for VDDCORE. This method is only advised on power supplies, such as Lithium Coin cells, which maintain a constant voltage over the life of the battery.
A similar method can be used for non-regulated sources (Figure B-2). In this case, it can be beneficial to use a low quiescent current external voltage regulator. Devices such as the MCP1700 consume only 1 μA to regulate to 2V or 2.5V, which is lower than the current required to power the internal voltage regulator.
FIGURE B-2:
POWER REDUCTION EXAMPLE FOR NON-REGULATED SUPPLIES
PIC24FJ64GA VDD DISVREG 3.3V ‘AA’ MCP1700 2.0V VDDCORE VSS
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INDEX
A
A/D Converter Analog Input Model ................................................... 190 Transfer Function...................................................... 191 Additional Guidance for Family Applications..................... 252 Assembler MPASM Assembler................................................... 210 Code Examples Basic Clock Switching Example ................................. 93 Configuring UART 1 Input and Output Functions (PPS) ............................................... 102 Erasing a Program Memory Block.............................. 44 I/O Port Read/Write .................................................... 98 Initiating a Programming Sequence ........................... 45 Loading the Write Buffers ........................................... 45 Single-Word Flash Programming ............................... 46 Code Protection ................................................................ 206 Configuration Bits ............................................................. 199 Core Features....................................................................... 7 CPU ALU............................................................................. 21 Control Registers........................................................ 20 Core Registers............................................................ 19 Programmer’s Model .................................................. 17 CRC CRCXOR Register.................................................... 182 Operation in Power Save Modes.............................. 180 User Interface ........................................................... 180 Customer Change Notification Service............................. 256 Customer Notification Service .......................................... 256 Customer Support............................................................. 256
B
Block Diagrams 10-Bit High-Speed A/D Converter............................. 184 Accessing Program Memory with Table Instructions .. 39 Addressable PMP Example ...................................... 166 CALL Stack Frame...................................................... 37 Comparator Operating Modes .................................. 193 Comparator Voltage Reference ................................ 197 CPU Programmer’s Model .......................................... 19 CRC Reconfigured for Polynomial ............................ 180 CRC Shifter Details................................................... 179 Data Access From Program Space Address Generation ............................................ 38 I2C Module ................................................................ 144 Input Capture ............................................................ 125 Legacy PMP Example............................................... 166 On-Chip Regulator Connections ............................... 204 Output Compare ....................................................... 130 PIC24F CPU Core ...................................................... 18 PIC24FJ64GA004 Family (General) ........................... 10 PMP Master Port Examples .............................. 166–168 PMP Module Overview ............................................. 159 PSV Operation ............................................................ 40 Reset System.............................................................. 47 RTCC ........................................................................ 169 Shared I/O Port Structure ........................................... 97 Simplified UART........................................................ 151 SPI Master/Frame Master Connection...................... 141 SPI Master/Frame Slave Connection........................ 141 SPI Master/Slave Connection (Enhanced Buffer Mode)................................... 140 SPI Master/Slave Connection (Standard Mode) ............................................... 140 SPI Slave/Frame Master Connection........................ 141 SPI Slave/Frame Slave Connection.......................... 141 SPIx Module (Enhanced Mode) ................................ 135 SPIx Module (Standard Mode).................................. 134 System Clock Diagram ............................................... 87 Timer1....................................................................... 117 Timer2 and Timer4 (16-Bit Modes) ........................... 121 Timer2/3 and Timer4/5 (32-Bit Mode)....................... 120 Timer3 and Timer5 (16-Bit Modes) ........................... 121 Watchdog Timer (WDT) ............................................ 206
D
Data Memory Address Space ........................................................... 25 Memory Map............................................................... 25 Near Data Space ........................................................ 26 Organization ............................................................... 26 SFR Space ................................................................. 26 Software Stack ........................................................... 37 Development Support ....................................................... 209 Device Features (Summary)................................................. 9 DISVREG Pin ................................................................... 204 Doze Mode ......................................................................... 96
E
Electrical Characteristics A/D Specifications .................................................... 236 Absolute Maximum Ratings ...................................... 221 Current Specifications ...................................... 225–229 I/O Pin Specifications ....................................... 230–231 Internal Clock Specifications .................................... 234 Load Conditions and Requirements for AC Characteristics............................................ 232 Program Memory Specifications............................... 231 Thermal Operating Conditions.................................. 223 V/F Graphs ............................................................... 222 Voltage Ratings ........................................................ 224 Voltage Regulator Specifications.............................. 231 Equations A/D Clock Conversion Period ................................... 190 Baud Rate Reload Calculation ................................. 145 Calculating the PWM Period..................................... 128 Calculation for Maximum PWM Resolution .............. 128 Device and SPI Clock Speed Relationship............... 142 UART Baud Rate with BRGH = 0 ............................. 152 UART Baud Rate with BRGH = 1 ............................. 152 Errata .................................................................................... 6
C
C Compilers MPLAB C18 .............................................................. 210 MPLAB C30 .............................................................. 210
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F
Flash Configuration Words.................................. 24, 199–202 Flash Program Memory and Table Instructions................................................. 41 Enhanced ICSP Operation.......................................... 42 JTAG Operation .......................................................... 42 Programming Algorithm .............................................. 44 RTSP Operation.......................................................... 42 Single-Word Programming.......................................... 46 Output Compare PWM Mode ............................................................... 128 Period and Duty Cycle Calculation ................... 129 Single Output Pulse Generation ............................... 127
P
Packaging Details....................................................................... 241 Marking ..................................................................... 239 Parallel Master Port. See PMP. ........................................ 159 Peripheral Enable Bits ........................................................ 96 Peripheral Module Disable (PMD) bits................................ 96 Peripheral Pin Select (PPS)................................................ 99 Available Peripherals and Pins ................................... 99 Configuration Control................................................ 101 Considerations for Use ............................................. 102 Input Mapping ............................................................. 99 Mapping Exceptions ................................................. 101 Output Mapping ........................................................ 100 Peripheral Priority ....................................................... 99 Registers .......................................................... 103–116 PICSTART Plus Development Programmer..................... 212 Pinout Descriptions....................................................... 11–16 PMP Master Port Examples ...................................... 166–168 Power-Saving Features ...................................................... 95 Power-up Requirements ................................................... 205 Product Identification System ........................................... 258 Program Memory Access Using Table Instructions................................. 39 Address Construction ................................................. 37 Address Space ........................................................... 23 Flash Configuration Words ......................................... 24 Memory Map............................................................... 23 Organization ............................................................... 24 Program Space Visibility............................................. 40 Pulse-Width Modulation. See PWM.................................. 128
I
I/O Ports Analog Port Configuration ........................................... 98 Input Change Notification............................................ 98 Open-Drain Configuration ........................................... 98 Parallel (PIO) .............................................................. 97 Peripheral Pin Select .................................................. 99 Pull-ups ....................................................................... 98 I2C Clock Rates............................................................... 145 Peripheral Remapping Options ................................. 143 Reserved Addresses................................................. 145 Slave Address Masking ............................................ 145 Idle Mode ............................................................................ 96 Instruction Set Overview ................................................................... 215 Summary................................................................... 213 Instruction-Based Power-Saving Modes ............................. 95 Inter-Integrated Circuit. See I2C........................................ 143 Internet Address................................................................ 256 Interrupts Alternate Interrupt Vector Table (AIVT) ...................... 53 and Reset Sequence .................................................. 53 Implemented Vectors .................................................. 55 Interrupt Vector Table (IVT) ........................................ 53 Registers ............................................................... 56–84 Setup and Service Procedures ................................... 85 Trap Vectors ............................................................... 54 Vector Table................................................................ 54
R
Reader Response............................................................. 257 Register Maps A/D Converter (ADC) .................................................. 33 Clock Control .............................................................. 36 CPU ............................................................................ 27 CRC ............................................................................ 34 Dual Comparator ........................................................ 34 I2C .............................................................................. 30 ICN ............................................................................. 27 Input Capture .............................................................. 29 Interrupt Controller...................................................... 28 NVM............................................................................ 36 Output Compare ......................................................... 30 Pad Configuration ....................................................... 32 Parallel Master/Slave Port .......................................... 33 Peripheral Pin Select .................................................. 35 PMD............................................................................ 36 PORTA ....................................................................... 32 PORTB ....................................................................... 32 PORTC ....................................................................... 32 Real-Time Clock and Calendar (RTCC) ..................... 34 SPI .............................................................................. 31 Timers......................................................................... 29 UART .......................................................................... 31
J
JTAG Interface .................................................................. 206
M
Microchip Internet Web Site .............................................. 256 MPLAB ASM30 Assembler, Linker, Librarian ................... 210 MPLAB ICD 2 In-Circuit Debugger.................................... 211 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................... 211 MPLAB Integrated Development Environment Software............................................... 209 MPLAB PM3 Device Programmer..................................... 211 MPLAB REAL ICE In-Circuit Emulator System................. 211 MPLINK Object Linker/MPLIB Object Librarian ................ 210
N
Near Data Space................................................................. 26
O
Oscillator Configuration Clock Switching........................................................... 92 Sequence............................................................ 93 Initial Configuration on POR ....................................... 88 Oscillator Modes ......................................................... 88
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Registers AD1CHS (A/D Input Select) ...................................... 188 AD1CON1 (A/D Control 1) ........................................ 185 AD1CON2 (A/D Control 2) ........................................ 186 AD1CON3 (A/D Control 3) ........................................ 187 AD1CSSL (A/D Input Scan Select) ........................... 189 AD1PCFG (A/D Port Configuration).......................... 189 ALCFGRPT (Alarm Configuration)............................ 173 ALMINSEC (Alarm Minutes and Seconds Value) ................................................ 177 ALMTHDY (Alarm Month and Day Value) ................ 176 ALWDHR (Alarm Weekday and Hours Value).......... 176 CLKDIV (Clock Divider) .............................................. 91 CMCON (Comparator Control) ................................. 194 CORCON (Core Control) ............................................ 57 CORCON (CPU Control) ............................................ 21 CRCCON (CRC Control) .......................................... 181 CRCXOR (CRC XOR Polynomial)............................ 182 CVRCON (Comparator Voltage Reference Control) ........................................... 198 CW1 (Flash Configuration Word 1)........................... 200 CW2 (Flash Configuration Word 2)........................... 202 DEVID (Device ID) .................................................... 203 DEVREV (Device Revision) ...................................... 203 I2CxCON (I2Cx Control) ........................................... 146 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 150 I2CxSTAT (I2Cx Status) ........................................... 148 ICxCON (Input Capture x Control) ............................ 126 IECn (Interrupt Enable Control 0-4) ...................... 65–69 IFSn (Interrupt Flag Status 0-4) ............................ 60–64 INTCON1 (Interrupt Control 1).................................... 58 INTCON2 (Interrupt Control 2).................................... 59 IPCn (Interrupt Priority Control 0-18) .................... 70–84 MINSEC (RTCC Minutes and Seconds Value)......... 175 MTHDY (RTCC Month and Day Value) .................... 174 NVMCON (Flash Memory Control) ............................. 43 OCxCON (Output Compare x Control) ..................... 131 OSCCON (Oscillator Control) ..................................... 89 OSCTUN (FRC Oscillator Tune)................................. 92 PADCFG1 (Pad Configuration Control) ............ 165, 172 PMADDR (PMP Address) ......................................... 163 PMAEN (PMP Enable).............................................. 163 PMCON (PMP Control)............................................. 160 PMMODE (PMP Mode)............................................. 162 PMPSTAT (PMP Status)........................................... 164 RCFGCAL (RTCC Calibration and Configuration) ................................................... 171 RCON (Reset Control) ................................................ 48 RPINRn (PPS Input Mapping 0-23) .................. 103–109 RPORn (PPS Output Mapping 0-12) ................ 110–116 SPIxCON1 (SPIx Control 1)...................................... 138 SPIxCON2 (SPIx Control 2)...................................... 139 SPIxSTAT (SPIx Status and Control) ....................... 136 SR (ALU STATUS) ............................................... 20, 57 T1CON (Timer1 Control)........................................... 118 TxCON (Timer2 and Timer4 Control)........................ 122 TyCON (Timer3 and Timer5 Control)........................ 123 UxMODE (UARTx Mode).......................................... 154 UxRXREG (UARTx Receive).................................... 158 UxSTA (UARTx Status and Control)......................... 156 UxTXREG (UARTx Transmit) ................................... 158 WKDYHR (RTCC Weekday and Hours Value) ..................................................... 175 YEAR (RTCC Year Value) ........................................ 174 Resets Clock Source Selection .............................................. 49 Delay Times................................................................ 50 RCON Flags Operation .............................................. 49 SFR States ................................................................. 51 Revision History................................................................ 251 RTCC Alarm Configuration.................................................. 178 Calibration ................................................................ 177 Register Mapping ..................................................... 170
S
Serial Peripheral Interface. See SPI. ................................ 133 SFR Space ......................................................................... 26 Selective Peripheral Power Control .................................... 96 Sleep Mode ........................................................................ 95 Software Simulator (MPLAB SIM) .................................... 210 Software Stack ................................................................... 37
T
Timer1 .............................................................................. 117 Timer2/3 and Timer4/5 ..................................................... 119 Timing Diagrams CLKO and I/O Timing ............................................... 235 External Clock Timing............................................... 233
U
UART Baud Rate Generator (BRG) .................................... 152 Break and Sync Sequence ....................................... 153 IrDA Support ............................................................. 153 Operation of UxCTS and UxRTS Control Pins ...................................................... 153 Receiving.................................................................. 153 Transmitting.............................................................. 153
V
VDDCORE/VCAP pin............................................................ 204 Voltage Regulator (On-Chip) ............................................ 204 and BOR................................................................... 205 and POR................................................................... 204 Standby Mode .......................................................... 205 Tracking Mode.......................................................... 204
W
Watchdog Timer (WDT).................................................... 205 Windowed Operation ................................................ 206 WWW Address ................................................................. 256 WWW, On-Line Support ....................................................... 6
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THE MICROCHIP WEB SITE
Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
CUSTOMER SUPPORT
Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line
Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com
CUSTOMER CHANGE NOTIFICATION SERVICE
Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.
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READER RESPONSE
It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________
From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39881C FAX: (______) _________ - _________
Device: PIC24FJ64GA004 Family Questions:
1. What are the best features of this document?
2. How does this document meet your hardware and software development needs?
3. Do you find the organization of this document easy to follow? If not, why?
4. What additions to the document do you think would enhance the structure and subject?
5. What deletions from the document could be made without affecting the overall usefulness?
6. Is there any incorrect or misleading information (what and where)?
7. How would you improve this document?
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PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 64 GA0 04 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern
b)
Examples:
a) PIC24FJ32GA002-I/ML: General purpose PIC24F, 32-Kbyte program memory, 28-pin, Industrial temp., QFN package. PIC24FJ64GA004-E/PT: General purpose PIC24F, 64-Kbyte program memory, 44-pin, Extended temp., TQFP package.
Architecture Flash Memory Family Product Group Pin Count
24 FJ
= 16-bit modified Harvard without DSP = Flash program memory
GA0 = General purpose microcontrollers 02 04 E I SP SO SS ML PT = 28-pin = 44-pin = -40°C to +125°C (Extended) = -40°C to +85°C (Industrial) = = = = = SPDIP SOIC SSOP QFN TQFP
Temperature Range
Package
Pattern
Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample
© 2008 Microchip Technology Inc.
Preliminary
DS39881C-page 259
WORLDWIDE SALES AND SERVICE
AMERICAS
Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509
ASIA/PACIFIC
Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350
EUROPE
Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820
01/02/08
DS39881C-page 260
Preliminary
© 2008 Microchip Technology Inc.
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