PIC24FJ256DA106

PIC24FJ256DA210 Family Data Sheet 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG)  2010 Microchip Technology Inc. DS39969B Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-235-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39969B-page 2  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 64/100-Pin, 16-Bit Flash Microcontrollers with Graphics Controller and USB On-The-Go (OTG) Graphics Controller Features: • Three Graphics Hardware Accelerators to Facilitate Rendering of Block Copying, Text and Unpacking of Compressed Data • Color Look-up Table (CLUT) with Maximum of 256 Entries • 1/2/4/8/16 bits-per-pixel (bpp) Color Depth Set at Run Time • Display Resolution Programmable According to Frame Buffer: - Supports direct access to external memory on devices with EPMP Peripheral Features: • Enhanced Parallel Master Port/Parallel Slave Port (EPMP/PSP), 100-pin devices only: - Direct access from CPU with an Extended Data Space (EDS) interface - 4, 8 and 16-bit wide data bus - Up to 23 programmable address lines - Up to 2 chip select lines - Up to 2 Acknowledgement lines (one per chip select) - Programmable address/data multiplexing - Programmable address and data Wait states - Programmable polarity on control signals • Peripheral Pin Select: - Up to 44 available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) • Three I2C™ modules Supporting Multi-Master/Slave modes and 7-Bit/10-Bit Addressing • Four UART modules: - Supports RS-485, RS-232, LIN/J2602 protocols and IrDA® • Five 16-Bit Timers/Counters with Programmable Prescaler • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • Hardware Real-Time Clock and Calendar (RTCC) • Enhanced Programmable Cyclic Redundancy Check (CRC) Generator • Up to 5 External Interrupt Sources - Resolution supported is up to 480x272 @ 60 Hz, 16 bpp; 640x480 @ 30 Hz, 16 bpp or 640x480 @ 60 Hz, 8 bpp • Supports Various Display Interfaces: - 4/8/16-bit Monochrome STN - 4/8/16-bit Color STN - 9/12/18/24-bit Color TFT (18 and 24-bit displays are connected as 16-bit, 5-6-5 RGB color format) Universal Serial Bus Features: • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – Can act as either Host or Peripheral • Low-Speed (1.5 Mbps) and Full-Speed (12 Mbps) USB Operation in Host mode • Full-Speed USB Operation in Device mode • High-Precision PLL for USB • Supports up to 32 Endpoints (16 bidirectional): - USB module can use the internal RAM location from 0x800 to 0xFFFF as USB endpoint buffers • On-Chip USB Transceiver with Interface for Off-Chip Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Program Memory (bytes) Graphics Controller Y Y Y Y Y Y Y Y Remappable Peripherals 10-Bit A/D (ch) SRAM (bytes) Comparators UART w/IrDA® EPMP/PSP 16-Bit Timers Remappable Pins IC/OC PWM PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA206 PIC24FJ256DA206 PIC24FJ128DA210 PIC24FJ256DA210 64 64 100/121 100/121 64 64 100/121 100/121 128K 256K 128K 256K 128K 256K 128K 256K 24K 24K 24K 24K 96K 96K 96K 96K 29 29 44 44 29 29 44 44 5 5 5 5 5 5 5 5 9/9 9/9 9/9 9/9 9/9 9/9 9/9 9/9 4 4 4 4 4 4 4 4 SPI PIC24FJ Device 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 24 24 16 16 24 24 3 3 3 3 3 3 3 3 Y Y Y Y Y Y Y Y N N Y Y N N Y Y Y Y Y Y Y Y Y Y  2010 Microchip Technology Inc. DS39969B-page 3 USB OTG Y Y Y Y Y Y Y Y CTMU RTCC I2C™ Pins PIC24FJ256DA210 FAMILY High-Performance CPU Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • Linear Program Memory Addressing, up to 12 Mbytes • Data Memory Addressing, up to 16 Mbytes: - 2K SFR space - 30K linear data memory - 66K extended data memory - Remaining (from 16 Mbytes) memory (external) can be accessed using extended data Memory (EDS) and EPMP (EDS is divided into 32-Kbyte pages) • Two Address Generation Units for Separate Read and Write Addressing of Data Memory • • • • • • • Analog Features: • 10-Bit, up to 24-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Operation is possible in Sleep mode - Band gap reference input feature • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Minimum time measurement setting at 100 ps • Available LVD Interrupt VLVD Level Special Microcontroller Features: • Operating Voltage Range of 2.2V to 3.6V • 5.5V Tolerant Input (digital pins only) • Configurable Open-Drain Outputs on Digital I/O Ports • High-Current Sink/Source (18 mA/18 mA) on all I/O Ports • Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up • Fail-Safe Clock Monitor (FSCM) Operation: - Detects clock failure and switches to on-chip, FRC oscillator • On-Chip LDO Regulator • Power-on Reset (POR) and Oscillator Start-up Timer (OST) • Brown-out Reset (BOR) • Flexible Watchdog Timer (WDT) with On-Chip Low-Power RC Oscillator for Reliable Operation • In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins • JTAG Boundary Scan Support • Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Self-reprogrammable under software control - Write protection option for Configuration Words Power Management: • On-Chip Voltage Regulator of 1.8V • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run Mode: 800 A/MIPS, 3.3V Typical • Sleep mode Current Down to 20 A, 3.3V Typical • Standby Current with 32 kHz Oscillator: 22 A, 3.3V Typical DS39969B-page 4  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin Diagram (64-Pin TQFP/QFN) HSYNC/CN62/RE4 GD3/CN61/RE3 GD2/CN60/RE2 GD1/CN59/RE1 GD0/CN58/RE0 GD11/VCMPST2/SESSVLD/CN69/RF1 GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0 ENVREG VCAP C3INA/SESSEND/CN16/RD7 C3INB/CN15/RD6 RP20/GPWR/CN14/RD5 RP25/GCLK/CN13/RD4 RP22/GEN/CN52/RD3 DPH/RP23/CN51/RD2 VCPCON/RP24/GD9/VBUSCHG/CN50/RD1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 VSYNC/CN63/RE5 GD12/SCL3/CN64/RE6 GD13/SDA3/CN65/RE7 C1IND/RP21/CN8/RG6 C1INC/RP26/CN9/RG7 C2IND/RP19/GD14/CN10/RG8 MCLR C2INC/RP27/GD15/CN11/RG9 VSS(1) VDD PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/ RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/GD7/CN56/RD11 SCL1/RP3/GD6/CN55/RD10 DPLN/SDA1/RP4/GD8/CN54/RD9 RTCC/DMLN/RP2/CN53/RD8 VSS(1) OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/CN83/RG2 D-/CN84/RG3 VUSB VBUS/RF7 RP16/USBID/CN71/RF3 PIC24FJXXXDAX06 Note 1: Legend: The back pad on QFN devices should be connected to VSS. RPn and RPIn represents remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 TMS/CVREF/AN10/CN28/RB10 TDO/AN11/CN29/RB11 VSS(1) VDD TCK/AN12/CTEDG2/CN30/RB12 TDI/AN13CTEDG1/CN31/RB13 AN14/CTPLS/RP14/CN32/RB14 AN15/RP29/REFO/CN12/RB15 SDA2/RP10/GD4/CN17/GD4/RF4 SCL2/RP17/GD5/CN18/RF5 DS39969B-page 5 PIC24FJ256DA210 FAMILY TABLE 1: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Legend: VSYNC/CN63/RE5 GD12/SCL3/CN64/RE6 GD13/SDA3/CN65/RE7 C1IND/RP21/CN8/RG6 C1INC/RP26/CN9/RG7 C2IND/RP19/GD14/CN10/RG8 MCLR C2INC/RP27/GD15/CN11/RG9 VSS VDD PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/CN6/RB4 AN3/C2INA/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/CN25/RB7 AVDD AVSS AN8/RP8/CN26/RB8 AN9/RP9/CN27/RB9 TMS/CVREF/AN10/CN28/RB10 TDO/AN11/CN29/RB11 VSS VDD TCK/AN12/CTEDG2/CN30/RB12 TDI/AN13/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/CN32/RB14 AN15/RP29/REFO/CN12/RB15 SDA2/RP10/GD4/CN17/RF4 SCL2/RP17/GD5/CN18/RF5 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 64-PIN DEVICES Function Pin 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 RP16/USBID/CN71/RF3 VBUS/RF7 VUSB D-/CN84/RG3 D+/CN83/RG2 VDD OSCI/CLKI/CN23/RC12 OSCO/CLKO/CN22/RC15 VSS RTCC/DMLN/RP2/CN53/RD8 DPLN/SDA1/RP4/GD8/CN54/RD9 SCL1/RP3/GD6/CN55/RD10 RP12/GD7/CN56/RD11 DMH/RP11/INT0/CN49/RD0 SOSCI/C3IND/CN1/RC13 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 VCPCON/RP24/GD9/VBUSCHG/CN50/RD1 DPH/RP23/CN51/RD2 RP22/GEN/CN52/RD3 RP25/GCLK/CN13/RD4 RP20/GPWR/CN14/RD5 C3INB/CN15/RD6 C3INA/SESSEND/CN16/RD7 VCAP ENVREG GD10/VBUSST/VCMPST1/VBUSVLD/CN68/RF0 GD11/VCMPST2/SESSVLD/CN69/RF1 GD0/CN58/RE0 GD1/CN59/RE1 GD2/CN60/RE2 GD3/CN61/RE3 HSYNC/CN62/RE4 Function RPn and RPIn represent remappable pins for Peripheral Pin Select functions. DS39969B-page 6  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Pin Diagram (100-Pin TQFP) PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 HSYNC/CN80/RG13 VSYNC/CN79/RG12 PMA16/CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 AN22/PMA17/CN40/RA7 AN23/GEN/CN39/RA6 PMD8/CN77/RG0 PMD9/CN78/RG1 VCMPST2/SESSVLD/PMD10/CN69/RF1 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 ENVREG VCAP C3INA/SESSEND/PMD15/CN16/RD7 C3INB/PMD14/CN15/RD6 RP20/PMRD/CN14/RD5 RP25/PMWR/CN13/RD4 PMD13/CN19/RD13 RPI42/PMD12/CN57/RD12 RP22/PMBE0/CN52/RD3 DPH/RP23/GD11/PMACK1/CN51/RD2 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 GCLK/CN82/RG15 VDD PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 RPI38/GD0/CN45/RC1 RPI39/GD8/CN46/RC2 RPI40/GD1/CN47/RC3 AN16/RPI41/PMCS2/PMA22/CN48/RC4 AN17/C1IND/RP21/PMA5/PMA18/CN8/ RG6 AN18/C1INC/RP26/PMA4/PMA20/CN9/RG7 AN19/C2IND/RP19/PMA3/PMA21/CN10/RG8 MCLR AN20/C2INC/RP27/PMA2/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGEC1/AN1/VREF-/RP1/CN3/RB1 PGED1/AN0/VREF+/RP0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 PIC24FJXXXDAX10 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/SCLKI/TICK/C3INC/ RPI37/CN0/RC14 SOSCI/C3IND/CN1/RC13 DMH/RP11/INT0/CN49/RD0 RP12/PMA14/PMCS1/CN56/RD11 RP3/PMA15/PMCS2/CN55/ RD10 DPLN/RP4/GD10/PMACK2/CN54/ RD9 DMLN/RTCC/RP2/CN53/RD8 SDA1/RPI35/PMBE1/CN44/ RA15 SCL1/RPI36/ PMA22/PMCS2/ CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD TDO/CN38/RA5 TDI/PMA21/PMA3/CN37/RA4 SDA2/PMA20/PMA4/CN36/RA3 SCL2/CN35/RA2 D+/CN83/RG2 D-/CN84/RG3 VUSB VBUS/CN73/RF7 RP15/GD9/CN74/RF8 RP30/GD3/CN70/RF2 RP16/USBID/CN71/RF3 AVDD AVSS AN8/RP8/GD12/CN26/RB8 GD13/AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/GD2/CN76/RF13 RPI32/PMA18/PMA5/CN75/RF12 AN12/PMA11/CTEDG2/CN30/RB12 AN13/PMA10/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 Legend: RPn and RPIn represent remappable peripheral pins. Shaded pins indicate pins that are tolerant to up to +5.5V.  2010 Microchip Technology Inc. PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 VSS VDD RPI43/GD14/CN20/RD14 RP5/GD15/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS39969B-page 7 PIC24FJ256DA210 FAMILY TABLE 2: Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Legend: Note 1: 2: 3: GCLK/CN82/RG15 VDD PMD5/CN63/RE5 SCL3/PMD6/CN64/RE6 SDA3/PMD7/CN65/RE7 RPI38/GD0/CN45/RC1 RPI39/GD8/CN46/RC2 RPI40/GD1/CN47/RC3 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 MCLR AN20/C2INC/RP27/PMA2/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 PGEC2/AN6/RP6/CN24/RB6 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 VREF-/PMA7/CN41/RA9 VREF+/PMA6/CN42/RA10 AVDD AVSS AN8/RP8/GD12/CN26/RB8 AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/GD2/CN76/RF13 RPI32/PMA18/PMA5(2)/CN75/RF12 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Function Pin 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Function AN12/PMA11/CTEDG2/CN30/RB12 AN13/PMA10/CTEDG1/CN31/RB13 AN14/CTPLS/RP14/PMA1/CN32/RB14 AN15/REFO/RP29/PMA0/CN12/RB15 VSS VDD RPI43/GD14/CN20/RD14 RP5/GD15/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 RP16/USBID/CN71/RF3 RP30/GD3/CN70/RF2 RP15/GD9/CN74/RF8 VBUS/CN73/RF7 VUSB D-/CN84/RG3 D+/CN83/RG2 SCL2/CN35/RA2 SDA2/PMA20/PMA4(2)/CN36/RA3 TDI/PMA21/PMA3(2)/CN37/RA4 TDO/CN38/RA5 VDD OSCI/CLKI/CN23/RC12 OSCO/CLKO/CN22/RC15 VSS SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 SDA1/RPI35/PMBE1/CN44/RA15 DMLN/RTCC/RP2/CN53/RD8 DPLN/RP4/GD10/PMACK2/CN54/RD9 RP3/PMA15/PMCS2(3)/CN55/RD10 RP12/PMA14/PMCS1(3)/CN56/RD11 DMH/RP11/INT0/CN49/RD0 SOSCI/C3IND/CN1/RC13 SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 VSS VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 DPH/RP23/GD11/PMACK1/CN51/RD2 RP22/PMBE0/CN52/RD3 RPI42/PMD12/CN57/RD12 PMD13/CN19/RD13 RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF is not equal to ‘00’. DS39969B-page 8  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 2: Pin 81 82 83 84 85 86 87 88 89 90 Legend: Note 1: 2: 3: RP25/PMWR/CN13/RD4 RP20/PMRD/CN14/RD5 C3INB/PMD14/CN15/RD6 C3INA/SESSEND/PMD15/CN16/RD7 VCAP ENVREG VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 VCMPST2/SESSVLD/PMD10/CN69/RF1 PMD9/CN78/RG1 PMD8/CN77/RG0 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 100-PIN DEVICES Function Pin 91 92 93 94 95 96 97 98 99 100 AN23/GEN/CN39/RA6 AN22/PMA17/CN40/RA7 PMD0/CN58/RE0 PMD1/CN59/RE1 PMA16/CN81/RG14 VSYNC/CN79/RG12 HSYNC/CN80/RG13 PMD2/CN60/RE2 PMD3/CN61/RE3 PMD4/CN62/RE4 Function RPn and RPIn represent remappable pins for Peripheral Pin Select (PPS) functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF is not equal to ‘00’.  2010 Microchip Technology Inc. DS39969B-page 9 PIC24FJ256DA210 FAMILY Pin Diagram – Top View (121-Pin BGA)(1) 1 2 3 4 5 6 7 8 9 10 11 A RE4 RE3 HSYNC/ RG13 RE2 RE0 RG0 RF1 ENVREG N/C RD12 GD11/ RD2 VSS GD7/ RD1 RC14 B N/C GCLK/ RG15 VDD RE1 RA7 RF0 VCAP RD5 RD3 C RE6 VSYNC/ RG12 RE5 RG14 GEN/ RA6 VSS N/C RD7 RD4 VDD RC13 RD11 D GD0/ RC1 RC4 RE7 VSS N/C RD6 RD13 RD0 n/c RD10 E GD1/ RC3 RG8 RG6 GD8/ RC2 RG7 VDD RG1 N/C RA15 RD8 GD10/ RD9 VSS RA14 F MCLR RG9 VSS n/c N/C VDD OSCI/ RC12 RA5 OSCO/ RC15 RA4 G RE8 RE9 RA0 N/C VDD VSS VSS N/C RA3 H PGEC3/ PGED3/ GD4/RB4 RB5 GD5/ RB3 PGEC1/ RB1 PGEC2/ RB6 GD6/ RB2 PGED1/ RB0 RA9 VSS VDD N/C VDD n/c VBUS/ RF7 N/C VUSB D+/RG2 RA2 J PGED2/RB7 AVDD GPWR RB11 RA1 RB12 N/C GD9/RF8 D-/RG3 K RA10 GD12/ RB8 GD13/ RB9 N/C RF12 RB14 VDD GD15/ RD15 GD14/ RD14 USBID/ RF3 RF4 GD3/ RF2 RF5 L AVSS RB10 GD2/ RF13 RB13 RB15 Note 1: Legend: See Table 3 for complete functional pinout descriptions. RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Shaded pins indicate pins tolerant to up to +5.5V. DS39969B-page 10  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 3: Pin A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 Legend: Note 1: 2: 3: PMD4/CN62/RE4 PMD3/CN61/RE3 HSYNC/CN80/RG13 PMD0/CN58/RE0 PMD8/CN77/RG0 VCMPST2/SESSVLD/PMD10/CN69/RF1 ENVREG N/C RPI42/PMD12/CN57/RD12 DPH/RP23/GD11/PMACK1/CN51/RD2 VCPCON/RP24/GD7/VBUSCHG/CN50/RD1 N/C GCLK/CN82/RG15 PMD2/CN60/RE2 PMD1/CN59/RE1 AN22/PMA17/CN40/RA7 VBUSST/VCMPST1/VBUSVLD/PMD11/CN68/RF0 VCAP RP20/PMRD/CN14/RD5 RP22/PMBE0/CN52/RD3 VSS SOSCO/SCLKI/T1CK/C3INC/RPI37/CN0/RC14 SCL3/PMD6/CN64/RE6 VDD VSYNC/CN79/RG12 PMA16/CN81/RG14 AN23/GEN/CN39/RA6 N/C C3INA/SESSEND/PMD15/CN16/RD7 RP25/PMWR/CN13/RD4 VDD SOSCI/C3IND/CN1/RC13 RP12/PMA14/PMCS1(3)/CN56/RD11 RPI38/GD0/CN45/RC1 SDA3/PMD7/CN65/RE7 PMD5/CN63/RE5 VSS VSS N/C C3INB/PMD14/CN15/RD6 PMD13/CN19/RD13 DMH/RP11/INT0/CN49/RD0 N/C RP3/PMA15/PMCS2(3)/CN55/RD10 AN16/RPI41/PMCS2/PMA22(2)/CN48/RC4 RPI40/GD1/CN47/RC3 AN17/C1IND/RP21/PMA5/PMA18(2)/CN8/RG6 RPI39/GD8/CN46/RC2 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Function Pin E5 E6 E7 E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 VDD PMD9/CN78/RG1 N/C SDA1/RPI35/PMBE1/CN44/RA15 DMLN/RTCC/RP2/CN53/RD8 DPLN/RP4/GD10/PMACK2/CN54/RD9 SCL1/RPI36/PMA22/PMCS2(2)/CN43/RA14 MCLR AN19/C2IND/RP19/PMA3/PMA21(2)/CN10/RG8 AN20/C2INC/RP27/PMA2/CN11/RG9 AN18/C1INC/RP26/PMA4/PMA20(2)/CN9/RG7 VSS N/C N/C VDD OSCI/CLKI/CN23/RC12 VSS OSCO/CLKO/CN22/RC15 RPI33/PMCS1/CN66/RE8 AN21/RPI34/PMA19/CN67/RE9 TMS/CN33/RA0 N/C VDD VSS VSS N/C TDO/CN38/RA5 SDA2/PMA20/PMA4(2)/CN36/RA3 TDI/PMA21/PMA3(2)/CN37/RA4 PGEC3/AN5/C1INA/VBUSON/RP18/CN7/RB5 PGED3/AN4/C1INB/USBOEN/RP28/GD4/CN6/RB4 VSS VDD N/C VDD N/C VBUS/CN73/RF7 VUSB D+/CN83/RG2 SCL2/CN35/RA2 AN3/C2INA/GD5/VPIO/CN5/RB3 AN2/C2INB/VMIO/RP13/GD6/CN4/RB2 PGED2/AN7/RP7/RCV/GPWR/CN25/RB7 AVDD AN11/PMA12/CN29/RB11 TCK/CN34/RA1 AN12/PMA11/CTEDG2/CN30/RB12 N/C Function RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF is not equal to ‘00’.  2010 Microchip Technology Inc. DS39969B-page 11 PIC24FJ256DA210 FAMILY TABLE 3: Pin J9 J10 J11 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 Legend: Note 1: 2: 3: N/C RP15/GD9/CN74/RF8 D-/CN84/RG3 PGEC1/AN1/VREF-(1)/RP1/CN3/RB1 PGED1/AN0/VREF+(1)/RP0/CN2/RB0 VREF+(1)/PMA6/CN42/RA10 AN8/RP8/GD12/CN26/RB8 N/C RPI32/PMA18/PMA5(2)/CN75/RF12 AN14/CTPLS/RP14/PMA1/CN32/RB14 VDD RP5/GD15/CN21/RD15 RP16/USBID/CN71/RF3 RP30/GD3/CN70/RF2 COMPLETE PIN FUNCTION DESCRIPTIONS FOR 121-PIN (BGA) DEVICES Function Pin L1 L2 L3 L4 L5 L6 L7 L8 L9 L10 L11 — — — Function PGEC2/AN6/RP6/CN24/RB6 VREF-(1)/PMA7/CN41/RA9 AVSS AN9/RP9/GD13/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 RP31/GD2/CN76/RF13 AN13/PMA10/CTEDG1/CN31/RB13 AN15/REFO/RP29/PMA0/CN12/RB15 RPI43/GD14/CN20/RD14 RP10/PMA9/CN17/RF4 RP17/GD5/PMA8/SCL2/CN18/RF5 — — — RPn and RPIn represent remappable pins for Peripheral Pin Select functions. Alternate pin assignments for VREF+ and VREF- when the ALTVREF Configuration bit is programmed. Alternate pin assignments for EPMP when the ALTPMP Configuration bit is programmed. Pin assignment for PMCSx when CSF is not equal to ‘00’. DS39969B-page 12  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 33 3.0 CPU ........................................................................................................................................................................................... 39 4.0 Memory Organization ................................................................................................................................................................. 45 5.0 Flash Program Memory.............................................................................................................................................................. 81 6.0 Resets ........................................................................................................................................................................................ 87 7.0 Interrupt Controller ..................................................................................................................................................................... 93 8.0 Oscillator Configuration ............................................................................................................................................................ 141 9.0 Power-Saving Features............................................................................................................................................................ 155 10.0 I/O Ports ................................................................................................................................................................................... 157 11.0 Timer1 ...................................................................................................................................................................................... 189 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 191 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 197 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 201 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 211 16.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 223 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 231 18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 239 19.0 Enhanced Parallel Master Port (EPMP) ................................................................................................................................... 273 20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 285 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 297 22.0 Graphics Controller Module (GFX)........................................................................................................................................... 305 23.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 325 24.0 Triple Comparator Module........................................................................................................................................................ 335 25.0 Comparator Voltage Reference................................................................................................................................................ 341 26.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 343 27.0 Special Features ...................................................................................................................................................................... 347 28.0 Development Support............................................................................................................................................................... 359 29.0 Instruction Set Summary .......................................................................................................................................................... 363 30.0 Electrical Characteristics .......................................................................................................................................................... 371 31.0 Packaging Information.............................................................................................................................................................. 387 Appendix A: Revision History............................................................................................................................................................. 397 Index ................................................................................................................................................................................................. 399 The Microchip Web Site ..................................................................................................................................................................... 405 Customer Change Notification Service .............................................................................................................................................. 405 Customer Support .............................................................................................................................................................................. 405 Reader Response .............................................................................................................................................................................. 406 Product Identification System ............................................................................................................................................................ 407  2010 Microchip Technology Inc. DS39969B-page 13 PIC24FJ256DA210 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39969B-page 14  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ128DA106 • PIC24FJ256DA106 • PIC24FJ128DA110 • PIC24FJ256DA110 • PIC24FJ128DA206 • PIC24FJ256DA206 • PIC24FJ128DA210 • PIC24FJ256DA210 • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active with a single instruction in software. The PIC24FJ256DA210 family enhances on the existing line of Microchip‘s 16-bit microcontrollers, adding a new Graphics Controller (GFX) module to interface with a graphical LCD display and also adds large data RAM, up to 96 Kbytes. The PIC24FJ256DA210 family allows the CPU to fetch data directly from an external memory device using the EPMP module. 1.1.3 OSCILLATOR OPTIONS AND FEATURES 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE All of the devices in the PIC24FJ256DA210 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor (FSCM). This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® Digital Signal Controllers (DSCs). The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 32 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ • Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256DA210 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.  2010 Microchip Technology Inc. DS39969B-page 15 PIC24FJ256DA210 FAMILY 1.2 Graphics Controller 1.4 Other Special Features With the PIC24FJ256DA210 family of devices, Microchip introduces the Graphics Controller module, which acts as an interface between the CPU (mainly through SFRs) and a display. On-board RAM is provided for display buffer, scratch areas, images and fonts. In some cases, the RAM requirements for the display used exceeds the on-board RAM; external memory connected through EPMP can be used. This module provides acceleration for drawing points, vertical and horizontal lines, rectangles, copying rectangles between different locations on screen, drawing text and decompressing compressed data. • Peripheral Pin Select: The Peripheral Pin Select (PPS) feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ256DA210 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C™ modules that support both Master and Slave modes of operation. Devices also have, through the PPS feature, four independent UARTs with built-in IrDA® encoders/decoders and three SPI modules. • Analog Features: All members of the PIC24FJ256DA210 family include a 10-bit A/D Converter (ADC) module and a triple comparator module. The ADC module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, and faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: In addition to their other analog features, members of the PIC24FJ256DA210 family include the CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. • Enhanced Parallel Master/Parallel Slave Port: There are general purpose I/O ports, which can be configured for parallel data communications. In this mode, the device can be master or slave on the communication bus. 4-bit, 8-bit and 16-bit data transfers, with up to 23 external address lines are supported in Master modes. • Real-Time Clock and Calendar: (RTCC) This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.3 USB On-The-Go The USB On-The-Go (USB OTG) module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ256DA210 family devices provide a true single chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. DS39969B-page 16  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 1.5 Details on Individual Family Members 5. Devices in the PIC24FJ256DA210 family are available in 64-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in seven ways: 1. Flash program memory (128 Kbytes for PIC24FJ128DAXXX devices and 256 Kbytes for PIC24FJ256DAXXX devices). Data memory (24 Kbytes for PIC24FJXXXDA1XX devices, and 96 Kbytes for PIC24FJXXXDA2XX devices). Available I/O pins and ports (52 pins on 6 ports for PIC24FJXXXDAX06 devices and 84 pins on 7 ports for PIC24FJXXXDAX10 devices). Available Interrupt-on-Change Notification (ICN) inputs (52 on PIC24FJXXXDAx06 devices and 84 on PIC24FJXXXDAX10 devices). Available remappable pins (29 pins on PIC24FJXXXDAX06 devices and 44 pins on PIC24FJXXXDAX10 devices). Analog channels for ADC (16 channels for PIC24FJXXXDAX06 devices and 24 channels for PIC24FJxxxDAx10 devices). EPMP module (available in PIC24FJXXXDAX10 devices and not in PIC24FJXXXDAX06 devices). 6. 7. All other features for devices in this family are identical. These are summarized in Table 1-1 and Table 1-2. A list of the pin features available on the PIC24FJ256DA210 family devices, sorted by function, is shown in Table 1-1. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 2. 3. 4.  2010 Microchip Technology Inc. DS39969B-page 17 PIC24FJ256DA210 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 64-PIN Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (EPMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) Analog Comparators CTMU Interface USB OTG Graphics Controller Resets (and Delays) 4(1) 3(1) 3 No Yes 16 3 Yes Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP and QFN Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 52 128K 44,032 24K 65 (61/4) Ports B, C, D, E, F, G 52 29 (28 I/O, 1 Input only) 256K 87,552 PIC24FJ128DA106 PIC24FJ256DA106 PIC24FJ128DA206 128K 44,032 96K PIC24FJ256DA206 256K 87,552 DC – 32 MHz Instruction Set Packages Note 1: DS39969B-page 18  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256DA210 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (EPMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Converter (ADC) Module (input channels) Analog Comparators CTMU Interface USB OTG Graphics Controller Resets (and delays) 4(1) 3(1) 3 Yes Yes 24 3 Yes Yes Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP and 121-Pin BGA Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 84 128K 44,032 24K 66 (62/4) Ports A, B, C, D, E, F, G 84 44 (32 I/O, 12 input only) 256K 87,552 PIC24FJ128DA110 PIC24FJ256DA110 PIC24FJ128DA210 PIC24FJ256DA210 DC – 32 MHz 128K 44,032 96K 256K 87,552 Instruction Set Packages Note 1:  2010 Microchip Technology Inc. DS39969B-page 19 PIC24FJ256DA210 FAMILY FIGURE 1-1: PIC24FJ256DA210 FAMILY GENERAL BLOCK DIAGRAM Interrupt Controller Data Bus 16 8 16 16 Data Latch PORTA(1) (12 I/O) EDS and Table Data Access Control Block 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Up to 0x7FFF Address Latch 16 16 Read AGU Write AGU PORTB (16 I/O) 23 Address Latch Program Memory/ Extended Data Space Data Latch PORTC(1) (8 I/O) Address Bus 24 Inst Latch Inst Register Instruction Decode and Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer LVD & BOR Literal Data EA MUX 16 16 16 PORTD(1) (16 I/O) PORTE(1) Divide Support 17x17 Multiplier 16 x 16 W Reg Array (10 I/O) REFO 16-Bit ALU 16 PORTF(1) (10 I/O) PORTG(1) (12 I/O) VCAP VDD, VSS MCLR Timer1 Timer2/3(2) Timer4/5(2) RTCC 10-Bit ADC Comparators(2) USB OTG EPMP/PSP(3) IC 1-9(2) Note 1: 2: 3: OC/PWM 1-9(2) SPI 1/2/3(2) I2C™ 1/2/3 ICNs(1) UART 1/2/3/4(2) CTMU(2) Graphics Controller Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-1 for specific implementations by pin count. These peripheral I/Os are only accessible through remappable pins. Not available on 64-pin devices (PIC24FJxxxDAx06). DS39969B-page 20  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS Pin Number 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 9 10 11 12 14 19 92 91 30 31 20 21 11 10 22 23 14 12 84 83 74 73 63 64 121-Pin BGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 E1 E3 F4 F2 F3 G2 B5 C5 J4 L3 H1 H2 F4 E3 J1 J2 F3 F2 C7 D7 B11 C10 F9 F11 I/O Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA — — ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ST — Positive Supply for Analog modules. Ground Reference for Analog modules. Comparator 1 Input A. Comparator 1 Input B. Comparator 1 Input C. Comparator 1 Input D. Comparator 2 Input A. Comparator 2 Input B. Comparator 2 Input C. Comparator 2 Input D. Comparator 3 Input A. Comparator 3 Input B. Comparator 3 Input C. Comparator 3 Input D. Main Clock Input Connection. System Clock Output. A/D Analog Inputs. Description 64-Pin TQFP/QFN 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 — — — — — — — — 19 20 11 12 5 4 13 14 8 6 55 54 48 47 39 40 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 AN17 AN18 AN19 AN20 AN21 AN22 AN23 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I P P I I I I I I I I I I I I I O TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 21 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 64 63 26 27 32 33 34 35 41 42 43 17 38 58 59 60 61 91 121-Pin BGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 F11 F9 L1 J3 K4 L4 L5 J5 J7 L7 K7 G3 J6 H11 G10 G11 G9 C5 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 40 39 17 18 21 22 23 24 27 28 29 — — — — — — — CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39969B-page 22  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 92 28 29 66 67 6 7 8 9 72 76 77 78 68 69 70 71 79 93 94 98 99 100 3 4 5 18 19 87 88 52 51 54 53 40 39 90 89 96 97 121-Pin BGA B5 L2 K3 E11 E8 D1 E4 E2 E1 D9 A11 A10 B9 E9 E10 D11 C11 A9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 H8 J10 K6 L6 A5 E6 C3 A3 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN — — — — — — — — — 46 49 50 51 42 43 44 45 — 60 61 62 63 64 1 2 3 — — 58 59 — 33 — — — — — — — — CN40 CN41 CN42 CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN73 CN74 CN75 CN76 CN77 CN78 CN79 CN80 Legend: Note 1: 2: 3: 4: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 23 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 95 1 57 56 42 41 43 34 57 56 72 68 77 69 86 1 6 8 39 52 21 22 23 76 7 53 69 77 32 33 47 48 91 27 97 72 13 63 64 121-Pin BGA C4 B2 H10 J11 L7 J7 K7 L5 H10 J11 D9 E9 A10 E10 J7 B2 D1 E2 L6 K11 H2 J1 J2 A11 E4 J10 E10 A10 K4 L4 L9 K9 C5 J3 A3 D9 F1 F9 F11 I/O Input Buffer ST ST ST ST ANA ANA — — — — — — — — ST — — — — — — — — — — — — — — — — — — — — ST ST ANA ANA Graphics Display Enable Output. Graphics Display Power System Enable. Graphics Display Horizontal Sync Pulse. External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. Graphics Controller Data Output. CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output. Comparator Voltage Reference Output. USB Differential Plus Line (internal transceiver). USB Differential Minus Line (internal transceiver). D- External Pull-up Control Output. D- External Pull-down Control Output. D+ External Pull-up Control Output. D+ External Pull-down Control Output. Voltage Regulator Enable. Graphics Display Pixel Clock. Interrupt-on-Change Inputs. Description 64-Pin TQFP/QFN — — 37 36 28 27 29 23 37 36 46 42 50 43 57 52 60 61 62 63 31 32 44 45 43 49 58 59 2 3 6 8 51 53 64 46 7 39 40 CN81 CN82 CN83 CN84 CTEDG1 CTEDG2 CTPLS CVREF D+ DDMH DMLN DPH DPLN ENVREG GCLK GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 GD8 GD9 GD10 GD11 GD12 GD13 GD14 GD15 GEN GPWR HSYNC INT0 MCLR OSCI OSCO Legend: Note 1: 2: 3: 4: I I I I I I O O I/O I/O O O O O I O O O O O O O O O O O O O O O O O O O O I I I O TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39969B-page 24  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 24 25 26 27 20 21 44 43 14 12, 60(1) 11,59(1) 10,40(1) 29 28 50 49 42 41 35 34 71 70 95 92 40,10 19 59, 11(1) 60,12(1) 66,9(1) 77 69 44 43 14 78 67 71 ,18 70(2),9, 66(1) (3) (1) 64-Pin TQFP/QFN 15 16 17 18 11 12 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 121-Pin BGA K1 K2 L1 J3 H1 H2 L8 K7 F3 F2, G11(1) F4,G10(1) E3,K6(1) K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C4 B5 K6,E3 G2 G10, F4(1) G11,F2(1) E11,E1(1) A10 E10 L8 K7 F3 B9 E8 C11 (3) (1) I/O Input Buffer ST ST ST ST ST ST ST ST — — — — — — — — — — — — — — — — — — — — — Description PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMA16 PMA17 PMA18 PMA19 PMA20 PMA21 PMA22 PMACK1 PMACK2 PMALL PMALH PMALU PMBE0 PMBE1 PMCS1 PMCS2 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O O O O O O O O O O I I O O O O O I/O O In-Circuit Debugger/Emulator/ICSP™ Programming Clock 1. In-Circuit Debugger/Emulator/ICSP Programming Data 1. In-Circuit Debugger/Emulator/ICSP Programming Clock 2. In-Circuit Debugger/Emulator/ICSP Programming Data 2. In-Circuit Debugger/Emulator/ICSP Programming Clock 3. In-Circuit Debugger/Emulator/ICSP Programming Data 3. Parallel Master Port Address bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address bits. ST/TTL Parallel Master Port Acknowledge Input 1. ST/TTL Parallel Master Port Acknowledge Input 2. — — — — — — Parallel Master Port Lower Address Latch Strobe. Parallel Master Port Higher Address Latch Strobe. Parallel Master Port Upper Address Latch Strobe. Parallel Master Port Byte Enable Strobe 0. Parallel Master Port Byte Enable Strobe 1. ,G1 ST/TTL Parallel Master Port Chip Select Strobe 1. Parallel Master Port Chip Select Strobe 2. D11(2),E1, E11(1) TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 25 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 82 81 17 38 58 59 60 61 91 92 28 29 66 67 121-Pin BGA A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 B8 C8 G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 I/O Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL Parallel Master Port Read Strobe. ST/TTL Parallel Master Port Write Strobe. ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTA Digital I/O. Parallel Master Port Data bits. Description 64-Pin TQFP/QFN — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMRD PMWR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39969B-page 26  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 27 121-Pin BGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11 J3 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST USB Receive Input (from external transceiver). ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTC Digital I/O. PORTB Digital I/O. Description 64-Pin TQFP/QFN 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 — — — — 39 47 48 40 18 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 RCV Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 27 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 44 87 88 52 51 49 50 54 53 40 39 121-Pin BGA D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 L8 B6 A6 K11 K10 L10 L11 H8 J10 K6 L6 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTF Digital I/O. Reference Clock Output. PORTE Digital I/O. PORTD Digital I/O. Description 64-Pin TQFP/QFN 46 49 50 51 52 53 54 55 42 43 44 45 — — — — 60 61 62 63 64 1 2 3 — — 30 58 59 — 33 31 32 34 — — — RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REFO RF0 RF1 RF2 RF3 RF4 RF5 RF7 RF8 RF12 RF13 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39969B-page 28  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 90 89 57 56 10 11 12 14 96 97 95 1 25 24 68 70 69 48 26 27 32 33 49 72 71 23 43 53 51 50 20 12 121-Pin BGA A5 E6 H10 J11 E3 F4 F2 F3 C3 A3 C4 B2 K2 K1 E9 D11 E10 K9 L1 J3 K4 L4 L10 D9 C11 J2 K7 J10 K10 L11 H1 F2 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Remappable Peripheral (input or output). PORTG Digital I/O. Description 64-Pin TQFP/QFN — — 37 36 4 5 6 8 — — — — 16 15 42 44 43 — 17 18 21 22 31 46 45 14 29 — 33 32 11 6 RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 29 PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 82 10 78 77 76 81 11 14 21 44 52 39 40 18 19 67 66 74 6 7 8 9 79 47 68 66 58 4 74 67 59 5 84 88 73 74 74 121-Pin BGA B8 E3 B9 A10 A11 C8 F4 F3 H2 L8 K11 L6 K6 G1 G2 E8 E11 B11 D1 E4 E2 E1 A9 L9 E9 E11 H11 C1 B11 E8 G10 D2 C7 A6 C10 B11 B11 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — I2C™ I2C I2C ANA I2C I2C IC ST ST ANA ANA ST 2 64-Pin TQFP/QFN 53 4 51 50 49 52 5 8 12 30 — — — — — — — 48 — — — — — — 42 44 32 2 48 43 31 3 55 59 47 48 48 Description RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RTCC SCL1 SCL2 SCL3 SCLKI SDA1 SDA2 SDA3 SESSEND SESSVLD SOSCI SOSCO T1CK Legend: Note 1: 2: 3: 4: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I O I/O I/O I/O O I/O I/O I/O I I I O I Remappable Peripheral (input or output). Remappable Peripheral (input only). Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. Secondary Clock Input. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. USB VBUS Boost Generator, Comparator Input 3. USB VBUS Boost Generator, Comparator Input 2. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’. DS39969B-page 30  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 1-3: Function PIC24FJ256DA210 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 100-Pin TQFP 38 60 61 17 51 21 54 76 20 87 87 85 87 88 76 2, 16, 37, 46, 62 23 22 28, 24(4) 29, 25(4) 15, 36, 45, 65, 75 121-Pin BGA J6 G11 G9 G3 K10 H2 H8 A11 H1 B6 B6 B7 B6 A6 A11 C2, C9, F8, G5, H6, K8, H4, E5 J2 J1 L2, K1(4) K3, K2(4) B10, F5, F10, G6, G7, H3, D4, D5 C3 H9 I/O Input Buffer ST ST — ST ST — ANA — — ANA ST — ST ST — — JTAG Test Clock Input. JTAG Test Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. USB OTG ID (OTG mode only). USB Output Enable Control (for external transceiver). USB Voltage, Host mode (5V). External USB VBUS Charge Output. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. USB VBUS Boost Generator, Comparator Input 1. External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB VBUS Boost Generator, Comparator Input 2. USB OTG VBUS PWM/Charge Output. Positive Supply for Peripheral Digital Logic and I/O Pins. Description 64-Pin TQFP/QFN 27 28 24 23 33 12 34 49 11 58 58 56 58 59 49 10, 26, 38 TCK TDI TDO TMS USBID USBOEN VBUS VBUSCHG VBUSON VBUSST VBUSVLD VCAP VCMPST1 VCMPST2 VCPCON VDD I I O I I O I O O I I P I I O P VMIO VPIO VREFVREF+ VSS 14 13 15 16 9, 25, 41 I I I I P ST ST ANA ANA — USB Differential Minus Input/Output (external transceiver). USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins. VSYNC VUSB Legend: Note 1: 2: 3: 4: 1 35 96 55 O P — — Graphics Display Vertical Sync Pulse. USB Voltage (3.3V). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer The alternate EPMP pins are selected when the ALTPMP (CW3) bit is programmed to ‘0’. The PMSC2 signal will replace the PMA15 signal on the 15-pin PMA when CSF = 01 or 10. The PMCS1 signal will replace the PMA14 signal on the 14-pin PMA when CSF = 10. The alternate VREF pins selected when the ALTVREF (CW1) bit is programmed to ‘0’.  2010 Microchip Technology Inc. DS39969B-page 31 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 32  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) VDD VDD VSS 2.1 Getting started with the PIC24FJ256DA210 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. R1 R2 MCLR (1) (1) (EN/DIS)VREG VCAP/VDDCORE C1 PIC24FXXXX C6(2) VSS VDD VDD C7 C3(2) VSS AVDD AVSS VDD VSS C5(2) C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: See Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)” for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 2: The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. DS39969B-page 33 PIC24FJ256DA210 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC24FXXXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39969B-page 34  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) This section applies only to PIC24FJ devices with an on-chip voltage regulator. ESR () FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP Note: 10 1 The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: • For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator • For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator Refer to Section 27.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR (16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write NVMCON = 0x4042; // Initialize NVMCON asm("DISI #5"); // Block all interrupts with priority 16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); // Write to address low word __builtin_tblwth(offset, progDataH); // Write to upper byte asm(“DISI #5”); // Block interrupts with priority VBUS_VLD Bus Condition VBUS < VB_SESS_END VB_SESS_END < VBUS < VA_SESS_VLD VA_SESS_VLD < VBUS < VA_VBUS_VLD VBUS > VBUS_VLD If UVCMPSEL = 0 If UVCMPSEL = 1 VBUSVLD 0 0 0 1  2010 Microchip Technology Inc. DS39969B-page 253 PIC24FJ256DA210 FAMILY 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) With the exception of U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. The registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: • U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as ‘0’ for boundary alignment. • U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame. • U1PWMRRS: Contains the 8-bit value for PWM duty cycle bits and PWM period bits for the VBUS boost assist PWM module. This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 “USB Buffer Descriptors and the BDT”. DS39969B-page 254  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — R-0, HSC LSTATE U-0 — R-0, HSC SESVD R-0, HSC SESEND U-0 — R-0, HSC VBUSVD bit 0 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown REGISTER 18-3: U-0 — bit 15 R-0, HSC ID bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 Unimplemented: Read as ‘0’ ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle Unimplemented: Read as ‘0’ LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has not been stable for the previous 1 ms Unimplemented: Read as ‘0’ SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device SESEND: B Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device Unimplemented: Read as ‘0’ VBUSVD: A VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39969B-page 255 PIC24FJ256DA210 FAMILY REGISTER 18-4: U-0 — bit 15 R/W-0 DPPULUP bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 DMPULUP R/W-0 R/W-0 R/W-0 VBUSON(1) R/W-0 OTGEN(1) R/W-0 U-0 — U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 bit 0 DPPULDWN(1) DMPULDWN(1) VBUSCHG(1) VBUSDIS(1) Unimplemented: Read as ‘0’ DPPULUP: D+ Pull-up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled DMPULUP: D- Pull-up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-up and pull-down bits are enabled 0 = USB OTG is disabled; D+/D- pull-up and pull-down bits are controlled in hardware by the settings of the HOSTEN and USBEN (U1CON) bits VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged These bits are only used in Host mode; do not use in Device mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39969B-page 256  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-5: U-0 — bit 15 R/W-0, HS UACTPND bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 USLPGRD U-0 — U-0 — R/W-0, HC USUSPND U1PWRC: USB POWER CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 USBPWR bit 0 Unimplemented: Read as ‘0’ UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires the USLPGRD bit to be set) 0 = Module may be suspended or powered down Unimplemented: Read as ‘0’ USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend Unimplemented: Read as ‘0’ USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON and U1OTGCON) are all cleared. bit 6-5 bit 4 bit 3-2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39969B-page 257 PIC24FJ256DA210 FAMILY REGISTER 18-6: U-0 — bit 15 R-0, HSC ENDPT3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-0, HSC ENDPT2 R-0, HSC ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC PPBI(1) U-0 — U-0 — bit 0 U1STAT: USB STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ ENDPT: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 . . . 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (TX) 0 = The last transaction was a receive transfer (RX) PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the odd BD bank 0 = The last transaction was to the even BD bank Unimplemented: Read as ‘0’ This bit is only valid for endpoints with available even and odd BD registers. bit 3 bit 2 bit 1-0 Note 1: DS39969B-page 258  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-7: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 PKTDIS U-0 — R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 USBEN bit 0 Unimplemented: Read as ‘0’ SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled Unimplemented: Read as ‘0’ HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39969B-page 259 PIC24FJ256DA210 FAMILY REGISTER 18-8: U-0 — bit 15 R-x, HSC JSTATE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 TOKBUSY R/W-0 USBRST R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 SOFEN bit 0 Unimplemented: Read as ‘0’ JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB 0 = No J state is detected SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed USBRST: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 50 ms, then clear it 0 = USB Reset is terminated HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling is disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the even BD banks 0 = Ping-Pong Buffer Pointers are not reset SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token is sent every one 1 ms 0 = Start-Of-Frame token is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 260  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-9: U-0 — bit 15 R/W-0 LSPDEN(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADDR6 R/W-0 ADDR5 R/W-0 ADDR4 R/W-0 ADDR3 R/W-0 ADDR2 R/W-0 ADDR1 U1ADDR: USB ADDRESS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 ADDR0 bit 0 Unimplemented: Read as ‘0’ LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed ADDR: USB Device Address bits Host mode only. In Device mode, this bit is unimplemented and read as ‘0’. bit 6-0 Note 1: REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 — bit 15 R/W-0 PID3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PID2 R/W-0 PID1 R/W-0 PID0 R/W-0 EP3 R/W-0 EP2 R/W-0 EP1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 EP0 bit 0 Unimplemented: Read as ‘0’ PID: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) EP: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. All other combinations are reserved and are not to be used. bit 3-0 Note 1:  2010 Microchip Technology Inc. DS39969B-page 261 PIC24FJ256DA210 FAMILY REGISTER 18-11: U-0 — bit 15 R/W-0 CNT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 R/W-0 CNT6 R/W-0 CNT5 R/W-0 CNT4 R/W-0 CNT3 R/W-0 CNT2 R/W-0 CNT1 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CNT0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CNT: Start-Of-Frame Size bits Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 — bit 15 R/W-0 UTEYE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 UOEMON(1) U-0 — R/W-0 USBSIDL U-0 — U-0 — R/W-0 PPB1 R/W-0 PPB0 bit 0 Unimplemented: Read as ‘0’ UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal is inactive Unimplemented: Read as ‘0’ USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ PPB: Ping-Pong Buffers Configuration bits 11 = Even/Odd ping-pong buffers are enabled for Endpoints 1 to 15 10 = Even/Odd ping-pong buffers are enabled for all endpoints 01 = Even/Odd ping-pong buffers are enabled for OUT Endpoint 0 00 = Even/Odd ping-pong buffers are disabled This bit is only active when the UTRDIS bit (U1CNFG2) is set. bit 6 bit 5 bit 4 bit 3-2 bit 1-0 Note 1: DS39969B-page 262  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 UVCMPSEL R/W-0 PUVBUS R/W-0 EXTI2CEN R/W-0 UVBUSDIS(1) R/W-0 UVCMPDIS(1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 UTRDIS(1) bit 0 Unimplemented: Read as ‘0’ UVCMPSEL: VBUS Comparator External Interface Selection bit 1 = Use VBUSVLD, SESSVLD and SESSEND as comparator interface pins 0 = Use VCMPST1 and VCMPST2 as comparator interface pins PUVBUS: VBUS Pull-Up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled EXTI2CEN: I2C™ Interface For External Module Control Enable bit 1 = External module(s) is controlled via the I2C™ interface 0 = External module(s) controlled via the dedicated pins UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Never change these bits while the USBPWR bit is set (U1PWRC = 1). bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39969B-page 263 PIC24FJ256DA210 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 — bit 15 R/K-0, HS IDIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown R/K-0, HS T1MSECIF R/K-0, HS LSTATEIF R/K-0, HS ACTVIF R/K-0, HS SESVDIF R/K-0, HS SESENDIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS VBUSVDIF bit 0 Unimplemented: Read as ‘0’ IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change is detected T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from the last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END Unimplemented: Read as ‘0’ VBUSVDIF: A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device is detected VBUS threshold crossings may be either rising or falling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39969B-page 264  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 — bit 15 R/W-0 IDIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 T1MSECIE R/W-0 LSTATEIE R/W-0 ACTVIE R/W-0 SESVDIE R/W-0 SESENDIE U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 VBUSVDIE bit 0 Unimplemented: Read as ‘0’ IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as ‘0’ VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39969B-page 265 PIC24FJ256DA210 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 — bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS URSTIF bit 0 Unimplemented: Read as ‘0’ STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent Unimplemented: Read as ‘0’ RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token is not complete; clear the U1STAT register or load the next token from STAT (clearing this bit causes the STAT FIFO to advance) SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token is received by the peripheral or the Start-Of-Frame threshold is reached by the host 0 = No Start-Of-Frame token is received or threshold reached UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: DS39969B-page 266  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 — bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown R/K-0, HS ATTACHIF R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS DETACHIF bit 0 Unimplemented: Read as ‘0’ STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; it is set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attacement has been detected RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of the current token is complete; read the U1STAT register for endpoint information 0 = Processing of the current token not complete; clear the U1STAT register or load the next token from U1STAT SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment is detected. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note:  2010 Microchip Technology Inc. DS39969B-page 267 PIC24FJ256DA210 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 — bit 15 R/W-0 STALLIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ATTACHIE (1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 RESUMEIE R/W-0 IDLEIE R/W-0 TRNIE R/W-0 SOFIE R/W-0 UERRIE R/W-0 URSTIE DETACHIE bit 0 Unimplemented: Read as ‘0’ STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt is enabled 0 = Interrupt is disabled RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled SOFIE: Start-Of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented in Device mode, read as ‘0’. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39969B-page 268  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 — bit 15 R/K-0, HS BTSEF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/K-0, HS DMAEF R/K-0, HS BTOEF R/K-0, HS DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS PIDEF Unimplemented: Read as ‘0’ BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error has been detected Unimplemented: Read as ‘0’ DMAEF: DMA Error Flag bit 1 = A USB DMA error condition is detected; the data size indicated by the BD byte count field is less than the number of received bytes, the received data is truncated 0 = No DMA error BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet is rejected due to CRC5 error 0 = Token packet is accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt is disabled PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39969B-page 269 PIC24FJ256DA210 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 — bit 15 R/W-0 BTSEE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 DMAEE R/W-0 BTOEE R/W-0 DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PIDEE Unimplemented: Read as ‘0’ BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as ‘0’ DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39969B-page 270  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 18.7.3 U-0 — bit 15 R/W-0 LSPD(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 RETRYDIS(1) U-0 — R/W-0 EPCONDIS R/W-0 EPRXEN R/W-0 EPTXEN R/W-0 EPSTALL USB ENDPOINT MANAGEMENT REGISTERS U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 EPHSHK bit 0 REGISTER 18-21: U1EPn: USB ENDPOINT n CONTROL REGISTERS (n = 0 TO 15) Unimplemented: Read as ‘0’ LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions is disabled 0 = Retry NAK transactions is enabled; retry is done in hardware Unimplemented: Read as ‘0’ EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from control transfers; only TX and RX transfers are allowed 0 = Enable Endpoint n for control (SETUP) transfers; TX and RX transfers are also allowed For all other combinations of EPTXEN and EPRXEN: This bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) These bits are available only for U1EP0 and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as ‘0’. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39969B-page 271 PIC24FJ256DA210 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 PWMEN bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 PWMPOL R/W-0 CNTEN bit 8 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in the Reset state specified by PWMPOL Unimplemented: Read as ‘0’ PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled Unimplemented: Read as ‘0’ bit 14-10 bit 9 bit 8 bit 7-0 DS39969B-page 272  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 19.0 Note: ENHANCED PARALLEL MASTER PORT (EPMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 42. “Enhanced Parallel Master Port (EPMP)” (DS39730). The information in this data sheet supersedes the information in the FRM. Key features of the EPMP module are: • Extended Data Space (EDS) interface allows Direct Access from the CPU • Up to 23 Programmable Address Lines • Up to 2 Chip Select Lines • Up to 2 Acknowledgement Lines (one per chip select) • 4-bit, 8-bit or 16-bit wide Data Bus • Programmable Strobe Options (per chip select) - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Programmable Address/Data Multiplexing • Programmable Address Wait States • Programmable Data Wait States (per chip select) • Programmable Polarity on Control Signals (per chip select) • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Alternate Master feature The Enhanced Parallel Master Port (EPMP) module is present in PIC24FJXXXDAX10 devices and not in PIC24FJXXXDAX06 devices. The EPMP provides a parallel 4-bit (Master mode only), 8-bit (Master and Slave modes) or 16-bit (Master mode only) data bus interface to communicate with off-chip modules, such as memories, FIFOs, LCD controllers and other microcontrollers. This module can serve as either the master or the slave on the communication bus. For EPMP Master modes, all external addresses are mapped into the internal Extended Data Space (EDS). This is done by allocating a region of the EDS for each chip select, and then assigning each chip select to a particular external resource, such as a memory or external controller. This region should not be assigned to another device resource, such as RAM or SFRs. To perform a write or read on an external resource, the CPU should simply perform a write or read within the address range assigned for EPMP. Note: The EPMP module is not present in 64-pin devices (PIC24FJXXXDAX06). 19.1 ALTPMP Setting Many of the lower order EPMP address pins are shared with ADC inputs. This is an untenable situation for users that need both the ADC channels and the EPMP bus. If the user does not need to use all the address bits, then by clearing the ALTPMP (CW3) Configuration bit, the lower order address bits can be mapped to higher address pins, which frees the ADC channels. The EPMP has an alternative master feature. The graphics controller module can control the EPMP directly in Alternate Master mode to access an external graphics buffer. TABLE 19-1: Pin RA14 RC4 RF12 RG6 RG7 RA3 RG8 RA4 ALTERNATE EPMP PINS ALTPMP = 0 PMCS2 PMA22 PMA5 PMA18 PMA20 PMA4 PMA21 PMA3 ALTPMP = 1 PMA22 PMCS2 PMA18 PMA5 PMA4 PMA20 PMA3 PMA21  2010 Microchip Technology Inc. DS39969B-page 273 PIC24FJ256DA210 FAMILY TABLE 19-2: PARALLEL MASTER PORT PIN DESCRIPTION Type O O PMA, PMCS2 O I/O O PMA, PMCS1 O I/O O PMA PMA PMA, PMALU I/O O O O PMA, PMALH PMA, PMALL PMD PMD PMD PMCS1 PMCS2 PMWR, PMENB PMRD, PMRD/PMWR PMBE1 PMBE0 PMACK1 PMACK2 I/O O I/O O I/O I/O O I/O I/O O I/O I/O O O I I Address bus bit Chip Select 2 (alternate location) Data bus bit when port size is 16 bits and address is multiplexed Address bus bit Chip Select 1 (alternate location) Data bus bit 14 when port size is 16-bit and address is multiplexed Address bus bit< 13-8> Data bus bits when port size is 16 bits and address is multiplexed Address bus bit< 7-3> Address bus bit Address latch upper strobe for multiplexed address Address bus bit Address latch high strobe for multiplexed address Address bus bit Address latch low strobe for multiplexed address Data bus bits when address is not multiplexed Data bus bits Address bus bits when port size is 4 bits and address is multiplexed with 1 address phase Data bus bits Chip Select 1 Chip Select 2 Write strobe or Enable signal depending on Strobe mode Read strobe or Read/Write signal depending on Strobe mode Byte indicator Nibble or byte indicator Acknowledgment 1 Acknowledgment 2 Description Address bus bits Pin Name PMA DS39969B-page 274  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-1: R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 PMCON1: EPMP CONTROL REGISTER 1 U-0 — R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 U-0 — R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 IRQM0 bit 0 R/W-0 CSF0 R/W-0 ALP R/W-0 ALMODE U-0 — R/W-0 BUSKEEP R/W-0 IRQM1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5 bit 4 bit 3 bit 2 bit 1-0 PMPEN: Parallel Master Port Enable bit 1 = EPMP is enabled 0 = EPMP is disabled Unimplemented: Read as ‘0’ PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX: Address/Data Multiplexing Selection bits 11 = Lower address bits are multiplexed with data bits using 3 address phases 10 = Lower address bits are multiplexed with data bits using 2 address phases 01 = Lower address bits are multiplexed with data bits using 1 address phase 00 = Address and data appear on separate pins Unimplemented: Read as ‘0’ MODE: Parallel Port Mode Select bits 11 = Master mode 10 = Enhanced PSP; pins used are PMRD, PMWR, PMCS, PMD and PMA 01 = Buffered PSP; pins used are PMRD, PMWR, PMCS and PMD 00 = Legacy Parallel Slave Port; PMRD, PMWR, PMCS and PMD pins are used CSF: Chip Select Function bits 11 = Reserved 10 = PMA used for Chip Select 2, PMA used for Chip Select 1 01 = PMA used for Chip Select 2, PMCS1 used for Chip Select 1 00 = PMCS2 used for Chip Select 2, PMCS1 used for Chip Select 1 ALP: Address Latch Polarity bit 1 = Active-high (PMALL, PMALH and PMALU) 0 = Active-low (PMALL, PMALH and PMALU) ALMODE: Address Latch Strobe Mode bit 1 = Enable “smart” address strobes (each address phase is only present if the current access would cause a different address in the latch than the previous address) 0 = Disable “smart” address strobes Unimplemented: Read as ‘0’ BUSKEEP: Bus Keeper bit 1 = Data bus keeps its last value when not actively being driven 0 = Data bus is in high-impedance state when not actively being driven IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode), or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = Reserved 01 = Interrupt generated at the end of a read/write cycle 00 = No interrupt is generated  2010 Microchip Technology Inc. DS39969B-page 275 PIC24FJ256DA210 FAMILY REGISTER 19-2: R-0, HSC BUSY bit 15 R/W-0 RADDR23 bit 7 R/W-0 RADDR22 R/W-0 RADDR21 R/W-0 RADDR20 R/W-0 RADDR19 R/W-0 RADDR18 R/W-0 RADDR17 U-0 — PMCON2: EPMP CONTROL REGISTER 2 R/C-0, HS ERROR R/C-0, HS TIMEOUT R-0, HSC AMREQ R-1, HSC CURMST R/W-0 MSTSEL1 R/W-0 MSTSEL0 bit 8 R/W-0 RADDR16 bit 0 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ C = Clearable bit ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7-0 Note 1: BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy Unimplemented: Read as ‘0’ ERROR: Error bit 1 = Transaction error (illegal transaction was requested) 0 = Transaction completed successfully TIMEOUT: Time-Out bit 1 = Transaction timed out 0 = Transaction completed successfully AMREQ: Alternate Master Request bit 1 = The Alternate Master is requesting use of EPMP 0 = The Alternate Master is not requesting use of EPMP CURMST: Current Master bit 1 = EPMP access is granted to CPU 0 = EPMP access is granted to alternate master MSTSEL: Parallel Port Master Select bits 11 = Alternate master I/Os direct access (EPMP Bypass mode) 10 = Reserved 01 = Alternate master 00 = CPU RADDR: Parallel Master Port Reserved Address Space bits(1) If RADDR = 00000000, then the last EDS address for Chip Select 2 will be 0xFFFFFF. DS39969B-page 276  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-3: R/W-0 PTWREN bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 PMCON3: EPMP CONTROL REGISTER 3 R/W-0 PTBE1EN R/W-0 PTBE0EN U-0 — R/W-0 AWAITM1 R/W-0 AWAITM0 R/W-0 AWAITE bit 8 R/W-0 PTEN16 bit 0 R/W-0 PTRDEN R/W-0 PTEN22 R/W-0 PTEN21 R/W-0 PTEN20 R/W-0 PTEN19 R/W-0 PTEN18 R/W-0 PTEN17 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10-9 bit bit 8 bit 7 bit 6-0 PTWREN: Write/Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled PTBE1EN: High Nibble/Byte Enable Port Enable bit 1 = PMBE1 port is enabled 0 = PMBE1 port is disabled PTBE0EN: Low Nibble/Byte Enable Port Enable bit 1 = PMBE0 port is enabled 0 = PMBE0 port is disabled Unimplemented: Read as ‘0’ AWAITM: Address Latch Strobe Wait States bits 11 = Wait of 3½ TCY 10 = Wait of 2½ TCY 01 = Wait of 1½ TCY 00 = Wait of ½ TCY AWAITE: Address Hold After Address Latch Strobe Wait States bits 1 = Wait of 1¼ TCY 0 = Wait of ¼ TCY Unimplemented: Read as ‘0’ PTEN: EPMP Address Port Enable bits 1 = PMA function as EPMP address lines 0 = PMA function as port I/Os  2010 Microchip Technology Inc. DS39969B-page 277 PIC24FJ256DA210 FAMILY REGISTER 19-4: R/W-0 PTEN15 bit 15 R/W-0 PTEN7 bit 7 PMCON4: EPMP CONTROL REGISTER 4 R/W-0 PTEN13 R/W-0 PTEN12 R/W-0 PTEN11 R/W-0 PTEN10 R/W-0 PTEN9 R/W-0 PTEN8 bit 8 R/W-0 PTEN0 bit 0 R/W-0 PTEN14 R/W-0 PTEN6 R/W-0 PTEN5 R/W-0 PTEN4 R/W-0 PTEN3 R/W-0 PTEN2 R/W-0 PTEN1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13-3 bit 2-0 PTEN15: PMA15 Port Enable bit 1 = PMA15 functions as either Address Line 15 or Chip Select 2 0 = PMA15 functions as port I/O PTEN14: PMA14 Port Enable bit 1 = PMA14 functions as either Address Line 14 or Chip Select 1 0 = PMA14 functions as port I/O PTEN: EPMP Address Port Enable bits 1 = PMA function as EPMP address lines 0 = PMA function as port I/Os PTEN: PMALU/PMALH/PMALL Strobe Enable bits 1 = PMA function as either address lines or address latch strobes 0 = PMA function as port I/Os DS39969B-page 278  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-5: R/W-0 CSDIS bit 15 R/W-0 ACKP bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PTSZ1 R/W-0 PTSZ0 U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 PMCSxCF: CHIP SELECT x CONFIGURATION REGISTER R/W-0 CSPTEN R/W-0 BEP U-0 — R/W-0 WRSP R/W-0 RDSP R/W-0 SM bit 8 CSP R/W-0 CSDIS: Chip Select x Disable bit 1 = Disable the Chip Select x functionality 0 = Enable the Chip Select x functionality CSP: Chip Select x Polarity bit 1 = Active-high (PMCSx) 0 = Active-low (PMCSx) CSPTEN: PMCSx Port Enable bit 1 = PMCSx port is enabled 0 = PMCSx port is disabled BEP: Chip Select x Nibble/Byte Enable Polarity bit 1 = Nibble/Byte enable active-high (PMBE0, PMBE1) 0 = Nibble/Byte enable active-low (PMBE0, PMBE1) Unimplemented: Read as ‘0’ WRSP: Chip Select x Write Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode when SM = 1: 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Chip Select x Read Strobe Polarity bit For Slave modes and Master mode when SM = 0: 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode when SM = 1: 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/Write strobe active-low (PMRD/PMWR) SM: Chip Select x Strobe Mode bit 1 = Read/Write and enable strobes (PMRD/PMWR and PMENB) 0 = Read and write strobes (PMRD and PMWR) ACKP: Chip Select x Acknowledge Polarity bit 1 = ACK active-high (PMACK1) 0 = ACK active-low (PMACK1) PTSZ: Chip Select x Port Size bits 11 = Reserved 10 = 16-bit port size (PMD) 01 = 4-bit port size (PMD) 00 = 8-bit port size (PMD) Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4-0  2010 Microchip Technology Inc. DS39969B-page 279 PIC24FJ256DA210 FAMILY REGISTER 19-6: R/W(1) BASE23 bit 15 R/W(1) BASE15 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 bit 3 bit 2-0 Note 1: 2: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/W(1) BASE11 U-0 — U-0 — U-0 — bit 0 PMCSxBS: CHIP SELECT x BASE ADDRESS REGISTER R/W(1) BASE21 R/W(1) BASE20 R/W(1) BASE19 R/W(1) BASE18 R/W(1) BASE17 R/W(1) BASE16 bit 8 R/W(1) BASE22 BASE: Chip Select x Base Address bits(2) Unimplemented: Read as ‘0’ BASE: Chip Select x Base Address bits(2) Unimplemented: Read as ‘0’ Value at POR is 0x0200 for PMCS1BS and 0x0600 for PMCS2BS. If the whole PMCS2BS register is written together as 0x0000, then the last EDS address for the Chip Select 1 will be 0xFFFFFF. In this case, the Chip Select 2 should not be used. PMCS1BS has no such feature. DS39969B-page 280  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-7: R/W-0 ACKM1 bit 15 R/W-0 DWAITB1 bit 7 PMCSxMD: CHIP SELECT x MODE REGISTER R/W-0 AMWAIT2 R/W-0 AMWAIT1 R/W-0 AMWAIT0 U-0 — U-0 — U-0 — bit 8 R/W-0 ACKM0 R/W-0 DWAITB0 R/W-0 DWAITM3 R/W-0 DWAITM2 R/W-0 DWAITM1 R/W-0 DWAITM0 R/W-0 DWAITE1 R/W-0 DWAITE0 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 13-11 ACKM: Chip Select x Acknowledge Mode bits 11 = Reserved 10 = PMACKx is used to determine when a read/write operation is complete 01 = PMACKx is used to determine when a read/write operation is complete with time-out If DWAITM = 0000, the maximum time-out is 255 TCY, else it is DWAITM cycles. 00 = PMACKx is not used AMWAIT: Chip Select x Alternate Master Wait States bits 111 = Wait of 10 alternate master cycles ... bit 10-8 bit 7-6 bit 5-2 001 = Wait of 4 alternate master cycles 000 = Wait of 3 alternate master cycles Unimplemented: Read as ‘0’ DWAITB: Chip Select x Data Setup Before Read/Write Strobe Wait States bits 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY DWAITM: Chip Select x Data Read/Write Strobe Wait States bits For Write operations: 1111 = Wait of 15½ TCY ... 0001 = Wait of 1½ TCY 0000 = Wait of ½ TCY For Read operations: 1111 = Wait of 15¾ TCY ... bit 1-0 0001 = Wait of 1¾ TCY 0000 = Wait of ¾ TCY DWAITE: Chip Select x Data Hold After Read/Write Strobe Wait States bits For Write operations: 11 = Wait of 3¼ TCY 10 = Wait of 2¼ TCY 01 = Wait of 1¼ TCY 00 = Wait of ¼ TCY For Read operations: 11 = Wait of 3 TCY 10 = Wait of 2 TCY 01 = Wait of 1 TCY 00 = Wait of 0 TCY  2010 Microchip Technology Inc. DS39969B-page 281 PIC24FJ256DA210 FAMILY REGISTER 19-8: R-0, HSC IBF bit 15 R-1, HSC OBE bit 7 PMSTAT: EPMP STATUS REGISTER (SLAVE MODE ONLY) U-0 — U-0 — R-0, HSC IB3F R-0, HSC IB2F R-0, HSC IB1F R-0, HSC IB0F bit 8 R-1, HSC OB0E bit 0 R/W-0 HS IBOV R/W-0 HS OBUF U-0 — U-0 — R-1, HSC OB3E R-1, HSC OB2E R-1, HSC OB1E Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as ‘0’ IBxF: Input Buffer x Status Full bit(1) 1 = Input buffer contains unread data (reading buffer will clear this bit) 0 = Input buffer does not contain unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OBxE: Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains untransmitted data Even though an individual bit represents the byte in the buffer, the bits corresponding to the Word (byte 0 and 1, or byte 2 and 3) gets cleared even on byte reading. Note 1: DS39969B-page 282  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 19-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 RTSECSEL(1) PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PMPTTL(2) bit 0 Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: EPMP Module TTL Input Buffer Select bit(2) 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL) bit must also be set. Unimplemented in 64-pin devices (PIC24FJXXXDAX06); maintain as ‘0’. bit 0 Note 1: 2:  2010 Microchip Technology Inc. DS39969B-page 283 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 284  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 20.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The information in this data sheet supersedes the information in the FRM. The Real-Time Clock and Calendar (RTCC) provides a function that can be calibrated. Key features of the RTCC module are: • Operates in Sleep mode • Provides hours, minutes and seconds using 24-hour format • Visibility of half of one second period • Provides calendar – weekday, date, month and year • Alarm configurable for half a second, one second,10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • Alarm with indefinite repeat chime • Year, 2000 to 2099, leap year correction • BCD format for smaller software overhead • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust - Calibration to within ±2.64 seconds error per month - Calibrates up to 260 ppm of crystal error FIGURE 20-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALCFGRPT YEAR MTHDY WKDYHR MINSEC ALMTHDY Compare Registers with Masks Repeat Counter ALRMVAL ALWDHR ALMINSEC 32.768 kHz Input from SOSC Comparator RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE  2010 Microchip Technology Inc. DS39969B-page 285 PIC24FJ256DA210 FAMILY 20.1 RTCC Module Registers TABLE 20-2: ALRMPTR 00 01 10 11 The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL ALRMVAL ALRMMIN ALRMWD ALRMMNTH — ALRMSEC ALRMHR ALRMDAY — 20.1.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through the corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired Timer register pair (see Table 20-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes, they will decrement the ALRMPTR value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. Note: This only applies to read operations and not write operations. 20.1.2 WRITE LOCK TABLE 20-1: RTCPTR 00 01 10 11 RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL MINUTES WEEKDAY MONTH — RTCVAL SECONDS HOURS DAY YEAR The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 20-2). By writing the ALRMVALH byte, the Alarm Pointer value bits, ALRMPTR, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. In order to perform a write to any of the RTCC Timer registers, the RTCWREN (RCFGCAL) bit must be set (refer to Example 20-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 20-1. For applications written in C, the unlock sequence should be implemented using in-line assembly. EXAMPLE 20-1: asm asm asm asm asm asm SETTING THE RTCWREN BIT volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13"); //set the RTCWREN bit DS39969B-page 286  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 20.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 — R/W-0 RTCWREN R-0, HSC RTCSYNC R-0, HSC HALFSEC (3) REGISTER 20-1: R/W-0 RTCEN(2) bit 15 R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 RTCOE R/W-0, HSC RTCPTR1 R/W-0, HSC RTCPTR0 bit 8 R/W-0 CAL6 R/W-0 CAL5 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 R/W-0 CAL0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as ‘0’ RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 Note 1: 2: 3:  2010 Microchip Technology Inc. DS39969B-page 287 PIC24FJ256DA210 FAMILY REGISTER 20-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) CAL: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. REGISTER 20-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 RTSECSEL(1) R/W-0 PMPTTL bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: EPMP Module TTL Input Buffer Select bit 1 = EPMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = EPMP module inputs use Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL) bit must also be set. bit 0 Note 1: DS39969B-page 288  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-3: R/W-0 ALRMEN bit 15 R/W-0, HSC ARPT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0, HSC ARPT6 R/W-0, HSC ARPT5 R/W-0, HSC ARPT4 R/W-0, HSC ARPT3 R/W-0, HSC ARPT2 R/W-0, HSC ARPT1 ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0, HSC ALRMPTR1 R/W-0, HSC ALRMPTR0 bit 8 R/W-0, HSC ARPT0 bit 0 R/W-0 CHIME ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00h and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h AMASK: Alarm Mask Configuration bits 11xx = Reserved – do not use 101x = Reserved – do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. bit 14 bit 13-10 bit 9-8 bit 7-0  2010 Microchip Technology Inc. DS39969B-page 289 PIC24FJ256DA210 FAMILY 20.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-x, HSC YRTEN2 R/W-x, HSC YRTEN1 R/W-x, HSC YRTEN0 R/W-x, HSC YRONE3 R/W-x, HSC YRONE2 R/W-x, HSC YRONE1 R/W-x, HSC YRONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown REGISTER 20-4: U-0 — bit 15 R/W-x, HSC YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 Unimplemented: Read as ‘0’ YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. A write to the YEAR register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-5: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 — U-0 — R/W-x, HSC MTHTEN0 R/W-x, HSC MTHONE3 R/W-x, HSC MTHONE2 R/W-x, HSC MTHONE1 R/W-x, HSC MTHONE0 bit 8 U-0 — R/W-x, HSC DAYTEN1 R/W-x, HSC DAYTEN0 R/W-x, HSC DAYONE3 R/W-x, HSC DAYONE2 R/W-x, HSC DAYONE1 R/W-x, HSC DAYONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39969B-page 290  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x, HSC HRTEN1 R/W-x, HSC HRTEN0 R/W-x, HSC HRONE3 R/W-x, HSC HRONE2 R/W-x, HSC HRONE1 WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — R/W-x, HSC WDAY2 R/W-x, HSC WDAY1 R/W-x, HSC WDAY0 bit 8 R/W-x, HSC HRONE0 bit 0 Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-7: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 MINSEC: MINUTES AND SECONDS VALUE REGISTER R/W-x, HSC MINTEN1 R/W-x, HSC MINTEN0 R/W-x, HSC MINONE3 R/W-x, HSC MINONE2 R/W-x, HSC MINONE1 R/W-x, HSC MINONE0 bit 8 R/W-x, HSC MINTEN2 R/W-x, HSC SECTEN2 R/W-x, HSC SECTEN1 R/W-x, HSC SECTEN0 R/W-x, HSC SECONE3 R/W-x, HSC SECONE2 R/W-x, HSC SECONE1 R/W-x, HSC SECONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39969B-page 291 PIC24FJ256DA210 FAMILY 20.1.5 ALRMVAL REGISTER MAPPINGS ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 — U-0 — R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 8 U-0 — R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 R/W-x DAYONE0 bit 0 REGISTER 20-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of 0 or 1. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39969B-page 292  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 20-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRONE0 bit 0 Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x SECONE0 bit 0 Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39969B-page 293 PIC24FJ256DA210 FAMILY 20.2 Calibration 20.3 Alarm The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Refer to the following steps for RTCC calibration: 1. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register. • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT, Register 20-3) • One-time alarm and repeat alarm options available 20.3.1 CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As shown in Figure 20-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the ARPT bits, ARPT (ALCFGRPT). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT with FFh. After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. 2. EQUATION 20-1: RTCC CALIBRATION Error (clocks per minute) = (Ideal Frequency† – Measured Frequency) x 60 †Ideal Frequency = 32,768H 3. a) If the oscillator is faster then ideal (negative result form Step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) If the oscillator is slower then ideal (positive result from Step 2), the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be added to the timer counter, once every minute. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. 20.3.2 ALARM INTERRUPT At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. DS39969B-page 294  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Day of the Week Alarm Mask Setting (AMASK) 0000 – Every half second 0001 – Every second 0010 – Every 10 seconds 0011 – Every minute 0100 – Every 10 minutes 0101 – Every hour 0110 – Every day 0111 – Every week 1000 – Every month 1001 – Every year(1) Note 1: s m m m s s s s s s Month Day Hours Minutes Seconds h d d m m d d d h h h h h h h m m m m m m m m s s s s s s s s Annually, except when configured for February 29.  2010 Microchip Technology Inc. DS39969B-page 295 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 296  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 21.0 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 41. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS39729). The information in this data sheet supersedes the information in the FRM. The 32-bit programmable CRC generator provides a hardware implemented method of quickly generating checksums for various networking and security applications. It offers the following features: • User-programmable CRC polynomial equation, up to 32 bits • Programmable shift direction (little or big-endian) • Independent data and polynomial lengths • Configurable interrupt output • Data FIFO Figure 21-1 displays a simplified block diagram of the CRC generator. A simple version of the CRC shift engine is displayed in Figure 21-2. Note: FIGURE 21-1: CRCDATH CRC BLOCK DIAGRAM CRCDATL Variable FIFO (4x32, 8x16 or 16x8) CRCWDATH LENDIAN Shift Buffer 1 FIFO Empty Event CRCWDATL CRCISEL 1 0 CRC Interrupt CRC Shift Engine 0 Shift Complete Event Shifter Clock 2 * FCY FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL CRC Shift Engine Read/ rite Bus W X0 Shift Buffer Data X1 Xn(1) Bit 0 Bit 1 Bit n(1) Note 1: n = PLEN + 1.  2010 Microchip Technology Inc. DS39969B-page 297 PIC24FJ256DA210 FAMILY 21.1 21.1.1 User Interface POLYNOMIAL INTERFACE 21.1.2 DATA INTERFACE The CRC module can be programmed for CRC polynomials of up of up the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN bits (CRCCON2). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation; functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR. For example, consider two CRC polynomials, one a 16-bit and the other a 32-bit equation. The module incorporates a FIFO that works with a variable data width. Input data width can be configured to any value between one and 32 bits using the DWIDTH bits (CRCCON2). When the data width is greater than 15, the FIFO is four words deep. When the DWITDH bits are between 15 and 8, the FIFO is 8 words deep. When the DWIDTH bits are less than 8, the FIFO is 16 words deep. The data for which the CRC is to be calculated must first be written into the FIFO. Even if the data width is less than 8, the smallest data element that can be written into the FIFO is one byte. For example, if DWIDTH is five, then the size of the data is DWIDTH + 1 or six. The data is written as a whole byte; the two unused upper bits are ignored by the module. Once data is written into the MSb of the CRCDAT registers (that is, MSb as defined by the data width), the value of the VWORD bits (CRCCON1) increments by one. For example, if DWIDTH is 24, the VWORD bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written to before CRCDATH. The CRC engine starts shifting data when the CRCGO bit is set and the value of VWORD is greater than zero. Each word is copied out of the FIFO into a buffer register, which decrements VWORD. The data is then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until VWORD reaches zero. This means that for a given data width, it takes half that number of instructions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit data. When VWORD reaches the maximum value for the configured value of DWIDTH (4, 8 or 16), the CRCFUL bit becomes set. When VWORD reaches zero, the CRCMPT bit becomes set. The FIFO is emptied and the VWORD bits are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. EQUATION 21-1: 16-BIT, 32-BIT CRC POLYNOMIALS X16 + X12 + X5 + 1 and X32+X26 + X23 + X22 + X16 + X12 + X11 + X10 + X8 + X7 + X5 + X4 + X2 + X + 1 To program these polynomial into the CRC generator, set the register bits as shown in Table 21-1. Note that the appropriate positions are set to ‘1’ to indicate they are used in the equation (for example, X26 and X23). The ‘0’ bit required by the equation is always XORed; thus, X0 is a don’t care. For a polynomial of length 32, it is assumed that the 32nd bit will be used. Therefore, the X bits do not have the 32nd bit. TABLE 21-1: CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIALS Bit Values 16-Bit Polynomial 01111 0000 0000 0000 0001 0001 0000 0010 000X 32-Bit Polynomial 11111 0000 0100 1100 0001 0001 1101 1011 011x CRC Control Bits PLEN X X DS39969B-page 298  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 21.1.3 DATA SHIFT DIRECTION 3. The LENDIAN bit (CRCCON1) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction the data is shifted into the engine. The result of the CRC calculation will still be a normal CRC result, not a reverse CRC result. Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is set or no data is left. Clear old results by writing 00h to CRCWDATL and CRCWDATH. The CRCWDAT registers can also be left unchanged to resume a previously halted calculation. Set the CRCGO bit to start calculation. Write remaining data into the FIFO as space becomes available. When the calculation completes, CRCGO is automatically cleared. An interrupt will be generated if CRCISEL = 1. Read CRCWDATL and CRCWDATH for the result of the calculation. 4. 5. 6. 7. 21.1.4 INTERRUPT OPERATION 8. The module generates an interrupt that is configurable by the user for either of two conditions. If CRCISEL is ‘0’, an interrupt is generated when the VWORD bits make a transition from a value of ‘1’ to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will not generate an interrupt. Note that when an interrupt occurs, the CRC calculation would not yet be complete. The module will still need (PLEN + 1)/2 clock cycles after the interrupt is generated until the CRC calculation is finished. There are eight registers used to control programmable CRC operation: • • • • • • • • CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH 21.1.5 1. 2. TYPICAL OPERATION To use the module for a typical CRC calculation: Set the CRCEN bit to enable the module. Configure the module for desired operation: a) Program the desired polynomial using the CRCXORL and CRCXORH registers, and the PLEN bits. b) Configure the data width and shift direction using the DWIDTH and LENDIAN bits. c) Select the desired interrupt mode using the CRCISEL bit. The CRCCON1 and CRCCON2 registers (Register 21-1 and Register 21-2) control the operation of the module and configure the various settings. The CRCXOR registers (Register 21-3 and Register 21-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT registers are each register pairs that serve as buffers for the double-word input data, and CRC processed output, respectively.  2010 Microchip Technology Inc. DS39969B-page 299 PIC24FJ256DA210 FAMILY REGISTER 21-1: R/W-0 CRCEN bit 15 R-0, HSC CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR HC = Hardware Cleared bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-1, HSC CRCMPT R/W-0 CRCISEL R/W-0, HC CRCGO R/W-0 LENDIAN U-0 — U-0 — U-0 — bit 0 CRCCON1: CRC CONTROL 1 REGISTER U-0 — R/W-0 CSIDL R-0, HSC VWORD4 R-0, HSC VWORD3 R-0, HSC VWORD2 R-0, HSC VWORD1 R-0, HSC VWORD0 bit 8 HSC = Hardware Settable/Clearable bit CRCEN: CRC Enable bit 1 = Enables module 0 = Disables module; all state machines, pointers and CRCWDAT/CRCDATH reset; other SFRs are NOT reset Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN  7 or 16 when PLEN 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty bit 1 = FIFO is empty 0 = FIFO is not empty CRCISEL: CRC Interrupt Selection bit 1 = Interrupt on FIFO is empty; the final word of data is still shifting through the CRC 0 = Interrupt on shift is complete and results are ready CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC, starting with the LSb (little endian) 0 = Data word is shifted into the CRC, starting with the MSb (big endian) Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 DS39969B-page 300  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 21-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 PLEN4 R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 CRCCON2: CRC CONTROL 2 REGISTER U-0 — U-0 — R/W-0 DWIDTH4 R/W-0 DWIDTH3 R/W-0 DWIDTH2 R/W-0 DWIDTH1 R/W-0 DWIDTH0 bit 8 R/W-0 PLEN0 bit 0 Unimplemented: Read as ‘0’ DWIDTH: Data Word Width Configuration bits Configures the width of the data word (data word width – 1). Unimplemented: Read as ‘0’ PLEN: Polynomial Length Configuration bits Configures the length of the polynomial (polynomial length – 1). REGISTER 21-3: R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14 R/W-0 R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 — bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown X: XOR of Polynomial Term xn Enable bits Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39969B-page 301 PIC24FJ256DA210 FAMILY REGISTER 21-4: R/W-0 X31 bit 15 R/W-0 X23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 X22 R/W-0 X21 R/W-0 X20 R/W-0 X19 R/W-0 X18 R/W-0 X17 CRCXORH: CRC XOR HIGH REGISTER R/W-0 X29 R/W-0 X28 R/W-0 X27 R/W-0 X26 R/W-0 X25 R/W-0 X24 bit 8 R/W-0 X16 bit 0 X30 R/W-0 X: XOR of Polynomial Term xn Enable bits REGISTER 21-5: R/W-0 DATA15 bit 15 R/W-0 DATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCDATL: CRC DATA LOW REGISTER R/W-0 DATA13 R/W-0 DATA12 R/W-0 DATA11 R/W-0 DATA10 R/W-0 DATA9 R/W-0 DATA8 bit 8 R/W-0 DATA14 R/W-0 DATA6 R/W-0 DATA5 R/W-0 DATA4 R/W-0 DATA3 R/W-0 DATA2 R/W-0 DATA1 R/W-0 DATA0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DATA: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. REGISTER 21-6: R/W-0 DATA15 bit 15 R/W-0 DATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCDATH: CRC DATA HIGH REGISTER R/W-0 DATA13 R/W-0 DATA12 R/W-0 DATA11 R/W-0 DATA10 R/W-0 DATA9 R/W-0 DATA8 bit 8 R/W-0 DATA14 R/W-0 DATA6 R/W-0 DATA5 R/W-0 DATA4 R/W-0 DATA3 R/W-0 DATA2 R/W-0 DATA1 R/W-0 DATA0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown DATA: CRC Input Data bits Writing to this register fills the FIFO; reading from this register returns ‘0’. DS39969B-page 302  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 21-7: R/W-0, HSC SDATA15 bit 15 R/W-0, HSC SDATA7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0, HSC SDATA6 R/W-0, HSC SDATA5 R/W-0, HSC SDATA4 R/W-0, HSC SDATA3 R/W-0, HSC SDATA2 R/W-0, HSC SDATA1 CRCWDATL: CRC SHIFT LOW REGISTER R/W-0, HSC SDATA13 R/W-0, HSC SDATA12 R/W-0, HSC SDATA11 R/W-0, HSC SDATA10 R/W-0, HSC SDATA9 R/W-0, HSC SDATA8 bit 8 R/W-0, HSC SDATA0 bit 0 R/W-0, HSC SDATA14 SDATA: CRC Shift Register bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus. REGISTER 21-8: R/W-0, HSC SDATA31 bit 15 R/W-0, HSC SDATA23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 CRCWDATH: CRC SHIFT HIGH REGISTER R/W-0, HSC SDATA29 R/W-0, HSC SDATA28 R/W-0, HSC SDATA27 R/W-0, HSC SDATA26 R/W-0, HSC SDATA25 R/W-0, HSC SDATA24 bit 8 R/W-0, HSC SDATA30 R/W-0, HSC SDATA22 R/W-0, HSC SDATA21 R/W-0, HSC SDATA20 R/W-0, HSC SDATA19 R/W-0, HSC SDATA18 R/W-0, HSC SDATA17 R/W-0, HSC SDATA16 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown SDATA: CRC Input Data bits Writing to this register writes to the CRC Shift register through the CRC write bus. Reading from this register reads the CRC read bus.  2010 Microchip Technology Inc. DS39969B-page 303 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 304  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 22.0 Note: GRAPHICS CONTROLLER MODULE (GFX) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” (DS39731). The information in this data sheet supersedes the information in the FRM. Key features of the GFX module include: • Direct interface to three categories of display glasses: - Monochrome STN - Color STN - Color TFT • Programmable vertical and horizontal synchronization signals’ timing and display clock frequency to meet display’s frame rates • Optional internal or external display buffer to accommodate different types of display resolution • Graphic hardware accelerators: - Character Graphics Processing Unit (CHRGPU) - Rectangle Copy Graphics Processing Unit (RCCGPU) - Inflate Processing Unit (IPU) • 256 Entries Color Look-up Table (CLUT) • Supports 1/2/4/8/16 bits-per-pixel (bpp) color depth • Programmable display resolution • Supports multiple display interfaces: - 4/8/16-bit Monochrome STN - 4/8/16-bit Color STN - 9/12/18/24-bit color TFT (18 and 24-bit displays are connected as 16-bit 5-6-5 RGB color format) The Graphics Controller (GFX) module is specifically designed to directly interface with the display glasses, with a built-in analog drive, to individually control pixels in the screen. The module also provides an accelerated rendering of vertical and horizontal lines, rectangles, copying of rectangular area between different locations on the screen, drawing texts and decompressing packed data. The use of the accelerated rendering is performed using command registers. Once initiated, the hardware will perform the rendering, and the software can either poll the status, or use the interrupts to continue rendering of the succeeding shapes. FIGURE 22-1: GRAPHICS MODULE OVERVIEW PIC24F Graphics Controller Module Display Interface Clock (DISPCLK) System Clock Registers and Control Interface Display Module Interface GD VSYNC RCCGPU CHRGPU IPU GEN CLUT Memory Request Arbiter GPWR GCLK System RAM  2010 Microchip Technology Inc. DS39969B-page 305 To Display Glass Graphics Controller Clock (G1CLK) HSYNC GPU Command Interface PIC24FJ256DA210 FAMILY 22.1 GFX Module Registers G1CMDL: GPU COMMAND LOW REGISTER R/W-0 GCMD14 R/W-0 GCMD13 R/W-0 GCMD12 R/W-0 GCMD11 R/W-0 GCMD10 R/W-0 GCMD9 R/W-0 GCMD8 bit 8 R/W-0 GCMD6 R/W-0 GCMD5 R/W-0 GCMD4 R/W-0 GCMD3 R/W-0 GCMD2 R/W-0 GCMD1 R/W-0 GCMD0 bit 0 REGISTER 22-1: R/W-0 GCMD15 bit 15 R/W-0 GCMD7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GCMD: Low GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD). Writes to this register will not trigger the loading of GCMD to the command FIFO. For command FIFO loading, see the G1CMDH register description. REGISTER 22-2: R/W-0 GCMD31 bit 15 R/W-0 GCMD23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 G1CMDH: GPU COMMAND HIGH REGISTER R/W-0 R/W-0 GCMD29 R/W-0 GCMD28 R/W-0 GCMD27 R/W-0 GCMD26 R/W-0 GCMD25 R/W-0 GCMD24 bit 8 R/W-0 R/W-0 GCMD21 R/W-0 GCMD20 R/W-0 GCMD19 R/W-0 GCMD18 R/W-0 GCMD17 R/W-0 GCMD16 bit 0 GCMD30 GCMD22 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown GCMD: High GPU Command bits The full 32-bit command is defined by G1CMDH and G1CMDL (GCMD). A word write to the G1CMDH register triggers the loading of GCMD to the command FIFO. Byte writes to the G1CMDH are allowed but only a high byte write will trigger the command loading to the FIFO. Low byte write to this register will only update the G1CMDH bits. DS39969B-page 306  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-3: R/W-0 G1EN bit 15 R/W-0 PUBPP2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PUBPP1 R/W-0 PUBPP0 R-0, HSC GCMDCNT4 R-0, HSC GCMDCNT3 R-0, HSC GCMDCNT2 R-0, HSC GCMDCNT1 U-0 — G1CON1: DISPLAY CONTROL REGISTER 1 R/W-0 G1SIDL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R-0, HSC GCMDCNT0 bit 0 GCMDWMK4 GCMDWMK3 GCMDWMK2 GCMDWMK1 GCMDWMK0 G1EN: Module Enable bit 1 = Display module is enabled 0 = Display module is disabled Unimplemented: Read as ‘0’ G1SIDL: Stop in Idle bit 1 = Display module stops in Idle mode 0 = Display module does not stop in Idle mode GCMDWMK: Command FIFO Watermark bits Sets the command watermark level that triggers the CMDLVIF interrupt and sets the CMDLV flag; GCMDWMK (10000 = Reserved) 10000 = If the number of commands present in the FIFO goes from 16 to 15 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 01111 = f the number of commands present in the FIFO goes from 15 to 14 commands, CMDLVIF interrupt will trigger and CMDLV flag will be set . . . 00001 = If the number of commands present in the FIFO goes from 1 to 0 commands, the CMDLVIF interrupt will trigger and the CMDLV flag will be set 00000 = CMDLVIF interrupt will not trigger and the CMDLV flag will not be set PUBPP: GPU bits-per-pixel (bpp) Setting bits Other = Reserved 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per -pixel 000 = 1-bit -per-pixel GCMDCNT: Command FIFO Occupancy Status bits When the FIFO is full, any additional commands written to the FIFO are discarded. 10000 = 16 commands are present in the FIFO 01111 = 15 commands are present in the FIFO . . . 0001 = 1 command is present in the FIFO 0000 = 0 command is present in the FIFO bit 14 bit 13 bit 12-8 bit 7-5 bit 4-0  2010 Microchip Technology Inc. DS39969B-page 307 PIC24FJ256DA210 FAMILY REGISTER 22-4: R/W-0 DPGWDTH1 bit 15 R/W-0 DPBPP2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 DPBPP1 R/W-0 DPBPP0 U-0 — U-0 — R/W-0 DPMODE2 R/W-0 DPMODE1 G1CON2: DISPLAY CONTROL REGISTER 2 R/W-0 R/W-0 DPSTGER1 R/W-0 DPSTGER0 U-0 — U-0 — R/W-0 DPTEST1 R/W-0 DPTEST0 bit 8 R/W-0 DPMODE0 bit 0 DPGWDTH0 DPGWDTH: STN Display Glass Data Width bits 11 = Reserved 10 = 16 bits wide 01 = 8 bits wide 00 = 4 bits wide These bits have no effect on TFT mode. TFT display glass data width is always assumed to be 16 bits wide. DPSTGER: Display Data Timing Stagger bits 11 = Delays of the display data are staggered in groups: Bit group 0: 0 4 8 12 – not delayed Bit group 1: 1 5 9 13 – delayed by ½ GPUCLK cycle Bit group 2: 2 6 10 14 – delayed by full GPUCLK cycle Bit group 3: 3 7 11 15 – delayed by 1 ½ GPUCLK cycle 10 = Even bits of the display data are delayed by 1 full GPUCLK cycle; odd bits are not delayed 01 = Odd bits of the display data are delayed by ½ GPUCLK cycle; even bits are not delayed 00 = Display data timing is all synchronized on one clock GPUCLK edge Unimplemented: Read as ‘0’ DPTEST: Display Test Pattern Generator bits 11 = Borders 10 = Bars 01 = Black screen 00 = Normal Display mode; test patterns are off DPBPP: Display bits-per-pixel Setting bits This setting must match the GPU bits-per-pixel set in PUBPP (G1CON1). 100 = 16 bits-per-pixel 011 = 8 bits-per-pixel 010 = 4 bits-per-pixel 001 = 2 bits-per-pixel 000 = 1 bit-per-pixel Other = Reserved Unimplemented: Read as ‘0’ DPMODE: Display Glass Type bits 011 = Color STN type 010 = Mono STN type 001 = TFT type 000 = Display off Other = Reserved bit 13-12 bit 11-10 bit 9-8 bit 7-5 bit 4-3 bit 2-0 DS39969B-page 308  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 22-5: U-0 — bit 15 R/W-0 DPCLKPOL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 bit 9 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 DPENPOL R/W-0 DPVSPOL R/W-0 DPHSPOL R/W-0 DPPWROE R/W-0 DPENOE R/W-0 DPVSOE G1CON3: DISPLAY CONTROL REGISTER 3 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DPPINOE R/W-0 DPPOWER bit 8 R/W-0 DPHSOE bit 0 Unimplemented: Read as ‘0’ DPPINOE: Display Pin Output Pad Enable bit DPPINOE is the master output enable and must be set to allow GDBEN, DPENOE, DPPWROE, DPVSOE and DPHSOE to enable the associated pads 1 = Enable display output pads 0 = Disable display output signals as set by GDBEN Pins used by the signals are assigned to the next enabled module that uses the same pins. For data signals, GDBEN can be used to disable or enable specific data signals while DPPINOE is set. DPPOWER: Display Power-up Power-Down Sequencer Control bit Refer to the “PIC24F Family Reference Manual”, Section 43. “Graphics Controller Module (GFX)” for details. 1 = Set Display Power Sequencer Control port (GPWR) to ‘1’ 0 = Set Power Control Sequencer signal (GPWR) ‘0’ DPCLKPOL: Display Glass Clock (GCLK) Polarity bit 1 = Display latches data on the positive edge of GCLK 0 = Display latches data on the negative edge of GCLK DPENPOL: Display Enable Signal (GEN) Polarity bit For TFT mode (DPMODE (G1CON2) = 001): 1 = Active-high (GEN) 0 = Active-low (GEN) For STN mode (DPMODE (G1CON2) = 010 or 011): 1 = GEN connects to the shift clock input of the display (Shift Clock mode) 0 = GEN connects to the MOD input of the display (Line/Frame Toggle mode) DPVSPOL: Display Vertical Synchronization (VSYNC) Polarity bit 1 = Active-high (VSYNC) 0 = Active-low (VSYNC) DPHSPOL: Display Horizontal Synchronization (HSYNC) Polarity bit 1 = Active-high (HSYNC) 0 = Active-low (HSYNC) DPPWROE: Display Power-up/Power-Down Sequencer Control port (GPWR) enable bit 1 = GPWR port is enabled (pin controlled by the DPPOWER bit (G1CON3)) 0 = GPWR port is disabled (pin can be used as an ordinary I/O) DPENOE: Display Enable Port Enable bit 1 = GEN port is enabled 0 = GEN port is disabled bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2  2010 Microchip Technology Inc. DS39969B-page 309 PIC24FJ256DA210 FAMILY REGISTER 22-5: bit 1 G1CON3: DISPLAY CONTROL REGISTER 3 (CONTINUED) DPVSOE: Display Vertical Synchronization Port Enable bit 1 = VSYNC port is enabled 0 = VSYNC port is disabled DPHSOE: Display Horizontal Synchronization Port Enable bit 1 = HSYNC port is enabled 0 = HSYNC port is disabled bit 0 REGISTER 22-6: R-0, HSC PUBUSY bit 15 R-0, HSC IPUBUSY bit 7 Legend: R = Readable bit -n = Value at POR bit 15 — G1STAT: GFX STATUS REGISTER U-0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R-0, HSC RCCBUSY R-0, HSC CHRBUSY R-0, HSC VMRGN R-0, HSC HMRGN R-0, HSC CMDLV R-0, HSC CMDFUL R-0, HSC CMDMPT bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown PUBUSY: Processing Units are Busy Status bit This bit is logically equivalent to the ORed combination of IPUBUSY, RCCBUSY or CHRBUSY. 1 = At least one processing unit is busy 0 = None of the processing units are busy Unimplemented: Read as ‘0’ IPUBUSY: Inflate Processing Unit Busy Status bit 1 = IPU is busy 0 = IPU is not busy RCCBUSY: Rectangle Copy Graphics Processing Unit Busy Status bit 1 = RCCGPU is busy 0 = RCCGPU is not busy CHRBUSY: Character Graphics Processing Unit Busy Status bit 1 = CHRGPU is busy 0 = CHRGPU is not busy VMRGN: Vertical Blanking Status bit 1 = Display interface is in the vertical blanking period 0 = Display interface is not in the vertical blanking period HMRGN: Horizontal Blanking Status bit 1 = Display interface is in the horizontal blanking period 0 = Display interface is not in the horizontal blanking period CMDLV: Command Watermark Level Status bit The number of commands in the command FIFO changed from equal (=) to the command watermark value to less than ( CxINA Compare CEN = 1, CCH = 00 VINVIN+ CVREFM = xx COE Comparator CxINC > CxINA Compare CEN = 1, CCH = 01 VINVIN+ CVREFM = xx COE CXINB CXINA Cx CxOUT Pin CXINC CXINA Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CCH = 10 VINVIN+ CVREFM = xx COE Comparator VBG > CxINA Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 00 COE CXIND CXINA Cx CxOUT Pin VBG CXINA Cx CxOUT Pin Comparator VBG > CxINA Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 01 COE Comparator VBG > CxINA Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 10 COE VBG/2 CXINA Cx CxOUT Pin VBG/6 CXINA Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 11 COE VREF+ CXINA Cx CxOUT Pin DS39969B-page 336  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 24-3: CEN = 1, CCH = 00 VINVIN+ INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 0 Comparator CxINC > CVREF Compare CEN = 1, CCH = 01 COE CXINC VINVIN+ CVREFM = xx COE CVREFM = xx Comparator CxINB > CVREF Compare CXINB CVREF Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator CxIND > CVREF Compare CEN = 1, CCH = 10 VINVIN+ CVREFM = xx COE Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 00 COE CXIND CVREF VBG Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 01 COE Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 10 COE VBG/2 CVREF VBG/6 Cx CxOUT Pin Cx CxOUT Pin CVREF Comparator CxIND > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 11 COE VREF+ CVREF Cx CxOUT Pin FIGURE 24-4: INDIVIDUAL COMPARATOR CONFIGURATIONS WHEN CREF = 1 AND CVREFP = 1 Comparator CxINC > CVREF Compare CEN = 1, CCH = 01 VINVIN+ CVREFM = xx COE CVREFM = xx COE CXINC Comparator CxINB > CVREF Compare CEN = 1, CCH = 00 VINVIN+ CXINB VREF+ Cx CxOUT Pin Cx CxOUT Pin VREF+ Comparator CxIND > CVREF Compare CEN = 1, CCH = 10 VINVIN+ CVREFM = xx COE Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 00 COE CXIND VREF+ VBG Cx CxOUT Pin Cx CxOUT Pin VREF+ Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 01 COE Comparator VBG > CVREF Compare CEN = 1, CCH = 11 VINVIN+ CVREFM = 10 COE VBG/2 VREF+ VBG/6 Cx CxOUT Pin Cx CxOUT Pin VREF+  2010 Microchip Technology Inc. DS39969B-page 337 PIC24FJ256DA210 FAMILY REGISTER 24-1: R/W-0 CEN bit 15 R/W-0 EVPOL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 CPOL U-0 — U-0 — U-0 — R/W-0, HS CEVT R-0, HSC COUT bit 8 R/W-0 CCH0 bit 0 COE R/W-0 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as ‘0’ CEVT: Comparator Event bit 1 = Comparator event that is defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt is generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt is generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt is generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7-6 bit 5 DS39969B-page 338  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 24-1: bit 4 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to the internal CVREF voltage 0 = Non-inverting input connects to the CXINA pin Unimplemented: Read as ‘0’ CCH: Comparator Channel Select bits 11 = Inverting input of the comparator connects to the internal selectable reference voltage specified by the CVREFM bits in the CVRCON register 10 = Inverting input of the comparator connects to the CXIND pin 01 = Inverting input of the comparator connects to the CXINC pin 00 = Inverting input of the comparator connects to the CXINB pin bit 3-2 bit 1-0 REGISTER 24-2: R/W-0 CMIDL bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CMSTAT: COMPARATOR MODULE STATUS REGISTER U-0 — U-0 — U-0 — U-0 — R-0, HSC C3EVT R-0, HSC C2EVT R-0, HSC C1EVT bit 8 U-0 — U-0 — U-0 — U-0 — R-0, HSC C3OUT R-0, HSC C2OUT R-0, HSC C1OUT bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as ‘0’ C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). Unimplemented: Read as ‘0’ C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39969B-page 339 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 340  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 25.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 19. “Comparator Module” (DS39710). The information in this data sheet supersedes the information in the FRM. 25.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 25-1). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. FIGURE 25-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R CVR CVREN R R R 16-to-1 MUX R 16 Steps CVREF CVROE R R R CVREF Pin CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS  2010 Microchip Technology Inc. DS39969B-page 341 PIC24FJ256DA210 FAMILY REGISTER 25-1: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — R/W-0 CVREFP R/W-0 CVREFM1 R/W-0 CVREFM0 bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as ‘0’ CVREFP: Voltage Reference Select bit (valid only when CREF is ‘1’) 1 = VREF+ is used as a reference voltage to the comparators 0 = The CVR (4-bit DAC) within this module provides the the reference voltage to the comparators CVREFM: Band Gap Reference Source Select bits (valid only when CCH = 11) 00 = Band gap voltage is provided as an input to the comparators 01 = Band gap voltage divided-by-two is provided as an input to the comparators 10 = Band gap voltage divided-by-six is provided as an input to the comparators 11 = VREF+ pin is provided as an input the comparators CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on the CVREF pin 0 = CVREF voltage level is disconnected from the CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR: Comparator VREF Value Selection 0  CVR  15 bits When CVRR = 1: CVREF = (CVR/ 24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR/32)  (CVRSRC) bit 9-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 DS39969B-page 342  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 26.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724). The information in this data sheet supersedes the information in the FRM. source polarity selection, and edge sequencing. The CTMUICON register controls the selection and trim of the current source. 26.1 Measuring Capacitance The Charge Time Measurement Unit (CTMU) is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: dV C = I  -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 26-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers: CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge FIGURE 26-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter ANx ANY Current Source CAPP RPR  2010 Microchip Technology Inc. DS39969B-page 343 PIC24FJ256DA210 FAMILY 26.2 Measuring Time Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 26-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. When the module is configured for pulse generation delay by setting the TGEN (CTMUCON) bit, the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 26-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. 26.3 Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 26-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source ANx FIGURE 26-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39969B-page 344  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 26-1: R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0, HSC EDG2STAT CTMUCON: CTMU CONTROL REGISTER U-0 — R/W-0 CTMUSIDL R/W-0 TGEN(1) R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0, HSC EDG1STAT bit 0 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as ‘0’ CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when the device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 is programmed for a positive edge response 0 = Edge 2 is programmed for a negative edge response EDG2SEL: Edge 2 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 is programmed for a positive edge response 0 = Edge 1 is programmed for a negative edge response If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. bit 14 bit 13 bit 12 bit 10 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4 Note 1:  2010 Microchip Technology Inc. DS39969B-page 345 PIC24FJ256DA210 FAMILY REGISTER 26-1: bit 3-2 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1SEL: Edge 1 Source Select bits 11 = CTEDG1 pin 10 = CTEDG2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn/RPIn pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. bit 1 bit 0 Note 1: REGISTER 26-2: R/W-0 ITRIM5 bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 R/W-0 ITRIM4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 . . . 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current . . . 100010 100001 = Maximum negative change from nominal current IRNG: Current Source Range Select bits 11 = 100  Base Current 10 = 10  Base Current 01 = Base current level (0.55 A nominal) 00 = Current source is disabled Unimplemented: Read as ‘0’ bit 9-8 bit 7-0 DS39969B-page 346  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”. The information in this data sheet supersedes the information in the FRMs. • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) 27.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ256DA210 FAMILY DEVICES In PIC24FJ256DA210 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 27-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. PIC24FJ256DA210 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming™ In-Circuit Emulation When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be ‘0000 0000’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘0’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. 27.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 27-1 through Register 27-6. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 27-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256DA210 FAMILY DEVICES Configuration Word Addresses 1 157FEh 2ABFEh 2 157FCh 2ABFCh 3 157FAh 2ABFAh 4 157F8h 2ABF8h Device PIC24FJ128DAXXX PIC24FJ256DAXXX  2010 Microchip Technology Inc. DS39969B-page 347 PIC24FJ256DA210 FAMILY REGISTER 27-1: U-0 — bit 23 r-x reserved bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 bit 14 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/PO-1 WINDIS R/PO-1 ALTVREF(1) R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 reserved R/PO-1 ICS1 CW1: FLASH CONFIGURATION WORD 1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0 Unimplemented: Read as ‘1’ Reserved: The value is unknown; program as ‘0’ JTAGEN: JTAG Port Enable bit 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are not allowed DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Always maintain as ‘1’ ICS: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’ ALTVREF: Alternate VREF Pin Selection bit(1) 1 = VREF is on a default pin (VREF+ on RA10 and VREF- on RA9) 0 = VREF is on an alternate pin (VREF+ on RB0 and VREF- on RB1) Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1). bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 Note 1: DS39969B-page 348  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-1: bit 4 CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 WDTPS: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 Unimplemented in 64-pin devices, maintain at ‘1’ (VREF+ on RB0 and VREF- on RB1). bit 3-0 Note 1:  2010 Microchip Technology Inc. DS39969B-page 349 PIC24FJ256DA210 FAMILY REGISTER 27-2: U-0 — bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY r-1 reserved r-1 reserved R/PO-1 POSCMD1 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 R/PO-1 PLL96MHZ R/PO-1 FNOSC2 R/PO-1 FNOSC1 CW2: FLASH CONFIGURATION WORD 2 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0 Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled PLLDIV: 96 MHz PLL Prescaler Select bits 111 = Oscillator input is divided by 12 (48 MHz input) 110 = Oscillator input is divided by 8 (32 MHz input) 101 = Oscillator input is divided by 6 (24 MHz input) 100 = Oscillator input is divided by 5 (20 MHz input) 011 = Oscillator input is divided by 4 (16 MHz input) 010 = Oscillator input is divided by 3 (12 MHz input) 001 = Oscillator input is divided by 2 (8 MHz input) 000 = Oscillator input is used directly (4 MHz input) PLL96MHZ: 96 MHz PLL Start-Up Enable bit 1 = 96 MHz PLL is enabled automatically on start-up 0 = 96 MHz PLL is software controlled (can be enabled by setting the PLLEN bit in CLKDIV) FNOSC: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 DS39969B-page 350  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-2: bit 4 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed Reserved: Always maintain as ‘1’ POSCMD: Primary Oscillator Configuration bits 11 = Primary oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected bit 3-2 bit 1-0 REGISTER 27-3: U-0 — bit 23 R/PO-1 WPEND bit 15 R/PO-1 WPFP7 bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15 CW3: FLASH CONFIGURATION WORD 3 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 R/PO-1 WPCFG R/PO-1 WPDIS R/PO-1 ALTPMP(1) R/PO-1 WUTSEL1 R/PO-1 WUTSEL0 R/PO-1 SOSCSEL1 R/PO-1 SOSCSEL0 bit 8 R/PO-1 WPFP6 R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 WPFP0 bit 0 PO = Program-Once bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘1’ WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment upper boundary is at the last page of program memory; the lower boundary is the code page specified by WPFP 0 = Protected code segment lower boundary is at the bottom of the program memory (000000h); upper boundary is the code page specified by WPFP WPCFG: Configuration Word Code Page Write Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not write-protected(3) 0 = Last page and Flash Configuration Words are write-protected, provided WPDIS = ‘0’ WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by the WPEND, WPCFG and WPFPx Configuration bits ALTPMP: Alternate EPMP Pin Mapping bit(1) 1 = EPMP pins are in default location mode 0 = EPMP pins are in alternate location mode Unimplemented in 64-pin devices, maintain at ‘1’. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected. bit 14 bit 13 bit 12 Note 1: 2: 3:  2010 Microchip Technology Inc. DS39969B-page 351 PIC24FJ256DA210 FAMILY REGISTER 27-3: bit 11-10 CW3: FLASH CONFIGURATION WORD 3 (CONTINUED) WUTSEL: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use SOSCSEL: SOSC Selection Configuration bits 11 = Secondary oscillator is in Default (high drive strength) Oscillator mode 10 = Reserved; do not use 01 = Secondary oscillator is in Low-Power (low drive strength) Oscillator mode 00 = External clock (SCLKI) or Digital I/O mode(2) WPFP: Write Protected Code Segment Boundary Page bits Designates the 512 instruction words page boundary of the protected code segment. If WPEND = 1: Specifies the lower page boundary of the code-protected segment; the last page being the last implemented page in the device. If WPEND = 0: Specifies the upper page boundary of the code-protected segment; Page 0 being the lower boundary. Unimplemented in 64-pin devices, maintain at ‘1’. Ensure that the SCLKI pin is made a digital input while using this configuration, see Table 10-1. Regardless of WPCFG status, if WPEND = 1 or if WPFP corresponds to the Configuration Word’s page, the Configuration Word’s page is protected. bit 9-8 bit 7-0 Note 1: 2: 3: REGISTER 27-4: U-0 — bit 23 r-1 reserved bit 15 r-1 reserved bit 7 Legend: R = Readable bit -n = Value at POR bit 23-16 bit 15-0 CW4: FLASH CONFIGURATION WORD 4 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 r-1 r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved bit 8 r-1 r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved r-1 reserved bit 0 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown reserved reserved Unimplemented: Read as ‘0’ Reserved: Always maintain as ‘1’ DS39969B-page 352  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY REGISTER 27-5: U-0 — bit 23 R FAMID7 bit 15 R DEV7 bit 7 Legend: R = Readable bit bit 23-16 bit 15-8 bit 7-0 Unimplemented: Read as ‘1’ FAMID: Device Family Identifier bits 01000001 = PIC24FJ256DA210 family DEV: Individual Device Identifier bits 00001000 = PIC24FJ128DA206 00001001 = PIC24FJ128DA106 00001010 = PIC24FJ128DA210 00001011 = PIC24FJ128DA110 00001100 = PIC24FJ256DA206 00001101 = PIC24FJ256DA106 00001110 = PIC24FJ256DA210 00001111 = PIC24FJ256DA110 U = Unimplemented bit R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R FAMID0 bit 8 DEVID: DEVICE ID REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16  2010 Microchip Technology Inc. DS39969B-page 353 PIC24FJ256DA210 FAMILY REGISTER 27-6: U-0 — bit 23 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit bit 23-4 bit 3-0 Unimplemented: Read as ‘0’ REV: Device revision identifier bits U = Unimplemented bit U-0 — U-0 — U-0 — R REV3 R REV2 R REV1 R REV0 bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — DEVREV: DEVICE REVISION REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 16 U-0 — bit 8 27.2 On-Chip Voltage Regulator All PIC24FJ256DA210 family devices power their core digital logic at a nominal 1.8V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256DA210 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VCAP pin (Figure 27-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 30.1 “DC Characteristics”. Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt to trigger an orderly shutdown. FIGURE 27-1: CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V(1) PIC24FJXXXDA1/DA2 VDD ENVREG VCAP Regulator Enabled (ENVREG tied to VDD): CEFC (10 F typ) Note 1: VSS 27.2.1 VOLTAGE REGULATOR LOW-VOLTAGE DETECTION 27.2.2 This is a typical operating voltage. Refer to Section 30.1 “DC Characteristics” for the full operating ranges of VDD. When the on-chip regulator is enabled, it provides a constant voltage of 1.8V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.1V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels. In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the Brown-out Reset occurs. Then the regulator output follows VDD with a typical voltage drop of 300 mV. To provide information about when the regulator voltage starts reducing, the on-chip regulator includes a simple Low-Voltage Detect circuit, which sets the ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TVREG, code execution is disabled. TVREG is applied every time the device resumes operation after any power-down, including Sleep mode. TVREG is determined by the status of the VREGS bit (RCON) and the WUTSEL Configuration bits (CW3). Refer to Section 30.0 “Electrical Characteristics” for more information on TVREG. DS39969B-page 354  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.2.3 ON-CHIP REGULATOR AND BOR 27.3 Watchdog Timer (WDT) When the on-chip regulator is enabled, PIC24FJ256DA210 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the output level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR (RCON) flag bit. The brown-out voltage specifications are provided in Section 7. “Reset” (DS39712) in the “PIC24F Family Reference Manual”. Note: For more information, see Section 30.0 “Electrical Characteristics”. The information in this data sheet supersedes the information in the FRM. For PIC24FJ256DA210 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT Time-out period (TWDT) of 1 ms in 5-bit mode or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS Configuration bits (CW1), which allows the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds, can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE (RCON) bits will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 27.2.4 VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator can be made to enter Standby mode on its own whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON). Clearing the VREGS bit enables the Standby mode. When waking up from Standby mode, the regulator needs to wait for TVREG to expire before wake-up. The regulator wake-up time required for Standby mode is controlled by the WUTSEL (CW3) Configuration bits. The regulator wake-up time is lower when WUTSEL = 01, and higher when WUTSEL = 11. Refer to the TVREG specification in Table 30-10 for regulator wake-up time. When the regulator’s Standby mode is turned off (VREGS = 1), the device wakes up without waiting for TVREG. However, with the VREGS bit set, the power consumption while in Sleep mode will be approximately 40 A higher than what it would be if the regulator was allowed to enter Standby mode.  2010 Microchip Technology Inc. DS39969B-page 355 PIC24FJ256DA210 FAMILY 27.3.1 WINDOWED OPERATION 27.3.2 CONTROL REGISTER The Watchdog Timer has an optional Fixed-Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN Control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 27-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode DS39969B-page 356  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 27.4 Program Verification and Code Protection The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page in addition to the pages selected by the WPEND and WPFP bits setting. This is useful in circumstances where write protection is needed for both the code segment in the bottom of the memory and the Flash Configuration Words. The various options for segment code protection are shown in Table 27-2. PIC24FJ256DA210 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 27.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256DA210 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked. 27.4.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ256DA210 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half.  2010 Microchip Technology Inc. DS39969B-page 357 PIC24FJ256DA210 FAMILY 27.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code segment protection setting. TABLE 27-2: WPDIS 1 0 CODE SEGMENT PROTECTION CONFIGURATION OPTIONS WPCFG x x Write/Erase Protection of Code Segment No additional protection is enabled; all program memory protection is configured by GCP and GWRP. Addresses from the first address of the code page are defined by WPFP through the end of implemented program memory (inclusive), write/erase protected, including Flash Configuration Words. Address 000000h through the last address of the code page is defined by WPFP (inclusive), write/erase protected. Address 000000h through the last address of code page is defined by WPFP (inclusive), write/erase protected and the last page, including Flash Configuration Words are write/erase protected. Segment Configuration Bits WPEND X 1 0 0 0 0 1 0 27.5 JTAG Interface 27.7 In-Circuit Debugger PIC24FJ256DA210 family devices implement a JTAG interface, which supports boundary scan device testing. 27.6 In-Circuit Serial Programming™ PIC24FJ256DA210 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power (VDD), ground (VSS) and MCLR. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. When MPLAB® ICD 3 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. DS39969B-page 358  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 28.0 DEVELOPMENT SUPPORT 28.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39969B-page 359 PIC24FJ256DA210 FAMILY 28.2 MPLAB C Compilers for Various Device Families 28.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families 28.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS39969B-page 360  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 28.7 MPLAB SIM Software Simulator 28.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip’s most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easy-to-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.8 MPLAB REAL ICE In-Circuit Emulator System 28.10 PICkit 3 In-Circuit Debugger/Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer’s PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with in-circuit debugger systems (RJ11) or with the new high-speed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. DS39969B-page 361 PIC24FJ256DA210 FAMILY 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 28.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39969B-page 362  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 29.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture and is not intended to be a comprehensive reference source. The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 29-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 29-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’)  2010 Microchip Technology Inc. DS39969B-page 363 PIC24FJ256DA210 FAMILY TABLE 29-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit Bit Selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0000h...1FFFh} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16383} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39969B-page 364  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG BTSC BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None 1 None (2 or 3) 1 None (2 or 3)  2010 Microchip Technology Inc. DS39969B-page 365 PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CALL CALL CLR CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CP0 CP0 CPB CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW.B DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if  Wn = Decimal Adjust Wn f = f –1 WREG = f –1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39969B-page 366  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic GOTO GOTO GOTO INC INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP NOP NOPR POP POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None  2010 Microchip Technology Inc. DS39969B-page 367 PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic PWRSAV RCALL PWRSAV RCALL RCALL REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP TBLRDH TBLRDH f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn Read Prog to Wd # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None DS39969B-page 368  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 29-2: Assembly Mnemonic TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N  2010 Microchip Technology Inc. DS39969B-page 369 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 370  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY 30.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256DA210 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256DA210 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD < 3.0V............................................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS when VDD > 3.0V..................................................... -0.3V to (+5.5V) Voltage on VBUS pin with respect to VSS, independent of VDD or VUSB ................................................. -0.3V to (+5.5V) Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1) ................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 30-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39969B-page 371 PIC24FJ256DA210 FAMILY 30.1 DC Characteristics PIC24FJ256DA210 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) FIGURE 30-1: 3.6V PIC24FJXXXDA1 Voltage (VDD) 2.2V VBOR 3.6V 2.2V VBOR Frequency Note: VCAP (nominal On-Chip Regulator output voltage) = 1.8V. 32 MHz TABLE 30-1: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA PD PDMAX Min -40 -40 Typ — — PINT + PI/O (TJMAX – TA)/JA Max +125 +85 Unit °C °C W W PIC24FJ256DA210 family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation (with ENVREG = 1): Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation TABLE 30-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA Typ 69.4 76.6 28.0 40.2 Max — — — — Unit °C/W °C/W °C/W °C/W Note (Note 1) (Note 1) (Note 1) (Note 1) Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Package Thermal Resistance, 9x9x0.9 mm QFN Package Thermal Resistance, 10x10x1.1 mm BGA Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39969B-page 372  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VCAP(2) DC12 DC16 VDR VPOR RAM Data Retention Voltage(1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal Brown-out Reset Voltage on VDD Transition, High-to-Low LVD Trip Voltage VBOR — 1.5 Vss — 1.8V — — 3.6 — — — V V V V Regulator enabled Regulator enabled Characteristic DC17 SVDD 0.05 — — V/ms 0-3.3V in 66 ms 0-2.5V in 50 ms Regulator enabled VBOR 2.0 2.10 2.2 V VLVD Note 1: 2: — VBOR + 0.10 — V This is the limit to which the RAM data can be retained, while the on-chip regulator output voltage starts following the VDD. This is the on-chip regulator output voltage specification.  2010 Microchip Technology Inc. DS39969B-page 373 PIC24FJ256DA210 FAMILY TABLE 30-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20D DC20E DC20F DC23D DC23E DC23F DC24D DC24E DC24F DC31D DC31E DC31F Note 1: 2: Typical(1) Operating Current (IDD)(2) 0.8 0.8 0.8 3.0 3.0 3.0 12.0 12.0 12.0 55 55 135 1.3 1.3 1.3 4.8 4.8 4.8 18 18 18 95 95 225 mA mA mA mA mA mA mA mA mA A A A -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.3V(3) LPRC (31 kHz) 3.3V(3) 16 MIPS 3.3V(3) 4 MIPS 3.3V(3) 1 MIPS 3: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. DS39969B-page 374  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40D DC40E DC40F DC43D DC43E DC43F DC47D DC47E DC47F DC50D DC50E DC50F DC51D DC51E DC51F Note 1: 2: Typical(1) Idle Current (IIDLE)(2) 170 170 220 0.6 0.6 0.7 2.3 2.3 2.4 0.8 0.8 1.0 40.0 40.0 120.0 320 320 380 1.2 1.2 1.2 4.8 4.8 4.8 1.8 1.8 1.8 85 85 210 A A A mA mA mA mA mA mA mA mA mA A A A -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.3V (3) 3.3V(3) 1 MIPS 3.3V(3) 4 MIPS 3.3V(3) 16 MIPS FRC (4 MIPS) 3.3V(3) LPRC (31 kHz) 3: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off; OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled.  2010 Microchip Technology Inc. DS39969B-page 375 PIC24FJ256DA210 FAMILY TABLE 30-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60D DC60E DC60H DC60F DC61D DC61E DC61H DC61F DC62D DC62E DC62H DC62F DC63D DC63E DC63H DC63F Note 1: 2: Typical(1) Power-Down Current (IPD)(2) 20.0 20.0 55.0 95.0 1.0 1.0 1.0 2.5 1.5 1.5 1.5 8.0 4.0 4.0 6.5 12.0 45 45 105 185 3.5 3.5 3.5 6.5 6 6 6 18 18 18 18 25 A A A A A A A A A A A A A A A A -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C -40°C +25°C +60°C +85°C 3.3V(3) 3.3V(3) Low drive strength, 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL = 01(4) 3.3V(3) 31 kHz LPRC oscillator with RTCC, WDT or Timer1:ILPRC(4) 3.3V(3) Base power-down current(4) 32 kHz crystal with RTCC or Timer1: ISOSC; SOSCSEL = 11(4) 3: 4: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with the device in Sleep mode (all peripherals and clocks are shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator enabled (ENVREG tied to VDD). Brown-out Reset (BOR) is enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39969B-page 376  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbo No. l VIL DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Characteristic Input Low Voltage(3) I/O Pins with ST Buffer I/O Pins with TTL Buffer MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2C™ Buffer: I/O Pins with SMBus Buffer: Input High Voltage(3) I/O Pins with ST Buffer: with Analog Functions, Digital Only I/O Pins with TTL Buffer: with Analog Functions, Digital Only MCLR OSCI (XT mode) OSCI (HS mode) I/O Pins with I2C™ Buffer: with Analog Functions, Digital Only I/O Pins with SMBus Buffer: with Analog Functions, Digital Only ICNPU ICNPD IIL DI50 DI51 DI55 DI56 Note 1: 2: 3: CNxx Pull-up Current CNxx Pull-down Current Input Leakage Current(2) I/O Ports Analog Input Pins MCLR OSCI/CLKI — — — — — — — — +1 +1 +1 +1 A A A A VSS  VPIN  VDD, pin at high-impedance VSS  VPIN  VDD, pin at high-impedance VSS VPIN VDD VSS VPIN VDD, EC, XT and HS modes 0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 150 15 350 70 — — — — — — — — — VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 550 150 V V V V V V V V V 2.5V  VPIN  VDD V V A A VDD = 3.3V, VPIN = VSS VDD = 3.3V, VPIN = VDD VSS VSS VSS VSS VSS VSS VSS — — — — — — — 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled DI21 DI25 DI26 DI27 DI28 DI29 DI30 DI30A Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Negative current is defined as current sourced by the pin. Refer to Table 1-1 for I/O pins buffer types.  2010 Microchip Technology Inc. DS39969B-page 377 PIC24FJ256DA210 FAMILY TABLE 30-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VOL DO10 DO16 VOH DO20 Characteristic Output Low Voltage I/O Ports OSCO/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSCO/CLKO 2.4 1.4 — — — — — — — — — — — — V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.2V IOH = -3.0 mA, VDD = 2.2V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.2V — — — — — — — — 0.4 0.4 0.4 0.4 V V V V IOL = 6.6 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.2V IOL = 6.6 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.2V Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 30-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. D130 D131 D132B D133A TIW EP VPR Characteristic Program Flash Memory Cell Endurance VDD for Read VDD for Self-Timed Write Self-Timed Word Write Cycle Time Self-Timed Row Write Cycle Time D133B D134 D135 Note 1: TIE TRETD IDDP Self-Timed Page Erase Time Characteristic Retention Supply Current during Programming 10000 VMIN VMIN — — 20 20 — — — — 20 1.5 — — 16 — 3.6 3.6 — — 40 — — E/W V V s ms ms Year mA -40C to +85C VMIN = Minimum operating voltage VMIN = Minimum operating voltage If no other specifications are violated Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39969B-page 378  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. VRGOUT VBG CEFC Characteristics Regulator Output Voltage Internal Band Gap Reference External Filter Capacitor Value Min — — 4.7 Typ 1.8 1.2 10 Max Units — — — V V F Series resistance < 3 Ohm recommended; < 5 Ohm required. VREGS = 1, VREGS = 0 with WUTSEL = 01 or any POR or BOR Sleep wake-up with VREGS = 0 and WUTSEL = 11 Comments TVREG — 10 — s — TBG Band Gap Reference Start-up Time — 190 1 — — s ms 30.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256DA210 family AC characteristics and timing parameters. TABLE 30-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Operating voltage VDD range as described in Section 30.1 “DC Characteristics”. FIGURE 30-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSCO Load Condition 1 – for all pins except OSCO VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output  2010 Microchip Technology Inc. DS39969B-page 379 PIC24FJ256DA210 FAMILY TABLE 30-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSCO Characteristic OSCO/CLKO Pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI EC mode In I2C™ mode DO56 DO58 Note 1: CIO CB All I/O Pins and OSCO SCLx, SDAx — — — — 50 400 pF pF Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 30-3: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 DS39969B-page 380  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY TABLE 30-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. OS10 FOSC Characteristic External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min DC 4 3.5 4 10 10 31 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — — 6 6 Max 32 48 10 8 32 32 33 — DC — 20 10 10 Units MHz MHz MHz MHz MHz MHz kHz — ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS HSPLL SOSC See parameter OS10 for FOSC value Conditions OS20 TOSC OS25 TCY OS30 TosL, TosH OS31 TosR, TosF OS40 TckR OS41 TckF Note 1: 2: TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSCI) High or Low Time External Clock in (OSCI) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). TABLE 30-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.2V TO 3.6V) AC CHARACTERISTICS Param Symbol No. OS50 FPLLI Characteristic(1) PLL Input Frequency Range(2) PLL Output Frequency Range PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min 4 4 4 OS51 OS52 OS53 FSYS TLOCK DCLK 95.76 — -0.25 — — — Typ(2) — Max 48 32 8 96.24 200 0.25 Units MHz MHz MHz MHz s % Conditions ECPLL mode HSPLL mode XTPLL mode Note 1: 2: These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39969B-page 381 PIC24FJ256DA210 FAMILY TABLE 30-15: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 F21 Note 1: 2: Characteristic FRC Accuracy @ 8 MHz(1,2) LPRC @ 31 kHz Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial Min -1 -20 Typ ±0.15 — Max 1 20 Units % % Conditions -40°C  TA +85°C -40°C  TA +85°C 2.2V  VDD 3.6V VCAP (on-chip regulator output voltage) = 1.8V Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. To achieve this accuracy, physical stress applied to the microcontroller package (ex., by flexing the PCB) must be kept to a minimum. TABLE 30-16: RC OSCILLATOR START-UP TIME AC CHARACTERISTICS Param No. TFRC TLPRC Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min — — Typ 15 50 Max — — Units s s Conditions TABLE 30-17: RESET AND BROWN-OUT RESET REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY12 SY13 SY25 TMCL TPOR TIOZ TBOR TRST Characteristic MCLR Pulse width (Low) Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Internal State Reset Time Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min 2 — — 1 — Typ — 2 — — 50 Max — — 100 — — Units s s ns s s VDD VBOR Conditions DS39969B-page 382  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY FIGURE 30-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value DO31 DO32 Note: Refer to Figure 30-2 for load conditions. Old Value TABLE 30-18: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. DO31 DO32 DI35 DI40 Note 1: TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (input) CNx High or Low Time (input) Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39969B-page 383 PIC24FJ256DA210 FAMILY TABLE 30-19: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Symbol Characteristic Standard Operating Conditions: 2.2V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C Min. Typ Max. Units Conditions Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 2.2 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 V AD02 AD05 AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage — — — — V V V V Reference Inputs Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN VINL Absolute Input Voltage Absolute VINL Input Voltage Leakage Current VREFL AVSS – 0.3 AVSS – 0.3 — ±1.0 — — VREFH AVDD + 0.3 AVDD/2 ±610 V V V nA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k 10-bit (Note 2) AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) — — 2.5K  ADC Accuracy AD20B Nr AD21B INL AD22B DNL AD23B GERR AD24B EOFF AD25B Note 1: 2: — — — — — — 10 ±1 ±0.5 ±1 ±1 — — 74)3@ The following sections give the technical details of the packages. /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c φ A2 α β A1 L L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E ƒ ƒ ƒ ± 0,1 0,//,0(7(56 120 %6& ± ± 5() ƒ %6& %6& %6& %6& ± ƒ ƒ ƒ ƒ ƒ 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG PP SHU VLGH 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & % DS39969B-page 388  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ  2010 Microchip Technology Inc. DS39969B-page 389 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 390  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39969B-page 391 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 392  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 b N 1 23 NOTE 1 c NOTE 2 α A β φ L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E ƒ ƒ ƒ ƒ ƒ ƒ ± ƒ 5() ƒ %6& %6& %6& %6& ƒ ± ± %6& ± 0,1 A1 L1 0,//,0(7(56 120 0$; A2 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & %  2010 Microchip Technology Inc. DS39969B-page 393 PIC24FJ256DA210 FAMILY /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS39969B-page 394  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. DS39969B-page 395 PIC24FJ256DA210 FAMILY Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS39969B-page 396  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY APPENDIX A: REVISION HISTORY Revision A (February 2010) Original data sheet for the PIC24FJ256DA210 family of devices. Revision B (May 2010) Minor changes throughout text and the values in Section 30.0 “Electrical Characteristics” were updated.  2010 Microchip Technology Inc. DS39969B-page 397 PIC24FJ256DA210 FAMILY NOTES: DS39969B-page 398  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY INDEX A A/D Conversion 10-Bit High-Speed A/D Converter............................. 325 A/D Converter ................................................................... 325 Analog Input Model ................................................... 333 Transfer Function...................................................... 333 AC Characteristics ADC Conversion Timing ........................................... 385 CLKO and I/O Timing................................................ 383 Internal RC Accuracy ................................................ 382 Alternate Interrupt Vector Table (AIVT) .............................. 93 Alternative Master EPMP........................................................................ 273 Assembler MPASM Assembler................................................... 360 Shared I/O Port Structure ......................................... 157 SPI Master, Frame Master Connection .................... 220 SPI Master, Frame Slave Connection ...................... 220 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 219 SPI Master/Slave Connection (Standard Mode)............................................... 219 SPI Slave, Frame Master Connection ...................... 220 SPI Slave, Frame Slave Connection ........................ 220 SPIx Module (Enhanced Mode)................................ 213 SPIx Module (Standard Mode) ................................. 212 System Clock............................................................ 141 Triple Comparator Module........................................ 335 UART (Simplified)..................................................... 231 USB OTG Device Mode Power Modes.............................. 241 USB OTG Interrupt Funnel ....................................... 248 USB OTG Module..................................................... 240 Watchdog Timer (WDT)............................................ 356 B Block Diagram CRC .......................................................................... 297 Block Diagrams 10-Bit High-Speed A/D Converter............................. 326 16-Bit Asynchronous Timer3 and Timer5 ................. 193 16-Bit Synchronous Timer2 and Timer4 ................... 193 16-Bit Timer1 Module................................................ 189 32-Bit Timer2/3 and Timer4/5 ................................... 192 96 MHz PLL .............................................................. 150 Accessing Program Space Using Table Operations .......................................................... 77 Addressing for Table Registers................................... 81 BDT Mapping for Endpoint Buffering Modes ............ 244 CALL Stack Frame...................................................... 75 Comparator Voltage Reference ................................ 341 CPU Programmer’s Model .......................................... 41 CRC Shift Engine Detail............................................ 297 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 343 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 344 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 344 Data Access From Program Space Address Generation ........................................... 76 Graphics Module Overview....................................... 305 I2C Module ................................................................ 224 Individual Comparator Configurations, CREF = 0 .......................................................... 336 Individual Comparator Configurations, CREF = 1 and CVREFP = 0 ............................. 337 Individual Comparator ConfigurationS, CREF = 1 and CVREFP = 1 ............................. 337 Input Capture ............................................................ 197 On-Chip Regulator Connections ............................... 354 Output Compare (16-Bit Mode)................................. 202 Output Compare (Double-Buffered, 16-Bit PWM Mode) ........................................... 204 PCI24FJ256DA210 Family (General) ......................... 20 PIC24F CPU Core ...................................................... 40 PSV Operation (Higher Word) .................................... 79 PSV Operation (Lower Word) ..................................... 79 Reset System.............................................................. 87 RTCC ........................................................................ 285 C C Compilers MPLAB C18.............................................................. 360 Charge Time Measurement Unit (CTMU)......................... 343 Key Features ............................................................ 343 Charge Time Measurement Unit. See CTMU. Code Examples Basic Sequence for Clock Switching in Assembly .......................................................... 149 Configuring UART1 I/O Input/Output Functions (PPS) ............................................... 168 EDS Read From Program Memory in Assembly ........ 80 EDS Read in Assembly .............................................. 72 EDS Write in Assembly .............................................. 73 Erasing a Program Memory Block (Assembly) ........... 84 I/O Port Read/Write in ‘C’ ......................................... 163 I/O Port Read/Write in Assembly.............................. 163 Initiating a Programming Sequence ........................... 85 PWRSAV Instruction Syntax .................................... 155 Setting the RTCWREN Bit ........................................ 286 Single-Word Flash Programming ............................... 86 Single-Word Flash Programming (‘C’ Language) .................................................... 86 Code Protection ................................................................ 357 Code Segment Protection ........................................ 357 Configuration Options....................................... 358 Configuration Protection ........................................... 358 Comparator Voltage Reference ........................................ 341 Configuring ............................................................... 341 Configuration Bits ............................................................. 347 Core Features..................................................................... 15 CPU Arithmetic Logic Unit (ALU) ........................................ 43 Control Registers........................................................ 42 Core Registers............................................................ 40 Programmer’s Model .................................................. 39 CRC 32-Bit Programmable Cyclic Redundancy Check .......................................... 297 Polynomials .............................................................. 298 Setup Examples for 16 and 32-Bit Polynomials ....... 298 User Interface ........................................................... 298  2010 Microchip Technology Inc. DS39969B-page 399 PIC24FJ256DA210 FAMILY CTMU Measuring Capacitance ............................................ 343 Measuring Time ........................................................ 344 Pulse Delay and Generation ..................................... 344 Customer Change Notification Service ............................. 405 Customer Notification Service........................................... 405 Customer Support ............................................................. 405 F Flash Configuration Words ......................................... 46, 347 Flash Program Memory ...................................................... 81 and Table Instructions ................................................ 81 Enhanced ICSP Operation ......................................... 82 JTAG Operation.......................................................... 82 Programming Algorithm .............................................. 84 RTSP Operation ......................................................... 82 Single-Word Programming ......................................... 86 D Data Memory Address Space............................................................ 47 Memory Map ............................................................... 48 Near Data Space ........................................................ 49 SFR Space.................................................................. 49 Software Stack ............................................................ 75 Space Organization, Alignment .................................. 49 DC Characteristics I/O Pin Input Specifications ....................................... 377 I/O Pin Output Specifications .................................... 378 Program Memory ...................................................... 378 Development Support ....................................................... 359 Device Features 100/121--Pin ............................................................... 19 64-Pin.......................................................................... 18 Doze Mode........................................................................ 156 G Graphics Controller (GFX) ................................................ 305 Key Features ............................................................ 305 Graphics Controller Module (GFX) ................................... 305 Graphics Display Module Display Clock (GCLK) Source .................................. 324 Display Configuration................................................ 324 Memory Locations .................................................... 324 Memory Requirements ............................................. 324 Module Registers...................................................... 306 Graphics Display Module (GFX) ....................................... 305 I I/O Ports Analog Port Pins Configuration................................. 158 Analog/Digital Function of an I/O Pin........................ 158 Input Change Notification ......................................... 163 Open-Drain Configuration......................................... 158 Parallel (PIO) ............................................................ 157 Peripheral Pin Select ................................................ 164 Pull-ups and Pull-downs ........................................... 163 Selectable Input Sources.......................................... 165 I2C Clock Rates .............................................................. 225 Reserved Addresses ................................................ 225 Setting Baud Rate as Bus Master............................. 225 Slave Address Masking ............................................ 225 Idle Mode .......................................................................... 156 Input Capture 32-Bit Mode .............................................................. 198 Operations ................................................................ 198 Synchronous and Trigger Modes.............................. 197 Input Capture with Dedicated Timers ............................... 197 Input Voltage Levels for Port or Pin Tolerated Description Input....................................... 158 Instruction Set Overview................................................................... 365 Summary .................................................................. 363 Instruction-Based Power-Saving Modes................... 155, 156 Interfacing Program and Data Spaces................................ 75 Inter-Integrated Circuit. See I2C. ...................................... 223 Internet Address ............................................................... 405 Interrupt Vector Table (IVT) ................................................ 93 Interrupts Control and Status Registers...................................... 96 Implemented Vectors.................................................. 95 Reset Sequence ......................................................... 93 Setup and Service Procedures ................................. 140 Trap Vectors ............................................................... 94 Vector Table ............................................................... 94 E EDS................................................................................... 273 Electrical Characteristics A/D Specifications ..................................................... 384 Absolute Maximum Ratings ...................................... 371 Capacitive Loading on Output Pin ............................ 380 External Clock Timing ............................................... 381 Idle Current ............................................................... 375 Load Conditions and Requirements for Specifications.................................................... 379 Operating Current ..................................................... 374 PLL Clock Timing Specifications............................... 381 Power-Down Current ................................................ 376 RC Oscillator Start-up Time ...................................... 382 Reset and Brown-out Reset Requirements .............. 382 Temperature and Voltage Specifications .................. 373 Thermal Conditions ................................................... 372 V/F Graph ................................................................. 372 Voltage Regulator Specifications .............................. 379 Enhanced Parallel Master Port. See EPMP...................... 273 ENVREG Pin..................................................................... 354 EPMP ................................................................................ 273 Alternative Master ..................................................... 273 Key Features............................................................. 273 Master Port Pins ....................................................... 274 Equations 16-Bit, 32-Bit CRC Polynomials ................................ 298 A/D Conversion Clock Period ................................... 332 Baud Rate Reload Calculation .................................. 225 Calculating the PWM Period ..................................... 204 Calculation for Maximum PWM Resolution............... 205 Estimating USB Transceiver Current Consumption..................................................... 243 Relationship Between Device and SPI Clock Speed...................................................... 221 RTCC Calibration ...................................................... 294 UART Baud Rate with BRGH = 0 ............................. 232 UART Baud Rate with BRGH = 1 ............................. 232 Errata .................................................................................. 14 J JTAG Interface.................................................................. 358 DS39969B-page 400  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY K Key Features..................................................................... 347 CTMU........................................................................ 343 EPMP........................................................................ 273 RTCC ........................................................................ 285 Program Memory Access Using Table Instructions ................................ 77 Address Construction ................................................. 75 Address Space ........................................................... 45 Flash Configuration Words ......................................... 46 Memory Maps............................................................. 45 Organization ............................................................... 46 Reading From Program Memory Using EDS ............. 78 Pulse-Width Modulation (PWM) Mode.............................. 203 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period.............................................. 204 M Memory Organization.......................................................... 45 Microchip Internet Web Site .............................................. 405 MPLAB ASM30 Assembler, Linker, Librarian ................... 360 MPLAB Integrated Development Environment Software............................................... 359 MPLAB PM3 Device Programmer .................................... 362 MPLAB REAL ICE In-Circuit Emulator System................. 361 MPLINK Object Linker/MPLIB Object Librarian ................ 360 R Reader Response............................................................. 406 Reference Clock Output ................................................... 152 Register Maps A/D Converter............................................................. 61 ANCFG ....................................................................... 64 ANSEL........................................................................ 64 Comparators............................................................... 66 CPU Core ................................................................... 50 CRC............................................................................ 66 CTMU ......................................................................... 62 Enhanced Parallel Master/Slave Port ......................... 65 Graphics ..................................................................... 69 I2C™........................................................................... 56 ICN ............................................................................. 51 Input Capture.............................................................. 54 Interrupt Controller...................................................... 52 NVM............................................................................ 70 Output Compare ......................................................... 55 Pad Configuration....................................................... 60 Peripheral Pin Select .................................................. 67 PMD............................................................................ 70 PORTA ....................................................................... 58 PORTB ....................................................................... 58 PORTC ....................................................................... 59 PORTD ....................................................................... 59 PORTE ....................................................................... 59 PORTF ....................................................................... 60 PORTG....................................................................... 60 RTCC.......................................................................... 65 SPI.............................................................................. 58 System........................................................................ 70 Timers......................................................................... 53 UART.......................................................................... 57 USB OTG ................................................................... 63 Registers AD1CHS (A/D Input Select)...................................... 330 AD1CON1 (A/D Control 1)........................................ 327 AD1CON2 (A/D Control 2)........................................ 328 AD1CON3 (A/D Control 3)........................................ 329 AD1CSSH (A/D Input Scan Select, High)................. 332 AD1CSSL (A/D Input Scan Select, Low) .................. 331 ALCFGRPT (Alarm Configuration) ........................... 289 ALMINSEC (Alarm Minutes and Seconds Value)..... 293 ALMTHDY (Alarm Month and Day Value) ................ 292 ALWDHR (Alarm Weekday and Hours Value) ......... 293 ANCFG (A/D Band Gap Reference Configuration) ................................................... 331 ANSA (PORTA Analog Function Selection) ............. 159 ANSB (PORTB Analog Function Selection) ............. 160 ANSC (PORTC Analog Function Selection) ............. 160 ANSD (PORTD Analog Function Selection) ............. 161 ANSE (PORTE Analog Function Selection) ............. 161 N Near Data Space ................................................................ 49 O Oscillator Configuration 96 MHz PLL .............................................................. 149 Clock Selection ......................................................... 142 Clock Switching......................................................... 148 Sequence.......................................................... 148 CPU Clocking Scheme ............................................. 142 Display Clock Frequency Division............................. 152 Initial Configuration on POR ..................................... 142 USB Operations ........................................................ 151 Output Compare 32-Bit Mode............................................................... 201 Synchronous and Trigger Modes.............................. 201 Output Compare with Dedicated Timers ........................... 201 P Packaging ......................................................................... 387 Details ....................................................................... 388 Marking ..................................................................... 387 Peripheral Enable Bits ...................................................... 156 Peripheral Module Disable Bits ......................................... 156 Peripheral Pin Select (PPS) .............................................. 164 Available Peripherals and Pins ................................. 164 Configuration Control ................................................ 167 Considerations for Use ............................................. 168 Input Mapping ........................................................... 164 Mapping Exceptions.................................................. 167 Output Mapping ........................................................ 166 Peripheral Priority ..................................................... 164 Registers................................................................... 169 Pin Descriptions 100-Pin Devices............................................................ 8 121 (BGA)-Pin Devices............................................... 11 64-Pin Devices.............................................................. 6 Pin Diagrams 100-Pin TQFP ............................................................... 7 121-Pin BGA ............................................................... 10 64-Pin TQFP/QFN ........................................................ 5 Pinout Descriptions ............................................................. 21 POR and On-Chip Voltage Regulator................................ 354 Power-Saving Clock Frequency and Clock Switching...................... 155 Features.................................................................... 155 Instruction-Based Modes .......................................... 155 Power-up Requirements ................................................... 355 Product Identification System ........................................... 407  2010 Microchip Technology Inc. DS39969B-page 401 PIC24FJ256DA210 FAMILY ANSF (PORTF Analog Function Selection) .............. 162 ANSG (PORTG Analog Function Selection) ............. 162 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ........................................... 247 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode) ........................................... 246 CLKDIV (Clock Divider) ............................................ 145 CLKDIV2 (Clock Divider 2) ....................................... 147 CMSTAT (Comparator Status).................................. 339 CMxCON (Comparator x Control) ............................. 338 CORCON (CPU Core Control).............................. 43, 98 CRCCON1 (CRC Control 1) ..................................... 300 CRCCON2 (CRC Control 2) ..................................... 301 CRCDATH (CRC Data High) .................................... 302 CRCDATL (CRC Data Low)...................................... 302 CRCWDATH (CRC Shift High) ................................. 303 CRCWDATL (CRC Shift Low)................................... 303 CRCXORH (CRC XOR High) ................................... 302 CRCXORL (CRC XOR Polynomial, Low Byte) .......................................................... 301 CTMUCON (CTMU Control) ..................................... 345 CTMUICON (CTMU Current Control) ....................... 346 CVRCON (Comparator Voltage Reference Control)............................................ 342 CW1 (Flash Configuration Word 1) ........................... 348 CW2 (Flash Configuration Word 2) ........................... 350 CW3 (Flash Configuration Word 3) ........................... 351 CW4 (Flash Configuration Word 4) ........................... 352 DEVID (Device ID) .................................................... 353 DEVREV (Device Revision) ...................................... 354 G1ACTDA (Active Display Area) .............................. 317 G1CHRX (Character X-Coordinate Print Position).................................................... 321 G1CHRY (Character Y-Coordinate Print Position).................................................... 322 G1CLUT (Color Look-up Table Control) ................... 319 G1CLUTRD (Color Look-up Table Memory Read Data)........................................................ 320 G1CLUTWR (Color Look-up Table Memory Write Data)........................................................ 320 G1CMDH (GPU Command High) ............................. 306 G1CMDL (GPU Command Low)............................... 306 G1CON1 (Display Control 1) .................................... 307 G1CON2 (Display Control 2) .................................... 308 G1CON3 (Display Control 3) .................................... 309 G1DBEN (Data I/O Pad Enable) ............................... 323 G1DBLCON (Display Blanking Control).................... 318 G1DPADRH (Display Buffer Start Address High) ................................................... 315 G1DPADRL (Display Buffer Start Address Low) .................................................... 315 G1DPDPH (Display Buffer Height) ........................... 316 G1DPHT (Display Total Height) ................................ 316 G1DPW (Display Buffer Width) ................................. 315 G1DPWT (Display Total Width) ................................ 316 G1HSYNC (Horizontal Synchronization Control)................................... 317 G1IE (GFX Interrupt Enable) .................................... 311 G1IPU (Inflate Processor Status).............................. 322 G1IR (GFX Interrupt Status) ..................................... 312 G1MRGN (Interrupt Advance) .................................. 321 G1PUH (GPU Work Area Height) ............................. 314 G1PUW (GPU Work Area Width) ............................. 314 G1STAT (Graphics Control Status) .......................... 310 G1VSYNC (Vertical Synchronization Control) .......... 318 G1W1ADRH (GPU Work Area 1 Start Address High) .......................................... 313 G1W1ADRL (GPU Work Area 1 Start Address Low) ........................................... 313 G1W2ADRH (GPU Work Area 2 Start Address High ........................................... 314 G1W2ADRL (GPU Work Area 2 Start Address Low) ........................................... 313 I2CxCON (I2Cx Control) ........................................... 226 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 230 I2CxSTAT (I2Cx Status) ........................................... 228 ICxCON1 (Input Capture x Control 1)....................... 199 ICxCON2 (Input Capture x Control 2)....................... 200 IEC0 (Interrupt Enable Control 0) ............................. 109 IEC1 (Interrupt Enable Control 1) ............................. 110 IEC2 (Interrupt Enable Control 2) ............................. 112 IEC3 (Interrupt Enable Control 3) ............................. 113 IEC4 (Interrupt Enable Control 4) ............................. 114 IEC5 (Interrupt Enable Control 5) ............................. 115 IEC6 (Interrupt Enable Control 6) ............................. 116 IFS0 (Interrupt Flag Status 0) ................................... 101 IFS1 (Interrupt Flag Status 1) ................................... 102 IFS2 (Interrupt Flag Status 2) ................................... 103 IFS3 (Interrupt Flag Status 3) ................................... 105 IFS4 (Interrupt Flag Status 4) ................................... 106 IFS5 (Interrupt Flag Status 5) ................................... 107 IFS6 (Interrupt Flag Status 6) ................................... 108 INTCON1 (Interrupt Control 1).................................... 99 INTCON2 (Interrupt Control 2).................................. 100 INTTREG (Interrupt Controller Test.......................... 139 IPC0 (Interrupt Priority Control 0) ............................. 117 IPC1 (Interrupt Priority Control 1) ............................. 118 IPC10 (Interrupt Priority Control 10) ......................... 127 IPC11 (Interrupt Priority Control 11) ......................... 128 IPC12 (Interrupt Priority Control 12) ......................... 129 IPC13 (Interrupt Priority Control 13) ......................... 130 IPC15 (Interrupt Priority Control 15) ......................... 131 IPC16 (Interrupt Priority Control 16) ......................... 132 IPC18 (Interrupt Priority Control 18) ......................... 133 IPC19 (Interrupt Priority Control 19) ......................... 133 IPC2 (Interrupt Priority Control 2) ............................. 119 IPC20 (Interrupt Priority Control 20) ......................... 134 IPC21 (Interrupt Priority Control 21) ......................... 135 IPC22 (Interrupt Priority Control 22) ......................... 136 IPC23 (Interrupt Priority Control 23) ......................... 137 IPC25 (Interrupt Priority Control 25) ......................... 138 IPC3 (Interrupt Priority Control 3) ............................. 120 IPC4 (Interrupt Priority Control 4) ............................. 121 IPC5 (Interrupt Priority Control 5) ............................. 122 IPC6 (Interrupt Priority Control 6) ............................. 123 IPC7 (Interrupt Priority Control 7) ............................. 124 IPC8 (Interrupt Priority Control 8) ............................. 125 IPC9 (Interrupt Priority Control 9) ............................. 126 IPCn (Interrupt Priority Control 0-23) ........................ 137 MINSEC (RTCC Minutes and Seconds Value)......... 291 MTHDY (RTCC Month and Day Value) .................... 290 NVMCON (Flash Memory Control) ............................. 83 OCxCON1 (Output Compare x Control 1) ................ 206 OCxCON2 (Output Compare x Control 2) ................ 208 OSCCON (Oscillator Control) ................................... 143 DS39969B-page 402  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY OSCTUN (FRC Oscillator Tune)............................... 146 PADCFG1 (Pad Configuration Control) ............ 283, 288 PMCON1 (EPMP Control 1) ..................................... 275 PMCON2 (EPMP Control 2) ..................................... 276 PMCON3 (EPMP Control 3) ..................................... 277 PMCON4 (EPMP Control 4) ..................................... 278 PMCSxBS (Chip Select x Base Address) ................. 280 PMCSxCF (Chip Select x Configuration) .................. 279 PMCSxMD (Chip Select x Mode).............................. 281 PMSTAT (EPMP Status, Slave Mode)...................... 282 RCFGCAL (RTCC Calibration and Configuration).... 287 RCON (Reset Control) ................................................ 88 REFOCON (Reference Oscillator Control) ............... 153 RPINRn (PPS Input) ......................................... 169–179 RPORn (PPS Output) ....................................... 180–187 SPIxCON1 (SPIx Control 1)...................................... 216 SPIxCON2 (SPIx Control 2)...................................... 218 SPIxSTAT (SPIx Status and Control) ....................... 214 SR (ALU STATUS) ............................................... 42, 97 T1CON (Timer1 Control)........................................... 190 TxCON (Timer2 and Timer4 Control)........................ 194 TyCON (Timer3 and Timer5 Control)........................ 195 U1ADDR (USB Address) .......................................... 261 U1CNFG1 (USB Configuration 1) ............................. 262 U1CNFG2 (USB Configuration 2) ............................. 263 U1CON (USB Control, Device Mode) ....................... 259 U1CON (USB Control, Host Mode)........................... 260 U1EIE (USB Error Interrupt Enable) ......................... 270 U1EIR (USB Error Interrupt Status) .......................... 269 U1EPn (USB Endpoint n Control) ............................. 271 U1IE (USB Interrupt Enable)..................................... 268 U1IR (USB Interrupt Status, Device Mode) .............. 266 U1IR (USB Interrupt Status, Host Mode) .................. 267 U1OTGCON (USB OTG Control) ............................. 256 U1OTGIE (USB OTG Interrupt Enable, Host Mode) ....................................................... 265 U1OTGIR (USB OTG Interrupt Status, Host Mode) ....................................................... 264 U1OTGSTAT (USB OTG Status).............................. 255 U1PWMCON USB (VBUS PWM Generator Control) ............................................................. 272 U1PWRC (USB Power Control)................................ 257 U1SOF (USB OTG Start-Of-Token Threshold, Host Mode) ..................................... 262 U1STAT (USB Status) .............................................. 258 U1TOK (USB Token, Host Mode)............................. 261 UxMODE (UARTx Mode).......................................... 234 UxSTA (UARTx Status and Control)......................... 236 WKDYHR (RTCC Weekday and Hours Value)......... 291 YEAR (RTCC Year Value) ........................................ 290 Resets BOR (Brown-out Reset) .............................................. 87 Clock Source Selection............................................... 90 CM (Configuration Mismatch Reset)........................... 87 Delay Times ................................................................ 91 Device Times .............................................................. 90 IOPUWR (Illegal Opcode Reset) ................................ 87 MCLR (Pin Reset)....................................................... 87 POR (Power-on Reset) ............................................... 87 RCON Flags Operation............................................... 89 SFR States.................................................................. 90 SWR (RESET Instruction)........................................... 87 TRAPR (Trap Conflict Reset)...................................... 87 UWR (Uninitialized W Register Reset) ....................... 87 WDT (Watchdog Timer Reset).................................... 87 Revision History................................................................ 397 RTCC Alarm Configuration.................................................. 294 Calibration ................................................................ 294 Key Features ............................................................ 285 Register Mapping ..................................................... 286 S Selective Peripheral Power Control .................................. 156 Serial Peripheral Interface (SPI) ....................................... 211 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 49 Sleep Mode ...................................................................... 155 Software Simulator (MPLAB SIM) .................................... 361 Software Stack ................................................................... 75 Special Features................................................................. 16 SPI .................................................................................... 211 T Timer1 .............................................................................. 189 Timer2/3 and Timer4/5 ..................................................... 191 Timing Diagrams CLKO and I/O Timing ............................................... 383 External Clock .......................................................... 380 Triple Comparator............................................................. 335 Triple Comparator Module ................................................ 335 U UART ................................................................................ 231 Baud Rate Generator (BRG) .................................... 232 IrDA Support ............................................................. 233 Operation of UxCTS and UxRTS Pins...................... 233 Receiving in 8-Bit or 9-Bit Data Mode ...................... 233 Transmitting Break and Sync Sequence ............................... 233 in 8-Bit Data Mode............................................ 233 Transmitting in 9-Bit Data Mode ............................... 233 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus Buffer Descriptors Assignment in Different Buffering Modes ......... 245 Interrupts and USB Transactions...................................... 249 Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 16 USB OTG ......................................................................... 239 Buffer Descriptors and BDT...................................... 244 Device Mode Operation............................................ 249 DMA Interface........................................................... 245 Hardware Calculating Transceiver Power Requirements ............ 243 Hardware Configuration............................................ 241 Device Mode..................................................... 241 External Interface ............................................. 243 Host and OTG Modes....................................... 242 VBUS Voltage Generation ................................. 243 Host Mode Operation ............................................... 250 Interrupts .................................................................. 248 Operation.................................................................. 252 Registers .................................................................. 254 VBUS Voltage Generation ......................................... 243  2010 Microchip Technology Inc. DS39969B-page 403 PIC24FJ256DA210 FAMILY V Voltage Regulator (On-Chip)............................................. 354 and BOR ................................................................... 355 Low Voltage Detection .............................................. 354 Standby Mode ........................................................... 355 W Watchdog Timer (WDT).................................................... 355 Control Register........................................................ 356 Windowed Operation ................................................ 356 WWW Address ................................................................. 405 WWW, On-Line Support ..................................................... 14 DS39969B-page 404  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS39969B-page 405 PIC24FJ256DA210 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39969B FAX: (______) _________ - _________ Device: PIC24FJ256DA210 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39969B-page 406  2010 Microchip Technology Inc. PIC24FJ256DA210 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 DA2 10 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern c) b) Examples: a) PIC24FJ128DA206-I/PT: PIC24F device with Graphics Controller and USB On-The-Go, 128-KB program memory, 96-KB data memory, 64-pin, Industrial temp., TQFP package. PIC24FJ256DA110-I/PT: PIC24F device with Graphics Controller and USB On-The-Go, 256-KB program memory, 24-KB data memory, 100-pin, Industrial temp., TQFP package. PIC24FJ256DA210-I/BG: PIC24F device with Graphics Controller and USB On-The-Go, 256-KB program memory, 96-KB data memory, 121-pin, Industrial temp., BGA package. Architecture Flash Memory Family Product Group 24 FJ = 16-bit modified Harvard without DSP = Flash program memory DA2 = General purpose microcontrollers with Graphics Controller and USB On-The-Go 06 10 I = 64-pin = 100-pin (TQFP)/121-pin (BGA) = -40C to +85C (Industrial) Pin Count Temperature Range Package PT = 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) PT = 64-lead, TQFP (Thin Quad Flatpack) MR = 64-lead (9x9x0.9 mm) QFN (Quad Flatpack, No Lead) BG = 121-pin BGA package Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample Pattern  2010 Microchip Technology Inc. DS39969B-page 407 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 DS39969B-page 408  2010 Microchip Technology Inc.