PIC24FJ256GB110

PIC24FJ256GB110 Family Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) © 2008 Microchip Technology Inc. Preliminary DS39897B Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39897B-page ii Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Power Management: • On-Chip 2.5V Voltage Regulator • Switch between Clock Sources in Real Time • Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up • Run mode: 1 mA/MIPS, 2.0V Typical • Sleep mode Current Down to 100 nA Typical • Standby Current with 32 kHz Oscillator: 2.5 μA, 2.0V typical High-Performance CPU: • • • • • • • Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes • Linear Program Memory Addressing, Up to 12 Mbytes • Linear Data Memory Addressing, Up to 64 Kbytes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory Universal Serial Bus Features: • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – can act as either Host or Peripheral • Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode • Full-Speed USB Operation in Device mode • High-Precision PLL for USB • Internal Voltage Boost Assist for USB Bus Voltage Generation • Interface for Off-Chip Charge Pump for USB Bus Voltage Generation • Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers • On-Chip USB Transceiver with On-Chip Voltage Regulator • Interface for Off-Chip USB Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Analog Features: • 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Conversions available in Sleep mode • Three Analog Comparators with Programmable Input/ Output Configuration • Charge Time Measurement Unit (CTMU) Program Memory (Bytes) 10-Bit A/D (ch) SRAM (Bytes) Remappable Peripherals UART w/IrDA® Capture Input Timers 16-Bit Compare/ PWM Output Remappable Pins I2C™ Comparators PMP/PSP PIC24FJ64GB106 PIC24FJ128GB106 PIC24FJ192GB106 PIC24FJ256GB106 PIC24FJ64GB108 PIC24FJ128GB108 PIC24FJ192GB108 PIC24FJ256GB108 PIC24FJ64GB110 PIC24FJ128GB110 PIC24FJ192GB110 PIC24FJ256GB110 64 64 64 64 80 80 80 80 100 100 100 100 64K 128K 192K 256K 64K 128K 192K 256K 64K 128K 192K 256K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 16K 29 29 29 29 40 40 40 40 44 44 44 44 5 5 5 5 5 5 5 5 5 5 5 5 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 4 4 4 4 4 4 4 4 4 4 4 4 SPI Device 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 16 16 16 16 16 16 16 16 16 16 16 16 3 3 3 3 3 3 3 3 3 3 3 3 Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y Y © 2008 Microchip Technology Inc. Preliminary DS39897B-page 1 USBOTG Y Y Y Y Y Y Y Y Y Y Y Y CTMU JTAG Pins PIC24FJ256GB110 FAMILY Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - Up to 44 available pins (100-pin devices) • Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer • Three I2C™ modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing • Four UART modules: - Supports RS-485, RS-232, LIN/J6202 protocols and IrDA® - On-chip hardware encoder/decoder for IrDA - Auto-wake-up and Auto-Baud Detect (ABD) - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Nine 16-Bit Capture Inputs, each with a Dedicated Time Base • Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • 8-Bit Parallel Master Port (PMP/PSP): - Up to 16 address pins - Programmable polarity on control lines • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions • Programmable Cyclic Redundancy Check (CRC) Generator • Up to 5 External Interrupt Sources Special Microcontroller Features: • • • • • • • Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs on Digital I/O High-Current Sink/Source (18 mA/18 mA) on all I/O Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator On-Chip LDO Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power RC Oscillator for Reliable Operation In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support Brown-out Reset (BOR) Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words • • • • • • • DS39897B-page 2 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Pin Diagram (64-Pin TQFP) 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/VREF-/AN1/CN3/RB1 PGED1/RP0/PMA6/VREF+/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 RPI37/SOSCO/C3INC/TICK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/SCL1/PMCS2/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS RP16/USBID/CN71/RF3 PIC24FJXXXGB106 Legend: RPn represents remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. Preliminary TCK/PMA11/AN12/CTED2/CN30/RB12 TDI/PMA10/AN13/CTED1/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 PMA9/RP10/SDA2/CN17/RF4 PMA8/RP17/SCL2/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 AVDD AVSS RP8/AN8/CN26/RB8 PMA7/RP9/AN9/CN27/RB9 TMS/PMA13/AN10/CVREF/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 VSS VDD DS39897B-page 3 PIC24FJ256GB110 FAMILY Pin Diagram (80-Pin TQFP) PMD1/CN59/RE1 PMD0/CN58/RE0 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 ENVREG PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI40/CN47/RC3 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD TMS/RPI33/CN66/RE8 TDO/RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 RPI37/SOSCO/C3INC/T1CK/CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/SCL1/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA2/CN44/RA15 RPI36/SCL2/CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3 PIC24FJXXXGB108 PGED2/RCV/RP7/AN7/CN25/RB7 AN11/PMA12/CN29/RB11 Vss AVSS RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 RP5/CN21/RD15 AVDD VDD RP10/PMA9/CN17/RF4 PMA6/VREF+/CN42/RA10 TCK/AN12/CTED2/PMA11/CN30/RB12 TDI/AN13/CTED1/PMA10/CN31/RB13 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. DS39897B-page 4 Preliminary CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 RPI43/CN20/RD14 PGEC2/AN6/RP6/CN24/RB6 PMA7/VREF-/CN41/RA9 AN10/CVREF/PMA13/CN28/RB10 RP17/PMA8/CN18/RF5 © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Pin Diagram (100-Pin TQFP) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD2/CN60/RE2 CN80/RG13 CN79/RG12 CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 PMD4/CN62/RE4 PMD3/CN61/RE3 CN82/RG15 VDD PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 RPI38/CN45/RC1 RPI39/CN46/RC2 RPI40/CN47/RC3 RPI41/CN48/RC4 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 RP19/PMA3/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD TMS/CN33/RA0 RPI33/CN66/RE8 RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/AN1/CN3/RB1 PGED1/RP0/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 VSS RPI37/SOSCO/C3INC/T1CK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/PMCS2/CN55/RD10 RP4/DPLN/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 RPI35/SDA1/CN44/RA15 RPI36/SCL1/CN43/RA14 VSS OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 VDD TDO/CN38/RA5 TDI/CN37/RA4 SDA2/CN36/RA3 SCL2/CN35/RA2 D+/RG2 D-/RG3 VUSB VBUS RP15/CN74/RF8 RP30/CN70/RF2 RP16/USBID/CN71/RF3 PIC24FJXXXGB110 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PMA7/VREF-/CN41/RA9 PMA6/VREF+/CN42/RA10 AVDD AVSS RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/CTED2/PMA11/CN30/RB12 AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 Legend: RPn and RPIn represent remappable pins for Peripheral Pin Select feature. © 2008 Microchip Technology Inc. Preliminary VSS VDD RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS39897B-page 5 PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU ........................................................................................................................................................................................... 25 3.0 Memory Organization ................................................................................................................................................................. 31 4.0 Flash Program Memory .............................................................................................................................................................. 55 5.0 Resets ........................................................................................................................................................................................ 61 6.0 Interrupt Controller ..................................................................................................................................................................... 67 7.0 Oscillator Configuration ............................................................................................................................................................ 109 8.0 Power-Saving Features ............................................................................................................................................................ 119 9.0 I/O Ports ................................................................................................................................................................................... 121 10.0 Timer1 ...................................................................................................................................................................................... 147 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 149 12.0 Input Capture with Dedicated Timers ....................................................................................................................................... 155 13.0 Output Compare with Dedicated Timers .................................................................................................................................. 159 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 169 15.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 179 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 187 17.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 195 18.0 Parallel Master Port (PMP)....................................................................................................................................................... 225 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 235 20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 245 21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 249 22.0 Triple Comparator Module........................................................................................................................................................ 259 23.0 Comparator Voltage Reference................................................................................................................................................ 263 24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 265 25.0 Special Features ...................................................................................................................................................................... 269 26.0 Development Support............................................................................................................................................................... 281 27.0 Instruction Set Summary .......................................................................................................................................................... 285 28.0 Electrical Characteristics .......................................................................................................................................................... 293 29.0 Packaging Information.............................................................................................................................................................. 307 Appendix A: Revision History............................................................................................................................................................. 317 Index ................................................................................................................................................................................................. 319 The Microchip Web Site ..................................................................................................................................................................... 323 Customer Change Notification Service .............................................................................................................................................. 323 Customer Support .............................................................................................................................................................................. 323 Reader Response .............................................................................................................................................................................. 324 Product Identification System............................................................................................................................................................. 325 DS39897B-page 6 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 7 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 8 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ64GB106 • PIC24FJ128GB106 • PIC24FJ192GB106 • PIC24FJ256GB106 • PIC24FJ64GB108 • PIC24FJ128GB108 • PIC24FJ192GB108 • PIC24FJ256GB108 • PIC24FJ64GB110 • PIC24FJ128GB110 • PIC24FJ192GB110 • PIC24FJ256GB110 • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. • Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1.3 This expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 family provides a new platform for high-performance USB applications which may need more than an 8-bit platform, but don’t require the power of a digital signal processor. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. • A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages such as ‘C’ • Operational performance up to 16 MIPS 1.1.4 EASY MIGRATION 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB110 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 9 PIC24FJ256GB110 FAMILY 1.2 USB On-The-Go With the PIC24FJ256GB110 family of devices, Microchip introduces USB On-The-Go functionality on a single chip to its product line. This new module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ256GB110 family devices provide a true single-chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. 1.4 Details on Individual Family Members Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in four ways: 1. Flash program memory (64 Kbytes for PIC24FJ64GB1 devices, 128 Kbytes for PIC24FJ128GB1 devices, 192 Kbytes for PIC24FJ192GB1 devices and 256 Kbytes for PIC24FJ256GB1 devices). Available I/O pins and ports (51 pins on 6 ports for 64-pin devices, 65 pins on 7 ports for 80-pin devices and 83 pins on 7 ports for 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (49 on 64-pin devices, 63 on 80-pin devices, and 81 on 100-pin devices). Available remappable pins (29 pins on 64-pin devices, 40 pins on 80-pin devices and 44 pins on 100-pin devices) 1.3 Other Special Features • Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ256GB110 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, four independent UARTs with built-in IrDA encoder/decoders and three SPI modules. • Analog Features: All members of the PIC24FJ256GB110 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB110 family include the brand new CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. 2. 3. 4. All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ256GB110 family devices, sorted by function, is shown in Table 1-4. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. DS39897B-page 10 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 64-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 49 64K 22,016 64GB106 128GB106 128K 44,032 16,384 66 (62/4) Ports B, C, D, E, F, G 51 29 (28 I/O, 1 Input only) 192GB106 192K 67,072 256GB106 256K 87,552 DC – 32 MHz Instruction Set Packages Note 1: © 2008 Microchip Technology Inc. Preliminary DS39897B-page 11 PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 80-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 63 64K 22,016 64GB108 128GB108 128K 44,032 16,384 66 (62/4) Ports A, B, C, D, E, F, G 65 40 (31 I/O, 9 Input only) 192GB108 192K 67,072 256GB108 256K 87,552 DC – 32 MHz Instruction Set Packages Note 1: DS39897B-page 12 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan/Programming 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 4(1) 3(1) 3 Yes Yes 16 3 Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 100-Pin TQFP Peripherals are accessible through remappable pins. 5(1) 2 9(1) 9(1) 81 64K 22,016 64GB110 128GB110 128K 44,032 16,384 66 (62/4) Ports A, B, C, D, E, F, G 83 44 (32 I/O, 12 Input only) 192GB110 192K 67,072 256GB110 256K 87,552 DC – 32 MHz Instruction Set Packages Note 1: © 2008 Microchip Technology Inc. Preliminary DS39897B-page 13 PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Data Bus 16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU PORTB (16 I/O) PORTA(1) (13 I/O) Interrupt Controller 23 Address Latch Program Memory Data Latch PORTC(1) (8 I/O) Address Bus 24 Inst Latch Inst Register Instruction Decode & Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference ENVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD(2) Literal Data EA MUX 16 16 16 PORTD(1) (16 I/O) PORTE(1) Divide Support 17x17 Multiplier 16 x 16 W Reg Array (10 I/O) REFO 16-Bit ALU 16 PORTF(1) (9 I/O) PORTG(1) (12 I/O) VDDCORE/VCAP VDD, VSS MCLR Timer1 Timer2/3(3) Timer4/5(3) RTCC 10-Bit ADC Comparators(3) USB OTG PMP/PSP PWM/OC 1-9(3) SPI 1/2/3(3) IC 1-9(3) Note 1: 2: 3: ICNs(1) I2C 1/2/3 UART 1/2/3/4(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39897B-page 14 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number 64-Pin TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 19 20 11 12 5 4 13 14 8 6 55 54 48 47 39 40 80-Pin TQFP 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 25 26 15 16 7 6 17 18 10 8 69 68 60 59 49 50 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 30 31 20 21 11 10 22 23 14 12 84 83 74 73 63 64 I/O Input Buffer ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA — — ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA — Positive Supply for Analog modules. Ground Reference for Analog modules. Comparator 1 Input A. Comparator 1 Input B. Comparator 1 Input C. Comparator 1 Input D. Comparator 2 Input A. Comparator 2 Input B. Comparator 2 Input C. Comparator 2 Input D. Comparator 3 Input A. Comparator 3 Input B. Comparator 3 Input C. Comparator 3 Input D. Main Clock Input Connection. System Clock Output. A/D Analog Inputs. Description AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend: I I I I I I I I I I I I I I I I P P I I I I I I I I I I I I I O TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer © 2008 Microchip Technology Inc. Preliminary DS39897B-page 15 PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 40 39 17 18 21 22 23 24 27 28 29 — — — — — — — — — — 80-Pin TQFP 60 59 20 19 18 17 16 15 6 7 8 10 36 66 67 68 69 39 40 65 37 38 50 49 21 22 27 28 29 30 33 34 35 — — — — — — — — 23 24 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 64 63 26 27 32 33 34 35 41 42 43 17 38 58 59 60 61 91 92 28 29 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Description CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN24 CN25 CN26 CN27 CN28 CN29 CN30 CN31 CN32 CN33 CN34 CN35 CN36 CN37 CN38 CN39 CN40 CN41 CN42 Legend: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I Interrupt-on-Change Inputs. TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 16 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP — — — — — — 46 49 50 51 42 43 44 45 — 60 61 62 63 64 1 2 3 — — 58 59 — 33 — — — — — — — — — 28 27 29 23 80-Pin TQFP 52 53 4 — 5 — 58 61 62 63 54 55 56 57 64 76 77 78 79 80 1 2 3 13 14 72 73 42 41 43 — — 75 74 — — — — 34 33 35 29 100-Pin TQFP 66 67 6 7 8 9 72 76 77 78 68 69 70 71 79 93 94 98 99 100 3 4 5 18 19 87 88 52 51 53 40 39 90 89 96 97 95 1 42 41 43 34 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ANA — — CTMU External Edge Input 1. CTMU External Edge Input 2. CTMU Pulse Output. Comparator Voltage Reference Output. Description CN43 CN44 CN45 CN46 CN47 CN48 CN49 CN50 CN51 CN52 CN53 CN54 CN55 CN56 CN57 CN58 CN59 CN60 CN61 CN62 CN63 CN64 CN65 CN66 CN67 CN68 CN69 CN70 CN71 CN74 CN75 CN76 CN77 CN78 CN79 CN80 CN81 CN82 CTED1 CTED2 CTPLS CVREF Legend: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O Interrupt-on-Change Inputs. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer © 2008 Microchip Technology Inc. Preliminary DS39897B-page 17 PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 37 36 46 42 50 43 57 46 7 39 40 15 16 17 18 11 12 30 29 8 6 5 4 16 22 32 31 28 27 24 23 45 44 51 80-Pin TQFP 47 46 58 54 62 55 71 58 9 49 50 19 20 21 22 15 16 36 35 10 8 7 6 24 23 40 39 34 33 30 29 57 56 63 100-Pin TQFP 57 56 72 68 77 69 86 72 13 63 64 24 25 26 27 20 21 44 43 14 12 11 10 29 28 50 49 42 41 35 34 71 70 78 I/O Input Buffer — — — — — — ST ST ST ANA ANA ST ST ST ST ST ST ST ST — — — — — — — — — — — — ST/TTL ST — Parallel Master Port Chip Select 1 Strobe/Address Bit 15. Parallel Master Port Chip Select 2 Strobe/Address Bit 14. Parallel Master Port Byte Enable Strobe. Description D+ DDMH DMLN DPH DPLN ENVREG INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMCS1 PMCS2 PMBE Legend: I/O I/O O O O O I I I I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O O O O I/O O O USB Differential Plus line (internal transceiver). USB Differential Minus line (internal transceiver). D- External Pull-up Control Output. D- External Pull-down Control Output. D+ External Pull-up Control Output. D+ External Pull-down Control Output. Voltage Regulator Enable. External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger/Emulator/ICSP™ Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897B-page 18 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 60 61 62 63 64 1 2 3 53 52 — — — — — — — — — — — — 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 80-Pin TQFP 76 77 78 79 80 1 2 3 67 66 — — — — — — — — 23 24 52 53 20 19 18 17 16 15 21 22 27 28 29 30 33 34 35 36 100-Pin TQFP 93 94 98 99 100 3 4 5 82 81 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 I/O Input Buffer ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL — — ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTB Digital I/O. Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. PORTA Digital I/O. Description PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 Legend: I/O I/O I/O I/O I/O I/O I/O I/O O O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. Preliminary DS39897B-page 19 PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP — — — — 39 47 48 40 18 46 49 50 51 52 53 54 55 42 43 44 45 — — — — 60 61 62 63 64 1 2 3 — — 30 80-Pin TQFP 4 — 5 — 49 59 60 50 22 58 61 62 63 66 67 68 69 54 55 56 57 64 65 37 38 76 77 78 79 80 1 2 3 13 14 36 100-Pin TQFP 6 7 8 9 63 73 74 64 27 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 44 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — Reference Clock Output. ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer PORTE Digital I/O. USB Receive Input (from external transceiver). PORTD Digital I/O. PORTC Digital I/O. Description RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 RCV RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 REFO Legend: I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 20 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 58 59 — 33 31 32 — — — — — 37 36 4 5 6 8 — — — — 16 15 42 44 43 — 17 18 21 22 31 46 45 14 29 — 33 32 11 6 80-Pin TQFP 72 73 42 41 39 40 43 — — 75 74 47 46 6 7 8 10 — — — — 20 19 54 56 55 38 21 22 27 28 39 58 57 18 35 43 41 40 15 8 100-Pin TQFP 87 88 52 51 49 50 53 40 39 90 89 57 56 10 11 12 14 96 97 95 1 25 24 68 70 69 48 26 27 32 33 49 72 71 23 43 53 51 50 20 12 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer Remappable Peripheral (input or output). PORTG Digital I/O. PORTF Digital I/O. Description RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13 RG0 RG1 RG2 RG3 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP12 RP13 RP14 RP15 RP16 RP17 RP18 RP19 Legend: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O TTL = TTL input buffer ANA = Analog level input/output © 2008 Microchip Technology Inc. Preliminary DS39897B-page 21 PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 53 4 51 50 49 52 5 8 12 30 — — — — — — — 48 — — — — — — 42 44 32 2 43 31 3 47 48 48 27 28 24 23 33 12 80-Pin TQFP 67 6 63 62 61 66 7 10 16 36 42 — — 13 14 53 52 60 4 — 5 — 64 37 54 56 52 2 55 53 3 59 60 60 33 34 14 13 41 16 100-Pin TQFP 82 10 78 77 76 81 11 14 21 44 52 39 40 18 19 67 66 74 6 7 8 9 79 47 68 66 58 4 67 59 5 73 74 74 38 60 61 17 51 21 I/O Input Buffer ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — I2C I2C I2C I2C I2C I2C ANA ANA ST ST ST — ST ST — Real-Time Clock Alarm/Seconds Pulse Output. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. I2C3 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock. JTAG Test Clock/Programming Clock Input. JTAG Test Data/Programming Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. USB OTG ID (OTG mode only). USB Output Enable Control (for external transceiver). Remappable Peripheral (input only). Description RP20 RP21 RP22 RP23 RP24 RP25 RP26 RP27 RP28 RP29 RP30 RP31 RPI32 RPI33 RPI34 RPI35 RPI36 RPI37 RPI38 RPI39 RPI40 RPI41 RPI42 RPI43 RTCC SCL1 SCL2 SCL3 SDA1 SDA2 SDA3 SOSCI SOSCO T1CK TCK TDI TDO TMS USBID USBOEN Legend: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I O I/O I/O I/O I/O I/O I/O I O I I I O I I O Remappable Peripheral (input or output). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39897B-page 22 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: Function PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 34 11 58 56 58 59 49 80-Pin TQFP 44 15 72 70 72 73 61 12, 32, 48 70 18 17 23 24 11, 31, 51 45 100-Pin TQFP 54 20 87 85 87 88 76 2, 16, 37, 46, 62 85 23 22 28 29 15, 36, 45, 65, 75 55 I/O Input Buffer — — ANA — ST ST — — — ST ST ANA ANA — — Description VBUS VBUSON VBUSST VCAP VCMPST1 VCMPST2 VCPCON VDD VDDCORE VMIO VPIO VREFVREF+ VSS VUSB Legend: P O I P I I O P P I/O I/O I I P P USB Voltage, Host mode (5V). USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB VBUS Boost Generator, Comparator Input 2. USB OTG VBUS PWM/Charge Output. Positive Supply for Peripheral Digital Logic and I/O Pins. Positive Supply for Microcontroller Core Logic (regulator disabled). USB Differential Minus Input/Output (external transceiver). USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins. USB Voltage (3.3V) 10, 26, 38 56 14 13 15 16 9, 25, 41 35 TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer © 2008 Microchip Technology Inc. Preliminary DS39897B-page 23 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 24 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 2. CPU” (DS39703). For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. 2.1 Programmer’s Model The programmer’s model for the PIC24F is shown in Figure 2-2. All registers in the programmer’s model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer’s model are memory mapped. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 25 PIC24FJ256GB110 FAMILY FIGURE 2-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic Data RAM Address Latch 16 RAGU WAGU 16 Data Bus 16 16 Data Latch 16 PIC24F CPU CORE BLOCK DIAGRAM 23 Address Latch Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX Instruction Decode & Control Instruction Reg Control Signals to Various Blocks Hardware Multiplier Divide Support 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS39897B-page 26 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 2-1: W0 through W15 PC SR SPLIM TBLPAG PSVPAG RCOUNT CORCON CPU CORE REGISTERS Description Working Register Array 23-Bit Program Counter ALU STATUS Register Stack Pointer Limit Value Register Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register CPU Control Register Register(s) Name FIGURE 2-2: PROGRAMMER’S MODEL 15 0 W0 (WREG) W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 Frame Pointer Stack Pointer 0 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register Working/Address Registers Divider Working Registers Multiplier Registers SPLIM 22 PC 7 TBLPAG 7 PSVPAG 15 RCOUNT 15 SRH SRL 0 0 0 0 0 0 0 ALU STATUS Register (SR) — — — — — — — DC IPL 2 1 0 RA N OV Z C 15 0 CPU Control Register (CORCON) — — — — — — — — — — — — IPL3 PSV — — Registers or bits shadowed for PUSH.S and POP.S instructions. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 27 PIC24FJ256GB110 FAMILY 2.2 CPU Control Registers SR: ALU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(1) IPL1 (2) REGISTER 2-1: U-0 — bit 15 R/W-0(1) IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 (2) R/W-0(1) IPL0 (2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: ALU Overflow bit 1 = Overflow occurred for signed (2’s complement) arithmetic in this arithmetic operation 0 = No overflow has occurred Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39897B-page 28 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 2-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-4 bit 3 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/C-0 IPL3 (1) CORCON: CPU CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PSV U-0 — U-0 — bit 0 Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ User interrupts are disabled when IPL3 = 1. bit 2 bit 1-0 Note 1: 2.3 Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 2.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned © 2008 Microchip Technology Inc. Preliminary DS39897B-page 29 PIC24FJ256GB110 FAMILY 2.3.2 DIVIDER 2.3.3 MULTI-BIT SHIFT SUPPORT The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 2-2: Instruction ASR SL LSR INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Description Arithmetic shift right source register by one or more bits. Shift left source register by one or more bits. Logical shift right source register by one or more bits. DS39897B-page 30 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ256GB110 family of devices are shown in Figure 3-1. 3.1 Program Address Space The program address memory space of the PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES PIC24FJ128GB1XX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (44K instructions) PIC24FJ64GB1XX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Flash Program Memory (22K instructions) Flash Config Words User Memory Space PIC24FJ192GB1XX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24FJ256GB1XX GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 000000h 000002h 000004h 0000FEh 000100h 000104h 0001FEh 000200h User Flash Program Memory (67K instructions) Flash Config Words User Flash Program Memory (87K instructions) 00ABFEh 00AC00h 0157FEh 015800h 020BFEh 020C00h Flash Config Words Unimplemented Read ‘0’ Unimplemented Read ‘0’ Unimplemented Read ‘0’ Flash Config Words 02ABFEh 02AC00h Unimplemented Read ‘0’ 7FFFFFh 800000h Reserved Configuration Memory Space Reserved Reserved Reserved Device Config Registers Device Config Registers Device Config Registers Device Config Registers F7FFFEh F80000h F8000Eh F80010h Reserved Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) DEVID (2) FEFFFEh FF0000h FFFFFFh Note: Memory areas are not shown to scale. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 31 PIC24FJ256GB110 FAMILY 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 FLASH CONFIGURATION WORDS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. In PIC24FJ256GB110 family devices, the top three words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GB110 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 25.1 “Configuration Bits”. 3.1.2 HARD MEMORY VECTORS All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. TABLE 3-1: FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 FAMILY DEVICES Program Memory (Words) 22,016 44,032 67,072 87,552 Configuration Word Addresses 00ABFAh: 00ABFEh 0157FAh: 0157FEh 020BFAh: 020BFEh 02ABFAh: 02ABFEh Device PIC24FJ64GB PIC24FJ128GB PIC24FJ192GB PIC24FJ256GB FIGURE 3-2: MSW Address 000001h 000003h 000005h 000007h PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 000000h 000002h 000004h 000006h PC Address (LSW Address) DS39897B-page 32 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the program space visibility area (see Section 3.3.3 “Reading Data from Program Memory Using Program Space Visibility”). PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. FIGURE 3-3: DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES MSB Address 0001h 07FFh 0801h 1FFFh 2001h Data RAM LSB Address 0000h 07FEh 0800h 1FFEh 2000h SFR Space MSB SFR Space LSB Near Data Space Implemented Data RAM 47FFh 4801h Unimplemented Read as ‘0’ 7FFFh 8001h 47FEh 4800h 7FFFh 8000h Program Space Visibility Area FFFFh FFFEh Note: Data memory areas are not shown to scale. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 33 PIC24FJ256GB110 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 NEAR DATA SPACE The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. 3.2.4 SFR SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30. TABLE 3-2: IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 Core Timers I2C™ A/D — — PMP — UART A/D/CTMU — — RTC/Comp — SPI/UART — — — CRC System xx40 xx60 ICN Capture SPI/I2C — — — — NVM/PMD — — SPI — UART — USB — PPS — — — — xx80 xxA0 Interrupts Compare I/O — — — — — xxC0 xxE0 — 000h 100h 200h 300h 400h 500h 600h 700h Legend: — = No implemented SFRs in this block DS39897B-page 34 Preliminary © 2008 Microchip Technology Inc. TABLE 3-3: Bit 13 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Value Register Program Counter Low Word Register — — — — — — — — — — — — — — DC — — — — — Repeat Loop Counter Register IPL2 — IPL1 — IPL0 — Disable Interrupts Counter Register RA — N IPL3 OV PSV Z — C — — — — — — — — — — — Program Counter Register High Byte Table Memory Page Address Register Program Space Visibility Page Address Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPU CORE REGISTERS MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx File Name Addr Bit 15 Bit 14 WREG0 0000 WREG1 0002 WREG2 0004 WREG3 0006 WREG4 0008 WREG5 000A © 2008 Microchip Technology Inc. WREG6 000C WREG7 000E WREG8 0010 WREG9 0012 WREG10 0014 WREG11 0016 WREG12 0018 WREG13 001A WREG14 001C WREG15 001E SPLIM 0020 PCL 002E PIC24FJ256GB110 FAMILY Preliminary PCH 0030 — — TBLPAG 0032 — — PSVPAG 0034 — — RCOUNT 0036 SR 0042 — — CORCON 0044 — — DISICNT 0052 — — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS39897B-page 35 TABLE 3-4: Bit 13 CN13PDE CN29PDE CN61PDE — — CN9IE CN25IE CN41IE(1) CN57IE(1) CN56IE — — CN8PUE CN24PUE CN55PUE CN71PUE — — CN70PUE(1) — CN69PUE CN54PUE CN53PUE CN23PUE CN22PUE CN7PUE CN6PUE CN5PUE CN4PUE — — — — CN71IE CN70IE(1) CN69IE CN68IE — CN3PUE CN55IE CN54IE CN53IE CN52IE CN51IE CN67IE(1) — — CN9PUE CN25PUE CN40IE(2) CN39IE(2) CN38IE(2) CN37IE(2) CN36IE(2) CN35IE(2) CN24IE CN23IE CN22IE CN21IE(1) CN20IE(1) CN19IE(1) CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN18IE CN34IE(2) CN50IE CN66IE(1) CN82IE(2) CN2PUE CN18PUE CN51PUE — — CN50PUE CN68PUE CN67PUE(1) CN66PUE(1) — — — — — — — CN71PDE CN70PDE(1) CN69PDE CN68PDE CN67PDE(1) CN66PDE(1) — CN13IE CN29IE CN45IE(1) CN61IE CN77IE(1) — CN13PUE CN29PUE CN61PUE — — — — — — — — CN60PUE CN59PUE CN58PUE CN57PUE(1) CN56PUE CN28PUE CN27PUE CN26PUE CN12PUE CN11PUE CN10PUE — — — CN76IE(2) CN75IE(2) CN74IE(1) CN60IE CN59IE CN58IE CN44IE(1) CN43IE(1) CN42IE(1) CN28IE CN27IE CN26IE CN12IE CN11IE CN10IE — — — CN60PDE CN59PDE CN58PDE CN57PDE(1) CN56PDE CN55PDE CN54PDE CN53PDE CN52PDE CN51PDE CN50PDE CN49PDE CN65PDE CN1IE CN17IE CN33IE(2) CN49IE CN65IE CN81IE(2) CN1PUE CN17PUE CN49PUE CN65PUE CN28PDE CN27PDE CN26PDE CN25PDE CN24PDE CN23PDE CN22PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN18PDE CN17PDE CN12PDE CN11PDE CN10PDE CN9PDE CN8PDE CN7PDE CN6PDE CN5PDE CN4PDE CN3PDE CN2PDE CN1PDE CN0PDE CN16PDE CN32PDE CN64PDE CN0IE CN16IE CN32IE CN48IE(2) CN64IE CN80IE(2) CN0PUE CN16PUE CN32PUE CN52PUE CN64PUE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 CN48PDE(2) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN48PUE(2) 0000 0000 CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000 ICN REGISTER MAP File Name Addr Bit 15 Bit 14 CNPD1 0054 CN15PDE CN14PDE DS39897B-page 36 CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000 CN21PUE(1) CN20PUE(1) CN19PUE(1) CNPD2 0056 CN31PDE CN30PDE CNPD3 0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CNPD4 005A CN63PDE CN62PDE CNPD5 005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1) CNPD6 (2) 005E — — CNEN1 0060 CN15IE CN14IE CNEN2 0062 CN31IE CN30IE CNEN3 0064 CN47IE(1) CN46IE(2) CNEN4 0066 CN63IE CN62IE CNEN5 0068 CN79IE(2) CN78IE(1) CNEN6(2) 006A — — CNPU1 006C CN15PUE CN14PUE CNPU2 006E CN31PUE CN30PUE CNPU3 0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2) CNPU4 0072 CN63PUE CN62PUE CNPU5 0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1) PIC24FJ256GB110 FAMILY Preliminary CNPU6(2) 0076 — — Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices; read as ‘0’. Unimplemented in 64-pin and 80-pin devices; read as ‘0’. © 2008 Microchip Technology Inc. TABLE 3-5: Bit 13 — — AD1IF INT2IF PMPIF — CTMUIF IC9IF AD1IE INT2IE PMPIE — CTMUIE IC9IE T1IP1 T2IP1 — — — — — — — — — — — — — — — — — — — — — — — — RTCIP2 RTCIP1 INT4IP2 INT4IP1 MI2C2P2 MI2C2P1 MI2C2P0 INT4IP0 RTCIP0 — — — — — OC6IP2 OC6IP1 OC6IP0 IC4IP2 IC4IP1 IC4IP0 — — — — — — — — — — — SPF3IP1 — — SPF3IP0 — — — — — — — U2RXIP2 U2RXIP1 U2RXIP0 — OC4IP2 OC4IP1 OC4IP0 — IC7IP2 IC7IP1 IC7IP0 — — OC3IP2 INT2IP2 SPI2IP2 IC3IP2 OC5IP2 PMPIP2 SI2C2P2 INT3IP2 — — CMIP2 CMIP1 CMIP0 — — — — — AD1IP2 SPI1IP2 SPI1IP1 SPI1IP0 — SPF1IP2 SPF1IP1 AD1IP1 — OC3IP1 INT2IP1 SPI2IP1 IC3IP1 OC5IP1 PMPIP1 SI2C2P1 INT3IP1 — U1ERIP2 U1ERIP1 — U3ERIP2 U3ERIP1 MI2C3P2 MI2C3P1 U4TXIP2 IC9IP2 U4TXIP1 IC9IP1 — CNIP1 IC8IP1 T4IP1 U2TXIP1 — IC5IP1 OC7IP1 — — — — CRCIP1 — — U3TXIP1 SPI3IP1 — — SPI3IP0 U3TXIP0 — — CRCIP0 — — — — OC7IP0 IC5IP0 — U2TXIP0 T4IP0 IC8IP0 CNIP0 — T2IP0 — OC2IP2 OC2IP1 OC2IP0 — IC2IP2 IC2IP1 T1IP0 — OC1IP2 OC1IP1 OC1IP0 — IC1IP2 IC1IP1 OC9IE SPI3IE SPF3IE U4TXIE U4RXIE U4ERIE USB1IE MI2C3IE SI2C3IE IC1IP0 IC2IP0 SPF1IP0 AD1IP0 MI2C1P0 — OC3IP0 INT2IP0 SPI2IP0 IC3IP0 OC5IP0 PMPIP0 SI2C2P0 INT3IP0 — U1ERIP0 — CTMUIP2 CTMUIP1 CTMUIP0 U3ERIP0 MI2C3P0 U4TXIP0 IC9IP0 — — — — LVDIE — — — — — — — — — — INT4IE INT3IE — OC8IE OC7IE OC6IE OC5IE IC6IE IC5IE IC4IE IC3IE — — — CRCIE U3TXIE — — — — — — — — — — — — — — — — — — — — — — T5IE T4IE OC4IE OC3IE — IC8IE IC7IE — INT1IE CNIE U1TXIE U1RXIE SPI1IE SPF1IE T3IE T2IE OC2IE IC2IE — T1IE OC9IF SPI3IF SPF3IF U4TXIF U4RXIF U4ERIF USB1IF MI2C3IF SI2C3IF U3TXIF — — — — LVDIF — — — — CRCIF U2ERIF U3RXIF OC1IE CMIE — MI2C2IE U2ERIE U3RXIE INT0IP2 — T3IP2 U1TXIP2 SI2C1P2 INT1IP2 — T5IP2 SPF2IP2 — IC6IP2 OC8IP2 — — — — LVDIP2 — — SI2C3P2 OC9IP2 — — — — — — INT4IF INT3IF — — MI2C2IF OC8IF OC7IF OC6IF OC5IF IC6IF IC5IF IC4IF IC3IF — — — T5IF T4IF OC4IF OC3IF — IC8IF IC7IF — INT1IF CNIF CMIF MI2C1IF SPI2IF SI2C2IF U1ERIF U3ERIF IC1IE MI2C1IE SPI2IE SI2C2IE U1ERIE U3ERIE INT0IP1 — T3IP1 U1TXIP1 SI2C1P1 INT1IP1 — T5IP1 SPF2IP1 — IC6IP1 OC8IP1 — — — — LVDIP1 — — SI2C3P1 OC9IP1 U1TXIF U1RXIF SPI1IF SPF1IF T3IF T2IF OC2IF IC2IF — T1IF OC1IF IC1IF — — — — — — — — — — INT2EP INT1EP — — — — — — — — MATHERR ADDRERR STKERR OSCFAIL — INT0EP INT0IF SI2C1IF SPF2IF — — — INT0IE SI2C1IE SPF2IE — — — INT0IP0 — T3IP0 U1TXIP0 SI2C1P0 INT1IP0 — T5IP0 SPF2IP0 — IC6IP0 OC8IP0 — — — — LVDIP0 — — SI2C3P0 U4RXIP2 U4RXIP1 U4RXIP0 OC9IP0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTERRUPT CONTROLLER REGISTER MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4440 4444 0044 4444 4404 4440 4444 0044 4440 4444 0044 0440 0440 0400 4440 0004 0040 4440 4444 4444 0044 File Name Addr Bit 15 Bit 14 INTCON1 0080 NSTDIS — INTCON2 0082 ALTIVT DISI IFS0 0084 — — IFS1 0086 U2TXIF U2RXIF IFS2 0088 — — IFS3 008A — RTCIF IFS4 008C — — © 2008 Microchip Technology Inc. MI2C1P2 MI2C1P1 U2ERIP2 U2ERIP1 U2ERIP0 U3RXIP2 U3RXIP1 U3RXIP0 USB1IP2 USB1IP1 USB1IP0 SPF3IP2 IFS5 008E — — IEC0 0094 — — IEC1 0096 U2TXIE U2RXIE IEC2 0098 — — IEC3 009A — RTCIE IEC4 009C — — IEC5 009E — — IPC0 00A4 — T1IP2 IPC1 00A6 — T2IP2 IPC2 00A8 — U1RXIP2 U1RXIP1 U1RXIP0 IPC3 00AA — — IPC4 00AC — CNIP2 IPC5 00AE — IC8IP2 PIC24FJ256GB110 FAMILY Preliminary IPC6 00B0 — T4IP2 IPC7 00B2 — U2TXIP2 IPC8 00B4 — — IPC9 00B6 — IC5IP2 IPC10 00B8 — OC7IP2 IPC11 00BA — — IPC12 00BC — — IPC13 00BE — — IPC15 00C2 — — IPC16 00C4 — CRCIP2 IPC18 00C8 — — IPC19 00CA — — IPC20 00CC — U3TXIP2 IPC21 00CE — U4ERIP2 U4ERIP1 U4ERIP0 IPC22 00D0 — SPI3IP2 IPC23 00D2 — — DS39897B-page 37 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-6: Bit 13 Timer1 Register Timer1 Period Register — Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Timer2 Period Register Timer3 Period Register — — Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Timer4 Period Register Timer5 Period Register — — TSIDL — — — — — — TGATE TSIDL — — — — — — TGATE TCKPS1 TCKPS1 TCKPS0 TCKPS0 T32 — — — TCS TCS — — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 T32 — — TCS TCS — — TSIDL — — — — — — TGATE TCKPS1 TCKPS0 — TSYNC TCS — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000 TIMER REGISTER MAP File Name Addr Bit 15 Bit 14 TMR1 0100 PR1 0102 DS39897B-page 38 T1CON 0104 TON TMR2 0106 TMR3HLD 0108 TMR3 010A PR2 010C PR3 010E T2CON 0110 TON T3CON 0112 TON TMR4 0114 TMR5HLD 0116 TMR5 0118 PR4 011A PR5 011C T4CON 011E TON T5CON 0120 TON PIC24FJ256GB110 FAMILY Preliminary Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2008 Microchip Technology Inc. TABLE 3-7: Bit 13 ICSIDL — Input Capture 1 Buffer Register Timer Value 1 Register ICSIDL — Input Capture 2 Buffer Register Timer Value 2 Register ICSIDL — Input Capture 3 Buffer Register Timer Value 3 Register ICSIDL — Input Capture 4 Buffer Register Timer Value 4 Register ICSIDL — Input Capture 5 Buffer Register Timer Value 5 Register ICSIDL — — — — — IC32 ICTRIG ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 TRIGSTAT ICI0 — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — — IC32 ICTRIG TRIGSTAT — ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — — IC32 ICTRIG TRIGSTAT — ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — — IC32 ICTRIG TRIGSTAT — ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — — IC32 ICTRIG TRIGSTAT — ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — — IC32 ICTRIG TRIGSTAT — ICTSEL2 ICTSEL1 ICTSEL0 — — — ICI1 ICI0 ICOV ICBNE ICM2 ICM1 ICM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INPUT CAPTURE REGISTER MAP All Resets 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx ICI1 TRIGSTAT ICI0 — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx — IC32 — ICTRIG ICI1 TRIGSTAT Input Capture 8 Buffer Register Timer Value 8 Register ICSIDL — — — — ICTSEL2 ICTSEL1 ICTSEL0 — — — IC32 — ICTRIG ICI1 TRIGSTAT Input Capture 9 Buffer Register Timer Value 9 Register ICI0 — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICI0 — ICOV ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 0000 0000 0000 xxxx 0000 0000 0000 xxxx File Name SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 Addr Bit 15 Bit 14 IC1CON1 0140 — — IC1CON2 0142 — — IC1BUF 0144 IC1TMR 0146 IC2CON1 0148 — — IC2CON2 014A — — IC2BUF 014C © 2008 Microchip Technology Inc. Input Capture 6 Buffer Register Timer Value 6 Register ICSIDL — — — — — IC32 ICTSEL2 ICTSEL1 ICTSEL0 — — — ICTRIG Input Capture 7 Buffer Register Timer Value 7 Register ICSIDL — — — — — ICTSEL2 ICTSEL1 ICTSEL0 — IC2TMR 014E IC3CON1 0150 — — IC3CON2 0152 — — IC3BUF 0154 IC3TMR 0156 IC4CON1 0158 — — IC4CON2 015A — — IC4BUF 015C IC4TMR 015E IC5CON1 0160 — — IC5CON2 0162 — — IC5BUF 0164 IC5TMR 0166 PIC24FJ256GB110 FAMILY Preliminary IC6CON1 0168 — — IC6CON2 016A — — IC6BUF 016C IC6TMR 016E IC7CON1 0170 — — IC7CON2 0172 — — IC7BUF 0174 IC7TMR 0176 IC8CON1 0178 — — IC8CON2 017A — — IC8BUF 017C IC8TMR 017E IC9CON1 0180 — — IC9CON2 0182 — — IC9BUF 0184 IC9TMR 0186 DS39897B-page 39 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-8: Bit 13 OCSIDL OCINV Output Compare 1 Secondary Register Output Compare 1 Register Timer Value 1 Register OCSIDL OCINV Output Compare 2 Secondary Register Output Compare 2 Register Timer Value 2 Register OCSIDL OCINV Output Compare 3 Secondary Register Output Compare 3 Register Timer Value 3 Register OCSIDL OCINV Output Compare 4 Secondary Register Output Compare 4 Register Timer Value 4 Register OCSIDL OCINV Output Compare 5 Register Timer Value 5 Register OCSIDL OCINV — — — OC32 OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 OCTRIG — TRIGSTAT — OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT Output Compare 5 Secondary Register OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 Timer Value 6 Register OCSIDL OCINV — — — OCTSEL2 OCTSEL1 OCTSEL0 — — OC32 ENFLT0 OCTRIG — TRIGSTAT Output Compare 7 Secondary Register Output Compare 7 Register Timer Value 7 Register — OCTRIS OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 xxxx 0000 0000 0000 0000 xxxx OUTPUT COMPARE REGISTER MAP File Name Addr Bit 15 Bit 14 OC1CON1 0190 — — OC1CON2 0192 FLTMD FLTOUT FLTTRIEN SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 DS39897B-page 40 Output Compare 6 Secondary Register Output Compare 6 Register OC1RS 0194 OC1R 0196 OC1TMR 0198 OC2CON1 019A — — OC2CON2 019C FLTMD FLTOUT FLTTRIEN OC2RS 019E OC2R 01A0 OC2TMR 01A2 OC3CON1 01A4 — — OC3CON2 01A6 FLTMD FLTOUT FLTTRIEN OC3RS 01A8 OC3R 01AA OC3TMR 01AC OC4CON1 01AE — — OC4CON2 01B0 FLTMD FLTOUT FLTTRIEN OC4RS 01B2 OC4R 01B4 OC4TMR 01B6 PIC24FJ256GB110 FAMILY Preliminary OC5CON1 01B8 — — OC5CON2 01BA FLTMD FLTOUT FLTTRIEN OC5RS 01BC OC5R 01BE OC5TMR 01C0 OC6CON1 01C2 — — OC6CON2 01C4 FLTMD FLTOUT FLTTRIEN OC6RS 01C6 OC6R 01C8 OC6TMR 01CA OC7CON1 01CC — — OC7CON2 01CE FLTMD FLTOUT FLTTRIEN OC7RS 01D0 OC7R 01D2 OC7TMR 01D4 © 2008 Microchip Technology Inc. Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-8: Bit 13 OCSIDL OCINV Output Compare 8 Secondary Register Output Compare 8 Register Timer Value 8 Register OCSIDL OCINV Output Compare 9 Secondary Register Output Compare 9 Register Timer Value 9 Register — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 — — — OC32 OCTRIG TRIGSTAT OCTRIS OCTSEL2 OCTSEL1 OCTSEL0 — — ENFLT0 — — OCFLT0 TRIGMODE OCM2 OCM1 OCM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OUTPUT COMPARE REGISTER MAP (CONTINUED) All Resets 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx File Name Addr Bit 15 Bit 14 OC8CON1 01D6 — — OC8CON2 01D8 FLTMD FLTOUT FLTTRIEN SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OC8RS 01DA OC8R 01DC OC8TMR 01DE OC9CON1 01E0 — — © 2008 Microchip Technology Inc. Bit 14 — — — — — — — — — — I2CSIDL — — — — — — I2CSIDL — — — — — — — — — SCLREL IPMIEN — — — — — — A10M BCL — — — — — — — — — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV — — ACKDT D/A — — — — — BCL GCSTAT SCLREL IPMIEN A10M DISSLW — — — — SMEN ADD10 GCEN IWCOL STREN I2COV — — — — — ACKDT D/A — — — — — — — — — — — — — BCL GCSTAT ADD10 IWCOL — — — — — — — — — — — — — — I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN GCEN — — — — — STREN I2COV — — — — — — ACKDT D/A — — — — — — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register Receive Register Transmit Register Baud Rate Generator Register ACKEN P Address Register Address Mask Register RCEN S PEN R/W RSEN RBF SEN TBF RCEN S PEN R/W RSEN RBF SEN TBF RCEN S PEN R/W RSEN RBF SEN TBF Bit 2 Bit 1 Bit 0 OC9CON2 01E2 FLTMD FLTOUT FLTTRIEN OC9RS 01E4 OC9R 01E6 OC9TMR 01E8 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-9: I2C™ REGISTER MAP All Resets 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000 0000 00FF 0000 1000 0000 0000 0000 File Name Addr Bit 15 I2C1RCV 0200 — I2C1TRN 0202 — I2C1BRG 0204 — PIC24FJ256GB110 FAMILY Preliminary I2C1CON 0206 I2CEN I2C1STAT 0208 ACKSTAT TRSTAT I2C1ADD 020A — I2C1MSK 020C — I2C2RCV 0210 — I2C2TRN 0212 — I2C2BRG 0214 — I2C2CON 0216 I2CEN I2C2STAT 0218 ACKSTAT TRSTAT I2C2ADD 021A — I2C2MSK 021C — I2C3RCV 0270 — I2C3TRN 0272 — I2C3BRG 0274 — I2C3CON 0276 I2CEN I2C3STAT 0278 ACKSTAT TRSTAT I2C3ADD 027A — I2C3MSK 027C — DS39897B-page 41 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-10: Bit 13 USIDL UTXISEL0 — — Baud Rate Generator Prescaler Register — UTXISEL0 — — — Baud Rate Generator Prescaler Register — UTXISEL0 — — — Baud Rate Generator Prescaler Register — UTXISEL0 — — Baud Rate Generator Prescaler Register — — — — — — — — — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN — — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV RIDLE BRGH PERR PDSEL1 FERR PDSEL0 OERR STSEL URXDA — — — Receive Register — — — Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE — — PERR — — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 FERR PDSEL0 OERR STSEL URXDA — — — Receive Register — — — Transmit Register UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR — — — — USIDL IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 OERR STSEL URXDA — — — — Receive Register — — — — Transmit Register — UTXBRK UTXEN UTXBF TRMT URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx 0000 0000 0000 0110 xxxx Receive Register 0000 0000 UART REGISTER MAPS File Name — — — Addr Bit 15 Bit 14 U1MODE 0220 UARTEN U1STA 0222 UTXISEL1 UTXINV DS39897B-page 42 Transmit Register Bit 13 SPISIDL — SPIFPOL — — DISSCK — — DISSCK — — DISSDO — — — DISSDO MODE16 — — — — — SPISIDL — SPIFPOL SPISIDL — SPIFPOL DISSCK DISSDO MODE16 SMP CKE — — — SPIBEC2 SPIBEC1 SPIBEC0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 SRMPT SSEN — SRMPT CKE — SSEN — Transmit and Receive Buffer — — SPIBEC2 SPIBEC1 SPIBEC0 MODE16 — SMP — CKE — SRMPT SSEN — Transmit and Receive Buffer SPIROV CKP — SRXMPT MSTEN — SISEL2 SPRE2 — SISEL1 SPRE1 — SISEL0 SPRE0 — SPITBF PPRE1 SPIFE SPIRBF PPRE0 SPIBEN Bit 6 SPIROV CKP — SPIROV CKP — Bit 5 SRXMPT MSTEN — SRXMPT MSTEN — Bit 4 SISEL2 SPRE2 — SISEL2 SPRE2 — Bit 3 SISEL1 SPRE1 — SISEL1 SPRE1 — Bit 2 SISEL0 SPRE0 — SISEL0 SPRE0 — Bit 1 SPITBF PPRE1 SPIFE SPITBF PPRE1 SPIFE Bit 0 SPIRBF PPRE0 SPIBEN SPIRBF PPRE0 SPIBEN All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — Transmit and Receive Buffer — — SPIBEC2 SPIBEC1 SPIBEC0 SMP U1TXREG 0224 — U1RXREG 0226 — U1BRG 0228 U2MODE 0230 UARTEN U2STA 0232 UTXISEL1 UTXINV U2TXREG 0234 — U2RXREG 0236 — U2BRG 0238 U3MODE 0250 UARTEN U3STA 0252 UTXISEL1 UTXINV U3TXREG 0254 — U3RXREG 0256 — U3BRG 0258 U4MODE 02B0 UARTEN U4STA 02B2 UTXISEL1 UTXINV U4TXREG 02B4 — U4RXREG 02B6 — U4BRG 02B8 PIC24FJ256GB110 FAMILY Preliminary Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-11: SPI REGISTER MAPS File Name Addr Bit 15 Bit 14 SPI1STAT 0240 SPIEN SPI1CON1 0242 — SPI1CON2 0244 FRMEN SPIFSD SPI1BUF 0248 SPI2STAT 0260 SPIEN SPI2CON1 0262 — SPI2CON2 0264 FRMEN SPIFSD SPI2BUF 0268 SPI3STAT 0280 SPIEN SPI3CON1 0282 — SPI3CON2 0284 FRMEN SPIFSD SPI3BUF 0288 © 2008 Microchip Technology Inc. Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-12: Bit 13 — — — — — — ODA10 ODA9 — ODA7 ODA6 ODA5 ODA4 ODA3 ODA2 ODA1 — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 RA0 LATA0 ODA0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7(2) Bit 6(2) Bit 5(2) Bit 4(2) Bit 3(2) Bit2(2) Bit 1(2) Bit 0(2) PORTA REGISTER MAP(1) All Resets 36FF xxxx xxxx 0000 File Name Addr Bit 15 Bit 14 TRISA 02C0 TRISA15 TRISA14 PORTA 02C2 RA15 RA14 LATA 02C4 LATA15 LATA14 ODCA 02C6 ODA15 ODA14 © 2008 Microchip Technology Inc. Bit 13 TRISB10 RB10 LATB10 ODB10 ODB9 ODB8 ODB7 ODB6 ODB5 LATB9 LATB8 LATB7 LATB6 LATB5 RB9 RB8 RB7 RB6 RB5 RB4 LATB4 ODB4 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 TRISB3 RB3 LATB3 ODB3 Bit 2 TRISB2 RB2 LATB2 ODB2 Bit 1 TRISB1 RB1 LATB1 ODB1 Bit 0 TRISB0 RB0 LATB0 ODB0 RB13 LATB13 ODB13 ODB12 ODB11 LATB12 LATB11 RB12 RB11 Bit 13 — — — — — — — — — — — — — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — — — — Bit 4(1) TRISC4 RC4 LATC4 ODC4 Bit 3(2) TRISC3 RC3 LATC3 ODC3 Bit 2(1) TRISC2 RC2 LATC2 ODC2 Bit 1(2) TRISC1 RC1 LATC1 ODC1 Bit 0 — — — — RC13 LATC13 ODC13 ODC12 LATC12 RC12(3) Bit 13(1) Bit 11 Bit 12(1) Bit 10 Bit 9 TRISD9 RD10 LATD10 ODD11 ODD10 RD9 LATD9 ODD9 Bit 8 TRISD8 RD8 LATD8 ODD8 Bit 7 TRISD7 RD7 LATD7 ODD7 Bit 6 TRISD6 RD6 LATD6 ODD6 Bit 5 TRISD5 RD5 LATD5 ODD5 Bit 4 TRISD4 RD4 LATD4 ODD4 Bit 3 TRISD3 RD3 LATD3 ODD3 Bit 2 TRISD2 RD2 LATD2 ODD2 Bit 1 TRISD1 RD1 LATD1 ODD1 Bit 0 TRISD0 RD0 LATD0 ODD0 RD13 LATD13 ODD13 ODD12 LATD12 RD12 RD11 LATD11 Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. PORTA and all associated bits are unimplemented on 64-pin devices and read as ‘0’. Bits are available on 80-pin and 100-pin devices only, unless otherwise noted. Bits are implemented on 100-pin devices only; otherwise read as ‘0’. TABLE 3-13: PORTB REGISTER MAP All Resets FFFF xxxx xxxx 0000 File Name Addr Bit 15 Bit 14 TRISB 02C8 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 PORTB 02CA RB15 RB14 LATB 02CC LATB15 LATB14 ODCB 02CE ODB15 ODB14 Legend: Reset values are shown in hexadecimal. TABLE 3-14: PORTC REGISTER MAP All Resets F01E xxxx xxxx 0000 PIC24FJ256GB110 FAMILY Preliminary File Name Addr Bit 15 Bit 14 TRISC 02D0 TRISC15 TRISC14 TRISC13 TRISC12 PORTC 02D2 RC15(3,4) RC14 LATC 02D4 LATC15 LATC14 ODCC 02D6 ODC15 ODC14 Legend: Note 1: 2: 3: 4: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’. Bits are unimplemented in 64-pin devices; read as ‘0’. RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD1:POSCMD0 Configuration bits = 11 or 00); otherwise read as ‘0’. RC15 is only available when POSCMD1:POSCMD0 Configuration bits = 11 or 00 and the OSCIOFN Configuration bit = 1. TABLE 3-15: PORTD REGISTER MAP All Resets FFFF xxxx xxxx 0000 File Name Addr Bit 15(1) Bit 14(1) TRISD 02D8 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 PORTD 02DA RD15 RD14 LATD 02DC LATD15 LATD14 DS39897B-page 43 ODCD 02DE ODD15 ODD14 Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented on 64-pin devices; read as ‘0’. TABLE 3-16: Bit 13 — — — — — — — ODE9 ODE8 ODE7 ODE6 ODE5 ODE4 ODE3 ODE2 ODE1 — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 LATE0 ODE0 — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 Bit 12 Bit 11 Bit 10 Bit 9(1) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 8(1) All Resets 03FF xxxx xxxx 0000 PORTE REGISTER MAP File Name Addr Bit 15 Bit 14 TRISE 02E0 — — DS39897B-page 44 Bit 13(1) Bit 11 — — — — — — ODF8 ODF7 ODF6 ODF5 ODF4 — — LATF8 LATF7 LATF6 LATF5 LATF4 — — RF8 RF7 RF6 RF5 RF4 RF3 LATF3 ODF3 — — TRISF8 TRISF7 TRISF6 TRISF5 TRISF4 TRISF3 Bit 10 Bit 9 Bit 5 Bit 4 Bit 3 TRISF13 RF13 LATF13 ODF13 ODF12 LATF12 RF12 TRISF12 Bit 12(1) Bit 8(2) Bit 7(2) Bit 6(2) Bit 2(2) TRISF2 RF2 LATF2 ODF2 Bit 1 TRISF1 RF1 LATF1 ODF1 Bit 0 TRISF0 RF0 LATF0 ODF0 All Resets 31FF xxxx xxxx 0000 Bit 13(1) Bit 11 — — — — — ODG9 ODG8 — LATG9 LATG8 LATG7 ODG7 — RG9 RG8 RG7 — TRISG9 TRISG8 TRISG7 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 TRISG6 RG6 LATG6 ODG6 Bit 12(1) Bit 5 — — — — Bit 4 — — — — Bit 3 TRISG3 RG3 LATG3 ODG3 Bit 2 TRISG2 RG2 LATG2 ODG2 Bit 1(1) TRISG1 RG1 LATG1 ODG1 Bit 0(1) TRISG0 RG0 LATG0 ODG0 All Resets F3CF xxxx xxxx 0000 RG13 LATG13 ODG13 ODG12 LATG12 RG12 Bit 13 — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 — Bit 7 — Bit 6 — Bit 5 — Bit 4 — Bit 3 — Bit 2 — Bit 1 RTSECSEL Bit 0 PMPTTL All Resets 0000 PORTE 02E2 — — LATE 02E4 — — ODCE 02E6 — — Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as ‘0’. TABLE 3-17: PORTF REGISTER MAP File Name Addr Bit 15 Bit 14 TRISF 02E8 — — PORTF 02EA — — LATF 02EC — — ODCF 02EE — — Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’. Bits are unimplemented in 64-pin devices; read as ‘0’. PIC24FJ256GB110 FAMILY Preliminary TABLE 3-18: PORTG REGISTER MAP File Name Addr Bit 15(1) Bit 14(1) TRISG 02F0 TRISG15 TRISG14 TRISG13 TRISG12 PORTG 02F2 RG15 RG14 LATG 02F4 LATG15 LATG14 ODCG 02F6 ODG15 ODG14 Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’. TABLE 3-19: PAD CONFIGURATION REGISTER MAP File Name Addr Bit 15 Bit 14 PADCFG1 02FC — — © 2008 Microchip Technology Inc. Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-20: Bit 13 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 — VCFG0 r ADCS7 CH0NA — PCFG7 CSSL7 — — — PCFG6 CSSL6 — — — PCFG13 CSSL13 — — — — — — CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 — — — — — CH0SB4 CH0SB3 CH0SB2 CH0SB1 CH0SB0 SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 ADCS6 r — CSCNA — — BUFS — r — — ADSIDL — — — FORM1 FORM0 SSRC2 SSRC1 SSRC0 SMPI3 ADCS5 — — PCFG5 CSSL5 — — SMPI2 ADCS4 CH0SA4 — PCFG4 CSSL4 — — SMPI1 ADCS3 CH0SA3 — PCFG3 CSSL3 — ASAM SMPI0 ADCS2 CH0SA2 — PCFG2 CSSL2 — SAMP BUFM ADCS1 CH0SA1 PCFG17 PCFG1 CSSL1 CSS17 DONE ALTS ADCS0 CH0SA0 PCFG16 PCFG0 CSSL0 CSS16 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC REGISTER MAP All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Bit 15 Bit 14 ADC1BUF0 0300 ADC1BUF1 0302 ADC1BUF2 0304 ADC1BUF3 0306 ADC1BUF4 0308 ADC1BUF5 030A © 2008 Microchip Technology Inc. — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 — — — — — — — — ADC1BUF6 030C ADC1BUF7 030E ADC1BUF8 0310 ADC1BUF9 0312 ADC1BUFA 0314 ADC1BUFB 0316 ADC1BUFC 0318 ADC1BUFD 031A ADC1BUFE 031C ADC1BUFF 031E AD1CON1 0320 ADON AD1CON2 0322 VCFG2 VCFG1 AD1CON3 0324 ADRC AD1CHS0 0328 CH0NB PIC24FJ256GB110 FAMILY Preliminary AD1PCFGH 032A — AD1PCFGL 032C PCFG15 PCFG14 AD1CSSL 0330 CSSL15 CSSL14 AD1CSSH 0332 — Legend: — = unimplemented, read as ‘0’, r = reserved, maintain as ‘0’. Reset values are shown in hexadecimal. TABLE 3-21: CTMU REGISTER MAP All Resets 0000 0000 File Name Addr Bit 15 Bit 14 CTMUCON 033C CTMUEN — CTMUICON 033E ITRIM5 ITRIM4 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS39897B-page 45 TABLE 3-22: Bit 13 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — UTEYE UOEMON — — — — — — — — — — — — PID3 PID2 PID1 — — — — — — — — — — — — — — — — — — — — LSPDEN(1) — — — — — JSTATE(1) SE0 TOKBUSY RESET — — — — — — SE0 PKTDIS — — — — — — ENDPT3 ENDPT2 ENDPT1 ENDPT0 — — — — — BTSEE — DMAEE BTOEE DFN8EE DIR HOSTEN HOSTEN — — — — — BTSEE — DMAEE BTOEE DFN8EE — — — — — BTSEF — DMAEF BTOEF DFN8EF — — — — — BTSEF — DMAEF BTOEF DFN8EF — — — — — STALLIE ATTACHIE(1) RESUMEIE IDLEIE TRNIE SOFIE CRC16EF CRC16EF CRC16EE CRC16EE PPBI RESUME RESUME — — — — — STALLIE — RESUMEIE IDLEIE TRNIE SOFIE — — — — — STALLIF ATTACHIF(1) RESUMEIF IDLEIF TRNIF SOFIF — — — — — STALLIF — RESUMEIF IDLEIF TRNIF SOFIF UERRIF UERRIF UERRIE UERRIE CRC5EF EOFEF(1) CRC5EE EOFEE(1) — PPBRST PPBRST — — — — — UACTPND — — USLPGRD — — USUSPND — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG — — — — — ID — LSTATE — SESVD SESEND — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVD VBUSDIS USBPWR URSTIF DETACHIF(1) URSTIE PIDEF PIDEF PIDEE PIDEE — USBEN SOFEN(1) — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF VBUSVDIE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 DETACHIE(1) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PID0 USBSIDL PUVBUS EP3 Start-Of-Frame Count Register — — PPB1 EXTI2CEN UVBUSDIS UVCMPDIS PPB0 UTRDIS EP2 EP1 EP0 0000 0000 0000 0000 USB OTG REGISTER MAP File Name Addr Bit 15 Bit 14 U1OTGIR 0480 — — U1OTGIE 0482 — — DS39897B-page 46 USB Device Address (DEVADDR) Register Buffer Descriptor Table Base Address Register Frame Count Register Low Byte Frame Count Register High Byte U1OTGSTAT 0484 — — U1OTGCON 0486 — — U1PWRC 0488 — — U1IR 048A(1) — — — — U1IE 048C(1) — — — — U1EIR 048E(1) — — — — U1EIE 0490(1) — — — — U1STAT 0492 — — U1CON 0494(1) — — — — U1ADDR 0496 — — U1BDTP1 0498 — — U1FRML 049A — — U1FRMH 049C — — PIC24FJ256GB110 FAMILY Preliminary U1TOK(2) 049E — — U1SOF(2) 04A0 — — U1CNFG1 04A6 — — U1CNFG2 04A8 — — Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. © 2008 Microchip Technology Inc. TABLE 3-22: Bit 13 — — — — — — — — — — — — — — — — USB Power Supply PWM Duty Cycle Register — — — — PWMPOL CNTEN — — — — — — — — — — — — — — — — — — — EPCONDIS EPCONDIS — — — — — — — — — EPCONDIS — — — — — — — — EPCONDIS — — — — — — — — EPCONDIS EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN — — — — — — — — — EPCONDIS EPRXEN — — — — — — — — EPCONDIS EPRXEN — — — — — — — — EPCONDIS EPRXEN — — — — — — — — EPCONDIS EPRXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN — — — — — — — — — EPCONDIS EPRXEN EPTXEN — — — — — — — — EPCONDIS EPRXEN EPTXEN — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL — — — — — LSPD(1) — EPCONDIS EPRXEN EPTXEN EPSTALL RETRYDIS(1) EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 USB OTG REGISTER MAP (CONTINUED) File Name Addr Bit 15 Bit 14 U1EP0 04AA — — U1EP1 04AC — — U1EP2 04AE — — U1EP3 04B0 — — U1EP4 04B2 — — U1EP5 04B4 — — U1EP6 04B6 — — © 2008 Microchip Technology Inc. USB Power Supply PWM Period Register Bit 13 PSIDL IRQM0 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 INCM1 INCM0 MODE16 MODE1 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN MODE0 ADDR8 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 CSF1 WAITB1 ADDR7 Bit 6 CSF0 WAITB0 ADDR6 Bit 5 ALP WAITM3 ADDR5 Bit 4 CS2P WAITM2 ADDR4 Bit 3 CS1P WAITM1 ADDR3 Bit 2 BEP WAITM0 ADDR2 Bit 1 WRSP WAITE1 ADDR1 Bit 0 RDSP WAITE0 ADDR0 Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) PTEN13 — — IB3F PTEN12 PTEN11 PTEN10 IB2F PTEN9 IB1F PTEN8 IB0F PTEN7 OBE PTEN6 OBUF PTEN5 — PTEN4 — PTEN3 OB3E PTEN2 OB2E PTEN1 OB1E PTEN0 OB0E U1EP7 04B8 — — U1EP8 04BA — — U1EP9 04BC — — U1EP10 04BE — — U1EP11 04C0 — — U1EP12 04C2 — — U1EP13 04C4 — — U1EP14 04C6 — — U1EP15 04C8 — — U1PWMRRS 04CC U1PWMCON 04CE PWMEN — PIC24FJ256GB110 FAMILY Preliminary Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. TABLE 3-23: PARALLEL MASTER/SLAVE PORT REGISTER MAP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Bit 15 Bit 14 PMCON 0600 PMPEN — PMMODE 0602 BUSY IRQM1 PMADDR 0604 CS2 CS1 PMDOUT1 PMDOUT2 0606 PMDIN1 0608 PMDIN2 060A PMAEN 060C PTEN15 PTEN14 PMSTAT 060E IBF IBOV DS39897B-page 47 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-24: Bit 13 Alarm Value Register Window Based on ALRMPTR AMASK3 RTCC Value Register Window Based on RTCPTR RTCWREN RTCSYNC HALFSEC RTCOE RTCPTR1 RTCPTR0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx 0000 xxxx 0000 REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name Addr Bit 15 Bit 14 ALRMVAL 0620 ALCFGRPT 0622 ALRMEN CHIME DS39897B-page 48 Bit 13 — — CPOL — — — — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CEVT COUT EVPOL1 EVPOL0 — CREF — — CEVT COUT EVPOL1 EVPOL0 — CREF CPOL CPOL — — — — — — — — CVREN CVROE CVRR CVRSS CVR3 — C3EVT C2EVT C1EVT — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 C3OUT CVR2 — — — Bit 1 C2OUT CVR1 CCH1 CCH1 CCH1 Bit 0 C1OUT CVR0 CCH0 CCH0 CCH0 All Resets 0000 0000 0000 0000 0000 — — COE COE COE Bit 13 CSIDL X13 CRC Data Input Register CRC Result Register X12 X11 X10 X9 X8 X7 X6 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 — X5 Bit 4 CRCGO X4 Bit 3 PLEN3 X3 Bit 2 PLEN2 X2 Bit 1 PLEN1 X1 Bit 0 PLEN0 — All Resets 0040 0000 0000 0000 — RTCVAL 0624 RCFGCAL 0626 RTCEN — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-25: COMPARATORS REGISTER MAP File Name Addr Bit 15 Bit 14 CMSTAT 0630 CMIDL CVRCON 0632 — CM1CON 0634 CON CM2CON 0636 CON CM3CON 0638 CON Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-26: CRC REGISTER MAP File Name Addr Bit 15 Bit 14 PIC24FJ256GB110 FAMILY Preliminary CRCCON 0640 — CRCXOR 0642 X15 X14 CRCDAT 0644 CRCWDAT 0646 Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2008 Microchip Technology Inc. TABLE 3-27: Bit 13 INT1R5 INT3R5 T1CKR5 T3CKR5 T5CKR5 IC2R5 IC4R5 IC6R5 IC8R5 OCFBR5 IC9R5 U3RXR5 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 SCK1R5 U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 SCK2R5 — U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 SCK3R5 — RP1R5 RP3R5 RP5R5(1) RP7R5 RP9R5 RP11R5 RP13R5 RP17R5 RP19R5 RP21R5 RP23R5 RP25R5 RP27R5 RP29R5 RP29R4 RP29R3 RP27R4 RP27R3 RP25R4 RP25R3 RP23R4 RP23R3 RP21R4 RP21R3 RP21R2 RP23R2 RP25R2 RP27R2 RP29R2 RP19R4 RP19R3 RP19R2 RP17R4 RP17R3 RP17R2 RP17R1 RP19R1 RP21R1 RP23R1 RP25R1 RP27R1 RP29R1 RP13R4 RP13R3 RP13R2 RP13R1 RP11R4 RP11R3 RP11R2 RP11R1 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 RP11R0 RP13R0 RP17R0 RP19R0 RP21R0 RP23R0 RP25R0 RP27R0 RP29R0 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 — — — — — — — — — — — — — — — RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 — — — — — — — SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 — — — — SS1R5 SDI2R5 SS2R5 U4RXR5 SDI3R5 SS3R5 RP0R5 RP2R5 RP4R5 RP6R5 RP8R5 RP10R5 RP12R5 RP14R5 RP16R5 RP18R5 RP20R5 RP22R5 RP24R5 RP26R5 RP28R5 RP30R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 — — SDI1R5 — — U2RXR5 — — U1RXR5 U1RXR4 U2RXR4 SDI1R4 SS1R4 SDI2R4 SS2R4 U4RXR4 SDI3R4 SS3R4 RP0R4 RP2R4 RP4R4 RP6R4 RP8R4 RP10R4 RP12R4 RP14R4 RP16R4 RP18R4 RP20R4 RP22R4 RP24R4 RP26R4 RP28R4 RP30R4 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 — — — — IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 — — — — — — U1RXR3 U2RXR3 SDI1R3 SS1R3 SDI2R3 SS2R3 U4RXR3 SDI3R3 SS3R3 RP0R3 RP2R3 RP4R3 RP6R3 RP8R3 RP10R3 RP12R3 RP14R3 RP16R3 RP18R3 RP20R3 RP22R3 RP24R3 RP26R3 RP28R3 RP30R3 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 — — OCFAR5 OCFAR4 OCFAR3 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 — — IC7R5 IC7R4 IC7R3 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 — — IC5R5 IC5R4 IC5R3 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 — — IC3R5 IC3R4 IC3R3 IC3R2 IC5R2 IC7R2 OCFAR2 — — U1RXR2 U2RXR2 SDI1R2 SS1R2 SDI2R2 SS2R2 U4RXR2 SDI3R2 SS3R2 RP0R2 RP2R2 RP4R2 RP6R2 RP8R2 RP10R2 RP12R2 RP14R2 RP16R2 RP18R2 RP20R2 RP22R2 RP24R2 RP26R2 RP28R2 RP30R2 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 — — IC1R5 IC1R4 IC1R3 IC1R2 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 — — T4CKR5 T4CKR4 T4CKR3 T4CKR2 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 — — T2CKR5 T2CKR4 T2CKR3 T2CKR2 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 — — INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 T2CKR1 T4CKR1 IC1R1 IC3R1 IC5R1 IC7R1 OCFAR1 — — U1RXR1 U2RXR1 SDI1R1 SS1R1 SDI2R1 SS2R1 U4RXR1 SDI3R1 SS3R1 RP0R1 RP2R1 RP4R1 RP6R1 RP8R1 RP10R1 RP12R1 RP14R1 RP16R1 RP18R1 RP20R1 RP22R1 RP24R1 RP26R1 RP28R1 RP30R1 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 — — INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 — — — — — — — — INT2R0 INT4R0 T2CKR0 T4CKR0 IC1R0 IC3R0 IC5R0 IC7R0 OCFAR0 — — U1RXR0 U2RXR0 SDI1R0 SS1R0 SDI2R0 SS2R0 U4RXR0 SDI3R0 SS3R0 RP0R0 RP2R0 RP4R0 RP6R0 RP8R0 RP10R0 RP12R0 RP14R0 RP16R0 RP18R0 RP20R0 RP22R0 RP24R0 RP26R0 RP28R0 RP30R0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERIPHERAL PIN SELECT REGISTER MAP All Resets 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 003F 3F3F 3F3F 003F 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 File Name Addr Bit 15 Bit 14 RPINR0 0680 — — RPINR1 0682 — — RPINR2 0684 — — RPINR3 0686 — — RPINR4 0688 — — RPINR7 068E — — © 2008 Microchip Technology Inc. RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2) RPINR8 0690 — — RPINR9 0692 — — RPINR10 0694 — — RPINR11 0696 — — RPINR15 069E — — RPINR17 06A2 — — RPINR18 06A4 — — RPINR19 06A6 — — RPINR20 06A8 — — RPINR21 06AA — — RPINR22 06AC — — RPINR23 06AE — — RPINR27 06B6 — — RPINR28 06B8 — — PIC24FJ256GB110 FAMILY Preliminary RPINR29 06BA — — RPOR0 06C0 — — RPOR1 06C2 — — RPOR2 06C4 — — RPOR3 06C6 — — RPOR4 06C8 — — RPOR5 06CA — — RPOR6 06CC — — RPOR7 06CE — — RPOR8 06D0 — — RPOR9 06D2 — — RPOR10 06D4 — — RPOR11 06D6 — — RPOR12 06D8 — — RPOR13 06DA — — RPOR14 06DC — — DS39897B-page 49 RPOR15 06DE — — Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as ‘0’. Bits are unimplemented in 64-pin and 80-pin devices; read as ‘0’. TABLE 3-28: Bit 13 — COSC1 DOZE1 — ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 — — — — — — — — — — — — — — TUN5 TUN4 TUN3 TUN2 TUN1 DOZE0 DOZEN RCDIV2 RCDIV1 RCDIV0 CPDIV1 CPDIV0 — — — — — — TUN0 — COSC0 — NOSC2 NOSC1 NOSC0 CLKLOCK IOLOCK LOCK — CF POSCEN SOSCEN OSWEN — — — CM VREGS EXTR SWR SWDTEN WDTO SLEEP IDLE BOR POR Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Note 1 Note 2 0100 0000 0000 SYSTEM REGISTER MAP File Name Addr Bit 15 Bit 14 RCON 0740 TRAPR IOPUWR OSCCON — — 0742 — COSC2 DS39897B-page 50 Bit 13 WRERR — — — — — — — — — — — ERASE — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) 0000 NVMKEY Register Bit 13 T3MD IC6MD — — — — — — — — — — — — — IC9MD — — — — — — — — — — CMPMD RTCCMD PMPMD CRCMD IC5MD IC4MD IC3MD IC2MD IC1MD OC8MD T2MD T1MD — — — I2C1MD U2MD OC7MD — UPWMMD — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 U1MD OC6MD — U4MD — — Bit 4 SPI2MD OC5MD — — — — Bit 3 SPI1MD OC4MD U3MD — — Bit 2 — OC3MD I2C3MD REFOMD CTMUMD — — Bit 1 — OC2MD I2C2MD LVDMD — — Bit 0 ADC1MD OC1MD — USB1MD OC9MD SPI3MD All Resets 0000 0000 0000 0000 0000 0000 — — — — CLKDIV 0744 ROI DOZE2 OSCTUN 0748 — REFOCON 074E ROEN Legend: Note 1: 2: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. The Reset value of the RCON register is dependent on the type of Reset event. See Section 5.0 “Resets” for more information. The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 7.0 “Oscillator Configuration” for more information. TABLE 3-29: NVM REGISTER MAP File Name Addr Bit 15 Bit 14 NVMCON 0760 WR WREN NVMKEY 0766 — — Legend: Note 1: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 3-30: PMD REGISTER MAP PIC24FJ256GB110 FAMILY Preliminary File Name Addr Bit 15 Bit 14 PMD1 0770 T5MD T4MD PMD2 0772 IC8MD IC7MD PMD3 0774 — PMD4 0776 — PMD5 0778 — PMD6 077A — Legend: — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.2.5 SOFTWARE STACK 3.3 In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (program space visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. 3.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, whereas D refers to a data space word. FIGURE 3-4: 0000h 15 CALL STACK FRAME 0 Stack Grows Towards Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2008 Microchip Technology Inc. Preliminary DS39897B-page 51 PIC24FJ256GB110 FAMILY TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Visibility (Block Remap/Read) Note 1: User 0 0 Program Space Address 0 TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx PSVPAG xxxx xxxx PC 0xx xxxx xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 Bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 Bits 24 Bits 16 Bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 Bits 1 EA 0 15 Bits 23 Bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS39897B-page 52 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom’ byte, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (byte select = 1). The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P) to a data address (D). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is ‘1’; the lower byte is selected when it is ‘0’. In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed. FIGURE 3-6: TBLPAG 02 ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space Data EA 23 15 0 000000h 00000000 020000h 030000h 00000000 00000000 00000000 ‘Phantom’ Byte 23 16 8 0 TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 800000h © 2008 Microchip Technology Inc. Preliminary DS39897B-page 53 PIC24FJ256GB110 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’, and program space visibility is enabled by setting the PSV bit in the CPU Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. FIGURE 3-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 000000h 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... Data Space 0000h Data EA 8000h PSV Area ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. FFFFh 800000h DS39897B-page 54 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 4.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 4. Program Memory” (DS39715). RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time. 4.1 Table Instructions and Flash Programming The PIC24FJ256GB110 family of devices contains internal Flash program memory for storing and executing application code. It can be programmed in four ways: • • • • In-Circuit Serial Programming™ (ICSP™) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial Programming™ (Enhanced ICSP™) Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ICSP allows a PIC24FJ256GB110 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx and PGEDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 Bits 16 Bits User/Configuration Space Select 24-Bit EA Byte Select © 2008 Microchip Technology Inc. Preliminary DS39897B-page 55 PIC24FJ256GB110 FAMILY 4.2 RTSP Operation 4.3 JTAG Operation The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended. The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin-to-PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF). 4.4 Enhanced In-Circuit Serial Programming Enhanced In-Circuit Serial Programming uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification. 4.5 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 “Programming Operations” for further details. 4.6 Programming Operations All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation and the WR bit is automatically cleared when the operation is finished. DS39897B-page 56 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 4-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Set Only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) NVMOP3(2) R/W-0(1) NVMOP2(2) R/W-0(1) NVMOP1(2) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) NVMOP0(2) bit 0 WREN R/W-0(1) WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit(1) 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command Unimplemented: Read as ‘0’ NVMOP3:NVMOP0: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) These bits can only be reset on POR. All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSP™ mode only. Refer to device programming specification. bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: 3: © 2008 Microchip Technology Inc. Preliminary DS39897B-page 57 PIC24FJ256GB110 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-1). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3. EXAMPLE 4-1: ERASING A PROGRAM MEMORY BLOCK ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. 20.1.2 INTERRUPT OPERATION When the VWORD4:VWORD0 bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. 20.2 20.2.1 Operation in Power Save Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 20.2.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. DS39897B-page 246 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 20.3 Registers There are four registers used to control programmable CRC operation: • • • • CRCCON CRCXOR CRCDAT CRCWDAT REGISTER 20-1: U-0 — bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 CRCCON: CRC CONTROL REGISTER U-0 — R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 R-1 U-0 — R/W-0 CRCGO R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 R/W-0 PLEN0 bit 0 CRCMPT W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 ≤ 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as ‘0’ CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 247 PIC24FJ256GB110 FAMILY REGISTER 20-2: R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 — bit 0 CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14 R/W-0 X15:X1: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as ‘0’ DS39897B-page 248 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 21.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 17. 10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is shown in Figure 21-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFGL and AD1PCFGH). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. The 10-bit A/D Converter has the following key features: • • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 16 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. On all PIC24FJ256GB110 family devices, the 10-bit A/D Converter has 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 249 PIC24FJ256GB110 FAMILY FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD AVSS VREF+ VREFVINH AN0 AN1 AN2 AN3 MUX A AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 VBG VBG/2 Sample Control Input MUX Control Pin Config Control VRS/H VR+ VR Select VR+ 16 VRComparator VINL DAC VINH 10-Bit SAR Conversion Logic Data Formatting VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS0 MUX B VINH AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH VINL Control Logic Conversion Control DS39897B-page 250 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-1: R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 — U-0 — R/W-0 ASAM R/W-0, HCS SAMP AD1CON1: A/D CONTROL REGISTER 1 U-0 — R/W-0 ADSIDL U-0 — U-0 — U-0 — R/W-0 FORM1 R/W-0 FORM0 bit 8 R/W-0, HCS DONE bit 0 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = CTMU event ends sampling and starts conversion 011 = Timer5 compare ends sampling and starts conversion 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion Unimplemented: Read as ‘0’ ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. bit 14 bit 13 bit 12-10 bit 9-8 bit 7-5 bit 4-3 bit 2 bit 1 bit 0 Note 1: © 2008 Microchip Technology Inc. Preliminary DS39897B-page 251 PIC24FJ256GB110 FAMILY REGISTER 21-2: R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ r = Reserved bit’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG0 r-0 r U-0 — R/W-0 CSCNA U-0 — U-0 — bit 8 R/W-0 ALTS bit 0 R/W-0 VCFG1 VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 Reserved: Maintain as ‘0’ Unimplemented: Read as ‘0’ CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F Unimplemented: Read as ‘0’ SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer configured as one 16-word buffer (ADC1BUFn) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings bit 9-8 bit 7 bit 6 bit 5-2 bit 1 bit 0 DS39897B-page 252 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-3: R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set r = Reserved bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 r AD1CON3: A/D CONTROL REGISTER 3 r-0 r-0 r R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Reserved: Maintain as ‘0’ SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 • TCY ······ 00000001 = 2 • TCY 00000000 = TCY bit 14-13 bit 12-8 bit 7-0 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 253 PIC24FJ256GB110 FAMILY REGISTER 21-4: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 CH0SA4 R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 AD1CHS0: A/D INPUT SELECT REGISTER U-0 — U-0 — R/W-0 CH0SB4(1) R/W-0 CH0SB3(1) R/W-0 CH0SB2(1) R/W-0 CH0SB1(1) R/W-0 CH0SB0(1) bit 8 R/W-0 CH0SA0 bit 0 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SB4:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1) 10001 = Channel 0 positive input is internal band gap reference (VBG) 10000 = Channel 0 positive input is VBG/2 01111 = Channel 0 positive input is AN15 01110 = Channel 0 positive input is AN14 01101 = Channel 0 positive input is AN13 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 01010 = Channel 0 positive input is AN10 01001 = Channel 0 positive input is AN9 01000 = Channel 0 positive input is AN8 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Channel 0 positive input is AN5 00100 = Channel 0 positive input is AN4 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SA4:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Implemented combinations are identical to those for CHOSB4:CHOSB0 (above). Combinations not shown here are unimplemented; do not use. bit 14-13 bit 12-8 bit 7 bit 6-5 bit 4-0 Note 1: DS39897B-page 254 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-5: R/W-0 PCFG15 bit 15 R/W-0 PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 AD1PCFGL: A/D PORT CONFIGURATION REGISTER (LOW) R/W-0 PCFG13 R/W-0 PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0 PCFG8 bit 8 R/W-0 PCFG0 bit 0 R/W-0 PCFG14 PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage REGISTER 21-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 AD1PCFGH: A/D PORT CONFIGURATION REGISTER (HIGH) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 PCFG17 R/W-0 PCFG16 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ PCFG17: A/D Input Band Gap Scan Enable bit 1 = Internal band gap (VBG) channel enabled for input scan 0 = Analog channel disabled from input scan PCFG16: A/D Input Half Band Gap Scan Enable bit 1 = Internal VBG/2 channel enabled for input scan 0 = Analog channel disabled from input scan bit 0 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 255 PIC24FJ256GB110 FAMILY REGISTER 21-7: R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 bit 8 R/W-0 CSSL0 bit 0 R/W-0 CSSL14 CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan REGISTER 21-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 CSSL17 R/W-0 CSSL16 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSSL17: A/D Input Band Gap Scan Selection bit 1 = Internal band gap (VBG) channel selected for input scan 0 = Analog channel omitted from input scan CSSL16: A/D Input Half Band Gap Scan Selection bit 1 = Internal VBG/2 channel selected for input scan 0 = Analog channel omitted from input scan bit 0 DS39897B-page 256 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY EQUATION 21-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. FIGURE 21-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD ANx VT = 0.6V RIC ≤ 250Ω Sampling Switch RSS CHOLD = DAC capacitance = 4.4 pF (Typical) VSS RSS ≤ 5 kΩ (Typical) Rs VA CPIN 6-11 pF (Typical) VT = 0.6V ILEAKAGE ±500 nA Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs ≤ 5 kΩ. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 257 PIC24FJ256GB110 FAMILY FIGURE 21-3: Output Code (Binary (Decimal)) A/D TRANSFER FUNCTION 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ – VR-) 512*(VR+ – VR-) (VINH – VINL) VR+ – VRVR+ 1024 0 VR- 1024 Voltage Level VR- + VR- + 1024 DS39897B-page 258 Preliminary © 2008 Microchip Technology Inc. VR- + PIC24FJ256GB110 FAMILY 22.0 Note: TRIPLE COMPARATOR MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual” chapter. The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 22-1. Diagrams of the possible individual comparator configurations are shown in Figure 22-2. Each comparator has its own control register, CMxCON (Register 22-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 22-2). The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs as well, as a voltage reference input from either the internal band gap reference divided by two (VBG/2) or the comparator voltage reference generator. FIGURE 22-1: CCH1:CCH0 CREF TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE VINCXINB CXINC CXIND VBG/2 VIN+ Input Select Logic C1 CPOL COUT C1OUT Pin EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE CPOL VINVIN+ C2 COUT C2OUT Pin CXINA CVREF VINVIN+ C3 EVPOL1:EVPOL0 Trigger/Interrupt Logic CEVT COE CPOL COUT C3OUT Pin © 2008 Microchip Technology Inc. Preliminary DS39897B-page 259 PIC24FJ256GB110 FAMILY FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH1:CCH0 = xx VINVIN+ COE Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 00 CXINB CXINA VINVIN+ COE Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 01 CXINC CxOUT Pin CXINA VINVIN+ COE Cx Cx CxOUT Pin Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 10 CXIND CXINA VINVIN+ COE Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 11 VBG/2 CxOUT Pin CXINA VINVIN+ COE Cx Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 00 CXINB CVREF VINVIN+ COE Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 01 CXINC CxOUT Pin CVREF VINVIN+ COE Cx Cx CxOUT Pin Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 10 CXIND CVREF VINVIN+ COE Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 11 VBG/2 CxOUT Pin CVREF VINVIN+ COE Cx Cx CxOUT Pin DS39897B-page 260 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 22-1: R/W-0 CON bit 15 R/W-0 EVPOL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 CPOL U-0 — U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 CCH0 bit 0 COE R/W-0 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as ‘0’ CEVT: Comparator Event bit 1 = Comparator event defined by to EVPOL1:EVPOL0 has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL1:EVPOL0: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7-6 bit 5 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 261 PIC24FJ256GB110 FAMILY REGISTER 22-1: bit 4 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CXINA pin Unimplemented: Read as ‘0’ CCH1:CCH0: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CXIND pin 01 = Inverting input of comparator connects to CXINC pin 00 = Inverting input of comparator connects to CXINB pin bit 3-2 bit 1-0 REGISTER 22-2: R/W-0 CMIDL bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CMSTAT: COMPARATOR MODULE STATUS REGISTER U-0 — U-0 — U-0 — U-0 — R-0 C3EVT R-0 C2EVT R-0 C1EVT bit 8 U-0 — U-0 — U-0 — U-0 — R-0 C3OUT R-0 C2OUT R-0 C1OUT bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as ‘0’ C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). Unimplemented: Read as ‘0’ C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 bit 1 bit 0 DS39897B-page 262 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 23.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, ”Section 20. Comparator Voltage Reference Module” (DS39709). voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. 23.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 23-1). The comparator voltage reference provides two ranges of output FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSS = 0 8R R R R CVR3:CVR0 CVREN 16 Steps 16-to-1 MUX R CVREF R R R CVRR VREFCVRSS = 1 8R CVRSS = 0 AVSS © 2008 Microchip Technology Inc. Preliminary DS39897B-page 263 PIC24FJ256GB110 FAMILY REGISTER 23-1: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as ‘0’ CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR3:CVR0: Comparator VREF Value Selection 0 ≤ CVR3:CVR0 ≤ 15 bits When CVRR = 1: CVREF = (CVR/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC) bit 6 bit 5 bit 4 bit 3-0 DS39897B-page 264 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual” chapter. 24.1 Measuring Capacitance The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: dV C = I ⋅ -----dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 24-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register has controls the selection and trim of the current source. FIGURE 24-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter ANx ANY Current Source CAPP RPR © 2008 Microchip Technology Inc. Preliminary DS39897B-page 265 PIC24FJ256GB110 FAMILY 24.2 Measuring Time Time measurements on the pulse width can be similarly performed, using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 24-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the PIC24F Family Reference Manual. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 24-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. 24.3 Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 24-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse A/D Converter CAD RPR Current Source ANx FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB C2 CDELAY CVREF DS39897B-page 266 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 24-1: R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT CTMUCON: CTMU CONTROL REGISTER U-0 — R/W-0 CTMUSIDL R/W-0 TGEN R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0 EDG1STAT bit 0 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as ‘0’ CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL1:EDG2SEL0: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response bit 14 bit 13 bit 12 bit 10 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 267 PIC24FJ256GB110 FAMILY REGISTER 24-1: bit 3-2 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1SEL1:EDG1SEL0: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred bit 1 bit 0 REGISTER 24-2: R/W-0 ITRIM5 bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 R/W-0 ITRIM4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ITRIM5:ITRIM0: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG1:IRNG0 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current IRNG1:IRNG0: Current Source Range Select bits 11 = 100 × Base current 10 = 10 × Base current 01 = Base current level (0.55 μA nominal) 00 = Current source disabled Unimplemented: Read as ‘0’ bit 9-8 bit 7-0 DS39897B-page 268 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) 25.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ256GB110 FAMILY DEVICES PIC24FJ256GB110 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation In PIC24FJ256GB110 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 25-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. 25.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-5. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 25-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256GB110 FAMILY DEVICES Configuration Word Addresses 1 ABFEh 157FEh 20BFEh 2ABFEh 2 ABFCh 157FC 20BFC 2ABFC 3 ABFAh 157FA 20BFA 2ABFA Device PIC24FJ64GB1 PIC24FJ128GB1 PIC24FJ192GB1 PIC24FJ256GB1 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 269 PIC24FJ256GB110 FAMILY REGISTER 25-1: U-1 — bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 Unimplemented: Read as ‘1’ Reserved: The value is unknown; program as ‘0’ JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Reserved: Always maintain as ‘1’ ICS1:ICS0: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be ‘1’ Unimplemented: Read as ‘1’ FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while programming the device through the JTAG interface. r = Reserved bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/PO-1 WINDIS U-1 — R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG r-1 r R/PO-1 ICS1 CW1: FLASH CONFIGURATION WORD 1 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4 Note 1: DS39897B-page 270 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 25-1: bit 3-0 CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while programming the device through the JTAG interface. Note 1: © 2008 Microchip Technology Inc. Preliminary DS39897B-page 271 PIC24FJ256GB110 FAMILY REGISTER 25-2: U-1 — bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 CW2: FLASH CONFIGURATION WORD 2 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 r-0 r R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY R/PO-1 DISUVREG r-1 r R/PO-1 POSCMD1 Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 r = Reserved bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4 Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled PLLDIV2:PLLDIV0: USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 10 (40 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) 100 = Oscillator input divided by 5 (20 MHz input) 011 = Oscillator input divided by 4 (16 MHz input) 010 = Oscillator input divided by 3 (12 MHz input) 001 = Oscillator input divided by 2 (8 MHz input) 000 = Oscillator input used directly (4 MHz input) Reserved: Always maintain as ‘0’ FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON)can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed DS39897B-page 272 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 25-2: bit 3 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 2 bit 1-0 DISUVREG: Internal USB 3.3V Regulator Disable bit 1 = Regulator is disabled 0 = Regulator is enabled Reserved: Always maintain as ‘1’ POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected REGISTER 25-3: U-1 — bit 23 R/PO-1 WPEND bit 15 R/PO-1 WPFP7 bit 7 CW3: FLASH CONFIGURATION WORD 3 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 WPFP8 bit 8 R/PO-1 WPFP0 bit 0 R/PO-1 WPCFG R/PO-1 WPDIS U-1 — U-1 — U-1 — U-1 — R/PO-1 WPFP6 R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 14 bit 13 bit 12-9 bit 8-0 Unimplemented: Read as ‘1’ WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP8:WPFP0 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP8:WPFP0 WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection disabled 0 = Segmented code protection enabled; protected segment defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as ‘1’ WPFP8:WPFP0: Protected Code Segment Boundary Page bits Designates the 16 K word program code page that is the boundary of the protected code segment, starting with Page 0 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = ‘0’: First address of designated code page is the lower boundary of the segment. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 273 PIC24FJ256GB110 FAMILY REGISTER 25-4: U — bit 23 U — bit 15 R FAMID1 bit 7 DEVID: DEVICE ID REGISTER U — U — U — U — U — U — U — bit 16 R FAMID2 bit 8 R DEV0 bit 0 U — R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 Legend: R = Read-only bit bit 23-14 bit 13-6 bit 5-0 U = Unimplemented bit Unimplemented: Read as ‘1’ FAMID7:FAMID0: Device Family Identifier bits 01000000 = PIC24FJ256GB110 family DEV5:DEV0: Individual Device Identifier bits 000001 = PIC24FJ64GB106 000011 = PIC24FJ64GB108 000111 = PIC24FJ64GB110 001001 = PIC24FJ128GB106 001011 = PIC24FJ128GB108 001111 = PIC24FJ128GB110 010001 = PIC24FJ192GB106 010011 = PIC24FJ192GB108 010111 = PIC24FJ192GB110 011001 = PIC24FJ256GB106 011011 = PIC24FJ256GB108 011111 = PIC24FJ256GB110 REGISTER 25-5: U — bit 23 U — bit 15 R MAJRV1 bit 7 DEVREV: DEVICE REVISION REGISTER U — U — U — U — U — U — U — bit 16 R MAJRV2 bit 8 R DOT0 bit 0 U — U — U — U — U — U — R MAJRV0 U — U — U — R DOT2 R DOT1 Legend: R = Read-only bit bit 23-9 bit 8-6 bit 5-3 bit 2-0 U = Unimplemented bit Unimplemented: Read as ‘0’ MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as ‘0’ DOT2:DOT0: Minor Revision Identifier bits DS39897B-page 274 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.2 On-Chip Voltage Regulator FIGURE 25-1: All PIC24FJ256GB110 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB110 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 28.1 “DC Characteristics”. If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-1 for possible configurations. CONNECTIONS FOR THE ON-CHIP REGULATOR Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ256GB VDD ENVREG VDDCORE/VCAP CEFC (10 μF typ) VSS Regulator Disabled (ENVREG tied to ground): 2.5V(1) 3.3V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS 25.2.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent “brown out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled. Note 1: These are typical operating voltages. Refer to Section 28.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. 25.2.2 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 500 μs for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 275 PIC24FJ256GB110 FAMILY 25.2.3 ON-CHIP REGULATOR AND BOR 25.3 Watchdog Timer (WDT) When the on-chip regulator is enabled, PIC24FJ256GB110 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage specifications are provided in Section 7. Reset” (DS39712) in the “PIC24F Family Reference Manual”. For PIC24FJ256GB110 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (CW1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 25.2.4 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: For more information, see Section 28.0 “Electrical Characteristics”. 25.2.5 VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON). By default, this bit is cleared, which enables Standby mode. When waking up from Standby mode, the regulator will require around 190 μs to wake-up. This extra time is needed to ensure that the regulator can source enough current to power the Flash memory. For applications which require a faster wake-up time, it is possible to disable regulator Standby mode. The VREGS bit (RCON) can be set to turn off Standby mode so that the Flash stays powered when in Sleep mode and the device can wake-up in 10 μs. When VREGS is set, the power consumption while in Sleep mode, will be approximately 40 μA higher than power consumption when the regulator is allowed to enter Standby mode. DS39897B-page 276 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.3.1 WINDOWED OPERATION 25.3.2 CONTROL REGISTER The Watchdog Timer has an optional fixed-window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. FIGURE 25-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS3:WDTPS0 Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake from Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode 25.4 Program Verification and Code Protection 25.4.2 CODE SEGMENT PROTECTION PIC24FJ256GB110 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 25.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256GB110 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked. In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in PIC24FJ256GB110 family devices can be located by the user anywhere in the program space, and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. They do not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 277 PIC24FJ256GB110 FAMILY The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. The various options for segment code protection are shown in Table 25-2. 25.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting. TABLE 25-2: WPDIS 1 1 0 SEGMENT CODE PROTECTION CONFIGURATION OPTIONS WPCFG 1 0 0 Write/Erase Protection of Code Segment No additional protection enabled; all program memory protection configured by GCP and GWRP Last code page protected, including Flash Configuration Words Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words Address 000000h through last address of code page defined by WPFP8:WPFP0 (inclusive) protected Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected Segment Configuration Bits WPEND X X 1 0 0 0 1 0 1 0 0 1 DS39897B-page 278 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.5 JTAG Interface 25.7 In-Circuit Debugger PIC24FJ256GB110 family devices implement a JTAG interface, which supports boundary scan device testing as well as In-Circuit Serial Programming. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 25.6 In-Circuit Serial Programming PIC24FJ256GB110 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 279 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 280 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.0 DEVELOPMENT SUPPORT 26.1 The PIC® microcontrollers are supported with a full range of hardware and software development tools: • Integrated Development Environment - MPLAB® IDE Software • Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debugger - MPLAB ICD 2 • Device Programmers - PICSTART® Plus Development Programmer - MPLAB PM3 Device Programmer - PICkit™ 2 Development Programmer • Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Visual device initializer for easy register initialization • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either assembly or C) • One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 281 PIC24FJ256GB110 FAMILY 26.2 MPASM Assembler 26.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB ASM30 Assembler, Linker and Librarian MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 26.6 MPLAB SIM Software Simulator 26.3 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip’s PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. 26.4 MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39897B-page 282 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 26.9 MPLAB ICD 2 In-Circuit Debugger Microchip’s In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip’s In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft® Windows® 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. 26.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 283 PIC24FJ256GB110 FAMILY 26.11 PICSTART Plus Development Programmer The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. 26.13 Demonstration, Development and Evaluation Boards A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 26.12 PICkit 2 Development Programmer The PICkit™ 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip’s baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH’s PICC™ Lite C compiler, and is designed to help get up to speed quickly using PIC® microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip’s powerful, mid-range Flash memory family of microcontrollers. DS39897B-page 284 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 27.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 27-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 27-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) © 2008 Microchip Technology Inc. Preliminary DS39897B-page 285 PIC24FJ256GB110 FAMILY TABLE 27-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address ∈ {0000h...1FFFh} 1-bit unsigned literal ∈ {0,1} 4-bit unsigned literal ∈ {0...15} 5-bit unsigned literal ∈ {0...31} 8-bit unsigned literal ∈ {0...255} 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal ∈ {0...16383} 16-bit unsigned literal ∈ {0...65535} 23-bit unsigned literal ∈ {0...8388607}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal ∈ {-512...511} 16-bit signed literal ∈ {-32768...32767} 6-bit signed literal ∈ {-16...16} Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers ∈ {W0..W15} One of 16 destination working registers ∈ {W0..W15} One of 16 source working registers ∈ {W0..W15} W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39897B-page 286 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BRA BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSW BTG BTSC BSET BSET BSW.C BSW.Z BTG BTG BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None 1 None (2 or 3) 1 None (2 or 3) © 2008 Microchip Technology Inc. Preliminary DS39897B-page 287 PIC24FJ256GB110 FAMILY TABLE 27-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CLR CALL CALL CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CPB CP0 CP0 CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if ≠ Wn = Decimal Adjust Wn f = f –1 WREG = f –1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39897B-page 288 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: Assembly Mnemonic GOTO INC GOTO GOTO INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP POP NOP NOPR POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns+Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns+Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns+1) to Wd Move Double from Ws to W(nd+1):W(nd) {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns+1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None © 2008 Microchip Technology Inc. Preliminary DS39897B-page 289 PIC24FJ256GB110 FAMILY TABLE 27-2: Assembly Mnemonic PWRSAV RCALL REPEAT RESET RETFIE RETLW RETURN RLC PWRSAV RCALL RCALL REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None DS39897B-page 290 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: Assembly Mnemonic TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N © 2008 Microchip Technology Inc. Preliminary DS39897B-page 291 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 292 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GB110 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB110 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +100°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1) ................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 28-1). †NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 293 PIC24FJ256GB110 FAMILY 28.1 DC Characteristics PIC24FJ256GB110 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.25V 2.00V PIC24FJXXXGB1XX 2.25V 2.75V FIGURE 28-1: 16 MHz Frequency 32 MHz For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE ≤ VDD ≤ 3.6V. TABLE 28-1: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA Min -40 -40 Typ — — Max +125 +85 Unit °C °C PIC24FJ256GB110 family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – Σ IOH) I/O Pin Power Dissipation: PI/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W PD PINT + PI/O W TABLE 28-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol θJA θJA θJA Typ 50.0 69.4 76.6 Max — — — Unit °C/W °C/W °C/W Notes (Note 1) (Note 1) (Note 1) Package Thermal Resistance, 14x14x1 mm TQFP Package Thermal Resistance, 12x12x1 mm TQFP Package Thermal Resistance, 10x10x1 mm TQFP Note 1: Junction to ambient thermal resistance, Theta-JA (θJA) numbers are achieved by package simulations. DS39897B-page 294 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start VoltAge To ensure internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal 2.2 VDDCORE 2.0 1.5 — — — — — VSS 3.6 3.6 2.75 — — V V V V V Regulator enabled Regulator disabled Regulator disabled Characteristic DC17 SVDD .05 — — V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms Note 1: 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 295 PIC24FJ256GB110 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC20a DC20b DC20d DC20e DC20f DC23 DC23a DC23b DC23d DC23e DC23f DC24 DC24a DC24b DC24d DC24e DC24f DC31 DC31a DC31b DC31d DC31e DC31f Note 1: 2: Typical(1) Operating Current (IDD)(2) 0.83 0.83 0.83 1.1 1.1 1.1 3.3 3.3 3.3 4.3 4.3 4.3 18.2 18.2 18.2 18.2 18.2 18.2 15.0 15.0 20.0 57.0 57.0 95.0 1.2 1.2 1.2 1.6 1.6 1.6 4.3 4.3 4.3 6 6 6 24 24 24 24 24 24 20 20 26 75 75 124 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39897B-page 296 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC40 DC40a DC40b DC40d DC40e DC40f DC43 DC43a DC43b DC43d DC43e DC43f DC47 DC47a DC47b DC47c DC47d DC47e DC50 DC50a DC50b DC50d DC50e DC50f DC51 DC51a DC51b DC51d DC51e DC51f Note 1: 2: Typical(1) Idle Current (IIDLE)(2) 220 220 220 300 300 300 0.85 0.85 0.87 1.1 1.1 1.1 4.4 4.4 4.4 4.4 4.4 4.4 1.1 1.1 1.1 1.4 1.4 1.4 4.3 4.5 7.2 38 44 70 290 290 290 390 390 420 1.1 1.1 1.2 1.4 1.4 1.4 5.6 5.6 5.6 5.6 5.6 5.6 1.4 1.4 1.4 1.8 1.8 1.8 6.0 6.0 25 50 60 110 μA μA μA μA μA μA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 297 PIC24FJ256GB110 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60b DC60c DC60d DC60e DC60f DC60g DC60h DC61 DC61a DC61b DC61c DC61d DC61e DC61f DC61g DC61h DC62 DC62a DC62b DC62c DC62d DC62e DC62f DC62g DC62h Note 1: 2: Typical(1) Power-Down Current (IPD)(2) 0.1 0.15 3.7 0.2 0.25 4.2 3.6 4.0 11.0 1.75 1.75 1.75 2.4 2.4 2.4 2.8 2.8 2.8 2.5 2.5 3.0 2.8 3.0 3.0 3.5 3.5 4.0 1 1 18 1.3 1.3 27 9 10 36 3 3 3 4 4 4 5 5 5 7 7 7 7 7 7 10 10 10 μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA μA -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C -40°C +25°C +85°C 3.3V(4) 2.5V(3) RTCC + Timer1 w/32 kHz Crystal: ΔRTCC + ΔITI32(5) 2.0V(3) 3.3V(4) 2.5V(3) Watchdog Timer Current: ΔIWDT(5) 2.0V(3) 3.3V(4) 2.5V(3) Base Power-Down Current(5) 2.0V(3) 3: 4: 5: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, VREGS bit is clear, and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39897B-page 298 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins with ST Buffer I/O Pins with TTL Buffer MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2C™ Buffer: I/O Pins with SMBus Buffer: Input High Voltage(4) I/O Pins with ST Buffer: with Analog Functions, Digital Only I/O Pins with TTL Buffer: with Analog Functions, Digital Only MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2C Buffer: with Analog Functions, Digital Only I/O Pins with SMBus Buffer: with Analog Functions, Digital Only ICNPU CNxx Pull-up Current IIL DI50 DI51 DI55 DI56 Note 1: 2: Input Leakage I/O Ports Analog Input Pins MCLR OSC1 Current(2,3) — — — — — — — — +1 +1 +1 +1 μA μA μA μA VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD, Pin at high-impedance VSS ≤ VPIN ≤ VDD VSS ≤ VPIN ≤ VDD, XT and HS modes 0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 50 250 — — — — — — — — — VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 400 V V V V V V V V V 2.5V ≤ VPIN ≤ VDD V V μA VDD = 3.3V, VPIN = VSS VSS VSS VSS VSS VSS VSS VSS — — — — — — — 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled DI21 DI25 DI26 DI27 DI28 DI29 DI30 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-4 for I/O pins buffer types. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 299 PIC24FJ256GB110 FAMILY TABLE 28-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 VOH DO20 Sym VOL Characteristic Output Low Voltage I/O Ports OSC2/CLKO Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 DO26 Note 1: OSC2/CLKO 2.4 1.4 — — — — — — — — — — — — V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -3.0 mA, VDD = 2.0V IOH = -6.0 mA, VDD = 3.6V IOH = -3.0 mA, VDD = 2.0V — — — — — — — — 0.4 0.4 0.4 0.4 V V V V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V IOL = 8.5 mA, VDD = 3.6V IOL = 6.0 mA, VDD = 2.0V Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. D130 D131 D132B D133A D133B D134 D135 Note 1: Sym Characteristic Program Flash Memory EP VPR TIW TIE Cell Endurance VDD for Read Self-Timed Write Cycle Time Self-Timed Page Erase Time 10000 VMIN 2.25 — 40 20 — — — — 3 — — 7 — 3.6 3.6 — — — — E/W V V ms ms Year mA -40°C to +85°C VMIN = Minimum operating voltage VMIN = Minimum operating voltage VPEW VDD for Self-Timed Write TRETD Characteristic Retention IDDP Supply Current during Programming Provided no other specifications are violated Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. TABLE 28-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. VRGOUT CEFC Characteristics Regulator Output Voltage External Filter Capacitor Value Min — 4.7 Typ 2.5 10 Max — — Units V μF Series resistance < 3 Ohm recommended; < 5 Ohm required. ENVREG tied to VDD ENVREG tied to VSS Comments TVREG TPWRT — — 50 64 — — μs ms DS39897B-page 300 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 28.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256GB110 family AC characteristics and timing parameters. TABLE 28-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Operating voltage VDD range as described in Section 28.1 “DC Characteristics”. FIGURE 28-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSCO Load Condition 1 – for all pins except OSCO VDD/2 RL Pin VSS CL Pin VSS CL RL = 464Ω CL = 50 pF for all pins except OSCO 15 pF for OSCO output TABLE 28-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI. EC mode. In I2C™ mode. DO56 DO58 Note 1: CIO CB All I/O pins and OSCO SCLx, SDAx — — — — 50 400 pF pF Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 301 PIC24FJ256GB110 FAMILY FIGURE 28-3: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 TABLE 28-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min DC 4 3 4 10 10 31 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — — 6 6 Max 32 48 10 8 32 32 33 — DC — 20 10 10 Units MHz MHz MHz MHz MHz MHz kHz — ns ns ns ns ns EC EC EC ECPLL XT XTPLL HS HSPLL SOSC See parameter OS10 for FOSC value Conditions FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency OS20 OS25 OS30 OS31 OS40 OS41 TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2) TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3) Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39897B-page 302 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range(2) PLL Output Frequency Range Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min 4 95.76 — -0.25 Typ(2) — — — — Max 32 96.24 200 0.25 Units MHz MHz μs % Conditions ECPLL, HSPLL, XTPLL modes TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter) These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F20 Note 1: FRC Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions Internal FRC Accuracy @ 8 MHz(1) -2 -5 — — 2 5 % % +25°C -40°C ≤ TA ≤ +85°C 3.0V≤ VDD ≤ 3.6V 3.0V≤ VDD ≤ 3.6V Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. TABLE 28-16: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. F21 Note 1: Characteristic LPRC @ 31 kHz(1) -20 — 20 % -40°C ≤ TA ≤ +85°C 3.0V≤ VDD ≤ 3.6V Change of LPRC frequency as VDD changes. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min Typ Max Units Conditions © 2008 Microchip Technology Inc. Preliminary DS39897B-page 303 PIC24FJ256GB110 FAMILY FIGURE 28-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 28-2 for load conditions. New Value TABLE 28-17: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39897B-page 304 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-18: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Symbol Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C Min. Typ Max. Units Conditions Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 V AD02 AD05 AD06 AD07 AVSS VREFH VREFL VREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage — — — — V V V V Reference Inputs Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN VINL — Absolute Input Voltage Absolute VINL Input Voltage Leakage Current VREFL AVSS – 0.3 AVSS – 0.3 — ±0.00 1 — — — VREFH AVDD + 0.3 AVDD/2 ±0.610 V V V μA VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 kΩ 10-bit (Note 2) — AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) — 2.5K Ω ADC Accuracy AD20b Nr AD21b INL AD22b DNL AD23b GERR AD24b EOFF AD25b — Note 1: 2: — — — — — — 10 ±1 ±0.5 ±1 ±1 — — 74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c φ A2 α β L A1 L1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E   ƒ ƒ ƒ ±    0,1 0,//,0(7(56 120   %6& ±  ±   5() ƒ  %6&  %6&  %6&  %6& ±  ƒ ƒ   ƒ ƒ ƒ     0$; 1RWHV  3LQ  YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD  &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( 74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2008 Microchip Technology Inc. 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Preliminary DS39897B-page 315 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 316 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY APPENDIX A: REVISION HISTORY Revision A (October 2007) Original data sheet for the PIC24FJ256GB110 family of devices. Revision B (March 2008) Changes to Section 28.0 “Electrical Characteristics” and minor edits to text throughout document. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 317 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 318 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY INDEX A A/D Converter Analog Input Model ................................................... 257 Transfer Function...................................................... 258 AC Characteristics ADC Conversion Timing ........................................... 306 CLKO and I/O Timing................................................ 304 AC Characteristics Internal RC Accuracy ................................................ 303 Alternate Interrupt Vector Table (AIVT) .............................. 67 Assembler MPASM Assembler................................................... 282 PSV Operation............................................................ 54 Reset System ............................................................. 61 RTCC........................................................................ 235 Shared I/O Port Structure ......................................... 121 SPI Master, Frame Master Connection .................... 177 SPI Master, Frame Slave Connection ...................... 177 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 176 SPI Master/Slave Connection (Standard Mode)............................................... 176 SPI Slave, Frame Master Connection ...................... 177 SPI Slave, Frame Slave Connection ........................ 177 SPIx Module (Enhanced Mode)................................ 171 SPIx Module (Standard Mode) ................................. 170 System Clock Diagram ............................................. 109 Triple Comparator Module........................................ 259 UART (Simplified)..................................................... 187 USB OTG Interrupt Funnel ....................................... 201 USB OTG Module..................................................... 196 USB PLL................................................................... 116 USB Voltage Generation and Connections .............. 200 Watchdog Timer (WDT)............................................ 277 B Block Diagram CRC Shifter Details................................................... 245 Block Diagrams 10-Bit High-Speed A/D Converter............................. 250 16-Bit Asynchronous Timer3 and Timer5 ................. 151 16-Bit Synchronous Timer2 and Timer4 ................... 151 16-Bit Timer1 Module................................................ 147 32-Bit Timer2/3 and Timer4/5 ................................... 150 Accessing Program Space Using Table Operations ................................................ 53 Addressable PMP Example ...................................... 232 Addressing for Table Registers................................... 55 BDT Mapping for Endpoint Buffering Modes ............ 197 CALL Stack Frame...................................................... 51 Comparator Voltage Reference ................................ 263 CPU Programmer’s Model .......................................... 27 CRC Generator Configured for Polynomial............... 246 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 265 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 266 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 266 Data Access From Program Space Address Generation ............................................ 52 I2C Module ................................................................ 180 Individual Comparator Configuration ........................ 260 Input Capture ............................................................ 155 LCD Control .............................................................. 234 Legacy PMP Example............................................... 232 On-Chip Regulator Connections ............................... 275 Output Compare (16-Bit Mode)................................. 160 Output Compare (Double-Buffered 16-Bit PWM Mode) ........................................... 162 PCI24FJ256GB110 Family (General) ......................... 14 PIC24F CPU Core ...................................................... 26 PMP 8-Bit Multiplexed Address and Data Application................................................ 234 PMP EEPROM (8-Bit Data) ...................................... 234 PMP Master Mode, Demultiplexed Addressing ........................................................ 232 PMP Master Mode, Fully Multiplexed Addressing ........................................................ 233 PMP Master Mode, Partially Multiplexed Addressing ........................................................ 233 PMP Module Overview ............................................. 225 PMP Multiplexed Addressing .................................... 233 PMP Parallel EEPROM (16-Bit Data) ....................... 234 PMP Partially Multiplexed Addressing ...................... 233 C C Compilers MPLAB C18.............................................................. 282 MPLAB C30.............................................................. 282 Charge Time Measurement Unit. See CTMU. Code Examples Basic Clock Switching Example ............................... 115 Configuring UART1 Input and Output Functions (PPS) ............................................... 127 Erasing a Program Memory Block.............................. 58 I/O Port Read/Write .................................................. 122 Initiating a Programming Sequence ........................... 59 Loading the Write Buffers ........................................... 59 Single-Word Flash Programming ............................... 60 Code Protection ................................................................ 277 Code Segment Protection ........................................ 277 Configuration Options....................................... 278 Configuration Protection ........................................... 278 Configuration Bits ............................................................. 269 Core Features....................................................................... 9 CPU Arithmetic Logic Unit (ALU) ........................................ 29 Control Registers........................................................ 28 Core Registers............................................................ 27 Programmer’s Model .................................................. 25 CRC Setup Example ......................................................... 245 User Interface ........................................................... 246 CTMU Measuring Capacitance............................................ 265 Measuring Time........................................................ 266 Pulse Delay and Generation..................................... 266 Customer Change Notification Service............................. 323 Customer Notification Service .......................................... 323 Customer Support............................................................. 323 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 319 PIC24FJ256GB110 FAMILY D Data Memory Address Space............................................................ 33 Memory Map ............................................................... 33 Near Data Space ........................................................ 34 SFR Space.................................................................. 34 Software Stack ............................................................ 51 Space Organization .................................................... 34 DC Characteristics I/O Pin Input Specifications ....................................... 299 I/O Pin Output Specifications .................................... 300 Program Memory ...................................................... 300 Development Support ....................................................... 281 Device Features (Summary) 100-Pin........................................................................ 13 64-Pin.......................................................................... 11 80-Pin.......................................................................... 12 Doze Mode........................................................................ 120 I2C Clock Rates .............................................................. 181 Reserved Addresses ................................................ 181 Setting Baud Rate as Bus Master............................. 181 Slave Address Masking ............................................ 181 Idle Mode .......................................................................... 120 Input Capture 32-Bit Mode .............................................................. 156 Synchronous and Trigger Modes.............................. 155 Input Capture with Dedicated Timers ............................... 155 Instruction Set Overview................................................................... 287 Summary .................................................................. 285 Instruction-Based Power-Saving Modes................... 119, 120 Inter-Integrated Circuit. See I2C. ...................................... 179 Internet Address ............................................................... 323 Interrupt Vector Table (IVT) ................................................ 67 Interrupts and Reset Sequence .................................................. 67 Control and Status Registers...................................... 70 Implemented Vectors.................................................. 69 Setup and Service Procedures ................................. 108 Trap Vectors ............................................................... 68 Vector Table ............................................................... 68 IrDA Support ..................................................................... 189 E Electrical Characteristics A/D Specifications ..................................................... 305 Absolute Maximum Ratings ...................................... 293 Current Specifications ....................................... 296–298 External Clock ........................................................... 302 Load Conditions and Requirements for Specifications.................................................... 301 PLL Clock Specifications .......................................... 303 Thermal Conditions ................................................... 294 V/F Graph ................................................................. 294 Voltage Regulator Specifications .............................. 300 Voltage Specifications............................................... 295 Electrical Characteristics Internal RC Accuracy ................................................ 303 ENVREG Pin..................................................................... 275 Equations A/D Conversion Clock Period ................................... 257 Baud Rate Reload Calculation .................................. 181 Calculating the PWM Period ..................................... 163 Calculation for Maximum PWM Resolution............... 163 Relationship Between Device and SPI Clock Speed............................................... 178 RTCC Calibration ...................................................... 243 UART Baud Rate with BRGH = 0 ............................. 188 Errata .................................................................................... 7 J JTAG Interface.................................................................. 279 M Microchip Internet Web Site.............................................. 323 MPLAB ASM30 Assembler, Linker, Librarian ................... 282 MPLAB ICD 2 In-Circuit Debugger ................................... 283 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................... 283 MPLAB Integrated Development Environment Software .............................................. 281 MPLAB PM3 Device Programmer .................................... 283 MPLAB REAL ICE In-Circuit Emulator System ................ 283 MPLINK Object Linker/MPLIB Object Librarian ................ 282 N Near Data Space ................................................................ 34 O Oscillator Configuration Clock Selection ......................................................... 110 Clock Switching ........................................................ 114 Sequence ......................................................... 115 Initial Configuration on POR ..................................... 110 USB Operation ......................................................... 116 Special Considerations..................................... 117 Output Compare 32-Bit Mode .............................................................. 159 Synchronous and Trigger Modes.............................. 159 Output Compare with Dedicated Timers........................... 159 F Flash Configuration Words.................................. 32, 269–273 Flash Program Memory....................................................... 55 and Table Instructions................................................. 55 Enhanced ICSP Operation.......................................... 56 JTAG Operation .......................................................... 56 Programming Algorithm .............................................. 58 RTSP Operation.......................................................... 56 Single-Word Programming.......................................... 60 I I/O Ports Analog Port Pins Configuration ................................. 122 Input Change Notification.......................................... 122 Open-Drain Configuration ......................................... 122 Parallel (PIO) ............................................................ 121 Peripheral Pin Select ................................................ 123 Pull-ups and Pull-downs ........................................... 122 P Packaging ......................................................................... 307 Details....................................................................... 308 Marking ..................................................................... 307 Parallel Master Port. See PMP. ........................................ 225 Peripheral Enable bits....................................................... 120 Peripheral Module Disable bits ......................................... 120 DS39897B-page 320 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Peripheral Pin Select (PPS) .............................................. 123 Available Peripherals and Pins ................................. 123 Configuration Control ................................................ 126 Considerations for Use ............................................. 127 Input Mapping ........................................................... 124 Mapping Exceptions.................................................. 126 Output Mapping ........................................................ 125 Peripheral Priority ..................................................... 123 Registers........................................................... 128–146 PICSTART Plus Development Programmer ..................... 284 Pinout Descriptions ....................................................... 15–23 POR and On-Chip Voltage Regulator................................ 275 Power-Saving Clock Frequency and Clock Switching...................... 119 Power-Saving Features .................................................... 119 Power-up Requirements ................................................... 276 Product Identification System ........................................... 325 Program Memory Access Using Table Instructions................................. 53 Address Construction.................................................. 51 Address Space............................................................ 31 Flash Configuration Words ......................................... 32 Memory Maps ............................................................. 31 Organization................................................................ 32 Program Space Visibility ............................................. 54 Program Space Visibility (PSV) .......................................... 54 Pulse-Width Modulation (PWM) Mode .............................. 162 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 163 Registers AD1CHS0 (A/D Input Select).................................... 254 AD1CON1 (A/D Control 1)........................................ 251 AD1CON2 (A/D Control 2)........................................ 252 AD1CON3 (A/D Control 3)........................................ 253 AD1CSSH (A/D Input Scan Select, High)................. 256 AD1CSSL (A/D Input Scan Select, Low) .................. 256 AD1PCFGH (A/D Port Configuration, High) ............. 255 AD1PCFGL (A/D Port Configuration, Low)............... 255 ALCFGRPT (Alarm Configuration) ........................... 239 ALMINSEC (Alarm Minutes and Seconds Value) ................................................ 243 ALMTHDY (Alarm Month and Day Value) ................ 242 ALWDHR (Alarm Weekday and Hours Value) ......... 242 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ...................... 199 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode) ...................... 198 CLKDIV (Clock Divider) ............................................ 113 CMSTAT (Comparator Status) ................................. 262 CMxCON (Comparator x Control) ............................ 261 CORCON (CPU Control) ............................................ 29 CORCON (CPU Core Control) ................................... 71 CRCCON (CRC Control) .......................................... 247 CRCXOR (CRC XOR Polynomial) ........................... 248 CTMUCON (CTMU Control)..................................... 267 CTMUICON (CTMU Current Control) ....................... 268 CVRCON (Comparator Voltage Reference Control) ........................................... 264 CW1 (Flash Configuration Word 1) .......................... 270 CW2 (Flash Configuration Word 2) .......................... 272 CW3 (Flash Configuration Word 3) .......................... 273 DEVID (Device ID).................................................... 274 DEVREV (Device Revision)...................................... 274 I2CxCON (I2Cx Control)........................................... 182 I2CxMSK (I2C Slave Mode Address Mask).............. 186 I2CxSTAT (I2Cx Status) ........................................... 184 ICxCON1 (Input Capture x Control 1)....................... 157 ICxCON2 (Input Capture x Control 2)....................... 158 IECn (Interrupt Enable Control 0-5)...................... 80–86 IFSn (Interrupt Flag Status 0-5)............................ 74–79 INTCON1 (Interrupt Control 1) ................................... 72 INTCON2 (Interrupt Control 2) ................................... 73 IPCn (Interrupt Priority Control 0-23).................. 87–107 MINSEC (RTCC Minutes and Seconds Value) ................................................ 241 MTHDY (RTCC Month and Day Value).................... 240 NVMCON (Flash Memory Control)............................. 57 OCxCON1 (Output Compare x Control 1) ................ 165 OCxCON2 (Output Compare x Control 2) ................ 166 OSCCON (Oscillator Control)................................... 111 OSCTUN (FRC Oscillator Tune) .............................. 114 PADCFG1 (Pad Configuration Control).................... 231 PADCFG1 (Pad Configuration) ................................ 238 PMADDR (PMP Address)......................................... 229 PMAEN (PMP Enable) ............................................. 229 PMMODE (Parallel Port Mode) ................................ 228 PMPCON (PMP Control) .......................................... 226 PMSTAT (PMP Status)............................................. 230 RCFGCAL (RTCC Calibration and Configuration) ................................................... 237 RCON (Reset Control)................................................ 62 REFOCON (Reference Oscillator Control) ............... 118 RPINRn (PPS Input Mapping 0-29).................. 128–138 RPORn (PPS Output Mapping 0-15)................ 138–146 R Reader Response ............................................................. 324 Reference Clock Output.................................................... 117 Register Maps A/D Converter ............................................................. 45 Comparators ............................................................... 48 CPU Core.................................................................... 35 CRC ............................................................................ 48 CTMU.......................................................................... 45 I2C............................................................................... 41 ICN.............................................................................. 36 Input Capture .............................................................. 39 Interrupt Controller ...................................................... 37 NVM ............................................................................ 50 Output Compare ......................................................... 40 Pad Configuration ....................................................... 44 Parallel Master/Slave Port .......................................... 47 Peripheral Pin Select .................................................. 49 PMD ............................................................................ 50 PORTA........................................................................ 43 PORTB........................................................................ 43 PORTC ....................................................................... 43 PORTD ....................................................................... 43 PORTE........................................................................ 44 PORTF........................................................................ 44 PORTG ....................................................................... 44 RTCC .......................................................................... 48 SPI .............................................................................. 42 System ........................................................................ 50 Timers ......................................................................... 38 UART .......................................................................... 42 USB OTG.................................................................... 46 © 2008 Microchip Technology Inc. Preliminary DS39897B-page 321 PIC24FJ256GB110 FAMILY SPIxCON1 (SPIx Control 1) ...................................... 174 SPIxCON2 (SPIx Control 2) ...................................... 175 SPIxSTAT (SPIx Status) ........................................... 172 SR (ALU STATUS) ............................................... 28, 71 T1CON (Timer1 Control)........................................... 148 TxCON (Timer2 and Timer4 Control)........................ 152 TyCON (Timer3 and Timer5 Control)........................ 153 U1ADDR (USB Address) .......................................... 212 U1CNFG1 (USB Configuration 1) ............................. 213 U1CNFG2 (USB Configuration 2) ............................. 214 U1CON (USB Control, Device Mode) ....................... 210 U1CON (USB Control, Host Mode)........................... 211 U1EIE (USB Error Interrupt Enable) ......................... 221 U1EIR (USB Error Interrupt Status) .......................... 220 U1EPn (USB Endpoint n Control) ............................. 222 U1IE (USB Interrupt Enable)..................................... 219 U1IR (USB Interrupt Status, Device Mode) .............. 217 U1IR (USB Interrupt Status, Host Mode) .................. 218 U1OTGCON (USB OTG Control) ............................. 207 U1OTGIE (USB OTG Interrupt Enable) .................... 216 U1OTGIR (USB OTG Interrupt Status) ..................... 215 U1OTGSTAT (USB OTG Status).............................. 206 U1PWMCON USB (VBUS PWM Generator Control) ............................................ 223 U1PWRC (USB Power Control) ................................ 208 U1SOF (USB OTG Start-Of-Token Threshold)......................................................... 213 U1STAT (USB Status) .............................................. 209 U1TOK (USB Token) ................................................ 212 UxMODE (UARTx Mode) .......................................... 190 UxSTA (UARTx Status and Control) ......................... 192 WKDYHR (RTCC Weekday and Hours Value) ..................................................... 241 YEAR (RTCC Year Value) ........................................ 240 Resets BOR (Brown-out Reset) .............................................. 61 Clock Source Selection ............................................... 63 CM (Configuration Mismatch Reset) ........................... 61 Delay Times ................................................................ 64 Device Times .............................................................. 63 IOPUWR (Illegal Opcode Reset) ................................ 61 MCLR (Pin Reset) ....................................................... 61 POR (Power-on Reset) ............................................... 61 RCON Flags Operation ............................................... 63 SFR States.................................................................. 65 SWR (RESET Instruction)........................................... 61 TRAPR (Trap Conflict Reset)...................................... 61 UWR (Uninitialized W Register Reset)........................ 61 WDT (Watchdog Timer Reset).................................... 61 Revision History ................................................................ 317 RTCC Alarm Configuration .................................................. 244 Calibration ................................................................. 243 Register Mapping ...................................................... 236 S Selective Peripheral Power Control .................................. 120 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 34 Sleep Mode....................................................................... 119 Software Simulator (MPLAB SIM) .................................... 282 Software Stack.................................................................... 51 Special Features................................................................. 10 SPI T Timer1............................................................................... 147 Timer2/3 and Timer4/5 ..................................................... 149 Timing Diagrams CLKO and I/O Timing ............................................... 304 External Clock........................................................... 302 U UART ................................................................................ 187 Baud Rate Generator (BRG) .................................... 188 Operation of UxCTS and UxRTS Pins...................... 189 Receiving .................................................................. 189 Transmitting 8-Bit Data Mode................................................ 189 9-Bit Data Mode................................................ 189 Break and Sync Sequence ............................... 189 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 10 USB OTG Buffer Descriptors and BDT...................................... 197 Device Mode Operation ............................................ 202 DMA Interface........................................................... 198 Host Mode Operation................................................ 202 Interrupts .................................................................. 201 OTG Operation ......................................................... 204 Registers .......................................................... 205–223 VBUS Voltage Generation ......................................... 200 V VDDCORE/VCAP Pin ........................................................... 275 Voltage Regulator (On-Chip) ............................................ 275 and BOR ................................................................... 276 Standby Mode .......................................................... 276 Tracking Mode .......................................................... 275 W Watchdog Timer (WDT).................................................... 276 Control Register........................................................ 277 Windowed Operation ................................................ 277 WWW Address ................................................................. 323 WWW, On-Line Support ....................................................... 7 DS39897B-page 322 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. © 2008 Microchip Technology Inc. Preliminary DS39897B-page 323 PIC24FJ256GB110 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39897B FAX: (______) _________ - _________ Device: PIC24FJ256GB110 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39897B-page 324 Preliminary © 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB1 10 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern b) Examples: a) PIC24FJ64GB106-I/PT: PIC24F device with USB On-The-Go, 64-Kbyte program memory, 64-pin, Industrial temp.,TQFP package. PIC24FJ256GB110-I/PT: PIC24F device with USB On-The-Go, 256-Kbyte program memory, 100-pin, Industrial temp.,TQFP package. Architecture Flash Memory Family Product Group 24 FJ = 16-bit modified Harvard without DSP = Flash program memory GB1 = General purpose microcontrollers with USB On-The-Go 06 08 10 I PF PT = 64-pin = 80-pin = 100-pin = -40°C to +85°C (Industrial) = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack) = 64-lead, 80-lead, 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) Pin Count Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample © 2008 Microchip Technology Inc. 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