PIC24FJ64GB004

PIC24FJ64GB004 Family Data Sheet 28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology  2010 Microchip Technology Inc. DS39940D Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-439-1 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39940D-page 2  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 28/44-Pin, 16-Bit, Flash Microcontrollers with USB On-The-Go (OTG) and nanoWatt XLP Technology Universal Serial Bus Features: • USB v2.0 On-The-Go (OTG) Compliant • Dual Role Capable – can act as either Host or Peripheral • Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode • Full-Speed USB Operation in Device mode • High-Precision PLL for USB • 0.25% Accuracy using Internal Oscillator – No External Crystal Required • Internal Voltage Boost Assist for USB Bus Voltage Generation • Interface for Off-Chip Charge Pump for USB Bus Voltage Generation • Supports up to 32 Endpoints (16 bidirectional): - USB module can use any RAM location on the device as USB endpoint buffers • On-Chip USB Transceiver • Interface for Off-Chip USB Transceiver • Supports Control, Interrupt, Isochronous and Bulk Transfers • On-Chip Pull-up and Pull-Down Resistors Power Management Modes: • Selectable Power Management modes with nanoWatt XLP Technology for Extremely Low Power: - Deep Sleep mode allows near total power-down (20 nA typical and 500 nA with RTCC or WDT), along with the ability to wake-up on external triggers or self-wake on programmable WDT or RTCC alarm - Extreme low-power DSBOR for Deep Sleep, LPBOR for all other modes - Sleep mode shuts down peripherals and core for substantial power reduction, fast wake-up - Idle mode shuts down the CPU and peripherals for significant power reduction, down to 4.5 A typical - Doze mode enables CPU clock to run slower than peripherals - Alternate Clock modes allow on-the-fly switching to a lower clock speed for selective power reduction during Run mode down to 15 A typical Special Microcontroller Features: • • • • • Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) High-Current Sink/Source (18 mA/18 mA) on All I/O Pins Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip FRC oscillator On-Chip 2.5V Regulator Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) Two Flexible Watchdog Timers (WDT) for Reliable Operation: - Standard programmable WDT for normal operation - Extreme low-power WDT with programmable period of 2 ms to 26 days for Deep Sleep mode In-Circuit Serial Programming™ (ICSP™) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan Support High-Performance CPU: • Modified Harvard Architecture • Up to 16 MIPS Operation @ 32 MHz • 8 MHz Internal Oscillator with 0.25% Typical Accuracy: - 96 MHz PLL - Multiple divide options • 17-Bit x 17-Bit Single-Cycle Hardware Fractional/integer Multiplier • 32-Bit by 16-Bit Hardware Divider • 16 x 16-Bit Working Register Array • C Compiler Optimized Instruction Set Architecture: - 76 base instructions - Flexible addressing modes • Linear Program Memory Addressing up to 12 Mbytes • Linear Data Memory Addressing up to 64 Kbytes • Two Address Generation Units for Separate Read and Write Addressing of Data Memory • • • • • • Program Memory (Bytes) Remappable Peripherals Compare/PWM Output Comparators 10-Bit A/D (ch) Remappable Pins UART w/ IrDA® Capture Input USB OTG Y Y Y Y PMP/PSP SRAM (Bytes) CTMU Y Y Y Y RTCC Y Y Y Y I2C™ 2 2 2 2 Timers 16-Bit 32GB002 64GB002 32GB004 64GB004 28 28 44 44 32K 64K 32K 64K 8K 8K 8K 8K 15 15 25 25 5 5 5 5 5 5 5 5 5 5 5 5 2 2 2 2 SPI 2 2 2 2 PIC24FJ Device Pins 9 9 13 13 3 3 3 3 Y Y Y Y  2010 Microchip Technology Inc. DS39940D-page 3 PIC24FJ64GB004 FAMILY Analog Features: • 10-Bit, up to 13-Channel Analog-to-Digital (A/D) Converter: - 500 ksps conversion rate - Conversion available during Sleep and Idle • Three Analog Comparators with Programmable Input/Output Configuration • Charge Time Measurement Unit (CTMU): - Supports capacitive touch sensing for touch screens and capacitive switches - Provides high-resolution time measurement and simple temperature sensing • Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions - Functions even in Deep Sleep mode • Two 3-Wire/4-Wire SPI modules (support 4 Frame modes) with 8-Level FIFO Buffer • Two I2C™ modules support Multi-Master/Slave mode and 7-Bit/10-Bit Addressing • Two UART modules: - Supports RS-485, RS-232 and LIN/J2602 - On-chip hardware encoder/decoder for IrDA® - Auto-wake-up on Start bit - Auto-Baud Detect (ABD) - 4-level deep FIFO buffer • Five 16-Bit Timers/Counters with Programmable Prescaler • Five 16-Bit Capture Inputs, each with a Dedicated Time Base • Five 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base • Programmable, 32-Bit Cyclic Redundancy Check (CRC) Generator • Configurable Open-Drain Outputs on Digital I/O Pins • Up to 3 External Interrupt Sources Peripheral Features: • Peripheral Pin Select: - Allows independent I/O mapping of many peripherals - Up to 25 available pins (44-pin devices) - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes • 8-Bit Parallel Master Port (PMP/PSP): - Up to 16-bit multiplexed addressing, with up to 11 dedicated address pins on 44-pin devices - Programmable polarity on control lines - Supports legacy Parallel Slave Port Pin Diagrams 28-Pin SPDIP, SOIC, SSOP(1) MCLR PGED3/AN0/C3INC/VREF+/ASDA1(2)/RP5/PMD7/CTED1/VBUSVLD/VCMPST1/CN2/RA0 PGEC3/AN1/C3IND/VREF-/ASCL1(2)/RP6/PMD6/CTED2/SESSVLD/VCMPST2/CN3/RA1 PGED1/AN2/C2INB/DPH/RP0/PMD0/CN4/RB0 PGEC1/AN3/C2INA/DMH/RP1/PMD1/CN5/RB1 AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2 AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3 VSS OSCI/CLKI/C1IND/PMCS1/CN30/RA2 OSCO/CLKO/PMA0/CN29/RA3 SOSCI/C2IND/RP4/PMBE/CN1/RB4 SOSCO/SCLKI/T1CK/C2INC/PMA1/CN0/RA4 VDD TMS/USBID/CN27/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD VSS AN9/C3INA/VBUSCHG/RP15/VBUSST/CN11/RB15 AN10/C3INB/CVREF/VCPCON/VBUSON/RP14/CN12/RB14 AN11/C1INC/RP13/PMRD/REFO/SESSEND/CN13/RB13 VUSB PGEC2/D-/VMIO/RP11/CN15/RB11 PGED2/D+/VPIO/RP10/CN16/RB10 VCAP/VDDCORE DISVREG TDO/SDA1/RP9/PMD3/RCV/CN21/RB9 TCK/USBOEN/SCL1/RP8/PMD4/CN22/RB8 TDI/RP7/PMD5/INT0/CN23/RB7 VBUS PIC24FJXXGB002 Legend: Note 1: 2: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. DS39940D-page 4  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY Pin Diagrams 28-Pin QFN(1,3) PGEC3/AN1/C3IND/VREF-/ASCL1(2)/RP6/PMD6/CTED2/SESSVLD/VCMPST2/CN3/RA1 PGED3/AN0/C3INC/VREF+/ASDA1(2)/RP5/PMD7/CTED1/VBUSVLD/VCMPST1/CN2/RA0 MCLR PGED1/AN2/C2INB/DPH/RP0/PMD0/CN4/RB0 PGEC1/AN3/C2INA/DMH/RP1/PMD1/CN5/RB1 AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2 AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3 VSS OSCI/CLKI/C1IND/PMCS1/CN30/RA2 OSCO/CLKO/PMA0/CN29/RA3 28 27 26 25 24 23 22 1 21 2 20 3 19 4 PIC24FJXXGB00218 5 17 6 16 7 15 8 9 10 11 12 13 14 SOSCO/SCLKI/T1CK/C2INC/PMA1/CN0/RA4 VDD TMS/USBID//CN27/RB5 VBUS SOSCI/C2IND/RP4/PMBE/CN1/RB4 TDI/RP7/PMD5/INT0/CN23/RB7 TCK/USBOEN/SCL1/RP8/PMD4/CN22/RB8 VDD VSS AN9/C3INA/VBUSCHG/RP15/VBUSST/CN11/RB15 AN10/C3INB/CVREF/VCPCON/VBUSON/RP14/CN12/RB14 AN11/C1INC/RP13/PMRD/REFO/SESSEND/CN13/RB13 VUSB PGEC2/D-/VMIO/RP11/CN15/RB11 PGED2/D+/VPIO/RP10/CN16/RB10 VCAP/VDDCORE DISVREG TDO/SDA1/RP9/PMD3/RCV/CN21/RB9 Legend: Note 1: 2: 3: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. The back pad on QFN devices should be connected to VSS.  2010 Microchip Technology Inc. DS39940D-page 5 PIC24FJ64GB004 FAMILY Pin Diagrams 44-PIN TQFP, USBOEN/SCL1/RP8/PMD4/CN22/RB8 RP7/PMD5/INT0/CN23/RB7 VBUS CN27/USBID/RB5 VDD VSS RP21/PMA3/CN26/RC5 RP20/PMA4/CN25/RC4 AN12/RP19/PMBE/CN28/RC3 TDI/PMA9/RA9 SOSCO/SCLKI/T1CK/C2INC/CN0/RA4 44 43 42 41 40 39 38 37 36 35 34 44-Pin QFN(1,3) Legend: Note 1: 2: 3: RPn represents remappable peripheral pins. Gray shading indicates 5.5V tolerant input pins. Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set. The back pad on QFN devices should be connected to VSS. TMS/PMA10/RA10 TCK/PMA7/RA7 AN10/C3INB/CVREF/VCPCON/VBUSON/RP14/CN12/RB14 AN9/C3INA/VBUSCHG/RP15/VBUSST/CN11/RB15 AVSS AVDD MCLR PGED3/AN0/C3INC/VREF+/ASDA1(2)/RP5/PMD7/CTED1/VBUSVLD/VCMPST1/CN2/RA0 PGEC3/AN1/C3IND/VREF-/ASCL1(2)/RP6/PMD6/CTED2/SESSVLD/VCMPST2/CN3/RA1 PGED1/AN2/C2INB/DPH/RP0/PMD0/CN4/RB0 PGEC1/AN3/C2INA/DMH/RP1/PMD1/CN5/RB1 12 13 14 15 16 17 18 19 20 21 22 SDA1/RP9/PMD3/RCV/CN21/RB9 RP22/PMA1/CN18/RC6 RP23/PMA0/CN17/RC7 RP24/PMA5/CN20/RC8 RP25/PMA6/CN19/RC9 DISVREG VCAP/VDDCORE PGED2/D+/VPIO/RP10/CN16/RB10 PGEC2/D-/VMIO/RP11/CN15/RB11 VUSB AN11/C1INC/RP13/REFO/PMRD/SESSEND/CN13/RB13 1 2 3 4 5 6 7 8 9 10 11 PIC24FJXXGB004 33 32 31 30 29 28 27 26 25 24 23 SOSCI/C2IND/RP4/CN1/RB4 TDO/PMA8/RA8 OSCO/CLKO/CN29/RA3 OSCI/CLKI/C1IND/PMCS1/CN30/RA2 VSS VDD AN8/RP18/PMA2/CN10/RC2 AN7/RP17/CN9/RC1 AN6/RP16/CN8/RC0 AN5/C1INA/DMLN/RTCC/SCL2/RP3/PMWR/CN7/RB3 AN4/C1INB/DPLN/SDA2/RP2/PMD2/CN6/RB2 DS39940D-page 6  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 19 3.0 CPU ........................................................................................................................................................................................... 25 4.0 Memory Organization ................................................................................................................................................................. 31 5.0 Flash Program Memory.............................................................................................................................................................. 55 6.0 Resets ........................................................................................................................................................................................ 63 7.0 Interrupt Controller ..................................................................................................................................................................... 69 8.0 Oscillator Configuration ............................................................................................................................................................ 107 9.0 Power-Saving Features............................................................................................................................................................ 117 10.0 I/O Ports ................................................................................................................................................................................... 127 11.0 Timer1 ...................................................................................................................................................................................... 149 12.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 151 13.0 Input Capture with Dedicated Timers ....................................................................................................................................... 157 14.0 Output Compare with Dedicated Timers .................................................................................................................................. 161 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 171 16.0 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 181 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 189 18.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 197 19.0 Parallel Master Port (PMP)....................................................................................................................................................... 231 20.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 241 21.0 32-Bit Programmable Cyclic Redundancy Check (CRC) Generator ........................................................................................ 253 22.0 10-Bit High-Speed A/D Converter ............................................................................................................................................ 259 23.0 Triple Comparator Module........................................................................................................................................................ 269 24.0 Comparator Voltage Reference................................................................................................................................................ 273 25.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 275 26.0 Special Features ...................................................................................................................................................................... 279 27.0 Development Support............................................................................................................................................................... 293 28.0 Instruction Set Summary .......................................................................................................................................................... 297 29.0 Electrical Characteristics .......................................................................................................................................................... 305 30.0 Packaging Information.............................................................................................................................................................. 327 Appendix A: Revision History............................................................................................................................................................. 341 The Microchip Web Site ..................................................................................................................................................................... 349 Customer Change Notification Service .............................................................................................................................................. 349 Customer Support .............................................................................................................................................................................. 349 Reader Response .............................................................................................................................................................................. 350 Product Identification System ............................................................................................................................................................ 351  2010 Microchip Technology Inc. DS39940D-page 7 PIC24FJ64GB004 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS39940D-page 8  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: • PIC24FJ32GB002 • PIC24FJ64GB002 • PIC24FJ32GB004 • PIC24FJ64GB004 • Instruction-Based Power-Saving Modes: There are three instruction-based power-saving modes: - Idle Mode – The core is shut down while leaving the peripherals active. - Sleep Mode – The core and peripherals that require the system clock are shut down, leaving the peripherals active that use their own clock or the clock from other devices. - Deep Sleep Mode – The core, peripherals (except RTCC and DSWDT), Flash and SRAM are shut down for optimal current savings to extend battery life for portable applications. This family expands on the existing line of Microchip‘s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go (OTG). The PIC24FJ64GB004 family provides a new platform for high-performance USB applications which may need more than an 8-bit platform, but do not require the power of a digital signal processor. 1.1.3 OSCILLATOR OPTIONS AND FEATURES 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE All of the devices in the PIC24FJ64GB004 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes using crystals or ceramic resonators. • Two External Clock modes offering the option of a divide-by-2 clock output. • A Fast Internal RC Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. • A Phase Lock Loop (PLL) frequency multiplier available to the external oscillator modes and the FRC Oscillator, which allows clock speeds of up to 32 MHz. • A separate Low-Power Internal RC Oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip’s dsPIC® digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: • 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces • Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) • A 16-element working register array with built-in software stack support • A 17 x 17 hardware multiplier with support for integer math • Hardware support for 32 by 16-bit division • An instruction set that supports multiple addressing modes and is optimized for high-level languages, such as ‘C’ • Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ64GB004 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: • On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, Low-Power Internal RC Oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. • Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger device. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30 devices. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device.  2010 Microchip Technology Inc. DS39940D-page 9 PIC24FJ64GB004 FAMILY 1.2 USB On-The-Go The PIC24FJ64GB004 family of devices introduces USB On-The-Go functionality on a single chip to lower pin count Microchip devices. This module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. In addition to USB host functionality, PIC24FJ64GB004 family devices provide a true single chip USB solution, including an on-chip transceiver and a voltage boost generator for sourcing bus power during host operations. • Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 12 external address lines in Master modes. • Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for the use of the core application. 1.4 Details on Individual Family Members Devices in the PIC24FJ64GB004 family are available in 28-pin and 44-pin packages. The general block diagram for all devices is shown in Figure 1-1. The devices are differentiated from each other in several ways: • Flash Program Memory: - PIC24FJ32GB0 devices – 32 Kbytes - PIC24FJ64GB0 devices – 64 Kbytes • Available I/O Pins and Ports: - 28-pin devices – 19 pins on two ports - 44-pin devices – 33 pins on three ports • Available Interrupt-on-Change Notification (ICN) Inputs: - 28-pin devices – 19 - 44-pin devices – 29 • Available Remappable Pins: - 28-pin devices – 15 pins - 44-pin devices – 25 pins • Available PMP Address Pins: - 28-pin devices – 3 pins - 44-pin devices – 12 pins • Available A/D Input Channels: - 28-pin devices – 9 pins - 44-pin devices – 12 pins All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ64GB004 family devices, sorted by function, is shown in Table 1-2. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of this data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. 1.3 Other Special Features • Peripheral Pin Select: The Peripheral Pin Select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. • Communications: The PIC24FJ64GB004 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are two independent I2C™ modules that support both Master and Slave modes of operation. Devices also have, through the Peripheral Pin Select (PPS) feature, two independent UARTs with built-in IrDA® encoder/decoders and two SPI modules. • Analog Features: All members of the PIC24FJ64GB004 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. • CTMU Interface: This module provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS39940D-page 10  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GB004 FAMILY Features Operating Frequency Program Memory (bytes) Program Memory (instructions) Data Memory (bytes) Interrupt Sources (soft vectors/ NMI traps) I/O Ports Total I/O Pins Remappable Pins Timers: Total Number (16-bit) 32-Bit (from paired 16-bit timers) Input Capture Channels Output Compare/PWM Channels Input Change Notification Interrupt Serial Communications: UART SPI (3-wire/4-wire) I2C™ Parallel Communications (PMP/PSP) JTAG Boundary Scan 10-Bit Analog-to-Digital Module (input channels) Analog Comparators CTMU Interface Resets (and delays) 9 3 Yes POR, BOR, RESET Instruction, MCLR, WDT, Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations 28-Pin QFN, SOIC, SSOP and SPDIP Peripherals are accessible through remappable pins. 44-Pin QFN and TQFP 2(1) 2(1) 2 Yes Yes 13 19 5(1) 2 5(1) 5(1) 29 Ports A and B 19 15 32K 11,008 64K 22,016 8,192 45 (41/4) Ports A, B, C 33 25 PIC24FJ32GB002 PIC24FJ64GB002 PIC24FJ32GB004 PIC24FJ64GB004 DC – 32 MHz 32K 11,008 64K 22,016 Instruction Set Packages Note 1:  2010 Microchip Technology Inc. DS39940D-page 11 PIC24FJ64GB004 FAMILY FIGURE 1-1: PIC24FJ64GB004 FAMILY GENERAL BLOCK DIAGRAM Data Bus 16 8 PSV & Table Data Access Control Block 16 16 Data Latch 23 PCH PCL Program Counter Repeat Stack Control Control Logic Logic Data RAM Address Latch 16 16 Read AGU Write AGU PORTB (14 I/O) PORTA(1) (9 I/O) Interrupt Controller 23 Address Latch Program Memory Data Latch PORTC(1) (10 I/O) Address Bus 24 Inst Latch Inst Register Instruction Decode & Control OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference DISVREG Voltage Regulator Control Signals Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer BOR and LVD(2) Literal Data EA MUX 16 16 16 RP(1) RP0:RP25 Divide Support 17 x 17 Multiplier 16 x 16 W Reg Array REFO 16-Bit ALU 16 VDDCORE/VCAP VDD, VSS MCLR Timer1 Timer2/3(3) Timer4/5(3) RTCC 10-Bit ADC Comparators(3) USB OTG PMP/PSP PWM/OC 1-5(3) SPI 1/2(3) IC 1-5(3) Note 1: 2: 3: ICNs(1) I2C 1/2 UART 1/2(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-2 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39940D-page 12  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 2 3 4 5 6 7 — — — 26 25 24 — 3 2 — — 7 6 24 9 5 4 12 11 26 25 2 3 9 10 28-Pin QFN 27 28 1 2 3 4 — — — 23 22 21 — 28 27 — — 4 3 21 6 2 1 9 8 23 22 27 28 6 7 44-Pin QFN/TQFP 19 20 21 22 23 24 25 26 27 15 14 11 36 20 19 17 16 24 23 11 30 22 21 34 33 15 14 19 20 30 31 I/O Input Buffer Description AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 ASCL1 ASDA1 AVDD AVSS C1INA C1INB C1INC C1IND C2INA C2INB C2INC C2IND C3INA C3INB C3INC C3IND CLKI CLKO Legend: I I I I I I I I I I I I I I/O I/O P P I I I I I I I I I I I I I O ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA I2C I2C — — ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA ANA — A/D Analog Inputs. Alternate I2C1 Synchronous Serial Clock Input/Output. Alternate I2C1 Synchronous Serial Data Input/Output. Positive Supply for Analog modules. Ground Reference for Analog modules. Comparator 1 Input A. Comparator 1 Input B. Comparator 1 Input C. Comparator 1 Input D. Comparator 2 Input A. Comparator 2 Input B. Comparator 2 Input C. Comparator 2 Input D. Comparator 3 Input A. Comparator 3 Input B. Comparator 3 Input C. Comparator 3 Input D. Main Clock Input Connection. System Clock Output. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. DS39940D-page 13 PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 12 11 2 3 4 5 6 7 — — — 26 25 24 22 21 — — — — 18 17 16 — — 14 — 10 9 2 3 25 21 22 5 7 4 6 19 28-Pin QFN 9 8 27 28 1 2 3 4 — — — 23 22 21 19 18 — — — — 15 14 13 — — 11 — 7 6 27 28 22 18 19 2 4 1 3 16 44-Pin QFN/TQFP 34 33 19 20 21 22 23 24 25 26 27 15 14 11 9 8 3 2 5 4 1 44 43 37 38 41 36 31 30 19 20 14 8 9 22 24 21 23 6 I/O Input Buffer Description CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN15 CN16 CN17 CN18 CN19 CN20 CN21 CN22 CN23 CN25 CN26 CN27 CN28 CN29 CN30 CTED1 CTED2 CVREF D+ DDMH DMLN DPH DPLN DISVREG Legend: I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I I O I/O I/O O O O O I ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ANA ANA — — — — — — — ST Interrupt-on-Change Inputs. CTMU External Edge Input 1. CTMU External Edge Input 2. Comparator Voltage Reference Output. USB Differential Plus Line (internal transceiver). USB Differential Minus Line (internal transceiver). D- External Pull-up Control Output. D- External Pull-down Control Output. D+ External Pull-up Control Output. D+ External Pull-down Control Output. Voltage Regulator Disable. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39940D-page 14  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 16 1 9 10 5 4 22 21 3 2 10 12 — — — — — — — — — 9 11 4 5 6 18 17 16 3 2 24 7 28-Pin QFN 13 26 6 7 2 1 19 18 28 27 7 9 — — — — — — — — — 6 8 1 2 3 15 14 13 28 27 21 4 44-Pin QFN/TQFP 43 18 30 31 22 21 9 8 20 19 3 2 27 38 37 4 5 13 32 35 12 30 36 21 22 23 1 44 43 20 19 11 24 I/O Input Buffer Description INT0 MCLR OSCI OSCO PGEC1 PGED1 PGEC2 PGED2 PGEC3 PGED3 PMA0 PMA1 PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMCS1 PMBE PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR Legend: I I I O I/O I/O I/O I/O I/O I/O I/O I/O O O O O O O O O O I/O O I/O I/O I/O I/O I/O I/O I/O I/O O O ST ST ANA ANA ST ST ST ST ST ST ST ST — — — — — — — — — External Interrupt Input. Master Clear (device Reset) Input. This line is brought low to cause a Reset. Main Oscillator Input Connection. Main Oscillator Output Connection. In-Circuit Debugger/Emulator/ICSP™ Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. In-Circuit Debugger/Emulator/ICSP Programming Clock. In-Circuit Debugger/Emulator/ICSP Programming Data. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master modes). ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15. — Parallel Master Port Byte Enable Strobe. ST/TTL Parallel Master Port Data (Demultiplexed Master mode) or ST/TTL Address/Data (Multiplexed Master modes). ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL ST/TTL — — Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. DS39940D-page 15 PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 2 3 9 10 12 — — — — 4 5 6 7 11 14 16 17 18 21 22 24 25 26 — — — — — — — — — — 18 24 28-Pin QFN 27 28 6 7 9 — — — — 1 2 3 4 8 11 13 14 15 18 19 21 22 23 — — — — — — — — — — 15 21 44-Pin QFN/TQFP 19 20 30 31 34 13 32 35 12 21 22 23 24 33 41 43 44 1 8 9 11 14 15 25 26 27 36 37 38 2 3 4 5 1 11 I/O Input Buffer Description RA0 RA1 RA2 RA3 RA4 RA7 RA8 RA9 RA10 RB0 RB1 RB2 RB3 RB4 RB5 RB7 RB8 RB9 RB10 RB11 RB13 RB14 RB15 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 RCV REFO Legend: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — PORTA Digital I/O. PORTB Digital I/O. PORTC Digital I/O. USB Receive Input (from external transceiver). Reference Clock Output. TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39940D-page 16  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 4 5 6 7 11 2 3 16 17 18 21 22 24 25 26 — — — — — — — — — — 7 24 3 17 7 18 6 11 12 12 17 16 18 14 14 17 28-Pin QFN 1 2 3 4 8 27 28 13 14 15 18 19 21 22 23 — — — — — — — — — — 4 21 28 14 4 15 3 8 9 9 14 13 15 11 11 14 44-Pin QFN/TQFP 21 22 23 24 33 19 20 43 44 1 8 9 11 14 15 25 26 27 36 37 38 2 3 4 5 24 11 20 44 24 1 23 33 34 34 13 35 32 12 41 44 I/O Input Buffer Description RP0 RP1 RP2 RP3 RP4 RP5 RP6 RP7 RP8 RP9 RP10 RP11 RP13 RP14 RP15 RP16 RP17 RP18 RP19 RP20 RP21 RP22 RP23 RP24 RP25 RTCC SESSEND SESSVLD SCL1 SCL2 SDA1 SDA2 SOSCI SOSCO T1CK TCK TDI TDO TMS USBID USBOEN Legend: I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O I I I/O I/O I/O I/O I O I I I O I I O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST ST I2C I2C I2C IC ANA ANA ST ST ST — ST ST — 2 Remappable Peripheral (input or output). Real-Time Clock Alarm/Seconds Pulse Output. USB VBUS Session End Status Input. USB VBUS Session Valid Status Input. I2C1 Synchronous Serial Clock Input/Output. I2C2 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. I2C2 Data Input/Output. Secondary Oscillator/Timer1 Clock Input. Secondary Oscillator/Timer1 Clock Output. Timer1 Clock Input. JTAG Test Clock Input. JTAG Test Data Input. JTAG Test Data Output. JTAG Test Mode Select Input. USB OTG ID (OTG mode only). USB Output Enable Control (for external transceiver). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer  2010 Microchip Technology Inc. DS39940D-page 17 PIC24FJ64GB004 FAMILY TABLE 1-2: PIC24FJ64GB004 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 28-Pin SPDIP/ SOIC/SSOP 15 26 25 26 2 20 25 13, 28 20 22 21 3 2 8, 27 23 28-Pin QFN 12 23 22 23 27 17 22 10, 25 17 19 18 28 27 5, 24 20 44-Pin QFN/TQFP 42 15 14 15 19 7 14 28, 40 7 9 8 20 19 29, 39 10 I/O Input Buffer Description VBUS VBUSCHG VBUSON VBUSST VBUSVLD VCAP VCPCON VDD VDDCORE VMIO VPIO VREFVREF+ VSS VUSB Legend: P O O I I P O P P I/O I/O I I P P — — — ANA ST — — — — ST ST ANA ANA — — USB Voltage, Host mode (5V). USB External VBUS Control Output USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. USB VBUS Valid Status Input. External Filter Capacitor Connection (regulator enabled). USB OTG VBUS PWM/Charge Output. Positive Supply for Peripheral Digital Logic and I/O Pins. Positive Supply for Microcontroller Core Logic (regulator disabled). USB Differential Minus Input/Output (external transceiver). USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. A/D and Comparator Reference Voltage (high) Input. Ground Reference for Logic and I/O Pins. USB Voltage (3.3V). TTL = TTL input buffer ANA = Analog level input/output ST = Schmitt Trigger input buffer I2C™ = I2C/SMBus input buffer DS39940D-page 18  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS Basic Connection Requirements FIGURE 2-1: RECOMMENDED MINIMUM CONNECTIONS C2(2) VDD VDD VSS 2.1 Getting started with the PIC24FJ64GB004 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All VDD and VSS pins (see Section 2.2 “Power Supply Pins”) • All AVDD and AVSS pins, regardless of whether or not the analog device features are used (see Section 2.2 “Power Supply Pins”) • MCLR pin (see Section 2.3 “Master Clear (MCLR) Pin”) • ENVREG/DISVREG and VCAP/VDDCORE pins (PIC24FJ devices only) (see Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)”) These pins must also be connected if they are being used in the end application: • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSCI and OSCO pins when an external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for analog modules is implemented Note: The AVDD and AVSS pins must always be connected, regardless of whether any of the analog modules are being used. R1 R2 MCLR (1) (1) (EN/DIS)VREG VCAP/VDDCORE C1 PIC24FXXXX C6(2) VSS VDD VDD C7 C3(2) VSS AVDD AVSS VDD VSS C5(2) C4(2) Key (all values are recommendations): C1 through C6: 0.1 F, 20V ceramic C7: 10 F, 6.3V or greater, tantalum or ceramic R1: 10 kΩ R2: 100Ω to 470Ω Note 1: See Section 2.4 “Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE)” for explanation of ENVREG/DISVREG pin connections. The example shown is for a PIC24F device with five VDD/VSS and AVDD/AVSS pairs. Other devices may have more or less pairs; adjust the number of decoupling capacitors appropriately. 2: The minimum mandatory connections are shown in Figure 2-1.  2010 Microchip Technology Inc. DS39940D-page 19 PIC24FJ64GB004 FAMILY 2.2 2.2.1 Power Supply Pins DECOUPLING CAPACITORS 2.3 Master Clear (MCLR) Pin The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 F (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher. Ceramic capacitors are recommended. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is no greater than 0.25 inch (6 mm). • Handling high-frequency noise: If the board is experiencing high-frequency noise (upward of tens of MHz), add a second ceramic type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 F to 0.001 F. Place this second capacitor next to each primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible (e.g., 0.1 F in parallel with 0.001 F). • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB trace inductance. The MCLR pin provides two specific device functions: device Reset, and device programming and debugging. If programming and debugging are not required in the end application, a direct connection to VDD may be all that is required. The addition of other components, to help increase the application’s resistance to spurious Resets from voltage sags, may be beneficial. A typical configuration is shown in Figure 2-1. Other circuit designs may be implemented, depending on the application’s requirements. During programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R1 and C1 will need to be adjusted based on the application and PCB requirements. For example, it is recommended that the capacitor, C1, be isolated from the MCLR pin during programming and debugging operations by using a jumper (Figure 2-2). The jumper is replaced for normal run-time operations. Any components associated with the MCLR pin should be placed within 0.25 inch (6 mm) of the pin. FIGURE 2-2: VDD R1 EXAMPLE OF MCLR PIN CONNECTIONS R2 JP C1 MCLR PIC24FXXXX 2.2.2 TANK CAPACITORS Note 1: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 F to 47 F. R1  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R2  470 will limit any current flowing into MCLR from the external capacitor, C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS39940D-page 20  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 2.4 Voltage Regulator Pins (ENVREG/DISVREG and VCAP/VDDCORE) This section applies only to PIC24FJ devices with an on-chip voltage regulator. ESR () FIGURE 2-3: FREQUENCY vs. ESR PERFORMANCE FOR SUGGESTED VCAP Note: 10 1 The on-chip voltage regulator enable/disable pin (ENVREG or DISVREG, depending on the device family) must always be connected directly to either a supply voltage or to ground. The particular connection is determined by whether or not the regulator is to be used: • For ENVREG, tie to VDD to enable the regulator, or to ground to disable the regulator • For DISVREG, tie to ground to enable the regulator or to VDD to disable the regulator Refer to Section 26.2 “On-Chip Voltage Regulator” for details on connecting and using the on-chip regulator. When the regulator is enabled, a low-ESR (16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address __builtin_tblwtl(offset, 0x0000); // Set base address of erase block // with dummy latch write // Initialize NVMCON // // // // Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write necessary number of latches for(i=0; i < 2*NUM_INSTRUCTION_PER_ROW; i++) { __builtin_tblwtl(offset, progData[i++]); // Write to address low word __builtin_tblwth(offset, progData[i]); // Write to upper byte offset = offset + 2; // Increment address } EXAMPLE 5-5: DISI MOV MOV MOV MOV BSET NOP NOP BTSC BRA #5 INITIATING A PROGRAMMING SEQUENCE – ASSEMBLY LANGUAGE CODE ; Block all interrupts with priority >16; // Initialize PM Page Boundary SFR offset = progAddr & 0xFFFF; // Initialize lower word of address //Perform TBLWT instructions to write latches __builtin_tblwtl(offset, progDataL); __builtin_tblwth(offset, progDataH); asm(“DISI #5”); __builtin_write_NVM(); // // // // // // Write to address low word Write to upper byte Block interrupts with priority < 7 for next 5 instructions C30 function to perform unlock sequence and set WR  2010 Microchip Technology Inc. DS39940D-page 61 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 62  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 6.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 7. “Reset” (DS39712). Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: Refer to the specific peripheral or CPU section of this manual for register Reset states. The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: • • • • • • • • • POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 6-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this data sheet. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. A simplified block diagram of the Reset module is shown in Figure 6-1. FIGURE 6-1: RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect VDD Brown-out Reset BOR POR SYSRST Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register  2010 Microchip Technology Inc. Preliminary DS39940D-page 63 PIC24FJ64GB004 FAMILY REGISTER 6-1: R/W-0, HS TRAPR bit 15 R/W-0, HS EXTR bit 7 RCON: RESET CONTROL REGISTER(1) U-0 — U-0 — U-0 — R/CO-0, HS DPSLP R/W-0, HS CM R/W-0 PMSLP bit 8 R/W-1, HS POR bit 0 R/W-0, HS IOPUWR R/W-0, HS SWR R/W-0 SWDTEN(2) R/W-0, HS WDTO R/W-0, HS SLEEP R/W-0, HS IDLE R/W-1, HS BOR Legend: R = Readable bit -n = Value at POR bit 15 CO = Clearable Only bit W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13-11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as ‘0’ DPSLP: Deep Sleep Mode Flag bit 1 = Deep Sleep has occurred 0 = Deep Sleep has not occurred CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred PMSLP: Program Memory Power During Sleep bit 1 = Program memory bias voltage remains powered during Sleep 0 = Program memory bias voltage is powered down during Sleep and the voltage regulator enters Standby mode EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Note 1: 2: DS39940D-page 64 Preliminary  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 6-1: bit 1 RCON: RESET CONTROL REGISTER(1) (CONTINUED) bit 0 BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-on Reset has occurred 0 = A Power-on Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is ‘1’ (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. Note 1: 2: TABLE 6-1: RESET FLAG BIT OPERATION Setting Event Trap Conflict Event Illegal Opcode or Uninitialized W Register Access Configuration Mismatch Reset MCLR Reset RESET Instruction WDT Time-out PWRSAV #SLEEP Instruction PWRSAV #IDLE Instruction POR, BOR POR PWRSAV #SLEEP instruction with DSCON set Clearing Event POR POR POR POR POR PWRSAV Instruction, POR POR POR — — POR Flag Bit TRAPR (RCON) IOPUWR (RCON) CM (RCON) EXTR (RCON) SWR (RCON) WDTO (RCON) SLEEP (RCON) IDLE (RCON) BOR (RCON) POR (RCON) DPSLP (RCON) Note: All Reset flag bits may be set or cleared by the user software. 6.1 Clock Source Selection at Reset 6.2 Device Reset Times If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 6-2. If clock switching is disabled, the system clock source is always selected according to the oscillator configuration bits. Refer to Section 8.0 “Oscillator Configuration” for further details. The Reset times for various types of device Reset are summarized in Table 6-3. Note that the System Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. TABLE 6-2: OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant FNOSC Configuration bits (CW2) COSC Control bits (OSCCON) Reset Type POR BOR MCLR WDTO SWR  2010 Microchip Technology Inc. Preliminary DS39940D-page 65 PIC24FJ64GB004 FAMILY TABLE 6-3: Reset Type POR(6) EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL BOR EC FRC, FRCDIV LPRC ECPLL FRCPLL XT, HS, SOSC XTPLL, HSPLL All Others Note 1: 2: 3: 4: 5: 6: 7: Any Clock RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source SYSRST Delay TPOR + TRST + TPWRT TPOR + TRST + TPWRT TPOR + TRST + TPWRT TPOR + TRST + TPWRT TPOR + TRST + TPWRT TPOR+ TRST + TPWRT TPOR + TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST + TPWRT TRST System Clock Delay — TFRC TLPRC TLOCK TFRC + TLOCK TOST TOST + TLOCK — TFRC TLPRC TLOCK TFRC + TLOCK TOST TFRC + TLOCK — Notes 1, 2, 3 1, 2, 3, 4 1, 2, 3, 4 1, 2, 3, 5 1, 2, 3, 4, 5 1, 2, 3, 6 1, 2, 3, 5, 6 2, 3 2, 3, 4 2, 3, 4 2, 3, 5 2, 3, 4, 5 2, 3, 6 2, 3, 4, 5 2 TPOR = Power-on Reset delay. TRST = Internal State Reset time. TPWRT = 64 ms nominal if regulator is disabled (DISVREG tied to VDD). TFRC and TLPRC = RC Oscillator start-up times. TLOCK = PLL lock time. TOST = Oscillator Start-up Timer (OST). A 10-bit counter waits 1024 oscillator periods before releasing the oscillator clock to the system. If Two-Speed Start-up is enabled, regardless of the primary oscillator selected, the device starts with FRC, and in such cases, FRC start-up time is valid. For detailed operating frequency and timing specifications, see Section 29.0 “Electrical Characteristics”. Note: DS39940D-page 66 Preliminary  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 6.2.1 POR AND LONG OSCILLATOR START-UP TIMES 6.3 Special Function Register Reset States The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: • The oscillator circuit has not begun to oscillate. • The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). • The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2); see Table 6-2. The RCFGCAL and NVMCON registers are only affected by a POR. 6.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS 6.4 Deep Sleep BOR (DSBOR) If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC Oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine (TSR). Deep Sleep BOR is a very low-power BOR circuitry, used when the device is in Deep Sleep mode. Due to low-current consumption, accuracy may vary. The DSBOR trip point is around 2.0V. DSBOR is enabled by configuring CW4 = 1. DSBOR will re-arm the POR to ensure the device will reset if VDD drops below the POR threshold.  2010 Microchip Technology Inc. Preliminary DS39940D-page 67 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 68 Preliminary  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 7.0 Note: INTERRUPT CONTROLLER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 8. “Interrupts” (DS39707). 7.1.1 ALTERNATE INTERRUPT VECTOR TABLE The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: • • • • Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source • Fixed priority within a specified user priority level • Alternate Interrupt Vector Table (AIVT) for debug support • Fixed interrupt entry and return latencies The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 7-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 7.2 Reset Sequence 7.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 7-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). Interrupt vectors are prioritized in terms of their natural priority. This is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with Vector 0 will take priority over interrupts at any other vector address. PIC24FJ64GB004 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 7-1 and Table 7-2. A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction.  2010 Microchip Technology Inc. DS39940D-page 69 PIC24FJ64GB004 FAMILY FIGURE 7-1: PIC24F INTERRUPT VECTOR TABLE Reset – GOTO Instruction Reset – GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 — — — Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 — — — Interrupt Vector 116 Interrupt Vector 117 Start of Code 000000h 000002h 000004h 000014h Decreasing Natural Order Priority 00007Ch 00007Eh 000080h Interrupt Vector Table (IVT)(1) 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h 0001FEh 000200h Note 1: See Table 7-2 for the interrupt vector list. TABLE 7-1: 0 1 2 3 4 5 6 7 TRAP VECTOR DETAILS IVT Address 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h AIVT Address 000104h 000106h 000108h 00010Ah 00010Ch 00010Eh 000110h 000112h Reserved Oscillator Failure Address Error Stack Error Math Error Reserved Reserved Reserved  2010 Microchip Technology Inc. Vector Number Trap Source DS39940D-page 70 PIC24FJ64GB004 FAMILY TABLE 7-2: IMPLEMENTED INTERRUPT VECTORS Vector Number 13 18 67 77 0 20 29 17 16 50 49 1 5 37 38 39 19 72 2 6 25 26 41 45 62 9 10 32 33 3 7 8 27 28 65 11 12 66 30 31 86 IVT Address 00002Eh 000038h 00009Ah 0000AEh 000014h 00003Ch 00004Eh 000036h 000034h 000078h 000076h 000016h 00001Eh 00005Eh 000060h 000062h 00003Ah 0000A4h 000018h 000020h 000046h 000048h 000066h 00006Eh 000090h 000026h 000028h 000054h 000056h 00001Ah 000022h 000024h 00004Ah 00004Ch 000096h 00002Ah 00002Ch 000098h 000050h 000052h 0000C0h AIVT Address 00012Eh 000138h 00019Ah 0001AEh 000114h 00013Ch 00014Eh 000136h 000134h 000178h 000176h 000116h 00011Eh 00015Eh 000160h 000162h 00013Ah 0001A4h 000118h 000120h 000146h 000148h 000166h 00016Eh 000190h 000126h 000128h 000154h 000156h 00011Ah 000122h 000124h 00014Ah 00014Ch 000196h 00012Ah 00012Ch 000198h 000150h 000152h 0001C0h Interrupt Bit Locations Flag IFS0 IFS1 IFS4 IFS4 IFS0 IFS1 IFS1 IFS1 IFS1 IFS3 IFS3 IFS0 IFS0 IFS2 IFS2 IFS2 IFS1 IFS4 IFS0 IFS0 IFS1 IFS1 IFS2 IFS2 IFS3 IFS0 IFS0 IFS2 IFS2 IFS0 IFS0 IFS0 IFS1 IFS1 IFS4 IFS0 IFS0 IFS4 IFS1 IFS1 IFS5 Enable IEC0 IEC1 IEC4 IEC4 IEC0 IEC1 IEC1 IEC1 IEC1 IEC3 IEC3 IEC0 IEC0 IEC2 IEC2 IEC2 IEC1 IEC4 IEC0 IEC0 IEC1 IEC1 IEC2 IEC2 IEC3 IEC0 IEC0 IEC2 IEC2 IEC0 IEC0 IEC0 IEC1 IEC1 IEC4 IEC0 IEC0 IEC4 IEC1 IEC1 IEC5 Priority IPC3 IPC4 IPC16 IPC19 IPC0 IPC5 IPC7 IPC4 IPC4 IPC12 IPC12 IPC0 IPC1 IPC9 IPC9 IPC9 IPC4 IPC18 IPC0 IPC1 IPC6 IPC6 IPC10 IPC11 IPC15 IPC2 IPC2 IPC8 IPC8 IPC0 IPC1 IPC2 IPC6 IPC7 IPC16 IPC2 IPC3 IPC16 IPC7 IPC7 IPC21 Interrupt Source ADC1 Conversion Done Comparator Event CRC Generator CTMU Event External Interrupt 0 External Interrupt 1 External Interrupt 2 I2C1 Master Event I2C1 Slave Event I2C2 Master Event I2C2 Slave Event Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Input Change Notification LVD Low-Voltage Detect Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Parallel Master Port Real-Time Clock/Calendar SPI1 Error SPI1 Event SPI2 Error SPI2 Event Timer1 Timer2 Timer3 Timer4 Timer5 UART1 Error UART1 Receiver UART1 Transmitter UART2 Error UART2 Receiver UART2 Transmitter USB Interrupt  2010 Microchip Technology Inc. DS39940D-page 71 PIC24FJ64GB004 FAMILY 7.3 Interrupt Control and Status Registers The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 7-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0, the INT0IE enable bit in IEC0 and the INT0IP priority bits in the first position of IPC0 (IPC0). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU STATUS Register (SR) contains the IPL bits (SR); these indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which, together with IPL, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. The interrupt controller has the Interrupt Controller Test Register (INTTREG) that displays the status of the interrupt controller. When an interrupt request occurs, its associated vector number and the new interrupt priority level are latched into INTTREG. This information can be used to determine a specific interrupt source if a generic ISR is used for multiple vectors – such as when ISR remapping is used in bootloader applications. It also could be used to check if another interrupt is pending while in an ISR. All interrupt registers are described in Register 7-1 through Register 7-35, on the following pages. The PIC24FJ64GB004 family of devices implements the following registers for the interrupt controller: • • • • • INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC21 (except IPC13, IPC14 and IPC17) • INTTREG Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or an external signal, and is cleared via software. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the Interrupt Priority Level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39940D-page 72  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-1: U-0 — bit 15 R/W-0 IPL2 bit 7 Legend: R = Readable bit -n = Value at POR bit 7-5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown (2,3) SR: ALU STATUS REGISTER (IN CPU) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 DC(1) bit 8 R/W-0 IPL1(2,3) R/W-0 IPL0(2,3) R-0 RA(1) R/W-0 N(1) R/W-0 OV(1) R/W-0 Z(1) R/W-0 C(1) bit 0 IPL: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) See Register 3-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1) = 1. Note 1: 2: 3: REGISTER 7-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 3 CORCON: CPU CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(2) R/W-0 PSV(1) U-0 — U-0 — bit 0 C = Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less See Register 3-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. Note 1: 2:  2010 Microchip Technology Inc. DS39940D-page 73 PIC24FJ64GB004 FAMILY REGISTER 7-3: R/W-0 NSTDIS bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 MATHERR R/W-0 ADDRERR R/W-0 STKERR R/W-0 OSCFAIL U-0 — bit 0 INTCON1: INTERRUPT CONTROL REGISTER 1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled Unimplemented: Read as ‘0’ MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred Unimplemented: Read as ‘0’ bit 14-5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39940D-page 74  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-4: R/W-0 ALTIVT bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-0 INT2EP R/W-0 INT1EP INTCON2: INTERRUPT CONTROL REGISTER 2 R-0 DISI U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 INT0EP bit 0 ALTIVT: Enable Alternate Interrupt Vector Table (AIVT) bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) Interrupt Vector Table (IVT) DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active Unimplemented: Read as ‘0’ INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 14 bit 13-3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 75 PIC24FJ64GB004 FAMILY REGISTER 7-5: U-0 — bit 15 R/W-0 T2IF bit 7 IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 — R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 INT0IF bit 0 R/W-0 OC2IF R/W-0 IC2IF U-0 — R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as ‘0’ AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39940D-page 76  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-6: R/W-0 U2TXIF bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2RXIF R/W-0 INT2IF R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 — bit 8 R/W-0 SI2C1IF bit 0 U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 77 PIC24FJ64GB004 FAMILY REGISTER 7-7: U-0 — bit 15 R/W-0 IC5IF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 IC4IF R/W-0 IC3IF U-0 — U-0 — U-0 — R/W-0 SPI2IF IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 — R/W-0 PMPIF U-0 — U-0 — U-0 — R/W-0 OC5IF U-0 — bit 8 R/W-0 SPF2IF bit 0 Unimplemented: Read as ‘0’ PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1 bit 0 DS39940D-page 78  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-0, MI2C2IF R/W-0 SI2C2IF U-0 — bit 0 IFS3: INTERRUPT FLAG STATUS REGISTER 3 R/W-0 RTCIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ bit 13-3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 79 PIC24FJ64GB004 FAMILY REGISTER 7-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/W-0 CRCIF R/W-0 U2ERIF R/W-0 U1ERIF U-0 — bit 0 IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 — R/W-0 CTMUIF U-0 — U-0 — U-0 — U-0 — R/W-0 LVDIF bit 8 Unimplemented: Read as ‘0’ CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ bit 12-9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 DS39940D-page 80  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-10: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 USB1IF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 IFS5: INTERRUPT FLAG STATUS REGISTER 5 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as ‘0’ bit 5-0  2010 Microchip Technology Inc. DS39940D-page 81 PIC24FJ64GB004 FAMILY REGISTER 7-11: U-0 — bit 15 R/W-0 T2IE bit 7 IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 — R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 INT0IE bit 0 R/W-0 OC2IE R/W-0 IC2IE U-0 — R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Unimplemented: Read as ‘0’ AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled DS39940D-page 82  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-12: R/W-0 U2TXIE bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 INT2IE(1) R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 — bit 8 U-0 — U-0 — R/W-0 INT1IE(1) R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 R/W-0 U2RXIE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8-5 bit 4 bit 3 bit 2 bit 1 bit 0 U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPn or PRIx pin. See Section 10.4 “Peripheral Pin Select (PPS)” for more information. Note 1:  2010 Microchip Technology Inc. DS39940D-page 83 PIC24FJ64GB004 FAMILY REGISTER 7-13: U-0 — bit 15 R/W-0 IC5IE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 IC4IE R/W-0 IC3IE U-0 — U-0 — U-0 — R/W-0 SPI2IE IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 — R/W-0 PMPIE U-0 — U-0 — U-0 — R/W-0 OC5IE U-0 — bit 8 R/W-0 SPF2IE bit 0 Unimplemented: Read as ‘0’ PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled bit 12-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4-2 bit 1 bit 0 DS39940D-page 84  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-14: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-0 MI2C2IE R/W-0 SI2C2IE U-0 — bit 0 IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 RTCIE Unimplemented: Read as ‘0’ RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ bit 13-3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 85 PIC24FJ64GB004 FAMILY REGISTER 7-15: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — R/W-0 CRCIE R/W-0 U2ERIE R/W-0 U1ERIE U-0 — bit 0 IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 — R/W-0 CTMUIE U-0 — U-0 — U-0 — U-0 — R/W-0 LVDIE bit 8 Unimplemented: Read as ‘0’ CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ bit 12-9 bit 8 bit 7-4 bit 3 bit 2 bit 1 bit 0 DS39940D-page 86  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-16: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 USB1IE U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request is enabled 0 = Interrupt request is not enabled Unimplemented: Read as ‘0’ bit 5-0  2010 Microchip Technology Inc. DS39940D-page 87 PIC24FJ64GB004 FAMILY REGISTER 7-17: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 IC1IP2 R/W-0 IC1IP1 R/W-0 IC1IP0 U-0 — R/W-1 INT0IP2 R/W-0 INT0IP1 IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 R/W-0 T1IP1 R/W-0 T1IP0 U-0 — R/W-1 OC1IP2 R/W-0 OC1IP1 R/W-0 OC1IP0 bit 8 R/W-0 INT0IP0 bit 0 R/W-1 T1IP2 Unimplemented: Read as ‘0’ T1IP: Timer1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ OC1IP: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ IC1IP: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ INT0IP: External Interrupt 0 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS39940D-page 88  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-18: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 IC2IP2 R/W-0 IC2IP1 R/W-0 IC2IP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 R/W-0 T2IP1 R/W-0 T2IP0 U-0 — R/W-1 OC2IP2 R/W-0 OC2IP1 R/W-0 OC2IP0 bit 8 R/W-1 T2IP2 Unimplemented: Read as ‘0’ T2IP: Timer2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ OC2IP: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ IC2IP: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0  2010 Microchip Technology Inc. DS39940D-page 89 PIC24FJ64GB004 FAMILY REGISTER 7-19: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 SPF1IP2 R/W-0 SPF1IP1 R/W-0 SPF1IP0 U-0 — R/W-1 T3IP2 R/W-0 T3IP1 IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 R/W-0 U1RXIP1 R/W-0 U1RXIP0 U-0 — R/W-1 SPI1IP2 R/W-0 SPI1IP1 R/W-0 SPI1IP0 bit 8 R/W-0 T3IP0 bit 0 R/W-1 U1RXIP2 Unimplemented: Read as ‘0’ U1RXIP: UART1 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ SPI1IP: SPI1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ SPF1IP: SPI1 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ T3IP: Timer3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS39940D-page 90  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-20: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 AD1IP2 R/W-0 AD1IP1 R/W-0 AD1IP0 U-0 — R/W-1 U1TXIP2 R/W-0 U1TXIP1 IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 U1TXIP0 bit 0 Unimplemented: Read as ‘0’ AD1IP: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ U1TXIP: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 bit 2-0  2010 Microchip Technology Inc. DS39940D-page 91 PIC24FJ64GB004 FAMILY REGISTER 7-21: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 MI2C1IP2 R/W-0 MI2C1IP1 R/W-0 MI2C1IP0 U-0 — R/W-1 SI2C1IP2 R/W-0 SI2C1IP1 IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 R/W-0 CNIP1 R/W-0 CNIP0 U-0 — R/W-1 CMIP2 R/W-0 CMIP1 R/W-0 CMIP0 bit 8 R/W-0 SI2C1IP0 bit 0 R/W-1 CNIP2 Unimplemented: Read as ‘0’ CNIP: Input Change Notification Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ CMIP: Comparator Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ MI2C1IP: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ SI2C1IP: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0 DS39940D-page 92  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-22: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-1 INT1IP2 R/W-0 INT1IP1 IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 INT1IP0 bit 0 Unimplemented: Read as ‘0’ INT1IP: External Interrupt 1 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled  2010 Microchip Technology Inc. DS39940D-page 93 PIC24FJ64GB004 FAMILY REGISTER 7-23: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 OC3IP2 R/W-0 OC3IP1 R/W-0 OC3IP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 R/W-0 T4IP1 R/W-0 T4IP0 U-0 — R/W-1 OC4IP2 R/W-0 OC4IP1 R/W-0 OC4IP0 bit 8 R/W-1 T4IP2 Unimplemented: Read as ‘0’ T4IP: Timer4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ OC4IP: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ OC3IP: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0 DS39940D-page 94  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-24: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 INT2IP2 R/W-0 INT2IP1 R/W-0 INT2IP0 U-0 — R/W-1 T5IP2 R/W-0 T5IP1 IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 R/W-0 U2TXIP1 R/W-0 U2TXIP0 U-0 — R/W-1 U2RXIP2 R/W-0 U2RXIP1 R/W-0 U2RXIP0 bit 8 R/W-0 T5IP0 bit 0 R/W-1 U2TXIP2 Unimplemented: Read as ‘0’ U2TXIP: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ U2RXIP: UART2 Receiver Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ INT2IP: External Interrupt 2 Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ T5IP: Timer5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 11 bit 10-8 bit 7 bit 6-4 bit 3 bit 2-0  2010 Microchip Technology Inc. DS39940D-page 95 PIC24FJ64GB004 FAMILY REGISTER 7-25: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 SPI2IP2 R/W-0 SPI2IP1 R/W-0 SPI2IP0 U-0 — R/W-1 SPF2IP2 R/W-0 SPF2IP1 IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 SPF2IP0 bit 0 Unimplemented: Read as ‘0’ SPI2IP: SPI2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ SPF2IP: SPI2 Fault Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled bit 3 bit 2-0 DS39940D-page 96  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-26: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 IC3IP2 R/W-0 IC3IP1 R/W-0 IC3IP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 R/W-0 IC5IP1 R/W-0 IC5IP0 U-0 — R/W-1 IC4IP2 R/W-0 IC4IP1 R/W-0 IC4IP0 bit 8 R/W-1 IC5IP2 Unimplemented: Read as ‘0’ IC5IP: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ IC4IP: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ IC3IP: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0  2010 Microchip Technology Inc. DS39940D-page 97 PIC24FJ64GB004 FAMILY REGISTER 7-27: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 OC5IP2 R/W-0 OC5IP1 R/W-0 OC5IP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ OC5IP: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 3-0 DS39940D-page 98  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-28: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 PMPIP2 R/W-0 PMPIP1 R/W-0 PMPIP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ PMPIP: Parallel Master Port Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 3-0  2010 Microchip Technology Inc. DS39940D-page 99 PIC24FJ64GB004 FAMILY REGISTER 7-29: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 SI2C2IP2 R/W-0 SI2C2IP1 R/W-0 SI2C2IP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 — U-0 — U-0 — U-0 — R/W-1 MI2C2IP2 R/W-0 MI2C2IP1 R/W-0 MI2C2IP0 bit 8 Unimplemented: Read as ‘0’ MI2C2IP: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ SI2C2IP: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 7 bit 6-4 bit 3-0 DS39940D-page 100  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-30: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 — U-0 — U-0 — U-0 — R/W-1 RTCIP2 R/W-0 RTCIP1 R/W-0 RTCIP0 bit 8 Unimplemented: Read as ‘0’ RTCIP: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 7-0  2010 Microchip Technology Inc. DS39940D-page 101 PIC24FJ64GB004 FAMILY REGISTER 7-31: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-1 U1ERIP2 R/W-0 U1ERIP1 R/W-0 U1ERIP0 U-0 — U-0 — U-0 — U-0 — bit 0 IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 R/W-0 CRCIP1 R/W-0 CRCIP0 U-0 — R/W-1 U2ERIP2 R/W-0 U2ERIP1 R/W-0 U2ERIP0 bit 8 R/W-1 CRCIP2 Unimplemented: Read as ‘0’ CRCIP: CRC Generator Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ U2ERIP: UART2 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ U1ERIP: UART1 Error Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 11 bit 10-8 bit 7 bit 6-4 bit 3-0 DS39940D-page 102  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-32: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-1 LVDIP2 R/W-0 LVDIP1 IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 LVDIP0 bit 0 Unimplemented: Read as ‘0’ LVDIP: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled REGISTER 7-33: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6-4 IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-1 CTMUIP2 R/W-0 CTMUIP1 R/W-0 CTMUIP0 U-0 — U-0 — U-0 — U-0 — bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CTMUIP: CTMU Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 3-0  2010 Microchip Technology Inc. DS39940D-page 103 PIC24FJ64GB004 FAMILY REGISTER 7-34: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 — U-0 — U-0 — U-0 — R/W-0 USB1IP2 R/W-0 USB1IP1 R/W-0 USB1IP0 bit 8 Unimplemented: Read as ‘0’ USB1IP: USB Interrupt Priority bits 111 = Interrupt is Priority 7 (highest priority interrupt) • • • 001 = Interrupt is Priority 1 000 = Interrupt source is disabled Unimplemented: Read as ‘0’ bit 7-0 DS39940D-page 104  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 7-35: R-0 CPUIRQ bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-0 VECNUM6 R-0 VECNUM5 R-0 VECNUM4 R-0 VECNUM3 R-0 VECNUM2 R-0 VECNUM1 R-0 VECNUM0 bit 0 INTTREG: INTERRUPT CONTROL AND STATUS REGISTER U-0 — R/W-0 VHOLD U-0 — R-0 ILR3 R-0 ILR2 R-0 ILR1 R-0 ILR0 bit 8 CPUIRQ: Interrupt Request from Interrupt Controller CPU bit 1 = An interrupt request has occurred but has not yet been Acknowledged by the CPU; this happens when the CPU priority is higher than the interrupt priority 0 = No interrupt request is unacknowledged Unimplemented: Read as ‘0’ VHOLD: Vector Number Capture Configuration bit 1 = The VECNUM bits contain the value of the highest priority pending interrupt 0 = The VECNUM bits contain the value of the last Acknowledged interrupt (i.e., the last interrupt that has occurred with higher priority than the CPU, even if other interrupts are pending) Unimplemented: Read as ‘0’ ILR: New CPU Interrupt Priority Level bits 1111 = CPU Interrupt Priority Level is 15 • • • 0001 = CPU Interrupt Priority Level is 1 0000 = CPU Interrupt Priority Level is 0 Unimplemented: Read as ‘0’ VECNUM: Pending Interrupt Vector ID bits (pending vector number is VECNUM + 8) 0111111 = Interrupt vector pending is Number 135 • • • 0000001 = Interrupt vector pending is Number 9 0000000 = Interrupt vector pending is Number 8 bit 14 bit 13 bit 12 bit 11-8 bit 7 bit 6-0  2010 Microchip Technology Inc. DS39940D-page 105 PIC24FJ64GB004 FAMILY 7.4 7.4.1 1. 2. Interrupt Setup Procedures INITIALIZATION 7.4.3 TRAP SERVICE ROUTINE To configure an interrupt source: Set the NSTDIS control bit (INTCON1) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to Priority Level 4. A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 7.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to Priority Level 7 by inclusive ORing the value OEh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (Level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of Priority Levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. 3. 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 7.4.2 INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., ‘C’ or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS39940D-page 106  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 8.0 Note: OSCILLATOR CONFIGURATION This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 6. “Oscillator” (DS39700). The oscillator system for PIC24FJ64GB004 family devices has the following features: • A total of four external and internal oscillator options as clock sources, providing 11 different clock modes • An on-chip USB PLL block to provide a stable 48 MHz clock for the USB module, as well as a range of frequency options for the system clock • Software-controllable switching between various clock sources • Software-controllable postscaler for selective clocking of CPU for system power savings • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • A separate and independently configurable system clock output for synchronizing external hardware A simplified diagram of the oscillator system is shown in Figure 8-1. FIGURE 8-1: PIC24FJ64GB004 FAMILY CLOCK DIAGRAM PIC24FJ64GB004 Family 48 MHz USB Clock Primary Oscillator XT, HS, EC USB PLL XTPLL, HSPLL PLL & DIV PLLDIV CPDIV 8 MHz 4 MHz FRCDIV Peripherals ECPLL,FRCPLL REFOCON Reference Clock Generator REFO OSCO OSCI FRC Oscillator 8 MHz (nominal) Postscaler CLKDIV FRC CLKO Postscaler CPU LPRC Oscillator LPRC 31 kHz (nominal) Secondary Oscillator SOSCO SOSCEN Enable Oscillator SOSC CLKDIV SOSCI Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules  2010 Microchip Technology Inc. DS39940D-page 107 PIC24FJ64GB004 FAMILY 8.1 CPU Clocking Scheme 8.2 Initial Configuration on POR The system clock source can be provided by one of four sources: • Primary Oscillator (POSC) on the OSCI and OSCO pins • Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins • Fast Internal RC (FRC) Oscillator • Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHz PLL. Refer to Section 8.5 “Oscillator Modes and USB Operation” for additional information. The Fast Internal RC (FRC) provides an 8 MHz clock source. It can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 26.1 “Configuration Bits” for further details). The Primary Oscillator Configuration bits, POSCMD (Configuration Word 2), and the Initial Oscillator Select Configuration bits, FNOSC (Configuration Word 2), select the oscillator source that is used at a Power-on Reset. The FRC Primary Oscillator with Postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 8-1. 8.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSM Configuration bits (Configuration Word 2) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (‘0’). The FSCM is enabled only when the FCKSM bits are both programmed (‘00’). TABLE 8-1: CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Source Internal Internal Internal Secondary Primary Primary Primary Primary Primary Internal Internal POSCMD 11 xx 11 11 01 00 10 01 00 11 11 FNOSC 111 110 101 100 011 011 010 010 010 001 000 1 1 Notes 1, 2 1 1 1 Oscillator Mode Fast RC Oscillator with Postscaler (FRCDIV) (Reserved) Low-Power RC Oscillator (LPRC) Secondary (Timer1) Oscillator (SOSC) Primary Oscillator (XT) with PLL Module (XTPLL) Primary Oscillator (EC) with PLL Module (ECPLL) Primary Oscillator (HS) Primary Oscillator (XT) Primary Oscillator (EC) Fast RC Oscillator with PLL Module (FRCPLL) Fast RC Oscillator (FRC) Note 1: 2: OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39940D-page 108  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 8.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers (SFRs): • OSCCON • CLKDIV • OSCTUN The OSCCON register (Register 8-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The CLKDIV register (Register 8-2) controls the features associated with Doze mode, as well as the postscaler for the FRC Oscillator. The OSCTUN register (Register 8-3) allows the user to fine tune the FRC Oscillator over a range of approximately ±12%. REGISTER 8-1: U-0 — bit 15 R/SO-0 CLKLOCK bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 OSCCON: OSCILLATOR CONTROL REGISTER R-0 COSC2 R-0 COSC1 R-0 COSC0 U-0 — R/W-x(1) NOSC2 R/W-x(1) NOSC1 R/W-x(1) NOSC0 bit 8 R/W-0 R-0(3) LOCK U-0 — R/CO-0 CF R/W-0 POSCEN R/W-0 SOSCEN R/W-0 OSWEN bit 0 CO = Clearable Only bit W = Writable bit ‘1’ = Bit is set SO = Settable Only bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IOLOCK(2) Unimplemented: Read as ‘0’ COSC: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Unimplemented: Read as ‘0’ NOSC: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. bit 11 bit 10-8 Note 1: 2: 3:  2010 Microchip Technology Inc. DS39940D-page 109 PIC24FJ64GB004 FAMILY REGISTER 8-1: bit 7 OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled Unimplemented: Read as ‘0’ CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary oscillator continues to operate during Sleep mode 0 = Primary oscillator disabled during Sleep mode SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to the clock source specified by the NOSC bits 0 = Oscillator switch is complete Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is ‘1’, once the IOLOCK bit is set, it cannot be cleared. Also resets to ‘0’ during any valid clock switch or whenever a non-PLL Clock mode is selected. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS39940D-page 110  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 8-2: R/W-0 ROI bit 15 R/W-0 CPDIV1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CPDIV0 R/W-0 PLLEN U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 DOZE2 R/W-0 DOZE1 R/W-0 DOZE0 R/W-0 DOZEN(1) R/W-0 RCDIV2 R/W-0 RCDIV1 R/W-1 RCDIV0 bit 8 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit DOZE: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 DOZEN: DOZE Enable bit(1) 1 = DOZE bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio is set to 1:1 RCDIV: FRC Postscaler Select bits 111 = 31.25 kHz (divide-by-256) 110 = 125 kHz (divide-by-64) 101 = 250 kHz (divide-by-32) 100 = 500 kHz (divide-by-16) 011 = 1 MHz (divide-by-8) 010 = 2 MHz (divide-by-4) 001 = 4 MHz (divide-by-2) 000 = 8 MHz (divide-by-1) CPDIV: USB System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide-by-8)(2) 10 = 8 MHz (divide-by-4)(2) 01 = 16 MHz (divide-by-2) 00 = 32 MHz (divide-by-1) PLLEN: 96 MHz PLL Enable bit 1 = Enable PLL 0 = Disable PLL Unimplemented: Read as ‘0’ This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled. bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4-0 Note 1: 2:  2010 Microchip Technology Inc. DS39940D-page 111 PIC24FJ64GB004 FAMILY REGISTER 8-3: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 TUN5(1) R/W-0 TUN4(1) R/W-0 TUN3(1) R/W-0 TUN2(1) R/W-0 TUN1(1) OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 TUN0(1) bit 0 Unimplemented: Read as ‘0’ TUN: FRC Oscillator Tuning bits(1) 011111 = Maximum frequency deviation 011110 =    000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 =    100001 = 100000 = Minimum frequency deviation Increments or decrements of TUN may not change the FRC frequency in equal steps over the FRC tuning range and may not be monotonic. Note 1: 8.4 Clock Switching Operation 8.4.1 ENABLING CLOCK SWITCHING With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The Primary Oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from Primary Oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. To enable clock switching, the FCKSM Configuration bits in CW2 must be programmed to ‘00’. (Refer to Section 26.1 “Configuration Bits” for further details.) If the FCKSM Configuration bits are unprogrammed (‘1x’), the clock switching function and Fail-Safe Clock Monitor function are disabled; this is the default setting. The NOSCx control bits (OSCCON) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON) has no effect when clock switching is disabled; it is held at ‘0’ at all times. DS39940D-page 112  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 8.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: 1. 2. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock-sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is ‘0’. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. At a minimum, performing a clock switch requires this basic sequence: 1. If desired, read the COSCx bits (OSCCON) to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 2. 3. 4. 5. 3. 4. 5. 6. 7. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 1. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON) and CF (OSCCON) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM is enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing-sensitive code should not be executed during this time. 2: Direct clock switches between any Primary Oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. 8. 2. 3. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 8-1. EXAMPLE 8-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING 4. 5. 6. ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0  2010 Microchip Technology Inc. DS39940D-page 113 PIC24FJ64GB004 FAMILY 8.5 Oscillator Modes and USB Operation TABLE 8-2: SYSTEM CLOCK OPTIONS DURING USB OPERATION Microcontroller Clock Frequency 32 MHz 16 MHz 8 MHz 4 MHz MCU Clock Division (CPDIV) None (00) 2 (01) 4 (10) 8 (11) Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ64GB004 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals. The USB PLL block is shown in Figure 8-2. In this system, the input from the primary oscillator is divided down by a PLL prescaler to generate a 4 MHz output. This is used to drive an on-chip 96 MHz PLL frequency multiplier to drive the two clock branches. One branch uses a fixed, divide-by-2 frequency divider to generate the 48 MHz USB clock. The other branch uses a fixed, divide-by-3 frequency divider and configurable PLL prescaler/divider to generate a range of system clock frequencies. The CPDIV bits select the system clock speed; available clock options are listed in Table 8-2. The USB PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output using the PLLDIV Configuration bits. This limits the choices for primary oscillator frequency to a total of 8 possibilities, shown in Table 8-3. TABLE 8-3: VALID PRIMARY OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS Clock Mode ECPLL ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL HSPLL, ECPLL XTPLL, ECPLL XTPLL, ECPLL PLL Division (PLLDIV) 12 (111) 8 (110) 6 (101) 5 (100) 4 (011) 3 (010) 2 (001) 1 (000) Input Oscillator Frequency 48 MHz 32 MHz 24 MHz 20 MHz 16 MHz 12 MHz 8 MHz 4 MHz FIGURE 8-2: USB PLL BLOCK PLLDIV 48 MHz Clock for USB Module FNOSC PLL Prescaler Input from POSC Input from FRC (4 MHz or 8 MHz) 3 32 MHz PLL Prescaler  12 8 6 5 4 3 2 1 111 110 101 100 011 010 001 000 2 4 MHz 96 MHz PLL 8 4 2 1 11 10 01 00 PLL Output for System Clock CPDIV 8.5.1 CONSIDERATIONS FOR USB OPERATION When using the USB On-The-Go module in PIC24FJ64GB004 family devices, users must always observe these rules in configuring the system clock: • For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. • The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. • All oscillator modes are available; however, USB operation is not possible when these modes are selected. They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is Sleeping and waiting for bus attachment). DS39940D-page 114  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 8.6 8.6.1 Secondary Oscillator (SOSC) BASIC SOSC OPERATION PIC24FJ64GB004 family devices do not have to set the SOSCEN bit to use the secondary oscillator. Any module requiring the SOSC (such as RTCC, Timer1 or DSWDT) will automatically turn on the SOSC when the clock signal is needed. The SOSC, however, has a long start-up time. To avoid delays for peripheral start-up, the SOSC can be manually started using the SOSCEN bit. To use the secondary oscillator, the SOSCSEL bits (CW3) must be configured in an oscillator mode – either ‘11’ or ‘01’. Setting SOSCSEL to ‘00’ configures the SOSC pins for Digital mode, enabling digital I/O functionality on the pins. Digital functionality will not be available if the SOSC is configured in either of the oscillator modes. In general, the crystal circuit connections should be as short as possible. It is also good practice to surround the crystal circuit with a ground loop or ground plane. For more information on crystal circuit design, please refer to Section 6 “Oscillator” (DS39700) of the “PIC24F Family Reference Manual”. Additional information is also available in these Microchip Application Notes: • AN826, “Crystal Oscillator Basics and Crystal Selection for rfPIC® and PICmicro® Devices” (DS00826) • AN849, “Basic PICmicro® Oscillator Design” (DS00849). 8.7 Reference Clock Output 8.6.2 LOW-POWER SOSC OPERATION The secondary oscillator can operate in two distinct levels of power consumption based on device configuration. In Low-Power mode, the oscillator operates in a low drive strength, low-power state. By default, the oscillator uses a higher drive strength, and therefore, requires more power. The Secondary Oscillator Mode Configuration bits, SOSCSEL (CW3), determine the oscillator’s power mode. Programming the SOSCSEL bits to ‘01’ selects low-power operation. The lower drive strength of this mode makes the SOSC more sensitive to noise and requires a longer start-up time. When Low-Power mode is used, care must be taken in the design and layout of the SOSC circuit to ensure that the oscillator starts up and oscillates properly. In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ64GB004 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 8-4). Setting the ROEN bit (REFOCON) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. 8.6.3 EXTERNAL (DIGITAL) CLOCK MODE (SCLKI) The SOSC can also be configured to run from an external 32 kHz clock source, rather than the internal oscillator. In this mode, also referred to as Digital mode, the clock source provided on the SCLKI pin is used to clock any modules that are configured to use the secondary oscillator. In this mode, the crystal driving circuit is disabled and the SOSCEN bit (OSCCON) has no effect. 8.6.4 SOSC LAYOUT CONSIDERATIONS The pinout limitations on low pin count devices, such as those in the PIC24FJ64GB004 family, may make the SOSC more susceptible to noise than other PIC24F devices. Unless proper care is taken in the design and layout of the SOSC circuit, this external noise may introduce inaccuracies into the oscillator’s period.  2010 Microchip Technology Inc. DS39940D-page 115 PIC24FJ64GB004 FAMILY REGISTER 8-4: R/W-0 ROEN bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER U-0 — R/W-0 ROSSLP R/W-0 ROSEL R/W-0 RODIV3 R/W-0 RODIV2 R/W-0 RODIV1 R/W-0 RODIV0 bit 8 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator is enabled on REFO pin 0 = Reference oscillator is disabled Unimplemented: Read as ‘0’ ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator is used as the base clock. Note that the crystal oscillator must be enabled using the FOSC bits; the crystal maintains the operation in Sleep mode. 0 = System clock used as the base clock; base clock reflects any clock switching of the device RODIV: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12 bit 11-8 bit 7-0 DS39940D-page 116  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 9.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 39. “Power-Saving Features with Deep Sleep” (DS39727). The assembly syntax of the PWRSAV instruction is shown in Example 9-1. Note: SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. The PIC24FJ64GB004 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: • Clock Frequency • Instruction-Based Sleep, Idle and Deep Sleep modes • Software Controlled Doze mode • Selective Peripheral Control in Software Combinations of these methods can be used to selectively tailor an application’s power consumption, while still maintaining critical application features, such as timing-sensitive communications. Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to “wake-up”. 9.2.1 SLEEP MODE Sleep mode has these features: • The system clock source is shut down. If an on-chip oscillator is used, it is turned off. • The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. • The I/O pin directions and states are frozen. • The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. • The LPRC clock will continue to run in Sleep mode if the WDT or RTCC, with LPRC as clock source, is enabled. • The WDT, if enabled, is automatically cleared prior to entering Sleep mode. • Some device features or peripherals may continue to operate in Sleep mode. This includes items, such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of these events: • On any interrupt source that is individually enabled • On any form of device Reset • On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. 9.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 8.0 “Oscillator Configuration”. 9.2 Instruction-Based Power-Saving Modes PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. Deep Sleep mode stops clock operation, code execution and all peripherals except RTCC and DSWDT. It also freezes I/O states and removes power to SRAM and Flash memory. EXAMPLE 9-1: PWRSAV PWRSAV BSET PWRSAV PWRSAV INSTRUCTION SYNTAX ; ; ; ; Put the device into SLEEP mode Put the device into IDLE mode Enable Deep Sleep Put the device into Deep SLEEP mode #SLEEP_MODE #IDLE_MODE DSCON, #DSEN #SLEEP_MODE  2010 Microchip Technology Inc. DS39940D-page 117 PIC24FJ64GB004 FAMILY 9.2.2 IDLE MODE Note: Idle mode has these features: • The CPU will stop executing instructions. • The WDT is automatically cleared. • The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 9.4 “Selective Peripheral Module Control”). • If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: • Any interrupt that is individually enabled • Any device Reset • A WDT time-out On wake-up from Idle mode, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. Since Deep Sleep mode powers down the microcontroller by turning off the on-chip VDDCORE voltage regulator, Deep Sleep capability is available only when operating with the internal regulator enabled. 9.2.4.1 Entering Deep Sleep Mode Deep Sleep mode is entered by setting the DSEN bit in the DSCON register, and then executing a SLEEP instruction (PWRSAV #SLEEP_MODE) within one to three instruction cycles to minimize the chance that Deep Sleep will be spuriously entered. If the PWRSAV command is not given within three instruction cycles, the DSEN bit will be cleared by the hardware and must be set again by the software before entering Deep Sleep mode. The DSEN bit is also automatically cleared when exiting the Deep Sleep mode. Note: To re-enter Deep Sleep after a Deep Sleep wake-up, allow a delay of at least 3 TCY after clearing the RELEASE bit. 9.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS The sequence to enter Deep Sleep mode is: 1. If the application requires the Deep Sleep WDT, enable it and configure its clock source (see Section 9.2.4.7 “Deep Sleep WDT” for details). If the application requires Deep Sleep BOR, enable it by programming the DSBOREN Configuration bit (CW4). If the application requires wake-up from Deep Sleep on RTCC alarm, enable and configure the RTCC module (see Section 20.0 “Real-Time Clock and Calendar (RTCC)” for more information). If needed, save any critical application context data by writing it to the DSGPR0 and DSGPR1 registers (optional). Enable Deep Sleep mode by setting the DSEN bit (DSCON). Enter Deep Sleep mode by immediately issuing a PWRSAV #0 instruction. Any interrupt that coincides with the execution of a PWRSAV instruction (except for Deep Sleep mode) will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 2. 9.2.4 DEEP SLEEP MODE 3. In PIC24FJ64GB004 family devices, Deep Sleep mode is intended to provide the lowest levels of power consumption available, without requiring the use of external switches to completely remove all power from the device. Entry into Deep Sleep mode is completely under software control. Exit from Deep Sleep mode can be triggered from any of the following events: • • • • • POR event MCLR event RTCC alarm (If the RTCC is present) External Interrupt 0 Deep Sleep Watchdog Timer (DSWDT) time-out 4. 5. 6. Any time the DSEN bit is set, all bits in the DSWAKE register will be automatically cleared. In Deep Sleep mode, it is possible to keep the device Real-Time Clock and Calendar (RTCC) running without the loss of clock cycles. The device has a dedicated Deep Sleep Brown-out Reset (DSBOR) and a Deep Sleep Watchdog Timer Reset (DSWDT) for monitoring voltage and time-out events. The DSBOR and DSWDT are independent of the standard BOR and WDT used with other power-managed modes (Sleep, Idle and Doze). DS39940D-page 118  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 9.2.4.2 Special Cases when Entering Deep Sleep Mode When entering Deep Sleep mode, there are certain circumstances that require a delay between setting the DSEN bit and executing the PWRSAV instruction. These can be generally reduced to three scenarios: 1. 2. 3. Scenario (1): use an external wake-up source (INT0) or the RTCC Scenario (2): with application-level interrupts that can be temporarily disabled Scenario (3): with interrupts that must be monitored Examples for implementing these cases are shown in Example 9-2. It is recommended that an assembler, or in-line C routine, be used in these cases to ensure that the code executes in the number of cycles required. EXAMPLE 9-2: IMPLEMENTING THE SPECIAL CASES FOR ENTERING DEEP SLEEP In the first scenario, the application requires a wake-up from Deep Sleep on the assertion of the INT0 pin or the RTCC interrupt. In this case, three NOP instructions must be inserted to properly synchronize the detection of an asynchronous INT0 interrupt after the device enters Deep Sleep mode. If the application does not use wake-up on INT0 or RTCC, the NOP instructions are optional. In the second scenario, the application also uses interrupts which can be briefly ignored. With these applications, an interrupt event during the execution of the NOP instructions may cause an ISR to be executed. This means that more than three instruction cycles will elapse before returning to the code and that the DSEN bit will be cleared. To prevent the missed entry into Deep Sleep, temporarily disable interrupts prior to entering Deep Sleep mode. Invoking the DISI instruction for four cycles is sufficient to prevent interrupts from disrupting Deep Sleep entry. In the third scenario, interrupts cannot be ignored even briefly; constant interrupt detection is required, even during the interval between setting DSEN and executing the PWRSAV instruction. For these cases, it is possible to disable interrupts and test for an interrupt condition, skipping the PWRSAV instruction if necessary. Testing for interrupts can be accomplished by checking the status of the CPUIRQ bit (INTTREG); if an unserviced interrupt is pending, this bit will be set. If CPUIRQ is set prior to executing the PWRSAV instruction, the instruction is skipped. At this point, the DISI instruction has expired (being more than 4 instructions from when it was executed) and the application vectors to the appropriate ISR. When the application returns, it can either attempt to re-enter Deep Sleep mode or perform some other system function. In either case, the application must have some functional code located, following the PWRSAV instruction, in the event that the PWRSAV instruction is skipped and the device does not enter Deep Sleep mode. // Case 1: simplest delay scenario // asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("nop"); asm("pwrsav #0"); // // Case 2: interrupts disabled // asm("disi #4"); asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("nop"); asm("pwrsav #0"); // // Case 3: interrupts disabled with // interrupt testing // asm("disi #4"); asm("bset DSCON, #15"); asm("nop"); asm("nop"); asm("btss INTTREG, #15"); asm("pwrsav #0"); // continue with application code here //  2010 Microchip Technology Inc. DS39940D-page 119 PIC24FJ64GB004 FAMILY 9.2.4.3 Exiting Deep Sleep Mode 9.2.4.4 Deep Sleep Wake-up Time Deep Sleep mode exits on any one of the following events: • POR event on VDD supply. If there is no DSBOR circuit to re-arm the VDD supply POR circuit, the external VDD supply must be lowered to the natural arming voltage of the POR circuit. • DSWDT time-out. When the DSWDT timer times out, the device exits Deep Sleep. • RTCC alarm (if RTCEN = 1). • Assertion (‘0’) of the MCLR pin. • Assertion of the INT0 pin (if the interrupt was enabled before Deep Sleep mode was entered). The polarity configuration is used to determine the assertion level (‘0’ or ‘1’) of the pin that will cause an exit from Deep Sleep mode. Exiting from Deep Sleep mode requires a change on the INT0 pin while in Deep Sleep mode. Note: Any interrupt pending when entering Deep Sleep mode is cleared. Since wake-up from Deep Sleep results in a POR, the wake-up time from Deep Sleep is the same as the device POR time. Also, because the internal regulator is turned off, the voltage on VCAP may drop depending on how long the device is asleep. If VCAP has dropped below 2V, then there will be additional wake-up time while the regulator charges VCAP. Deep Sleep wake-up time is specified in Section 29.0 “Electrical Characteristics” as TDSWU. This specification indicates the worst case wake-up time, including the full POR Reset time (including TPOR and TRST), as well as the time to fully charge a 10 F capacitor on VCAP which has discharged to 0V. Wake-up may be significantly faster if VCAP has not discharged. 9.2.4.5 Saving Context Data with the DSGPR0/DSGPR1 Registers Exiting Deep Sleep mode generally does not retain the state of the device and is equivalent to a Power-on Reset (POR) of the device. Exceptions to this include the RTCC (if present), which remains operational through the wake-up, the DSGPRx registers and DSWDT. Wake-up events that occur from the time Deep Sleep exits, until the time that the POR sequence completes, are ignored and are not captured in the DSWAKE register. The sequence for exiting Deep Sleep mode is: 1. After a wake-up event, the device exits Deep Sleep and performs a POR. The DSEN bit is cleared automatically. Code execution resumes at the Reset vector. To determine if the device exited Deep Sleep, read the Deep Sleep bit, DPSLP (RCON). This bit will be set if there was an exit from Deep Sleep mode. If the bit is set, clear it. Determine the wake-up source by reading the DSWAKE register. Determine if a DSBOR event occurred during Deep Sleep mode by reading the DSBOR bit (DSCON). If application context data has been saved, read it back from the DSGPR0 and DSGPR1 registers. Clear the RELEASE bit (DSCON). As exiting Deep Sleep mode causes a POR, most Special Function Registers reset to their default POR values. In addition, because VDDCORE power is not supplied in Deep Sleep mode, information in data RAM may be lost when exiting this mode. Applications which require critical data to be saved prior to Deep Sleep may use the Deep Sleep General Purpose registers, DSGPR0 and DSGPR1, or data EEPROM (if available). Unlike other SFRs, the contents of these registers are preserved while the device is in Deep Sleep mode. After exiting Deep Sleep, software can restore the data by reading the registers and clearing the RELEASE bit (DSCON). 9.2.4.6 I/O Pins During Deep Sleep Mode 2. 3. 4. During Deep Sleep, the general purpose I/O pins retain their previous states and the Secondary Oscillator (SOSC) will remain running, if enabled. Pins that are configured as inputs (TRIS bit set) prior to entry into Deep Sleep remain high-impedance during Deep Sleep. Pins that are configured as outputs (TRIS bit clear) prior to entry into Deep Sleep remain as output pins during Deep Sleep. While in this mode, they continue to drive the output level determined by their corresponding LAT bit at the time of entry into Deep Sleep. 5. 6. DS39940D-page 120  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY Once the device wakes back up, all I/O pins continue to maintain their previous states, even after the device has finished the POR sequence and is executing application code again. Pins configured as inputs during Deep Sleep remain high-impedance and pins configured as outputs continue to drive their previous value. After waking up, the TRIS and LAT registers, and the SOSCEN bit (OSCCON) are reset. If firmware modifies any of these bits or registers, the I/O will not immediately go to the newly configured states. Once the firmware clears the RELEASE bit (DSCON) the I/O pins are “released”. This causes the I/O pins to take the states configured by their respective TRIS and LAT bit values. This means that keeping the SOSC running after waking up requires the SOSCEN bit to be set before clearing RELEASE. If the Deep Sleep BOR (DSBOR) is enabled, and a DSBOR or a true POR event occurs during Deep Sleep, the I/O pins will be immediately released similar to clearing the RELEASE bit. All previous state information will be lost, including the general purpose DSGPR0 and DSGPR1 contents. If a MCLR Reset event occurs during Deep Sleep, the DSGPRx, DSCON and DSWAKE registers will remain valid and the RELEASE bit will remain set. The state of the SOSC will also be retained. The I/O pins, however, will be reset to their MCLR Reset state. Since RELEASE is still set, changes to the SOSCEN bit (OSCCON) cannot take effect until the RELEASE bit is cleared. In all other Deep Sleep wake-up cases, application firmware must clear the RELEASE bit in order to reconfigure the I/O pins. 9.2.4.8 Switching Clocks in Deep Sleep Mode Both the RTCC and the DSWDT may run from either SOSC or the LPRC clock source. This allows both the RTCC and DSWDT to run without requiring both the LPRC and SOSC to be enabled together, reducing power consumption. Running the RTCC from LPRC will result in a loss of accuracy in the RTCC of approximately 5 to 10%. If an accurate RTCC is required, it must be run from the SOSC clock source. The RTCC clock source is selected with the RTCOSC Configuration bit (CW4). Under certain circumstances, it is possible for the DSWDT clock source to be off when entering Deep Sleep mode. In this case, the clock source is turned on automatically (if DSWDT is enabled), without the need for software intervention. However, this can cause a delay in the start of the DSWDT counters. In order to avoid this delay when using SOSC as a clock source, the application can activate SOSC prior to entering Deep Sleep mode. 9.2.4.9 Checking and Clearing the Status of Deep Sleep Mode Upon entry into Deep Sleep mode, the status bit, DPSLP (RCON), becomes set and must be cleared by software. On power-up, the software should read this status bit to determine if the Reset was due to an exit from Deep Sleep mode and clear the bit if it is set. Of the four possible combinations of DPSLP and POR bit states, three cases can be considered: • Both the DPSLP and POR bits are cleared. In this case, the Reset was due to some event other than a Deep Sleep mode exit. • The DPSLP bit is clear, but the POR bit is set. This is a normal Power-on Reset. • Both the DPSLP and POR bits are set. This means that Deep Sleep mode was entered, the device was powered down and Deep Sleep mode was exited. 9.2.4.7 Deep Sleep WDT To enable the DSWDT in Deep Sleep mode, program the Configuration bit, DSWDTEN (CW4). The device Watchdog Timer (WDT) need not be enabled for the DSWDT to function. Entry into Deep Sleep mode automatically resets the DSWDT. The DSWDT clock source is selected by the DSWDTOSC Configuration bit (CW4). The postscaler options are programmed by the DSWDTPS Configuration bits (CW4). The minimum time-out period that can be achieved is 2.1 ms and the maximum is 25.7 days. For more details on the CW4 Configuration register and DSWDT configuration options, refer to Section 26.0 “Special Features”.  2010 Microchip Technology Inc. DS39940D-page 121 PIC24FJ64GB004 FAMILY 9.2.4.10 Power-on Resets (PORs) 9.2.4.11 Summary of Deep Sleep Sequence VDD voltage is monitored to produce PORs. Since exiting from Deep Sleep functionally looks like a POR, the technique described in Section 9.2.4.9 “Checking and Clearing the Status of Deep Sleep Mode” should be used to distinguish between Deep Sleep and a true POR event. When a true POR occurs, the entire device, including all Deep Sleep logic (Deep Sleep registers, RTCC, DSWDT, etc.) is reset. To review, these are the necessary steps involved in invoking and exiting Deep Sleep mode: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Device exits Reset and begins to execute its application code. If DSWDT functionality is required, program the appropriate Configuration bit. Select the appropriate clock(s) for the DSWDT and RTCC (optional). Enable and configure the RTCC (optional). Write context data to the DSGPRx registers (optional). Enable the INT0 interrupt (optional). Set the DSEN bit in the DSCON register. Enter Deep Sleep by issuing a PWRSV #SLEEP_MODE command. Device exits Deep Sleep when a wake-up event occurs. The DSEN bit is automatically cleared. Read and clear the DPSLP status bit in RCON, and the DSWAKE status bits. Read the DSGPRx registers (optional). Once all state related configurations are complete, clear the RELEASE bit. Application resumes normal operation. DS39940D-page 122  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 9-1: R/W-0, HC DSEN(1) bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR HC = Hardware Clearable bit bit 15 W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit C = Clearable bit ‘0’ = Bit is cleared U = Unimplemented, read as ‘0’ x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0, HCS DSBOR (1,2,3) DSCON: DEEP SLEEP CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/C-0, HS RELEASE(1,2) bit 0 HCS = Hardware Clearable/Settable bit DSEN: Deep Sleep Enable bit(1) 1 = Device entered Deep Sleep when PWRSAV #0 was executed in the next instruction 0 = Device entered normal Sleep when PWRSAV #0 was executed Unimplemented: Read as ‘0’ DSBOR: Deep Sleep BOR Event Status bit(1,2,3) 1 = The DSBOR is active and a BOR event is detected during Deep Sleep 0 = The DSBOR is disabled or is active and does not detect a BOR event during Deep Sleep RELEASE: I/O Pin State Deep Sleep Release bit(1,2) 1 = I/O pins and SOSC maintain their states following exit from Deep Sleep, regardless of their LAT and TRIS configuration 0 = I/O pins and SOSC are released from their Deep Sleep states. The pin state is controlled by the LAT and TRIS configurations, and the SOSCEN bit. These bits are reset only in the case of a POR event outside of Deep Sleep mode. Reset value is ‘0’ for initial power-on POR only and ‘1’ for Deep Sleep POR. This is a status bit only; a DSBOR event will NOT cause a wake-up from Deep Sleep. bit 14-2 bit 1 bit 0 Note 1: 2: 3:  2010 Microchip Technology Inc. DS39940D-page 123 PIC24FJ64GB004 FAMILY REGISTER 9-2: U-0 — bit 15 R/W-0, HS DSFLT bit 7 Legend: R = Readable bit -n = Value at POR bit 15-9 bit 8 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown (1) DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0, HS DSINT0(1) bit 8 U-0 — U-0 — R/W-0, HS DSWDT (1) R/W-0, HS DSRTC (1) R/W-0, HS DSMCLR (1) U-0 — R/W-0, HS DSPOR(2) bit 0 Unimplemented: Read as ‘0’ DSINT0: Interrupt-on-Change bit(1) 1 = External Interrupt 0 was asserted during Deep Sleep 0 = External Interrupt 0 was not asserted during Deep Sleep DSFLT: Deep Sleep Fault Detected bit(1) 1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been corrupted 0 = No Fault was detected during Deep Sleep Unimplemented: Read as ‘0’ DSWDT: Deep Sleep Watchdog Timer Time-out bit(1) 1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep 0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep DSRTC: Real-Time Clock and Calendar Alarm bit(1) 1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep 0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep DSMCLR: Deep Sleep MCLR Event bit(1) 1 = The MCLR pin was asserted during Deep Sleep 0 = The MCLR pin was not asserted during Deep Sleep Unimplemented: Read as ‘0’ DSPOR: Power-on Reset Event bit(2) 1 = The VDD supply POR circuit was active and a POR event was detected 0 = The VDD supply POR circuit was not active, or was active, but did not detect a POR event This bit can only be set while the device is in Deep Sleep mode. This bit can be set outside of Deep Sleep. bit 7 bit 6-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS39940D-page 124  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 9.3 Doze Mode 9.4 Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV). The ratio between peripheral and core clock speed is determined by the DOZE bits (CLKDIV). There are eight possible configurations, from 1:1 to 1:128, with 1:1 being the default. It is also possible to use Doze mode to selectively reduce power consumption in event-driven applications. This allows clock-sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV). By default, interrupt events have no effect on Doze mode operation. Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked, and thus, consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: • The Peripheral Enable bit, generically named “XXXEN”, located in the module’s main control SFR. • The Peripheral Module Disable (PMD) bit, generically named “XXXMD”, located in one of the PMD Control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, “XXXIDL”. By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications.  2010 Microchip Technology Inc. DS39940D-page 125 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 126  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 10.0 Note: I/O PORTS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 12. “I/O Ports with Peripheral Pin Select (PPS)” (DS39711). When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/Os. The Data Direction register (TRIS) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LAT), read the latch. Writes to the Output Latch register, write the latch. Reads from the port (PORT), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LAT and TRIS registers, and the port pin will read as zeros. When a pin is shared with another peripheral or function that is defined as an input only, it is regarded as a dedicated port because there is no other competing source of outputs. All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 10.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral’s output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents “loop through”, in which a port’s digital output can drive the input of a peripheral that shares the same pin. Figure 10-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. FIGURE 10-1: BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data 1 0 1 0 Output Enable Output Multiplexers I/O PIO Module Read TRIS Output Data Data Bus WR TRIS D CK Q I/O Pin TRIS Latch D WR LAT + WR PORT CK Data Latch Q Read LAT Input Data Read PORT  2010 Microchip Technology Inc. DS39940D-page 127 PIC24FJ64GB004 FAMILY 10.1.1 OPEN-DRAIN CONFIGURATION 10.2.2 In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. ANALOG INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages up to VDD. Voltage excursions beyond VDD on these pins should be avoided. Table 10-1 summarizes the input voltage capabilities. Refer to Section 29.0 “Electrical Characteristics” for more details. 10.2 Configuring Analog Port Pins TABLE 10-1: Port or Pin PORTA PORTB PORTB PORTC(1) PORTA(1) PORTB PORTB PORTC(1) Note 1: INPUT VOLTAGE TOLERANCE Tolerate d Input VDD Description Only VDD input levels are tolerated. The AD1PCFGL and TRIS registers control the operation of the A/D port pins. Setting a port pin as an analog input also requires that the corresponding TRIS bit be set. If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 5.5V Tolerates input levels above VDD, useful for most standard logic. 10.2.1 I/O PORT WRITE/READ TIMING Not available on 28-pin devices. One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP (Example 10-1). EXAMPLE 10-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISB PORTB, #13 PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB as inputs and PORTB as outputs Delay 1 cycle Next Instruction DS39940D-page 128  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 10.3 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ64GB004 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input Change-of-States (COS) even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 29 external inputs that may be selected (enabled) for generating an interrupt request on a Change-of-State. Registers, CNEN1 and CNEN2, contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a weak pull-up connected to it. The pull-up acts as a current source that is connected to the pin. This eliminates the need for external resistors when push button or keypad devices are connected. The pull-ups are separately enabled using the CNPU1 and CNPU2 registers (for pull-ups). Each CN pin has individual control bits for its pull-up. Setting a control bit enables the weak pull-up for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD-0.7V (typical). Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 10.4.1 AVAILABLE PINS The Peripheral Pin Select feature is used with a range of up to 25 pins, depending on the particular device and its pin count. Pins that support the Peripheral Pin Select feature include the designation “RPn” in their full pin designation, where “n” is the remappable pin number. See Table 1-2 for a summary of pinout options in each package offering. 10.4.2 AVAILABLE PERIPHERALS The peripherals managed by the Peripheral Pin Select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. Peripheral Pin Select is not available for I2C™ change notification inputs, RTCC alarm outputs or peripherals with analog inputs. A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 10.4 Peripheral Pin Select (PPS) A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient work arounds in application code or a complete redesign may be the only option. The Peripheral Pin Select feature provides an alternative to these choices by enabling the user’s peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The Peripheral Pin Select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. Peripheral Pin Select is performed in software and generally does not require the device to be reprogrammed. Hardware 10.4.2.1 Peripheral Pin Select Function Priority Pin-selectable peripheral outputs (for example, OC and UART transmit) take priority over any general purpose digital functions permanently tied to that pin, such as PMP and port I/O. Specialized digital outputs, such as USB functionality, take priority over PPS outputs on the same pin. The pin diagrams at the beginning of this data sheet list peripheral outputs in order of priority. Refer to them for priority concerns on a particular pin. Unlike devices with fixed peripherals, pin-selectable peripheral inputs never take ownership of a pin. The pin’s output buffer is controlled by the pin’s TRIS bit setting, or by a fixed peripheral on the pin. If the pin is configured in Digital mode, then the PPS input will operate correctly, reading the input. If an analog function is enabled on the same pin, the pin-selectable input will be disabled.  2010 Microchip Technology Inc. DS39940D-page 129 PIC24FJ64GB004 FAMILY 10.4.3 CONTROLLING PERIPHERAL PIN SELECT 10.4.3.1 Input Mapping Peripheral Pin Select features are controlled through two sets of Special Function Registers: one to map peripheral inputs and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on if an input or an output is being mapped. The inputs of the Peripheral Pin Select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 10-1 through Register 10-14). Each register contains up to two sets of 5-bit fields, with each set associated with one of the pin-selectable peripherals. Programming a given peripheral’s bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of Peripheral Pin Select options supported by the device. TABLE 10-2: SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name INT1 INT2 IC1 IC2 IC3 IC4 IC5 OCFA OCFB SCK1IN SDI1 SS1IN SCK2IN SDI2 SS2IN T2CK T3CK T4CK T5CK U1CTS U1RX U2CTS U2RX Register RPINR0 RPINR1 RPINR7 RPINR7 RPINR8 RPINR8 RPINR9 RPINR11 RPINR11 RPINR20 RPINR20 RPINR21 RPINR22 RPINR22 RPINR23 RPINR3 RPINR3 RPINR4 RPINR4 RPINR18 RPINR18 RPINR19 RPINR19 Function Mapping Bits INT1R INT2R IC1R IC2R IC3R IC4R IC5R OCFAR OCFBR SCK1R SDI1R SS1R SCK2R SDI2R SS2R T2CKR T3CKR T4CKR T5CKR U1CTSR U1RXR U2CTSR U2RXR Input Name External Interrupt 1 External Interrupt 2 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare Fault A Output Compare Fault B SPI1 Clock Input SPI1 Data Input SPI1 Slave Select Input SPI2 Clock Input SPI2 Data Input SPI2 Slave Select Input Timer2 External Clock Timer3 External Clock Timer4 External Clock Timer5 External Clock UART1 Clear To Send UART1 Receive UART2 Clear To Send UART2 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. DS39940D-page 130  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 10.4.3.2 Output Mapping In contrast to inputs, the outputs of the Peripheral Pin Select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains up to two 5-bit fields, with each field being associated with one RPn pin (see Register 10-15 through Register 10-27). The value of the bit field corresponds to one of the peripherals and that peripheral’s output is mapped to the pin (see Table 10-3). Because of the mapping technique, the list of peripherals for output mapping also includes a null value of ‘000000’. This permits any given pin to remain disconnected from the output of any of the pin-selectable peripherals. TABLE 10-3: SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Function NULL(2) C1OUT C2OUT U1TX U1RTS (3) Output Function Number(1) 0 1 2 3 4 5 6 7 8 9 10 11 12 18 19 20 21 22 23-28 29 30 31 Note 1: 2: 3: Output Name Null Comparator 1 Output Comparator 2 Output UART1 Transmit UART1 Request To Send UART2 Transmit UART2 Request To Send SPI1 Data Output SPI1 Clock Output SPI1 Slave Select Output SPI2 Data Output SPI2 Clock Output SPI2 Slave Select Output Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 NC CTMU Output Pulse Comparator 3 Output NC U2TX U2RTS(3) SDO1 SCK1OUT SS1OUT SDO2 SCK2OUT SS2OUT OC1 OC2 OC3 OC4 OC5 (unused) CTPLS C3OUT (unused) Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA® BCLK functionality uses this output.  2010 Microchip Technology Inc. DS39940D-page 131 PIC24FJ64GB004 FAMILY 10.4.3.3 Mapping Limitations 10.4.4.1 Control Register Lock The control schema of the Peripheral Pin Select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input, or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON. Write 57h to OSCCON. Clear (or set) IOLOCK as a single operation. 10.4.3.4 PPS Mapping Exceptions for PIC24FJ64GB0 Family Devices Although the PPS registers allow for up to 32 remappable pins, not all of these are implemented in all devices. Exceptions and unimplemented RPn pins are listed in Table 10-4. TABLE 10-4: REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ64GB004 FAMILY DEVICES RP Pins (I/O) Total 15 25 Unimplemented RP12, RP16-RP25 RP12 Unlike the similar sequence with the oscillator’s LOCK bit, IOLOCK remains in one state until changed. This allows all of the Peripheral Pin Selects to be configured with a single unlock sequence, followed by an update to all control registers, then locked with a second lock sequence. 10.4.4.2 Continuous State Monitoring Device Pin Count 28 Pins 44 Pins 10.4.4 CONTROLLING CONFIGURATION CHANGES In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 10.4.4.3 Configuration Bit Pin Select Lock Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: • Control register lock sequence • Continuous state monitoring • Configuration bit remapping lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the Peripheral Pin Select registers. DS39940D-page 132  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 10.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control Peripheral Pin Selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the Peripheral Pin Selects are not available on default pins in the device’s default (Reset) state. Since all RPINRx registers reset to ‘11111’ and all RPORx registers reset to ‘00000’, all Peripheral Pin Select inputs are tied to VSS and all Peripheral Pin Select outputs are disconnected. Note: RP31 does not have to exist on a device for the registers to be reset to it, or for peripheral pin outputs to be tied to it. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin’s I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that Peripheral Pin Select functions neither override analog inputs, nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a Peripheral Pin Select. Example 10-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: • Input Functions: U1RX, U1CTS • Output Functions: U1TX, U1RTS This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing-critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing in-line assembly. Choosing the configuration requires the review of all Peripheral Pin Selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output.  2010 Microchip Technology Inc. DS39940D-page 133 PIC24FJ64GB004 FAMILY EXAMPLE 10-2: ;unlock push push push mov mov mov mov.b mov.b bclr CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ASSEMBLY CODE registers w1; w2; w3; #OSCCON, w1; #0x46, w2; #0x57, w3; w2, [w1]; w3, [w1]; OSCCON, #6; ; Configure Input Functions (Table10-2) ; Assign U1CTS To Pin RP1, U1RX To Pin RP0 mov #0x0100, w1; mov w1,RPINR18; ; Configure Output Functions (Table 10-3) ; Assign U1RTS To Pin RP3, U1TX To Pin RP2 mov #0x0403, w1; mov w1, RPOR1; ;lock mov mov mov mov.b mov.b bset pop pop pop registers #OSCCON, w1; #0x46, w2; #0x57, w3; w2, [w1]; w3, [w1]; OSCCON, #6; w3; w2; w1; EXAMPLE 10-3: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS IN ‘C’ //unlock registers __builtin_write_OSCCONL(OSCCON & 0xBF); // Configure Input Functions (Table 9-1) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; //lock registers __builtin_write_OSCCONL(OSCCON | 0x40); DS39940D-page 134  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 10.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ64GB004 family of devices implements a total of 27 registers for remappable peripheral configuration: • Input Remappable Peripheral Registers (14) • Output Remappable Peripheral Registers (13) Input and output register values can only be changed if IOLOCK (OSCCON) = 0. See Section 10.4.4.1 “Control Register Lock” for a specific command sequence. REGISTER 10-1: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-0 RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 — U-0 — R/W-1 INT1R4 R/W-1 INT1R3 R/W-1 INT1R2 R/W-1 INT1R1 R/W-1 INT1R0 bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ INT1R: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ REGISTER 10-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — R/W-1 INT2R4 R/W-1 INT2R3 R/W-1 INT2R2 R/W-1 INT2R1 R/W-1 INT2R0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ INT1R: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39940D-page 135 PIC24FJ64GB004 FAMILY REGISTER 10-3: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 T2CKR4 R/W-1 T2CKR3 R/W-1 T2CKR2 R/W-1 T2CKR1 RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 — U-0 — R/W-1 T3CKR4 R/W-1 T3CKR3 R/W-1 T3CKR2 R/W-1 T3CKR1 R/W-1 T3CKR0 bit 8 R/W-1 T2CKR0 bit 0 Unimplemented: Read as ‘0’ T3CKR: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ T2CKR: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits REGISTER 10-4: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 — U-0 — R/W-1 T5CKR4 R/W-1 T5CKR3 R/W-1 T5CKR2 R/W-1 T5CKR1 R/W-1 T5CKR0 bit 8 U-0 — U-0 — R/W-1 T4CKR4 R/W-1 T4CKR3 R/W-1 T4CKR2 R/W-1 T4CKR1 R/W-1 T4CKR0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ T5CKR: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ T4CKR: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits DS39940D-page 136  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 10-5: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 IC1R4 R/W-1 IC1R3 R/W-1 IC1R2 R/W-1 IC1R1 RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 — U-0 — R/W-1 IC2R4 R/W-1 IC2R3 R/W-1 IC2R2 R/W-1 IC2R1 R/W-1 IC2R0 bit 8 R/W-1 IC1R0 bit 0 Unimplemented: Read as ‘0’ IC2R: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ IC1R: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits REGISTER 10-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 — U-0 — R/W-1 IC4R4 R/W-1 IC4R3 R/W-1 IC4R2 R/W-1 IC4R1 R/W-1 IC4R0 bit 8 U-0 — U-0 — R/W-1 IC3R4 R/W-1 IC3R3 R/W-1 IC3R2 R/W-1 IC3R1 R/W-1 IC3R0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ IC4R: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ IC3R: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39940D-page 137 PIC24FJ64GB004 FAMILY REGISTER 10-7: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 IC5R4 R/W-1 IC5R3 R/W-1 IC5R2 R/W-1 IC5R1 RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-1 IC5R0 bit 0 Unimplemented: Read as ‘0’ IC5R: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits REGISTER 10-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 — U-0 — R/W-1 OCFBR4 R/W-1 OCFBR3 R/W-1 OCFBR2 R/W-1 OCFBR1 R/W-1 OCFBR0 bit 8 U-0 — U-0 — R/W-1 OCFAR4 R/W-1 OCFAR3 R/W-1 OCFAR2 R/W-1 OCFAR1 R/W-1 OCFAR0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ OCFBR: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ OCFAR: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits DS39940D-page 138  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 10-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 U1RXR4 R/W-1 U1RXR3 R/W-1 U1RXR2 R/W-1 U1RXR1 RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 — U-0 — R/W-1 U1CTSR4 R/W-1 U1CTSR3 R/W-1 U1CTSR2 R/W-1 U1CTSR1 R/W-1 U1CTSR0 bit 8 R/W-1 U1RXR0 bit 0 Unimplemented: Read as ‘0’ U1CTSR: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ U1RXR: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 10-10: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 U2RXR4 R/W-1 U2RXR3 R/W-1 U2RXR2 R/W-1 U2RXR1 U-0 — U-0 — R/W-1 U2CTSR4 R/W-1 U2CTSR3 R/W-1 U2CTSR2 R/W-1 U2CTSR1 R/W-1 U2CTSR0 bit 8 R/W-1 U2RXR0 bit 0 Unimplemented: Read as ‘0’ U2CTSR: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ U2RXR: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39940D-page 139 PIC24FJ64GB004 FAMILY REGISTER 10-11: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SDI1R4 R/W-1 SDI1R3 R/W-1 SDI1R2 R/W-1 SDI1R1 U-0 — U-0 — R/W-1 SCK1R4 R/W-1 SCK1R3 R/W-1 SCK1R2 R/W-1 SCK1R1 R/W-1 SCK1R0 bit 8 R/W-1 SDI1R0 bit 0 Unimplemented: Read as ‘0’ SCK1R: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ SDI1R: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 10-12: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SS1R4 R/W-1 SS1R3 R/W-1 SS1R2 R/W-1 SS1R1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-1 SS1R0 bit 0 Unimplemented: Read as ‘0’ SS1R: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits DS39940D-page 140  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 10-13: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SDI2R4 R/W-1 SDI2R3 R/W-1 SDI2R2 R/W-1 SDI2R1 U-0 — U-0 — R/W-1 SCK2R4 R/W-1 SCK2R3 R/W-1 SCK2R2 R/W-1 SCK2R1 R/W-1 SCK2R0 bit 8 R/W-1 SDI2R0 bit 0 Unimplemented: Read as ‘0’ SCK2R: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits Unimplemented: Read as ‘0’ SDI2R: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 10-14: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-1 SS2R4 R/W-1 SS2R3 R/W-1 SS2R2 R/W-1 SS2R1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-1 SS2R0 bit 0 Unimplemented: Read as ‘0’ SS2R: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits  2010 Microchip Technology Inc. DS39940D-page 141 PIC24FJ64GB004 FAMILY REGISTER 10-15: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP2R4 R/W-0 RP2R3 R/W-0 RP2R2 R/W-0 RP2R1 U-0 — U-0 — R/W-0 RP3R4 R/W-0 RP3R3 R/W-0 RP3R2 R/W-0 RP3R1 R/W-0 RP3R0 bit 8 R/W-0 RP2R0 bit 0 Unimplemented: Read as ‘0’ RP3R: RP3 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP3 (see Table 10-3 for peripheral function numbers). Unimplemented: Read as ‘0’ RP2R: RP2 Output Pin Mapping bits Peripheral output number n is assigned to pin, RP2 (see Table 10-3 for peripheral function numbers). REGISTER 10-16: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 RP0R4 R/W-0 RP0R3 R/W-0 RP0R2 R/W-0 RP0R1 U-0 — U-0 — R/W-0 RP1R4 R/W-0 RP1R3 R/W-0 RP1R2 R/W-0 RP1R1 R/W-0 RP1R0 bit 8 R/W-0 RP0R0 bit 0 Unimplemented: Read as ‘0’ RP1R VVBUS_VLD Bus Condition If UVCMPSEL = 0 If UVCMPSEL = 1 VBUSVLD 0 0 0 1 SESSVLD 0 0 1 1 SESSEND 1 0 0 0 VBUS < VB_SESS_END VB_SESS_END < VBUS < VA_SESS_VLD VA_SESS_VLD < VBUS < VA_VBUS_VLD VBUS > VVBUS_VLD Bus Condition  2010 Microchip Technology Inc. DS39940D-page 211 PIC24FJ64GB004 FAMILY 18.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: • • • • USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) Registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: • U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as ‘0’ for boundary alignment • U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame • U1PWMRRS: Contains the 8-bit value for PWM duty cycle (bits) and PWM period (bits) for the VBUS boost assist PWM module. This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 18-1 and Register 18-2, are shown separately in Section 18.2 “USB Buffer Descriptors and the BDT”. With the exception U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented, and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. DS39940D-page 212  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 18.7.1 USB OTG MODULE CONTROL REGISTERS U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — R-0, HSC LSTATE U-0 — R-0, HSC SESVD R-0, HSC SESEND U-0 — R-0, HSC VBUSVD bit 0 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown REGISTER 18-3: U-0 — bit 15 R-0, HSC ID bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 Unimplemented: Read as ‘0’ ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle Unimplemented: Read as ‘0’ LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has NOT been stable for the previous 1 ms Unimplemented: Read as ‘0’ SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device SESEND: B-Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device Unimplemented: Read as ‘0’ VBUSVD: A-VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 213 PIC24FJ64GB004 FAMILY REGISTER 18-4: U-0 — bit 15 R/W-0 DPPULUP bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 DMPULUP R/W-0 R/W-0 R/W-0 VBUSON(1) R/W-0 OTGEN(1) R/W-0 U-0 — U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 bit 0 DPPULDWN(1) DMPULDWN(1) VBUSCHG(1) VBUSDIS(1) Unimplemented: Read as ‘0’ DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled VBUSON: VBUS Power-on bit(1) 1 = VBUS line is powered 0 = VBUS line is not powered OTGEN: OTG Features Enable bit(1) 1 = USB OTG is enabled; all D+/D- pull-ups and pull-downs bits are enabled 0 = USB OTG is disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of the HOSTEN and USBEN bits (U1CON) VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line is set to charge to 3.3V 0 = VBUS line is set to charge to 5V VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line is discharged through a resistor 0 = VBUS line is not discharged These bits are only used in Host mode; do not use in Device mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39940D-page 214  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-5: U-0 — bit 15 R/W-0, HS UACTPND bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set HC = Hardware Clearable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 USLPGRD U-0 — U-0 — R/W-0, HC USUSPND U1PWRC: USB POWER CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 USBPWR bit 0 Unimplemented: Read as ‘0’ UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires USLPGRD bit to be set) 0 = Module may be suspended or powered down Unimplemented: Read as ‘0’ USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend Unimplemented: Read as ‘0’ USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON and U1OTGCON) are all cleared. bit 6-5 bit 4 bit 3-2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 215 PIC24FJ64GB004 FAMILY REGISTER 18-6: U-0 — bit 15 R-0, HSC ENDPT3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-0, HSC ENDPT2 R-0, HSC ENDPT1 R-0, HSC ENDPT0 R-0, HSC DIR R-0, HSC PPBI(1) U-0 — U-0 — bit 0 U1STAT: USB STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 Unimplemented: Read as ‘0’ ENDPT: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer). 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (Tx) 0 = The last transaction was a receive transfer (Rx) PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank Unimplemented: Read as ‘0’ This bit is only valid for endpoints with available EVEN and ODD BD registers. bit 3 bit 2 bit 1-0 Note 1: DS39940D-page 216  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-7: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-7 bit 6 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 PKTDIS U-0 — R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 USBEN bit 0 Unimplemented: Read as ‘0’ SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing are disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing are enabled Unimplemented: Read as ‘0’ HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling is activated 0 = Resume signaling is disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers are not reset USBEN: USB Module Enable bit 1 = USB module and supporting circuitry are enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry are disabled (device detached) bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 217 PIC24FJ64GB004 FAMILY REGISTER 18-8: U-0 — bit 15 R-x, HSC JSTATE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ W = Writable bit ‘1’ = Bit is set HSC = Hardware Settable/Clearable bit ‘0’ = Bit is cleared x = Bit is unknown R-x, HSC SE0 R/W-0 TOKBUSY R/W-0 USBRST R/W-0 HOSTEN R/W-0 RESUME R/W-0 PPBRST U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 SOFEN bit 0 Unimplemented: Read as ‘0’ JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential ‘0’ in low speed, differential ‘1’ in full speed) is detected on the USB 0 = No J state was detected SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero is active on the USB bus 0 = No single-ended zero is detected TOKBUSY: Token Busy Status bit 1 = Token is being executed by the USB module in On-The-Go state 0 = No token is being executed USBRST: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 50 ms, then clear it 0 = USB Reset is terminated HOSTEN: Host Mode Enable bit 1 = USB host capability is enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability is disabled RESUME: Resume Signaling Enable bit 1 = Resume signaling activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling disabled PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers are not reset SOFEN: Start-of-Frame Enable bit 1 = Start-of-Frame token is sent every one 1 millisecond 0 = Start-of-Frame token is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39940D-page 218  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-9: U-0 — bit 15 R/W-0 LSPDEN(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADDR6 R/W-0 ADDR5 R/W-0 ADDR4 R/W-0 ADDR3 R/W-0 ADDR2 R/W-0 ADDR1 U1ADDR: USB ADDRESS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 ADDR0 bit 0 Unimplemented: Read as ‘0’ LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed ADDR: USB Device Address bits Host mode only. In Device mode, this bit is unimplemented and read as ‘0’. bit 6-0 Note 1: REGISTER 18-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 — bit 15 R/W-0 PID3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 PID2 R/W-0 PID1 R/W-0 PID0 R/W-0 EP3 R/W-0 EP2 R/W-0 EP1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 EP0 bit 0 Unimplemented: Read as ‘0’ PID: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) EP: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. All other combinations are reserved and are not to be used. bit 3-0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 219 PIC24FJ64GB004 FAMILY REGISTER 18-11: U-0 — bit 15 R/W-0 CNT7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 CNT6 R/W-0 CNT5 R/W-0 CNT4 R/W-0 CNT3 R/W-0 CNT2 R/W-0 CNT1 R/W-0 CNT0 bit 0 Unimplemented: Read as ‘0’ CNT: Start-of-Frame Size bits; Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 — bit 15 R/W-0 UTEYE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 R/W-0 UOEMON(1) U-0 — R/W-0 USBSIDL U-0 — U-0 — R/W-0 PPB1 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PPB0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test is enabled 0 = Eye pattern test is disabled UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal is active; it indicates the intervals during which the D+/D- lines are driving 0 = OE signal is inactive Unimplemented: Read as ‘0’ USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ This bit is only active when the UTRDIS bit (U1CNFG2) is set. bit 6 bit 5 bit 4 bit 3-2 Note 1: DS39940D-page 220  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-12: U1CNFG1: USB CONFIGURATION REGISTER 1 (CONTINUED) bit 1-0 PPB: Ping-Pong Buffers Configuration bit 11 = EVEN/ODD ping-pong buffers are enabled for Endpoints 1 to 15 10 = EVEN/ODD ping-pong buffers are enabled for all endpoints 01 = EVEN/ODD ping-pong buffers are enabled for OUT Endpoint 0 00 = EVEN/ODD ping-pong are buffers are disabled This bit is only active when the UTRDIS bit (U1CNFG2) is set. Note 1: REGISTER 18-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-6 bit 5 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 UVCMPSEL R/W-0 PUVBUS R/W-0 EXTI2CEN R/W-0 R/W-0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 UTRDIS(1) bit 0 UVBUSDIS(1) UVCMPDIS(1) Unimplemented: Read as ‘0’ UVCMPSEL: External Comparator Input Mode Select bit (see Table 18-3) When UVCMPDIS is set: 1 = Use 3 pin input for external comparators 0 = Use 2 pin input for external comparators PUVBUS: VBUS Pull-up Enable bit 1 = Pull-up on VBUS pin is enabled 0 = Pull-up on VBUS pin is disabled EXTI2CEN: I2C™ Interface For External Module Control Enable bit 1 = External module(s) is controlled via I2C interface 0 = External module(s) is controlled via dedicated pins UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder is disabled; digital output control interface is enabled 0 = On-chip boost regulator builder is active UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator is disabled; digital input status interface is enabled 0 = On-chip charge VBUS comparator is active UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver is disabled; digital transceiver interface is enabled 0 = On-chip transceiver is active Never change these bits while the USBPWR bit is set (U1PWRC = 1). bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 221 PIC24FJ64GB004 FAMILY 18.7.2 USB INTERRUPT REGISTERS REGISTER 18-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 — bit 15 R/K-0, HS IDIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown R/K-0, HS T1MSECIF R/K-0, HS LSTATEIF R/K-0, HS ACTVIF R/K-0, HS SESVDIF R/K-0, HS SESENDIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS VBUSVDIF bit 0 Unimplemented: Read as ‘0’ IDIF: ID State Change Indicator bit 1 = Change in ID state is detected 0 = No ID state change T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS is detected 0 = No activity on the D+/D- lines or VBUS is detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device is detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END Unimplemented: Read as ‘0’ VBUSVDIF A-Device VBUS Change Indicator bit 1 = VBUS change on A-device is detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device is detected VBUS threshold crossings may be either rising or falling. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39940D-page 222  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 — bit 15 R/W-0 IDIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 T1MSECIE R/W-0 LSTATEIE R/W-0 ACTVIE R/W-0 SESVDIE R/W-0 SESENDIE U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 VBUSVDIE bit 0 Unimplemented: Read as ‘0’ IDIE: ID Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as ‘0’ VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0  2010 Microchip Technology Inc. DS39940D-page 223 PIC24FJ64GB004 FAMILY REGISTER 18-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 — bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS URSTIF bit 0 Unimplemented: Read as ‘0’ STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent Unimplemented: Read as ‘0’ RESUMEIF: Resume Interrupt bit 1 = A K-state was observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state was observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition was detected (constant Idle state of 3 ms or more) 0 = No Idle condition was detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token was complete; read U1STAT register for endpoint information 0 = Processing of current token was not complete; clear U1STAT register or load next token from STAT (clearing this bit causes the STAT FIFO to advance) SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token received by the peripheral or the Start-of-Frame threshold was reached by the host 0 = No Start-of-Frame token was received or threshold reached UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: DS39940D-page 224  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 — bit 15 R/K-0, HS STALLIF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown R/K-0, HS ATTACHIF R/K-0, HS RESUMEIF R/K-0, HS IDLEIF R/K-0, HS TRNIF R/K-0, HS SOFIF R-0 UERRIF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS DETACHIF bit 0 Unimplemented: Read as ‘0’ STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attachment is detected RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential ‘1’ for low speed, differential ‘0’ for full speed) 0 = No K-state is observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition is detected (constant Idle state of 3 ms or more) 0 = No Idle condition is detected TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token is not complete; clear U1STAT register or load next token from U1STAT SOFIF: Start-of-Frame Token Interrupt bit 1 = A Start-of-Frame token is received by the peripheral or the Start-of-Frame threshold reached by the host 0 = No Start-of-Frame token is received or threshold reached UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment detected. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note:  2010 Microchip Technology Inc. DS39940D-page 225 PIC24FJ64GB004 FAMILY REGISTER 18-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 — bit 15 R/W-0 STALLIE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ATTACHIE (1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 RESUMEIE R/W-0 IDLEIE R/W-0 TRNIE R/W-0 SOFIE R/W-0 UERRIE R/W-0 URSTIE DETACHIE bit 0 Unimplemented: Read as ‘0’ STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt is enabled 0 = Interrupt is disabled RESUMEIE: Resume Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled IDLEIE: Idle Detect Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt is enabled 0 = Interrupt disabled UERRIE: USB Error Condition Interrupt bit 1 = Interrupt is enabled 0 = Interrupt is disabled URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented in Device mode; read as ‘0’. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS39940D-page 226  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 18-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 — bit 15 R/K-0, HS BTSEF bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 U = Unimplemented bit, read as ‘0’ K = Write ‘1’ to clear bit ‘1’ = Bit is set HS = Hardware Settable bit ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/K-0, HS DMAEF R/K-0, HS BTOEF R/K-0, HS DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/K-0, HS PIDEF bit 0 Unimplemented: Read as ‘0’ BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error Unimplemented: Read as ‘0’ DMAEF: DMA Error Flag bit 1 = A USB DMA error condition detected; the data size indicated by the BD byte count field is less than the number of received bytes. The received data is truncated. 0 = No DMA error BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt disabled PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed. Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note: Individual bits can only be cleared by writing a ‘1’ to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared.  2010 Microchip Technology Inc. DS39940D-page 227 PIC24FJ64GB004 FAMILY REGISTER 18-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 — bit 15 R/W-0 BTSEE bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 DMAEE R/W-0 BTOEE R/W-0 DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PIDEE bit 0 Unimplemented: Read as ‘0’ BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as ‘0’ DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS39940D-page 228  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 18.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 18-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15) U-0 — bit 15 R/W-0 LSPD(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 RETRYDIS(1) U-0 — R/W-0 EPCONDIS R/W-0 EPRXEN R/W-0 EPTXEN R/W-0 EPSTALL U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 EPHSHK bit 0 Unimplemented: Read as ‘0’ LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device is enabled 0 = Direct connection to a low-speed device is disabled RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions are disabled 0 = Retry NAK transactions are enabled; retry done in hardware Unimplemented: Read as ‘0’ EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers are allowed 0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also are allowed. For all other combinations of EPTXEN and EPRXEN: This bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive is enabled 0 = Endpoint n receive is disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit is enabled 0 = Endpoint n transmit is disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake is enabled 0 = Endpoint handshake is disabled (typically used for isochronous endpoints) These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as ‘0’. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 229 PIC24FJ64GB004 FAMILY 18.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 18-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 PWMEN bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 PWMPOL R/W-0 CNTEN bit 8 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in Reset state specified by PWMPOL Unimplemented: Read as ‘0’ PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled Unimplemented: Read as ‘0’ bit 14-10 bit 9 bit 8 bit 7-0 DS39940D-page 230  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 19.0 Note: PARALLEL MASTER PORT (PMP) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 13. “Parallel Master Port (PMP)” (DS39713). Key features of the PMP module include: • Up to 16 Programmable Address Lines • One Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels The Parallel Master Port (PMP) module is a parallel, 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Note: A number of the pins for the PMP are not present on PIC24FJ64GB0 family devices. Refer to the specific device’s pinout to determine which pins are available. FIGURE 19-1: PMP MODULE OVERVIEW Address Bus Data Bus Control Lines PMA PMALL PMA PMALH (1) Up to 11-Bit Address PIC24F Parallel Master Port PMA PMCS1 EEPROM PMBE PMRD PMRD/PMWR PMWR PMENB PMD PMA PMA Microcontroller LCD FIFO Buffer 8-Bit Data Note 1: PMA bits are not available on 28-pin devices.  2010 Microchip Technology Inc. DS39940D-page 231 PIC24FJ64GB004 FAMILY REGISTER 19-1: R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CSF0 R/W-0(2) ALP U-0 — R/W-0(2) CS1P R/W-0 BEP R/W-0 WRSP PMCON: PARALLEL PORT CONTROL REGISTER U-0 — R/W-0 PSIDL R/W-0 R/W-0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 RDSP bit 0 ADRMUX1(1) ADRMUX0(1) PMPEN: Parallel Master Port Enable bit 1 = PMP is enabled 0 = PMP is disabled, no off-chip access performed Unimplemented: Read as ‘0’ PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins; upper 3 bits are multiplexed on PMA 00 = Address and data appear on separate pins PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port is enabled 0 = PMBE port is disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port is enabled 0 = PMWR/PMENB port is disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port is enabled 0 = PMRD/PMWR port is disabled CSF: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip set 01 = Reserved 00 = Reserved ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Unimplemented: Read as ‘0’ CS1P: Chip Select 1 Polarity bit(2) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) PMA bits are not available on 28-pin devices. These bits have no effect when their corresponding pins are used as address lines. bit 14 bit 13 bit 12-11 bit 10 bit 9 bit 8 bit 7-6 bit 5 bit 4 bit 3 Note 1: 2: DS39940D-page 232  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 19-1: bit 2 PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) BEP: Byte Enable Polarity bit 1 = Byte enable is active-high (PMBE) 0 = Byte enable is active-low (PMBE) WRSP: Write Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODE = 00,01,10): 1 = Write strobe is active-high (PMWR) 0 = Write strobe is active-low (PMWR) For Master Mode 1 (PMMODE = 11): 1 = Enable strobe is active-high (PMENB) 0 = Enable strobe is active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master Mode 2 (PMMODE = 00,01,10): 1 = Read strobe is active-high (PMRD) 0 = Read strobe is active-low (PMRD) For Master Mode 1 (PMMODE = 11): 1 = Read/write strobe is active-high (PMRD/PMWR) 0 = Read/write strobe is active-low (PMRD/PMWR) PMA bits are not available on 28-pin devices. These bits have no effect when their corresponding pins are used as address lines. bit 1 bit 0 Note 1: 2:  2010 Microchip Technology Inc. DS39940D-page 233 PIC24FJ64GB004 FAMILY REGISTER 19-2: R-0 BUSY bit 15 R/W-0 WAITB1(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 WAITB0(1) R/W-0 WAITM3 R/W-0 WAITM2 R/W-0 WAITM1 R/W-0 WAITM0 R/W-0 WAITE1(1) PMMODE: PARALLEL PORT MODE REGISTER R/W-0 IRQM0 R/W-0 INCM1 R/W-0 INCM0 R/W-0 MODE16 R/W-0 MODE1 R/W-0 MODE0 bit 8 R/W-0 WAITE0(1) bit 0 R/W-0 IRQM1 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy IRQM: Interrupt Request Mode bits 11 = Interrupt is generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = No interrupt is generated; processor stall activated 01 = Interrupt is generated at the end of the read/write cycle 00 = No interrupt is generated INCM: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR by 1 every read/write cycle 01 = Increment ADDR by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits; a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits; a read or write to the Data register invokes one 8-bit transfer MODE: Parallel Port Mode Select bits 11 = Master Mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA and PMD) 10 = Master Mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA and PMD) 01 = Enhanced PSP control signals (PMRD, PMWR, PMCS1, PMD and PMA) 00 = Legacy Parallel Slave Port control signals (PMRD, PMWR, PMCS1 and PMD) WAITB: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY WAITM: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) WAITE: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY WAITB and WAITE bits are ignored whenever WAITM = 0000. bit 14-13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5-2 bit 1-0 Note 1: DS39940D-page 234  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 19-3: U-0 — bit 15 R/W-0 ADDR7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown (1) PMADDR: PARALLEL PORT ADDRESS REGISTER U-0 — U-0 — U-0 — R/W-0 ADDR10(1) R/W-0 ADDR9(1) R/W-0 ADDR8(1) bit 8 CS1 R/W-0 R/W-0 ADDR6(1) R/W-0 ADDR5(1) R/W-0 ADDR4(1) R/W-0 ADDR3(1) R/W-0 ADDR2(1) R/W-0 ADDR1(1) R/W-0 ADDR0(1) bit 0 Unimplemented: Read as ‘0’ CS1: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive Unimplemented: Read as ‘0’ ADDR: Parallel Port Destination Address bits(1) PMA bits are not available on 28-pin devices. bit 13-11 bit 10-0 Note 1: REGISTER 19-4: U-0 — bit 15 R/W-0 PTEN7(1) bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 PMAEN: PARALLEL PORT ENABLE REGISTER U-0 — U-0 — U-0 — R/W-0 PTEN10(1) R/W-0 PTEN9(1) R/W-0 PTEN8(1) bit 8 R/W-0 PTEN14 R/W-0 PTEN6(1) R/W-0 PTEN5(1) R/W-0 PTEN4(1) R/W-0 PTEN3(1) R/W-0 PTEN2(1) R/W-0 PTEN1 R/W-0 PTEN0 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ PTEN14: PMCS1 Strobe Enable bit 1 = PMCS1 functions as chip select 0 = PMCS1 pin functions as port I/O Unimplemented: Read as ‘0’ PTEN: PMP Address Port Enable bits(1) 1 = PMA function as PMP address lines 0 = PMA function as port I/O PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL 0 = PMA1 and PMA0 pads function as port I/O PMA bits are not available on 28-pin devices. bit 13-11 bit 10-2 bit 1-0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 235 PIC24FJ64GB004 FAMILY REGISTER 19-5: R-0 IBF bit 15 R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Settable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0, HS OBUF U-0 — U-0 — R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0 PMSTAT: PARALLEL PORT STATUS REGISTER U-0 — U-0 — R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 8 R/W-0, HS IBOV IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register has occurred (must be cleared in software) 0 = No overflow has occurred Unimplemented: Read as ‘0’ IB3F:IB0F Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OB3E:OB0E Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 DS39940D-page 236  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 19-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 — PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PMPTTL bit 0 RTSECSEL1(1) RTSECSEL0(1) Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the setting of the Flash Configuration bit, RTCOSC (CW4)) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. bit 0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 237 PIC24FJ64GB004 FAMILY FIGURE 19-2: Master PMD PMCS1 PMRD PMWR LEGACY PARALLEL SLAVE PORT EXAMPLE PIC24F Slave PMD PMCS1 PMRD PMWR Address Bus Data Bus Control Lines FIGURE 19-3: Master PMA PMD ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE PMA PMD Write Address Decode PMDOUT1L (0) PIC24F Slave Read Address Decode PMDIN1L (0) PMDIN1H (1) PMDIN2L (2) PMDIN2H (3) PMCS1 PMRD PMWR Address Bus Data Bus Control Lines PMCS1 PMRD PMWR PMDOUT1H (1) PMDOUT2L (2) PMDOUT2H (3) TABLE 19-1: SLAVE MODE ADDRESS RESOLUTION Output Register (Buffer) PMDOUT1 (0) PMDOUT1 (1) PMDOUT2 (2) PMDOUT2 (3) Input Register (Buffer) PMDIN1 (0) PMDIN1 (1) PMDIN2 (2) PMDIN2 (3) PMA 00 01 10 11 FIGURE 19-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F PMA PMD PMCS1 PMRD Address Bus Data Bus Control Lines PMWR DS39940D-page 238  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY FIGURE 19-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F PMA PMD PMA PMCS1 PMALL PMRD PMWR Address Bus Multiplexed Data and Address Bus Control Lines FIGURE 19-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, SINGLE CHIP SELECT) PIC24F PMD PMA PMA PMCS1 PMALL PMALH PMRD PMWR Multiplexed Data and Address Bus Control Lines FIGURE 19-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION 373 A D A A D CE OE WR Address Bus Data Bus Control Lines PIC24F PMD PMALL PMALH PMCS1 PMRD PMWR 373 FIGURE 19-8: EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION 373 A D A A D CE OE WR Address Bus Data Bus Control Lines PIC24F PMD PMALL PMA PMCS1 PMRD PMWR  2010 Microchip Technology Inc. DS39940D-page 239 PIC24FJ64GB004 FAMILY FIGURE 19-9: PIC24F PMD PMALL PMCS1 PMRD PMWR EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION Parallel Peripheral AD ALE CS RD WR Address Bus Data Bus Control Lines FIGURE 19-10: PIC24F PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 8-BIT DATA) Parallel EEPROM A D CE OE WR Address Bus Data Bus Control Lines PMA PMD PMCS1 PMRD PMWR FIGURE 19-11: PIC24F PARALLEL EEPROM EXAMPLE (UP TO 11-BIT ADDRESS, 16-BIT DATA) Parallel EEPROM A D A0 CE OE WR Address Bus Data Bus Control Lines PMA PMD PMBE PMCS1 PMRD PMWR FIGURE 19-12: PIC24F LCD CONTROL EXAMPLE (BYTE MODE OPERATION) LCD Controller D RS PMD PMA0 PMRD/PMWR PMCS1 R/W E Address Bus Data Bus Control Lines DS39940D-page 240  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 20.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 29. “Real-Time Clock and Calendar (RTCC)” (DS39696). The RTCC provides the user with a Real-Time Clock and Calendar (RTCC) function that can be calibrated. Key features of the RTCC module are: • Operates in Deep Sleep mode • Selectable clock source • Provides hours, minutes and seconds using 24-hour format • Visibility of one half second period • Provides calendar – weekday, date, month and year • Alarm-configurable for half a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month or one year • Alarm repeat with decrementing counter • Alarm with indefinite repeat chime • Year 2000 to 2099 leap year correction • BCD format for smaller software overhead • Optimized for long-term battery operation • User calibration of the 32.768 kHz clock crystal/32K INTRC frequency with periodic auto-adjust 20.1 RTCC Source Clock The user can select between the SOSC crystal oscillator or the LPRC Low-Power Internal RC Oscillator as the clock reference for the RTCC module. This is configured using the RTCOSC (CW4) Configuration bit. This gives the user an option to trade off system cost, accuracy and power consumption, based on the overall system needs. The SOSC and RTCC will both remain running while the device is held in Reset with MCLR and will continue running after MCLR is released. FIGURE 20-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5 Sec RTCC Timer RTCVAL 1 Sec Comparator ALMTHDY ALWDHR ALMINSEC RTSECSEL 01 RTCC Interrupt Logic RTCC Interrupt Alarm Pulse 00 RTCC Pin Clock Source RTCOE 10 ALCFGRPT YEAR MTHDY WKDYHR MINSEC Input from SOSC/LPRC Oscillator Alarm Event Alarm Registers with Masks ALRMVAL Repeat Counter  2010 Microchip Technology Inc. DS39940D-page 241 PIC24FJ64GB004 FAMILY 20.2 RTCC Module Registers TABLE 20-2: ALRMPTR 00 01 10 11 The RTCC module registers are organized as three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL ALRMVAL ALRMMIN ALRMWD ALRMMNTH — ALRMSEC ALRMHR ALRMDAY — 20.2.1 REGISTER MAPPING To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired Timer register pair (see Table 20-1). By writing to the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrements by one until they reach ‘00’. After they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes, the ALRMPTR value will be decremented. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. Note: This only applies to read operations and not write operations. 20.2.2 WRITE LOCK TABLE 20-1: RTCPTR 00 01 10 11 RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL MINUTES WEEKDAY MONTH — RTCVAL SECONDS HOURS DAY YEAR In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL) must be set (refer to Example 20-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only one instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 20-1. The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 20-2). By writing to the ALRMVALH byte, the Alarm Pointer value, ALRMPTR bits, decrements by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. 20.2.3 SELECTING RTCC CLOCK SOURCE The clock source for the RTCC module can be selected using the Flash Configuration bit, RTCOSC (CW4). When the bit is set to ‘1’, the Secondary Oscillator (SOSC) is used as the reference clock, and when the bit is ‘0’, LPRC is used as the reference clock. EXAMPLE 20-1: asm asm asm asm asm asm asm asm asm asm SETTING THE RTCWREN BIT volatile(“push w7”); volatile(“push w8”); volatile(“disi #5”); volatile(“mov #0x55, w7”); volatile(“mov w7, _NVMKEY”); volatile(“mov #0xAA, w8”); volatile(“mov w8, _NVMKEY”); volatile(“bset _RCFGCAL, #13”); volatile(“pop w8”); volatile(“pop w7”); //set the RTCWREN bit DS39940D-page 242  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 20.2.4 RTCC CONTROL REGISTERS REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) R/W-0 RTCEN bit 15 R/W-0 CAL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CAL6 R/W-0 CAL5 R/W-0 CAL4 R/W-0 CAL3 R/W-0 CAL2 R/W-0 CAL1 (2) U-0 — R/W-0 RTCWREN R-0, HSC RTCSYNC R-0, HSC HALFSEC(3) R/W-0 RTCOE R/W-0 RTCPTR1 R/W-0 RTCPTR0 bit 8 R/W-0 CAL0 bit 0 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as ‘0’ RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output is enabled 0 = RTCC output is disabled RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading the RTCVALH and RTCVALL registers. The RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 Note 1: 2: 3:  2010 Microchip Technology Inc. DS39940D-page 243 PIC24FJ64GB004 FAMILY REGISTER 20-1: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) bit 7-0 CAL: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute . . . 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute . . . 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only; it is cleared to ‘0’ on a write to the lower half of the MINSEC register. Note 1: 2: 3: REGISTER 20-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-3 bit 2-1 PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 R/W-0 PMPTTL bit 0 RTSECSEL1(1) RTSECSEL0(1) W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bits(1) 11 = Reserved; do not use 10 = RTCC source clock is selected for the RTCC pin (clock can be LPRC or SOSC, depending on the setting of the RTCOSC bit (CW4)) 01 = RTCC seconds clock is selected for the RTCC pin 00 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE (RCFGCAL) bit needs to be set. bit 0 Note 1: DS39940D-page 244  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 20-3: R/W-0 ALRMEN bit 15 R/W-0 ARPT7 bit 7 ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 AMASK3 R/W-0 AMASK2 R/W-0 AMASK1 R/W-0 AMASK0 R/W-0 ALRMPTR1 R/W-0 ALRMPTR0 bit 8 R/W-0 ARPT0 bit 0 R/W-0 CHIME R/W-0 ARPT6 R/W-0 ARPT5 R/W-0 ARPT4 R/W-0 ARPT3 R/W-0 ARPT2 R/W-0 ARPT1 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 14 bit 13-10 bit 9-8 bit 7-0 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 00h and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT bits stop once they reach 00h AMASK: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved; do not use 11xx = Reserved; do not use ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading the ALRMVALH and ALRMVALL registers. The ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times . . . 00000000 = Alarm will not repeat The counter decrements on any alarm event; it is prevented from rolling over from 00h to FFh unless CHIME = 1.  2010 Microchip Technology Inc. DS39940D-page 245 PIC24FJ64GB004 FAMILY 20.2.5 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1) U-0, HSC — U-0, HSC — U-0, HSC — U-0, HSC — U-0, HSC — U-0, HSC — bit 8 R/W-x, HSC YRTEN2 R/W-x, HSC YRTEN1 R/W-x, HSC YRTEN0 R/W-x, HSC YRONE3 R/W-x, HSC YRONE2 R/W-x, HSC YRONE1 R/W-x, HSC YRONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown — REGISTER 20-4: U-0, HSC — bit 15 R/W-x, HSC YRTEN3 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 U-0, HSC Unimplemented: Read as ‘0’ YRTEN: Binary Coded Decimal Value of Year’s Tens Digit bits Contains a value from 0 to 9. YRONE: Binary Coded Decimal Value of Year’s Ones Digit bits Contains a value from 0 to 9. A write to the YEAR register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-5: U-0, HSC — bit 15 U-0, HSC — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0, HSC — R/W-x, HSC MTHTEN0 R/W-x, HSC MTHONE3 R/W-x, HSC MTHONE2 R/W-x, HSC MTHONE1 R/W-x, HSC MTHONE0 bit 8 — U-0, HSC U-0, HSC — R/W-x, HSC DAYTEN1 R/W-x, HSC DAYTEN0 R/W-x, HSC DAYONE3 R/W-x, HSC DAYONE2 R/W-x, HSC DAYONE1 R/W-x, HSC DAYONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: DS39940D-page 246  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 20-6: U-0, HSC — bit 15 U-0, HSC — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0, HSC — R/W-x, HSC HRTEN1 R/W-x, HSC HRTEN0 R/W-x, HSC HRONE3 R/W-x, HSC HRONE2 R/W-x, HSC HRONE1 WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0, HSC — U-0, HSC — U-0, HSC — R/W-x, HSC WDAY2 R/W-x, HSC WDAY1 R/W-x, HSC WDAY0 bit 8 R/W-x, HSC HRONE0 bit 0 — U-0, HSC Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. Note 1: REGISTER 20-7: U-0, HSC — bit 15 U-0, HSC — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 MINSEC: MINUTES AND SECONDS VALUE REGISTER R/W-x, HSC MINTEN1 R/W-x, HSC MINTEN0 R/W-x, HSC MINONE3 R/W-x, HSC MINONE2 R/W-x, HSC MINONE1 R/W-x, HSC MINONE0 bit 8 R/W-x, HSC MINTEN2 R/W-x, HSC SECTEN2 R/W-x, HSC SECTEN1 R/W-x, HSC SECTEN0 R/W-x, HSC SECONE3 R/W-x, HSC SECONE2 R/W-x, HSC SECONE1 R/W-x, HSC SECONE0 bit 0 HSC = Hardware Settable/Clearable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39940D-page 247 PIC24FJ64GB004 FAMILY 20.2.6 ALRMVAL REGISTER MAPPINGS ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 — U-0 — R/W-x MTHTEN0 R/W-x MTHONE3 R/W-x MTHONE2 R/W-x MTHONE1 R/W-x MTHONE0 bit 8 R/W-x DAYONE0 bit 0 REGISTER 20-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1: U-0 — R/W-x DAYTEN1 R/W-x DAYTEN0 R/W-x DAYONE3 R/W-x DAYONE2 R/W-x DAYONE1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit bit Contains a value of ‘0’ or ‘1’. MTHONE: Binary Coded Decimal Value of Month’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit bits Contains a value from 0 to 3. DAYONE: Binary Coded Decimal Value of Day’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. REGISTER 20-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 R/W-x HRONE0 bit 0 U-0 — R/W-x HRTEN1 R/W-x HRTEN0 R/W-x HRONE3 R/W-x HRONE2 R/W-x HRONE1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit bits Contains a value from 0 to 6. Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit bits Contains a value from 0 to 2. HRONE: Binary Coded Decimal Value of Hour’s Ones Digit bits Contains a value from 0 to 9. A write to this register is only allowed when RTCWREN = 1. DS39940D-page 248  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 20-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x SECTEN2 R/W-x SECTEN1 R/W-x SECTEN0 R/W-x SECONE3 R/W-x SECONE2 R/W-x SECONE1 R/W-x MINTEN2 R/W-x MINTEN1 R/W-x MINTEN0 R/W-x MINONE3 R/W-x MINONE2 R/W-x MINONE1 R/W-x MINONE0 bit 8 R/W-x SECONE0 bit 0 Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit bits Contains a value from 0 to 5. MINONE: Binary Coded Decimal Value of Minute’s Ones Digit bits Contains a value from 0 to 9. Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit bits Contains a value from 0 to 5. SECONE: Binary Coded Decimal Value of Second’s Ones Digit bits Contains a value from 0 to 9.  2010 Microchip Technology Inc. DS39940D-page 249 PIC24FJ64GB004 FAMILY 20.3 Calibration 20.4.1 CONFIGURING THE ALARM The real-time crystal input can be calibrated using the periodic auto-adjust feature. When calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will either be added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. 2. 3. Using another timer resource on the device; the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute. a) If the oscillator is faster than ideal (negative result from step 2), the RCFGCAL register value must be negative. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. b) If the oscillator is slower than ideal (positive result from step 2), the RCFGCAL register value must be positive. This causes the specified number of clock pulses to be subtracted from the timer counter, once every minute. The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. As displayed in Figure 20-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs, once the alarm is enabled, is stored in the ARPT bits (ALCFGRPT). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT with FFh. After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which, the ALRMEN bit will be cleared automatically and the alarm will turn off. Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. Divide the number of error clocks per minute by 4 to get the correct calibration value and load the RCFGCAL register with the correct value. (Each 1-bit increment in the calibration adds or subtracts 4 pulses.) 20.4.2 ALARM INTERRUPT EQUATION 20-1: (Ideal Frequency† – Measured Frequency) * 60 = Clocks per Minute † Ideal Frequency = 32,768 Hz Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off or immediately after the rising edge of the seconds pulse. Note: It is up to the user to include, in the error value, the initial error of the crystal drift due to temperature and drift due to crystal aging. At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. Note: Changing any of the registers, other than the RCFGCAL and ALCFGRPT registers, and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. 20.4 Alarm • Configurable from half second to one year • Enabled using the ALRMEN bit (ALCFGRPT) • One-time alarm and repeat alarm options are available DS39940D-page 250  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY FIGURE 20-2: ALARM MASK SETTINGS Day of the Week Alarm Mask Setting (AMASK) 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds 0011 - Every minute 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week 1000 - Every month 1001 - Every year(1) s m m m s s s s s s Month Day Hours Minutes Seconds h d d m m d d d h h h h h h h m m m m m m m m s s s s s s s s Note 1: Annually, except when configured for February 29.  2010 Microchip Technology Inc. DS39940D-page 251 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 252  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 21.0 32-BIT PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 41. “32-Bit Programmable Cyclic Redundancy Check (CRC)” (DS39729). The programmable CRC generator provides a hardware-implemented method of quickly generating checksums for various networking and security applications. It offers the following features: • User-programmable CRC polynomial equation, up to 32 bits • Programmable shift direction (little or big-endian) • Independent data and polynomial lengths • Configurable Interrupt output • Data FIFO A simplified block diagram of the CRC generator is shown in Figure 21-1. A simple version of the CRC shift engine is shown in Figure 21-2. Note: FIGURE 21-1: CRC BLOCK DIAGRAM CRCDATH CRCDATL Variable FIFO (4x32, 8x16 or 16x8) FIFO Empty Event CRCISEL 2 * FCY Shift Clock Shift Buffer 1 0 0 1 LENDIAN Set CRCIF CRC Shift Engine Shift Complete Event CRCWDATH CRCWDATL FIGURE 21-2: CRC SHIFT ENGINE DETAIL CRCWDATH CRCWDATL Read/Write Bus X(1)(1) Shift Buffer Data X(2)(1) X(n)(1) Bit 0 Bit 1 Bit 2 Bit n(2) Note 1: 2: Each XOR stage of the shift engine is programmable. See text for details. Polynomial length n is determined by ([PLEN] + 1).  2010 Microchip Technology Inc. DS39940D-page 253 PIC24FJ64GB004 FAMILY 21.1 21.1.1 User Interface POLYNOMIAL INTERFACE The CRC module can be programmed for CRC polynomials of up to the 32nd order, using up to 32 bits. Polynomial length, which reflects the highest exponent in the equation, is selected by the PLEN bits (CRCCON2). The CRCXORL and CRCXORH registers control which exponent terms are included in the equation. Setting a particular bit includes that exponent term in the equation; functionally, this includes an XOR operation on the corresponding bit in the CRC engine. Clearing the bit disables the XOR. For example, consider two CRC polynomials, one a 16-bit equation and the other a 32-bit equation: x16 + x12 + x5 + 1 and x32 + x26 + x23 + x22 + x16 + x12 + x11 + x10 + x8 + x7 + x5 + x4 + x2 + x + 1 To program these polynomials into the CRC generator, set the register bits as shown in Table 21-1. Note that the appropriate positions are set to ‘1’ to indicate that they are used in the equation (for example, X26 and X23). The 0 bit required by the equation is always XORed; thus, X0 is a don’t care. For a polynomial of length N, it is assumed that the Nth bit will always be used, regardless of the bit setting. Therefore, for a polynomial length of 32, there is no 32nd bit in the CRCxOR register. The data for which the CRC is to be calculated must first be written into the FIFO. Even if the data width is less than 8, the smallest data element that can be written into the FIFO is one byte. For example, if the DWIDTH value is five, then the size of the data is DWIDTH + 1, or six. The data is written as a whole byte; the two unused upper bits are ignored by the module. Once data is written into the MSb of the CRCDAT registers (that is, MSb as defined by the data width), the value of the VWORD bits (CRCCON1) increments by one. For example, if the DWIDTH value is 24, the VWORD bits will increment when bit 7 of CRCDATH is written. Therefore, CRCDATL must always be written before CRCDATH. The CRC engine starts shifting data when the CRCGO bit is set and the value of VWORD is greater than zero. Each word is copied out of the FIFO into a buffer register, which decrements VWORD. The data is then shifted out of the buffer. The CRC engine continues shifting at a rate of two bits per instruction cycle, until the VWORD value reaches zero. This means that for a given data width, it takes half that number of instructions for each word to complete the calculation. For example, it takes 16 cycles to calculate the CRC for a single word of 32-bit data. When the VWORD value reaches the maximum value for the configured value of DWIDTH (4, 8 or 16), the CRCFUL bit becomes set. When the VWORD value reaches zero, the CRCMPT bit becomes set. The FIFO is emptied and VWORD are set to ‘00000’ whenever CRCEN is ‘0’. At least one instruction cycle must pass, after a write to CRCDAT, before a read of the VWORD bits is done. 21.1.2 DATA INTERFACE The module incorporates a FIFO that works with a variable data width. Input data width can be configured to any value between one and 32 bits using the DWIDTH bits (CRCCON2). When the data width is greater than 15, the FIFO is four words deep. When the DWIDTH value is between 15 and 8, the FIFO is 8 words deep. When the DWIDTH value is less than 8, the FIFO is 16 words deep. TABLE 21-1: CRC Control Bits PLEN X X CRC SETUP EXAMPLES FOR 16 AND 32-BIT POLYNOMIAL Bit Values 16-Bit Polynomial 01111 0000 0000 0000 000x 0001 0000 0010 000x 32-Bit Polynomial 11111 0000 0100 1100 0001 0001 1101 1011 011x DS39940D-page 254  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 21.1.3 DATA SHIFT DIRECTION 21.2 • • • • • • • • Registers The LENDIAN bit (CRCCON1) is used to control the shift direction. By default, the CRC will shift data through the engine, MSb first. Setting LENDIAN (= 1) causes the CRC to shift data, LSb first. This setting allows better integration with various communication schemes and removes the overhead of reversing the bit order in software. Note that this only changes the direction of the data that is shifted into the engine. The result of the CRC calculation will still be a normal CRC result, not a reverse CRC result. There are eight registers associated with the module: CRCCON1 CRCCON2 CRCXORL CRCXORH CRCDATL CRCDATH CRCWDATL CRCWDATH 21.1.4 INTERRUPT OPERATION The module generates an interrupt that is configurable by the user for either of two conditions. If CRCISEL is ‘0’, an interrupt is generated when the VWORD bits make a transition from a value of ‘1’ to ‘0’. If CRCISEL is ‘1’, an interrupt will be generated after the CRC operation finishes and the module sets the CRCGO bit to ‘0’. Manually setting CRCGO to ‘0’ will not generate an interrupt. The CRCCON1 and CRCCON2 registers (Register 21-1 and Register 21-2) control the operation of the module and configure the various settings. The CRCXOR registers (Register 21-3 and Register 21-4) select the polynomial terms to be used in the CRC equation. The CRCDAT and CRCWDAT registers are each register pairs that serve as buffers for the double-word, input data and CRC processed output, respectively. 21.1.5 1. 2. TYPICAL OPERATION To use the module for a typical CRC calculation: Set the CRCEN bit to enable the module. Configure the module for the desired operation: a) Program the desired polynomial using the CRCXORL and CRCXORH registers, and the PLEN bits b) Configure the data width and shift direction using the DWIDTH and LENDIAN bits c) Select the desired interrupt mode using the CRCISEL bit Preload the FIFO by writing to the CRCDATL and CRCDATH registers until the CRCFUL bit is set or no data is left Clear old results by writing 00h to CRCWDATL and CRCWDATH. CRCWDAT can also be left unchanged to resume a previously halted calculation. Set the CRCGO bit to start calculation. Write remaining data into the FIFO as space becomes available. When the calculation completes, CRCGO is automatically cleared. An interrupt will be generated if CRCISEL = 1. Read CRCWDATL and CRCWDATH for the result of the calculation. 3. 4. 5. 6. 7. 8.  2010 Microchip Technology Inc. DS39940D-page 255 PIC24FJ64GB004 FAMILY REGISTER 21-1: R/W-0 CRCEN bit 15 R-0, HCS CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HC = Hardware Clearable bit W = Writable bit ‘1’ = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R-1, HCS CRCMPT R/W-0 CRCISEL R/W-0, HC CRCGO R/W-0 LENDIAN U-0 — U-0 — — CRCCON1: CRC CONTROL REGISTER 1 U-0 R/W-0 CSIDL R-0 VWORD4 R-0 VWORD3 R-0 VWORD2 R-0 VWORD1 R-0 VWORD0 bit 8 U-0 — bit 0 CRCEN: CRC Enable bit 1 = Module is enabled 0 = Module is enabled. All state machines, pointers and CRCWDAT/CRCDAT are reset; other SFRs are NOT reset Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN > 7 or 16 when PLEN 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty CRCISEL: CRC interrupt Selection bit 1 = Interrupt on FIFO is empty; CRC calculation is not complete 0 = Interrupt on shift is complete and CRCWDAT result is ready CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter is turned off LENDIAN: Data Shift Direction Select bit 1 = Data word is shifted into the CRC starting with the LSb (little endian) 0 = Data word is shifted into the CRC starting with the MSb (big endian) Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 DS39940D-page 256  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 21-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12-8 bit 7-5 bit 4-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 PLEN4 R/W-0 PLEN3 R/W-0 PLEN2 R/W-0 PLEN1 CRCCON2: CRC CONTROL REGISTER 2 U-0 — U-0 — R/W-0 DWIDTH4 R/W-0 DWIDTH3 R/W-0 DWIDTH2 R/W-0 DWIDTH1 R/W-0 DWIDTH0 bit 8 R/W-0 PLEN0 bit 0 Unimplemented: Read as ‘0’ DWIDTH: Data Width Select bits Defines the width of the data word (Data Word Width = (DWIDTH) + 1). Unimplemented: Read as ‘0’ PLEN: Polynomial Length Select bits Defines the length of the CRC polynomial (Polynomial Length = (PLEN) + 1). REGISTER 21-3: R/W-0 X15 bit 15 R/W-0 X7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 CRCXORL: CRC XOR POLYNOMIAL REGISTER, LOW BYTE R/W-0 X13 R/W-0 X12 R/W-0 X11 R/W-0 X10 R/W-0 X9 R/W-0 X8 bit 8 X14 R/W-0 R/W-0 X6 R/W-0 X5 R/W-0 X4 R/W-0 X3 R/W-0 X2 R/W-0 X1 U-0 — bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown X: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as ‘0’  2010 Microchip Technology Inc. DS39940D-page 257 PIC24FJ64GB004 FAMILY REGISTER 21-4: R/W-0 X31 bit 15 R/W-0 X23 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 X22 R/W-0 X21 R/W-0 X20 R/W-0 X19 R/W-0 X18 R/W-0 X17 CRCXORH: CRC XOR POLYNOMIAL REGISTER, HIGH BYTE R/W-0 X29 R/W-0 X28 R/W-0 X27 R/W-0 X26 R/W-0 X25 R/W-0 X24 bit 8 R/W-0 X16 bit 0 X30 R/W-0 X: XOR of Polynomial Term Xn Enable bits DS39940D-page 258  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 22.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 17. “10-Bit A/D Converter” (DS39705). A block diagram of the A/D Converter is shown in Figure 22-1. To perform an A/D conversion: 1. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFGL and AD1PCFGH). b) Select voltage reference source to match expected range on analog inputs (AD1CON2). c) Select the analog conversion clock to match the desired data rate with the processor clock (AD1CON3). d) Select the appropriate sample/conversion sequence (AD1CON1 and AD1CON3). e) Select how conversion results are presented in the buffer (AD1CON1). f) Select interrupt rate (AD1CON2). g) Turn on A/D module (AD1CON1). Configure the A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. The 10-bit A/D Converter has the following key features: • • • • • • • • • • • Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 13 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. On all PIC24FJ64GB004 family devices, the 10-bit A/D Converter has 13 analog input pins, designated AN0 through AN12. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins.  2010 Microchip Technology Inc. DS39940D-page 259 PIC24FJ64GB004 FAMILY FIGURE 22-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVDD AVSS VREF+ VREFVINH AN0 AN1 AN2 AN3 MUX A AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 VDDCORE VBG/2 VBG Sample Control Input MUX Control Pin Config Control VRS/H VR+ VR Select VR+ 16 VRComparator VINL DAC VINH 10-Bit SAR Conversion Logic Data Formatting VINL ADC1BUF0: ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS0 MUX B VINH AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH VINL Control Logic Conversion Control DS39940D-page 260  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 22-1: R/W-0 ADON(1) bit 15 R/W-0 SSRC2 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 C = Clearable bit W = Writable bit ‘1’ = Bit is set HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 SSRC1 R/W-0 SSRC0 U-0 — U-0 — R/W-0 ASAM R/W-0, HCS SAMP AD1CON1: A/D CONTROL REGISTER 1 U-0 — R/W-0 ADSIDL U-0 — U-0 — U-0 — R/W-0 FORM1 R/W-0 FORM0 bit 8 R/C-0, HCS DONE bit 0 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off Unimplemented: Read as ‘0’ ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ FORM: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) SSRC: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = CTMU event ends sampling and starts conversion 101 = Reserved 100 = Timer5 compare ends sampling and starts conversion 011 = Reserved 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing the SAMP bit ends sampling and starts conversion Unimplemented: Read as ‘0’ ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after the last conversion completes; SAMP bit is auto-set 0 = Sampling begins when the SAMP bit is set SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. bit 14 bit 13 bit 12-10 bit 9-8 bit 7-5 bit 4-3 bit 2 bit 1 bit 0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 261 PIC24FJ64GB004 FAMILY REGISTER 22-2: R/W-0 VCFG2 bit 15 R-0 BUFS bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-0 SMPI3 R/W-0 SMPI2 R/W-0 SMPI1 R/W-0 SMPI0 R/W-0 BUFM AD1CON2: A/D CONTROL REGISTER 2 R/W-0 VCFG0 r-0 r U-0 — R/W-0 CSCNA U-0 — U-0 — bit 8 R/W-0 ALTS bit 0 R/W-0 VCFG1 VCFG: Voltage Reference Configuration bits VCFG 000 001 010 011 1xx VR+ AVDD External VREF+ pin AVDD External VREF+ pin AVDD VRAVSS AVSS External VREF- pin External VREF- pin AVSS bit 12 bit 11 bit 10 Reserved: Maintain as ‘0’ Unimplemented: Read as ‘0’ CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F; user should access data in 00-07 0 = A/D is currently filling buffer 00-07; user should access data in 08-0F Unimplemented: Read as ‘0’ SMPI: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts are at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts are at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts are at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts are at the completion of conversion for each sample/convert sequence BUFM: Buffer Mode Select bit 1 = Buffer is configured as two 8-word buffers (ADC1BUFn and ADC1BUFn) 0 = Buffer is configured as one 16-word buffer (ADC1BUFn) ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings bit 9-8 bit 7 bit 6 bit 5-2 bit 1 bit 0 DS39940D-page 262  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 22-3: R/W-0 ADRC bit 15 R/W-0 ADCS7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 r = Reserved bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 ADCS6 R/W-0 ADCS5 R/W-0 ADCS4 R/W-0 ADCS3 R/W-0 ADCS2 R/W-0 ADCS1 r AD1CON3: A/D CONTROL REGISTER 3 r-0 r-0 r R/W-0 SAMC4 R/W-0 SAMC3 R/W-0 SAMC2 R/W-0 SAMC1 R/W-0 SAMC0 bit 8 R/W-0 ADCS0 bit 0 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock Reserved: Maintain as ‘0’ SAMC: Auto-Sample Time bits 11111 = 31 TAD ····· 00001 = 1 TAD 00000 = 0 TAD (not recommended) ADCS: A/D Conversion Clock Select bits 11111111 to 01000000 = Reserved ······ 00111111 = 64 • TCY ······ 00000001 = 2 • TCY 00000000 = TCY bit 14-13 bit 12-8 bit 7-0  2010 Microchip Technology Inc. DS39940D-page 263 PIC24FJ64GB004 FAMILY REGISTER 22-4: R/W-0 CH0NB bit 15 R/W-0 CH0NA bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — R/W-0 CH0SA4 R/W-0 CH0SA3 R/W-0 CH0SA2 R/W-0 CH0SA1 AD1CHS: A/D INPUT SELECT REGISTER U-0 — U-0 — R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 CH0SA0 bit 0 CH0SB4(1,2) CH0SB3(1,2) CH0SB2(1,2) CH0SB1(1,2) CH0SB0(1,2) CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SB: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1,2) 11111 = Channel 0 positive input is reserved for CTMU use only(3) 1xxxx = Unimplemented; do not use. 01111 = Channel 0 positive input is internal band gap reference (VBG) 01110 = Channel 0 positive input is VBG/2 01101 = Channel 0 positive input is voltage regulator output (VDDCORE) 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 01010 = Channel 0 positive input is AN10 01001 = Channel 0 positive input is AN9 01000 = Channel 0 positive input is AN8 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Channel 0 positive input is AN5 00100 = Channel 0 positive input is AN4 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VRUnimplemented: Read as ‘0’ CH0SA: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Implemented combinations are identical to those for CH0SB (above). Combinations not shown here are unimplemented; do not use. Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; do not use. Selecting this internal channel allows the CTMU module to utilize the A/D Converter sample and hold capacitor (CAD) for the smallest time measurements. bit 14-13 bit 12-8 bit 7 bit 6-5 bit 4-0 Note 1: 2: 3: DS39940D-page 264  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 22-5: R/W-0 PCFG15 bit 15 R/W-0(1) PCFG7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) PCFG6 R/W-0 PCFG5 R/W-0 PCFG4 R/W-0 PCFG3 R/W-0 PCFG2 R/W-0 PCFG1 AD1PCFG: A/D PORT CONFIGURATION REGISTER R/W-0 PCFG13 R/W-0(1) PCFG12 R/W-0 PCFG11 R/W-0 PCFG10 R/W-0 PCFG9 R/W-0(1) PCFG8 bit 8 R/W-0 PCFG0 bit 0 R/W-0 PCFG14 PCFG15: A/D Input Band Gap Reference Enable bit 1 = Internal band gap (VBG) reference channel is disabled 0 = Internal band gap reference channel is enabled PCFG14: A/D Input Half Band Gap Reference Enable bit 1 = Internal half band gap (VBG/2) reference channel is disabled 0 = Internal half band gap reference channel is enabled PCFG13: A/D Input Voltage Regulator Output Reference Enable bit 1 = Internal voltage regulator output (VDDCORE) reference channel is disabled 0 = Internal voltage regulator output reference channel is enabled PCFG: Analog Input Pin Configuration Control bits(1) 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read is enabled 0 = Pin is configured in Analog mode; I/O port read is disabled, A/D samples pin voltage Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding bits set. bit 14 bit 13 bit 12-0 Note 1:  2010 Microchip Technology Inc. DS39940D-page 265 PIC24FJ64GB004 FAMILY REGISTER 22-6: R/W-0 CSSL15 bit 15 R/W-0 CSSL7 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CSSL6 R/W-0 CSSL5 R/W-0 CSSL4 R/W-0 CSSL3 R/W-0 CSSL2 R/W-0 CSSL1 AD1CSSL: A/D INPUT SCAN SELECT REGISTER R/W-0 CSSL13 R/W-0(1) CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8(1) bit 8 R/W-0 CSSL0 bit 0 R/W-0 CSSL14 CSSL15: A/D Input Band Gap Scan Enable bit 1 = Internal band gap (VBG) channel is enabled for input scan 0 = Analog channel is disabled from input scan CSSL14: A/D Input Half Band Gap Scan Enable bit 1 = Internal half band gap (VBG/2) channel is enabled for input scan 0 = Analog channel is disabled from input scan CSSL13: A/D Input Voltage Regulator Output Scan Enable bit 1 = Internal voltage regulator output (VDDCORE) is enabled for input scan 0 = Analog channel is disabled from input scan CSSL: A/D Input Pin Scan Selection bits(1) 1 = Corresponding analog channel is selected for input scan 0 = Analog channel is omitted from input scan Analog channels, AN6, AN7, AN8 and AN12, are unavailable on 28-pin devices; leave these corresponding bits cleared. bit 14 bit 13 bit 12-0 Note 1: DS39940D-page 266  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY EQUATION 22-1: A/D CONVERSION CLOCK PERIOD(1) ADCS = TAD –1 TCY TAD = TCY • (ADCS + 1) Note 1: Based on TCY = 2 * TOSC, Doze mode and PLL are disabled. FIGURE 22-2: 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD ANx VT = 0.6V RIC  250 Sampling Switch RSS CHOLD = ADC capacitance = 4.4 pF (Typical) VSS RSS  5 k(Typical) Rs VA CPIN 6-11 pF (Typical) VT = 0.6V ILEAKAGE 500 nA Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. The effect of CPIN is negligible if Rs  5 k.  2010 Microchip Technology Inc. DS39940D-page 267 PIC24FJ64GB004 FAMILY FIGURE 22-3: Output Code (Binary (Decimal)) A/D TRANSFER FUNCTION 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) 00 0000 0000 (0) 1023*(VR+ – VR-) 512*(VR+ – VR-) (VINH – VINL) VR+ – VRVR+ 1024 0 VR- 1024 Voltage Level VR- + VR- + 1024 DS39940D-page 268  2010 Microchip Technology Inc. VR- + PIC24FJ64GB004 FAMILY 23.0 Note: TRIPLE COMPARATOR MODULE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 46. “Scalable Comparator Module” (DS39734). The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals ‘1’, the I/O pad logic makes the unsynchronized output of the comparator available on the pin. A simplified block diagram of the module in shown in Figure 23-1. Diagrams of the possible individual comparator configurations are shown in Figure 23-2. Each comparator has its own control register, CMxCON (Register 23-1), for enabling and configuring its operation. The output and event status of all three comparators are provided in the CMSTAT register (Register 23-2). The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs, as well as voltage reference inputs from the voltage reference generator and band gap reference. FIGURE 23-1: CCH CREF TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL Trigger/Interrupt Logic CEVT COE CPOL VINCXINB CXINC CXIND CVREFVIN+ Input Select Logic C1 COUT C1OUT Pin EVPOL Trigger/Interrupt Logic CEVT COE CPOL VINVIN+ C2 COUT C2OUT Pin CXINA CVREF+ VINVIN+ C3 EVPOL Trigger/Interrupt Logic CEVT COE CPOL COUT C3OUT Pin  2010 Microchip Technology Inc. DS39940D-page 269 PIC24FJ64GB004 FAMILY FIGURE 23-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CEN = 0, CREF = x, CCH = xx VINVIN+ COE Cx Off (Read as ‘0’) CxOUT Pin Comparator CxINB > CxINA Compare CEN = 1, CREF = 0, CCH = 00 CXINB CXINA VINVIN+ COE Comparator CxINC > CxINA Compare CEN = 1, CREF = 0, CCH = 01 CXINC CxOUT Pin VINVIN+ COE Cx CXINA Cx CxOUT Pin Comparator CxIND > CxINA Compare CEN = 1, CREF = 0, CCH = 10 CXIND CXINA VINVIN+ COE Comparator CVREF- > CxINA Compare CEN = 1, CREF = 0, CCH = 11 CVREFCxOUT Pin VINVIN+ COE Cx CXINA Cx CxOUT Pin Comparator CxINB > CVREF+ Compare CEN = 1, CREF = 1, CCH = 00 CXINB CVREF+ VINVIN+ COE Comparator CxINC > CVREF+ Compare CEN = 1, CREF = 1, CCH = 01 CXINC CxOUT Pin VINVIN+ COE Cx CVREF+ Cx CxOUT Pin Comparator CxIND > CVREF+ Compare CEN = 1, CREF = 1, CCH = 10 CXIND CVREF+ VINVIN+ COE Comparator CVREF- > CVREF+ Compare CEN = 1, CREF = 1, CCH = 11 CVREFCxOUT Pin VINVIN+ COE Cx CVREF+ Cx CxOUT Pin DS39940D-page 270  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 23-1: R/W-0 CEN bit 15 R/W-0 EVPOL1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EVPOL0 U-0 — R/W-0 CREF U-0 — U-0 — R/W-0 CCH1 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 CPOL U-0 — U-0 — U-0 — R/W-0 CEVT R-0 COUT bit 8 R/W-0 CCH0 bit 0 COE R/W-0 CEN: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted Unimplemented: Read as ‘0’ CEVT: Comparator Event bit 1 = Comparator event defined by EVPOL has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VINEVPOL: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7-6 bit 5  2010 Microchip Technology Inc. DS39940D-page 271 PIC24FJ64GB004 FAMILY REGISTER 23-1: bit 4 CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF+ input reference voltage 0 = Non-inverting input connects to CxINA pin Unimplemented: Read as ‘0’ CCH: Comparator Channel Select bits 11 = Inverting input of comparator connects to CVREF- input reference voltage 10 = Inverting input of comparator connects to CxIND pin 01 = Inverting input of comparator connects to CxINC pin 00 = Inverting input of comparator connects to CxINB pin bit 3-2 bit 1-0 REGISTER 23-2: R/W-0 CMIDL bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 CMSTAT: COMPARATOR MODULE STATUS REGISTER U-0 — U-0 — U-0 — U-0 — R-0 C3EVT R-0 C2EVT R-0 C1EVT bit 8 U-0 — U-0 — U-0 — U-0 — R-0 C3OUT R-0 C2OUT R-0 C1OUT bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode Unimplemented: Read as ‘0’ C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON). C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON). C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON). Unimplemented: Read as ‘0’ C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON). C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON). C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON). bit 14-11 bit 10 bit 9 bit 8 bit 7-3 bit 2 bit 1 bit 0 DS39940D-page 272  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 24.0 Note: COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the “PIC24F Family Reference Manual”, Section 20. “Comparator Voltage Reference Module” (DS39709). voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. 24.1 Configuring the Comparator Voltage Reference The voltage reference module is controlled through the CVRCON register (Register 24-1). The comparator voltage reference provides two ranges of output FIGURE 24-1: VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSS = 0 8R R R R CVR CVREFP CVREN VREF+ 1 CVREF+ 16 Steps 16-to-1 MUX R 0 CVREF R R R CVRR VREFCVRSS = 1 CVROE CVREFM 8R VREF+ VBG/6 11 10 01 00 CVREF- CVRSS = 0 AVSS VBG VBG/2  2010 Microchip Technology Inc. DS39940D-page 273 PIC24FJ64GB004 FAMILY REGISTER 24-1: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 CVR3 R/W-0 CVR2 R/W-0 CVR1 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — R/W-0 CVREFP R/W-0 CVREFM1 R/W-0 CVREFM0 bit 8 R/W-0 CVR0 bit 0 Unimplemented: Read as ‘0’ CVREFP: CVREF+ Reference Output Select bit 1 = Use VREF+ input pin as CVREF+ reference output to comparators 0 = Use comparator voltage reference module’s generated output as CVREF+ reference output to comparators CVREFM: CVREF- Reference Output Select bits 11 = Use VREF+ input pin as CVREF- reference output to comparators 10 = Use VBG/6 as CVREF- reference output to comparators 01 = Use VBG as CVREF- reference output to comparators 00 = Use VBG/2 as CVREF- reference output to comparators CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit is powered on 0 = CVREF circuit is powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source, CVRSRC = VREF+ – VREF0 = Comparator reference source, CVRSRC = AVDD – AVSS CVR: Comparator VREF Value Selection (0  CVR  15) bits When CVRR = 1: CVREF = (CVR/24)  (CVRSRC) When CVRR = 0: CVREF = 1/4  (CVRSRC) + (CVR/32)  (CVRSRC) bit 9-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 DS39940D-page 274  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 25.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated “PIC24F Family Reference Manual”, Section 11. “Charge Time Measurement Unit (CTMU)” (DS39724). 25.1 Measuring Capacitance The CTMU module measures capacitance by generating an output pulse, with a width equal to the time between edge events, on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module’s precision current source to calculate capacitance according to the relationship: i=C• dV dT The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: • • • • • • Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output’s pulse. A Precision Resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Figure 25-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers: CTMUCON and CTMUICON. CTMUCON enables the module and controls edge source selection, edge source polarity selection and edge sequencing. The CTMUICON register controls the selection and trim of the current source. FIGURE 25-1: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 EDG2 Output Pulse A/D Converter Current Source ANx ANY CAPP RPR  2010 Microchip Technology Inc. DS39940D-page 275 PIC24FJ64GB004 FAMILY 25.2 Measuring Time 25.3 Pulse Generation and Delay Time measurements on the pulse width can be similarly performed using the A/D module’s internal capacitor (CAD) and a precision resistor for current calibration. Figure 25-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. For the smallest time measurements, select the internal A/D Channel 31, CH0S = 11111. This minimizes any stray capacitance that may otherwise be associated with using an input pin, thus keeping the total capacitance to that of the A/D Converter itself (4-5 pF). A detailed discussion on measuring capacitance and time with the CTMU module is provided in the “PIC24F Family Reference Manual”. The CTMU module can also generate an output pulse with edges that are not synchronous with the device’s system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Figure 25-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the “PIC24F Family Reference Manual”. FIGURE 25-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT PIC24F Device CTMU CTEDG1 CTEDG2 EDG1 EDG2 Output Pulse ANx RPR A/D Converter CAD Current Source FIGURE 25-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB CDELAY CVREF C2 DS39940D-page 276  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 25-1: R/W-0 CTMUEN bit 15 R/W-0 EDG2POL bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 EDG2SEL1 R/W-0 EDG2SEL0 R/W-0 EDG1POL R/W-0 EDG1SEL1 R/W-0 EDG1SEL0 R/W-0 EDG2STAT CTMUCON: CTMU CONTROL REGISTER U-0 — R/W-0 CTMUSIDL R/W-0 TGEN (1) R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN R/W-0 CTTRIG bit 8 R/W-0 EDG1STAT bit 0 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as ‘0’ CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response EDG2SEL: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6-5 bit 4 Note 1:  2010 Microchip Technology Inc. DS39940D-page 277 PIC24FJ64GB004 FAMILY REGISTER 25-1: bit 3-2 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1SEL: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred If TGEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. For more information, see Section 10.4 “Peripheral Pin Select (PPS)”. bit 1 bit 0 Note 1: REGISTER 25-2: R/W-0 ITRIM5 bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-10 CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 ITRIM3 R/W-0 ITRIM2 R/W-0 ITRIM1 R/W-0 ITRIM0 R/W-0 IRNG1 R/W-0 IRNG0 bit 8 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 0 R/W-0 ITRIM4 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current IRNG: Current Source Range Select bits 11 = 100  Base Current 10 = 10  Base Current 01 = Base current level (0.55 A nominal) 00 = Current source disabled Unimplemented: Read as ‘0’ bit 9-8 bit 7-0 DS39940D-page 278  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 26.0 Note: SPECIAL FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the “PIC24F Family Reference Manual”: • Section 9. “Watchdog Timer (WDT)” (DS39697) • Section 32. “High-Level Device Integration” (DS39719) • Section 33. “Programming and Diagnostics” (DS39716) 26.1.1 CONSIDERATIONS FOR CONFIGURING PIC24FJ64GB004 FAMILY DEVICES PIC24FJ64GB004 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: • • • • • • Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation In PIC24FJ64GB004 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 26-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. The upper byte of all Flash Configuration Words in program memory should always be ‘1111 1111’. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing ‘1’s to these locations has no effect on device operation. Note: Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. 26.1 Configuration Bits The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 26-1 through Register 26-6. Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 26-1: FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ64GB004 FAMILY DEVICES Configuration Word Addresses 1 57FEh ABFEh 2 57FCh ABFCh 3 57FAh ABFAh 4 57F8h ABF8h Device PIC24FJ32GB00X PIC24FJ64GB00X  2010 Microchip Technology Inc. DS39940D-page 279 PIC24FJ64GB004 FAMILY REGISTER 26-1: U-1 — bit 23 r-x r bit 15 R/PO-1 FWDTEN bit 7 Legend: R = Readable bit r = Reserved bit PO = Program Once bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared R/PO-1 WINDIS U-1 — R/PO-1 FWPSA R/PO-1 WDTPS3 R/PO-1 WDTPS2 R/PO-1 WDTPS1 R/PO-1 JTAGEN(1) R/PO-1 GCP R/PO-1 GWRP R/PO-1 DEBUG U-1 — R/PO-1 ICS1 CW1: FLASH CONFIGURATION WORD 1 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 ICS0 bit 8 R/PO-1 WDTPS0 bit 0 -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 Unimplemented: Read as ‘1’ Reserved: The value is unknown; program as ‘0’ JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode Unimplemented: Read as ‘1’ ICS: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer is enabled 0 = Windowed Watchdog Timer is enabled; FWDTEN must be ‘1’ Unimplemented: Read as ‘1’ FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while connected through the JTAG interface. bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5 bit 4 Note 1: DS39940D-page 280  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 26-1: bit 3-0 CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial Programming™ (ICSP™). It cannot be modified while connected through the JTAG interface. Note 1:  2010 Microchip Technology Inc. DS39940D-page 281 PIC24FJ64GB004 FAMILY REGISTER 26-2: U-1 — bit 23 R/PO-1 IESO bit 15 R/PO-1 FCKSM1 bit 7 CW2: FLASH CONFIGURATION WORD 2 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 FNOSC0 bit 8 R/PO-1 POSCMD0 bit 0 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 R/PO-1 PLL96MHZ R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY U-1 — R/PO-1 I2C1SEL R/PO-1 POSCMD1 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 Unimplemented: Read as ‘1’ IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) is enabled 0 = IESO mode (Two-Speed Start-up) is disabled PLLDIV: USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 8 (32 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) 100 = Oscillator input divided by 5 (20 MHz input) 011 = Oscillator input divided by 4 (16 MHz input) 010 = Oscillator input divided by 3 (12 MHz input) 001 = Oscillator input divided by 2 (8 MHz input) 000 = Oscillator input used directly (4 MHz input) PLL96MHZ: USB 96 MHz PLL Start-up Enable bit 1 = 96 MHz PLL is enabled automatically on start-up 0 = 96 MHz PLL is enabled by user in software (controlled with the PLLEN bit in CLKDIV) FNOSC: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD = 11 or 00: 1 = OSCO/CLKO/RA3 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RA3 functions as port I/O (RC15) If POSCMD = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RA3. DS39940D-page 282  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 26-2: bit 4 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) bit 3 bit 2 bit 1-0 IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON) can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed Unimplemented: Read as ‘1’ I2C1SEL: I2C1 Pin Select bit 1 = Use default SCL1/SDA1 pins 0 = Use alternate SCL1/SDA1 pins POSCMD: Primary Oscillator Configuration bits 11 = Primary Oscillator is disabled 10 = HS Oscillator mode is selected 01 = XT Oscillator mode is selected 00 = EC Oscillator mode is selected  2010 Microchip Technology Inc. DS39940D-page 283 PIC24FJ64GB004 FAMILY REGISTER 26-3: U-1 — bit 23 R/PO-1 WPEND bit 15 U-1 — bit 7 Legend: R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed bit 23-16 bit 15 CW3: FLASH CONFIGURATION WORD 3 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 R/PO-1 WPCFG R/PO-1 WPDIS U-1 — R/PO-1 WUTSEL1 R/PO-1 WUTSEL0 R/PO-1 R/PO-1 (1) SOSCSEL0(1) SOSCSEL1 bit 8 R/PO-1 WPFP1 R/PO-1 WPFP0 bit 0 U-1 — R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared bit 14 bit 13 bit 12 bit 11-10 bit 9-8 bit 7-6 bit 5-0 Unimplemented: Read as ‘1’ WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code-protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection is disabled 0 = Segmented code protection is enabled; protected segment is defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as ‘1’ WUTSEL: Voltage Regulator Standby Mode Wake-up Time Select bits 11 = Default regulator start-up time is used 01 = Fast regulator start-up time is used x0 = Reserved; do not use SOSCSEL: Secondary Oscillator Power Mode Select bits(1) 11 = SOSC pins are in default (high drive strength) oscillator mode 01 = SOSC pins are in Low-Power (low drive strength) Oscillator mode 00 = SOSC pins have digital I/O functions (RA4, RB4); SCLKI can be used 10 = Reserved Unimplemented: Read as ‘1’ WPFP: Protected Code Segment Boundary Page bits Designates the 512 instruction page that is the boundary of the protected code segment, starting with Page 9 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = 0: First address of designated code page is the lower boundary of the segment. Digital functions on the SOSCI and SOSCO pins are only available when configured in Digital I/O mode (‘00’). Note 1: DS39940D-page 284  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY REGISTER 26-4: U-1 — bit 23 U-1 — bit 15 R/PO-1 DSWDTEN bit 7 Legend: R = Readable bit PO = Program Once bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared -n = Value when device is unprogrammed bit 23-8 bit 7 Unimplemented: Read as ‘1’ DSWDTEN: Deep Sleep Watchdog Timer Enable bit 1 = DSWDT is enabled 0 = DSWDT is disabled DSBOREN: Deep Sleep BOR Enable bit 1 = BOR is enabled in Deep Sleep 0 = BOR is disabled in Deep Sleep (does not affect Sleep mode) RTCOSC: RTCC Reference Clock Select bit 1 = RTCC uses SOSC as reference clock 0 = RTCC uses LPRC as reference clock DSWDTOSC: DSWDT Reference Clock Select bit 1 = DSWDT uses LPRC as reference clock 0 = DSWDT uses SOSC as reference clock DSWDTPS: DSWDT Postscale select bits The DSWDT prescaler is 32; this creates an approximate base time unit of 1 ms. 1111 = 1:2,147,483,648 (25.7 days) 1110 = 1:536,870,912 (6.4 days) 1101 = 1:134,217,728 (38.5 hours) 1100 = 1:33,554,432 (9.6 hours) 1011 = 1:8,388,608 (2.4 hours) 1010 = 1:2,097,152 (36 minutes) 1001 = 1:524,288 (9 minutes) 1000 = 1:131,072 (135 seconds) 0111 = 1:32,768 (34 seconds) 0110 = 1:8,192 (8.5 seconds) 0101 = 1:2,048 (2.1 seconds) 0100 = 1:512 (528 ms) 0011 = 1:128 (132 ms) 0010 = 1:32 (33 ms) 0001 = 1:8 (8.3 ms) 0000 = 1:2 (2.1 ms) R/PO-1 DSBOREN R/PO-1 RTCOSC R/PO-1 R/PO-1 R/PO-1 R/PO-1 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — CW4: FLASH CONFIGURATION WORD 4 U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — U-1 — bit 16 U-1 — bit 8 R/PO-1 bit 0 DSWDTOSC DSWDTPS3 DSWDTPS2 DSWDTPS1 DSWDTPS0 bit 6 bit 5 bit 4 bit 3-0  2010 Microchip Technology Inc. DS39940D-page 285 PIC24FJ64GB004 FAMILY REGISTER 26-5: U — bit 23 R FAMID7 bit 15 R DEV7 bit 7 DEVID: DEVICE ID REGISTER U — U — U — U — U — U — U — bit 16 R FAMID0 bit 8 R DEV0 bit 0 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 R FAMID1 R DEV6 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 Legend: R = Read-Only bit bit 23-16 bit 15-8 bit 7-0 Unimplemented: Read as ‘1’ FAMID: Device Family Identifier bits 01000010 = PIC24FJ64GB004 family DEV: Individual Device Identifier bits 00000011 = PIC24FJ32GB002 00000111 = PIC24FJ64GB002 00001011 = PIC24FJ32GB004 00001111 = PIC24FJ64GB004 U = Unimplemented bit REGISTER 26-6: U — bit 23 U — bit 15 U — bit 7 DEVREV: DEVICE REVISION REGISTER U — U — U — U — U — U — U — bit 16 U — bit 8 U — U — U — R REV3 R REV2 R REV1 R REV0 bit 0 U — U — U — U — U — U — Legend: R = Read-only bit bit 23-4 bit 3-0 U = Unimplemented bit Unimplemented: Read as ‘0’ REV: Minor Revision Identifier bits Encodes revision number of the device (sequential number only; no major/minor fields). DS39940D-page 286  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 26.2 On-Chip Voltage Regulator FIGURE 26-1: All PIC24FJ64GB004 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ64GB004 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator is controlled by the DISVREG pin. Tying VSS to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 26-1). This helps to maintain the stability of the regulator. The recommended value for the Filter Capacitor (CEFC) is provided in Section 29.1 “DC Characteristics”. If DISVREG is tied to VDD, the regulator is disabled. In this case, separate power for the core logic, at a nominal 2.5V, must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 26-1 for possible configurations. CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V PIC24FJ64GB004 VDD DISVREG VDDCORE/VCAP Regulator Enabled (DISVREG tied to VSS): CEFC (10 F typ) VSS Regulator Disabled (DISVREG tied to VDD): 2.5V(1) 3.3V(1) PIC24FJ64GB004 VDD DISVREG VDDCORE/VCAP VSS 26.2.1 VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ64GB004 VDD DISVREG VDDCORE/VCAP VSS When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. The regulator can provide this level from a VDD of about 2.5V, all the way up to the device’s VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent “brown-out” conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4). This can be used to generate an interrupt and put the application into a Low-Power Operational mode or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled. Note 1: These are typical operating voltages. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD and VDDCORE. 26.2.2 ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 10 s for it to generate output. During this time, designated as TPM, code execution is disabled. TPM is applied every time the device resumes operation after any power-down, including Sleep mode. TPM is determined by the setting of the PMSLP bit (RCON) and the WUTSEL Configuration bits (CW3). Note: For more information on TPM, see Section 29.0 “Electrical Characteristics”. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up (POR or BOR only).  2010 Microchip Technology Inc. DS39940D-page 287 PIC24FJ64GB004 FAMILY When waking up from Sleep mode with the regulator disabled, TPM is used to determine the wake-up time. To decrease the device wake-up time when operating with the regulator disabled, the PMSLP bit can be set. 26.3 Watchdog Timer (WDT) For PIC24FJ64GB004 family devices, the WDT is driven by the LPRC Oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS Configuration bits (CW1), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler time-out periods, ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 26.2.3 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ64GB004 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage specifications are provided in Section 29.0 “Electrical Characteristics”. 26.2.4 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: For more information, see Section 29.0 “Electrical Characteristics”. 26.2.5 VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically places itself into Standby mode whenever the device goes into Sleep mode by removing power from the Flash program memory. This feature is controlled by the PMSLP bit (RCON). By default, this bit is cleared, which enables Standby mode. For PIC24FJ64GB004 family devices, the time required for regulator wake-up from Standby mode is controlled by the WUTSEL Configuration bits (CW3). The default wake-up time for all devices is 190 s, which is a Legacy mode provided to match older PIC24F device wake-up times. Implementing the WUTSEL Configuration bits provides a fast wake-up option. When WUTSEL = 01, the regulator wake-up time is TPM, 10 s. When the regulator’s Standby mode is turned off (PMSLP = 1), Flash program memory stays powered in Sleep mode. That enables device wake-up without waiting for TPM. With PMSLP set, however, the power consumption, while in Sleep mode, will be approximately 40 A higher than what it would be if the regulator was allowed to enter Standby mode. DS39940D-page 288  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 26.3.1 WINDOWED OPERATION 26.3.2 CONTROL REGISTER The Watchdog Timer has an optional Fixed Window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction is executed before that window causes a WDT Reset; this is similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1) to ‘0’. The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The WDT software option allows the user to enable the WDT for critical code segments, and disable the WDT during non-critical segments, for maximum power savings. FIGURE 26-2: SWDTEN FWDTEN WDT BLOCK DIAGRAM LPRC Control FWPSA Prescaler (5-bit/7-bit) 31 kHz 1 ms/4 ms WDT Counter WDTPS Postscaler 1:1 to 1:32.768 WDT Overflow Reset Wake From Sleep LPRC Input All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode 26.4 Deep Sleep Watchdog Timer (DSWDT) 26.5 Program Verification and Code Protection PIC24FJ64GB004 family devices have both a WDT module and a DSWDT module. The latter runs, if enabled, when a device is in Deep Sleep and is driven by either the SOSC or LPRC Oscillator. The clock source is selected by the DSWDTOSC (CW4) Configuration bit. The DSWDT can be configured to generate a time-out at 2.1 ms to 25.7 days by selecting the respective postscaler. The postscaler can be selected by the Configuration bits, DSWDTPS (CW4). When the DSWDT is enabled, the clock source is also enabled. DSWDT is one of the sources that can wake the device from Deep Sleep mode. PIC24FJ64GB004 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 26.5.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ64GB004 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to ‘0’, internal write and erase operations to program memory are blocked.  2010 Microchip Technology Inc. DS39940D-page 289 PIC24FJ64GB004 FAMILY 26.5.2 CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of erase and write-protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in the PIC24FJ64GB004 family devices can be located by the user anywhere in the program space and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock, whenever a write or erase address falls within a specified range. It does not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page, regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. The various options for segment code protection are shown in Table 26-2. 26.5.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes, or reads in two ways. The primary protection method is the same as that of the RP registers – shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting. TABLE 26-2: WPDIS 1 1 0 SEGMENT CODE PROTECTION CONFIGURATION OPTIONS WPCFG 1 0 0 Write/Erase Protection of Code Segment No additional protection enabled; all program memory protection is configured by GCP and GWRP Last code page protected, including Flash Configuration Words Addresses from the first address of code page, defined by WPFP through the end of implemented program memory (inclusive), are protected, including Flash Configuration Words Address, 000000h, through the last address of code page, defined by WPFP (inclusive) is protected Addresses from first address of code page, defined by WPFP through the end of implemented program memory (inclusive), are protected, including Flash Configuration Words Addresses from first address of code page, defined by WPFP through the end of implemented program memory (inclusive), are protected Segment Configuration Bits WPEND x x 1 0 0 0 1 0 1 0 0 1 DS39940D-page 290  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 26.6 JTAG Interface 26.8 In-Circuit Debugger PIC24FJ64GB004 family devices implement a JTAG interface, which supports boundary scan device testing. When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. 26.7 In-Circuit Serial Programming PIC24FJ64GB004 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx), and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.  2010 Microchip Technology Inc. DS39940D-page 291 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 292  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 27.0 DEVELOPMENT SUPPORT 27.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power.  2010 Microchip Technology Inc. DS39940D-page 293 PIC24FJ64GB004 FAMILY 27.2 MPLAB C Compilers for Various Device Families 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS39940D-page 294  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 27.7 MPLAB SIM Software Simulator 27.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.8 MPLAB REAL ICE In-Circuit Emulator System 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ-11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables.  2010 Microchip Technology Inc. DS39940D-page 295 PIC24FJ64GB004 FAMILY 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS39940D-page 296  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 28.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand, which is a register ‘Wb’ without any address modifier • The second source operand, which is a literal value • The destination of the result (only if not the same as the first source operand), which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. The PIC24F instruction set adds many enhancements to the previous PIC® MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 28-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 28-2 lists all of the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand, which is typically a register ‘Wb’ without any address modifier • The second source operand, which is typically a register ‘Ws’ with or without an address modifier • The destination of the result, which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value, ‘f’ • The destination, which could either be the file register, ‘f’, or the W0 register, which is denoted as ‘WREG’ Most bit-oriented instructions (including rotate/shift instructions) have two operands: simple • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register, ‘Wb’)  2010 Microchip Technology Inc. DS39940D-page 297 PIC24FJ64GB004 FAMILY TABLE 28-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double-Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address {0000h...1FFFh} 1-bit unsigned literal {0,1} 4-bit unsigned literal {0...15} 5-bit unsigned literal {0...31} 8-bit unsigned literal {0...255} 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal {0...16383} 16-bit unsigned literal {0...65535} 23-bit unsigned literal {0...8388607}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal {-512...511} 16-bit signed literal {-32768...32767} 6-bit signed literal {-16...16} Base W register {W0..W15} Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register  { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) One of 16 working registers {W0..W15} One of 16 destination working registers {W0..W15} One of 16 source working registers {W0..W15} W0 (working register used in file register instructions) Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS39940D-page 298  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 28-2: Assembly Mnemonic ADD ADD ADD ADD ADD ADD ADDC ADDC ADDC ADDC ADDC ADDC AND AND AND AND AND AND ASR ASR ASR ASR ASR ASR BCLR BCLR BCLR BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BSET BSET BSET BSW BSW.C BSW.Z BTG BTG BTG BTSC BTSC BTSC f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NOV,Expr NZ,Expr OV,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 INSTRUCTION SET OVERVIEW Assembly Syntax f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if Greater than or Equal Branch if Unsigned Greater than or Equal Branch if Greater than Branch if Unsigned Greater than Branch if Less than or Equal Branch if Unsigned Less than or Equal Branch if Less than Branch if Unsigned Less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Overflow Branch if Not Zero Branch if Overflow Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Description # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 Status Flags Affected C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None None None None None None None None None None None None None None None None None None None None None None None None None 1 None (2 or 3) 1 None (2 or 3)  2010 Microchip Technology Inc. DS39940D-page 299 PIC24FJ64GB004 FAMILY TABLE 28-2: Assembly Mnemonic BTSS BTSS BTSS BTST BTST BTST.C BTST.Z BTST.C BTST.Z BTSTS BTSTS BTSTS.C BTSTS.Z CALL CALL CALL CLR CLR CLR CLR CLRWDT COM CLRWDT COM COM COM CP CP CP CP CP0 CP0 CP0 CPB CPB CPB CPB CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW.B DEC DEC DEC DEC2 DEC2 DEC2 DEC2 DISI DIV DISI DIV.SW DIV.SD DIV.UW DIV.UD EXCH FF1L FF1R EXCH FF1L FF1R f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb,Wn Wb,Wn Wb,Wn Wb,Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Description Bit Test f, Skip if Set Bit Test Ws, Skip if Set Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call Subroutine Call Indirect Subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, Skip if = Compare Wb with Wn, Skip if > Compare Wb with Wn, Skip if < Compare Wb with Wn, Skip if  Wn = Decimal Adjust Wn f=f–1 WREG = f – 1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k Instruction Cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find First One from Left (MSb) Side Find First One from Right (LSb) Side # of Words 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles Status Flags Affected 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Z C Z C Z Z C Z None None None None None WDTO, Sleep N, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 None (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 C C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None N, Z, C, OV N, Z, C, OV N, Z, C, OV N, Z, C, OV None C C DS39940D-page 300  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 28-2: Assembly Mnemonic GOTO GOTO GOTO INC INC INC INC INC2 INC2 INC2 INC2 IOR IOR IOR IOR IOR IOR LNK LSR LNK LSR LSR LSR LSR LSR MOV MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV MOV.D MOV.D MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL NEG NEG NEG NEG NOP NOP NOPR POP POP POP POP.D POP.S PUSH PUSH PUSH PUSH.D PUSH.S f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Expr Wn f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn [Wns+Slit10],Wnd f f,WREG #lit16,Wn #lit8,Wn Wn,f Wns,[Wns+Slit10] Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd Go to Address Go to Indirect f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move [Wns + Slit10] to Wnd Move f to f Move f to WREG Move 16-bit Literal to Wn Move 8-bit Literal to Wn Move Wn to f Move Wns to [Wns + Slit10] Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns + 1) to Wd Move Double from Ws to W(nd + 1):W(nd) {Wnd + 1, Wnd} = Signed(Wb) * Signed(Ws) {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(Ws) {Wnd + 1, Wnd} = Unsigned(Wb) * Signed(Ws) {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(Ws) {Wnd + 1, Wnd} = Signed(Wb) * Unsigned(lit5) {Wnd + 1, Wnd} = Unsigned(Wb) * Unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns + 1) to Top-of-Stack (TOS) Push Shadow Registers Description # of Words 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 None N, Z None None None None None None None None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None None None None All None None None None Status Flags Affected None None C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z N, Z N, Z N, Z N, Z N, Z None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z None None N, Z N, Z None None None  2010 Microchip Technology Inc. DS39940D-page 301 PIC24FJ64GB004 FAMILY TABLE 28-2: Assembly Mnemonic PWRSAV RCALL PWRSAV RCALL RCALL REPEAT REPEAT REPEAT RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC RLNC RLNC RLNC RLNC RRC RRC RRC RRC RRNC RRNC RRNC RRNC SE SETM SE SETM SETM SETM SL SL SL SL SL SL SUB SUB SUB SUB SUB SUB SUBB SUBB SUBB SUBB SUBB SUBB SUBR SUBR SUBR SUBR SUBR SUBBR SUBBR SUBBR SUBBR SUBBR SWAP SWAP.b SWAP f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit1 Expr Wn #lit14 Wn Description Go into Sleep or Idle mode Relative Call Computed Call Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software Device Reset Return from Interrupt Return with Literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = Sign-Extended Ws f = FFFFh WREG = FFFFh Ws = FFFFh f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = Nibble Swap Wn Wn = Byte Swap Wn # of Words 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 1 2 2 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected WDTO, Sleep None None None None None None None None C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z C, N, Z C, N, Z N, Z N, Z N, Z C, N, Z None None None C, N, OV, Z C, N, OV, Z C, N, OV, Z N, Z N, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z C, DC, N, OV, Z None None DS39940D-page 302  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 28-2: Assembly Mnemonic TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR TBLRDH TBLRDL TBLWTH TBLWTL ULNK XOR XOR XOR XOR XOR ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Ws,Wd Ws,Wd Ws,Wd Ws,Wd Description Read Prog to Wd Read Prog to Wd Write Ws to Prog Write Ws to Prog Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-Extend Ws # of Words 1 1 1 1 1 1 1 1 1 1 1 # of Cycles 2 2 2 2 1 1 1 1 1 1 1 Status Flags Affected None None None None None N, Z N, Z N, Z N, Z N, Z C, Z, N  2010 Microchip Technology Inc. DS39940D-page 303 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 304  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ64GB004 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ64GB004 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(†) Ambient temperature under bias.............................................................................................................-40°C to +135°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin, and MCLR, with respect to VSS ........................ -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1) ................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1) ....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 29-1). NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.  2010 Microchip Technology Inc. DS39940D-page 305 PIC24FJ64GB004 FAMILY 29.1 DC Characteristics PIC24FJ64GB004 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V 2.75V Voltage (VDDCORE)(1) 2.50V 2.35V 2.00V PIC24FJ64GB004 Family 2.35V 2.75V FIGURE 29-1: 16 MHz Frequency 32 MHz For frequencies between 16 MHz and 32 MHz, FMAX = (45.7 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD 3.6V. FIGURE 29-2: PIC24FJ64GB004 FAMILY VOLTAGE-FREQUENCY GRAPH (EXTENDED TEMPERATURE) 3.00V 2.75V (VDDCORE)(1) 2.50V 2.25V 2.00V PIC24FJ64GB004 Family 2.75V 2.35V Voltage 16 MHz Frequency 24 MHz For frequencies between 16 MHz and 24 MHz, FMAX = (22.9 MHz/V) * (VDDCORE – 2V) + 16 MHz. Note 1: WHEN the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCOREVDD 3.6V. DS39940D-page 306  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-1: THERMAL OPERATING CONDITIONS Rating PIC24FJ64GB004 Family: Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD –  IOH) I/O Pin Power Dissipation: PI/O =  ({VDD – VOH} x IOH) +  (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W TJ TA -40 -40 — — +140 +125 °C °C Symbol Min Typ Max Unit PD PINT + PI/O W TABLE 29-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol JA JA JA JA Typ 49 33.7 28 39.3 Max — — — — Unit °C/W °C/W °C/W °C/W Notes (Note 1) (Note 1) (Note 1) (Note 1) Package Thermal Resistance, 300 mil SOIC Package Thermal Resistance, 6x6x0.9 mm QFN Package Thermal Resistance, 8x8x1 mm QFN Package Thermal Resistance, 10x10x1 mm TQFP Note 1: Junction to ambient thermal resistance; Theta-JA (JA) numbers are achieved by package simulations.  2010 Microchip Technology Inc. DS39940D-page 307 PIC24FJ64GB004 FAMILY TABLE 29-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 Supply Voltage VDD VDD VDDCORE DC12 DC16 VDR VPOR RAM Data Retention Voltage(2) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal Brown-out Reset Voltage 2.2 VDDCORE 2.0 1.5 VSS — — — — — 3.6 3.6 2.75 — — V V V V V Regulator enabled Regulator disabled Regulator disabled Characteristic DC17 SVDD 0.05 — — V/ms 0-3.3V in 0.1s 0-2.5V in 60 ms DC18 VBOR — 2.05 — V Note 1: 2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. DS39940D-page 308  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC21 DC21a DC21b DC21f DC21c DC21d DC21e DC21g DC20 DC20a DC20b DC20c DC20d DC20e DC20f DC20g DC23 DC23a DC23b DC23c DC23d DC23e DC23f DC23g Note 1: 2: Typical(1) Operating Current (IDD)(2) 0.24 0.25 0.25 0.3 0.44 0.41 0.41 0.6 0.5 0.5 0.5 0.6 0.75 0.75 0.75 1.0 2.0 2.0 2.0 2.4 2.9 2.9 2.9 3.5 0.395 0.395 0.395 0.395 0.78 0.78 0.78 0.78 0.75 0.75 0.75 0.75 1.4 1.4 1.4 1.4 3.0 3.0 3.0 3.0 4.2 4.2 4.2 4.2 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 0.5 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.  2010 Microchip Technology Inc. DS39940D-page 309 PIC24FJ64GB004 FAMILY TABLE 29-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC24 DC24a DC24b DC24c DC24d DC24e DC24f DC24g DC31 DC31a DC31b DC31c DC31d DC31e DC31f DC31g Note 1: 2: Typical(1) Operating Current (IDD)(2) 10.5 10.5 10.5 11.3 11.3 11.3 11.3 11.3 15.0 15.0 20.0 42.0 57.0 57.0 95.0 114.0 15.5 15.5 15.5 15.5 15.5 15.5 15.5 15.5 18.0 19.0 36.0 55.0 120.0 125.0 160.0 180.0 mA mA mA mA mA mA mA mA A A A A A A A A -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.5V(3) 16 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39940D-page 310  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC41 DC41a DC41b DC41f DC41c DC41d DC41e DC41g DC40 DC40a DC40b DC40c DC40d DC40e DC40f DC40g DC43 DC43a DC43b DC43c DC43d DC43e DC43f DC43g DC47 DC47a DC47b DC47f DC47c DC47d DC47e DC47g Note 1: 2: Typical(1) Idle Current (IIDLE)(2) 67 68 74 102 166 167 177 225 125 125 125 167 210 210 210 305 0.5 0.5 0.5 0.54 0.75 0.75 0.75 0.80 2.6 2.6 2.6 2.7 2.9 2.9 2.9 3.0 100 100 100 120 265 265 265 285 180 180 180 200 350 350 350 370 0.6 0.6 0.6 0.62 0.95 0.95 0.95 0.97 3.3 3.3 3.3 3.3 3.5 3.5 3.5 3.6 A A A A A A A A A A A A A A A A mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 0.5 MIPS 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled.  2010 Microchip Technology Inc. DS39940D-page 311 PIC24FJ64GB004 FAMILY TABLE 29-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC50 DC50a DC50b DC50c DC50d DC50e DC50f DC50g DC51 DC51a DC51b DC51c DC51d DC51e DC51f DC51g Note 1: 2: Typical(1) Idle Current (IIDLE)(2) 0.8 0.8 0.8 0.9 1.1 1.1 1.1 1.2 2.4 2.2 7.2 35 38 44 70 96 1.0 1.0 1.0 1.1 1.3 1.3 1.3 1.4 8.0 8.0 21 50 55 60 100 150 mA mA mA mA mA mA mA mA A A A A A A A A -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C -40°C +25°C +85°C +125C 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) 2.0V(3) FRC (4 MIPS) 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39940D-page 312  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-6: DC CHARACTERISTICS: POWER-DOWN BASE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC60 DC60a DC60i DC60b DC60m DC60c DC60d DC60j DC60e DC60n DC60f DC60g DC60k DC60h DC60p DC70c DC70d DC70j DC70e DC70a DC70f DC70g DC70k DC70h DC70b Note 1: 2: Typical(1) Power-Down Current (IPD)(2) 0.05 0.2 2.0 3.5 29.9 0.1 0.4 2.5 4.2 36.2 3.3 3.3 5.0 7.0 39.2 0.003 0.02 0.2 0.51 6.1 0.01 0.04 0.2 0.71 7.2 1.0 1.0 6.5 12 50 1.0 1.0 15 25 75 9.0 10 20 30 80 0.2 0.2 0.35 1.5 12 0.3 0.3 0.5 2.0 16 A A A A A A A A A A A A A A A A A A A A A A A A A -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C 3.3V(4) Base Deep Sleep Current 2.5V(4) 3.3V(4) 2.5V(3) Base Power-Down Current(5) 2.0V(3) 3: 4: 5: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, PMSLP bit is clear and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2010 Microchip Technology Inc. DS39940D-page 313 PIC24FJ64GB004 FAMILY TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC61 DC61a DC61i DC61b DC61m DC61c DC61d DC61j DC61e DC61p DC61f DC61g DC61k DC61h DC61n DC62 DC62a DC62i DC62b DC62m DC62c DC62d DC62j DC62e DC62n DC62f DC62g DC62k DC62h DC62p Note 1: 2: Typical(1)  Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) 0.2 0.2 0.2 0.23 0.3 0.25 0.25 0.25 0.28 0.5 0.6 0.6 0.6 0.8 1.0 0.5 0.5 0.5 0.5 0.6 0.7 0.7 0.7 0.7 0.8 1.5 1.5 1.5 1.5 1.9 0.7 0.7 0.7 0.7 1.0 0.9 0.9 0.9 0.9 1.2 1.5 1.5 1.5 1.5 1.7 1.0 1.0 1.0 1.3 1.6 1.5 1.5 1.5 1.8 2.1 2.0 2.0 2.0 2.5 3.0 A A A A A A A A A A A A A A A A A A A A A A A A A A A A A A -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C 3.3V(4) 2.5V (3) 2.0V(3) 2.5V(3) 31 kHz LPRC Oscillator with RTCC, WDT, DSWDT or Timer 1: ILPRC(5) 3.3V(4) 2.0V(3) Low drive strength, 32 kHz Crystal with RTCC, DSWDT or Timer1: ISOSC; SOSCSEL = 01(5) 3: 4: 5: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled. PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39940D-page 314  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN PERIPHERAL MODULE CURRENT (IPD) (CONTINUED) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. DC63 DC63a DC63i DC63b DC63m DC63c DC63d DC63j DC63e DC63n DC63f DC63g DC63k DC63h DC63p DC71c DC71d DC71j DC71e DC71a DC71f DC71g DC71k DC71h DC71b Note 1: 2: Typical(1)  Power-Down Current (IPD): PMD Bits are Set, PMSLP Bit is ‘0’(2) 1.8 1.8 1.8 1.8 2.2 2 2 2 2 2.5 2.25 2.25 2.25 2.25 2.8 0.001 0.03 0.05 0.08 3.9 0.001 0.03 0.05 0.08 3.9 2.3 2.7 3.0 3.0 3.3 2.7 2.9 3.2 3.5 3.8 3.0 3.0 3.3 3.5 4.0 0.25 0.25 0.60 2.0 10 0.50 0.50 0.75 2.5 12.5 A A A A A A A A A A A A A A A A A A A A A A A A A -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C -40°C +25°C +60°C +85°C +125C 3.3V(4) Deep Sleep BOR: IDSBOR(5) 2.5V(4) 3.3V(4) 2.5V(3) 32 kHz Crystal with RTCC, DSWDT or Timer1: ISOSC; SOSCSEL = 11(5) 2.0V(3) 3: 4: 5: Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Peripheral IPD deltas are measured with the device in Sleep mode (all peripherals and clocks shut down). All I/Os are configured as inputs and pulled high. Only the peripheral or clock being measured is enabled. PMSLP bit is clear and the Peripheral Module Disable bits (PMD) for all unused peripherals are set. On-chip voltage regulator disabled (DISVREG tied to VDD). On-chip voltage regulator enabled (DISVREG tied to VSS). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The  current is the additional current consumed when the module is enabled. This current should be added to the base IPD current.  2010 Microchip Technology Inc. DS39940D-page 315 PIC24FJ64GB004 FAMILY TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DI10 DI11 DI15 DI16 DI17 DI18 DI19 VIH DI20 Sym VIL Characteristic Input Low Voltage(4) I/O Pins with ST Buffer I/O Pins with TTL Buffer MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2C™ Buffer: I/O Pins with SMBus Buffer: Input High Voltage(4) I/O Pins with ST Buffer: with Analog Functions, Digital Only I/O Pins with TTL Buffer: with Analog Functions, Digital Only MCLR OSC1 (XT mode) OSC1 (HS mode) I/O Pins with I2C Buffer: with Analog Functions, Digital Only I/O Pins with SMBus Buffer: with Analog Functions, Digital Only VSS VSS VSS VSS VSS VSS VSS — — — — — — — 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 V V V V V V V SMBus enabled 0.8 VDD 0.8 VDD 0.25 VDD + 0.8 0.25 VDD + 0.8 0.8 VDD 0.7 VDD 0.7 VDD 0.7 VDD 0.7 VDD 2.1 2.1 50 — — — — — — — — — — — — — — VDD 5.5 VDD 5.5 VDD VDD VDD VDD 5.5 VDD 5.5 V V V V V V V V V 2.5V  VPIN  VDD V V A nA nA nA nA nA VDD = 3.3V, VPIN = VSS VSS  VPIN  VDD, Pin at high-impedance VSS  VPIN  VDD, Pin at high-impedance VUSB  VDD VSS VPIN VDD VSS VPIN VDD, XT and HS modes DI21 DI25 DI26 DI27 DI28 DI29 DI30 DI50 DI51 DI52 DI55 DI56 Note 1: 2: ICNPU CNx Pull-up Current IIL Input Leakage I/O Ports Analog Input Pins USB Differential Pins (D+, D-) MCLR OSC1 Current(2,3) 250 — — — — — 400 +50 +50 +50 +50 +50 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-2 for I/O pins buffer types. DS39940D-page 316  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param No. DO10 DO16 Sym VOL Characteristic Output Low Voltage I/O Ports I/O Ports — — — — — — — — 0.4 0.4 0.4 0.4 V V V V IOL = 8.5 mA, VDD = 3.6V IOL = 5.0 mA, VDD = 2.0V IOL = 8.0 mA, VDD = 3.6V, 125°C IOL = 4.5 mA, VDD = 2.0V, 125°C VOH DO20 Output High Voltage I/O Ports 3.0 2.4 1.65 1.4 — — — — — — — — — — — — V V V V V V IOH = -3.0 mA, VDD = 3.6V IOH = -6.0 mA, VDD = 3.6V IOH = -1.0 mA, VDD = 2.0V IOH = -3.0 mA, VDD = 2.0V IOH = -2.5 mA, VDD = 3.6V, 125°C IOH = -0.5 mA, VDD = 2.0V, 125°C DO26 I/O Ports 3.0 1.65 Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-10: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Param No. D130 D131 Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic Cell Endurance VDD for Read Min 10,000 VMIN Typ(1) — — Max — 3.6 Units E/W V Conditions -40C to +85C VMIN = Minimum operating voltage Sym EP VPR VPEW Supply Voltage for Self-Timed Writes D132A D132B D133A D133B D134 D135 Note 1: TIW TIE VDDCORE VDD Self-Timed Write Cycle Time Self-Timed Page Erase Time 2.25 2.35 — 40 20 — — — 3 — — 7 3.6 3.6 — — — — V V ms ms Year mA Provided no other specifications are violated TRETD Characteristic Retention IDDP Supply Current during Programming Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39940D-page 317 PIC24FJ64GB004 FAMILY TABLE 29-11: COMPARATOR SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. D300 D301 D302 300 301 * Note 1: Symbol VIOFF VICM CMRR TRESP TMC2OV Characteristic Input Offset Voltage* Input Common Mode Voltage* Common Mode Rejection Ratio* Response Time*(1) Comparator Mode Change to Output Valid* Min — 0 55 — — Typ 20 — — 150 — Max 40 VDD — 400 10 Units mV V dB ns s Comments Parameters are characterized but not tested. Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. TABLE 29-12: COMPARATOR VOLTAGE REFERENCE SPECIFICATIONS Operating Conditions: 2.0V < VDD < 3.6V, -40°C < TA < +85°C (unless otherwise stated) Param No. Symbol Characteristic Resolution Absolute Accuracy Unit Resistor Value (R) Settling Time(1) Min VDD/24 — — — Typ — — 2k — Max VDD/32 AVDD – 1.5 — 10 Units LSb LSb  s Comments VRD310 CVRES VRD311 CVRAA VRD312 CVRUR VR310 Note 1: TSET Settling time measured while CVRR = 1 and CVR bits transition from ‘0000’ to ‘1111’. TABLE 29-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40°C < TA < +85°C (unless otherwise stated) Param Symbol No. VBG TBG VRGOUT CEFC Characteristics Band Gap Reference Voltage Band Gap Reference Start-up Time Regulator Output Voltage External Filter Capacitor Value Min 1.14 — 2.35 4.7 Typ 1.2 1 2.5 10 Max 1.26 — 2.75 — Unit s V ms V F Series resistance < 3 Ohm recommended; < 5 Ohm required. Comments DS39940D-page 318  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY 29.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ64GB004 family AC characteristics and timing parameters. TABLE 29-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC AC CHARACTERISTICS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial and -40°C  TA  +125°C for Extended Operating voltage VDD range as described in Section 29.1 “DC Characteristics”. FIGURE 29-3: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSCO Load Condition 1 – for all pins except OSCO VDD/2 RL Pin VSS CL Pin VSS CL RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output TABLE 29-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSCO/CLKO Pin Min — Typ(1) — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSCI. EC mode. In I2C™ mode. DO56 DO58 Note 1: CIO CB All I/O Pins and OSCO SCLx, SDAx — — — — 50 400 pF pF Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested.  2010 Microchip Technology Inc. DS39940D-page 319 PIC24FJ64GB004 FAMILY FIGURE 29-4: Q4 EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS40 OS41 TABLE 29-16: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min DC 4 DC 4 3 3 10 31 3 10 — 62.5 0.45 x TOSC — — — Typ(1) — — — — — — — — — — — — — — 6 6 Max 32 8 24 6 10 8 32 33 6 24 — DC — 20 10 10 Units MHz MHz MHz MHz MHz MHz MHz kHz MHz MHz — ns ns ns ns ns EC EC Conditions EC, -40°C  TA  +85°C ECPLL, -40°C  TA  +85°C EC, -40°C  TA  +125°C ECPLL, -40°C  TA  +125°C XT XTPLL, -40°C  TA  +85°C HS, -40°C  TA  +85°C SOSC XTPLL, -40°C  TA  +125°C HS, -40°C  TA  +125°C See parameter OS10 for FOSC value FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency OS20 OS25 OS30 OS31 OS40 OS41 TOSC TOSC = 1/FOSC TCY Instruction Cycle Time(2) TosL, External Clock in (OSCI) TosH High or Low Time TosR, External Clock in (OSCI) TosF Rise or Fall Time TckR TckF CLKO Rise Time(3) CLKO Fall Time(3) Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “Min.” values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the “Max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39940D-page 320  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 OS51 OS52 OS53 Note 1: 2: Sym FPLLI FSYS Characteristic(1) PLL Input Frequency Range(2) PLL Output Frequency Range Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min 4 95.76 — -0.25 Typ(2) — — 180 — Max 32 96.24 — 0.25 Units MHz MHz s % Conditions ECPLL, HSPLL, XTPLL modes TLOCK PLL Start-up Time (Lock Time) DCLK CLKO Stability (Jitter) These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 29-18: INTERNAL RC OSCILLATOR SPECIFICATIONS AC CHARACTERISTICS Param No. Sym TFRC Characteristic(1) FRC Start-up Time Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min — — Typ 15 500 Max — — Units s s Conditions TLPRC LPRC Start-up Time TABLE 29-19: INTERNAL RC OSCILLATOR ACCURACY AC CHARACTERISTICS Param No. F20 F21 Note 1: 2: 3: Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA +85°C for Industrial -40°C  TA  +125°C for Extended Min -1.25 -15 Typ +0.25 — Max 1.0 15 Units % % Conditions -40°C  TA +85°C, 3.0V  VDD 3.6V -40°C  TA +85°C, 3.0V  VDD 3.6V Characteristic FRC Accuracy @ 8 MHz(1,3) LPRC Accuracy @ 31 kHz(2) Frequency calibrated at 25°C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. Change of LPRC frequency as VDD changes. To achieve this accuracy, physical stress applied to the microcontroller package (ex: by flexing the PCB) must be kept to a minimum.  2010 Microchip Technology Inc. DS39940D-page 321 PIC24FJ64GB004 FAMILY FIGURE 29-5: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 29-3 for load conditions. New Value TABLE 29-20: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. DO31 DO32 DI35 DI40 Note 1: Sym TIOR TIOF TINP TRBP Characteristic Port Output Rise Time Port Output Fall Time INTx pin High or Low Time (output) CNx High or Low Time (input) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. TABLE 29-21: RESET, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. SY10 SY11 SY12 SY13 SY25 TmcL TPWRT TPOR TIOZ TBOR TRST TDSWU Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic MCLR Pulse Width (low) Power-up Timer Period Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Brown-out Reset Pulse Width Internal State Reset Time Wake-up from Deep Sleep Time Min. 2 — — — 1 — — Typ(1) — 64 2 — — 50 200 Max. — — — 100 — — — Units s ms s ns s s s Based on full discharge of 10 F capacitor on VCAP. Includes TPOR and TRST. VDD VBOR Conditions Note 1: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. DS39940D-page 322  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY TABLE 29-21: RESET, POWER-UP TIMER AND BROWN-OUT RESET TIMING REQUIREMENTS AC CHARACTERISTICS Param Symbol No. TPM Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic Min. — — Note 1: Typ(1) 10 190 Max. — — Units s s Sleep wake-up with PMSLP = 0 and WUTSEL = 11 Conditions Data in “Typ” column is at 3.3V, 25°C unless otherwise stated.  2010 Microchip Technology Inc. DS39940D-page 323 PIC24FJ64GB004 FAMILY TABLE 29-22: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param No. AD01 Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40°C  TA  +85°C for Industrial -40°C  TA  +125°C for Extended Characteristic Min. Typ Max. Units Conditions Symbol Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 2.0 VSS – 0.3 AVSS + 1.7 AVSS AVSS – 0.3 — — — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD AVDD – 1.7 AVDD + 0.3 1.25 — V AD02 AD05 AD06 AD07 AD08 AD09 AVSS VREFH VREFL VREF IVREF ZVREF Module VSS Supply Reference Voltage High Reference Voltage Low Absolute Reference Voltage Reference voltage input current Reference input impedance — — — — — 10k V V V V mA  (Note 3) (Note 4) Reference Inputs Analog Input AD10 AD11 AD12 AD13 VINH-VINL Full-Scale Input Span VIN VINL — Absolute Input Voltage Absolute VINL Input Voltage Leakage Current VREFL AVSS – 0.3 AVSS – 0.3 — — — — ±0.001 VREFH AVDD + 0.3 AVDD/2 ±0.610 V V V A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k 10-bit (Note 2) AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity(1) — — 2.5K  ADC Accuracy AD20b NR AD21b INL AD22b DNL AD23b GERR AD24b EOFF AD25b — Note 1: 2: 3: 4: — — — — — — 10 ±1 ±0.5 ±1 ±1 — — 4)1@ ZLWK PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D2 EXPOSED PAD e E E2 2 1 2 1 N NOTE 1 TOP VIEW BOTTOM VIEW L K b N A A3 A1 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI 3LQV 3LWFK 2YHUDOO +HLJKW 6WDQGRII &RQWDFW 7KLFNQHVV 2YHUDOO :LGWK ([SRVHG 3DG :LGWK 2YHUDOO /HQJWK ([SRVHG 3DG /HQJWK &RQWDFW :LGWK &RQWDFW /HQJWK 1 H $ $ $ ( ( ' ' E / ± %6& 5() %6& %6& 0,1 0,//,0(7(56 120 0$; &RQWDFW WR ([SRVHG 3DG . ± 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD 3DFNDJH LV VDZ VLQJXODWHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & %  2010 Microchip Technology Inc. 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DS39940D-page 339 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 340  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY APPENDIX A: REVISION HISTORY Revision C (October 2009) Corrected Section 10.3 “Input Change Notification” regarding the number of ICN inputs and the availability of pull-downs. Updated Section 10.4.2 “Available Peripherals” by removing the Timer 1 clock input from Table 10-2. Updated Section 29.1 “DC Characteristics” as follows: • Added new specifications to Tables 29-4 and 29-5 for IDD and IIDLE at 0.5 MIPS operation. • Updated Table 29-4 with revised maximum IDD specifications for 1 MIPS and 4 MIPS. • Renumbered the parameters for the delta IPD current (32 kHz, SOSCEL = 11) from DC62n to DC63n. Revision A (April 2009) Original data sheet for the PIC24FJ64GB004 family of devices. Revision B (July 2009) Removed the unimplemented CNPD1 and CNPD2 registers from Table 4-4. Corrected the addresses of the CNPU1 and CNPU2 registers in the same table. Updated Table 6-2 (Reset Delay Times) with the addition of TRSRT to all table entries. Updated Register 7-35 (INTTREG) with a more descriptive version. Updated Section 9.2.4 “Deep Sleep Mode” with family-specific information and an extended discussion of special cases for Deep Sleep mode entry. Updated Section 29.1 “DC Characteristics” as follows: • Added Maximum values to Tables 29-4, 29-5, 29-6 and 29-7. • Updated specifications in Tables 29-3 and 29-8. • Added new Tables 29-11 (Comparator Specifications) and 29-12 (Comparator Voltage Reference Specifications), renumbering all subsequent tables. • Removed redundant or obsolete specifications in Tables 29-6, 29-7 and 29-12. Updated Section 29.2 “AC Characteristics and Timing Parameters” as follows: • Updated specifications in Tables 29-17 and 29-19. • Added new Table 29-21 (Reset, Power-up Timer and Brown-out Reset Timing Requirements), renumbering all subsequent tables. Other minor typographic revisions throughout the document. Revision D (August 2010) Updated Section 10.4.5 “Considerations Peripheral Pin Selection” as follows: • Replaced the code in Example 10-1. • Added the new code in Example 10-3. Updated Figure 18-1 in Section 18.0 “Universal Serial Bus with On-The-Go Support (USB OTG)” Updated follows: Section 29.1 “DC Characteristics”as for • Added the “125°c data” in Table 29-4,Table 29-5,Table 29-6 and Table 29-7. • Updated Min and Typ columns of DC16 in Table 29-3. • Updated OS10 parameter in Table 29-16. • Added rows, AD08 and AD09, in Table 29-22. • Added Figure 29-2.  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 342  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY INDEX A A/D Converter Analog Input Model ................................................... 267 Transfer Function...................................................... 268 AC Characteristics A/D Specifications..................................................... 324 ADC Conversion Requirements................................ 325 Capacitive Loading Requirements on Output Pins ....................................................... 319 CLKO and I/O Timing................................................ 322 External Clock Requirements ................................... 320 Internal RC Oscillator Accuracy ................................ 321 Internal RC Oscillator Specifications......................... 321 Load Conditions and Requirements for Timing Specifications ........................................ 319 PLL Clock Specifications .......................................... 321 Reset, Power-up Timer and Brown-out Reset Timing..................................................... 322 Temperature and Voltage Specifications .................. 319 Alternate Interrupt Vector Table (AIVT) .............................. 69 Assembler MPASM Assembler................................................... 294 Partially Multiplexed Addressing Application Example ......................................... 239 PIC24F CPU Core ...................................................... 26 PIC24FJ64GB004 Family (General)........................... 12 PMP Module Overview ............................................. 231 PSV Operation............................................................ 53 Reset System ............................................................. 63 RTCC........................................................................ 241 SPI Master, Frame Master Connection .................... 179 SPI Master, Frame Slave Connection ...................... 179 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 178 SPI Master/Slave Connection (Standard Mode)....... 178 SPI Slave, Frame Master Connection ...................... 179 SPI Slave, Frame Slave Connection ........................ 179 SPIx Module (Enhanced Mode)................................ 173 SPIx Module (Standard Mode) ................................. 172 System Clock............................................................ 107 Triple Comparator Module........................................ 269 Typical Shared I/O Port Structure............................. 127 UART (Simplified)..................................................... 189 USB OTG Bus Power Only................................................ 199 Dual Power, Example ....................................... 199 External Pull-up for Full-Speed Device Mode ............................................ 199 Host Interface, Example ................................... 200 OTG Interface, Example................................... 200 Self-Power Only................................................ 199 USB OTG Interrupt Funnel ....................................... 206 USB OTG Module..................................................... 198 USB PLL................................................................... 114 Watchdog Timer (WDT)............................................ 289 B Block Diagrams 10-Bit High-Speed A/D Converter............................. 260 16-Bit Asynchronous Timer3 and Timer5 ................. 153 16-Bit Synchronous Timer2 and Timer4 ................... 153 16-Bit Timer1 Module................................................ 149 32-Bit Timer2/3 and Timer4/5 ................................... 152 8-Bit Multiplexed Address and Data Application Example ......................................... 240 Accessing Program Memory Using Table Instructions 52 Addressable PSP Example....................................... 238 Addressing for Table Registers................................... 55 BDT Mapping for Endpoint Buffering Modes ............ 202 CALL Stack Frame...................................................... 50 Comparator Voltage Reference ................................ 273 CPU Programmer’s Model .......................................... 27 CRC Module ............................................................. 253 CRC Shift Engine...................................................... 253 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 275 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 276 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 276 Data Access From Program Space Address Generation .......................................................... 51 I2C Module ................................................................ 182 Individual Comparator Configurations....................... 270 Input Capture ............................................................ 157 LCD Control Example, Byte Mode ............................ 240 Legacy PSP Example ............................................... 238 Master Mode, Demultiplexed Addressing ................. 238 Master Mode, Fully Multiplexed Addressing ............. 239 Master Mode, Partially Multiplexed Addressing ........ 239 Multiplexed Addressing Application Example ........... 239 On-Chip Regulator Connections ............................... 287 Output Compare (16-Bit Mode)................................. 162 Parallel EEPROM Example, 16-Bit Data .................. 240 Parallel EEPROM Example, 8-Bit Data .................... 240 C C Compilers MPLAB C18.............................................................. 294 Charge Time Measurement Unit. See CTMU. Code Examples Basic Clock Switching Sequence ............................. 113 Configuring UART1 Input and Output Functions, Assembly ........................................ 134 Erasing a Program Memory Block, ‘C’........................ 59 I/O Port Write/Read .................................................. 128 Initiating a Programming Sequence, ‘C’ ..................... 60 Initiating a Programming Sequence, Assembly.......... 60 Loading the Write Buffers, ‘C’..................................... 60 Loading the Write Buffers, Assembly ......................... 59 PWRSAV Instruction Syntax .................................... 117 Setting the RTCWREN Bit ........................................ 242 Single-Word Flash Programming, ‘C’ ......................... 61 Single-Word Flash Programming, Assembly.............. 61 Code Protection ................................................................ 289 Code Segment Protection ........................................ 290 Configuration Options....................................... 290 Configuration Register Protection............................. 290 Comparator Voltage Reference ........................................ 273 Configuring ............................................................... 273 Configuration Bits ............................................................. 279 Core Features....................................................................... 9  2010 Microchip Technology Inc. DS39940D-page 343 PIC24FJ64GB004 FAMILY CPU Arithmetic Logic Unit (ALU)......................................... 29 Clocking Scheme ...................................................... 108 Control Registers ........................................................ 28 Core Registers ............................................................ 27 Programmer’s Model................................................... 25 CRC Registers ................................................................... 255 Typical Operation ...................................................... 255 User Interface ........................................................... 254 Data .................................................................. 254 Polynomial ........................................................ 254 CTMU Measuring Capacitance ............................................ 275 Measuring Time ........................................................ 276 Pulse Delay and Generation ..................................... 276 Customer Change Notification Service ............................. 348 Customer Notification Service........................................... 348 Customer Support ............................................................. 348 F Flash Configuration Words ................................. 32, 279–285 Flash Program Memory ...................................................... 55 and Table Instructions ................................................ 55 Enhanced ICSP Operation ......................................... 56 JTAG Operation.......................................................... 56 Programming Algorithm .............................................. 58 RTSP Operation ......................................................... 56 Single-Word Programming ......................................... 61 I I/O Ports Analog Input Voltage Considerations ....................... 128 Analog Port Pins Configuration................................. 128 Input Change Notification ......................................... 129 Open-Drain Configuration......................................... 128 Parallel (PIO) ............................................................ 127 Peripheral Pin Select ................................................ 129 Pull-ups and Pull-Downs........................................... 129 I2C Clock Rates .............................................................. 183 Communicating as Master in a Single Master Environment ......................................... 181 Reserved Addresses ................................................ 183 Setting Baud Rate When Operating as Bus Master ....................................................... 183 Slave Address Masking ............................................ 183 Input Capture 32-Bit Mode .............................................................. 158 Operations ................................................................ 158 Synchronous and Trigger Modes.............................. 157 Input Capture with Dedicated Timers ............................... 157 Instruction Set Overview................................................................... 299 Summary .................................................................. 297 Symbols Used in Opcode Descriptions .................... 298 Instruction-Based Power-Saving Modes........................... 117 Deep Sleep ............................................................... 118 Idle ............................................................................ 118 Sleep ........................................................................ 117 Inter-Integrated Circuit. See I2C. ...................................... 181 Internet Address ............................................................... 348 Interrupt Service Routine (ISR)......................................... 106 Interrupt Vector Table (IVT) ................................................ 69 Interrupts and Reset Sequence .................................................. 69 Control and Status Registers...................................... 72 Implemented Vectors.................................................. 71 Setup and Service Procedures ................................. 106 Trap Vectors ............................................................... 70 Vector Table ............................................................... 70 D Data Memory Address Space............................................................ 33 Memory Map ............................................................... 33 Near Data Space ........................................................ 34 SFR Space.................................................................. 34 Software Stack ............................................................ 50 Space Organization and Alignment ............................ 34 DC Characteristics Comparator Specifications ........................................ 318 Comparator Voltage Reference ................................ 318 I/O Pin Input Specifications ....................................... 316 I/O Pin Output Specifications .................................... 317 Idle Current ............................................................... 311 Internal Voltage Regulator ........................................ 318 Operating Current ..................................................... 309 Power-Down Base Current ....................................... 313 Power-Down Peripheral Module Current (IPD) .......... 314 Program Memory ...................................................... 317 Temperature and Voltage Specifications .................. 308 Deep Sleep BOR (DSBOR) ................................................ 67 Deep Sleep Watchdog Timer (DSWDT) ........................... 289 Development Support ....................................................... 293 DISVREG Pin.................................................................... 287 Doze Mode........................................................................ 125 E Electrical Characteristics Absolute Maximum Ratings ...................................... 305 Thermal Conditions ................................................... 307 V/F Graphs................................................................ 306 Equations A/D Conversion Clock Period ................................... 267 Baud Rate Reload Calculation .................................. 183 Calculating the PWM Period ..................................... 165 Calculation for Maximum PWM Resolution............... 165 Estimating USB Transceiver Current Consumption..................................................... 201 Relationship Between Device and SPI Clock Speed...................................................... 180 UART Baud Rate with BRGH = 0 ............................. 190 UART Baud Rate with BRGH = 1 ............................. 190 Errata .................................................................................... 8 Examples Baud Rate Error Calculation (BRGH = 0) ................. 190 J JTAG Interface.................................................................. 291 M Microchip Internet Web Site.............................................. 348 MPLAB ASM30 Assembler, Linker, Librarian ................... 294 MPLAB Integrated Development Environment Software.. 293 MPLAB PM3 Device Programmer .................................... 296 MPLAB REAL ICE In-Circuit Emulator System ................ 295 MPLINK Object Linker/MPLIB Object Librarian ................ 294 DS39940D-page 344  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY N Near Data Space ................................................................ 34 O On-Chip Voltage Regulator ............................................... 287 BOR .......................................................................... 288 POR .......................................................................... 287 Power-up Requirements ........................................... 288 Standby Mode........................................................... 288 Tracking .................................................................... 287 Oscillator Configuration..................................................... 107 Clock Selection ......................................................... 108 Clock Switching......................................................... 112 Sequence.......................................................... 113 Initial Configuration on POR ..................................... 108 Secondary Oscillator (SOSC) ................................... 115 USB Operation.......................................................... 114 Special Considerations ..................................... 114 Output Compare 32-Bit Mode............................................................... 161 Operations ................................................................ 163 Subcycle Resolution ................................................. 166 Synchronous and Trigger Modes.............................. 161 Output Compare with Dedicated Timers ........................... 161 P Packaging ......................................................................... 327 Details ....................................................................... 329 Marking ..................................................................... 327 Parallel Master Port. See PMP. ........................................ 231 Peripheral Enable Bits ...................................................... 125 Peripheral Module Disable Bits ......................................... 125 Peripheral Pin Select (PPS) .............................................. 129 Available Peripherals and Pins ................................. 129 Configuration Control ................................................ 132 Considerations for Use ............................................. 133 Input Mapping ........................................................... 130 Output Mapping ........................................................ 131 Peripheral Priority ..................................................... 129 Pin Diagrams ................................................................ 4, 5, 6 Pinout Descriptions ............................................................. 13 Power-Saving Features .................................................... 117 Clock Frequency and Clock Switching...................... 117 Product Identification System ........................................... 350 Program Memory Access Using Table Instructions................................. 52 Address Space............................................................ 31 Addressing .................................................................. 50 Flash Configuration Words ......................................... 32 Memory Maps ............................................................. 31 Organization................................................................ 32 Program Space Visibility ............................................. 53 Program Space Visibility (PSV) .......................................... 53 Program Verification ......................................................... 289 Pulse-Width Modulation (PWM) Mode .............................. 164 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 165 R Reader Response ............................................................. 349 Reference Clock Output.................................................... 115 Register Maps A/D Converter ............................................................. 43 Comparators ............................................................... 46 CPU Core ................................................................... 35 CRC............................................................................ 46 CTMU ......................................................................... 43 Deep Sleep................................................................. 48 I2C .............................................................................. 41 ICN ............................................................................. 36 Input Capture.............................................................. 39 Interrupt Controller...................................................... 37 NVM............................................................................ 48 Output Compare ......................................................... 40 Pad Configuration....................................................... 43 Parallel Master/Slave Port .......................................... 45 Peripheral Pin Select .................................................. 47 PMD............................................................................ 49 PORTA ....................................................................... 42 PORTB ....................................................................... 42 PORTC ....................................................................... 42 RTCC.......................................................................... 46 SPI.............................................................................. 42 System........................................................................ 48 Timers......................................................................... 38 UART.......................................................................... 41 USB OTG ................................................................... 44 Registers AD1CHS (A/D Input Select)...................................... 264 AD1CON1 (A/D Control 1)........................................ 261 AD1CON2 (A/D Control 2)........................................ 262 AD1CON3 (A/D Control 3)........................................ 263 AD1CSSL (A/D Input Scan Select)........................... 266 AD1PCFG (A/D Port Configuration) ......................... 265 ALCFGRPT (Alarm Configuration) ........................... 245 ALMINSEC (Alarm Minutes and Seconds Value) ................................................ 249 ALMTHDY (Alarm Month and Day Value) ................ 248 ALWDHR (Alarm Weekday and Hours Value) ......... 248 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode)........................................... 205 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode)........................................... 204 CLKDIV (Clock Divider) ............................................ 111 CMSTAT (Comparator Module Status) .................... 272 CMxCON (Comparator x Control) ............................ 271 CORCON (CPU Control) ............................................ 29 CORCON (CPU Core Control) ................................... 73 CRCCON1 (CRC Control 1) ..................................... 256 CRCCON2 (CRC Control 2) ..................................... 257 CRCXORH (CRC XOR Polynomial, High Byte) ....... 258 CRCXORL (CRC XOR Polynomial, Low Byte)......... 257 CTMUCON (CTMU Control)..................................... 277 CTMUICON (CTMU Current Control) ....................... 278 CVRCON (Comparator Voltage Reference Control) ........................................... 274 CW1 (Flash Configuration Word 1) .......................... 280 CW2 (Flash Configuration Word 2) .......................... 282 CW3 (Flash Configuration Word 3) .......................... 284 DEVID (Device ID).................................................... 286 DEVREV (Device Revision)...................................... 286 DSCON (Deep Sleep Control).................................. 123 DSWAKE (Deep Sleep Wake-up Source) ................ 124 I2CxCON (I2Cx Control)........................................... 184 I2CxMSK (I2Cx Slave Mode Address Mask)............ 188 I2CxSTAT (I2Cx Status) ........................................... 186 ICxCON1 (Input Capture x Control 1)....................... 159 ICxCON2 (Input Capture x Control 2)....................... 160 IEC0 (Interrupt Enable Control 0) ............................... 82  2010 Microchip Technology Inc. DS39940D-page 345 PIC24FJ64GB004 FAMILY IEC1 (Interrupt Enable Control 1) ............................... 83 IEC2 (Interrupt Enable Control 2) ............................... 84 IEC3 (Interrupt Enable Control 3) ............................... 85 IEC4 (Interrupt Enable Control 4) ............................... 86 IEC5 (Interrupt Enable Control 5) ............................... 87 IFS0 (Interrupt Flag Status 0) ..................................... 76 IFS1 (Interrupt Flag Status 1) ..................................... 77 IFS2 (Interrupt Flag Status 2) ..................................... 78 IFS3 (Interrupt Flag Status 3) ..................................... 79 IFS4 (Interrupt Flag Status 4) ..................................... 80 IFS5 (Interrupt Flag Status 5) ..................................... 81 INTCON1 (Interrupt Control 1) .................................... 74 INTCON2 (Interrupt Control 2) .................................... 75 INTTREG (Interrupt Control and Status)................... 105 IPC0 (Interrupt Priority Control 0) ............................... 88 IPC1 (Interrupt Priority Control 1) ............................... 89 IPC10 (Interrupt Priority Control 10) ........................... 98 IPC11 (Interrupt Priority Control 11) ........................... 99 IPC12 (Interrupt Priority Control 12) ......................... 100 IPC15 (Interrupt Priority Control 15) ......................... 101 IPC16 (Interrupt Priority Control 16) ......................... 102 IPC18 (Interrupt Priority Control 18) ......................... 103 IPC19 (Interrupt Priority Control 19) ......................... 103 IPC2 (Interrupt Priority Control 2) ............................... 90 IPC21 (Interrupt Priority Control 21) ......................... 104 IPC3 (Interrupt Priority Control 3) ............................... 91 IPC4 (Interrupt Priority Control 4) ............................... 92 IPC5 (Interrupt Priority Control 5) ............................... 93 IPC6 (Interrupt Priority Control 6) ............................... 94 IPC7 (Interrupt Priority Control 7) ............................... 95 IPC8 (Interrupt Priority Control 8) ............................... 96 IPC9 (Interrupt Priority Control 9) ............................... 97 MINSEC (RTCC Minutes and Seconds Value) ......... 247 MTHDY (RTCC Month and Day Value) .................... 246 NVMCON (Flash Memory Control) ............................. 57 OCxCON1 (Output Compare x Control 1) ................ 167 OCxCON2 (Output Compare x Control 2) ................ 169 OSCCON (Oscillator Control) ................................... 109 OSCTUN (FRC Oscillator Tune) ............................... 112 PADCFG1 (Pad Configuration Control) ............ 237, 244 PMADDR (Parallel Port Address) ............................. 235 PMAEN (Parallel Port Enable) .................................. 235 PMCON (Parallel Port Control) ................................. 232 PMMODE (Parallel Port Mode) ................................. 234 PMSTAT (Parallel Port Status) ................................. 236 RCFGCAL (RTCC Calibration and Configuration) ................................................... 243 RCON (Reset Control) ................................................ 64 REFOCON (Reference Oscillator Control)................ 116 RPINR0 (Peripheral Pin Select Input 0) .................... 135 RPINR1 (Peripheral Pin Select Input 1) .................... 135 RPINR11 (Peripheral Pin Select Input 11) ................ 138 RPINR18 (Peripheral Pin Select Input 18) ................ 139 RPINR19 (Peripheral Pin Select Input 19) ................ 139 RPINR20 (Peripheral Pin Select Input 20) ................ 140 RPINR21 (Peripheral Pin Select Input 21) ................ 140 RPINR22 (Peripheral Pin Select Input 22) ................ 141 RPINR23 (Peripheral Pin Select Input 23) ................ 141 RPINR3 (Peripheral Pin Select Input 3) .................... 136 RPINR4 (Peripheral Pin Select Input 4) .................... 136 RPINR7 (Peripheral Pin Select Input 7) .................... 137 RPINR8 (Peripheral Pin Select Input 8) .................... 137 RPINR9 (Peripheral Pin Select Input 9) .................... 138 RPOR1 (Peripheral Pin Select Output 1) .................. 142 RPOR10 (Peripheral Pin Select Output 10) .............. 147 RPOR11 (Peripheral Pin Select Output 11).............. 147 RPOR12 (Peripheral Pin Select Output 12).............. 148 RPOR2 (Peripheral Pin Select Output 2).................. 143 RPOR3 (Peripheral Pin Select Output 3).................. 143 RPOR4 (Peripheral Pin Select Output 4).................. 144 RPOR5 (Peripheral Pin Select Output 5).................. 144 RPOR6 (Peripheral Pin Select Output 6).................. 145 RPOR7 (Peripheral Pin Select Output 7).................. 145 RPOR8 (Peripheral Pin Select Output 8).................. 146 RPOR9 (Peripheral Pin Select Output 9).................. 146 SPIxCON1 (SPIx Control 1)...................................... 176 SPIxCON2 (SPIx Control 2)...................................... 177 SPIxSTAT (SPIx Status and Control) ....................... 174 SR (ALU STATUS, in CPU)........................................ 73 SR (ALU STATUS) ..................................................... 28 T1CON (Timer1 Control) .......................................... 150 TxCON (Timer2 and Timer4 Control) ....................... 154 TyCON (Timer3 and Timer5 Control) ....................... 155 U1ADDR (USB Address) .......................................... 219 U1CNFG1 (USB Configuration 1)............................. 220 U1CNFG2 (USB Configuration 2)............................. 221 U1CON (USB Control, Device Mode)....................... 217 U1CON (USB Control, Host Mode) .......................... 218 U1EIE (USB Error Interrupt Enable) ......................... 228 U1EIR (USB Error Interrupt Status).......................... 227 U1EPn (USB Endpoint n Control)............................. 229 U1IE (USB Interrupt Enable) .................................... 226 U1IR (USB Interrupt Status, Device Mode) .............. 224 U1IR (USB Interrupt Status, Host Mode).................. 225 U1OTGCON (USB OTG Control) ............................. 214 U1OTGIE (USB OTG Interrupt Enable, Host Mode) ....................................................... 223 U1OTGIR (USB OTG Interrupt Status, Host Mode) ....................................................... 222 U1OTGSTAT (USB OTG Status, Host Mode) .......... 213 U1PWMCON USB (VBUS PWM Generator Control)............................................................. 230 U1PWRC (USB Power Control)................................ 215 U1SOF (USB OTG Start-of-Token Threshold, Host Mode) ..................................... 220 U1STAT (USB Status) .............................................. 216 U1TOK (USB Token, Host Mode)............................. 219 UxMODE (UARTx Mode).......................................... 192 UxSTA (UARTx Status and Control)......................... 194 WKDYHR (RTCC Weekday and Hours Value)......... 247 YEAR (RTCC Year Value)........................................ 246 Reset, Power-up Timer and Brown-out Reset Timing Requirements................................................ 322 Resets BOR (Brown-out Reset).............................................. 63 Clock Source Selection............................................... 65 CM (Configuration Mismatch Reset)........................... 63 Delay Times................................................................ 66 Device Times .............................................................. 65 IOPUWR (Illegal Opcode Reset) ................................ 63 MCLR (Pin Reset)....................................................... 63 POR (Power-on Reset)............................................... 63 RCON Flags Operation............................................... 65 SFR States ................................................................. 67 SWR (RESET Instruction) .......................................... 63 TRAPR (Trap Conflict Reset) ..................................... 63 UWR (Uninitialized W Register Reset) ....................... 63 WDT (Watchdog Timer Reset) ................................... 63 Revision History................................................................ 341 DS39940D-page 346  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY RTCC Alarm Configuration .................................................. 250 Alarm Mask Settings (figure)..................................... 251 Calibration................................................................. 250 Register Mapping...................................................... 242 Selecting Clock Source............................................. 242 Source Clock............................................................. 241 Write Lock ................................................................. 242 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus Buffer Descriptors Assignment in Different Buffering Modes ......... 203 Interrupts and USB Transactions...................................... 207 Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 10 USB OTG Buffer Descriptors and BDT...................................... 202 Device Mode Operation............................................ 207 DMA Interface........................................................... 203 Hardware Configuration Device Mode..................................................... 199 External Interface ............................................. 201 Host and OTG Modes....................................... 200 Transceiver Power Requirements .................... 201 VBUS Voltage Generation ................................. 201 Host Mode Operation ............................................... 208 Interrupts .................................................................. 206 OTG Operation ......................................................... 210 Registers .......................................................... 212–230 VBUS Voltage Generation ......................................... 201 S Selective Peripheral Power Control .................................. 125 Serial Peripheral Interface. See SPI. SFR Space.......................................................................... 34 Software Simulator (MPLAB SIM)..................................... 295 Software Stack .................................................................... 50 Special Features ................................................................. 10 SPI T Timer1 ............................................................................... 149 Timer2/3 and Timer4/5...................................................... 151 Timing Diagrams CLKO and I/O Timing................................................ 322 External Clock........................................................... 320 Trap Service Routine (TSR).............................................. 106 Triple Comparator ............................................................. 269 V VDDCORE/VCAP Pin ........................................................... 287 U UART ................................................................................ 189 Baud Rate Generator (BRG)..................................... 190 IrDA Support ............................................................. 191 Operation of UxCTS and UxRTS Pins ...................... 191 Receiving 8-Bit or 9-Bit Data Mode ................................... 191 Transmitting 8-Bit Data Mode ................................................ 191 9-Bit Data Mode ................................................ 191 Break and Sync Sequence ............................... 191 W Watchdog Timer (WDT).................................................... 288 Control Register........................................................ 289 Windowed Operation ................................................ 289 WWW Address ................................................................. 348 WWW, On-Line Support ....................................................... 8  2010 Microchip Technology Inc. DS39940D-page 347 PIC24FJ64GB004 FAMILY NOTES: DS39940D-page 348  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions.  2010 Microchip Technology Inc. DS39940D-page 349 PIC24FJ64GB004 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS39940D FAX: (______) _________ - _________ Device: PIC24FJ64GB004 Family Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39940D-page 350  2010 Microchip Technology Inc. PIC24FJ64GB004 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 64 GB0 04 T - I / PT - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern b) Examples: a) PIC24FJ64GB004-I/PT: PIC24F device with USB On-The-Go, 64-Kbyte program memory, 44-pin, Industrial temp.,TQFP package. PIC24FJ32GB002-I/ML: PIC24F device with USB On-The-Go, 32-Kbyte program memory, 28-pin, Industrial temp.,QFN package. Architecture Flash Memory Family Product Group 24 FJ = 16-bit modified Harvard without DSP = Flash program memory GB0 = General purpose microcontrollers with USB On-The-Go 02 04 I E ML PT SO SP SS = 28-pin = 44-pin = -40C to +85C (Industrial) = -40C to +125C (Extended) = 28-lead (6x6 mm) or 44-lead (8x8 mm) QFN (Quad Flat) = 44-lead (10x10x1 mm) TQFP (Thin Quad Flatpack) = 28-lead 7.50 mm wide) SOIC (Small Outline) = 28-lead (300 mil) SPDIP (Skinny Plastic Dual In-Line) = 28-lead (530 mm) SSOP (Plastic Shrink Small) Pin Count Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2010 Microchip Technology Inc. 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