PIC24HJ12GP201

PIC24HJ12GP201/202 Data Sheet High-Performance, 16-Bit Microcontrollers © 2007 Microchip Technology Inc. Preliminary DS70282B Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, PS logo, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70282B-page ii Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 High-Performance, 16-Bit Digital Signal Controllers Operating Range: • Up to 40 MIPS operation (@ 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) Digital I/O: • • • • • • • Peripheral Pin Select Functionality Up to 21 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 21 pins Output pins can drive from 3.0V to 3.6V Up to 5V output with open drain configuration All digital input pins are 5V tolerant 4 mA sink on all I/O pins High-Performance CPU: • • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions, mostly 1 word/1 cycle Sixteen 16-bit general purpose registers Flexible and powerful addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit shifts for up to 40-bit data System Management: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Interrupt Controller: • • • • • • 5-cycle latency 118 interrupt vectors Up to 21 available interrupt sources Up to 3 external interrupts 7 programmable priority levels 4 processor exceptions Timers/Capture/Compare: • Timer/Counters, up to three 16-bit timers: - Can pair up to make one 32-bit timer - 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to 4 channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to 2 channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM Mode On-Chip Flash and SRAM: • Flash program memory (12 Kbytes) • Data SRAM (1024 bytes) • Boot and General Security for Program Flash © 2007 Microchip Technology Inc. Preliminary DS70282B-page 1 PIC24HJ12GP201/202 Communication Modules: • 4-wire SPI: - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART: - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Analog-to-Digital Converters (ADCs): • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2 and 4 simultaneous samples (10-bit ADC) - Up to 10 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and extended temperature Low power consumption Packaging: • 18-pin SDIP/SOIC • 28-pin SDIP/SOIC/QFN Note: See the device variant tables for exact peripheral features per device. DS70282B-page 2 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 PIC24HJ12GP201/202 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ12GP201/202 CONTROLLER FAMILIES Program Flash Memory (Kbyte) Remappable Peripherals 10-Bit/12-Bit ADC Output Compare Std. PWM I/O Pins (Max) Input Capture Remappable Pins 16-bit Timer Packages SDIP SOIC SDIP SOIC QFN RAM (Kbyte) UART PIC24HJ12GP201 PIC24HJ12GP202 18 28 12 12 1 1 8 16 3(1) 3(1) 4 4 2 2 1 1 SPI Device 1 1 1 ADC, 6 ch 1 ADC, 10 ch I2C™ 1 1 Pins 13 21 Note 1: Only 2 out of 3 timers are remappable. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 3 PIC24HJ12GP201/202 Pin Diagrams 18-Pin SDIP, SOIC MCLR PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 1 2 3 4 5 6 7 8 9 VDD VSS AN6/RP15/CN11/RB15 AN7/RP14/CN12/RB14 VDDCORE VSS SCL1/RP9/CN21/RB9 SDA1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 18 17 16 15 14 13 12 11 10 PIC24HJ12GP201 28-Pin SDIP, SOIC MCLR PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 Vss OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 PGD3/EMUD3/SOSC/RP4/CN1/RB4 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 VDD ASDA1/RP5/CN27/RB5 1 2 3 4 28 27 26 25 AVDD AVSS AN6/RP15/CN11/RB15 AN7/RP14/CN12/RB14 AN8/RP13/CN13/RB13 AN9/RP12/CN14/RB12 TMS/RP11/CN15/RB11 TDI/RP10/CN16/RB10 VDDCORE Vss TDO/SDA1/RP9/CN21/RB9 TCK/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 ASCL1/RP6/CN24/RB6 PIC24HJ12GP202 5 6 7 8 9 10 11 12 13 14 24 23 22 21 20 19 18 17 16 15 DS70282B-page 4 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 Pin Diagrams (Continued) 28-Pin QFN PGD2/EMUD2/AN0/VREF+/CN2/RA0 PGC2/EMUC2/AN1/VREF-/CN3/RA1 28 PGD1/EMUD1/AN2/RP0/CN4/RB0 PGC1/EMUC1/AN3/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 1 2 3 4 5 6 7 8 PGD3/EMUD3/SOSCI/RP4/CN1/RB4 27 26 25 24 23 AN7/RP14/CN12/RB14 22 21 20 19 AN8/RP13/CN13/RB13 AN9/RP12/CN14/RB12 TMS/RP11/CN15/RB11 TDI/RP10/CN16/RB10 VDDCORE VSS TDO/SDA1/RP9/CN21/RB9 18 17 16 15 14 TCK/SCL1/RP8/CN22/RB8 PIC24HJ12GP202 9 PGC3/EMUC3/SOSCO/T1CK/CN0/RA4 10 VDD 11 ASDA1/RP5/CN27/RB5 12 ASCL1/RP6/CN24/RB6 © 2007 Microchip Technology Inc. Preliminary INT0/RP7/CN23/RB7 AN6/RP15/CN11/RB15 13 MCLR AVDD AVSS DS70282B-page 5 PIC24HJ12GP201/202 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 7 2.0 CPU ............................................................................................................................................................................................ 11 3.0 Memory Organization ................................................................................................................................................................. 17 4.0 Flash Program Memory .............................................................................................................................................................. 37 5.0 Resets ....................................................................................................................................................................................... 43 6.0 Interrupt Controller ..................................................................................................................................................................... 49 7.0 Oscillator Configuration .............................................................................................................................................................. 77 8.0 Power-Saving Features .............................................................................................................................................................. 87 9.0 I/O Ports ..................................................................................................................................................................................... 89 10.0 Timer1 ...................................................................................................................................................................................... 109 11.0 Timer2/3 Feature...................................................................................................................................................................... 111 12.0 Input Capture............................................................................................................................................................................ 117 13.0 Output Compare ....................................................................................................................................................................... 119 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 125 15.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 133 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 143 17.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 151 18.0 Special Features ...................................................................................................................................................................... 163 19.0 Instruction Set Summary .......................................................................................................................................................... 171 20.0 Development Support............................................................................................................................................................... 179 21.0 Electrical Characteristics .......................................................................................................................................................... 183 22.0 Packaging Information.............................................................................................................................................................. 217 Appendix A: Revision History............................................................................................................................................................. 223 Index ................................................................................................................................................................................................. 225 The Microchip Web Site ..................................................................................................................................................................... 229 Customer Change Notification Service .............................................................................................................................................. 229 Customer Support .............................................................................................................................................................................. 229 Reader Response .............................................................................................................................................................................. 230 Product Identification System............................................................................................................................................................. 231 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70282B-page 6 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the PIC24HJ12GP201/202 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest PIC24H Family Reference Manual chapters. This document contains device specific information for the following devices: • PIC24HJ12GP201 • PIC24HJ12GP202 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ12GP201/202 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 7 PIC24HJ12GP201/202 FIGURE 1-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch 16 PORTB PIC24HJ12GP201/202 BLOCK DIAGRAM Data Bus 16 Data Latch PORTA 16 16 23 16 Address Generator Units Remappable Pins Address Latch Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data EA MUX 16 Instruction Decode & Control Control Signals to Various Blocks OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 17 x 17 Multiplier 16 x 16 W Register Array 16 Divide Support 16-bit ALU 16 VDDCORE/VCAP VDD, VSS MCLR Timers 1-3 ADC1 UART1 IC1,2,7,8 OC/ PWM1,2 CNx SPI1 I2C1 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70282B-page 8 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 TABLE 1-1: Pin Name AN0-AN9 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I I O Buffer Type Analog Analog input channels. Description ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS — otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. — 32.768 kHz low-power oscillator crystal output. ST Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. OSC1 OSC2 I I/O SOSCI SOSCO CN0-CN7 CN11-CN15 CN21-CN24 CN27 CN29-CN30 IC0-IC1 IC7-IC8 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RB0-RB15 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SS1 SCL1 SDA1 ASCL1 ASDA1 TMS TCK TDI TDO PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3 I O I I I O I I I I/O I/O I I I I O I O I/O I O I/O I/O I/O I/O I/O I I I O I/O I I/O I I/O I ST ST — ST ST ST ST ST ST ST ST ST — ST — ST ST — ST ST ST ST ST ST ST ST — ST ST ST ST ST ST Capture inputs 1/2 Capture inputs 7/8 Compare Fault A input (for Compare Channels 1 and 2). Compare outputs 1 through 2. External interrupt 0. External interrupt 1. External interrupt 2. PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels © 2007 Microchip Technology Inc. Preliminary DS70282B-page 9 PIC24HJ12GP201/202 TABLE 1-1: Pin Name VDDCORE VSS VREF+ VREFAVDD MCLR AVSS VDD PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type P P I I P I/P P P Buffer Type — — Analog Analog P ST P — Description CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels DS70282B-page 10 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 2.0 Note: CPU This data sheet summarizes the features of this group of PIC24HJ12GP201/202 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest PIC24H Family Reference Manual chapters. 2.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. The PIC24HJ12GP201/202 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. The PIC24HJ12GP201/202 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJ12GP201/202 instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJ12GP201/202 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the PIC24HJ12GP201/202 is shown in Figure 2-2. 2.2 Special MCU Features The PIC24HJ12GP201/202 features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. The PIC24HJ12GP201/202 supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 11 PIC24HJ12GP201/202 FIGURE 2-1: PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 X Data Bus PIC24HJ12GP201/202 CPU CORE BLOCK DIAGRAM 16 16 Data Latch X RAM Address Latch 16 23 16 Address Latch Address Generator Units Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX Instruction Decode & Control Instruction Reg 17 x 17 Multiplier 16 Control Signals to Various Blocks Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70282B-page 12 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 FIGURE 2-2: PIC24HJ12GP201/202 PROGRAMMER’S MODEL D15 W0/WREG W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers DO Shadow D0 PUSH.S Shadow Legend PC22 0 TBLPAG 7 PSVPAG 0 Data Table Page Address PC0 0 Program Counter 7 Program Space Visibility Page Address 15 RCOUNT 0 REPEAT Loop Counter 15 CORCON 0 Core Configuration Register — — — — — — — DC IPL2 IPL1 IPL0 RA SRL N OV Z C STATUS Register SRH © 2007 Microchip Technology Inc. Preliminary DS70282B-page 13 PIC24HJ12GP201/202 2.3 CPU Control Registers SR: CPU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(2) IPL(2) bit 7 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set bit 15-9 bit 8 R = Readable bit W = Writable bit ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown R/W-0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 U-0 — bit 15 R/W-0(1) REGISTER 2-1: bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. 2: The IPL Status bits are read only when NSTDIS = 1 (INTCON1). DS70282B-page 14 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 REGISTER 2-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 C = Clear only bit W = Writable bit ‘x = Bit is unknown CORCON: CORE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 15 PIC24HJ12GP201/202 2.4 Arithmetic Logic Unit (ALU) 2.4.2 DIVIDER The PIC24HJ12GP201/202 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The PIC24HJ12GP201/202 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 2.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. 2.4.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS70282B-page 16 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC24HJ12GP201/202 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest PIC24H Family Reference Manual chapters. 3.1 Program Address Space The program address memory space of the PIC24HJ12GP201/202 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3.4 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ12GP201/202 device is shown in Figure 3-1. The PIC24HJ12GP201/202 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 3-1: PROGRAM MEMORY FOR PIC24HJ12GP201/202 DEVICES PIC24HJ12GP201/202 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Memory Space 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 User Program Flash Memory (4K instructions) 0x001FFE 0x002000 Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 Reserved Configuration Memory Space Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE © 2007 Microchip Technology Inc. Preliminary DS70282B-page 17 PIC24HJ12GP201/202 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. All PIC24HJ12GP201/202 devices reserve the addresses between 0x00000 and 0x000200 for hardcoded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ12GP201/202 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 6.1 “Interrupt Vector Table”. FIGURE 3-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70282B-page 18 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.2 Data Address Space The PIC24HJ12GP201/202 CPU has a separate 16bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 3.4.3 “Reading Data From Program Memory Using Program Space Visibility”). PIC24HJ12GP201/202 devices implement up to 30 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16-bit-wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 3.2.3 SFR SPACE The first 2 Kbytes of the near data space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJ12GP201/202 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-21. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24HJ12GP201/202 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 3.2.4 NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 19 PIC24HJ12GP201/202 FIGURE 3-3: DATA MEMORY MAP FOR PIC24HJ12GP201/202 DEVICES WITH 1 KB RAM MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0BFF 0x0C01 0x1FFF 0x2001 0x0BFE 0x0C00 0x1FFFF 0x2000 0x07FE 0x0800 8 Kbyte Near Data Space LSB Address LSb 0x0000 16 bits 1 Kbyte SRAM Space 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70282B-page 20 Preliminary © 2007 Microchip Technology Inc. © 2007 Microchip Technology Inc. TABLE 3-1: SFR Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: CPU CORE REGISTERS MAP SFR Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register — — — DC — IPL2 — Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL1 — IPL0 — RA — N IPL3 OV PSV Z — C — Preliminary DS70282B-page 21 PIC24HJ12GP201/202 0000 0000 0000 xxxx 0000 0000 xxxx Repeat Loop Counter Register Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70282B-page 22 PIC24HJ12GP201/202 TABLE 3-2: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP202 Bit 15 CN15IE — Bit 14 CN14IE CN30IE Bit 13 CN13IE CN29IE Bit 12 CN12IE — Bit 11 CN11IE CN27IE Bit 10 —— — — Bit 9 — — — — Bit 8 — CN24IE — Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE — CN4PUE — Bit 3 CN3IE — CN3PUE — Bit 2 CN2IE — CN2PUE — Bit 1 CN1IE — CN1PUE — Bit 0 CN0IE CN16IE CN0PUE CN16PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — CN30PUE CN29PUE — CN27PUE CN24PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-3: SFR Name CNEN1 CNEN2 CNPU1 SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ12GP201 Bit 15 — — — — Bit 14 — CN30IE — Bit 13 — CN29IE — Bit 12 CN12IE — Bit 11 CN11IE — Bit 10 — — — — Bit 9 — — — — Bit 8 — — — — Bit 7 — CN23IE — Bit 6 — CN22IE — Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE — CN4PUE — Bit 3 CN3IE — Bit 2 CN2IE — Bit 1 CN1IE — Bit 0 CN0IE — All Resets 0000 0000 0000 0000 CN12PUE CN11PUE — — CN3PUE CN2PUE CN1PUE CN0PUE — — — — Preliminary © 2007 Microchip Technology Inc. CNPU2 Legend: CN30PUE CN29PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2007 Microchip Technology Inc. TABLE 3-4: SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS4 IEC0 IEC1 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC7 IPC16 INTTREG Legend: SFR Addr 0080 0082 0084 0086 008C 0094 0096 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B2 00C4 00E0 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT — — — — — — — — — — — — — — — — — — — Bit 14 — DISI — — — — — — Bit 13 — — AD1IF INT2IF — AD1IE INT2IE — T1IP T2IP U1RXIP — CNIP IC8IP — — — — — — — Bit 12 — — U1TXIF — — U1TXIE — — Bit 11 — — U1RXIF — — U1RXIE — — — — — — — — — — — — — — Bit 10 — — — — — — Bit 9 — — — — — — OC1IP OC2IP SPI1IP — — IC7IP — — — — — — Bit 8 — — T3IF — — T3IE — — Bit 7 — — T2IF IC8IF — T2IE IC8IE — — — — — — — — — — — Bit 6 DIV0ERR — OC2IF IC7IF — OC2IE IC7IE — Bit 5 — — IC2IF — — IC2IE — — IC1IP IC2IP SPI1EIP AD1IP MI2C1IP — INT2IP U1EIP — Bit 4 Bit 3 Bit 2 Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF U1EIF IC1IE U1EIE INT0IP — — T3IP U1TXIP SI2C1IP INT1IP — — — — — — — Bit 0 — INT0EP INT0IF SI2C1IF — INT0IE — All Resets 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444 MATHERR ADDRERR STKERR — — INT1IF — — INT1IE — — T1IF CNIF — T1IE CNIE — — — — — — — — — VECNUM INT2EP OC1IF — — OC1IE — — SPI1IF SPI1EIF SPI1IE SPI1EIE MI2C1IE SI2C1IE Preliminary DS70282B-page 23 ILR> PIC24HJ12GP201/202 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70282B-page 24 PIC24HJ12GP201/202 TABLE 3-5: SFR Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON Legend: SFR Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF TGATE TCKPS — TSYNC TCS — 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 Timer1 Register Period Register 1 TON — TSIDL — — — — — — Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON — — TSIDL TSIDL — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-6: SFR Name IC1BUF IC1CON IC2BUF IC2CON IC7BUF IC7CON IC8BUF IC8CON Legend: SFR Addr 0140 0142 0144 0146 0158 015A 015C 015E INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI ICI ICI ICI ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICM ICM ICM ICM 0000 xxxx 0000 xxxx 0000 xxxx 0000 Preliminary © 2007 Microchip Technology Inc. Input 1 Capture Register — — — — — — — — ICSIDL ICSIDL ICSIDL ICSIDL — — — — — — — — — — — — — — — — — — — — ICTMR ICTMR ICTMR ICTMR Input 2 Capture Register Input 7 Capture Register Input 8Capture Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-7: SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON Legend: SFR Addr 0180 0182 0184 0186 0188 018A OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — — OCFLT OCTSEL OCM 0000 xxxx xxxx — — OCFLT OCTSEL OCM 0000 Output Compare 1 Secondary Register Output Compare 1 Register — — OCSIDL — — — — — — Output Compare 2 Secondary Register Output Compare 2 Register — — OCSIDL — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2007 Microchip Technology Inc. TABLE 3-8: SFR Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: SFR Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — ACKDT D_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKEN P RCEN S Address Register Address Mask Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-9: SFR Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: SFR Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — — — Bit 13 USIDL — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR UTXINV UTXISEL0 URXISEL Preliminary DS70282B-page 25 UART Transmit Register UART Receive Register PIC24HJ12GP201/202 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-10: SFR Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: SFR Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF FRMDLY Bit 0 SPIRBF — All Resets 0000 0000 0000 0000 PPRE SPI1 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70282B-page 26 PIC24HJ12GP201/202 TABLE 3-11: File Name RPINR0 RPINR1 RPINR3 RPINR7 RPINR10 RPINR11 RPINR18 RPINR20 RPINR21 Legend: Addr 0680 0682 0686 068E 0694 0696 06A4 06A8 06AA PERIPHERAL PIN SELECT INPUT REGISTER MAP Bit 15 — — — — — — — — — Bit 14 — — — — — — — — — Bit 13 — — — — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 INT1R — T3CKR IC2R IC8R — U1CTSR SCK1R — — — — — — — Bit 9 Bit 8 Bit 7 — — — — — — — — — Bit 6 — — — — — — — — — Bit 5 — — — — — — — — — Bit 4 — Bit 3 — Bit 2 — INT2R T2CKR IC1R IC7R OCFAR U1RX SDI1R SS1R Bit 1 — Bit 0 — All Resets 1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-12: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 Legend: PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP202 Bit 15 — — — — — — — — Bit 14 — — — — — — — — Bit 13 — — — — — — — — Bit 12 Bit 11 Bit 10 RP1R RP3R RP5R RP7R RP9R RP11R RP13R RP15R Bit 9 Bit 8 Bit 7 — — — — — — — — Bit 6 — — — — — — — — Bit 5 — — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 Preliminary © 2007 Microchip Technology Inc. Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-13: File Name RPOR0 RPOR2 RPOR3 RPOR4 RPOR7 Legend: Addr 06C0 06C4 06C6 06C8 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ12GP201 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — — — Bit 12 Bit 11 Bit 10 RP1R — RP7R RP9R — — Bit 9 Bit 8 Bit 7 — — — — Bit 6 — — — — — Bit 5 — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP4R — RP8R RP14R — — Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 — — — RP15R — 06CE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-14: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFE AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330 ADC1 REGISTER MAP FOR PIC24HJ12GP201 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC BUFS — CH123SB — — — CH0NA — — — — — — — — — — — — PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 — — SIMSAM ASAM SAMP BUFM CH123NA CH0SA PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 SMPI ADCS — © 2007 Microchip Technology Inc. ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON ADRC — CH0NB — — — VCFG — — — — — — — — — — — — — — — — ADSIDL — — — — AD12B CSCNA SAMC CH123NB CH0SB — — FORM CHPS Preliminary DS70282B-page 27 PIC24HJ12GP201/202 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70282B-page 28 PIC24HJ12GP201/202 TABLE 3-15: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330 ADC1 REGISTER MAP FOR PIC24HJ12GP202 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC BUFS — CH123SB PCFG8 CSS8 — CH0NA PCFG7 CSS7 CSS9 — — — — PCFG6 CSS6 — — PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 — — SIMSAM ASAM SAMP BUFM CH123NA CH0SA PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 SMPI ADCS — ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON ADRC — CH0NB — — — VCFG — — — — — — — — — — — — — — — — ADSIDL — — — — AD12B CSCNA SAMC CH123NB CH0SB — — PCFG9 FORM CHPS Preliminary © 2007 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2007 Microchip Technology Inc. TABLE 3-16: File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 — — — — Bit 7 — — — — Bit 6 — — — — Bit 5 — — — — Bit 4 TRISA4 RA4 LATA4 ODCA4 Bit 3 TRISA3 RA3 LATA3 ODCA3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets 001F xxxx xxxx xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-17: File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE PORTB REGISTER MAP FOR PIC24HJ12GP202 Bit 15 TRISB15 RB15 LATB15 ODCB15 Bit 14 TRISB14 RB14 LATB14 ODCB14 Bit 13 TRISB13 RB13 LATB13 ODCB13 Bit 12 TRISB12 RB12 LATB12 ODCB12 Bit 11 TRISB11 RB11 LATB11 ODCB11 Bit 10 TRISB10 RB10 LATB10 ODCB10 Bit 9 TRISB9 RB9 LATB9 ODCB9 Bit 8 TRISB8 RB8 LATB8 ODCB8 Bit 7 TRISB7 RB7 LATB7 ODCB7 Bit 6 TRISB6 RB6 LATB6 ODCB6 Bit 5 TRISB5 RB5 LATB5 ODCB5 Bit 4 TRISB4 RB4 LATB4 ODCB4 Bit 3 TRISB3 RB3 LATB3 ODCB3 Bit 2 TRISB2 RB2 LATB2 ODCB2 Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets FFFF xxxx xxxx xxxx x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Preliminary DS70282B-page 29 TABLE 3-18: File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE PORTB REGISTER MAP FOR PIC24HJ12GP201 Bit 15 Bit 14 Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 TRISB9 RB9 LATB9 ODCB9 Bit 8 TRISB8 RB8 LATB8 ODCB8 Bit 7 TRISB7 RB7 LATB7 ODCB7 Bit 6 — — — — Bit 5 — — — — Bit 4 TRISB4 RB4 LATB4 ODCB4 Bit 3 — — — — Bit 2 — — — — Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets C393 xxxx xxxx xxxx PIC24HJ12GP201/202 TRISB15 TRISB14 RB15 LATB15 ODCB15 RB14 LATB14 ODCB14 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 3-19: File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0746 0748 SYSTEM CONTROL REGISTER MAP Bit 15 TRAPR — ROI — — — — Bit 14 IOPUWR Bit 13 — COSC DOZE — — — — Bit 12 — Bit 11 — — DOZEN — — — — Bit 10 — Bit 9 CM NOSC FRCDIV — — — — — Bit 8 VREGS Bit 7 EXTR Bit 6 SWR Bit 5 SWDTEN LOCK — PLLDIV TUN Bit 4 WDTO — Bit 3 SLEEP CF Bit 2 IDLE — PLLPRE Bit 1 BOR LPOSCEN Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 0040 0030 0000 CLKLOCK IOLOCK PLLPOST x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. DS70282B-page 30 PIC24HJ12GP201/202 TABLE 3-20: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR — Bit 14 WREN — Bit 13 WRERR — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — Bit 6 ERASE Bit 5 — Bit 4 — NVMKEY Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000 NVMOP x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 3-21: File Name PMD1 PMD2 Legend: Addr 0770 0772 PMD REGISTER MAP Bit 15 — IC8MD Bit 14 — IC7MD Bit 13 T3MD — Bit 12 T2MD — Bit 11 T1MD — Bit 10 — — Bit 9 — IC2MD Bit 8 — IC1MD Bit 7 I2C1MD — Bit 6 — — Bit 5 U1MD — Bit 4 — — Bit 3 SPI1MD — Bit 2 — — Bit 1 — OC2MD Bit 0 AD1MD OC1MD All Resets 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.2.5 SOFTWARE STACK 3.2.6 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 register in the PIC24HJ12GP201/202 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-1 for an overview of the BSRAM and SSRAM SFRs. 3.3 Instruction Addressing Modes The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. When an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. The addressing modes shown in Table 3-22 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 3.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 3.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. FIGURE 3-4: 0x0000 15 CALL STACK FRAME 0 Stack Grows Toward Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2007 Microchip Technology Inc. Preliminary DS70282B-page 31 PIC24HJ12GP201/202 TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA.) The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. In summary, the following addressing modes are supported by move instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. 3.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the addressing modes supported by most MCU instructions, MOV instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). 3.3.4 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. DS70282B-page 32 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.4 Interfacing Program and Data Memory Spaces 3.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-23 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. The PIC24HJ12GP201/202 architecture uses a 24-bitwide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24HJ12GP201/ 202 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 3-23: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address 0 0xx xxxx TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx 0 0 PSVPAG xxxx xxxx PC xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 33 PIC24HJ12GP201/202 FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70282B-page 34 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom byte’, will always be ‘0’. In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, as in the TBLRDL instruction. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bitwide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). FIGURE 3-6: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 23 15 0 02 0x000000 00000000 00000000 00000000 00000000 23 16 8 0 0x020000 0x030000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 © 2007 Microchip Technology Inc. Preliminary DS70282B-page 35 PIC24HJ12GP201/202 3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data to execute in a single cycle. FIGURE 3-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 DS70282B-page 36 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 4.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC24HJ12GP201/202 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest PIC24H Family Reference Manual chapters. then program the digital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 4.1 The PIC24HJ12GP201/202 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ12GP201/202 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/PGD1, PGC2/PGD2 or PGC3/PGD3), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 4-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select © 2007 Microchip Technology Inc. Preliminary DS70282B-page 37 PIC24HJ12GP201/202 4.2 RTSP Operation 4.3 Control Registers The PIC24HJ12GP201/202 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. Two SFRs are used to read and write the program Flash memory: • NVMCON: Flash Memory Control Register • NVMKEY: NonVolatile Memory Key Register The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 4-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.4 “Programming Operations” for further details. 4.4 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 4 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. DS70282B-page 38 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 REGISTER 4-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Satiable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) R/W-0(1) R/W-0(1) (2) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) bit 0 WREN R/W-0(1) NVMOP WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command Unimplemented: Read as ‘0’ NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: These bits can only be Reset on POR. All other combinations of NVMOP are unimplemented. © 2007 Microchip Technology Inc. Preliminary DS70282B-page 39 PIC24HJ12GP201/202 REGISTER 4-2: U-0 — bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 SO = Satiable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0 NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 NVMKEY Unimplemented: Read as ‘0’ NVMKEY: Key Register (write-only) bits DS70282B-page 40 Preliminary © 2007 Microchip Technology Inc. PIC24HJ12GP201/202 4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3. EXAMPLE 4-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority -1 2 2 — -77 59 63 — 10.95 -1 >-1 1.25 -2 — 12 data bits — — 1.5 -1.5 — 12 data bits — — 3 3 — -69 63 72 — 11.1 +1 -1 1 1 — 10 data bits — — 3 2 — 10 data bits — — ±5 ±2 — -64 57 67 — 9.7 +1