PIC24HJ32GP202/204 and PIC24HJ16GP304 Data Sheet
High-Performance, 16-bit Microcontrollers
© 2007 Microchip Technology Inc.
Preliminary
DS70289A
Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”
• •
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.
Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Linear Active Thermistor, Migratable Memory, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2007, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper.
Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.
DS70289A-page ii
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 AND PIC24HJ16GP304
High-Performance, 16-bit Microcontrollers
Operating Range:
• Up to 40 MIPS operation (@ 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C)
Digital I/O:
• • • • • • • Peripheral Pin Select Functionality Up to 35 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 21 pins Output pins can drive from 3.0V to 3.6V Up to 5V output with open drain configuration All digital input pins are 5V tolerant 4 mA sink on all I/O pins
High-Performance CPU:
• • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions, mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Flexible and powerful addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit shifts for up to 40-bit data
System Management:
• Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources
Power Management:
• On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up
Interrupt Controller:
• • • • • • 5-cycle latency 118 interrupt vectors Up to 21 available interrupt sources Up to 3 external interrupts 7 programmable priority levels 4 processor exceptions
Timers/Capture/Compare:
• Timer/Counters, up to three 16-bit timers: - Can pair up to make one 32-bit timer - 1 timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to 4 channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to 2 channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM Mode
On-Chip Flash and SRAM:
• Flash program memory (up to 32 Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 1
PIC24HJ32GP202/204 and PIC24HJ16GP304
Communication Modules:
• 4-wire SPI - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS
Analog-to-Digital Converters (ADCs):
• 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - 2 and 4 simultaneous samples (10-bit ADC) - Up to 13 input channels with auto-scanning - Conversion start can be manual or synchronized with 1 of 4 trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity
CMOS Flash Technology:
• • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and extended temperature Low-power consumption
Packaging:
• 28-pin SDIP/SOIC/QFN-S • 44-pin QFN/TQFP Note: See the device variant tables for exact peripheral features per device.
DS70289A-page 2
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
PIC24HJ32GP202/204 and PIC24HJ16GP304 Product Families
The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams.
TABLE 1:
PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES
Program Flash Memory (Kbyte) 10-Bit/12-Bit ADC Remappable Peripherals Output Compare Std. PWM Input Capture Remappable Pins 16-bit Timer I/O Pins (Max)
UART
PIC24HJ32GP202
28
32
2
16
3(1)
4
2
1
SPI
Device
1
1 ADC, 10 ch
1
21
SDIP SOIC QFN-S QFN TQFP QFN TQFP
PIC24HJ32GP204 PIC24HJ16GP304
44 44
32 16
2 2
26 26
3(1) 3(1)
4 4
2 2
1 1
1 1
1 ADC, 13 ch 1 ADC, 13 ch
1 1
35 35
Note 1:
Only 2 out of 3 timers are Remappable
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 3
Packages
I2C™
RAM
Pins
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams
28-Pin SDIP, SOIC
MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 SOSCI/RP4/CN1/RB4 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5/CN27/RB5
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16 / RB10 VCAP/VDDCORE VSS TDO/SDA1/RP9/CN21/RB9 TCK/SCL1/RP8/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6/CN24/RB6
PIC24HFJ32GP202
28-Pin QFN-S
28 27 26 25 24 23 22 PGED1/AN2/C2IN-/RP0/CN4/RB0 PGEC1/AN3/C2IN+/RP1/CN5/RB1 AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 1 2 3 4 5 6 7 8 SOSCI/RP4/CN1/RB4 9 10 11 12 13 14 PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 TCK/SCL1/RP8/CN22/RB8 SOSCO/T1CK/CN0/RA4 VDD 21 20 19 18 17 16 15 AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/TMS/RP11/CN15/RB11 PGED2/TDI/RP10/CN16/RB10 VCAP/VDDCORE Vss TDO/SDA1/RP9/CN21/RB9
PIC24HJ32GP202
DS70289A-page 4
Preliminary
AN10/RP14/CN12/RB14
AVSS AN9/RP15/CN11/RB15
AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR
AVDD
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams (Continued)
44-Pin TQFP
PGEC1/AN3/C2IN+/RP1/CN5/RB1 PGED1/AN2/C2IN-/RP0/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 TCK/RA7 TMS/RA10 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1
34 35 36 37
© 2007 Microchip Technology Inc.
SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19/CN28/RC3 RP20/CN25/RC4 RP21/CN26/RC5 VSS VDD PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 SCL1/RP8/CN22/RB8
Preliminary
38 39 40 41 42 43 44
AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 VDD VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4
23 24 25 26 27 28 29 30 31 32 33
PIC24HJ32GP204 PIC24HJ16GP304
AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/RP11/CN15/RB11 PGED2/RP10/CN16/RB10 VCAP/VDDCORE VSS RP25/CN19/RC9 RP24/CN20/RC8 RP23/CN17/RC7 RP22/CN18/RC6 SDA1/RP9/CN21/RB9
DS70289A-page 5
PIC24HJ32GP202/204 and PIC24HJ16GP304
Pin Diagrams (Continued)
44-Pin TQFP
PGEC1/AN3/C2IN+/RP1/CN5/RB1 PGED1/AN2/C2IN-/RP0/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/RB15 AN10/RP14/CN12/RB14 TCK/RA7 TMS/RA10 12 13 14 15 16 17 18 19 20 21 22 11 10 9 8 7 6 5 4 3 2 1
SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19/CN28/RC3 RP20/CN25/RC4 RP21/CN26/RC5 VSS VDD PGED3/ASDA1/RP5/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7/CN23/RB7 SCL1/RP8/CN22/RB8
34 35 36 37 38 39 40 41 42 43 44
AN4/RP2/CN6/RB2 AN5/RP3/CN7/RB3 AN6/RP16/CN8/RC0 AN7/RP17/CN9/RC1 AN8/RP18/CN10/RC2 VDD VSS OSCI/CLKI/CN30/RA2 OSCO/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4/CN1/RB4
23 24 25 26 27 28 29 30 31 32 33
PIC24HJ32GP204 PIC24HJ16GP304
AN11/RP13/CN13/RB13 AN12/RP12/CN14/RB12 PGEC2/RP11/CN15/RB11 PGED2/RP10/CN16/RB10 VCAP/VDDCORE VSS RP25/CN19/RC9 RP24/CN20/RC8 RP23/CN17/RC7 RP22/CN18/RC6 SDA1/RP9/CN21/RB9
DS70289A-page 6
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Table of Contents
1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU............................................................................................................................................................................................ 13 3.0 Memory Organization ................................................................................................................................................................. 19 4.0 Flash Program Memory.............................................................................................................................................................. 41 5.0 Resets ....................................................................................................................................................................................... 47 6.0 Interrupt Controller ..................................................................................................................................................................... 53 7.0 Oscillator Configuration .............................................................................................................................................................. 81 8.0 Power-Saving Features.............................................................................................................................................................. 91 9.0 I/O Ports ..................................................................................................................................................................................... 93 10.0 Timer1 ...................................................................................................................................................................................... 117 11.0 Timer2/3 Feature...................................................................................................................................................................... 119 12.0 Input Capture............................................................................................................................................................................ 125 13.0 Output Compare....................................................................................................................................................................... 127 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 133 15.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 141 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 151 17.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 159 18.0 Special Features ...................................................................................................................................................................... 173 19.0 Instruction Set Summary .......................................................................................................................................................... 181 20.0 Development Support............................................................................................................................................................... 189 21.0 Electrical Characteristics .......................................................................................................................................................... 193 22.0 Packaging Information.............................................................................................................................................................. 227 Appendix A: Revision History............................................................................................................................................................. 233 Index ................................................................................................................................................................................................. 235 The Microchip Web Site ..................................................................................................................................................................... 239 Customer Change Notification Service .............................................................................................................................................. 239 Customer Support .............................................................................................................................................................................. 239 Reader Response .............................................................................................................................................................................. 240 Product Identification System ............................................................................................................................................................ 241
TO OUR VALUED CUSTOMERS
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Most Current Data Sheet
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Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using.
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© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 7
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 8
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
1.0
Note:
DEVICE OVERVIEW
This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”.
This document contains device-specific information for the following devices: • PIC24HJ32GP202 • PIC24HJ32GP204 • PIC24HJ16GP304 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 9
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 1-1:
PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch
16 PORTB
PIC24HJ32GP202/204 AND PIC24HJ16GP304 BLOCK DIAGRAM
Data Bus 16 Data Latch
PORTA
16
16
23
16 Address Generator Units
Remappable Pins
Address Latch
Program Memory Address Bus Data Latch 24 ROM Latch 16
Literal Data
EA MUX
16
Instruction Decode & Control Control Signals to Various Blocks
OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Instruction Reg
16
17 x 17 Multiplier 16 x 16 W Register Array 16
Divide Support
16-bit ALU 16
VDDCORE/VCAP
VDD, VSS
MCLR
Timers 1-3
ADC1
UART1
IC1,2,7,8
OC/ PWM1,2
CNx
SPI1
I2C1
Note:
Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device.
DS70289A-page 10
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 1-1:
Pin Name AN0-AN12 CLKI CLKO
PINOUT I/O DESCRIPTIONS
Pin Type I I O Buffer Type Analog ST/CMOS — Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture inputs 1/2 Capture inputs 7/8 Compare Fault A input (for Compare Channels 1 and 2). Compare outputs 1 through 2. External interrupt 0. External interrupt 1. External interrupt 2. PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Description
OSC1 OSC2 SOSCI SOSCO CN0-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RA7-RA15 RB0-RB15 RC0-RC9 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SS1 SCL1 SDA1 ASCL1 ASDA1 TMS TCK TDI TDO PGD1/EMUD1 PGC1/EMUC1 PGD2/EMUD2 PGC2/EMUC2 PGD3/EMUD3 PGC3/EMUC3 VDDCORE VSS VREF+ VREF-
I I/O I O I I I O I I I I/O I/O I/O I I I I O I O I/O I O I/O I/O I/O I/O I/O I I I O I/O I I/O I I/O I P P I I
ST/CMOS — ST/CMOS — ST ST ST — ST ST ST ST ST ST ST ST ST ST — ST — ST ST — ST ST ST ST ST ST ST ST — ST ST ST ST ST ST — — Analog Analog
Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels
Analog = Analog input I = Input
O = Output P = Power
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 11
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 1-1:
Pin Name AVDD MCLR AVSS VDD
PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Type P I/P P P Buffer Type P ST P — Description Positive supply for analog modules. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins.
Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels
Analog = Analog input I = Input
O = Output P = Power
DS70289A-page 12
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.0
Note:
CPU
This data sheet summarizes the features of this group of PIC24HJ32GP202/204 and PIC24HJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”.
2.1
Data Addressing Overview
The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU modules have a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, singlecycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJ32GP202/204 and PIC24HJ16GP304 instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJ32GP202/204 and PIC24HJ16GP304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 2-1, and the programmer’s model for the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 is shown in Figure 2-2.
The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but this may be used as general purpose RAM.
2.2
Special MCU Features
The PIC24HJ32GP202/204 and PIC24HJ16GP304 feature a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixedsign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. The PIC24HJ32GP202/204 and PIC24HJ16GP304 supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 13
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 2-1:
PSV & Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 X Data Bus
PIC24HJ32GP202/204 AND PIC24HJ16GP304 CPU CORE BLOCK DIAGRAM
16
16 Data Latch X RAM Address Latch 16
23 16 Address Latch Address Generator Units
Program Memory Address Bus Data Latch 24 ROM Latch 16 Literal Data 16 EA MUX
Instruction Decode & Control
Instruction Reg 17 x 17 Multiplier
16
Control Signals to Various Blocks
Divide Support
16 x 16 W Register Array 16
16-bit ALU 16
To Peripheral Modules
DS70289A-page 14
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 2-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL
D15 W0/WREG W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers
DO Shadow
D0
PUSH.S Shadow
Legend
PC22 0 TBLPAG 7 PSVPAG 0 Data Table Page Address
PC0 0 Program Counter
7
Program Space Visibility Page Address 15 RCOUNT 0 REPEAT Loop Counter
15 CORCON
0 Core Configuration Register
—
—
—
—
—
—
— DC
IPL2 IPL1 IPL0 RA SRL
N
OV
Z
C
STATUS Register
SRH
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 15
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.3 CPU Control Registers
SR: CPU STATUS REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(2) IPL(2) bit 7 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set bit 15-9 bit 8 R = Readable bit W = Writable bit ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown R/W-0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 U-0 — bit 15 R/W-0(1)
REGISTER 2-1:
bit 7-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. 2: The IPL Status bits are read only when NSTDIS = 1 (INTCON1).
DS70289A-page 16
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 2-2:
U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 C = Clear only bit W = Writable bit ‘x = Bit is unknown
CORCON: CORE CONTROL REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0
-n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’
Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 17
PIC24HJ32GP202/204 and PIC24HJ16GP304
2.4 Arithmetic Logic Unit (ALU)
2.4.2 DIVIDER
The PIC24HJ32GP202/204 and PIC24HJ16GP304 Arithmetic Logic Unit (ALU) is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. The ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register depending on the operation. The C and DC Status bits operate as Borrow and Digit Borrow bits respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for more information on the SR bits affected by each instruction. The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and a support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes. 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide
The quotient for all divide instructions ends up in W0 and the remainder in W1. A 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/ 16-bit and 16-bit/16-bit instructions take the same number of cycles to execute.
2.4.3
MULTI-BIT DATA SHIFTER
The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. and a negative value shifts the operand left. A value of ‘0’ does not modify the operand.
2.4.1
MULTIPLIER
Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned
DS70289A-page 18
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.0
Note:
MEMORY ORGANIZATION
This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”.
3.1
Program Address Space
The program address memory space of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 3.4 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices are shown in Figure 3-1.
The PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution.
FIGURE 3-1:
PROGRAM MEMORY FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES
PIC24HJ32GP202/204 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
PIC24HJ16GP304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table
User Memory Space
0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200
User Memory Space
User Program Flash Memory (11264 instructions)
0x0057FE 0x005800
User Program Flash Memory (5632 instructions)
0x002BFE 0x002C00
Unimplemented (Read ‘0’s)
Unimplemented (Read ‘0’s)
0x7FFFFE 0x800000
0x7FFFFE 0x800000
Reserved
Configuration Memory Space Configuration Memory Space
Reserved
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Device Configuration Registers
0xF7FFFE 0xF80000 0xF80017 0xF80018
Reserved
Reserved
DEVID (2)
0xFEFFFE 0xFF0000 0xFFFFFE
DEVID (2)
0xFEFFFE 0xFF0000 0xFFFFFE
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 19
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.2 INTERRUPT AND TRAP VECTORS
All PIC24HJ32GP202/204 and PIC24HJ16GP304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ32GP202/204 and PIC24HJ16GP304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). Section 6.1 “Interrupt Vector Table” provides a more detailed discussion of the interrupt vector tables.
The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (See Figure 3-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible.
FIGURE 3-2:
msw Address 0x000001 0x000003 0x000005 0x000007
PROGRAM MEMORY ORGANIZATION
most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address)
DS70289A-page 20
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.2 Data Address Space
The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU has a separate 16-bit-wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to the bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 3.4.3 “Reading Data From Program Memory Using Program Space Visibility”). PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement up to 30 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or when translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address.
3.2.1
DATA SPACE WIDTH
The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses.
3.2.3
SFR SPACE
The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJ32GP202/204 and PIC24HJ16GP304 core and peripheral modules to control the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 3-1 through Table 3-21. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information.
3.2.2
DATA MEMORY ORGANIZATION AND ALIGNMENT
To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24HJ32GP202/204 and PIC24HJ16GP304 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through wordaligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [WS++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address.
3.2.4
NEAR DATA SPACE
The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 21
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 3-3: DATA MEMORY MAP FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES WITH 2 KB RAM
MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 0x1FFF 0x2001 0x0FFE 0x1000 0x1FFE 0x2000 0x07FE 0x0800 8 Kbyte Near data space LSB Address LSb 0x0000
16 bits
2 Kbyte SRAM Space
0x8001
0x8000
Optionally Mapped into Program Memory
X Data Unimplemented (X)
0xFFFF
0xFFFE
DS70289A-page 22
Preliminary
© 2007 Microchip Technology Inc.
TABLE 3-1:
Bit 14 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register — — — — — — — — — — — — — — — — — DC — — — — — — IPL2 — — — — — — — — — — — — — Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL1 — IPL0 — Disable Interrupts Counter Register RA — N IPL3 OV PSV Z — C — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
CPU CORE REGISTERS MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 0000 0000 0000 xxxx 0000 0000 xxxx
SFR Name
SFR Addr
Bit 15
WREG0
0000
WREG1
0002
WREG2
0004
WREG3
0006
WREG4
0008
WREG5
000A
© 2007 Microchip Technology Inc.
Repeat Loop Counter Register
WREG6
000C
WREG7
000E
WREG8
0010
WREG9
0012
WREG10
0014
WREG11
0016
WREG12
0018
WREG13
001A
WREG14
001C
WREG15
001E
SPLIM
0020
PCL
002E
PCH
0030
—
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
TBLPAG
0032
—
PSVPAG
0034
—
RCOUNT
0036
SR
0042
—
CORCON
0044
—
DISICNT
0052
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70289A-page 23
TABLE 3-2:
Bit 13 CN13IE —— — — — CN24PUE CN23PUE CN22PUE CN21PUE — — — — — — CN7PUE CN6PUE CN5PUE CN4PUE CN3PUE CN2PUE CN1PUE — CN24IE — — — — CN23IE CN22IE CN21IE CN16IE CN0PUE CN16PUE — — CN29IE — CN27PUE CN27IE CN12IE CN11IE CN7IE CN6IE CN5IE CN4IE CN3IE CN2IE CN1IE CN0IE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ32GP202
SFR Name
SFR Addr
Bit 15
Bit 14
CNEN1
0060
CN15IE
CN14IE
DS70289A-page 24
— Bit 13 CN13IE CN29IE CN6PUE CN5PUE CN4PUE CN28IE CN27IE CN26IE CN25IE CN24IE CN23IE CN22IE CN21IE CN20IE CN12IE CN11IE CN10IE CN9IE CN8IE CN7IE CN6IE CN5IE CN4IE CN3IE CN19IE CN3PUE Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000
CNEN2
0062
—
CN30IE
CNPU1
0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CNPU2
006A
—
CN30PUE CN29PUE
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-3:
CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304
SFR Name
SFR Addr
Bit 15
Bit 14
CNEN1
0060
CN15IE
CN14IE
CNEN2
0062
—
CN30IE
CNPU1
0068
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE
CNPU2
006A
—
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2007 Microchip Technology Inc.
TABLE 3-4:
Bit 13 — DIV0ERR — OC2IF IC7IF — OC2IE IC7IE — IC1IP IC2IP SPI1EIP AD1IP MI2C1IP — INT2IP U1EIP — — — — — — — — — VECNUM — — — — — — — — INT1IE CNIE — — IC2IE — T1IE OC1IE — — — — — INT1IF CNIF — IC2IF — T1IF OC1IF IC1IF MI2C1IF U1EIF IC1IE U1EIE INT0IP — T3IP U1TXIP SI2C1IP INT1IP — — — — — — — — INT2EP INT1EP — MATHERR ADDRERR STKERR OSCFAIL — AD1IF INT2IF — AD1IE INT2IE — T1IP T2IP U1RXIP — CNIP IC8IP — — — — ILR> — — — — — — — — — — — — — — IC7IP — — — — — — — — — — — — — SPI1IP — — OC2IP — — OC1IP — — — — — — — — — — — — IC8IE U1TXIE U1RXIE SPI1IE SPI1EIE T3IE T2IE — — — — — — — — — — — IC8IF U1TXIF U1RXIF SPI1IF SPI1EIF T3IF T2IF — — — — — — — — — — — — — INT0EP INT0IF SI2C1IF — INT0IE MI2C1IE SI2C1IE — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
INTERRUPT CONTROLLER REGISTER MAP
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 4444 4444 4444 4444 4444 4444
SFR Name
SFR Addr
Bit 15
Bit 14
INTCON1
0080
NSTDIS
—
INTCON2
0082
ALTIVT
DISI
IFS0
0084
—
—
IFS1
0086
—
—
IFS4
008C
—
—
IEC0
0094
—
—
© 2007 Microchip Technology Inc.
IEC1
0096
—
—
IEC4
009C
—
—
IPC0
00A4
—
IPC1
00A6
—
IPC2
00A8
—
IPC3
00AA
—
—
IPC4
00AC
—
IPC5
00AE
—
IPC7
00B2
—
—
IPC16
00C4
—
—
INTTREG
00E0
—
—
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70289A-page 25
TABLE 3-5:
Bit 14 Timer1 Register Period Register 1 — Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 — — TSIDL — — — — — — TGATE TCKPS — TSIDL — — — — — — TGATE TCKPS T32 — — TCS TCS — — TSIDL — — — — — — TGATE TCKPS — TSYNC TCS — Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF 0000 xxxx xxxx xxxx FFFF FFFF 0000 0000
TIMER REGISTER MAP
SFR Name
SFR Addr
Bit 15
TMR1
0100
DS70289A-page 26
Bit 14 Input 1 Capture Register — Input 2 Capture Register — Input 7 Capture Register — Input 8Capture Register — ICSIDL — — — — — ICTMR ICI ICOV ICBNE ICM ICSIDL — — — — — ICTMR ICI ICOV ICBNE ICM ICSIDL — — — — — ICTMR ICI ICOV ICBNE ICM ICSIDL — — — — — ICTMR ICI ICOV ICBNE ICM Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx Output Compare 1 Register — OCSIDL — — — — — — Output Compare 2 Register — OCSIDL — — — — — — — — OCFLT OCTSEL OCM — Output Compare 2 Secondary Register — OCFLT OCTSEL OCM xxxx 0000 xxxx xxxx 0000 Output Compare 1 Secondary Register
PR1
0102
T1CON
0104
TON
TMR2
0106
TMR3HLD
0108
TMR3
010A
PR2
010C
PR3
010E
T2CON
0110
TON
T3CON
0112
TON
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-6:
INPUT CAPTURE REGISTER MAP
SFR Name
SFR Addr
Bit 15
IC1BUF
0140
IC1CON
0142
—
IC2BUF
0144
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
IC2CON
0146
—
IC7BUF
0158
IC7CON
015A
—
IC8BUF
015C
IC8CON
015E
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-7:
OUTPUT COMPARE REGISTER MAP
SFR Name
SFR Addr
Bit 15
OC1RS
0180
OC1R
0182
OC1CON
0184
—
OC2RS
0186
OC2R
0188
OC2CON
018A
—
© 2007 Microchip Technology Inc.
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-8:
Bit 13 — — — I2CSIDL — — — — — — Address Mask Register — — — Address Register — — BCL GCSTAT ADD10 IWCOL I2COV D_A P S R_W SCLREL IPMIEN A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN RBF — — — — Baud Rate Generator Register SEN TBF — — — — — Transmit Register — — — — — Receive Register Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
I2C1 REGISTER MAP
All Resets 0000 00FF 0000 1000 0000 0000 0000
SFR Name — — — — — —
SFR Addr
Bit 15
Bit 14
I2C1RCV
0200
—
I2C1TRN
0202
—
I2C1BRG
0204
—
I2C1CON
0206
I2CEN
I2C1STAT
0208
ACKSTAT
TRSTAT
I2C1ADD
020A
—
© 2007 Microchip Technology Inc.
Bit 13 USIDL — — — Baud Rate Generator Prescaler — — — — — — UTXBRK UTXEN UTXBF TRMT URXISEL ADDEN — — IREN RTSMD — UEN1 UEN0 WAKE LPBACK ABAUD Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 PDSEL FERR OERR Bit 0 STSEL URXDA — — — UART Transmit Register UART Receive Register Bit 13 SPISIDL — FRMPOL — — — — DISSCK DISSDO MODE16 SMP CKE — — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF FRMDLY Bit 0 SPIRBF PPRE — — — SPI1 Transmit and Receive Buffer Register
I2C1MSK
020C
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-9:
UART1 REGISTER MAP
All Resets 0000 0110 xxxx 0000 0000
SFR Name
SFR Addr
Bit 15
Bit 14
U1MODE
0220
UARTEN
U1STA
0222
UTXISEL1
UTXINV UTXISEL0
U1TXREG
0224
—
U1RXREG
0226
—
U1BRG
0228
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-10:
SPI1 REGISTER MAP
All Resets 0000 0000 0000 0000
SFR Name
SFR Addr
Bit 15
Bit 14
SPI1STAT
0240
SPIEN
SPI1CON1
0242
—
SPI1CON2
0244
FRMEN
SPIFSD
SPI1BUF
0248
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70289A-page 27
TABLE 3-11:
Bit 13 — — — — — — — — — — — — — — — — — SCK1R — — — U1CTSR — — — U1RX SDI1R SS1R — — — — — — — — OCFAR IC8R — — — IC7R IC2R — — — IC1R T3CKR — — — T2CKR — — — — — — — — INT2R INT1R — — — — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F
PERIPHERAL PIN SELECT INPUT REGISTER MAP
File Name
Addr
Bit 15
Bit 14
RPINR0
0680
—
—
DS70289A-page 28
Bit 13 — — — — — — — — RP15R — RP13R — RP11R — RP9R — — — — — RP7R — — RP5R — — RP3R — — — — — — — — — RP1R — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000
RPINR1
0682
—
—
RPINR3
0686
—
—
RPINR7
068E
—
—
RPINR10
0694
—
—
RPINR11
0696
—
—
RPINR18
06A4
—
—
RPINR20
06A8
—
—
RPINR21
06AA
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-12:
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ32GP202
File Name
Addr
Bit 15
Bit 14
RPOR0
06C0
—
—
RPOR1
06C2
—
—
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
RPOR2
06C4
—
—
RPOR3
06C6
—
—
RPOR4
06C8
—
—
RPOR5
06CA
—
—
RPOR6
06CC
—
—
RPOR7
06CE
—
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2007 Microchip Technology Inc.
TABLE 3-13:
Bit 13 — — — — — — — — — — — — — — RP23R — — — RP21R — — — RP19R — — — RP17R — — — RP15R — — — RP13R — — — RP11R — — — RP10R RP12R RP14R RP16R RP18R RP20R RP22R RP24R RP9R — — — RP8R RP7R — — — RP6R RP5R — — — RP4R RP3R — — — RP2R RP1R — — — RP0R Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304
All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
RPOR0
06C0
—
—
RPOR1
06C2
—
—
RPOR2
06C4
—
—
RPOR3
06C6
—
—
RPOR4
06C8
—
—
RPOR5
06CA
—
—
© 2007 Microchip Technology Inc.
RPOR6
06CC
—
—
RPOR7
06CE
—
—
RPOR8
06D0
—
—
RPOR9
06D2
—
—
RPOR10
06D4
—
—
RPOR11
06D6
—
—
RPOR12
Legend:
— — — RP25R — 06D8 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
DS70289A-page 29
TABLE 3-14:
Bit 13 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 — — — — — — — CSS12 CSS11 CSS10 CSS9 CSS8 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 CH0SB — — CH123NB CH123SB — CH0NA PCFG7 CSS7 SAMC — — PCFG6 CSS6 — — PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 — CSCNA CHPS BUFS — — — — — — ADSIDL — — AD12B FORM SSRC — SIMSAM SMPI ADCS — — CH123NA CH0SA PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA ASAM SAMP BUFM DONE ALTS Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000
ADC1 REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304
File Name
Addr
Bit 15
Bit 14
ADC1BUF0
0300
DS70289A-page 30
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
ADC1BUF5
030A
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFE
031E
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
AD1CON1
0320
ADON
AD1CON2
0322
VCFG
AD1CON3
0324
ADRC
AD1CHS123
0326
—
AD1CHS0
0328
CH0NB
AD1PCFGL
032C
—
AD1CSSL
0330
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
© 2007 Microchip Technology Inc.
TABLE 3-15:
Bit 13 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 — — — — — — — CSS12 CSS11 CSS10 CSS9 — PCFG12 PCFG11 PCFG10 PCFG9 — CH0SB — — CH123NB CH123SB — CH0NA — — SAMC — — — — — — PCFG5 CSS5 PCFG4 CSS4 PCFG3 CSS3 — CSCNA CHPS BUFS — — — — — ADSIDL — — AD12B FORM SSRC — — SIMSAM SMPI ADCS — — CH123NA CH0SA PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA ASAM SAMP BUFM DONE ALTS Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ADC1 REGISTER MAP FOR PIC24HJ32GP202
All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000
File Name
Addr
Bit 15
Bit 14
ADC1BUF0
0300
ADC1BUF1
0302
ADC1BUF2
0304
ADC1BUF3
0306
ADC1BUF4
0308
© 2007 Microchip Technology Inc.
ADC1BUF5
030A
ADC1BUF6
030C
ADC1BUF7
030E
ADC1BUF8
0310
ADC1BUF9
0312
ADC1BUFA
0314
ADC1BUFB
0316
ADC1BUFC
0318
ADC1BUFD
031A
ADC1BUFE
031C
ADC1BUFF
031E
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
AD1CON1
0320
ADON
AD1CON2
0322
VCFG
AD1CON3
0324
ADRC
AD1CHS123
0326
—
AD1CHS0
0328
CH0NB
AD1PCFGL
032C
—
AD1CSSL
0330
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
DS70289A-page 31
TABLE 3-16:
Bit 13 — TRISA4 RA4 LATA4 ODCA4 ODCA3 ODCA2 ODCA1 LATA3 LATA2 LATA1 RA3 RA2 RA1 RA0 LATA0 ODCA0 TRISA3 TRISA2 TRISA1 TRISA0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 001F xxxx xxxx xxxx
PORTA REGISTER MAP FOR PIC24HJ32GP202
File Name — — — —
Addr
Bit 15
Bit 14
TRISA
02C0
—
DS70289A-page 32
Bit 13 — TRISA10 RA10 LATA10 ODCA10 ODCA9 ODCA8 ODCA7 — — ODCA4 LATA9 LATA8 LATA7 — — LATA4 RA9 RA8 RA7 — — RA4 RA3 LATA3 ODCA3 TRISA9 TRISA8 TRISA7 TRISA4 — — — — — — — — — — — — — TRISA3 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets 079F xxxx xxxx xxxx — — — — Bit 13 TRISB13 RB13 LATB13 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 RB12 RB11 RB10 RB9 RB8 RB7 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 RB6 LATB6 ODCB6 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 TRISB5 RB5 LATB5 ODCB5 Bit 4 TRISB4 RB4 LATB4 ODCB4 Bit 3 TRISB3 RB3 LATB3 ODCB3 Bit 2 TRISB2 RB2 LATB2 ODCB2 Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets FFFF xxxx xxxx xxxx Bit 13 — — — — — — — — — — — — — — — — TRISC9 RC9 LATC9 ODCC9 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 TRISC8 RC8 LATC8 ODCC8 Bit 7 TRISC7 RC7 LATC7 ODCC7 Bit 6 TRISC6 RC6 LATC6 ODCC6 Bit 5 TRISC5 RC5 LATC5 ODCC5 Bit 4 TRISC4 RC4 LATC4 ODCC4 Bit 3 TRISC3 RC4 LATC4 ODCC4 Bit 2 TRISC2 RC2 LATC2 ODCC2 Bit 1 TRISC1 RC1 LATC1 ODCC1 Bit 0 TRISC0 RC0 LATC0 ODCC0 All Resets 03FF xxxx xxxx xxxx — — — —
PORTA
02C2
—
LATA
02C4
—
ODCA
02C6
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-17:
PORTA REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304
File Name
Addr
Bit 15
Bit 14
TRISA
02C0
—
PORTA
02C2
—
LATA
02C4
—
ODCA
02C6
—
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-18:
PORTB REGISTER MAP
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
File Name
Addr
Bit 15
Bit 14
TRISB
02C8
TRISB15
TRISB14
PORTB
02CA
RB15
RB14
LATB
02CC
LATB15
LATB14
ODCB
02CE
ODCB15
ODCB14
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices.
TABLE 3-19:
PORTC REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304
File Name
Addr
Bit 15
Bit 14
TRISC
02D0
—
PORTC
02D2
—
LATC
02D4
—
ODCC
02D6
—
© 2007 Microchip Technology Inc.
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
TABLE 3-20:
Bit 13 WRERR — — — — — — NVMKEY — — — — — — ERASE — — NVMOP Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
NVM REGISTER MAP
All Resets 0000(1) 0000
File Name
Addr
Bit 15
Bit 14
NVMCON —
0760
WR
WREN
NVMKEY
0766
—
© 2007 Microchip Technology Inc.
Bit 13 T3MD — — — — IC2MD IC1MD — — — — T2MD T1MD — I2C1MD U1MD — — — — Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 SPI1MD — Bit 2 — — Bit 1 — OC2MD Bit 0 AD1MD OC1MD
Legend: Note 1:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset.
TABLE 3-21:
PMD REGISTER MAP
All Resets 0000 0000
File Name
Addr
Bit 15
Bit 14
PMD1
0770
—
—
PMD2
0772
IC8MD
IC7MD
Legend:
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
PIC24HJ32GP202/204 and PIC24HJ16GP304
Preliminary
DS70289A-page 33
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.2.5 SOFTWARE STACK 3.2.6 DATA RAM PROTECTION FEATURE
In addition to its use as a working register, the W15 register in the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and postincrements for stack pushes, as shown in Figure 3-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 3-1 for an overview of the BSRAM and SSRAM SFRs.
3.3
Instruction Addressing Modes
The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. Similarly, the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word aligned. When an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be lesser than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15.
The addressing modes shown in Table 3-22 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types.
3.3.1
FILE REGISTER INSTRUCTIONS
Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space.
3.3.2
MCU INSTRUCTIONS
The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where, Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes.
FIGURE 3-4:
0x0000 15
CALL STACK FRAME
0
Stack Grows Toward Higher Address
PC 000000000 PC
W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++]
DS70289A-page 34
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
TABLE 3-22: FUNDAMENTAL ADDRESSING MODES SUPPORTED
Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA.) The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified
Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. In summary, move instructions support the following addressing modes: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes.
3.3.3
MOVE (MOV) INSTRUCTION
Move instructions provide a greater degree of addressing flexibility than the other instructions. In addition to the Addressing modes supported by most MCU instructions, MOV instructions also support Register Indirect with Register Offset Addressing mode. This is also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and the destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one).
3.3.4
OTHER INSTRUCTIONS
Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 35
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.4 Interfacing Program and Data Memory Spaces
3.4.1 ADDRESSING PROGRAM SPACE
Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-23 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word.
The PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture uses a 24-bit-wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, which means that the data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24HJ32GP202/ 204 and PIC24HJ16GP304 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the Least Significant word of the program word.
TABLE 3-23:
PROGRAM SPACE ADDRESS CONSTRUCTION
Access Space User User Configuration Program Space Address 0 0xx xxxx TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx 0 0 PSVPAG xxxx xxxx PC xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0
Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write)
Program Space Visibility (Block Remap/Read) Note 1:
User
Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG.
DS70289A-page 36
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION
Program Counter(1)
0
Program Counter 23 bits EA
0
1/0
Table Operations(2)
1/0
TBLPAG 8 bits 24 bits 16 bits
Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits
1
EA
0
15 bits 23 bits
User/Configuration Space Select
Byte Select
Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 37
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS
In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom byte’, will always be ‘0’. In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, as in the TBLRDL instruction. Note that the data will always be ‘0’ when the upper ‘Phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space.
The TBLRDL and TBLWTL instructions offer a direct method to read or write the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only methods to read or write the upper 8 bits of a program space word as data. The PC is incremented by 2 for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D).
FIGURE 3-6:
TBLPAG
ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS
Program Space
23 15 0
02
0x000000
00000000 00000000 00000000 00000000
23
16
8
0
0x020000 0x030000
‘Phantom’ Byte
TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area.
0x800000
DS70289A-page 38
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
3.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY
24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes.
The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to the stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 8000h and higher maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the
For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data to execute in a single cycle.
FIGURE 3-7:
PROGRAM SPACE VISIBILITY OPERATION
When CORCON = 1 and EA = 1:
Program Space
PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space...
Data Space
0x0000 Data EA
0x8000
PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address.
0x800000
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 39
PIC24HJ32GP202/204 and PIC24HJ16GP304
NOTES:
DS70289A-page 40
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
4.0
Note:
FLASH PROGRAM MEMORY
This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”.
RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in ‘blocks’ or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time.
4.1
The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices contain internal Flash program memory to store and execute application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ32GP202/204 and PIC24HJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGC1/ PGD1, PGC2/PGD2 or PGC3/PGD3), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed.
Table Instructions and Flash Programming
Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The TBLRDL and the TBLWTL instructions are used to read or write to the bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode.
FIGURE 4-1:
ADDRESSING FOR TABLE REGISTERS
24 bits Using Program Counter 0 Program Counter 0
Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits
User/Configuration Space Select
24-bit EA
Byte Select
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 41
PIC24HJ32GP202/204 and PIC24HJ16GP304
4.2 RTSP Operation 4.3 Control Registers
The PIC24HJ32GP202/204 and PIC24HJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. Two SFRs are used to read and write the program Flash memory: • NVMCON: Flash Memory Control Register • NVMKEY: Non-Volatile Memory Key Register The NVMCON register (Register 4-1) controls which blocks need to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 4-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.4 “Programming Operations” for further details.
4.4
Programming Operations
A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. A programming operation is nominally 4 ms in duration and the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished.
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Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 4-1:
R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Satiable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) R/W-0(1) R/W-0(1)
(2)
NVMCON: FLASH MEMORY CONTROL REGISTER
R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) bit 0 WREN
R/W-0(1)
NVMOP
WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command Unimplemented: Read as ‘0’ NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte
bit 14
bit 13
bit 12-7 bit 6
bit 5-4 bit 3-0
Note 1: 2:
These bits can only be reset on POR. All other combinations of NVMOP are unimplemented.
© 2007 Microchip Technology Inc.
Preliminary
DS70289A-page 43
PIC24HJ32GP202/204 and PIC24HJ16GP304
REGISTER 4-2:
U-0 — bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 SO = Satiable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0
NVMKEY: NON-VOLATILE MEMORY KEY REGISTER
U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8
NVMKEY
Unimplemented: Read as ‘0’ NVMKEY: Key Register (Write Only) bits
DS70289A-page 44
Preliminary
© 2007 Microchip Technology Inc.
PIC24HJ32GP202/204 and PIC24HJ16GP304
4.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY
4. 5. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory.
Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically.
6.
To protect against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3.
EXAMPLE 4-1:
ERASING A PROGRAM MEMORY PAGE
; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ;
; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR
Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority -1 2 2 — -77 59 63 — 10.95 -2 >-1 1.25 1.25 — 12 data bits — — 1.5 1.52 — 12 data bits — — 3 3 — -69 63 72 — 11.1 +2 -1 1 1 — 10 data bits — — 3 2 — 10 data bits — — 5 2 — -64 57 60 — 9.7 +1
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