PIC24HJ32GP204

PIC24HJ32GP202/204 and PIC24HJ16GP304 Data Sheet High-Performance, 16-bit Microcontrollers © 2011 Microchip Technology Inc. DS70289G Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-825-2 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70289G-page 2 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 and PIC24HJ16GP304 High-Performance, 16-bit Microcontrollers Operating Range: • Up to 40 MIPS operation (@ 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) • Up to 20 MIPS operation (@ 3.0-3.6V): - High temperature range (-40°C to +150°C) Digital I/O: • • • • • Peripheral Pin Select Functionality Up to 35 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 31 pins Output pins can drive from 3.0V to 3.6V Up to 5.5V output with open drain configuration on 5V tolerant pins with external pull-up • 4 mA sink on all I/O pins High-Performance CPU: • • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions, mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Flexible and powerful addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit shifts for up to 40-bit data System Management: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Interrupt Controller: • • • • • 5-cycle latency Up to 21 available interrupt sources Up to three external interrupts Seven programmable priority levels Four processor exceptions Timers/Capture/Compare: • Timer/Counters, up to three 16-bit timers: - Can pair up to make one 32-bit timer - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to four channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to two channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM Mode On-Chip Flash and SRAM: • Flash program memory (up to 32 Kbytes) • Data SRAM (2 Kbytes) • Boot and General Security for Program Flash © 2011 Microchip Technology Inc. DS70289G-page 3 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Communication Modules: • 4-wire SPI - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS Analog-to-Digital Converters (ADCs): • 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion: - Two and four simultaneous samples (10-bit ADC) - Up to 13 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and extended temperature Low-power consumption Packaging: • 28-pin SDIP/SOIC/SSOP/QFN-S • 44-pin QFN/TQFP Note: See Table 1 for the exact peripheral features per device. DS70289G-page 4 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 PIC24HJ32GP202/204 and PIC24HJ16GP304 Product Families The device names, pin counts, memory sizes and peripheral availability of each family are listed below, followed by their pinout diagrams. TABLE 1: PIC24HJ32GP202/204 AND PIC24HJ16GP304 CONTROLLER FAMILIES Program Flash Memory (Kbyte) Remappable Peripherals External Interrupts(2) 10-Bit/12-Bit ADC Remappable Pins Output Compare Std. PWM I/O Pins (Max) 21 35 35 Input Capture Packages SDIP SOIC SSOP QFN-S QFN TQFP QFN TQFP 16-bit Timer UART PIC24HJ32GP202 28 32 2 16 3(1) 4 2 1 3 1 SPI Device 1 ADC, 10 ch PIC24HJ32GP204 PIC24HJ16GP304 Note 1: 2: 44 44 32 16 2 2 26 26 3(1) 3(1) 4 4 2 2 1 1 3 3 1 1 1 ADC, 13 ch 1 ADC, 13 ch Only two out of three timers are remappable. Only two out of three interrupts are remappable. © 2011 Microchip Technology Inc. I2C™ 1 1 1 RAM Pins DS70289G-page 5 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams 28-Pin SDIP, SOIC, SSOP = Pins are up to 5V tolerant MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 SOSCI/RP4(1)/CN1/RB4 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/TMS/RP11(1)/CN15/RB11 PGED2/TDI/RP10(1)/CN16/RB10 VCAP(3) VSS TDO/SDA1/RP9(1)/CN21/RB9 TCK/SCL1/RP8(1)/CN22/RB8 INT0/RP7/CN23/RB7 PGEC3/ASCL1/RP6(1)/CN24/RB6 PIC24HJ32GP202 28-Pin QFN-S(2) = Pins are up to 5V tolerant 28 27 26 25 24 23 22 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 VSS 1 2 3 4 5 21 20 19 18 17 16 15 8 SOSCI/RP4/CN1/RB4 9 10 11 12 13 14 SOSCO/T1CK/CN0/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/RB5 PGEC3/ASCL1/RP6/CN24/RB6 INT0/RP7(1(1))/CN23/RB7 TCK/SCL1/RP8(1)/CN22/RB8 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/TMS/RP11(1)/CN15/RB11 PGED2/TDI/RP10/CN16/RB10 VCAP(3) Vss TDO/SDA1/RP9(1)/CN21/RB9 PIC24HJ32GP202 OSC1/CLKI/CN30/RA2 6 OSC2/CLKO/CN29/RA3 7 Note 1: 2: 3: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. AVSS AN9/RP15(1)/CN11/RB15 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AN10/RP14(1)/CN12/RB14 AVDD DS70289G-page 6 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin QFN(2) = Pins are up to 5V tolerant PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16 /CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4(1)/CN1/RB4 (1) 22 21 20 19 18 17 16 15 14 13 12 23 24 25 26 27 28 29 30 31 32 33 11 10 9 8 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/RP11(1)/CN15/RB11 PGED2/RP10(1)/CN16/RB10 VCAP(3) VSS RP25(1)/CN19/RC9 RP24(1)/CN20/RC8 RP23(1)/CN17/RC7 RP22(1)/CN18/RC6 SDA1/RP9(1)/CN21/RB9 PIC24HJ32GP204 PIC24HJ16GP304 7 6 5 4 3 2 34 35 36 37 38 39 40 41 42 43 44 SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19(1)/CN28/RC3 (1)/CN25/RC4 RP20 RP21(1)/CN26/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/RB5 PGEC3/ASCL1/RP6(1)/CN24/RB6 INT0/RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 1 Note 1: 2: 3: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. © 2011 Microchip Technology Inc. DS70289G-page 7 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Pin Diagrams (Continued) 44-Pin TQFP = Pins are up to 5V tolerant 22 21 20 19 18 17 16 15 14 13 12 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/RB15 AN10/RP14(1)/CN12/RB14 TCK/RA7 TMS/RA10 34 35 36 37 Note 1: 2: The RPn pins can be used by any remappable peripheral. See Table 1 for the list of available peripherals. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. SOSCO/T1CK/CN0/RA4 TDI/RA9 RP19(1)/CN28/RC3 RP20(1)/CN25/RC4 RP21(1)/CN26/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/RB5 PGEC3/ASCL1/RP6(1)/CN24/RB6 INT0/ RP7(1)/CN23/RB7 SCL1/RP8(1)/CN22/RB8 38 39 40 41 42 43 44 AN4/RP2(1)/CN6/RB2 AN5/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/RP18(1)/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/RA8 SOSCI/RP4(1)/CN1/RB4 23 24 25 26 27 28 29 30 31 32 33 PIC24HJ32GP204 PIC24HJ16GP304 11 10 9 8 7 6 5 4 3 2 1 AN11/RP13(1)/CN13/RB13 AN12/RP12(1)/CN14/RB12 PGEC2/RP11(1)/CN15/RB11 PGED2/RP10(1)/CN16/RB10 VCAP(2) VSS RP25(1)/CN19/RC9 RP24(1)/CN20/RC8 RP23(1)/CN17/RC7 RP22/CN18/RC6 SDA1(1)/RP9(1)/CN21/RB9 DS70289G-page 8 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 47 6.0 Resets ....................................................................................................................................................................................... 53 7.0 Interrupt Controller ..................................................................................................................................................................... 61 8.0 Oscillator Configuration .............................................................................................................................................................. 89 9.0 Power-Saving Features.............................................................................................................................................................. 99 10.0 I/O Ports ................................................................................................................................................................................... 103 11.0 Timer1 ...................................................................................................................................................................................... 123 12.0 Timer2/3 Feature...................................................................................................................................................................... 125 13.0 Input Capture............................................................................................................................................................................ 131 14.0 Output Compare....................................................................................................................................................................... 133 15.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 137 16.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 143 17.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 151 18.0 10-bit/12-bit Analog-to-Digital Converter (ADC) ....................................................................................................................... 157 19.0 Special Features ...................................................................................................................................................................... 171 20.0 Instruction Set Summary .......................................................................................................................................................... 179 21.0 Development Support............................................................................................................................................................... 187 22.0 Electrical Characteristics .......................................................................................................................................................... 191 23.0 High Temperature Electrical Characteristics ............................................................................................................................ 235 24.0 Packaging Information.............................................................................................................................................................. 245 Appendix A: Revision History............................................................................................................................................................. 257 Index ................................................................................................................................................................................................. 265 The Microchip Web Site ..................................................................................................................................................................... 269 Customer Change Notification Service .............................................................................................................................................. 269 Customer Support .............................................................................................................................................................................. 269 Reader Response .............................................................................................................................................................................. 270 Product Identification System ............................................................................................................................................................ 271 TO OUR VALUED CUSTOMERS It is our intention to provide our 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To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2011 Microchip Technology Inc. DS70289G-page 9 PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 10 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This document contains device-specific information for the following devices: • PIC24HJ32GP202 • PIC24HJ32GP204 • PIC24HJ16GP304 Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. DS70289G-page 11 PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 1-1: PSV and Table Data Access Control Block Interrupt Controller 8 16 Data Bus PORTA 16 PIC24HJ32GP202/204 AND PIC24HJ16GP304 BLOCK DIAGRAM 16 Data Latch 23 23 PCU PCH PCL Program Counter Stack Control Logic 23 Loop Control Logic X RAM Address Latch PORTB 16 PORTC 16 Address Generator Units Remappable Pins Address Latch Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode and Control Instruction Reg 16 Control Signals to Various Blocks Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 17 x 17 Multiplier 16 x 16 W Register Array 16 OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Divide Support 16-bit ALU 16 VCAP VDD, VSS MCLR Timers 1-3 ADC1 UART1 IC1,2,7,8 OC/ PWM1,2 CNx SPI1 I2C1 Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features present on each device. DS70289G-page 12 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 1-1: Pin Name AN0-AN12 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I I O Buffer Type Analog ST/CMOS — PPS No No No Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture inputs 1/2. Capture inputs 7/8. Compare Fault A input (for Compare Channels 1 and 2). Compare outputs 1 through 2. External interrupt 0. External interrupt 1. External interrupt 2. PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Analog = Analog input I = Input O = Output P = Power Description OSC1 OSC2 SOSCI SOSCO CN0-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC2 INT0 INT1 INT2 RA0-RA4 RA7-RA10 RB0-RB15 RC0-RC9 T1CK T2CK T3CK U1CTS U1RTS U1RX U1TX SCK1 SDI1 SDO1 SS1 SCL1 SDA1 ASCL1 ASDA1 TMS TCK TDI TDO PGED PGEC1 PGED2 PGEC2 PGED3 PGEC3 I I/O I O I I I O I I I I/O I/O I/O I I I I O I O I/O I O I/O I/O I/O I/O I/O I I I O I/O I I/O I I/O I ST/CMOS — ST/CMOS — ST ST ST — ST ST ST ST ST ST ST ST ST ST — ST — ST ST — ST ST ST ST ST ST ST ST — ST ST ST ST ST ST No No No No No Yes Yes Yes Yes No Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No No No No No No No Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. DS70289G-page 13 PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 1-1: Pin Name VCAP VSS VREF+ VREFAVDD MCLR AVSS VDD PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type P P I I P I/P P P Buffer Type — — Analog Analog P ST P — PPS No No No No No No No No Description CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Positive supply for analog modules. This pin must be connected at all times. Master Clear (Reset) input. This pin is an active-low Reset to the device. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Analog = Analog input I = Input O = Output P = Power Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select DS70289G-page 14 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have a resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the microcontroller. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the microcontroller pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of 16-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (even if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. DS70289G-page 15 PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. VDD R R1 10 µF Tantalum VCAP VDD VSS MCLR C PIC24H VSS VDD VDD VSS AVDD AVSS VDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 10 Ω 0.1 µF Ceramic 0.1 µF Ceramic For example, as shown in Figure 2-2, it is recommended that capacitor C is isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including microcontrollers to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the microcontroller, and the maximum current drawn by the microcontroller in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 MCLR JP C PIC24H 2.3 CPU Logic Filter Capacitor Connection (VCAP) Note 1: R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R1 ≤ 470W will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 22.0 “Electrical Characteristics” for additional information. The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 19.2 “On-Chip Voltage Regulator” for details. 2: DS70289G-page 16 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP)™ and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the microcontroller as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL ICE™ in-circuit emulator For more information on MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE in-circuit emulator connection requirements, refer to the following documents that are available on the Microchip website. • “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™ In-Circuit Emulator” (poster) DS51749 Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the microcontroller. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 © 2011 Microchip Technology Inc. DS70289G-page 17 PIC24HJ32GP202/204 AND PIC24HJ16GP304 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with PLL enabled. This means that if the external oscillator frequency is outside this range, the application must start-up in FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, MPLAB ICD 3, or MPLAB REAL ICE in-circuit emulator is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL registers. The bits in the registers that correspond to the A/D pins that are initialized by MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 2, MPLAB ICD 3 or MPLAB REAL ICE in-circuit emulator is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic low state. Alternatively, connect a 1k to 10k resistor between VSS and the unused pins. DS70289G-page 18 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 3.0 CPU 3.1 Data Addressing Overview Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 2. CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU modules have a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJ32GP202/204 and PIC24HJ16GP304 instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJ32GP202/204 and PIC24HJ16GP304 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1. The programmer’s model for the PIC24HJ32GP202/204 and PIC24HJ16GP304 is shown in Figure 3-2. The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page register (PSVPAG). The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but this may be used as general purpose RAM. 3.2 Special MCU Features The PIC24HJ32GP202/204 and PIC24HJ16GP304 feature a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. The PIC24HJ32GP202/204 and PIC24HJ16GP304 supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. © 2011 Microchip Technology Inc. DS70289G-page 19 PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 3-1: PSV and Table Data Access Control Block Interrupt Controller 8 16 X Data Bus PIC24HJ32GP202/204 AND PIC24HJ16GP304 CPU CORE BLOCK DIAGRAM 16 16 Data Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch 16 23 16 Address Latch Address Generator Units Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode and Control Instruction Reg 17 x 17 Multiplier 16 Control Signals to Various Blocks Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70289G-page 20 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 3-2: PIC24HJ32GP202/204 AND PIC24HJ16GP304 PROGRAMMER’S MODEL D15 W0/WREG W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer Working Registers DO Shadow D0 PUSH.S Shadow Legend SPLIM Stack Pointer Limit Register PC22 PC0 0 Program Counter 7 TBLPAG 7 PSVPAG 0 Data Table Page Address 0 Program Space Visibility Page Address 15 RCOUNT 0 REPEAT Loop Counter 15 CORCON 0 Core Configuration Register — — — — — — — DC IPL2 IPL1 IPL0 RA SRL N OV Z C STATUS Register SRH © 2011 Microchip Technology Inc. DS70289G-page 21 PIC24HJ32GP202/204 AND PIC24HJ16GP304 3.3 CPU Control Registers SR: CPU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(2) IPL(2) bit 7 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set bit 15-9 bit 8 R = Readable bit W = Writable bit ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read-only when the NSTDIS bit (INTCON1) = 1. U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown R/W-0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 U-0 — bit 15 R/W-0(1) REGISTER 3-1: bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS70289G-page 22 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 3-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 C = Clear only bit W = Writable bit ‘x = Bit is unknown CORCON: CORE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ bit 2 bit 1-0 Note 1: Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. DS70289G-page 23 PIC24HJ32GP202/204 AND PIC24HJ16GP304 3.4 Arithmetic Logic Unit (ALU) 3.4.2 DIVIDER The PIC24HJ32GP202/204 and PIC24HJ16GP304 Arithmetic Logic Unit (ALU) is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. The ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register depending on the operation. The C and DC Status bits operate as Borrow and Digit Borrow bits respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157) for more information on the SR bits affected by each instruction. The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and a support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes. • • • • 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. A 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. and a negative value shifts the operand left. A value of ‘0’ does not modify the operand. 3.4.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS70289G-page 24 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”, “Section 4. Program Memory” (DS70202), which is available from the Microchip website (www.microchip.com). 4.1 Program Address Space The program address memory space of the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory maps for the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices are shown in Figure 4-1. The PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES PIC24HJ32GP202/204 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 PIC24HJ16GP304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Memory Space 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 User Memory Space User Program Flash Memory (11264 instructions) 0x0057FE 0x005800 User Program Flash Memory (5632 instructions) 0x002BFE 0x002C00 Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 0x7FFFFE 0x800000 Reserved Configuration Memory Space Configuration Memory Space Reserved Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved Reserved DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE © 2011 Microchip Technology Inc. DS70289G-page 25 PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (See Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. All PIC24HJ32GP202/204 and PIC24HJ16GP304 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ32GP202/204 and PIC24HJ16GP304 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). Section 7.1 “Interrupt Vector Table” provides a more detailed discussion of the interrupt vector tables. FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70289G-page 26 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.2 Data Address Space The PIC24HJ32GP202/204 and PIC24HJ16GP304 CPU has a separate 16 bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps is shown in Figure 4-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to the bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.4.3 “Reading Data from Program Memory Using Program Space Visibility”). PIC24HJ32GP202/204 and PIC24HJ16GP304 devices implement up to 2 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or when translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the instruction occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.1 DATA SPACE WIDTH The data memory space is organized in byte addressable, 16 bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. 4.2.3 SFR SPACE The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJ32GP202/204 and PIC24HJ16GP304 core and peripheral modules to control the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 4-1 through Table 4-22. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® devices and improve data space memory usage efficiency, the PIC24HJ32GP202/204 and PIC24HJ16GP304 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [WS++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode, but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 4.2.4 NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. © 2011 Microchip Technology Inc. DS70289G-page 27 PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ32GP202/204 AND PIC24HJ16GP304 DEVICES WITH 2 KB RAM MSB Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 X Data RAM (X) 0x0FFF 0x1001 0x1FFF 0x2001 0x0FFE 0x1000 0x1FFE 0x2000 0x07FE 0x0800 LSB Address LSb 0x0000 16 bits 2 Kbyte SRAM Space 8 Kbyte Near data space 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70289G-page 28 © 2011 Microchip Technology Inc. © 2011 Microchip Technology Inc. DS70289G-page 29 TABLE 4-1: SFR Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: CPU CORE REGISTERS MAP SFR Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL2 — IPL1 — IPL0 — RA — N IPL3 OV PSV Z — C — 0000 0000 0000 xxxx 0000 0000 xxxx Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register — — — DC — PIC24HJ32GP202/204 AND PIC24HJ16GP304 Repeat Loop Counter Register Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70289G-page 30 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-2: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ32GP202 Bit 15 CN15IE — Bit 14 CN14IE CN30IE Bit 13 CN13IE CN29IE Bit 12 CN12IE — Bit 11 CN11IE CN27IE Bit 10 —— — — Bit 9 — — — — Bit 8 — CN24IE — Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE — CN4PUE — Bit 3 CN3IE — CN3PUE — Bit 2 CN2IE — CN2PUE — Bit 1 CN1IE — CN1PUE — Bit 0 CN0IE CN16IE CN0PUE CN16PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — CN30PUE CN29PUE — CN27PUE CN24PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 Bit 15 CN15IE — Bit 14 CN14IE CN30IE Bit 13 CN13IE CN29IE Bit 12 CN12IE CN28IE Bit 11 CN11IE CN27IE Bit 10 CN10IE CN26IE Bit 9 CN9IE CN25IE Bit 8 CN8IE CN24IE Bit 7 CN7IE CN23IE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE — CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70289G-page 31 TABLE 4-4: SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS4 IEC0 IEC1 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC7 IPC16 INTTREG Legend: SFR Addr 0080 0082 0084 0086 008C 0094 0096 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B2 00C4 00E0 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT — — — — — — — — — — — — — — — — — — — Bit 14 — DISI — — — — — — Bit 13 — — AD1IF INT2IF — AD1IE INT2IE — T1IP T2IP U1RXIP — CNIP IC8IP — — — — — — — Bit 12 — — U1TXIF — — U1TXIE — — Bit 11 — — U1RXIF — — U1RXIE — — — — — — — — — — — — ILR — — Bit 10 — — Bit 9 — — Bit 8 — — T3IF — — T3IE — — Bit 7 — — T2IF IC8IF — T2IE IC8IE — — — — — — — — — — — — — — — Bit 6 DIV0ERR — OC2IF IC7IF — OC2IE IC7IE — Bit 5 — — IC2IF — — IC2IE — — IC1IP IC2IP SPI1EIP AD1IP MI2C1IP — INT2IP U1EIP — Bit 4 Bit 3 Bit 2 Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF U1EIF IC1IE Bit 0 — INT0EP INT0IF SI2C1IF — INT0IE All Resets 0000 0000 0000 0000 0000 0000 0000 0000 4444 — 4440 4444 0044 4044 4404 — — 0040 0040 0000 MATHERR ADDRERR STKERR — — INT1IF — — INT1IE — — T1IF CNIF — T1IE CNIE — — — — — — — — — VECNUM — — — INT2EP OC1IF — — OC1IE — — PIC24HJ32GP202/204 AND PIC24HJ16GP304 SPI1IF SPI1EIF — — — — SPI1IE SPI1EIE — — — — OC1IP OC2IP SPI1IP — — IC7IP — — MI2C1IE SI2C1IE U1EIE INT0IP — T3IP U1TXIP SI2C1IP INT1IP — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70289G-page 32 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-5: SFR Name SFR Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 FFFF TGATE TCKPS — TSYNC TCS — 0000 0000 xxxx 0000 FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON Legend: Timer1 Register Period Register 1 TON — TSIDL — — — — — — Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON — — TSIDL TSIDL — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-6: SFR Name IC1BUF IC1CON IC2BUF IC2CON IC7BUF IC7CON IC8BUF IC8CON Legend: SFR Addr 0140 0142 0144 0146 0158 015A 015C 015E INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 Input 1 Capture Register — — ICSIDL — — — — — ICTMR Input 2 Capture Register — — ICSIDL — — — — — ICTMR Input 7 Capture Register — — ICSIDL — — — — — ICTMR Input 8Capture Register — — ICSIDL — — — — — ICTMR x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-7: SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON Legend: SFR Addr 0180 0182 0184 0186 0188 018A OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — — OCFLT OCTSEL OCM 0000 xxxx xxxx — — OCFLT OCTSEL OCM 0000 Output Compare 1 Secondary Register Output Compare 1 Register — — OCSIDL — — — — — — Output Compare 2 Secondary Register Output Compare 2 Register — — OCSIDL — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70289G-page 33 TABLE 4-8: SFR Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: SFR Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKDT D_A ACKEN P RCEN S PIC24HJ32GP202/204 AND PIC24HJ16GP304 Address Register Address Mask Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-9: SFR Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: SFR Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — UTXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR URXISEL UART Transmit Register UART Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-10: SFR Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: SFR Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF Bit 0 SPIRBF All Resets 0000 0000 0000 0000 PPRE FRMDLY — SPI1 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70289G-page 34 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-11: File Name RPINR0 RPINR1 RPINR3 RPINR7 RPINR10 RPINR11 RPINR18 RPINR20 RPINR21 Legend: Addr 0680 0682 0686 068E 0694 0696 06A4 06A8 06AA PERIPHERAL PIN SELECT INPUT REGISTER MAP Bit 15 — — — — — — — — — Bit 14 — — — — — — — — — Bit 13 — — — — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 INT1R — T3CKR IC2R IC8R — U1CTSR SCK1R — — — — — — — Bit 9 Bit 8 Bit 7 — — — — — — — — — Bit 6 — — — — — — — — — Bit 5 — — — — — — — — — Bit 4 — Bit 3 — Bit 2 — INT2R T2CKR IC1R IC7R OCFAR U1RXR SDI1R SS1R Bit 1 — Bit 0 — All Resets 1F00 001F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 001F x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 Legend: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ32GP202 Bit 15 — — — — — — — — Bit 14 — — — — — — — — Bit 13 — — — — — — — — Bit 12 Bit 11 Bit 10 RP1R RP3R RP5R RP7R RP9R RP11R RP13R RP15R Bit 9 Bit 8 Bit 7 — — — — — — — — Bit 6 — — — — — — — — Bit 5 — — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70289G-page 35 TABLE 4-13: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 Legend: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 Bit 15 — — — — — — — — — — — — Bit 14 — — — — — — — — — — — — Bit 13 — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 RP1R RP3R RP5R RP7R RP9R RP11R RP13R RP15R RP17R RP19R RP21R RP23R Bit 9 Bit 8 Bit 7 — — — — — — — — — — — — Bit 6 — — — — — — — — — — — — — Bit 5 — — — — — — — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R RP16R RP18R RP20R RP22R RP24R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PIC24HJ32GP202/204 AND PIC24HJ16GP304 06D8 — — — RP25R — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70289G-page 36 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-14: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFE AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330 ADC1 REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC BUFS — — SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123NA CH0SA PCFG4 CSS4 PCFG3 CSS3 PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA 0000 0000 0000 0000 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON — VCFG ADRC — CH0NB — — — — — — — — — — — — PCFG12 CSS12 — — ADSIDL — — — — AD12B CSCNA SAMC CH123NB CH0SB PCFG11 PCFG10 CSS11 CSS10 PCFG9 CSS9 PCFG8 CSS8 CH123SB — CH0NA PCFG7 CSS7 — — PCFG6 CSS6 — — PCFG5 CSS5 FORM CHPS SMPI ADCS — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70289G-page 37 TABLE 4-15: File Name ADC1BUF0 ADC1BUF1 ADC1BUF2 ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE ADC1BUFF AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL Legend: Addr 0300 0302 0304 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C 031E 0320 0322 0324 0326 0328 032C 0330 ADC1 REGISTER MAP FOR PIC24HJ32GP202 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx SSRC BUFS — — SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123NA CH0SA PCFG4 CSS4 PCFG3 CSS3 PCFG2 CSS2 PCFG1 CSS1 PCFG0 CSS0 CH123SA 0000 0000 0000 0000 ADC Data Buffer 0 ADC Data Buffer 1 ADC Data Buffer 2 ADC Data Buffer 3 ADC Data Buffer 4 ADC Data Buffer 5 ADC Data Buffer 6 ADC Data Buffer 7 ADC Data Buffer 8 ADC Data Buffer 9 ADC Data Buffer 10 ADC Data Buffer 11 ADC Data Buffer 12 ADC Data Buffer 13 ADC Data Buffer 14 ADC Data Buffer 15 ADON — VCFG ADRC — CH0NB — — — — — — — — — — — — — — ADSIDL — — — — AD12B CSCNA SAMC CH123NB CH0SB PCFG12 PCFG11 PCFG10 CSS12 CSS11 CSS10 PCFG9 CSS9 — — CH123SB — CH0NA — — — — — — — — PCFG5 CSS5 FORM CHPS PIC24HJ32GP202/204 AND PIC24HJ16GP304 SMPI ADCS — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70289G-page 38 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-16: File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP FOR PIC24HJ32GP202 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 — — — — Bit 7 — — — — Bit 6 — — — — Bit 5 — — — — Bit 4 TRISA4 RA4 LATA4 ODCA4 Bit 3 TRISA3 RA3 LATA3 ODCA3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets 001F xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 TRISA10 RA10 LATA10 ODCA10 Bit 9 TRISA9 RA9 LATA9 ODCA9 Bit 8 TRISA8 RA8 LATA8 ODCA8 Bit 7 TRISA7 RA7 LATA7 ODCA7 Bit 6 — — — — Bit 5 — — — — Bit 4 TRISA4 RA4 LATA4 ODCA4 Bit 3 TRISA3 RA3 LATA3 ODCA3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets 001F xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE PORTB REGISTER MAP Bit 15 TRISB15 RB15 LATB15 ODCB15 Bit 14 TRISB14 RB14 LATB14 ODCB14 Bit 13 TRISB13 RB13 LATB13 ODCB13 Bit 12 TRISB12 RB12 LATB12 ODCB12 Bit 11 TRISB11 RB11 LATB11 ODCB11 Bit 10 TRISB10 RB10 LATB10 ODCB10 Bit 9 TRISB9 RB9 LATB9 ODCB9 Bit 8 TRISB8 RB8 LATB8 ODCB8 Bit 7 TRISB7 RB7 LATB7 ODCB7 Bit 6 TRISB6 RB6 LATB6 ODCB6 Bit 5 TRISB5 RB5 LATB5 ODCB5 Bit 4 TRISB4 RB4 LATB4 ODCB4 Bit 3 TRISB3 RB3 LATB3 ODCB3 Bit 2 TRISB2 RB2 LATB2 ODCB2 Bit 1 TRISB1 RB1 LATB1 ODCB1 Bit 0 TRISB0 RB0 LATB0 ODCB0 All Resets FFFF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-19: File Name TRISC PORTC LATC ODCC Legend: Addr 02D0 02D2 02D4 02D6 PORTC REGISTER MAP FOR PIC24HJ32GP204 AND PIC24HJ16GP304 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 TRISC9 RC9 LATC9 ODCC9 Bit 8 TRISC8 RC8 LATC8 ODCC8 Bit 7 TRISC7 RC7 LATC7 ODCC7 Bit 6 TRISC6 RC6 LATC6 ODCC6 Bit 5 TRISC5 RC5 LATC5 ODCC5 Bit 4 TRISC4 RC4 LATC4 ODCC4 Bit 3 TRISC3 RC4 LATC4 ODCC4 Bit 2 TRISC2 RC2 LATC2 ODCC2 Bit 1 TRISC1 RC1 LATC1 ODCC1 Bit 0 TRISC0 RC0 LATC0 ODCC0 All Resets 03FF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70289G-page 39 TABLE 4-20: File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0746 0748 SYSTEM CONTROL REGISTER MAP Bit 15 TRAPR — ROI — — — — Bit 14 IOPUWR Bit 13 — COSC DOZE — — — — Bit 12 — Bit 11 — — DOZEN — — — — Bit 10 — Bit 9 CM NOSC FRCDIV — — — — — Bit 8 VREGS Bit 7 EXTR Bit 6 SWR Bit 5 SWDTEN LOCK — PLLDIV TUN Bit 4 WDTO — Bit 3 SLEEP CF Bit 2 IDLE — Bit 1 BOR LPOSCEN Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 3040 0030 0000 PIC24HJ32GP202/204 AND PIC24HJ16GP304 CLKLOCK IOLOCK PLLPOST PLLPRE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-21: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR — Bit 14 WREN — Bit 13 WRERR — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — Bit 6 ERASE Bit 5 — Bit 4 — NVMKEY Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000 NVMOP x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 4-22: File Name PMD1 PMD2 Legend: Addr 0770 0772 PMD REGISTER MAP Bit 15 — IC8MD Bit 14 — IC7MD Bit 13 T3MD — Bit 12 T2MD — Bit 11 T1MD — Bit 10 — — Bit 9 — IC2MD Bit 8 — IC1MD Bit 7 I2C1MD — Bit 6 — — Bit 5 U1MD — Bit 4 — — Bit 3 SPI1MD — Bit 2 — — Bit 1 — OC2MD Bit 0 AD1MD OC1MD All Resets 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.2.5 SOFTWARE STACK 4.2.6 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 register in the PIC24HJ32GP202/204 and PIC24HJ16GP304 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-4. For a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.3 Instruction Addressing Modes The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. Similarly, the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word aligned. When an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x1000 in RAM, initialize the SPLIM with the value 0x0FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be lesser than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. The addressing modes shown in Table 4-23 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where: Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. FIGURE 4-4: 0x0000 15 CALL STACK FRAME 0 Stack Grows Toward Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] DS70289G-page 40 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 4-23: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA.) The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE (MOV) INSTRUCTION Move instructions provide a greater degree of addressing flexibility than the other instructions. In addition to the Addressing modes supported by most MCU instructions, MOV instructions also support Register Indirect with Register Offset Addressing mode. This is also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and the destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). In summary, move instructions support the following addressing modes: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. 4.3.4 OTHER INSTRUCTIONS Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. © 2011 Microchip Technology Inc. DS70289G-page 41 PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4 Interfacing Program and Data Memory Spaces 4.4.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-24 and Figure 4-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. The PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture uses a 24-bit-wide program space and a 16 bit wide data space. The architecture is also a modified Harvard scheme, which means that the data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24HJ32GP202/204 and PIC24HJ16GP304 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. The application can only access the least significant word of the program word. TABLE 4-24: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address 0 0xx xxxx TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx 0 0 PSVPAG xxxx xxxx PC xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. DS70289G-page 42 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 FIGURE 4-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits 0 EA Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits 1/0 Select Program Space (Remapping) Visibility(1) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. © 2011 Microchip Technology Inc. DS70289G-page 43 PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom byte’, will always be ‘0’. In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, as in the TBLRDL instruction. Note that the data will always be ‘0’ when the upper ‘Phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method to read or write the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only methods to read or write the upper 8 bits of a program space word as data. The PC is incremented by 2 for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16 bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). FIGURE 4-6: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 02 23 15 0 0x000000 00000000 00000000 23 16 8 0 0x020000 0x030000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 DS70289G-page 44 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to the stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 0x8000 and higher maps directly into a corresponding program memory address (see Figure 4-7), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction using PSV to access data to execute in a single cycle. FIGURE 4-7: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 © 2011 Microchip Technology Inc. DS70289G-page 45 PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 46 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC24HJ32GP202/204 and PIC24HJ16GP304 family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 4. Program Memory” (DS70202) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC24HJ32GP202/204 and PIC24HJ16GP304 devices contain internal Flash program memory to store and execute application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows a PIC24HJ32GP202/204 and PIC24HJ16GP304 device to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in ‘blocks’ or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 5.1 Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to the bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select © 2011 Microchip Technology Inc. DS70289G-page 47 PIC24HJ32GP202/204 AND PIC24HJ16GP304 5.2 RTSP Operation The PIC24HJ32GP202/204 and PIC24HJ16GP304 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN bits (see Register 8-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. EQUATION 5-2: MINIMUM ROW WRITE TIME 11064 Cycles T RW = ---------------------------------------------------------------------------------------------- = 1.435 ms 7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 ) The maximum row write time is equal to Equation 5-3. EQUATION 5-3: MAXIMUM ROW WRITE TIME 11064 Cycles T RW = --------------------------------------------------------------------------------------------- = 1.586 ms 7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 ) Setting the WR bit (NVMCON) starts the operaion, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers The two SFRs that are used to read and write the program Flash memory are: • NVMCON: Flash Memory Control Register • NVMKEY: Nonvolatile Memory Key Register The NVMCON register (Register 5-1) controls which blocks need to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. 5.3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 22-18) and the value of the FRC Oscillator Tuning register (see Register 8-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 22-12). EQUATION 5-1: PROGRAMMING TIME T ------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy ) % × ( FRC Tuning ) % DS70289G-page 48 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 5-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable Only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) R/W-0(1) R/W-0(1) (2) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) bit 0 WREN R/W-0(1) NVMOP WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command Unimplemented: Read as ‘0’ NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1101 = Erase General Segment 1100 = Erase Secure Segment 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1101 = No operation 1100 = No operation 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: These bits can only be reset on a Power-on Reset (POR). All other combinations of NVMOP are unimplemented. © 2011 Microchip Technology Inc. DS70289G-page 49 PIC24HJ32GP202/204 AND PIC24HJ16GP304 REGISTER 5-2: U-0 — bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 SO = Settable Only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0 NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 NVMKEY Unimplemented: Read as ‘0’ NVMKEY: Key Register (write-only) bits DS70289G-page 50 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. To protect against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority 4)16@ ZLWK  PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2011 Microchip Technology Inc. DS70289G-page 251 PIC24HJ32GP202/204 AND PIC24HJ16GP304 44-Lead Plastic Quad Flat, No Lead Package (ML) – 8x8 mm Body [QFN] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D EXPOSED PAD D2 e E E2 b 2 1 N TOP VIEW NOTE 1 2 1 N L BOTTOM VIEW K A A3 A1 Units Dimension Limits Number of Pins Pitch Overall Height Standoff Contact Thickness Overall Width Exposed Pad Width Overall Length Exposed Pad Length Contact Width Contact Length Contact-to-Exposed Pad N e A A1 A3 E E2 D D2 b L K 6.30 0.25 0.30 0.20 6.30 0.80 0.00 MIN MILLIMETERS NOM 44 0.65 BSC 0.90 0.02 0.20 REF 8.00 BSC 6.45 8.00 BSC 6.45 0.30 0.40 – 6.80 0.38 0.50 – 6.80 1.00 0.05 MAX Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Package is saw singulated. 3. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-103B DS70289G-page 252 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 /HDG 3ODVWLF 4XDG )ODW 1R /HDG 3DFNDJH 0/ ± [ PP %RG\ >4)1@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2011 Microchip Technology Inc. DS70289G-page 253 PIC24HJ32GP202/204 AND PIC24HJ16GP304 44-Lead Plastic Thin Quad Flatpack (PT) – 10x10x1 mm Body, 2.00 mm Footprint [TQFP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D D1 E e E1 N b NOTE 1 123 φ NOTE 2 A c α β A1 L L1 A2 Units Dimension Limits Number of Leads Lead Pitch Overall Height Molded Package Thickness Standoff Foot Length Footprint Foot Angle Overall Width Overall Length Molded Package Width Molded Package Length Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom N e A A2 A1 L L1 φ E D E1 D1 c b α β 0.09 0.30 11° 11° 0° – 0.95 0.05 0.45 MIN MILLIMETERS NOM 44 0.80 BSC – 1.00 – 0.60 1.00 REF 3.5° 12.00 BSC 12.00 BSC 10.00 BSC 10.00 BSC – 0.37 12° 12° 0.20 0.45 13° 13° 7° 1.20 1.05 0.15 0.75 MAX Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. Chamfers at corners are optional; size may vary. 3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.25 mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M. BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. Microchip Technology Drawing C04-076B DS70289G-page 254 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± [[ PP %RG\  PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ © 2011 Microchip Technology Inc. DS70289G-page 255 PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 256 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 APPENDIX A: REVISION HISTORY Revision A (July 2007) Initial release of this document. Revision B (June 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE 24-1: MAJOR SECTION UPDATES Update Description Added Extended Interrupts column to Remappable Peripherals in the Controller Families table and Note 2 (see Table 1). Added Note 1 to all pin diagrams, which references RPn pin usage by remappable peripherals (see “Pin Diagrams”). Section Name “High-Performance, 16-bit Microcontrollers” Section 1.0 “Device Overview” Section 3.0 “Memory Organization” Changed PORTA pin name from RA15 to RA10 (see Table 1-1). Updated Reset values for the following SFRs: IPC1, IPC3-IPC5, IPC7, IPC16, and INTTREG (see Table 3-4). Added the System Control Register Map (see Table 3-20). Section 5.0 “Resets” Section 7.0 “Oscillator Configuration” Entire section was replaced to maintain consistency with other PIC24H data sheets. Removed the first sentence of the third clock source item (External Clock) in Section 7.1.1.2 “Primary”. Updated the default bit values for DOZE and FRCDIV in the Clock Divisor Register (see Register 7-2). Added the center frequency in the OSCTUN register for the FRC Tuning bits (TUN) value 011111 and updated the center frequency for bits value 011110 (see Register 7-4). Section 8.0 “Power-Saving Features” Section 9.0 “I/O Ports” Added the following two registers: • PMD1: Peripheral Module Disable Control Register 1 • PMD2: Peripheral Module Disable Control Register 2 Added paragraph and Table 9-1 to Section 9.1.1 “Open-Drain Configuration”, which provides details on I/O pins and their functionality. Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 9.4.2 “Available Peripherals” • 9.4.3.3 “Mapping” • 9.4.5 “Considerations for Peripheral Pin Selection” Section 13.0 “Output Compare” Section 14.0 “Serial Peripheral Interface (SPI)” Replaced sections 13.1, 13.2 and 13.3 and related figures and tables with entirely new content. Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 14.1 “Interrupts” • 14.2 “Receive Operations” • 14.3 “Transmit Operations” • 14.4 “SPI Setup” (retained Figure 14-1: SPI Module Block Diagram) © 2011 Microchip Technology Inc. DS70289G-page 257 PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 24-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Removed the following sections, which are now available in the related section of the dsPIC33F/PIC24H Family Reference Manual: • 15.3 “I2C Interrupts” • 15.4 “Baud Rate Generator” (retained Figure 15-1: I2C Block Diagram) • 15.5 “I2C Module Addresses” • 15.6 “Slave Address Masking” • 15.7 “IPMI Support” • 15.8 “General Call Address Support” • 15.9 “Automatic Clock Stretch” • 15.10 “Software Controlled Clock Stretching (STREN = 1)” • 15.11 “Slope Control” • 15.12 “Clock Arbitration” • 15.13 “Multi-Master Communication, Bus Collision, and Bus Arbitration” • 15.14 “Peripheral Pin Select Limitations” Section Name Section 15.0 “Inter-Integrated Circuit (I2C™)” Section 16.0 “Universal Removed the following sections, which are now available in the related Asynchronous Receiver Transmitter section of the dsPIC33F/PIC24H Family Reference Manual: (UART)” • 16.1 “UART Baud Rate Generator” • 16.2 “Transmitting in 8-bit Data Mode” • 16.3 “Transmitting in 9-bit Data Mode” • 16.4 “Break and Sync Transmit Sequence” • 16.5 “Receiving in 8-bit or 9-bit Data Mode” • 16.6 “Flow Control Using UxCTS and UxRTS Pins” • 16.7 “Infrared Support” Removed IrDA references and Note 1, and updated the bit and bit value descriptions for UTXINV (UxSTA) in the UARTx Status and Control Register (see Register 16-2). Section 17.0 “10-bit/12-bit Analogto-Digital Converter (ADC)” Removed Equation 17-1: ADC Conversion Clock Period and Figure 17-2: ADC Transfer Function (10-Bit Example). Added ADC1 Module Block Diagram for PIC24HFJ16GP304 and PIC24HJ32GP204 Devices (Figure 17-1) and ADC1 Module Block Diagram FOR PIC24HJ32GP202 Devices (Figure 17-2). Added Note 2 to Figure 17-3: ADC Conversion Clock Period Block Diagram. Added device-specific information to Note 1 in the ADC1 Input Scan Select Register Low (see Register 17-6), and updated the default bit value for bits 12-10 (CSS12-CSS10) from U-0 to R/W-0. Added device-specific information to Note 1 in the ADC1 Port Configuration Register Low (see Register 17-7), and updated the default bit value for bits 12-10 (PCFG12-PCFG10) from U-0 to R/W-0. DS70289G-page 258 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE 24-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Added FICD register information for address 0xF8000E in the Device Configuration Register Map (see Table 18-1). Added FICD register content (BKBUG, COE, JTAGEN, and ICS to the PIC24HJ32GP202/204 and PIC24HJ16GP304 Configuration Bits Description (see Table 18-2). Added a note regarding the placement of low-ESR capacitors, after the second paragraph of Section 18.2 “On-Chip Voltage Regulator” and to Figure 18-1. Removed the words “if enabled” from the second sentence in the fifth paragraph of Section 18.3 “BOR: Brown-Out Reset”. Section 21.0 “Electrical Characteristics” Removed Typ value for parameter DC12 (see Table 21-4). Updated MIPS conditions for parameters DC24c, DC44c, DC72a, DC72f and DC72g (see Table 21-5, Table 21-6 and Table 21-8). Added Note 4 (reference to new table containing digital-only and analog pin information to I/O Pin Input Specifications (see Table 21-9). Updated Min, Typ, and Max values and updated Min values for Program Memory parameters D136, D137 and D138 (see Table 21-12). Updated Max value for Internal RC Accuracy parameter F21 for -40°C ≤ TA ≤ +125°C condition and added Note 2 (see Table 21-19). Removed all values for Reset, Watchdog Timer, Oscillator Start-up Timer, and Power-up Timer parameter SY20 and updated conditions, which now refers to Section 18.4 “Watchdog Timer (WDT)” and LPRC parameter F21 (see Table 21-21). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 21-37). Updated Min and Typ values for parameters AD60, AD61, AD62 and AD63 and removed Note 3 (see Table 21-38). Section Name Section 18.0 “Special Features” © 2011 Microchip Technology Inc. DS70289G-page 259 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Revision C (December 2008) This revision includes minor typographical and formatting changes throughout the data sheet text. The major changes are referenced by their respective section in the following table. TABLE 24-2: MAJOR SECTION UPDATES Update Description Updated all pin diagrams to denote the pin voltage tolerance (see “Pin Diagrams”). Section Name “High-Performance, 16-bit Microcontrollers” Section 2.0 “Guidelines for Getting Added new section to the data sheet that provides guidelines on getting Started with 16-bit Microcontrollers” started with 16-bit microcontrollers. Section 10.0 “I/O Ports” Section 22.0 “Electrical Characteristics” Updated 5V tolerant status for I/O pin RB4 from Yes to No (see Table 10-1). Removed the maximum value for parameter DC12 (RAM Data Retention Voltage) in Table 22-4. Updated typical values for Operating Current (IDD) and added Note 3 in Table 22-5. Updated typical and maximum values for Idle Current (IIDLE): Core OFF Clock ON Base Current and added Note 3 in Table 22-6. Updated typical and maximum values for Power Down Current (IPD) and added Note 5 in Table 22-7. Updated typical and maximum values for Doze Current (IDOZE) and added Note 2 in Table 22-8. Added Note 3 to Table 22-12. Updated minimum value for Internal Voltage Regulator Specifications in Table 22-13. Added parameter OS42 (GM) and Notes 4, 5, and 6 to Table 22-16. Added Notes 2 and 3 to Table 22-17. Added Note 2 to Table 22-20. Added Note 2 to Table 22-21. Added Note 2 to Table 22-22. Added Note 1 to Table 22-23. Added Note 1 to Table 22-24. Added Note 3 to Table 22-32. Added Note 2 to Table 22-33. Updated typical value for parameter AD08 (ADC in operation) and added Notes 2 and 3 in Table 22-34. Updated minimum, typical, and maximum values for parameters AD23a, AD24a, AD30a, AD32a, AD32a, and AD34a, and added Notes 2 and 3 in Table 22-35. Updated minimum, typical, and maximum values for parameters AD23b, AD24b, AD30b, AD32b, AD32b, and AD34b, and added Notes 2 and 3 in Table 22-36. DS70289G-page 260 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Revision D (June 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. Global changes include: • Changed all instances of OSCI to OSC1 and OSCO to OSC2 • Changed all instances of PGCx/EMUCx and PGDx/EMUDx (where x = 1, 2, or 3) to PGECx and PGEDx Changed all instances of VDDCORE and VDDCORE/VCAP to VCAP/VDDCORE All other major changes are referenced by their respective section in the following table. TABLE 24-3: MAJOR SECTION UPDATES Section Name Update Description Added Note 2 to the 28-Pin QFN-S and 44-Pin QFN pin diagrams, which references pin connections to VSS. Updated the Oscillator System Diagram (see Figure 8-1). Added Note 1 to the Oscillator Tuning (OSCTUN) register (see Register 8-4). “High-Performance, 16-bit Microcontrollers” Section 8.0 “Oscillator Configuration” Section 10.0 “I/O Ports” Section 15.0 “Serial Peripheral Interface (SPI)” Section 17.0 “Universal Asynchronous Receiver Transmitter (UART)” Removed Table 10-1 and added reference to pin diagrams for I/O pin availability and functionality. Added Note 2 to the SPIx Control Register 1 (see Register 15-2). Updated the UTXINV bit settings in the UxSTA register and added Note 1 (see Register 17-2). Section 22.0 “Electrical Characteristics” Updated the Min value for parameter DC12 (RAM Retention Voltage) and added Note 4 to the DC Temperature and Voltage Specifications (see Table 22-4). Updated the Min value for parameter DI35 (see Table 22-20). Updated AD08 and added reference to Note 2 for parameters AD05a, AD06a, and AD08a (see Table 22-34). © 2011 Microchip Technology Inc. DS70289G-page 261 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Revision E (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits This revision also includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE 24-4: MAJOR SECTION UPDATES Section Name Update Description Added information on high temperature operation (see “Operating Range:”). Changed the reference to digital-only pins to 5V tolerant pins in the second paragraph of Section 10.2 “Open-Drain Configuration”. Updated the two baud rate range features to: 10 Mbps to 38 bps at 40 MIPS. Updated the ADC1 block diagrams (see Figure 18-1 and Figure 18-2). Updated the second paragraph and removed the fourth paragraph in Section 19.1 “Configuration Bits”. Updated the Device Configuration Register Map (see Table 19-1). “High-Performance, 16-bit Microcontrollers” Section 10.0 “I/O Ports” Section 17.0 “Universal Asynchronous Receiver Transmitter (UART)” Section 18.0 “10-bit/12-bit Analog-to-Digital Converter (ADC)” Section 19.0 “Special Features” Section 22.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings for high temperature and added Note 4. Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics (see Figure 22-12). Section 23.0 “High Temperature Electrical Characteristics” “Product Identification System” Added new chapter with high temperature specifications. Added the “H” definition for high temperature. Revision F (November 2009) This revision includes minor typographical and formatting changes throughout the data sheet text. All other major changes are referenced by their respective section in the following table. TABLE A-1: MAJOR SECTION UPDATES Section Name Update Description Updated MIPS rating from 16 to 20 for high temperature devices in “Operating Range:” and in TABLE 23-1: “Operating MIPS vs. Voltage”. “High-Performance, 16-bit Microcontrollers” DS70289G-page 262 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 Revision G (January 2011) This revision includes typographical and formatting changes throughout the data sheet text. In addition, all instances of VDDCORE have been removed. All other major changes are referenced by their respective section in the following table. TABLE A-2: MAJOR SECTION UPDATES Section Name Update Description Added the SSOP package information (see “Packaging:”, Table 1, and “Pin Diagrams”). The frequency limitation for device PLL start-up conditions was updated in Section 2.7 “Oscillator Value Conditions on Device Start-up”. The second paragraph in Section 2.9 “Unused I/Os” was updated. High-Performance, 16-bit Microcontrollers Section 2.0 “Guidelines for Getting Started with 16-bit Microcontrollers” Section 4.0 “Memory Organization” Updated the data memory reference in the third paragraph in Section 4.2 “Data Address Space”. The All Resets values for the following SFRs in the Timer Register Map were changed (see Table 4-5): • TMR1 • TMR2 • TMR3 Section 8.0 “Oscillator Configuration” Added Note 3 to the OSCCON: Oscillator Control Register (see Register 8-1). Added Note 2 to the CLKDIV: Clock Divisor Register (see Register 8-2). Added Note 1 to the PLLFBD: PLL Feedback Divisor Register (see Register 8-3). Added Note 2 to the OSCTUN: FRC Oscillator Tuning Register (see Register 8-4). Section 18.0 “10-bit/12-bit Analog-to-Digital Updated the VREFL references in the ADC1 module block diagrams Converter (ADC)” (see Figure 18-1 and Figure 18-2). Section 19.0 “Special Features” Added a new paragraph and removed the third paragraph in Section 19.1 “Configuration Bits”. Added the column “RTSP Effects” to the Configuration Bits Descriptions (see Table 19-2). © 2011 Microchip Technology Inc. DS70289G-page 263 PIC24HJ32GP202/204 AND PIC24HJ16GP304 TABLE A-2: MAJOR SECTION UPDATES (CONTINUED) Section Name Section 22.0 “Electrical Characteristics” Update Description Added 28-pin SSOP Thermal Packaging Characteristics (see Table 22-3). Removed Note 4 from the DC Temperature and Voltage Specifications (see Table 22-4). Updated the maximum value for parameter DI19 and added parameters DI28, DI29, DI60a, DI60b, and DI60c to the I/O Pin Input Specifications (see Table 22-9). Updated Note 3 in the PLL Clock Timing Specifications (see Table 22-17). Removed Note 2 from the AC Characteristics: Internal RC Accuracy (see Table 22-18). Updated the characteristic description for parameter DI35 in the I/O Timing Requirements (see Table 22-20). Updated all SPI specifications (see Table 22-28 through Table 22-35 and Figure 22-10 through Figure 22-16). Added Note 4 to the 12-bit ADC Module Specifications (see Table 22-39). Added Note 4 to the 10-bit ADC Module Specifications (see Table 22-40). Section 23.0 “High Temperature Electrical Characteristics” Updated all ambient temperature end range values to +150ºC throughout the chapter. Updated the storage temperature end range to +160ºC. Updated the maximum junction temperature from +145ºC to +155ºC. Updated Note 1 in the PLL Clock Timing Specifications (see Table 23-10). Added Note 3 to the 12-bit Mode ADC Module Specifications (see Table 23-17). Added Note 3 to the 10-bit Mode ADC Module Specifications (see Table 23-18). Section 24.0 “Packaging Information” Added the 28-Lead SSOP package information (see Section 24.1 “Package Marking Information” and Section 24.2 “Package Details”). Added the “SS” definition for the SSOP package. “Product Identification System” DS70289G-page 264 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 INDEX A A/D Converter ................................................................... 157 Initialization ............................................................... 157 Key Features............................................................. 157 AC Characteristics .................................................... 200, 228 ADC Module.............................................................. 231 ADC Module (10-bit Mode) ....................................... 232 ADC Module (12-bit Mode) ....................................... 231 Internal RC Accuracy ................................................ 202 Load Conditions ................................................ 200, 228 ADC Module ADC11 Register Map ...................................... 34, 36, 37 Alternate Interrupt Vector Table (AIVT) .............................. 61 Arithmetic Logic Unit (ALU)................................................. 24 Assembler MPASM Assembler................................................... 188 D Data Address Space........................................................... 27 Alignment.................................................................... 27 Memory Map for PIC24H Devices with 8 KBs RAM ... 28 Near Data Space ........................................................ 27 Software Stack ........................................................... 40 Width .......................................................................... 27 DC Characteristics............................................................ 192 Doze Current (IDOZE)................................................ 227 High Temperature..................................................... 226 I/O Pin Input Specifications ...................................... 197 I/O Pin Output........................................................... 227 I/O Pin Output Specifications.................................... 198 Idle Current (IDOZE) .................................................. 196 Idle Current (IIDLE) .................................................... 195 Operating Current (IDD) ............................................ 194 Operating MIPS vs. Voltage ..................................... 226 Power-Down Current (IPD)........................................ 196 Power-down Current (IPD) ........................................ 226 Program Memory.............................................. 199, 227 Temperature and Voltage......................................... 226 Temperature and Voltage Specifications.................. 193 Thermal Operating Conditions.................................. 226 Development Support ....................................................... 187 B Block Diagrams 16-bit Timer1 Module ................................................ 123 A/D Module ....................................................... 158, 159 Connections for On-Chip Voltage Regulator............. 174 Device Clock ......................................................... 89, 91 Input Capture ............................................................ 131 Output Compare ....................................................... 133 PIC24H ....................................................................... 12 PIC24H CPU Core ...................................................... 20 PLL.............................................................................. 91 Reset System.............................................................. 53 Shared Port Structure ............................................... 103 SPI ............................................................................ 137 Timer2 (16-bit) .......................................................... 127 Timer2/3 (32-bit) ....................................................... 126 UART ........................................................................ 151 Watchdog Timer (WDT) ............................................ 175 E Electrical Characteristics .................................................. 191 AC..................................................................... 200, 228 Equations Device Operating Frequency...................................... 90 Errata .................................................................................... 9 F Flash Program Memory ...................................................... 47 Control Registers........................................................ 48 Operations .................................................................. 48 Programming Algorithm.............................................. 51 RTSP Operation ......................................................... 48 Table Instructions ....................................................... 47 Flexible Configuration ....................................................... 171 C C Compilers MPLAB C18 .............................................................. 188 Clock Switching................................................................... 97 Enabling ...................................................................... 97 Sequence.................................................................... 97 Code Examples Erasing a Program Memory Page............................... 51 Initiating a Programming Sequence............................ 52 Loading Write Buffers ................................................. 52 Port Write/Read ........................................................ 104 PWRSAV Instruction Syntax....................................... 99 Code Protection ........................................................ 171, 176 Configuration Bits.............................................................. 171 Description (Table).................................................... 172 Configuration Register Map .............................................. 171 Configuring Analog Port Pins ............................................ 104 CPU Control Register .......................................................... 22 CPU Clocking System......................................................... 90 Options........................................................................ 90 Selection ..................................................................... 90 Customer Change Notification Service ............................. 257 Customer Notification Service........................................... 257 Customer Support ............................................................. 257 H High Temperature Electrical Characteristics .................... 225 I I/O Ports ........................................................................... 103 Parallel I/O (PIO) ...................................................... 103 Write/Read Timing.................................................... 104 I2 C Addresses................................................................. 144 Operating Modes ...................................................... 143 Registers .................................................................. 143 I2C Module I2C1 Register Map...................................................... 33 In-Circuit Debugger........................................................... 177 In-Circuit Emulation .......................................................... 171 In-Circuit Serial Programming (ICSP)....................... 171, 177 Input Capture Registers .................................................................. 132 Input Change Notification ................................................. 104 © 2011 Microchip Technology Inc. DS70289G-page 265 PIC24HJ32GP202/204 AND PIC24HJ16GP304 Instruction Addressing Modes............................................. 40 File Register Instructions ............................................ 40 Fundamental Modes Supported.................................. 41 MCU Instructions ........................................................ 40 Move and Accumulator Instructions ............................ 41 Other Instructions........................................................ 41 Instruction Set Overview ................................................................... 181 Summary................................................................... 179 Instruction-Based Power-Saving Modes ............................. 99 Idle ............................................................................ 100 Sleep ........................................................................... 99 Internal RC Oscillator Use with WDT ........................................................... 175 Internet Address................................................................ 257 Interrupt Control and Status Registers................................ 65 IECx ............................................................................ 65 IFSx............................................................................. 65 INTCON1 .................................................................... 65 INTCON2 .................................................................... 65 IPCx ............................................................................ 65 Interrupt Setup Procedures ................................................. 87 Initialization ................................................................. 87 Interrupt Disable.......................................................... 87 Interrupt Service Routine ............................................ 87 Trap Service Routine .................................................. 87 Interrupt Vector Table (IVT) ................................................ 61 Interrupts Coincident with Power Save Instructions.......... 100 Program Address Space..................................................... 25 Construction ............................................................... 42 Data Access from Program Memory Using Program Space Visibility ................................................... 45 Data Access from Program Memory Using Table Instructions .................................................................... 44 Data Access from, Address Generation ..................... 43 Memory Map............................................................... 25 Table Read Instructions TBLRDH ............................................................. 44 TBLRDL.............................................................. 44 Visibility Operation ...................................................... 45 Program Memory Interrupt Vector ........................................................... 26 Organization ............................................................... 26 Reset Vector ............................................................... 26 R Reader Response............................................................. 258 Registers AD1CHS0 (ADC1 Input Channel 0 Select ................ 167 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select)... 165 AD1CON1 (ADC1 Control 1) .................................... 161 AD1CON2 (ADC1 Control 2) .................................... 163 AD1CON3 (ADC1 Control 3) .................................... 164 AD1CSSL (ADC1 Input Scan Select Low)................ 169 AD1PCFGL (ADC1 Port Configuration Low) ............ 169 CLKDIV (Clock Divisor) .............................................. 94 CORCON (Core Control) ...................................... 23, 67 I2CxCON (I2Cx Control) ........................................... 145 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 149 I2CxSTAT (I2Cx Status) ........................................... 147 ICxCON (Input Capture x Control)............................ 132 IEC0 (Interrupt Enable Control 0) ......................... 74, 77 IEC1 (Interrupt Enable Control 1) ............................... 76 IFS0 (Interrupt Flag Status 0) ..................................... 70 IFS1 (Interrupt Flag Status 1) ..................................... 72 IFS4 (Interrupt Flag Status 4) ..................................... 73 INTCON1 (Interrupt Control 1).................................... 68 INTCON2 (Interrupt Control 2).................................... 69 INTTREG Interrupt Control and Status Register ........ 86 IPC0 (Interrupt Priority Control 0) ............................... 78 IPC1 (Interrupt Priority Control 1) ............................... 79 IPC16 (Interrupt Priority Control 16) ........................... 85 IPC2 (Interrupt Priority Control 2) ............................... 80 IPC3 (Interrupt Priority Control 3) ............................... 81 IPC4 (Interrupt Priority Control 4) ............................... 82 IPC5 (Interrupt Priority Control 5) ............................... 83 IPC7 (Interrupt Priority Control 7) ............................... 84 NVMCOM (Flash Memory Control)....................... 49, 50 OCxCON (Output Compare x Control) ..................... 135 OSCCON (Oscillator Control) ..................................... 92 OSCTUN (FRC Oscillator Tuning).............................. 96 PLLFBD (PLL Feedback Divisor)................................ 95 PMD1 (Peripheral Module Disable Control Register 1) ........................................................ 101 PMD2 (Peripheral Module Disable Control Register 2) ........................................................ 102 RCON (Reset Control)................................................ 54 SPIxCON1 (SPIx Control 1)...................................... 139 SPIxCON2 (SPIx Control 2)...................................... 141 SPIxSTAT (SPIx Status and Control) ....................... 138 SR (CPU Status)................................................... 22, 66 T1CON (Timer1 Control) .......................................... 124 TxCON (T2CON, T4CON, T6CON or T8CON Control)................................................ 128 J JTAG Boundary Scan Interface ........................................ 171 M Memory Organization.......................................................... 25 Microchip Internet Web Site .............................................. 257 MPLAB ASM30 Assembler, Linker, Librarian ................... 188 MPLAB Integrated Development Environment Software .. 187 MPLAB PM3 Device Programmer..................................... 190 MPLAB REAL ICE In-Circuit Emulator System................. 189 MPLINK Object Linker/MPLIB Object Librarian ................ 188 Multi-Bit Data Shifter ........................................................... 24 N NVM Module Register Map............................................................... 39 O Open-Drain Configuration ................................................. 104 Output Compare................................................................ 133 Registers ................................................................... 135 P Packaging ......................................................................... 235 Details ....................................................................... 236 Marking ..................................................................... 235 Peripheral Module Disable (PMD)..................................... 100 Pinout I/O Descriptions (table) ............................................ 13 PMD Module Register Map............................................................... 39 PORTA Register Map............................................................... 38 PORTB Register Map............................................................... 38 Power-on Reset (POR) ....................................................... 58 Power-Saving Features....................................................... 99 Clock Frequency and Switching.................................. 99 DS70289G-page 266 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 TyCON (T3CON, T5CON, T7CON or T9CON Control) ................................................ 129 UxMODE (UARTx Mode).......................................... 152 UxSTA (UARTx Status and Control)......................... 154 Reset Illegal Opcode ....................................................... 53, 60 Trap Conflict.......................................................... 59, 60 Uninitialized W Register........................................ 53, 60 Reset Sequence ................................................................. 61 Resets ................................................................................. 53 SPIx Master Mode (CKE = 1) ................................... 211 SPIx Slave Mode (CKE = 0) ..................................... 212 SPIx Slave Mode (CKE = 1) ..................................... 213 Timer1, 2, 3, 4, 5, 6, 7, 8, 9 External Clock .............. 206 Timing Requirements ADC Conversion (10-bit mode) ................................ 233 ADC Conversion (12-bit Mode) ................................ 233 CLKO and I/O ........................................................... 203 External Clock .......................................................... 201 Input Capture............................................................ 208 SPIx Master Mode (CKE = 0) ................................... 229 SPIx Module Master Mode (CKE = 1) ...................... 229 SPIx Module Slave Mode (CKE = 0) ........................ 230 SPIx Module Slave Mode (CKE = 1) ........................ 230 Timing Specifications 10-bit A/D Conversion Requirements ....................... 224 12-bit A/D Conversion Requirements ....................... 222 I2Cx Bus Data Requirements (Master Mode)........... 216 I2Cx Bus Data Requirements (Slave Mode)............. 218 Output Compare Requirements................................ 208 PLL Clock ......................................................... 202, 228 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements......................................... 205 Simple OC/PWM Mode Requirements ..................... 209 SPIx Master Mode (CKE = 0) Requirements............ 210 SPIx Master Mode (CKE = 1) Requirements............ 211 SPIx Slave Mode (CKE = 0) Requirements.............. 212 SPIx Slave Mode (CKE = 1) Requirements.............. 214 Timer1 External Clock Requirements....................... 206 Timer2, Timer4, Timer6 and Timer8 External Clock Requirements ......................................... 207 Timer3, Timer5, Timer7 and Timer9 External Clock Requirements ......................................... 207 S Serial Peripheral Interface (SPI) ....................................... 137 Software Reset Instruction (SWR) ...................................... 59 Software Simulator (MPLAB SIM)..................................... 189 Software Stack Pointer, Frame Pointer CALL Stack Frame...................................................... 40 Special Features of the CPU ............................................ 171 SPI Module SPI1 Register Map...................................................... 33 Symbols Used in Opcode Descriptions............................. 180 System Control Register Map............................................................... 39 T Temperature and Voltage Specifications AC ..................................................................... 200, 228 Timer1 ............................................................................... 123 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ..................... 125 Timing Characteristics CLKO and I/O ........................................................... 203 Timing Diagrams 10-bit A/D Conversion............................................... 223 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) ......................... 223 12-bit A/D Conversion (ASAM = 0, SSRC = 000) ........................ 222 Brown-out Situations................................................... 59 External Clock........................................................... 201 I2Cx Bus Data (Master Mode) .................................. 215 I2Cx Bus Data (Slave Mode) .................................... 217 I2Cx Bus Start/Stop Bits (Master Mode) ................... 215 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 217 Input Capture (CAPx)................................................ 208 OC/PWM................................................................... 209 Output Compare (OCx)............................................. 208 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ......................................... 204 SPIx Master Mode (CKE = 0) ................................... 210 U UART Module UART1 Register Map ................................................. 33 Using the RCON Status Bits............................................... 60 V Voltage Regulator (On-Chip) ............................................ 174 W Watchdog Time-out Reset (WDTR).................................... 59 Watchdog Timer (WDT)............................................ 171, 175 Programming Considerations ................................... 175 WWW Address ................................................................. 257 WWW, On-Line Support ....................................................... 9 © 2011 Microchip Technology Inc. DS70289G-page 267 PIC24HJ32GP202/204 AND PIC24HJ16GP304 NOTES: DS70289G-page 268 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2011 Microchip Technology Inc. DS70289G-page 269 PIC24HJ32GP202/204 AND PIC24HJ16GP304 READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS70289G FAX: (______) _________ - _________ Device: PIC24HJ32GP202/204 and PIC24HJ16GP304 Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS70289G-page 270 © 2011 Microchip Technology Inc. PIC24HJ32GP202/204 AND PIC24HJ16GP304 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 HJ 32 GP2 02 T E / SP - XXX Microchip Trademark Architecture Flash Memory Family Program Memory Size (KB) Product Group Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Examples: a) PIC24HJ32GP202-E/SP: General-purpose PIC24H, 32 KB program memory, 28-pin, Extended temp., SPDIP package. Architecture: 24 = 16-bit Microcontroller Flash Memory Family: HJ = Flash program memory, 3.3V Product Group: GP2 GP3 = = General purpose family General purpose family Pin Count: 02 03 = = 28-pin 44-pin -40°C to +85°C (Industrial) -40°C to +125°C (Extended) -40°C to +150°C (High) Temperature Range: I E H = = = Package: SP SO SS MM PT ML = = = = = = Skinny Plastic Dual In-Line - 300 mil body (SPDIP) Plastic Small Outline - Wide - 7.5 mm body (SOIC) Plastic Shrink Small Outline - 5.3 mm body (SSOP) Plastic Quad, No Lead Package - 6x6 mm body (QFN-S) Plastic Thin Quad Flatpack - 10x10x1 mm body (TQFP Plastic Quad, No Lead Package - 8x8 mm body (QFN) © 2011 Microchip Technology Inc. DS70289G-page 271 Worldwide Sales and Service AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-213-7830 Fax: 886-7-330-9305 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 08/04/10 © 2011 Microchip Technology Inc. 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