PIC24HJ32GP302_11

PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Data Sheet High-Performance, 16-bit Microcontrollers © 2011 Microchip Technology Inc. DS70293E Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-821-4 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70293E-page 2 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 High-Performance, 16-bit Microcontrollers Operating Range: • Up to 40 MIPS operation (at 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) • Up to 20 MIPS operation (at 3.0-3.6V): - High temperature range (-40°C to +150°C) Timers/Capture/Compare/PWM: • Timer/Counters, up to five 16-bit timers: - Can pair up to make two 32-bit timers - One timer runs as a Real-Time Clock with an external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to four channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to four channels): - Single or Dual 16-bit Compare mode - 16-bit Glitchless PWM mode • Hardware Real-Time Clock and Calendar (RTCC): - Provides clock, calendar and alarm functions High-Performance CPU: • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions: mostly 1 word/1 cycle Flexible and powerful addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit shifts for up to 40-bit data Interrupt Controller: • • • • • 5-cycle latency Up to 45 available interrupt sources Up to three external interrupts Seven programmable priority levels Five processor exceptions Direct Memory Access (DMA): • 8-channel hardware DMA • Up to 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA Digital I/O: • • • • • Peripheral pin Select functionality Up to 35 programmable digital I/O pins Wake-up/Interrupt-on-Change for up to 31 pins Output pins can drive from 3.0V to 3.6V Up to 5.5V output with open drain configuration on 5V tolerant pins with external pull-up • 4 mA sink on all I/O pins On-Chip Flash and SRAM: • Flash program memory (up to 128 Kbytes) • Data SRAM (up to 8 Kbytes) • Boot, Secure and General Security for program Flash © 2011 Microchip Technology Inc. DS70293E-page 3 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Communication Modules: • 4-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™: - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN 2.0 bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • Enhanced CAN (ECAN™ module) 2.0B active: - Up to eight transmit and up to 32 receive buffers - 16 receive filters and three masks - Loopback, Listen Only and Listen All - Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support • Parallel Master Slave Port (PMP/EPSP): - Supports 8-bit or 16-bit data - Supports 16 address lines • Programmable Cyclic Redundancy Check (CRC): - Programmable bit length for the CRC generator polynomial (up to 16-bit length) - 8-deep, 16-bit or 16-deep, 8-bit FIFO for data input System Management: • Flexible clock options: - External, crystal, resonator and internal RC - Fully integrated Phase-Locked Loop (PLL) - Extremely low jitter PLL • Power-Up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Analog-to-Digital Converters (ADCs): • 10-bit, 1.1 Msps or 12-bit, 500 Ksps conversion: - Two and four simultaneous samples (10-bit ADC) - Up to 13 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±2 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity Comparator Module: • Two analog comparators with programmable input/output configuration CMOS Flash Technology: • • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and Extended temperature Low power consumption Packaging: • 28-pin SDIP/SOIC/QFN-S • 44-pin TQFP/QFN Note: See the device variant tables for exact peripheral features per device. DS70293E-page 4 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PRODUCT FAMILIES The device names, pin counts, memory sizes and peripheral availability of each device are listed below. The following pages show their pinout diagrams. TABLE 1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CONTROLLER FAMILIES Analog Comparator (2 Channels/Voltage Regulator) Remappable Peripheral Program Flash Memory (Kbyte) 8-bit Parallel Master Port (Address Lines) External Interrupts(3) Remappable Pins Output Compare Standard PWM 16-bit Timer(2) 10-bit/12-bit ADC (Channels) Input Capture I2C™ CRC Generator RAM (Kbyte)(1) PIC24HJ128GP504 44 PIC24HJ128GP502 28 128 128 8 8 26 5 16 5 4 4 4 4 2 2 SPI Device 2 2 ECAN™ 1 1 3 3 111 111 13 10 1/1 1/0 11 2 35 21 QFN TQFP SDIP SOIC QFN-S QFN TQFP SDIP SOIC QFN-S QFN TQFP SDIP SOIC QFN-S QFN TQFP SDIP SOIC QFN-S QFN TQFP PIC24HJ128GP204 44 PIC24HJ128GP202 28 128 128 8 8 26 5 16 5 4 4 4 4 2 2 2 2 0 0 3 3 111 111 13 10 1/1 1/0 11 2 35 21 PIC24HJ64GP504 PIC24HJ64GP502 44 28 64 64 8 8 26 5 16 5 4 4 4 4 2 2 2 2 1 1 3 3 111 111 13 10 1/1 1/0 11 2 35 21 PIC24HJ64GP204 PIC24HJ64GP202 44 28 64 64 8 8 26 5 16 5 4 4 4 4 2 2 2 2 0 0 3 3 111 111 13 10 1/1 1/0 11 2 35 21 PIC24HJ32GP304 PIC24HJ32GP302 44 28 32 32 4 4 26 5 16 5 4 4 4 4 2 2 2 2 0 0 3 3 111 111 13 10 1/1 1/0 11 2 35 21 Note 1: 2: 3: SDIP SOIC QFN-S RAM size is inclusive of 2 Kbytes of DMA RAM for all devices except PIC24HJ32GP302/304, which include 1 Kbyte of DMA RAM. Only four out of five timers are remappable. Only two out of three interrupts are remappable. © 2011 Microchip Technology Inc. DS70293E-page 5 Packages UART I/O Pins RTCC Pins PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams 28-Pin SDIP, SOIC MCLR AN0/VREF+/CN2/RA0 AN1/VREF-/CN3/RA1 PGED1/AN2/C2IN-/RP0 /CN4/RB0 PGEC1/ AN3/C2IN+/RP1 /CN5/RB1 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 SOSCI/RP4(1)/CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 (1) (1) Pins are up to 5V tolerant 1 2 3 4 PIC24HJ32GP302 PIC24HJ64GP202 PIC24HJ64GP502 PIC24HJ128GP202 PIC24HJ128GP502 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VCAP(3) VSS TDO/SDA1/RP9(1)/CN21/PMD3/RB9 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 INT0/RP7(1)/CN23/PMD5/RB7 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 28-Pin QFN-S(2) AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15/CN11/PMCS1/RB15 AN10/RTCC/RP14/CN12/PMWR/RB14 Pins are up to 5V tolerant PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/PMA0/RA3 28 27 26 25 24 23 22 1 2 3 4 5 6 7 8 9 10 11 12 13 14 21 PIC24HJ32GP302 PIC24HJ64GP202 PIC24HJ64GP502 PIC24HJ128GP202 PIC24HJ128GP502 20 19 18 17 16 15 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/TMS/RP11(1)/CN15/PMD1/RB11 PGED2/TDI/RP10(1)/CN16/PMD2/RB10 VCAP(3) VSS TDO/SDA1/RP9(1)/CN21/PMD3/RB9 Note 1: 2: 3: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. SOSCI/RP4(1)/CN1/PMBE/RB4 SOSCO/T1CK/CN0/PMA1/RA4 VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3//ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 TCK/SCL1/RP8(1)/CN22/PMD4/RB8 DS70293E-page 6 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin QFN(2) Pins are up to 5V tolerant PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 22 21 20 19 18 17 16 15 14 13 12 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3 /CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4 /CN1/RB4 (1) (1) 23 24 25 26 27 28 29 30 31 32 33 11 10 9 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/RP10(1)/CN16/PMD2/RB10 VCAP(3) VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 PIC24HJ32GP304 PIC24HJ64GP204 PIC24HJ64GP504 PIC24HJ128GP204 PIC24HJ128GP504 8 7 6 5 4 3 2 34 35 36 37 38 39 40 41 42 43 44 SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 RP20(1)/CN25/PMA4/RC4 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 1 Note 1: 2: 3: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. © 2011 Microchip Technology Inc. DS70293E-page 7 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Pin Diagrams (Continued) 44-Pin TQFP PGEC1/AN3/C2IN+/RP1(1)/CN5/RB1 PGED1/AN2/C2IN-/RP0(1)/CN4/RB0 AN1/VREF-/CN3/RA1 AN0/VREF+/CN2/RA0 MCLR AVDD AVSS AN9/RP15(1)/CN11/PMCS1/RB15 AN10/RTCC/RP14(1)/CN12/PMWR/RB14 TCK/PMA7/RA7 TMS/PMA10/RA10 Pins are up to 5V tolerant 22 21 20 19 18 17 16 15 14 13 12 Note 1: 2: The RPx pins can be used by any remappable peripheral. See Table 1 in this section for the list of available peripherals. Refer to Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)” for proper connection to this pin. SOSCO/T1CK/CN0/RA4 TDI/PMA9/RA9 RP19(1)/CN28/PMBE/RC3 (1)/CN25/PMA4/RC4 RP20 RP21(1)/CN26/PMA3/RC5 VSS VDD PGED3/ASDA1/RP5(1)/CN27/PMD7/RB5 PGEC3/ASCL1/RP6(1)/CN24/PMD6/RB6 INT0/RP7(1)/CN23/PMD5/RB7 SCL1/RP8(1)/CN22/PMD4/RB8 34 35 36 37 38 39 40 41 42 43 44 AN4/C1IN-/RP2(1)/CN6/RB2 AN5/C1IN+/RP3(1)/CN7/RB3 AN6/RP16(1)/CN8/RC0 AN7/RP17(1)/CN9/RC1 AN8/CVREF/RP18(1)/PMA2/CN10/RC2 VDD VSS OSC1/CLKI/CN30/RA2 OSC2/CLKO/CN29/RA3 TDO/PMA8/RA8 SOSCI/RP4(1)/CN1/RB4 23 24 25 26 27 28 29 30 31 32 33 PIC24HJ32GP304 PIC24HJ64GP204 PIC24HJ64GP504 PIC24HJ128GP204 PIC24HJ128GP504 11 10 9 8 7 6 5 4 3 2 1 AN11/RP13(1)/CN13/PMRD/RB13 AN12/RP12(1)/CN14/PMD0/RB12 PGEC2/RP11(1)/CN15/PMD1/RB11 PGED2/EMCD2/RP10(1)/CN16/PMD2/RB10 VCAP(2) VSS RP25(1)/CN19/PMA6/RC9 RP24(1)/CN20/PMA5/RC8 RP23(1)/CN17/PMA0/RC7 RP22(1)/CN18/PMA1/RC6 SDA1/RP9(1)/CN21/PMD3/RB9 DS70293E-page 8 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Table of Contents PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Product Families ........................................................ 5 1.0 Device Overview ........................................................................................................................................................................ 11 2.0 Guidelines for Getting Started with 16-bit Microcontrollers ........................................................................................................ 15 3.0 CPU............................................................................................................................................................................................ 19 4.0 Memory Organization ................................................................................................................................................................. 25 5.0 Flash Program Memory.............................................................................................................................................................. 53 6.0 Resets ....................................................................................................................................................................................... 59 7.0 Interrupt Controller ..................................................................................................................................................................... 67 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 105 9.0 Oscillator Configuration ............................................................................................................................................................ 117 10.0 Power-Saving Features............................................................................................................................................................ 127 11.0 I/O Ports ................................................................................................................................................................................... 133 12.0 Timer1 ...................................................................................................................................................................................... 159 13.0 Timer2/3 And TImer4/5 Feature .............................................................................................................................................. 161 14.0 Input Capture............................................................................................................................................................................ 167 15.0 Output Compare....................................................................................................................................................................... 169 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 173 17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 179 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 187 19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 193 20.0 10-bit/12-bit Analog-to-Digital Converter (ADC1) ..................................................................................................................... 219 21.0 Comparator Module.................................................................................................................................................................. 231 22.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 237 23.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 247 24.0 Parallel Master Port (PMP)....................................................................................................................................................... 251 25.0 Special Features ...................................................................................................................................................................... 259 26.0 Instruction Set Summary .......................................................................................................................................................... 269 27.0 Development Support............................................................................................................................................................... 277 28.0 Electrical Characteristics .......................................................................................................................................................... 281 29.0 High Temperature Electrical Characteristics ............................................................................................................................ 331 30.0 Packaging Information.............................................................................................................................................................. 341 Appendix A: Revision History............................................................................................................................................................. 351 Index ................................................................................................................................................................................................. 361 The Microchip Web Site ..................................................................................................................................................................... 365 Customer Change Notification Service .............................................................................................................................................. 365 Customer Support .............................................................................................................................................................................. 365 Reader Response .............................................................................................................................................................................. 366 Product Identification System ............................................................................................................................................................ 367 © 2011 Microchip Technology Inc. DS70293E-page 9 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70293E-page 10 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 1.0 DEVICE OVERVIEW Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This document contains device specific information for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. © 2011 Microchip Technology Inc. DS70293E-page 11 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 1-1: PSV and Table Data Access Control Block Interrupt Controller 8 16 X Data Bus PORTA PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 BLOCK DIAGRAM 16 16 Data Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch DMA RAM PORTB 16 23 16 Address Generator Units DMA Controller PORTC Address Latch Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data Remappable Pins 16 Instruction Decode and Control Control Signals to Various Blocks Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 17 x 17 Multiplier 16 x 16 W Register Array 16 OSC2/CLKO OSC1/CLKI Divide Support 16-bit ALU 16 VCAP VDD, VSS MCLR PMP/ EPSP Comparator 2 Ch. ECAN1 Timers 1-5 UART1, 2 ADC1 OC/ PWM1-4 RTCC SPI1, 2 IC1, 2, 7, 8 CNx I2C1 Note: Not all pins or features are implemented on all device pinout configurations. See “Pin Diagrams” for the specific pins and features present on each device. DS70293E-page 12 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 1-1: Pin Name AN0-AN12 CLKI PINOUT I/O DESCRIPTIONS Pin Type I I Buffer Type Analog ST/CMOS No PPS Analog input channels. External clock source input. Always associated with OSC1 pin function. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. 32.768 kHz low-power oscillator crystal input; CMOS otherwise. 32.768 kHz low-power oscillator crystal output. Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture inputs 1/2 Capture inputs 7/8. Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare outputs 1 through 4. External interrupt 0. External interrupt 1. External interrupt 2. PORTA is a bidirectional I/O port. PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Analog = Analog input O = Output TTL = TTL input buffer P = Power I = Input Description CLKO OSC1 OSC2 SOSCI SOSCO CN0-CN30 IC1-IC2 IC7-IC8 OCFA OC1-OC4 INT0 INT1 INT2 RA0-RA4 RA7-RA10 RB0-RB15 RC0-RC9 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 O I I/O I O I I I I O I I I I/O I/O I/O I/O I I I I I I O I O I O I O I/O I O I/O I/O I O I/O — ST/CMOS — ST/CMOS — ST ST ST ST — ST ST ST ST ST ST ST ST ST ST ST ST ST — ST — ST — ST — ST ST — ST ST ST — ST No No No No No No Yes Yes Yes Yes No Yes Yes No No No No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select © 2011 Microchip Technology Inc. DS70293E-page 13 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 1-1: Pin Name SCL1 SDA1 ASCL1 ASDA1 TMS TCK TDI TDO C1RX C1TX RTCC CVREF C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PMA1 PMA2 -PMPA10 PMBE PMCS1 PMD0-PMPD7 PMRD PMWR PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 MCLR AVDD AVSS VDD VCAP VSS VREF+ VREF- PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I/O I/O I/O I/O I I I O I O O O I I O I I O I/O I/O O O O I/O O O I/O I I/O I I/O I I/P P P P P P I I Buffer Type ST ST ST ST ST ST ST — ST — — ANA ANA ANA — ANA ANA — TTL/ST TTL/ST — — — TTL/ST — — ST ST ST ST ST ST ST P P — — — Analog Analog PPS No No No No No No No No Yes Yes No No No No Yes No No Yes No No No No No No No No No No No No No No No No No No No No No No Description Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Alternate synchronous serial clock input/output for I2C1. Alternate synchronous serial data input/output for I2C1. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. ECAN1 bus receive pin. ECAN1 bus transmit pin. Real-Time Clock Alarm Output. Comparator Voltage Reference Output. Comparator 1 Negative Input. Comparator 1 Positive Input. Comparator 1 Output. Comparator 2 Negative Input. Comparator 2 Positive Input. Comparator 2 Output. Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). Parallel Master Port Address (Demultiplexed Master Modes). Parallel Master Port Byte Enable Strobe. Parallel Master Port Chip Select 1 Strobe. Parallel Master Port Data (Demultiplexed Master mode) or Address/ Data (Multiplexed Master modes). Parallel Master Port Read Strobe. Parallel Master Port Write Strobe. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output TTL = TTL input buffer P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels PPS = Peripheral Pin Select DS70293E-page 14 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS 2.2 Decoupling Capacitors The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP (see Section 2.3 “CPU Logic Filter Capacitor Connection (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2011 Microchip Technology Inc. DS70293E-page 15 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. VDD R R1 10 µF Tantalum VCAP VDD VSS MCLR C PIC24H VSS VDD VDD VSS AVDD AVSS VDD VSS 0.1 µF Ceramic 0.1 µF Ceramic 10 Ω 0.1 µF Ceramic 0.1 µF Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 MCLR JP C PIC24H 2.3 CPU Logic Filter Capacitor Connection (VCAP) Note 1: A low-ESR (< 5 Ohms) capacitor is required on the VCAP pin, which is used to stabilize the voltage regulator output voltage. The VCAP pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 28.0 “Electrical Characteristics” for additional information. The placement of this capacitor should be close to the VCAP. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 25.2 “On-Chip Voltage Regulator” for details. R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS70293E-page 16 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB® ICD 3 or MPLAB® REAL ICE™. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. • “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring 14 15 Guard Trace Secondary Oscillator 16 17 18 19 20 © 2011 Microchip Technology Inc. DS70293E-page 17 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 2.7 Oscillator Value Conditions on Device Start-up 2.9 Unused I/Os If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to ≤ 8 MHz for start-up with the PLL enabled to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor between VSS and the unused pins. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. DS70293E-page 18 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.0 CPU The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the PIC24HJ32GP302/ 304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/ X04 is shown in Figure 3-2. Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 2. CPU” (DS70204) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 3.1 Overview The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. 3.2 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. © 2011 Microchip Technology Inc. DS70293E-page 19 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.3 Special MCU Features The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices support 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 features a 17-bit by 17bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. FIGURE 3-1: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CPU CORE BLOCK DIAGRAM PSV and Table Data Access Control Block Interrupt Controller 8 16 X Data Bus 16 16 Data Latch 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch DMA RAM 16 23 16 Address Latch Address Generator Units DMA Controller Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode and Control Instruction Reg 16 Control Signals to Various Blocks 17 x 17 Multiplier 16 x 16 W Register Array 16 Divide Support 16-bit ALU 16 To Peripheral Modules DS70293E-page 20 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 3-2: PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 PROGRAMMER’S MODEL D15 W0/WREG W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer Working Registers D0 PUSH.S Shadow Legend SPLIM Stack Pointer Limit Register PC22 PC0 0 Program Counter 7 TBLPAG 7 PSVPAG 0 Data Table Page Address 0 Program Space Visibility Page Address 15 RCOUNT 0 REPEAT Loop Counter 15 CORCON 0 Core Configuration Register — — — — — — — DC IPL2 IPL1 IPL0 RA SRL N OV Z C STATUS Register SRH © 2011 Microchip Technology Inc. DS70293E-page 21 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.4 CPU Control Registers SR: CPU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0(2) IPL(2) bit 7 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set bit 15-9 bit 8 R = Readable bit W = Writable bit ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (two’s complement). It indicates an overflow of a magnitude that causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation that affects the Z bit has set it at some time in the past 0 = The most recent operation that affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. The IPL Status bits are read only when the NSTDIS bit (INTCON1) = 1. U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown R/W-0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z R/W-0 C bit 0 REGISTER 3-1: U-0 — bit 15 R/W-0(1) bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: DS70293E-page 22 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 3-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 C = Clear only bit W = Writable bit ‘x = Bit is unknown CORCON: CORE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ bit 2 bit 1-0 Note 1: Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. © 2011 Microchip Technology Inc. DS70293E-page 23 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 3.5 Arithmetic Logic Unit (ALU) 3.5.2 DIVIDER The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are two’s complement in nature. Depending on the operation, the ALU can affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. For information on the SR bits affected by each instruction, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit-divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: • • • • 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. 16-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.5.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. 3.5.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several MCU multiplication modes: • • • • • • • 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS70293E-page 24 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 4. “Program Memory” (DS70203) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 4.1 Program Address Space The program address memory space of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is 4M instructions. The space is addressable by a 24-bit value derived either from the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program and Data Memory Spaces”. User application access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. The memory map for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is shown in Figure 4-1. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 DEVICES PIC24HJ64GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ128GPX02/X04 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 PIC24HJ32GP302/304 GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table User Program Flash Memory (11264 instructions) User Memory Space User Program Flash Memory (22016 instructions) User Program Flash Memory (44032 instructions) 0x0057FE 0x005800 0x00ABFE 0x00AC00 Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 0x0157FE 0x015800 Reserved Configuration Memory Space Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80018 Reserved Reserved Reserved 0xFEFFFE 0xFF0000 0xFF0002 0xFFFFFE DEVID (2) Reserved DEVID (2) Reserved DEVID (2) Reserved Note: Memory areas are not shown to scale. © 2011 Microchip Technology Inc. DS70293E-page 25 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement provides compatibility with data memory space addressing and makes data in the program memory space accessible. All PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user application at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70293E-page 26 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.2 Data Address Space All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed. If the error occurred on a write, the instruction is executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user application to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. A sign-extend instruction (SE) is provided to allow user applications to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, user applications can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 CPU has a separate 16 bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. The data memory maps are shown in Figure 4-3 and Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.4.3 “Reading Data from Program Memory Using Program Space Visibility”). PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices implement up to 8 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte is returned. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes (LSBs) of each word have even addresses, while the Most Significant Bytes (MSBs) have odd addresses. The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. Note: The actual set of peripheral features and interrupts varies by the device. Refer to the corresponding device tables and pinout diagrams for device-specific information. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] results in a value of Ws + 1 for byte operations and Ws + 2 for word operations. A data byte read, reads the complete word that contains the byte, using the LSB of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register that matches the byte address. 4.2.4 NEAR DATA SPACE The 8 Kbyte area between 0x0000 and 0x1FFF is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an address pointer. © 2011 Microchip Technology Inc. DS70293E-page 27 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.2.5 DMA RAM When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. The PIC24HJ32GP302/304 devices contain 1 Kbytes of dual ported DMA RAM located at the end of X data space. The PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices contain 2 Kbytes of dual ported DMA RAM located at the end of X data space, and is a part of X data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJ32GP302/304 DEVICES WITH 4 KB RAM MSb Address MSb 0x0000 SFR Space 0x07FF 0x0801 0x07FE 0x0800 6 Kbyte Near Data Space 0x13FE 0x1400 DMA RAM 0x17FF 0x1801 0x8001 0x17FE 0x1800 LSb Address LSb 0x0000 16 bits 2 Kbyte SFR Space X Data RAM (X) 4 Kbyte SRAM Space 0x13FF 0x1401 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70293E-page 28 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 4-4: DATA MEMORY MAP FOR PIC24HJ128GP202/204, PIC24HJ64GP202/204, PIC24HJ128GP502/504 AND PIC24HJ64GP502/504 DEVICES WITH 8 KB RAM MSb Address MSb 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 8 Kbyte Near Data Space 0x1FFE 0x2000 DMA RAM 0x27FF 0x2801 0x27FE 0x2800 16 bits LSb 0x0000 LSb Address X Data RAM (X) 8 Kbyte SRAM Space 0x1FFF 0x2001 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE © 2011 Microchip Technology Inc. DS70293E-page 29 DS70293E-page 30 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-1: SFR Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT Legend: SFR Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL2 — IPL1 — IPL0 — RA — N IPL3 OV PSV Z — C — 0000 0000 0000 xxxx 0000 0000 xxxx Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Repeat Loop Counter Register DC — Disable Interrupts Counter Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70293E-page 31 TABLE 4-2: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 Bit 15 CN15IE — Bit 14 CN14IE CN30IE Bit 13 CN13IE CN29IE Bit 12 CN12IE — Bit 11 CN11IE CN27IE Bit 10 —— — — Bit 9 — — — — Bit 8 — CN24IE — Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE — CN4PUE — Bit 3 CN3IE — CN3PUE — Bit 2 CN2IE — CN2PUE — Bit 1 CN1IE — CN1PUE — Bit 0 CN0IE CN16IE CN0PUE CN16PUE All Resets 0000 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE — CN30PUE CN29PUE — CN27PUE CN24PUE CN23PUE CN22PUE CN21PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-3: SFR Name CNEN1 CNEN2 CNPU1 SFR Addr 0060 0062 0068 CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 Bit 15 CN15IE — Bit 14 CN14IE CN30IE Bit 13 CN13IE CN29IE Bit 12 CN12IE CN28IE Bit 11 CN11IE CN27IE Bit 10 CN10IE CN26IE Bit 9 CN9IE CN25IE CN9PUE Bit 8 CN8IE CN24IE CN8PUE Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE — CNPU2 006A Legend: CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 32 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-4: SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC11 IPC15 IPC16 IPC17 SFR Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00BA 00C2 00C4 00C6 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT — U2TXIF — — — — U2TXIE — — — — — — — — — — — — — — — — — — — — — — — — Bit 14 — DISI DMA1IF U2RXIF DMA4IF RTCIF — DMA1IE U2RXIE DMA4IE RTCIE — Bit 13 — — AD1IF INT2IF PMPIF DMA5IF — AD1IE INT2IE PMPIE DMA5IE — T1IP T2IP U1RXIP — CNIP IC8IP T4IP U2TXIP C1IP(1) — — — CRCIP — — — — — — — — Bit 12 — — U1TXIF T5IF — — — U1TXIE T5IE — — — Bit 11 — — U1RXIF T4IF — — — U1RXIE T4IE — — — — — — — — — — — — — — — — — — Bit 10 — — SPI1IF OC4IF — — — SPI1IE OC4IE — — — Bit 9 — — SPI1EIF OC3IF — — — SPI1EIE OC3IE — — — OC1IP OC2IP SPI1IP DMA1IP CMIP IC7IP OC4IP U2RXIP C1RXIP(1) — DMA4IP RTCIP U2EIP C1TXIP(1) ILR — Bit 8 — — T3IF DMA2IF — — — T3IE DMA2IE — — — Bit 7 — — T2IF IC8IF — — — T2IE IC8IE — — — — — — — — — — — — — — — — — — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 — INT0EP INT0IF All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4444 4404 4444 4444 4444 0004 — — — 0440 0440 4440 0444 4444 DIV0ERR DMACERR MATHERR ADDRERR STKERR OSCFAIL — OC2IF IC7IF — — C1TXIF(1) OC2IE IC7IE — — C1TXIE(1) — IC2IF — — — DMA7IF IC2IE — — — DMA7IE IC1IP IC2IP SPI1EIP AD1IP MI2C1IP — OC3IP INT2IP SPI2IP — PMPIP DMA5IP U1EIP DMA7IP — — — DMA0IF INT1IF DMA3IF — DMA6IF DMA0IE INT1IE DMA3IE — DMA6IE — T1IF CNIF C1IF(1) — CRCIF T1IE CNIE C1IE(1) — CRCIE — — — — — — — — — — — — — — VECNUM — — — INT2EP OC1IF CMIF C1RXIF(1) — U2EIF OC1IE CMIE C1RXIE(1) — U2EIE INT1EP IC1IF MI2C1IF SI2C1IF SPI2IF — U1EIF IC1IE SPI2EIF — — INT0IE MI2C1IE SI2C1IE SPI2IE — U1EIE INT0IP DMA0IP T3IP U1TXIP SI2C1IP INT1IP DMA2IP T5IP SPI2EIP DMA3IP — — — DMA6IP SPI2EIE — — INTTREG 00E0 Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Interrupts disabled on devices without ECAN™ modules. © 2011 Microchip Technology Inc. DS70293E-page 33 TABLE 4-5: SFR Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 PR5 T4CON T5CON Legend: SFR Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 Timer1 Register Period Register 1 TON — TSIDL — — — — — — TGATE TCKPS — TSYNC TCS — PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FFFF 0000 0000 xxxx 0000 FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 0000 xxxx 0000 FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON — — TSIDL TSIDL — — — — — — — — — — — — Timer4 Register Timer5 Holding Register (for 32-bit timer operations only) Timer5 Register Period Register 4 Period Register 5 TON TON — — TSIDL TSIDL — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-6: SFR Name IC1BUF IC1CON IC2BUF IC2CON IC7BUF IC7CON IC8BUF IC8CON Legend: SFR Addr 0140 0142 0144 0146 0158 015A 015C 015E INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 xxxx ICI ICOV ICBNE ICM 0000 Input 1 Capture Register — — ICSIDL — — — — — ICTMR Input 2 Capture Register — — ICSIDL — — — — — ICTMR Input 7 Capture Register — — ICSIDL — — — — — ICTMR Input 8Capture Register — — ICSIDL — — — — — ICTMR x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 34 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-7: SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON Legend: SFR Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — OCFLT OCTSEL OCM 0000 xxxx xxxx — OCFLT OCTSEL OCM 0000 xxxx xxxx — OCFLT OCTSEL OCM 0000 xxxx xxxx — OCFLT OCTSEL OCM 0000 Output Compare 1 Secondary Register Output Compare 1 Register — — OCSIDL — — — — — — — Output Compare 2 Secondary Register Output Compare 2 Register — — OCSIDL — — — — — — — Output Compare 3 Secondary Register Output Compare 3 Register — — OCSIDL — — — — — — — Output Compare 4 Secondary Register Output Compare 4 Register — — OCSIDL — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-8: SFR Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: SFR Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKDT D_A ACKEN P RCEN S Address Register Address Mask Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-9: SFR Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: SFR Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — UTXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Bit 8 UEN0 TRMT UTX8 URX8 Baud Rate Generator Prescaler Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR URXISEL UART Transmit Register UART Received Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70293E-page 35 TABLE 4-10: SFR Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: SFR Addr 0230 0232 0234 0236 0238 UART2 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — UTXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Bit 8 UEN0 TRMT UTX8 URX8 Baud Rate Generator Prescaler Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 URXISEL UART Transmit Register UART Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-11: SFR Name SPI1STAT SPI1CON1 SPI1CON2 SPI1BUF Legend: SFR Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF Bit 0 SPIRBF All Resets 0000 0000 0000 0000 PPRE FRMDLY — SPI1 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-12: SFR Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: SFR Addr 0260 0262 0264 0268 SPI2 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF Bit 0 SPIRBF All Resets 0000 0000 0000 0000 PPRE FRMDLY — SPI2 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 36 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-13: File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL AD1CON4 Legend: Addr 0300 0320 0322 0324 0326 0328 032C 0330 0332 ADC1 REGISTER MAP FOR PIC24HJ64GP202/502, PIC24HJ128GP202/502 AND PIC24HJ32GP302 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC BUFS — — SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123NA CH0SA PCFG4 CSS4 — PCFG3 CSS3 — PCFG2 CSS2 PCFG1 CSS1 DMABL PCFG0 CSS0 CH123SA 0000 0000 0000 0000 0000 ADC Data Buffer 0 ADON — VCFG ADRC — CH0NB — — — — — — — — — — — — — — — PCFG12 CSS12 — — — ADSIDL ADDMABM — — — AD12B CSCNA SAMC CH123NB CH0SB PCFG11 PCFG10 CSS11 — CSS10 — PCFG9 CSS9 — — — — CH123SB — CH0NA — — — — — — — — — — PCFG5 CSS5 — FORM CHPS SMPI ADCS — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-14: File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGL AD1CSSL AD1CON4 Legend: Addr 0300 0320 0322 0324 0326 0328 032C 0330 0332 ADC1 REGISTER MAP FOR PIC24HJ64GP204/504, PIC24HJ128GP204/504 AND PIC24HJ32GP304 Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC BUFS — — SIMSAM ASAM SAMP BUFM DONE ALTS 0000 0000 0000 CH123NA CH0SA PCFG4 CSS4 — PCFG3 CSS3 — PCFG2 CSS2 PCFG1 CSS1 DMABL PCFG0 CSS0 CH123SA 0000 0000 0000 0000 0000 ADC Data Buffer 0 ADON — VCFG ADRC — CH0NB — — — — — — — — — — — — — — — PCFG12 CSS12 — — — ADSIDL ADDMABM — — — AD12B CSCNA SAMC CH123NB CH0SB PCFG11 PCFG10 CSS11 — CSS10 — PCFG9 CSS9 — PCFG8 CSS8 — CH123SB — CH0NA PCFG7 CSS7 — — — PCFG6 CSS6 — — — PCFG5 CSS5 — FORM CHPS SMPI ADCS — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70293E-page 37 TABLE 4-15: File Name DMA0CON DMA0REQ DMA0STA DMA0STB DMA0PAD DMA0CNT DMA1CON DMA1REQ DMA1STA DMA1STB DMA1PAD DMA1CNT DMA2CON DMA2REQ DMA2STA DMA2STB DMA2PAD DMA2CNT DMA3CON DMA3REQ DMA3STA DMA3STB DMA3PAD DMA3CNT DMA4CON DMA4REQ DMA4STA DMA4STB DMA4PAD DMA4CNT DMA5CON DMA5REQ DMA5STA DMA5STB Legend: Addr 0380 0382 0384 0386 0388 038A 038C 038E 0390 0392 0394 0396 0398 039A 039C 039E 03A0 03A2 03A4 03A6 03A8 03AA 03AC 03AE 03B0 03B2 03B4 03B6 03B8 03BA 03BC 03BE 03C0 03C2 DMA REGISTER MAP Bit 15 CHEN FORCE Bit 14 SIZE — Bit 13 DIR — Bit 12 HALF — Bit 11 NULLW — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE Bit 6 — Bit 5 Bit 4 Bit 3 — IRQSEL Bit 2 — Bit 1 Bit 0 All Resets 0000 AMODE MODE PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 38 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-15: File Name DMA5PAD DMA5CNT DMA6CON DMA6REQ DMA6STA DMA6STB DMA6PAD DMA6CNT DMA7CON DMA7REQ DMA7STA DMA7STB DMA7PAD DMA7CNT DMACS0 DMACS1 DSADR Legend: Addr 03C4 03C6 03C8 03CA 03CC 03CE 03D0 03D2 03D4 03D6 03D8 03DA 03DC 03DE 03E0 03E2 03E4 DMA REGISTER MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — — — — — — XWCOL7 PPST7 DSADR XWCOL6 PPST6 CNT XWCOL5 PPST5 XWCOL4 PPST4 XWCOL3 PPST3 XWCOL2 PPST2 XWCOL1 PPST1 XWCOL0 PPST0 — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 — — — — LSTCH — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-16: File Name C1CTRL1 C1CTRL2 C1VEC C1FCTRL C1FIFO C1INTF C1INTE C1EC C1CFG1 C1CFG2 C1FEN1 C1FMSKSEL1 C1FMSKSEL2 Legend: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) Bit 15 — — — Bit 14 — — — DMABS — — — — — — TXBO — TXBP — Bit 13 CSIDL — — — — FBP RXBP — TXWAR — RXWAR — EWARN — Bit 12 ABAT — Bit 11 — — — FILHIT — — — Bit 10 Bit 9 REQOP — — — — — — IVRIF IVRIE — — WAKIF WAKIE ERRIF ERRIE — — — Bit 8 Bit 7 Bit 6 OPMODE — — Bit 5 Bit 4 — Bit 3 CANCAP Bit 2 — Bit 1 — Bit 0 WIN All Resets 0480 © 2011 Microchip Technology Inc. DS70293E-page 39 Addr 0400 0402 0404 0406 0408 040A 040C 040E 0410 0412 0414 0418 041A DNCNT ICODE FSA FNRB FIFOIF FIFOIE RBOVIF RBOVIE RBIF RBIE TBIF TBIE PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 0000 0000 0000 0000 0000 0000 0000 0000 TERRCNT — — FLTEN15 — WAKFIL FLTEN14 — — FLTEN13 — — FLTEN12 — — FLTEN11 — — SEG2PH FLTEN10 FLTEN9 FLTEN8 — SJW SEG2PHTS FLTEN7 SAM FLTEN6 RERRCNT BRP SEG1PH FLTEN5 FLTEN4 FLTEN3 PRSEG FLTEN2 FLTEN1 FLTEN0 0000 FFFF 0000 0000 F7MSK F15MSK F6MSK F14MSK F5MSK F13MSK F4MSK F12MSK F3MSK F11MSK F2MSK F10MSK F1MSK F9MSK F0MSK F8MSK — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-17: File Name Addr 0400041E C1RXFUL1 C1RXFUL2 C1RXOVF1 C1RXOVF2 0420 0422 0428 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXFUL5 RXFUL4 RXFUL3 RXFUL2 RXFUL1 RXFUL0 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TXEN1 TXEN3 TXEN5 TXEN7 TXABT1 TXABT3 TXABT5 TXABT7 TXLARB1 TXLARB3 TXLARB5 TXLARB7 TXERR1 TXERR3 TXERR5 TXERR7 TXREQ1 TXREQ3 TXREQ5 TXREQ7 RTREN1 RTREN3 RTREN5 RTREN7 TX1PRI TX3PRI TX5PRI TX7PRI TXEN0 TXEN2 TXEN4 TXEN6 TXABT0 TXABT2 TXABT4 TXABT6 TXLARB0 TXLARB2 TXLARB4 TXLARB6 TXERR0 TXERR2 TXERR4 TXERR6 TXREQ0 TXREQ2 TXREQ4 TXREQ6 RTREN0 RTREN2 RTREN4 RTREN6 TX0PRI TX2PRI TX4PRI TX6PRI C1TR01CON 0430 C1TR23CON 0432 C1TR45CON 0434 C1TR67CON 0436 C1RXD C1TXD Legend: 0440 0442 Received Data Word Transmit Data Word x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 40 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-18: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Addr 0400041E See definition when WIN = x F3BP F7BP F11BP F15BP SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID SID SID SID SID SID SID SID SID SID SID SID SID F2BP F6BP F10BP F14BP F1BP F5BP F9BP F13BP SID — MIDE F0BP F4BP F8BP F12BP — EID 0000 0000 0000 0000 xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx C1BUFPNT1 C1BUFPNT2 C1BUFPNT3 C1BUFPNT4 C1RXM0SID C1RXM0EID C1RXM1SID C1RXM1EID C1RXM2SID C1RXM2EID C1RXF0SID C1RXF0EID C1RXF1SID C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID C1RXF6SID C1RXF6EID C1RXF7SID C1RXF7EID C1RXF8SID C1RXF8EID C1RXF9SID C1RXF9EID C1RXF10SID C1RXF10EID Legend: 0420 0422 0424 0426 0430 0432 0434 0436 0438 043A 0440 0442 0444 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 046A EID — MIDE EID — MIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID — EXIDE EID x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-18: File Name C1RXF11SID C1RXF11EID C1RXF12SID C1RXF12EID C1RXF13SID C1RXF13EID C1RXF14SID C1RXF14EID C1RXF15SID C1RXF15EID Legend: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 (FOR PIC24HJ128GP502/504 AND PIC24HJ64GP502/504) (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 SID Bit 5 Bit 4 — Bit 3 EXIDE Bit 2 — Bit 1 Bit 0 All Resets xxxx © 2011 Microchip Technology Inc. DS70293E-page 41 Addr 046C 046E 0470 0472 0474 0476 0478 047A 047C 047E SID EID SID EID SID EID SID EID SID EID EID PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 EID SID — EXIDE — EID xxxx xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx — EID xxxx xxxx EID SID — EXIDE EID SID — EXIDE EID SID — EXIDE EID x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-19: File Name RPINR0 RPINR1 RPINR3 RPINR4 RPINR7 RPINR10 RPINR11 RPINR18 RPINR19 RPINR20 RPINR21 RPINR22 RPINR23 RPINR26(1) Legend: Note 1: Addr 0680 0682 0686 0688 068E 0694 0696 06A4 06A6 06A8 06AA 06AC 06AE 06B4 PERIPHERAL PIN SELECT INPUT REGISTER MAP Bit 15 Bit 14 — — — — — — — — — — — — — — — — — — — — — — — — — — — — Bit 13 — — — — — — — — — — — — — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 INT1R — T3CKR T5CKR IC2R IC8R — U1CTSR U2CTSR SCK1R — SCK2R — — — — — — — — — — — — Bit 9 Bit 8 Bit 7 — — — — — — — — — — — — — — Bit 6 — — — — — — — — — — — — — — Bit 5 — — — — — — — — — — — — — — Bit 4 — Bit 3 — Bit 2 — INT2R T2CKR T4CKR IC1R IC7R OCFAR U1RXR U2RXR SDI1R SS1R SDI2R SS2R C1RXR Bit 1 — Bit 0 — All Resets 1F00 001F 1F1F 1F1F 1F1F 1F1F 001F 1F1F 1F1F 1F1F 001F 1F1F 001F 001F x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is present for PIC24HJ128GP502/504 and PIC24HJ64GP502/504 devices only. DS70293E-page 42 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-20: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 Legend: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 Bit 15 — — — — — — — Bit 14 — — — — — — — Bit 13 — — — — — — — Bit 12 Bit 11 Bit 10 RP1R RP3R RP5R RP7R RP9R RP11R RP13R Bit 9 Bit 8 Bit 7 — — — — — — — Bit 6 — — — — — — — — Bit 5 — — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 06CE — — — RP15R — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-21: File Name RPOR0 RPOR1 RPOR2 RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 Legend: Addr 06C0 06C2 06C4 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 PERIPHERAL PIN SELECT OUTPUT REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 Bit 15 — — — — — — — — — — — — Bit 14 — — — — — — — — — — — — Bit 13 — — — — — — — — — — — — Bit 12 Bit 11 Bit 10 RP1R RP3R RP5R RP7R RP9R RP11R RP13R RP15R RP17R RP19R RP21R RP23R Bit 9 Bit 8 Bit 7 — — — — — — — — — — — — Bit 6 — — — — — — — — — — — — — Bit 5 — — — — — — — — — — — — — Bit 4 Bit 3 Bit 2 RP0R RP2R RP4R RP6R RP8R RP10R RP12R RP14R RP16R RP18R RP20R RP22R RP24R Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 06D8 — — — RP25R — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70293E-page 43 TABLE 4-22: File Name PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 PMDIN1 PMPDIN2 PMAEN PMSTAT Legend: Addr 0600 0602 0604 0606 0608 060A 060C 060E PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HPIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 Bit 15 PMPEN BUSY ADDR15 Bit 14 — Bit 13 PSIDL Bit 12 Bit 11 Bit 10 PTBEEN MODE16 Bit 9 Bit 8 Bit 7 CSF1 Bit 6 CSF0 Bit 5 ALP Bit 4 — Bit 3 CS1P Bit 2 BEP Bit 1 WRSP Bit 0 RDSP All Resets PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 ADRMUX INCM PTWREN PTRDEN MODE 0000 0000 0000 0000 0000 0000 0000 IRQM CS1 WAITB ADDR WAITM WAITE Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) — IBF PTEN14 IBOV — — — — — IB3F — IB2F — IB1F — IB0F — OBE — OBUF — — — — — OB3E — OB2E PTEN OB1E OB0E 0000 008F — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-23: File Name PMCON PMMODE PMADDR PMDOUT1 PMDOUT2 PMDIN1 PMPDIN2 PMAEN PMSTAT Legend: Addr 0600 0602 0604 0606 0608 060A 060C 060E PARALLEL MASTER/SLAVE PORT REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 Bit 15 PMPEN BUSY ADDR15 Bit 14 — Bit 13 PSIDL Bit 12 Bit 11 Bit 10 PTBEEN MODE16 Bit 9 Bit 8 Bit 7 CSF1 Bit 6 CSF0 Bit 5 ALP Bit 4 — Bit 3 CS1P Bit 2 BEP Bit 1 WRSP Bit 0 RDSP All Resets 0000 0000 0000 0000 0000 0000 0000 0000 — OB3E OB2E OB1E OB0E 008F ADRMUX INCM PTWREN PTRDEN MODE IRQM CS1 WAITB ADDR WAITM WAITE Parallel Port Data Out Register 1 (Buffers 0 and 1) Parallel Port Data Out Register 2 (Buffers 2 and 3) Parallel Port Data In Register 1 (Buffers 0 and 1) Parallel Port Data In Register 2 (Buffers 2 and 3) — IBF PTEN14 IBOV — — — — — IB3F IB2F IB1F IB0F OBE OBUF PTEN — — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70293E-page 44 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-24: File Name ALRMVAL ALCFGRPT RTCVAL RCFGCAL PADCFG1 Legend: Addr 0620 0622 0624 0626 02FC REAL-TIME CLOCK AND CALENDAR REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ARPT 0000 xxxx CAL — — — — — — RTSECSEL PMPTTL 0000 0000 Alarm Value Register Window based on APTR ALRMEN CHIME AMASK ALRMPTR RTCC Value Register Window based on RTCPTR RTCEN — — — RTCWREN RTCSYNC HALFSEC — — — RTCOE — RTCPTR — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-25: File Name CRCCON CRCXOR CRCDAT CRCWDAT Legend: Addr 0640 0642 0644 0646 CRC REGISTER MAP Bit 15 — Bit 14 — Bit 13 CSIDL Bit 12 Bit 11 Bit 10 VWORD Bit 9 Bit 8 Bit 7 CRCFUL X CRC Data Input Register CRC Result Register Bit 6 CRCMPT Bit 5 — Bit 4 CRCGO Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 PLEN — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-26: File Name CMCON CVRCON Legend: Addr 0630 0632 DUAL COMPARATOR REGISTER MAP Bit 15 CMIDL — Bit 14 — — Bit 13 C2EVT — Bit 12 C1EVT — Bit 11 C2EN — Bit 10 C1EN — Bit 9 C2OUTEN — Bit 8 C1OUTEN — Bit 7 C2OUT CVREN Bit 6 C1OUT CVROE Bit 5 C2INV CVRR Bit 4 C1INV CVRSS Bit 3 C2NEG Bit 2 C2POS Bit 1 C1NEG Bit 0 C1POS All Resets 0000 0000 CVR — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-27: File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP FOR PIC24HJ128GP202/502, PIC24HJ64GP202/502 AND PIC24HJ32GP302 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 — — — — Bit 7 — — — — Bit 6 — — — — Bit 5 — — — — Bit 4 TRISA4 RA4 LATA4 — Bit 3 TRISA3 RA3 LATA3 — Bit 2 TRISA2 RA2 LATA2 — Bit 1 TRISA1 RA1 LATA1 — Bit 0 TRISA0 RA0 LATA0 — All Resets 001F xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. © 2011 Microchip Technology Inc. DS70293E-page 45 TABLE 4-28: File Name TRISA PORTA LATA ODCA Legend: Addr 02C0 02C2 02C4 02C6 PORTA REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 TRISA10 RA10 LATA10 ODCA10 Bit 9 TRISA9 RA9 LATA9 ODCA9 Bit 8 TRISA8 RA8 LATA8 ODCA8 Bit 7 TRISA7 RA7 LATA7 ODCA7 Bit 6 — — — — Bit 5 — — — — Bit 4 TRISA4 RA4 LATA4 — Bit 3 TRISA3 RA3 LATA3 — Bit 2 TRISA2 RA2 LATA2 — Bit 1 TRISA1 RA1 LATA1 — Bit 0 TRISA0 RA0 LATA0 — All Resets 079F PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-29: File Name TRISB PORTB LATB ODCB Legend: Addr 02C8 02CA 02CC 02CE PORTB REGISTER MAP Bit 15 TRISB15 RB15 LATB15 — Bit 14 TRISB14 RB14 LATB14 — Bit 13 TRISB13 RB13 LATB13 — Bit 12 TRISB12 RB12 LATB12 — Bit 11 TRISB11 RB11 LATB11 ODCB11 Bit 10 TRISB10 RB10 LATB10 ODCB10 Bit 9 TRISB9 RB9 LATB9 ODCB9 Bit 8 TRISB8 RB8 LATB8 ODCB8 Bit 7 TRISB7 RB7 LATB7 ODCB7 Bit 6 TRISB6 RB6 LATB6 ODCB6 Bit 5 TRISB5 RB5 LATB5 ODCB5 Bit 4 TRISB4 RB4 LATB4 — Bit 3 TRISB3 RB3 LATB3 — Bit 2 TRISB2 RB2 LATB2 — Bit 1 TRISB1 RB1 LATB1 — Bit 0 TRISB0 RB0 LATB0 — All Resets FFFF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-30: File Name TRISC PORTC LATC ODCC Legend: Addr 02D0 02D2 02D4 02D6 PORTC REGISTER MAP FOR PIC24HJ128GP204/504, PIC24HJ64GP204/504 AND PIC24HJ32GP304 Bit 15 — — — — Bit 14 — — — — Bit 13 — — — — Bit 12 — — — — Bit 11 — — — — Bit 10 — — — — Bit 9 TRISC9 RC9 LATC9 ODCC9 Bit 8 TRISC8 RC8 LATC8 ODCC8 Bit 7 TRISC7 RC7 LATC7 ODCC7 Bit 6 TRISC6 RC6 LATC6 ODCC6 Bit 5 TRISC5 RC5 LATC5 ODCC5 Bit 4 TRISC4 RC4 LATC4 ODCC4 Bit 3 TRISC3 RC3 LATC3 ODCC3 Bit 2 TRISC2 RC2 LATC2 — Bit 1 TRISC1 RC1 LATC1 — Bit 0 TRISC0 RC0 LATC0 — All Resets 03FF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-31: File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0746 0748 SYSTEM CONTROL REGISTER MAP Bit 15 TRAPR — ROI — — — — Bit 14 IOPUWR Bit 13 — COSC DOZE — — — — Bit 12 — Bit 11 — — DOZEN — — — — Bit 10 — Bit 9 CM NOSC FRCDIV — — — — — Bit 8 VREGS Bit 7 EXTR CLKLOCK Bit 6 SWR IOLOCK Bit 5 SWDTEN LOCK — PLLDIV TUN Bit 4 WDTO — Bit 3 SLEEP CF Bit 2 IDLE — Bit 1 BOR LPOSCEN Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 3040 0030 0000 PLLPOST PLLPRE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-32: File Name BSRAM SSRAM Legend: Note 1: Addr 0750 0752 SECURITY REGISTER MAP(1) Bit 15 — — Bit 14 — — Bit 13 — — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — — Bit 6 — — Bit 5 — — Bit 4 — — Bit 3 — — Bit 2 IW_BSR IW_ SSR Bit 1 IR_BSR IR_SSR Bit 0 RL_BSR RL_SSR All Resets 0000 0000 DS70293E-page 46 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register is not present in devices with 32K Flash (PIC24HJ32GP302/304). TABLE 4-33: File Name NVMCON NVMKEY Legend: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR — Bit 14 WREN — Bit 13 WRERR — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — Bit 6 ERASE Bit 5 — Bit 4 — NVMKEY Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 NVMOP x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-34: File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774 PMD REGISTER MAP Bit 15 T5MD IC8MD — Bit 14 T4MD IC7MD — Bit 13 T3MD — — Bit 12 T2MD — — Bit 11 T1MD — — Bit 10 — — CMPMD Bit 9 — IC2MD RTCCMD Bit 8 — IC1MD PMPMD Bit 7 I2C1MD — CRCMD Bit 6 U2MD — — Bit 5 U1MD — — Bit 4 SPI2MD — — Bit 3 SPI1MD OC4MD — Bit 2 — OC3MD — Bit 1 C1MD OC2MD — Bit 0 AD1MD OC1MD — All Resets 0000 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.2.6 SOFTWARE STACK 4.2.7 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 register in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 4-5. For a PC push during any CALL instruction, the MSb of the PC is zero-extended before the push, ensuring that the MSb is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSb of the PC prior to the push. The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.3 Instruction Addressing Modes The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap does not occur. The stack error trap occurs on a subsequent push operation. For example, to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. The addressing modes shown in Table 4-35 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions differ from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (near data space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The three-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where: Operand 1 is always a working register (that is, the addressing mode can only be register direct), which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: FIGURE 4-5: 0x0000 15 CALL STACK FRAME 0 Stack Grows Toward Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions can support different subsets of these addressing modes. © 2011 Microchip Technology Inc. DS70293E-page 47 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 4-35: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the Effective Address (EA). The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. (Register Indexed) Register Indirect with Literal Offset The sum of Wn and a literal forms the EA. 4.3.3 MOVE (MOV) INSTRUCTION 4.3.4 OTHER INSTRUCTIONS Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, MOV instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared by both source and destination (but typically only used by one). Besides the addressing modes outlined previously, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, such as ADD Acc, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. In summary, the following addressing modes are supported by move instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. DS70293E-page 48 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4 Interfacing Program and Data Memory Spaces 4.4.1 ADDRESSING PROGRAM SPACE The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture uses a 24-bit-wide program space and a 16-bit-wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated periodically. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look-ups from a large table of static data. The application can only access the least significant word of the program word. Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-36 and Figure 4-6 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, and D refers to a data space word. TABLE 4-36: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address 0 TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx 0 0 PSVPAG xxxx xxxx PC 0xx xxxx xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. © 2011 Microchip Technology Inc. DS70293E-page 49 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 4-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits 0 EA Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits 1/0 Select Program Space (Remapping) Visibility(1) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The Least Significant bit (LSb) of program space addresses is always fixed as ‘0’ to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word aligned. Table read operations are permitted in the configuration memory space. DS70293E-page 50 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS - In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. • TBLRDH (Table Read High): - In Word mode, this instruction maps the entire upper word of a program address (P) to a data address. The ‘phantom’ byte (D), is always ‘0’. - In Byte mode, this instruction maps the upper or lower byte of the program word to D of the data address, in the TBLRDL instruction. The data is always ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user application and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16 bit wide word address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space that contains the least significant data word. TBLRDH and TBLWTH access the space that contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. • TBLRDL (Table Read Low): - In Word mode, this instruction maps the lower word of the program space location (P) to a data address (D). FIGURE 4-7: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 02 23 15 0 0x000000 00000000 00000000 23 16 8 0 0x020000 0x030000 00000000 00000000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 © 2011 Microchip Technology Inc. DS70293E-page 51 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access to stored constant data from the data space without the need to use special instructions (such as TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. By incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add a cycle to the instruction being executed, since two program memory fetches are required. Although each data space address 0x8000 and higher maps directly into a corresponding program memory address (see Figure 4-8), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, and are executed inside a REPEAT loop, these instances require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop allows the instruction using PSV to access data, to execute in a single cycle. FIGURE 4-8: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 DS70293E-page 52 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.0 FLASH PROGRAM MEMORY PGEC2/PGED2 or PGEC3/PGED3), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user application can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time or a single program memory word, and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to “Section 5. Flash Programming” (DS70191) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: • In-Circuit Serial Programming™ (ICSP™) programming capability • Run-Time Self-Programming (RTSP) ICSP allows the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices to be serially programmed while in the end application circuit. This is done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGEC1/PGED1, 5.1 Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select © 2011 Microchip Technology Inc. DS70293E-page 53 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.2 RTSP Operation For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN bits (see Register 9-4) are set to ‘b111111, the minimum row write time is equal to Equation 5-2. The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user application to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 28-12 shows typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers sequentially. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. EQUATION 5-2: MINIMUM ROW WRITE TIME 11064 Cycles T RW = ----------------------------------------------------------------------------------------------- = 1.435 ms 7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 ) The maximum row write time is equal to Equation 5-3. EQUATION 5-3: MAXIMUM ROW WRITE TIME 11064 Cycles T RW = ----------------------------------------------------------------------------------------------- = 1.586 ms 7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 ) Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers Two SFRs are used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY (Register 5-2) is a write-only register that is used for write protection. To start a programming or erase sequence, the user application must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. 5.3 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 28-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time, and Word Write Cycle Time parameters (see Table 28-12). EQUATION 5-1: PROGRAMMING TIME T --------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy ) % × ( FRC Tuning ) % DS70293E-page 54 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 5-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) R/W-0(1) R/W-0(1) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) bit 0 NVMOP(2) WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command Unimplemented: Read as ‘0’ NVMOP: NVM Operation Select bits(2) If ERASE = 1: 1111 = Memory bulk erase operation 1110 = Reserved 1101 = Erase General Segment 1100 = Erase Secure Segment 1011 = Reserved 0011 = No operation 0010 = Memory page erase operation 0001 = No operation 0000 = Erase a single Configuration register byte If ERASE = 0: 1111 = No operation 1110 = Reserved 1101 = No operation 1100 = No operation 1011 = Reserved 0011 = Memory word program operation 0010 = No operation 0001 = Memory row program operation 0000 = Program a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: 2: These bits can only be reset on a POR. All other combinations of NVMOP are unimplemented. © 2011 Microchip Technology Inc. DS70293E-page 55 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 5-2: U-0 — bit 15 W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown W-0 W-0 W-0 W-0 W-0 W-0 W-0 bit 0 NVMKEY: NONVOLATILE MEMORY KEY REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 NVMKEY Unimplemented: Read as ‘0’ NVMKEY: Key Register (write-only) bits DS70293E-page 56 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. Programmers can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 5-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Write 0x55 to NVMKEY. d) Write 0xAA to NVMKEY. e) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user application must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority C1 VIN0 = C1 VIN+ < C1 VINWhen C1INV = 1: 0 = C1 VIN+ > C1 VIN1 = C1 VIN+ < C1 VINC2INV: Comparator 2 Output Inversion bit 1 = C2 output inverted 0 = C2 output not inverted C1INV: Comparator 1 Output Inversion bit 1 = C1 output inverted 0 = C1 output not inverted C2NEG: Comparator 2 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the comparator modes. C2POS: Comparator 2 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the comparator modes. C1NEG: Comparator 1 Negative Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to VINSee Figure 21-1 for the comparator modes. C1POS: Comparator 1 Positive Input Configure bit 1 = Input is connected to VIN+ 0 = Input is connected to CVREF See Figure 21-1 for the comparator modes. If C2OUTEN = 1, the C2OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. If C1OUTEN = 1, the C1OUT peripheral output must be configured to an available RPx pin. See Section 11.6 “Peripheral Pin Select” for more information. bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: © 2011 Microchip Technology Inc. DS70293E-page 233 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 21.1 21.1.1 Comparator Voltage Reference CONFIGURING THE COMPARATOR VOLTAGE REFERENCE The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON). The settling time of the comparator voltage reference must be considered when changing the CVREF output. The Voltage Reference module is controlled through the CVRCON register (Register 21-2). The comparator voltage reference provides two ranges of output voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. FIGURE 21-2: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 CVRSRC 8R R R R R 16 Steps CVRCON CVR3 CVR2 CVR1 CVR0 CVRSS = 0 CVREN CVREFIN 16-to-1 MUX CVREF R R R CVROE (CVRCON) CVRR VREFAVSS CVRSS = 1 8R CVRSS = 0 DS70293E-page 234 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 21-2: U-0 — bit 15 R/W-0 CVREN bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CVROE R/W-0 CVRR R/W-0 CVRSS R/W-0 R/W-0 R/W-0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 bit 0 CVR Unimplemented: Read as ‘0’ CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ – VREF0 = Comparator reference source CVRSRC = AVDD – AVSS CVR: Comparator VREF Value Selection 0 ≤ CVR ≤ 15 bits When CVRR = 1: CVREF = (CVR/ 24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC) bit 6 bit 5 bit 4 bit 3-0 © 2011 Microchip Technology Inc. DS70293E-page 235 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 236 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 22.0 REAL-TIME CLOCK AND CALENDAR (RTCC) • Time: hours, minutes and seconds • 24-hour format (military time) • Calendar: weekday, date, month and year • Alarm configurable • Year range: 2000 to 2099 • Leap year correction • BCD format for compact firmware • Optimized for low-power operation • User calibration with auto-adjust • Calibration range: ±2.64 seconds error per month • Requirements: External 32.768 kHz clock crystal • Alarm pulse or seconds clock output on RTCC pin The RTCC module is intended for applications where accurate time must be maintained for extended periods of time with minimum to no intervention from the CPU. The RTCC module is optimized for low-power usage to provide extended battery lifetime while keeping track of time. The RTCC module is a 100-year clock and calendar with automatic leap year detection. The range of the clock is from 00:00:00 (midnight) on January 1, 2000 to 23:59:59 on December 31, 2099. The hours are available in 24-hour (military time) format. The clock provides a granularity of one second with half-second visibility to the user. Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. “Real-Time Clock and Calendar (RTCC)” (DS70301) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This chapter discusses the Real-Time Clock and Calendar (RTCC) module, available on PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices, and its operation. The following are some of the key features of this module: FIGURE 22-1: RTCC BLOCK DIAGRAM RTCC Clock Domain CPU Clock Domain RCFGCAL RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL ALCFGRPT 32.768 kHz Input from SOSC Oscillator Comparator Compare Registers with Masks Repeat Counter ALRMVAL RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE © 2011 Microchip Technology Inc. DS70293E-page 237 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 22.1 RTCC Module Registers By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. The RTCC module registers are organized into three categories: • RTCC Control Registers • RTCC Value Registers • Alarm Value Registers TABLE 22-2: ALRMPTR 00 01 10 11 22.1.1 REGISTER MAPPING ALRMVAL REGISTER MAPPING Alarm Value Register Window ALRMVAL ALRMVAL ALRMMIN ALRMWD ALRMMNTH — ALRMSEC ALRMHR ALRMDAY — To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL) to select the desired timer register pair (see Table 22-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR bits, decrement by one until they reach ‘00’. Once they reach ‘00’, the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. TABLE 22-1: RTCPTR 00 01 10 11 RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL MINUTES WEEKDAY MONTH — RTCVAL SECONDS HOURS DAY YEAR Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR being decremented. Note: This only applies to read operations and not write operations. 22.1.2 WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL) must be set (refer to Example 22-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the 55h/AA sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 22-1. The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT) to select the desired Alarm register pair (see Table 22-2). EXAMPLE 22-1: MOV MOV MOV MOV MOV BSET SETTING THE RTCWREN BIT ;move the address of NVMKEY into W1 #NVMKEY, W1 #0x55, W2 #0xAA, W3 W2, [W1] W3, [W1] RCFGCAL, #13 ;start 55/AA sequence ;set the RTCWREN bit DS70293E-page 238 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-1: R/W-0 RTCEN(2) bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) U-0 — R/W-0 RTCWREN R-0 RTCSYNC R-0 HALFSEC(3) R/W-0 RTCOE R/W-0 R/W-0 bit 8 R/W-0 bit 0 RTCPTR CAL RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as ‘0’ RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled RTCPTR: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR value decrements on every read or write of RTCVALH until it reaches ‘00’. RTCVAL: 11 = Reserved 10 = MONTH 01 = WEEKDAY 00 = MINUTES RTCVAL: 11 = YEAR 10 = DAY 01 = HOURS 00 = SECONDS The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 Note 1: 2: 3: © 2011 Microchip Technology Inc. DS70293E-page 239 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-1: bit 7-0 RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL: RTC Drift Calibration bits 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute • • • 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute • • • 00000001 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to ‘0’ on a write to the lower half of the MINSEC register. Note 1: 2: 3: DS70293E-page 240 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 RTSECSEL (1) PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PMPTTL bit 0 Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE bit (RCFGCAL) needs to be set. bit 0 Note 1: © 2011 Microchip Technology Inc. DS70293E-page 241 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-3: R/W-0 ALRMEN bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 CHIME R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 AMASK ALRMPTR ARPT ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT = 0x00 and CHIME = 0) 0 = Alarm is disabled CHIME: Chime Enable bit 1 = Chime is enabled; ARPT bits are allowed to roll over from 0x00 to 0xFF 0 = Chime is disabled; ARPT bits stop once they reach 0x00 AMASK: Alarm Mask Configuration bits 11xx = Reserved – do not use 101x = Reserved – do not use 1001 = Once a year (except when configured for February 29th, once every 4 years) 1000 = Once a month 0111 = Once a week 0110 = Once a day 0101 = Every hour 0100 = Every 10 minutes 0011 = Every minute 0010 = Every 10 seconds 0001 = Every second 0000 = Every half second ALRMPTR: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR value decrements on every read or write of ALRMVALH until it reaches ‘00’. ALRMVAL: 11 = Unimplemented 10 = ALRMMNTH 01 = ALRMWD 00 = ALRMMIN ALRMVAL: 11 = Unimplemented 10 = ALRMDAY 01 = ALRMHR 00 = ALRMSEC ARPT: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times • • • 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 0x00 to 0xFF unless CHIME = 1. bit 14 bit 13-10 bit 9-8 bit 7-0 DS70293E-page 242 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-4: U-0 — bit 15 R/W-x bit 7 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-4 bit 3-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x RTCVAL (WHEN RTCPTR = 11): YEAR VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-x bit 0 YRTEN YRONE Unimplemented: Read as ‘0’ YRTEN: Binary Coded Decimal Value of Year’s Tens Digit; contains a value from 0 to 9 YRONE: Binary Coded Decimal Value of Year’s Ones Digit; contains a value from 0 to 9 A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 22-5: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1: RTCVAL (WHEN RTCPTR = 10): MONTH AND DAY VALUE REGISTER(1) U-0 — U-0 — R-x MTHTEN0 R-x R-x R-x R-x bit 8 U-0 — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 0 MTHONE DAYTEN DAYONE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1. © 2011 Microchip Technology Inc. DS70293E-page 243 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x R/W-x R/W-x R/W-x R/W-x RTCVAL (WHEN RTCPTR = 01): WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — R/W-x R/W-x WDAY bit 8 R/W-x bit 0 R/W-x HRTEN HRONE Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1. REGISTER 22-7: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 RTCVAL (WHEN RTCPTR = 00): MINUTES AND SECONDS VALUE REGISTER R/W-x R/W-x MINTEN R/W-x R/W-x R/W-x R/W-x R/W-x bit 8 R/W-x R/W-x SECTEN R/W-x R/W-x R/W-x R/W-x R/W-x bit 0 MINONE SECONE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 SECONE: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 DS70293E-page 244 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-8: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-13 bit 12 bit 11-8 bit 7-6 bit 5-4 bit 3-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — R/W-x R/W-x R/W-x R/W-x R/W-x ALRMVAL (WHEN ALRMPTR = 10): ALARM MONTH AND DAY VALUE REGISTER(1) U-0 — U-0 — R/W-x MTHTEN0 R/W-x R/W-x R/W-x R/W-x bit 8 R/W-x bit 0 MTHONE DAYTEN DAYONE Unimplemented: Read as ‘0’ MTHTEN0: Binary Coded Decimal Value of Month’s Tens Digit; contains a value of 0 or 1 MTHONE: Binary Coded Decimal Value of Month’s Ones Digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ DAYTEN: Binary Coded Decimal Value of Day’s Tens Digit; contains a value from 0 to 3 DAYONE: Binary Coded Decimal Value of Day’s Ones Digit; contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1. REGISTER 22-9: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-11 bit 10-8 bit 7-6 bit 5-4 bit 3-0 Note 1: ALRMVAL (WHEN ALRMPTR = 01): ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 — U-0 — U-0 — U-0 — R/W-x WDAY2 R/W-x WDAY1 R/W-x WDAY0 bit 8 U-0 — R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x bit 0 HRTEN HRONE W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ WDAY: Binary Coded Decimal Value of Weekday Digit; contains a value from 0 to 6 Unimplemented: Read as ‘0’ HRTEN: Binary Coded Decimal Value of Hour’s Tens Digit; contains a value from 0 to 2 HRONE: Binary Coded Decimal Value of Hour’s Ones Digit; contains a value from 0 to 9 A write to this register is only allowed when RTCWREN = 1. © 2011 Microchip Technology Inc. DS70293E-page 245 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 22-10: ALRMVAL (WHEN ALRMPTR = 00): ALARM MINUTES AND SECONDS VALUE REGISTER U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14-12 bit 11-8 bit 7 bit 6-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-x R/W-x SECTEN R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x MINTEN R/W-x R/W-x R/W-x R/W-x R/W-x bit 8 R/W-x bit 0 MINONE SECONE Unimplemented: Read as ‘0’ MINTEN: Binary Coded Decimal Value of Minute’s Tens Digit; contains a value from 0 to 5 MINONE: Binary Coded Decimal Value of Minute’s Ones Digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ SECTEN: Binary Coded Decimal Value of Second’s Tens Digit; contains a value from 0 to 5 SECONE: Binary Coded Decimal Value of Second’s Ones Digit; contains a value from 0 to 9 DS70293E-page 246 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 23.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR 23.1 Overview Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 36. “Programmable Cyclic Redundancy Check (CRC)” (DS70298) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The programmable CRC generator offers the following features: • User-programmable polynomial CRC equation • Interrupt output • Data FIFO The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the CRCXOR bits (X) and the CRCCON bits (PLEN), respectively. EQUATION 23-1: x 16 CRC EQUATION +x 12 5 +x +1 To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 23-1. TABLE 23-1: Bit Name PLEN X EXAMPLE CRC SETUP Bit Value 1111 000100000010000 For the value of X, the 12th bit and the 5th bit are set to ‘1’, as required by the CRC equation. The 0th bit required by the CRC equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X bits do not have the 0th bit or the 16th bit. The topology of a standard CRC generator is shown in Figure 23-2. FIGURE 23-1: CRC SHIFTER DETAILS PLEN 0 1 2 15 CRC Shift Register Hold XOR DOUT X1 0 Hold X2 0 Hold X3 0 X15 0 Hold OUT IN BIT 0 OUT IN BIT 1 OUT IN BIT 2 OUT IN BIT 15 1 1 1 1 p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus © 2011 Microchip Technology Inc. DS70293E-page 247 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 23-2: XOR D SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 Q D Q D Q D Q D Q CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 23.2 23.2.1 User Interface DATA INTERFACE To empty words already written into a FIFO, the CRCGO bit must be set to ‘1’ and the CRC shifter allowed to run until the CRCMPT bit is set. Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 23.2.2 “Interrupt Operation”). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. To start serial shifting, a ‘1’ must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when PLEN (PLEN) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = ‘bxx Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of VWORD (VWORD) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially “prime” the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to ‘1’. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. 23.2.2 INTERRUPT OPERATION When the VWORD bits make a transition from a value of ‘1’ to ‘0’, an interrupt will be generated. 23.3 23.3.1 Operation in Power-Saving Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 23.3.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. DS70293E-page 248 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 23.4 Registers The CRC module provides the following registers: • CRC Control Register • CRC XOR Polynomial Register REGISTER 23-1: U-0 — bit 15 R-0 CRCFUL bit 7 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 CRCCON: CRC CONTROL REGISTER U-0 — R/W-0 CSIDL R-0 R-0 R-0 VWORD bit 8 R-1 U-0 — R/W-0 CRCGO R/W-0 R/W-0 R/W-0 R/W-0 bit 0 R-0 R-0 CRCMPT PLEN W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode VWORD: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN is greater than 7, or 16 when PLEN is less than or equal to 7. CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty Unimplemented: Read as ‘0’ CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = Turn off CRC serial shifter after FIFO is empty PLEN: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. bit 12-8 bit 7 bit 6 bit 5 bit 4 bit 3-0 © 2011 Microchip Technology Inc. DS70293E-page 249 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 23-2: R/W-0 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15-1 bit 0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 X R/W-0 R/W-0 R/W-0 U-0 — bit 0 CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 X X: XOR of Polynomial Term Xn Enable bits Unimplemented: Read as ‘0’ DS70293E-page 250 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 24.0 PARALLEL MASTER PORT (PMP) devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. Key features of the PMP module include: • Fully Multiplexed Address/Data Mode • Demultiplexed or Partially Multiplexed Address/ Data Mode: - Up to 11 address lines with single Chip Select - Up to 12 address lines without Chip Select • Single Chip Select Line • Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 35. “Parallel Master Port (PMP)” (DS70299) of the “dsPIC33F/PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory FIGURE 24-1: PMP MODULE OVERVIEW Address Bus Data Bus PIC24H Parallel Master Port PMA PMALL PMA PMALH Control Lines Up to 11-Bit Address EEPROM PMA(1) PMA PMCS1 PMBE PMRD PMRD/PMWR PMWR PMENB Microcontroller LCD FIFO Buffer PMD PMA PMA 8-Bit Data Note 1: 28-pin devices do not have PMA. © 2011 Microchip Technology Inc. DS70293E-page 251 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 24-1: R/W-0 PMPEN bit 15 R/W-0 CSF1 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 CSF0 R/W-0(1) ALP U-0 — R/W-0(1) CS1P R/W-0 BEP R/W-0 WRSP PMCON: PARALLEL PORT CONTROL REGISTER U-0 — R/W-0 PSIDL R/W-0 ADRMUX1 R/W-0 ADRMUX0 R/W-0 PTBEEN R/W-0 PTWREN R/W-0 PTRDEN bit 8 R/W-0 RDSP bit 0 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as ‘0’ PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins, upper 3 bits are multiplexed on PMA 00 = Address and data appear on separate pins PTBEEN: Byte Enable Port Enable bit (16-bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip select 0x = PMCS1 functions as address bit 14 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) Unimplemented: Read as ‘0’ CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) These bits have no effect when their corresponding pins are used as address lines. bit 14 bit 13 bit 12-11 bit 10 bit 9 bit 8 bit 7-6 bit 5 bit 4 bit 3 bit 2 Note 1: DS70293E-page 252 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 24-1: bit 1 PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) These bits have no effect when their corresponding pins are used as address lines. bit 0 Note 1: © 2011 Microchip Technology Inc. DS70293E-page 253 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 Register 24-2: R-0 BUSY bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMMODE: PARALLEL PORT MODE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 MODE16 R/W-0 R/W-0 bit 8 R/W-0 bit 0 IRQM INCM MODE WAITB(1) WAITM WAITE(1) BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy IRQM: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated INCM: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR by 1 every read/write cycle 01 = Increment ADDR by 1 every read/write cycle 00 = No increment or decrement of address MODE16: 8/16-bit Mode bit 1 = 16-bit mode: data register is 16 bits, a read or write to the data register invokes two 8-bit transfers 0 = 8-bit mode: data register is 8 bits, a read or write to the data register invokes one 8-bit transfer MODE: Parallel Port Mode Select bits 11 =Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA and PMD) 10 =Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA and PMD) 01 =Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD and PMA) 00 =Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD) WAITB: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY WAITM: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY • • • 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY) WAITE: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. bit 14-13 bit 12-11 bit 10 bit 9-8 bit 7-6 bit 5-2 bit 1-0 Note 1: DS70293E-page 254 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 24-3: R/W-0 ADDR15 bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 8 R/W-0 bit 0 ADDR ADDR ADDR15: Parallel Port Destination Address bits CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive ADDR13:ADDR0: Parallel Port Destination Address bits bit 13-0 REGISTER 24-4: U-0 — bit 15 R/W-0 bit 7 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 PMAEN: PARALLEL PORT ENABLE REGISTER R/W-0 U-0 — U-0 — U-0 — R/W-0 R/W-0 PTEN(1) bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 bit 0 R/W-0 PTEN14 PTEN(1) PTEN W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ PTEN14: PMCS1 Strobe Enable bit 1 = PMA14 functions as either PMA bit or PMCS1 0 = PMA14 pin functions as port I/O Unimplemented: Read as ‘0’ PTEN: PMP Address Port Enable bits(1) 1 = PMA function as PMP address lines 0 = PMA function as port I/O PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O Devices with 28 pins do not have PMA. bit 13-11 bit 10-2 bit 1-0 Note 1: © 2011 Microchip Technology Inc. DS70293E-page 255 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 24-5: R-0 IBF bit 15 R-1 OBE bit 7 Legend: R = Readable bit -n = Value at POR bit 15 HS = Hardware Set bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0, HS OBUF U-0 — U-0 — R-1 OB3E R-1 OB2E R-1 OB1E R-1 OB0E bit 0 PMSTAT: PARALLEL PORT STATUS REGISTER U-0 — U-0 — R-0 IB3F R-0 IB2F R-0 IB1F R-0 IB0F bit 8 R/W-0, HS IBOV IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred Unimplemented: Read as ‘0’ IB3F:IB0F Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OB3E:OB0E Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted bit 14 bit 13-12 bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 DS70293E-page 256 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 REGISTER 24-6: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15-2 bit 1 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 RTSECSEL (1) PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0 PMPTTL bit 0 Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffers To enable the actual RTCC output, the RTCOE bit (RCFGCAL) needs to be set. bit 0 Note 1: © 2011 Microchip Technology Inc. DS70293E-page 257 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 258 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 25.0 SPECIAL FEATURES 25.1 Configuration Bits Note 1: This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices include the following features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components: • • • • • • Flexible configuration Watchdog Timer (WDT) Code Protection and CodeGuard™ Security JTAG Boundary Scan Interface In-Circuit Serial Programming™ (ICSP™) In-Circuit Emulation The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices provide nonvolatile memory implementation for device configuration bits. Refer to Section 25. “Device Configuration” (DS70194), in the “dsPIC33F/PIC24H Family Reference Manual” for more information on this implementation. The Configuration bits can be programmed (read as ‘0’), or left unprogrammed (read as ‘1’), to select various device configurations. These bits are mapped starting at program memory location 0xF80000. The individual Configuration bit descriptions for the Configuration registers are shown in Table 25-1. Note that address 0xF80000 is beyond the user program memory space. It belongs to the configuration memory space (0x800000-0xFFFFFF), which can only be accessed using table reads and table writes. The Device Configuration register map is shown in Table 25-1. TABLE 25-1: Address 0xF80000 FBS DEVICE CONFIGURATION REGISTER MAP Name Bit 7 Bit 6 Bit 5 — — — — IOL1WAY — JTAGEN — WDTPRE ALTI2C — — — — Bit 4 — — — — — — Bit 3 Bit 2 BSS SSS GSS FNOSC OSCIOFNC POSCMD WDTPOST FPWRT ICS Bit 1 Bit 0 BWRP SWRP GWRP RBS RSS — IESO — — 0xF80002 FSS(1) 0xF80004 FGS 0xF80006 FOSCSEL 0xF80008 FOSC 0xF8000A FWDT 0xF8000C FPOR 0xF8000E FICD 0xF80010 FUID0 0xF80012 FUID1 0xF80014 FUID2 0xF80016 FUID3 Legend: Note 1: 2: 3: FCKSM FWDTEN WINDIS Reserved(2) Reserved(3) User Unit ID Byte 0 User Unit ID Byte 1 User Unit ID Byte 2 User Unit ID Byte 3 — = unimplemented bit, read as ‘0’. This Configuration register is not available and reads as 0xFF on PIC24HJ32GP302/304 devices. These bits are reserved and always read as ‘1’. These bits are reserved for use by development tools and must be programmed as ‘1’. © 2011 Microchip Technology Inc. DS70293E-page 259 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 25-2: Bit Field BWRP PIC24H CONFIGURATION BITS DESCRIPTION Register FBS RTSP Effect Immediate Description Boot Segment Program Flash Write Protection 1 = Boot segment can be written 0 = Boot segment is write-protected Boot Segment Program Flash Code Protection Size X11 = No Boot program Flash segment Boot space is 1K Instruction Words (except interrupt vectors) 110 = Standard security; boot program Flash segment ends at 0x0007FE 010 = High security; boot program Flash segment ends at 0x0007FE Boot space is 4K Instruction Words (except interrupt vectors) 101 = Standard security; boot program Flash segment, ends at 0x001FFE 001 = High security; boot program Flash segment ends at 0x001FFE Boot space is 8K Instruction Words (except interrupt vectors) 100 = Standard security; boot program Flash segment ends at 0x003FFE 000 = High security; boot program Flash segment ends at 0x003FFE BSS FBS Immediate RBS(1) FBS Immediate Boot Segment RAM Code Protection Size 11 = No Boot RAM defined 10 = Boot RAM is 128 bytes 01 = Boot RAM is 256 bytes 00 = Boot RAM is 1024 bytes Secure Segment Program Flash Write-Protect bit 1 = Secure Segment can bet written 0 = Secure Segment is write-protected Secure Segment Program Flash Code Protection Size (Secure segment is not implemented on 32K devices) X11 = No Secure program flash segment Secure space is 4K IW less BS 110 = Standard security; secure program flash segment starts at End of BS, ends at 0x001FFE 010 = High security; secure program flash segment starts at End of BS, ends at 0x001FFE Secure space is 8K IW less BS 101 = Standard security; secure program flash segment starts at End of BS, ends at 0x003FFE 001 = High security; secure program flash segment starts at End of BS, ends at 0x003FFE Secure space is 16K IW less BS 100 = Standard security; secure program flash segment starts at End of BS, ends at 007FFEh 000 = High security; secure program flash segment starts at End of BS, ends at 0x007FFE SWRP(1) FSS(1) Immediate SSS(1) FSS(1) Immediate Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices. DS70293E-page 260 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 25-2: Bit Field RSS(1) PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FSS(1) RTSP Effect Immediate Description Secure Segment RAM Code Protection 11 = No Secure RAM defined 10 = Secure RAM is 256 Bytes less BS RAM 01 = Secure RAM is 2048 Bytes less BS RAM 00 = Secure RAM is 4096 Bytes less BS RAM General Segment Code-Protect bit 11 = User program memory is not code-protected 10 = Standard security 0x = High security General Segment Write-Protect bit 1 = User program memory is not write-protected 0 = User program memory is write-protected Two-speed Oscillator Start-up Enable bit 1 = Start-up device with FRC, then automatically switch to the user-selected oscillator source when ready 0 = Start-up device with user-selected oscillator source Initial Oscillator Source Selection bits 111 = Internal Fast RC (FRC) oscillator with postscaler 110 = Internal Fast RC (FRC) oscillator with divide-by-16 101 = LPRC oscillator 100 = Secondary (LP) oscillator 011 = Primary (XT, HS, EC) oscillator with PLL 010 = Primary (XT, HS, EC) oscillator 001 = Internal Fast RC (FRC) oscillator with PLL 000 = FRC oscillator Clock Switching Mode bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled Peripheral pin select configuration 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations OSC2 Pin Function bit (except in XT and HS modes) 1 = OSC2 is clock output 0 = OSC2 is general purpose digital I/O pin Primary Oscillator Mode Select bits 11 = Primary oscillator disabled 10 = HS Crystal Oscillator mode 01 = XT Crystal Oscillator mode 00 = EC (External Clock) mode Watchdog Timer Enable bit 1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled. Clearing the SWDTEN bit in the RCON register has no effect.) 0 = Watchdog Timer enabled/disabled by user software (LPRC can be disabled by clearing the SWDTEN bit in the RCON register) Watchdog Timer Window Enable bit 1 = Watchdog Timer in Non-Window mode 0 = Watchdog Timer in Window mode GSS FGS Immediate GWRP FGS Immediate IESO FOSCSEL Immediate FNOSC FOSCSEL If clock switch is enabled, RTSP effect is on any device Reset; otherwise, Immediate FCKSM FOSC Immediate IOL1WAY FOSC Immediate OSCIOFNC FOSC Immediate POSCMD FOSC Immediate FWDTEN FWDT Immediate WINDIS FWDT Immediate Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices. © 2011 Microchip Technology Inc. DS70293E-page 261 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 25-2: Bit Field WDTPRE PIC24H CONFIGURATION BITS DESCRIPTION (CONTINUED) Register FWDT RTSP Effect Immediate Description Watchdog Timer Prescaler bit 1 = 1:128 0 = 1:32 Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use WDTPOST FWDT Immediate FPWRT FPOR Immediate ALTI2C FPOR Immediate JTAGEN FICD Immediate ICS FICD Immediate Note 1: This Configuration register is not available on PIC24HJ32GP302/304 devices. DS70293E-page 262 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 25.2 On-Chip Voltage Regulator 25.3 Brown-out Reset (BOR) All of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices power their core digital logic at a nominal 2.5V. This can create a conflict for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. The regulator provides power to the core from the other VDD pins. When the regulator is enabled, a low-ESR (less than 5 Ohms) capacitor (such as tantalum or ceramic) must be connected to the VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Table 28-13 located in Section 28.1 “DC Characteristics”. Note: It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. The Brown-out Reset (BOR) module is based on an internal voltage reference circuit that monitors the regulated supply voltage VCAP. The main purpose of the BOR module is to generate a device Reset when a brown-out condition occurs. Brown-out conditions are generally caused by glitches on the AC mains (for example, missing portions of the AC cycle waveform due to bad power transmission lines, or voltage sags due to excessive current draw when a large inductive load is turned on). A BOR generates a Reset pulse, which resets the device. The BOR selects the clock source, based on the device Configuration bit values (FNOSC and POSCMD). If an oscillator mode is selected, the BOR activates the Oscillator Start-up Timer (OST). The system clock is held until OST expires. If the PLL is used, the clock is held until the LOCK bit (OSCCON) is ‘1’. Concurrently, the PWRT time-out (TPWRT) is applied before the internal Reset is released. If TPWRT = 0 and a crystal oscillator is being used, then a nominal delay of TFSCM = 100 is applied. The total delay in this case is TFSCM. The BOR Status bit (RCON) is set to indicate that a BOR has occurred. The BOR circuit continues to operate while in Sleep or Idle modes and resets the device should VDD fall below the BOR threshold voltage. On a POR, it takes approximately 20 μs for the on-chip voltage regulator to generate an output voltage. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down. FIGURE 25-1: CONNECTIONS FOR THE ON-CHIP VOLTAGE REGULATOR(1) 3.3V PIC24H VDD VCAP CEFC 10 µF Tantalum VSS Note 1: These are typical operating voltages. Refer to Table 28-13, located in Section 28.1 “DC Characteristics” for the full operating ranges of VDD and VCAP. It is important for the low-ESR capacitor to be placed as close as possible to the VCAP pin. 2: © 2011 Microchip Technology Inc. DS70293E-page 263 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 25.4 Watchdog Timer (WDT) 25.4.2 SLEEP AND IDLE MODES For PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. 25.4.1 PRESCALER/POSTSCALER If the WDT is enabled, it continues to run during Sleep or Idle modes. When the WDT time-out occurs, the device wakes the device and code execution continues from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON) needs to be cleared in software after the device wakes up. The nominal WDT clock source from LPRC is 32 kHz. This feeds a prescaler than can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the WDTPRE Configuration bit. With a 32 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPOST Configuration bits (FWDT), which allow the selection of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: • On any device Reset • On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits) or by hardware (i.e., Fail-Safe Clock Monitor) • When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) • When the device exits Sleep or Idle mode to resume normal operation • By a CLRWDT instruction during normal execution Note: The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. 25.4.3 ENABLING WDT The WDT is enabled or disabled by the FWDTEN Configuration bit in the FWDT Configuration register. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to ‘0’. The WDT is enabled in software by setting the SWDTEN control bit (RCON). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user application to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. Note: If the WINDIS bit (FWDT) is cleared, the CLRWDT instruction should be executed by the application software only during the last 1/4 of the WDT period. This CLRWDT window can be determined by using a timer. If a CLRWDT instruction is executed before this window, a WDT Reset occurs. The WDT flag bit, WDTO (RCON), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. FIGURE 25-2: WDT BLOCK DIAGRAM All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode PWRSAV Instruction CLRWDT Instruction Watchdog Timer Sleep/Idle WDTPRE WDTPOST WDT Wake-up RS Prescaler (divide by N1) RS 1 WDT Reset Postscaler (divide by N2) 0 SWDTEN FWDTEN LPRC Clock WINDIS WDT Window Select CLRWDT Instruction DS70293E-page 264 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 25.5 JTAG Interface 25.8 Code Protection and CodeGuard™ Security PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices implement a JTAG interface, which supports boundary scan device testing, as well as in-circuit programming. Detailed information on this interface is provided in future revisions of the document. Note: Refer to Section 24. “Programming and Diagnostics” (DS70246) of the “dsPIC33F/PIC24H Family Reference Manual” for further information on usage, configuration and operation of the JTAG interface. The PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices offer advanced implementation of CodeGuard Security that supports BS, SS and GS while, the PIC24HJ32GP302/304 devices offer the intermediate level of CodeGuard Security that supports only BS and GS. CodeGuard Security enables multiple parties to securely share resources (memory, interrupts and peripherals) on a single chip. This feature helps protect individual Intellectual Property in collaborative system designs. When coupled with software encryption libraries, CodeGuard Security can be used to securely update Flash even when multiple IPs reside on the single chip. The code protection features vary depending on the actual PIC24H implemented. The following sections provide an overview of these features. Secure segment and RAM protection is implemented on the PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices. The PIC24HJ32GP302/304 devices do not support secure segment and RAM protection. Note: Refer to Section 23. “CodeGuard™ Security” (DS70239) of the “dsPIC33F/PIC24H Family Reference Manual” for further information on usage, configuration and operation of CodeGuard Security. 25.6 In-Circuit Serial Programming The PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 devices can be serially programmed while in the end application circuit. This is done with two lines for clock and data and three other lines for power, ground and the programming sequence. Serial programming allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. Serial programming also allows the most recent firmware or a custom firmware to be programmed. Refer to the “dsPIC33F/PIC24H Flash Programming Specification” (DS70152) for details about In-Circuit Serial Programming (ICSP). Any of the three pairs of programming clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 25.7 In-Circuit Debugger When MPLAB® ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pin functions. Any of the three pairs of debugging clock/data pins can be used: • PGEC1 and PGED1 • PGEC2 and PGED2 • PGEC3 and PGED3 To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS, and the PGECx/PGEDx pin pair. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. © 2011 Microchip Technology Inc. DS70293E-page 265 TABLE 25-3: CODE FLASH SECURITY SEGMENT SIZES FOR 32 KB DEVICES BSS = x11 0K VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x10 1K VS = 256 IW BS = 768 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x01 4K VS = 256 IW BS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh BSS = x00 8K VS = 256 IW BS = 7936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x0057FEh 0x0157FEh DS70293E-page 266 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 CONFIG BITS SSS = x11 0K GS = 11008 IW GS = 10240 IW GS = 7168 IW GS = 3072 IW TABLE 25-4: CONFIG BITS CODE FLASH SECURITY SEGMENT SIZES FOR 64 KB DEVICES BSS = x11 0K VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW SS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 768 IW VS = 256 IW BS = 768 IW SS = 7168 IW GS = 13824 IW VS = 256 IW BS = 768 IW SS = 3072 IW BSS = x10 1K VS = 256 IW BS = 768 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 3840 IW VS = 256 IW BS = 3840 IW SS = 4096 IW GS = 13824 IW VS = 256 IW BS = 3840 IW BSS = x01 4K VS = 256 IW BS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW BS = 7936 IW VS = 256 IW BS = 7936 IW VS = 256 IW BS = 7936 IW BSS = x00 8K VS = 256 IW BS = 7936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh © 2011 Microchip Technology Inc. DS70293E-page 267 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 SSS = x11 0K GS = 21760 IW GS = 20992 IW GS = 17920 IW GS = 13824 IW SSS = x10 4K GS = 17920 IW GS = 17920 IW GS = 17920 IW GS = 13824 IW SSS = x01 8K SS = 7936 IW GS = 13824 IW GS = 13824 IW SSS = x00 16K SS = 16128 IW GS = 5632 IW SS = 15360 IW GS = 5632 IW SS = 12288 IW GS = 5632 IW SS = 8192 IW GS = 5632 IW TABLE 25-5: CONFIG BITS CODE FLASH SECURITY SEGMENT SIZES FOR 128 KB DEVICES BSS = x11 0K VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW SS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 768 IW VS = 256 IW BS = 768 IW SS = 7168 IW VS = 256 IW BS = 768 IW SS = 3072 IW BSS = x10 1K VS = 256 IW BS = 768 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 3840 IW VS = 256 IW BS = 3840 IW SS = 4096 IW VS = 256 IW BS = 3840 IW BSS = x01 4K VS = 256 IW BS = 3840 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh VS = 256 IW BS = 7936 IW VS = 256 IW BS = 7936 IW VS = 256 IW BS = 7936 IW BSS = x00 8K VS = 256 IW BS = 7936 IW 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00ABFEh 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh 0x000000h 0x0001FEh 0x000200h 0x0007FEh 0x000800h 0x001FFEh 0x002000h 0x003FFEh 0x004000h 0x007FFEh 0x008000h 0x00FFFEh 0x010000h 0x0157FEh DS70293E-page 268 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 SSS = x11 0K GS = 43776 IW GS = 43008 IW GS = 39936 IW GS = 35840 IW SSS = x10 4K GS = 39936 IW GS = 39936 IW GS = 39936 IW GS = 35840 IW SSS = x01 8K SS = 7936 IW GS = 35840 IW GS = 35840 IW GS = 35840 IW GS = 35840 IW SSS = x00 16K SS = 16128 IW GS = 27648 IW SS = 15360 IW GS = 27648 IW SS = 12288 IW GS = 27648 IW SS = 8192 IW GS = 27648 IW PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 26.0 Note: INSTRUCTION SET SUMMARY This data sheet summarizes the features of the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 families of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip web site (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual sections. Most bit-oriented instructions (including simple rotate/shift instructions) have two operands: • The W register (with or without an address modifier) or file register (specified by the value of ‘Ws’ or ‘f’) • The bit in the W register or file register (specified by a literal value or indirectly by the contents of register ‘Wb’) The literal instructions that involve data movement may use some of the following operands: • A literal value to be loaded into a W register or file register (specified by the value of ‘k’) • The W register or file register where the literal value is to be loaded (specified by ‘Wb’ or ‘f’) However, literal instructions that involve arithmetic or logical operations use some of the following operands: • The first source operand which is a register ‘Wb’ without any address modifier • The second source operand which is a literal value • The destination of the result (only if not the same as the first source operand) which is typically a register ‘Wd’ with or without an address modifier The control instructions may use some of the following operands: • A program memory address • The mode of the table read and table write instructions All instructions are a single word, except for certain double word instructions, which were made double word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are ‘0’s. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true, or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or double word instruction. Moreover, double word moves require two cycles. The double word instructions execute in two instruction cycles. Note: For more details on the instruction set, refer to the “16-bit MCU and DSC Programmer’s Reference Manual” (DS70157). The PIC24H instruction set is identical to that of the PIC24F, and is a subset of the dsPIC30F/33F instruction set. Most instructions are a single program memory word (24 bits). Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word, divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into five basic categories: • • • • Word or byte-oriented operations Bit-oriented operations Literal operations Control operations Table 26-1 shows the general symbols used in describing the instructions. The PIC24H instruction set summary in Table 26-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: • The first source operand which is typically a register ‘Wb’ without any address modifier • The second source operand which is typically a register ‘Ws’ with or without an address modifier • The destination of the result which is typically a register ‘Wd’ with or without an address modifier However, word or byte-oriented file register instructions have two operands: • The file register specified by the value ‘f’ • The destination, which could either be the file register ‘f’ or the W0 register, which is denoted as ‘WREG’ © 2011 Microchip Technology Inc. DS70293E-page 269 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-1: Field #text (text) [text] {} .b .d .S .w bit4 C, DC, N, OV, Z Expr f lit1 lit4 lit5 lit8 lit10 lit14 lit16 lit23 None PC Slit10 Slit16 Slit6 Wb Wd Wdo Wm,Wn Wm*Wm Wn Wnd Wns WREG Ws Wso Means literal defined by “text” Means “content of text” Means “the location addressed by text” Optional field or operation Register bit field Byte mode selection Double Word mode selection Shadow register select Word mode selection (default) 4-bit bit selection field (used in word addressed instructions) ∈ {0...15} MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Absolute address, label or expression (resolved by the linker) File register address ∈ {0x0000...0x1FFF} 1-bit unsigned literal ∈ {0,1} 4-bit unsigned literal ∈ {0...15} 5-bit unsigned literal ∈ {0...31} 8-bit unsigned literal ∈ {0...255} 10-bit unsigned literal ∈ {0...255} for Byte mode, {0:1023} for Word mode 14-bit unsigned literal ∈ {0...16384} 16-bit unsigned literal ∈ {0...65535} 23-bit unsigned literal ∈ {0...8388608}; LSB must be ‘0’ Field does not require an entry, may be blank Program Counter 10-bit signed literal ∈ {-512...511} 16-bit signed literal ∈ {-32768...32767} 6-bit signed literal ∈ {-16...16} Base W register ∈ {W0..W15} Destination W register ∈ { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Destination W register ∈ { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Dividend, Divisor working register pair (direct addressing) Multiplicand and Multiplier working register pair for Square instructions ∈ {W4 * W4,W5 * W5,W6 * W6,W7 * W7} One of 16 working registers ∈ {W0..W15} One of 16 destination working registers ∈ {W0...W15} One of 16 source working registers ∈ {W0...W15} W0 (working register used in file register instructions) Source W register ∈ { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Source W register ∈ { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } SYMBOLS USED IN OPCODE DESCRIPTIONS Description DS70293E-page 270 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-2: Base Instr # 1 Assembly Mnemonic ADD INSTRUCTION SET OVERVIEW Assembly Syntax ADD ADD ADD ADD ADD f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,#bit4 Ws,#bit4 C,Expr GE,Expr GEU,Expr GT,Expr GTU,Expr LE,Expr LEU,Expr LT,Expr LTU,Expr N,Expr NC,Expr NN,Expr NZ,Expr Expr Z,Expr Wn f,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 f,#bit4 Ws,#bit4 f = f + WREG WREG = f + WREG Wd = lit10 + Wd Wd = Wb + Ws Wd = Wb + lit5 f = f + WREG + (C) WREG = f + WREG + (C) Wd = lit10 + Wd + (C) Wd = Wb + Ws + (C) Wd = Wb + lit5 + (C) f = f .AND. WREG WREG = f .AND. WREG Wd = lit10 .AND. Wd Wd = Wb .AND. Ws Wd = Wb .AND. lit5 f = Arithmetic Right Shift f WREG = Arithmetic Right Shift f Wd = Arithmetic Right Shift Ws Wnd = Arithmetic Right Shift Wb by Wns Wnd = Arithmetic Right Shift Wb by lit5 Bit Clear f Bit Clear Ws Branch if Carry Branch if greater than or equal Branch if unsigned greater than or equal Branch if greater than Branch if unsigned greater than Branch if less than or equal Branch if unsigned less than or equal Branch if less than Branch if unsigned less than Branch if Negative Branch if Not Carry Branch if Not Negative Branch if Not Zero Branch Unconditionally Branch if Zero Computed Branch Bit Set f Bit Set Ws Write C bit to Ws Write Z bit to Ws Bit Toggle f Bit Toggle Ws Bit Test f, Skip if Clear Bit Test Ws, Skip if Clear Bit Test f, Skip if Set Bit Test Ws, Skip if Set Description # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 1 (2) 2 1 (2) 2 1 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) Status Flags Affected C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z N,Z N,Z N,Z N,Z N,Z C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z None None None None None None None None None None None None None None None None None None None None None None None None None None None None 2 ADDC ADDC ADDC ADDC ADDC ADDC 3 AND AND AND AND AND AND 4 ASR ASR ASR ASR ASR ASR 5 BCLR BCLR BCLR 6 BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA BRA 7 BSET BSET BSET 8 BSW BSW.C BSW.Z 9 BTG BTG BTG 10 BTSC BTSC BTSC 11 BTSS BTSS BTSS © 2011 Microchip Technology Inc. DS70293E-page 271 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-2: Base Instr # 12 Assembly Mnemonic BTST BTST BTST.C BTST.Z BTST.C BTST.Z 13 BTSTS BTSTS BTSTS.C BTSTS.Z 14 CALL CALL CALL 15 CLR CLR CLR CLR 16 17 CLRWDT COM CLRWDT COM COM COM 18 CP CP CP CP 19 CP0 CP0 CP0 20 CPB CPB CPB CPB 21 22 23 24 25 26 CPSEQ CPSGT CPSLT CPSNE DAW DEC CPSEQ CPSGT CPSLT CPSNE DAW DEC DEC DEC 27 DEC2 DEC2 DEC2 DEC2 28 29 DISI DIV DISI DIV.S DIV.SD DIV.U DIV.UD 30 31 32 33 34 EXCH FBCL FF1L FF1R GOTO EXCH FBCL FF1L FF1R GOTO GOTO f f,WREG Ws,Wd f Wb,#lit5 Wb,Ws f Ws f Wb,#lit5 Wb,Ws Wb, Wn Wb, Wn Wb, Wn Wb, Wn Wn f f,WREG Ws,Wd f f,WREG Ws,Wd #lit14 Wm,Wn Wm,Wn Wm,Wn Wm,Wn Wns,Wnd Ws,Wnd Ws,Wnd Ws,Wnd Expr Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f,#bit4 Ws,#bit4 Ws,#bit4 Ws,Wb Ws,Wb f,#bit4 Ws,#bit4 Ws,#bit4 lit23 Wn f WREG Ws Bit Test f Bit Test Ws to C Bit Test Ws to Z Bit Test Ws to C Bit Test Ws to Z Bit Test then Set f Bit Test Ws to C, then Set Bit Test Ws to Z, then Set Call subroutine Call indirect subroutine f = 0x0000 WREG = 0x0000 Ws = 0x0000 Clear Watchdog Timer f=f WREG = f Wd = Ws Compare f with WREG Compare Wb with lit5 Compare Wb with Ws (Wb – Ws) Compare f with 0x0000 Compare Ws with 0x0000 Compare f with WREG, with Borrow Compare Wb with lit5, with Borrow Compare Wb with Ws, with Borrow (Wb – Ws – C) Compare Wb with Wn, skip if = Compare Wb with Wn, skip if > Compare Wb with Wn, skip if < Compare Wb with Wn, skip if ≠ Wn = decimal adjust Wn f=f–1 WREG = f – 1 Wd = Ws – 1 f=f–2 WREG = f – 2 Wd = Ws – 2 Disable Interrupts for k instruction cycles Signed 16/16-bit Integer Divide Signed 32/16-bit Integer Divide Unsigned 16/16-bit Integer Divide Unsigned 32/16-bit Integer Divide Swap Wns with Wnd Find Bit Change from Left (MSb) Side Find First One from Left (MSb) Side Find First One from Right (LSb) Side Go to address Go to indirect Description # of # of Words Cycles 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 (2 or 3) 1 1 1 1 1 1 1 1 18 18 18 18 1 1 1 1 2 2 Status Flags Affected Z C Z C Z Z C Z None None None None None WDTO,Sleep N,Z N,Z N,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None C C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None N,Z,C,OV N,Z,C,OV N,Z,C,OV N,Z,C,OV None C C C None None DS70293E-page 272 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-2: Base Instr # 35 Assembly Mnemonic INC INC INC INC 36 INC2 INC2 INC2 INC2 37 IOR IOR IOR IOR IOR IOR 38 39 LNK LSR LNK LSR LSR LSR LSR LSR 40 MOV MOV MOV MOV MOV MOV.b MOV MOV MOV MOV.D MOV.D 41 MUL MUL.SS MUL.SU MUL.US MUL.UU MUL.SU MUL.UU MUL 42 NEG NEG NEG NEG 43 NOP NOP NOPR 44 POP POP POP POP.D POP.S 45 PUSH PUSH PUSH PUSH.D PUSH.S 46 47 PWRSAV RCALL PWRSAV RCALL RCALL #lit1 Expr Wn f Wso Wns f Wdo Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd #lit14 f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f,Wn f f,WREG #lit16,Wn #lit8,Wn Wn,f Wso,Wdo WREG,f Wns,Wd Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,Ws,Wnd Wb,#lit5,Wnd Wb,#lit5,Wnd f f f,WREG Ws,Wd f=f+1 WREG = f + 1 Wd = Ws + 1 f=f+2 WREG = f + 2 Wd = Ws + 2 f = f .IOR. WREG WREG = f .IOR. WREG Wd = lit10 .IOR. Wd Wd = Wb .IOR. Ws Wd = Wb .IOR. lit5 Link Frame Pointer f = Logical Right Shift f WREG = Logical Right Shift f Wd = Logical Right Shift Ws Wnd = Logical Right Shift Wb by Wns Wnd = Logical Right Shift Wb by lit5 Move f to Wn Move f to f Move f to WREG Move 16-bit literal to Wn Move 8-bit literal to Wn Move Wn to f Move Ws to Wd Move WREG to f Move Double from W(ns):W(ns + 1) to Wd Move Double from Ws to W(nd + 1):W(nd) {Wnd + 1, Wnd} = signed(Wb) * signed(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * signed(Ws) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(Ws) {Wnd + 1, Wnd} = signed(Wb) * unsigned(lit5) {Wnd + 1, Wnd} = unsigned(Wb) * unsigned(lit5) W3:W2 = f * WREG f=f+1 WREG = f + 1 Wd = Ws + 1 No Operation No Operation Pop f from Top-of-Stack (TOS) Pop from Top-of-Stack (TOS) to Wdo Pop from Top-of-Stack (TOS) to W(nd):W(nd + 1) Pop Shadow Registers Push f to Top-of-Stack (TOS) Push Wso to Top-of-Stack (TOS) Push W(ns):W(ns + 1) to Top-of-Stack (TOS) Push Shadow Registers Go into Sleep or Idle mode Relative Call Computed Call Description # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 1 1 1 2 1 1 2 2 Status Flags Affected C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z N,Z N,Z N,Z N,Z N,Z None C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z None None N,Z None None None None None None None None None None None None None None C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None All None None None None WDTO,Sleep None None © 2011 Microchip Technology Inc. DS70293E-page 273 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-2: Base Instr # 48 Assembly Mnemonic REPEAT REPEAT REPEAT 49 50 51 52 53 RESET RETFIE RETLW RETURN RLC RESET RETFIE RETLW RETURN RLC RLC RLC 54 RLNC RLNC RLNC RLNC 55 RRC RRC RRC RRC 56 RRNC RRNC RRNC RRNC 57 58 SE SETM SE SETM SETM SETM 59 SL SL SL SL SL SL 60 SUB SUB SUB SUB SUB SUB 61 SUBB SUBB SUBB SUBB SUBB SUBB 62 SUBR SUBR SUBR SUBR SUBR 63 SUBBR SUBBR SUBBR SUBBR SUBBR 64 SWAP SWAP.b SWAP 65 66 67 68 TBLRDH TBLRDL TBLWTH TBLWTL TBLRDH TBLRDL TBLWTH TBLWTL f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd f f,WREG Ws,Wd Ws,Wnd f WREG Ws f f,WREG Ws,Wd Wb,Wns,Wnd Wb,#lit5,Wnd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd f f,WREG Wb,Ws,Wd Wb,#lit5,Wd Wn Wn Ws,Wd Ws,Wd Ws,Wd Ws,Wd #lit10,Wn INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax #lit14 Wn Description Repeat Next Instruction lit14 + 1 times Repeat Next Instruction (Wn) + 1 times Software device Reset Return from interrupt Return with literal in Wn Return from Subroutine f = Rotate Left through Carry f WREG = Rotate Left through Carry f Wd = Rotate Left through Carry Ws f = Rotate Left (No Carry) f WREG = Rotate Left (No Carry) f Wd = Rotate Left (No Carry) Ws f = Rotate Right through Carry f WREG = Rotate Right through Carry f Wd = Rotate Right through Carry Ws f = Rotate Right (No Carry) f WREG = Rotate Right (No Carry) f Wd = Rotate Right (No Carry) Ws Wnd = sign-extended Ws f = 0xFFFF WREG = 0xFFFF Ws = 0xFFFF f = Left Shift f WREG = Left Shift f Wd = Left Shift Ws Wnd = Left Shift Wb by Wns Wnd = Left Shift Wb by lit5 f = f – WREG WREG = f – WREG Wn = Wn – lit10 Wd = Wb – Ws Wd = Wb – lit5 f = f – WREG – (C) WREG = f – WREG – (C) Wn = Wn – lit10 – (C) Wd = Wb – Ws – (C) Wd = Wb – lit5 – (C) f = WREG – f WREG = WREG – f Wd = Ws – Wb Wd = lit5 – Wb f = WREG – f – (C) WREG = WREG – f – (C) Wd = Ws – Wb – (C) Wd = lit5 – Wb – (C) Wn = nibble swap Wn Wn = byte swap Wn Read Prog to Wd Read Prog to Wd Write Ws to Prog Write Ws to Prog # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 (2) 3 (2) 3 (2) 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 2 2 Status Flags Affected None None None None None None C,N,Z C,N,Z C,N,Z N,Z N,Z N,Z C,N,Z C,N,Z C,N,Z N,Z N,Z N,Z C,N,Z None None None C,N,OV,Z C,N,OV,Z C,N,OV,Z N,Z N,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z C,DC,N,OV,Z None None None None None None DS70293E-page 274 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 26-2: Base Instr # 69 70 Assembly Mnemonic ULNK XOR ULNK XOR XOR XOR XOR XOR 71 ZE ZE f f,WREG #lit10,Wn Wb,Ws,Wd Wb,#lit5,Wd Ws,Wnd INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Syntax Description Unlink Frame Pointer f = f .XOR. WREG WREG = f .XOR. WREG Wd = lit10 .XOR. Wd Wd = Wb .XOR. Ws Wd = Wb .XOR. lit5 Wnd = Zero-extend Ws # of # of Words Cycles 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Status Flags Affected None N,Z N,Z N,Z N,Z N,Z C,Z,N © 2011 Microchip Technology Inc. DS70293E-page 275 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 NOTES: DS70293E-page 276 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 27.0 DEVELOPMENT SUPPORT 27.1 MPLAB Integrated Development Environment Software The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011 Microchip Technology Inc. DS70293E-page 277 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 27.2 MPLAB C Compilers for Various Device Families 27.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 27.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 27.6 MPLAB Assembler, Linker and Librarian for Various Device Families 27.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS70293E-page 278 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 27.7 MPLAB SIM Software Simulator 27.9 MPLAB ICD 3 In-Circuit Debugger System The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 27.8 MPLAB REAL ICE In-Circuit Emulator System 27.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and and dsPIC® Flash programming of PIC® microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011 Microchip Technology Inc. DS70293E-page 279 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 27.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 27.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 27.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS70293E-page 280 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 electrical characteristics. Additional information is provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 family are listed below. Exposure to these maximum rating conditions for extended periods can affect device reliability. Functional operation of the device at these or any other conditions above the parameters indicated in the operation listings of this specification is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +125°C Storage temperature .............................................................................................................................. -65°C to +160°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant with respect to VSS(4) .................................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 3.0V(4) .................................................. -0.3V to +5.6V Voltage on any 5V tolerant pin with respect to Vss when VDD < 3.0V(4) ...................................................... -0.3V to 3.6V Voltage on VCAP with respect to VSS ...................................................................................................... 2.25V to 2.75V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin(2) ...........................................................................................................................250 mA Maximum output current sunk by any I/O pin(3) ........................................................................................................4 mA Maximum output current sourced by any I/O pin(3) ...................................................................................................4 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports(2) ...............................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” can cause permanent damage to the device. This is a stress rating only, and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods can affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 28-2). 3: Exceptions are CLKOUT, which is able to sink/source 25 mA, and the VREF+, VREF-, SCLx, SDAx, PGECx and PGEDx pins, which are able to sink/source 12 mA. 4: See the “Pin Diagrams” section for 5V tolerant pins. © 2011 Microchip Technology Inc. DS70293E-page 281 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 28.1 DC Characteristics OPERATING MIPS VS. VOLTAGE Max MIPS Characteristic VDD Range (in Volts) Temp Range (in °C) PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 40 40 TABLE 28-1: 3.0-3.6V 3.0-3.6V -40°C to +85°C -40°C to +125°C TABLE 28-2: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Extended Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal chip power dissipation: PINT = VDD x (IDD – Σ IOH) I/O Pin Power Dissipation: I/O = Σ ({VDD – VOH} x IOH) + Σ (VOL x IOL) Maximum Allowed Power Dissipation PDMAX (TJ – TA)/θJA W TJ TA -40 -40 — — +155 +125 °C °C TJ TA -40 -40 — — +125 +85 °C °C PD PINT + PI/O W TABLE 28-3: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ 30 40 45 50 30 Max — — — — — Unit °C/W °C/W °C/W °C/W °C/W Notes 1 1 1 1 1 Package Thermal Resistance, 44-pin QFN Package Thermal Resistance, 44-pin TFQP Package Thermal Resistance, 28-pin SPDIP Package Thermal Resistance, 28-pin SOIC Package Thermal Resistance, 28-pin QFN-S Note 1: Junction to ambient thermal resistance, Theta-JA (θ JA) numbers are achieved by package simulations. θJA θJA θJA θJA θJA DS70293E-page 282 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. Operating Voltage DC10 DC12 DC16 Supply Voltage VDD VDR VPOR 3.0 RAM Data Retention Voltage(2) VDD Start Voltage to ensure internal Power-on Reset signal VDD Rise Rate to ensure internal Power-on Reset signal VDD Core(3) Internal regulator voltage 1.8 — — — — 3.6 — VSS V V V Industrial and Extended — — DC17 SVDD 0.03 — — V/ms 0-3.0V in 0.1s DC18 VCORE 2.25 — 2.75 V Voltage is dependent on load, temperature and VDD Note 1: 2: 3: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. This is the limit to which VDD can be lowered without losing RAM data. These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70293E-page 283 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤TA ≤+125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Operating Current (IDD)(2) DC20d DC20a DC20b DC20c DC21d DC21a DC21b DC21c DC22d DC22a DC22b DC22c DC23d DC23a DC23b DC23c DC24d DC24a DC24b DC24c Note 1: 2: 18 18 18 18 30 30 30 30 34 34 34 35 49 49 49 49 63 63 63 63 21 22 22 25 35 34 34 36 42 41 42 44 58 57 57 60 75 74 74 76 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V 40 MIPS 3.3V 30 MIPS 3.3V 20 MIPS 3.3V 16 MIPS 3.3V 10 MIPS Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSC1 driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD, WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating; however, every peripheral is being clocked (PMD bits are all zeroed). DS70293E-page 284 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Idle Current (IIDLE): Core OFF Clock ON Base Current(2) DC40d DC40a DC40b DC40c DC41d DC41a DC41b DC41c DC42d DC42a DC42b DC42c DC43a DC43d DC43b DC43c DC44d DC44a DC44b DC44c Note 1: 2: 8 8 9 10 13 13 13 13 15 16 16 17 23 23 24 25 31 31 32 34 10 10 10 13 15 15 16 19 18 18 19 22 27 26 28 31 42 36 39 43 mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C +25°C -40°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V 40 MIPS 3.3V 30 MIPS 3.3V 20 MIPS 3.3V 16 MIPS 3.3V 10 MIPS Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Base IIDLE current is measured with core off, clock on and all modules turned off. Peripheral Module Disable SFR registers are zeroed. All I/O pins are configured as inputs and pulled to VSS. © 2011 Microchip Technology Inc. DS70293E-page 285 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max Units Conditions DC CHARACTERISTICS Parameter No. Typical(1) Power-Down Current (IPD)(2) DC60d DC60a DC60b DC60c DC61d DC61a DC61b DC61c Note 1: 2: 3: 4: 24 28 124 350 8 10 12 13 68 87 292 1000 13 15 20 25 μA μA μA μA μA μA μA μA -40°C +25°C +85°C +125°C -40°C +25°C +85°C +125°C 3.3V Watchdog Timer Current: ΔIWDT(3) 3.3V Base Power-Down Current(2,4) Data in the Typical column is at 3.3V, 25°C unless otherwise stated. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled to VSS. WDT, etc., are all switched off and VREGS (RCON) = 1. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. These currents are measured on the device containing the most memory in this family. TABLE 28-8: DC CHARACTERISTICS: DOZE CURRENT (IDOZE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Max 50 30 30 50 30 30 50 30 30 50 30 30 Doze Ratio 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 1:2 1:64 1:128 Units mA mA mA mA mA mA mA mA mA mA mA mA +125°C 3.3V 40 MIPS +85°C 3.3V 40 MIPS +25°C 3.3V 40 MIPS -40°C 3.3V 40 MIPS Conditions DC CHARACTERISTICS Parameter No. DC73a DC73f DC73g DC70a DC70f DC70g DC71a DC71f DC71g DC72a DC72f DC72g Note 1: Typical(1) 20 17 17 20 17 17 20 17 17 21 18 18 Data in the Typical column is at 3.3V, 25°C unless otherwise stated. DS70293E-page 286 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Input Low Voltage I/O pins PMP pins MCLR I/O Pins with OSC1 or SOSCI I/O Pins with SDAx, SCLx I/O Pins with SDAx, SCLx VSS VSS VSS VSS VSS VSS 0.7 VDD 0.7 VDD 0.24 VDD + 0.8 0.24 VDD + 0.8 0.7 VDD 2.1 50 — — — — — — — — — — — — 250 0.2 VDD 0.15 VDD 0.2 VDD 0.2 VDD 0.3 VDD 0.8 VDD 5.5 VDD 5.5 5.5 5.5 400 V V V V V V V V V V V V μA SMbus disabled SMbus enabled VDD = 3.3V, VPIN = VSS SMbus disabled SMbus enabled — PMPTTL = 1 Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. VIL DI10 DI11 DI15 DI16 DI18 DI19 VIH DI20 DI21 Input High Voltage I/O Pins Not 5V Tolerant(4) I/O Pins 5V Tolerant(4) I/O Pins Not 5V Tolerant with PMP(4) I/O Pins 5V Tolerant with PMP(4) SDAx, SCLx SDAx, SCLx DI28 DI29 ICNPU DI30 Note 1: 2: CNx Pull-up Current 3: 4: 5: 6: 7: 8: 9: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See “Pin Diagrams” for the 5V tolerant I/O pins. VIL source < (VSS – 0.3). Characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. © 2011 Microchip Technology Inc. DS70293E-page 287 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Input Leakage Current(2,3) I/O pins 5V Tolerant(4) I/O Pins Not 5V Tolerant(4) — — — — ±2 ±1 μA μA VSS ≤VPIN ≤VDD, Pin at high-impedance VSS ≤VPIN ≤VDD, Pin at high-impedance, 40°C ≤ TA ≤+85°C Shared with external reference pins, 40°C ≤ TA ≤+85°C VSS ≤VPIN ≤VDD, Pin at high-impedance, -40°C ≤TA ≤+125°C Analog pins shared with external reference pins, -40°C ≤TA ≤+125°C VSS ≤VPIN ≤VDD VSS ≤VPIN ≤VDD, XT and HS modes Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. IIL DI50 DI51 DI51a I/O Pins Not 5V Tolerant(4) — — ±2 μA DI51b I/O Pins Not 5V Tolerant(4) — — ±3.5 μA DI51c I/O Pins Not 5V Tolerant(4) — — ±8 μA DI55 DI56 Note 1: 2: MCLR OSC1 — — — — ±2 ±2 μA μA 3: 4: 5: 6: 7: 8: 9: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See “Pin Diagrams” for the 5V tolerant I/O pins. VIL source < (VSS – 0.3). Characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. DS70293E-page 288 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-9: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Input Low Injection Current 0 IICH DI60b 0 — +5(6,7,8) mA Input High Injection Current All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, RB14, and digital 5V-tolerant designated pins Absolute instantaneous sum of all ± input injection currents from all I/O pins I ( | IICL + | IICH | ) ≤∑ICT — -5(5,8) mA All pins except VDD, VSS, AVDD, AVSS, MCLR, VCAP, SOSCI, SOSCO, and RB14 Min Typ(1) Max Units Conditions DC CHARACTERISTICS Param Symbol No. IICL DI60a ∑ICT I DI60c Total Input Injection Current (sum of all I/O and control pins) -20(9) — +20(9) mA Note 1: 2: 3: 4: 5: 6: 7: 8: 9: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current can be measured at different input voltages. Negative current is defined as current sourced by the pin. See “Pin Diagrams” for the 5V tolerant I/O pins. VIL source < (VSS – 0.3). Characterized but not tested. Non-5V tolerant pins VIH source > (VDD + 0.3), 5V tolerant pins VIH source > 5.5V. Characterized but not tested. Digital 5V tolerant pins cannot tolerate any “positive” input injection current from input sources > 5.5V. Injection currents > | 0 | can affect the ADC results by approximately 4-6 counts. Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted provided the mathematical “absolute instantaneous” sum of the input injection currents from all pins do not exceed the specified limit. Characterized but not tested. © 2011 Microchip Technology Inc. DS70293E-page 289 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-10: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Output Low Voltage I/O ports OSC2/CLKO VOH DO20 DO26 Output High Voltage I/O ports OSC2/CLKO 2.40 2.41 — — — — V V IOH = -2.3 mA, VDD = 3.3V IOH = -1.3 mA, VDD = 3.3V — — — — 0.4 0.4 V V IOL = 2 mA, VDD = 3.3V IOL = 2 mA, VDD = 3.3V Min Typ Max Units Conditions Param Symbol No. VOL DO10 DO16 TABLE 28-11: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic BOR Event on VDD transition high-to-low BOR event is tied to VDD core voltage decrease Min(1) 2.40 Typ — Max(1) 2.55 Units V Conditions — Param No. BO10 Symbol VBOR Note 1: Parameters are for design guidance only and are not tested in manufacturing. DS70293E-page 290 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-12: DC CHARACTERISTICS: PROGRAM MEMORY DC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Program Flash Memory D130a D131 D132B D134 D135 D136a D136b D137a D137b D138a D138b Note 1: 2: EP VPR VPEW TRETD IDDP TRW TRW TPE TPE TWW TWW Cell Endurance VDD for Read VDD for Self-Timed Write Characteristic Retention Supply Current during Programming Row Write Time Row Write Time Page Erase Time Page Erase Time Word Write Cycle Time Word Write Cycle Time 10,000 VMIN VMIN 20 — 1.32 1.28 20.1 19.5 42.3 41.1 — — — — 10 — — — — — — — 3.6 3.6 — — 1.74 1.79 26.5 27.3 55.9 57.6 E/W -40° C to +125° C V V VMIN = Minimum operating voltage VMIN = Minimum operating voltage Min Typ(1) Max Units Conditions Param Symbol No. Year Provided no other specifications are violated mA ms ms ms ms µs µs — TRW = 11064 FRC cycles, TA = +85°C, See Note 2 TRW = 11064 FRC cycles, TA = +125°C, See Note 2 TPE = 168517 FRC cycles, TA = +85°C, See Note 2 TPE = 168517 FRC cycles, TA = +125°C, See Note 2 TWW = 355 FRC cycles, TA = +85°C, See Note 2 TWW = 355 FRC cycles, TA = +125°C, See Note 2 Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Other conditions: FRC = 7.37 MHz, TUN = b'011111 (for Min), TUN = b'100000 (for Max). This parameter depends on the FRC accuracy (see Table 28-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). For complete details on calculating the Minimum and Maximum time see Section 5.3 “Programming Operations”. TABLE 28-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Standard Operating Conditions (unless otherwise stated): Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. Symbol CEFC Characteristics External Filter Capacitor Value Min 4.7 Typ 10 Max — Units μF Comments Capacitor must be low series resistance (< 5 Ohms) © 2011 Microchip Technology Inc. DS70293E-page 291 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 28.2 AC Characteristics and Timing Parameters This section defines PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 and PIC24HJ128GPX02/X04 AC characteristics and timing parameters. TABLE 28-14: TEMPERATURE AND VOLTAGE SPECIFICATIONS – AC Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Operating voltage VDD range as described in Table 28-1. AC CHARACTERISTICS FIGURE 28-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSC2 Load Condition 1 – for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464Ω CL = 50 pF for all pins except OSC2 15 pF for OSC2 output TABLE 28-15: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. DO50 COSC2 Characteristic OSC2/SOSC2 pin Min — Typ — Max 15 Units pF Conditions In XT and HS modes when external clock is used to drive OSC1 EC mode In I2C™ mode DO56 DO58 CIO CB All I/O pins and OSC2 SCLx, SDAx — — — — 50 400 pF pF DS70293E-page 292 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-2: EXTERNAL CLOCK TIMING Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 OS20 OS25 OS30 OS30 OS31 OS31 CLKO OS41 OS40 TABLE 28-16: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency Min DC Typ(1) — Max 40 Units MHz Conditions EC Param No. OS10 Symb FIN 3.5 10 12.5 — — — — — — — 5.2 5.2 16 10 40 33 DC DC 0.625 x TOSC 20 — — 18 MHz MHz kHz ns ns ns ns ns ns mA/V XT HS SOSC OS20 OS25 OS30 OS31 OS40 OS41 OS42 Note 1: 2: TOSC TCY TosL, TosH TosR, TosF TckR TckF GM TOSC = 1/FOSC Instruction Cycle Time(2) External Clock in (OSC1) High or Low Time External Clock in (OSC1) Rise or Fall Time CLKO Rise Time(3) CLKO Fall Time(3) External Oscillator Transconductance(4) 25 0.375 x TOSC — — — 14 EC EC — — VDD = 3.3V TA = +25ºC 3: 4: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Instruction cycle period (TCY) equals two times the input oscillator time-base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. When an external clock input is used, the “max.” cycle time limit is “DC” (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSC2 pin. Data for this parameter is Preliminary. This parameter is characterized, but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70293E-page 293 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-17: PLL CLOCK TIMING SPECIFICATIONS (VDD = 3.0V TO 3.6V) AC CHARACTERISTICS Param No. OS50 Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Jitter) Min 0.8 Typ(1) — Max 8 Units MHz Conditions ECPLL, HSPLL, XTPLL modes — Symbol FPLLI OS51 OS52 OS53 Note 1: 2: FSYS TLOCK DCLK 100 0.9 -3 — 1.5 0.5 200 3.1 3 MHz mS % — Measured over 100 ms period Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. These parameters are characterized by similarity, but are not tested in manufacturing. This specification is based on clock cycle by clock cycle measurements. To calculate the effective jitter for individual time bases or communication clocks use this formula:: D CLK Peripheral Clock Jitter = ----------------------------------------------------------------------F OSC ⎛ ------------------------------------------------------------- ⎞ ⎝ Peripheral Bit Rate Clock⎠ For example: Fosc = 32 MHz, DCLK = 3%, SPI bit rate clock, (i.e., SCK) is 2 MHz. D CLK 3%3% SPI SCK Jitter = ----------------------------- = --------- = ------- = 0.75% 4 16 ⎛ 32 M Hz⎞ ------------------⎝ 2 M Hz ⎠ TABLE 28-18: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions Characteristic Internal FRC Accuracy @ 7.3728 MHz(1) F20 Note 1: FRC FRC -2 -5 — — +2 +5 % % -40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V VDD = 3.0-3.6V Frequency calibrated at 25°C and 3.3V. TUN bits can be used to compensate for temperature drift. TABLE 28-19: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min Typ Max Units Conditions Characteristic LPRC @ 32.768 kHz(1) F21 Note 1: LPRC LPRC -20 -30 ±6 — +20 +30 % % -40°C ≤ TA ≤ +85°C -40°C ≤ TA ≤ +125°C VDD = 3.0-3.6V VDD = 3.0-3.6V Change of LPRC frequency as VDD changes. DS70293E-page 294 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-3: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) Old Value DO31 DO32 Note: Refer to Figure 28-1 for load conditions. New Value TABLE 28-20: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time (input) CNx High or Low Time (input) Min — — 20 2 Typ(1) 10 10 — — Max 25 25 — — Units ns ns ns TCY Conditions — — — — Param No. DO31 DO32 DI35 DI40 Note 1: Symbol TIOR TIOF TINP TRBP Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. DS70293E-page 295 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER AND POWER-UP TIMER TIMING CHARACTERISTICS SY12 VDD MCLR Internal POR SY10 SY11 PWRT Time-out OSC Time-out Internal Reset Watchdog Timer Reset SY13 I/O Pins SY35 FSCM Delay Note: Refer to Figure 28-1 for load conditions. SY20 SY13 SY30 DS70293E-page 296 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-21: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic(1) MCLR Pulse Width (low) Power-up Timer Period Min 2 — Typ(2) — 2 4 8 16 32 64 128 10 0.72 Max — — Units μs ms Conditions -40°C to +85°C -40°C to +85°C User programmable Param Symbol No. SY10 SY11 TMCL TPWRT SY12 SY13 TPOR TIOZ Power-on Reset Delay I/O High-Impedance from MCLR Low or Watchdog Timer Reset Watchdog Timer Time-out Period 3 0.68 30 1.2 μs μs -40°C to +85°C — SY20 TWDT1 — — — — See Section 25.4 “Watchdog Timer (WDT)” and LPRC specification F21 (Table 28-19) TOSC = OSC1 period -40°C to +85°C SY30 SY35 Note 1: 2: TOST TFSCM Oscillator Start-up Timer Period Fail-Safe Clock Monitor Delay — — 1024 TOSC 500 — 900 — μs These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. © 2011 Microchip Technology Inc. DS70293E-page 297 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-5: TIMER1, 2, 3 AND 4 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 28-1 for load conditions. TABLE 28-22: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic TxCK High Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA11 TTXL TxCK Low Time Synchronous, no prescaler Synchronous, with prescaler Asynchronous TA15 TTXP TxCK Input Period Synchronous, no prescaler Synchronous, with prescaler Min TCY + 20 (TCY + 20)/N 20 (TCY + 20) (TCY + 20)/N 20 2 TCY + 40 Greater of: 40 ns or (2 TCY + 40)/ N 40 DC Typ — — — — — — — — Max — — — — — — — — Units ns ns ns ns ns ns ns — Conditions Must also meet parameter TA15. N = prescale value (1, 8, 64, 256) Must also meet parameter TA15. N = prescale value (1, 8, 64, 256) — N = prescale value (1, 8, 64, 256) — — Param No. TA10 Symbol TTXH Asynchronous OS60 Ft1 SOSCI/T1CK Oscillator Input frequency Range (oscillator enabled by setting bit TCS (T1CON)) — — — 50 ns kHz TA20 Note 1: TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment Timer1 is a Type A. 0.75 TCY + 40 1.75 TCY + 40 — — DS70293E-page 298 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-23: TIMER2 AND TIMER 4 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) TxCK High Synchronous mode Time Min Greater of: 20 or (TCY + 20)/N Typ — Max — Units ns Conditions Must also meet parameter TB15 N = prescale value (1, 8, 64, 256) Must also meet parameter TB15 N = prescale value (1, 8, 64, 256) N = prescale value (1, 8, 64, 256) Param No. TB10 Symbol TtxH TB11 TtxL TxCK Low Synchronous Time mode Greater of: 20 or (TCY + 20)/N — — ns TB15 TtxP TxCK Input Period Synchronous mode Greater of: 40 or (2 TCY + 40)/N 0.75 TCY + 40 — — ns TB20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment — 1.75 TCY + 40 ns Note 1: These parameters are characterized, but are not tested in manufacturing. TABLE 28-24: TIMER3 AND TIMER5 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) TxCK High Time TxCK Low Time TxCK Input Period Synchronous Synchronous Synchronous, with prescaler Min TCY + 20 TCY + 20 2 TCY + 40 Typ — — — Max — — — Units ns ns ns Conditions Must also meet parameter TC15 Must also meet parameter TC15 N = prescale value (1, 8, 64, 256) Param No. TC10 TC11 TC15 Symbol TtxH TtxL TtxP TC20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment 0.75 TCY + 40 — 1.75 TCY + 40 ns Note 1: These parameters are characterized, but are not tested in manufacturing. © 2011 Microchip Technology Inc. DS70293E-page 299 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-6: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 28-1 for load conditions. IC11 TABLE 28-25: INPUT CAPTURE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic(1) ICx Input Low Time ICx Input High Time ICx Input Period No Prescaler With Prescaler IC11 IC15 Note 1: TccH TccP No Prescaler With Prescaler Min 0.5 TCY + 20 10 0.5 TCY + 20 10 (TCY + 40)/N Max — — — — — Units ns ns ns ns ns N = prescale value (1, 4, 16) — Conditions — Param No. IC10 Symbol TccL These parameters are characterized but not tested in manufacturing. FIGURE 28-7: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS OCx (Output Compare or PWM Mode) OC11 OC10 Note: Refer to Figure 28-1 for load conditions. TABLE 28-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min — — Typ — — Max — — Units ns ns Conditions See parameter D032 See parameter D031 Param Symbol No. OC10 OC11 Note 1: TccF TccR Characteristic(1) OCx Output Fall Time OCx Output Rise Time These parameters are characterized but not tested in manufacturing. DS70293E-page 300 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-8: OC/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA OC15 OCx Active Tri-state TABLE 28-27: SIMPLE OC/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic(1) Fault Input to PWM I/O Change Fault Input Pulse Width Min — TCY + 20 Typ — — Max TCY + 20 — Units ns ns Conditions — — Param No. OC15 OC20 Note 1: Symbol TFD TFLT These parameters are characterized but not tested in manufacturing. © 2011 Microchip Technology Inc. DS70293E-page 301 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-28: SPIx MAXIMUM DATA/CLOCK RATE SUMMARY AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Master Transmit/Receive (Full-Duplex) — Table 28-30 Table 28-31 — — — — Slave Transmit/Receive (Full-Duplex) — — — Table 28-32 Table 28-33 Table 28-34 Table 28-35 CKE 0,1 1 0 1 1 0 0 CKP 0, 1 0, 1 0, 1 0 1 1 0 SMP 0, 1 1 1 0 0 0 0 Maximum Data Rate 15 Mhz 9 Mhz 9 Mhz 15 Mhz 11 Mhz 15 Mhz 11 Mhz Master Transmit Only (Half-Duplex) Table 28-29 — — — — — — FIGURE 28-9: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 0) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SCKx (CKP = 1) SP35 SP20 SP21 SP21 SP20 SDOx SP30, SP31 MSb Bit 14 - - - - - -1 LSb SP30, SP31 Note: Refer to Figure 28-1 for load conditions. FIGURE 28-10: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY CKE = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SCKx (CKP = 1) SP35 SP20 SP21 SP21 SP20 SDOx MSb Bit 14 - - - - - -1 SP30, SP31 LSb Note: Refer to Figure 28-1 for load conditions. DS70293E-page 302 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-29: SPIx MASTER MODE (HALF-DUPLEX, TRANSMIT ONLY) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Frequency SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Min — — — — — — 30 Typ(2) — — — — — 6 — Max 15 — — — — 20 — Units MHz ns ns ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — — Param No. SP10 SP20 SP21 SP30 SP31 SP35 SP36 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, TscL2doV TdiV2scH, TdiV2scL These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 303 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-11: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS SP36 SCKx (CKP = 0) SP10 SCKx (CKP = 1) SP35 SP20 SP21 SP21 SP20 SDOx MSb Bit 14 - - - - - -1 SP30, SP31 LSb SP40 SDIx MSb In SP41 Bit 14 - - - -1 LSb In Note: Refer to Figure 28-1 for load conditions. TABLE 28-30: SPIx MASTER MODE (FULL-DUPLEX, CKE = 1, CKP = x, SMP = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Frequency SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min — — — — — Typ(2) — — — — — Max 9 — — — — Units MHz ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — Param No. SP10 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2sc, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS70293E-page 304 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-12: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS SCKx (CKP = 0) SP10 SCKx (CKP = 1) SP35 SP20 SP21 SP21 SP20 SDOx SP30, SP31 SDIx MSb Bit 14 - - - - - -1 LSb SP30, SP31 Bit 14 - - - -1 LSb In MSb In SP40 SP41 Note: Refer to Figure 28-1 for load conditions. TABLE 28-31: SPIx MASTER MODE (FULL-DUPLEX, CKE = 0, CKP = x, SMP = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Frequency SCKx Output Fall Time SCKx Output Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min — — — — — Typ(2) — — — — — Max 9 — — — — Units MHz ns ns ns ns Conditions -40ºC to +125ºC and see Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — Param No. SP10 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after — 6 20 ns TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to 30 — — ns — TdoV2scL First SCKx Edge TdiV2scH, Setup Time of SDIx Data 30 — — ns — TdiV2scL Input to SCKx Edge TscH2diL, Hold Time of SDIx Data Input 30 — — ns — TscL2diL to SCKx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 111 ns. The clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 305 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-13: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SCKx (CKP = 0) SP70 SCKx (CKP = 1) SP35 SP72 MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI MSb In SP41 SP40 Bit 14 - - - -1 LSb In LSb SP51 SP73 SP73 SP72 SP52 SDOx Note: Refer to Figure 28-1 for load conditions. DS70293E-page 306 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-32: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 0, SMP = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Input Frequency SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time SDOx Data Output Valid after SCKx Edge SDOx Data Output Setup to First SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx ↓ to SCKx ↑ or SCKx Input SSx ↑ to SDOx Output High-Impedance(4) Min — — — — — — 30 30 30 120 10 1.5 TCY + 40 Typ(2) — — — — — 6 — — — — — — Max 15 — — — — 20 — — — — 50 — Units MHz ns ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — — — — — — See Note 4 Param No. SP70 SP72 SP73 SP30 SP31 SP35 SP36 SP40 SP41 SP50 SP51 SP52 SP60 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, TscL2doV TdoV2scH, TdoV2scL TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ TscH2ssH SSx after SCKx Edge TscL2ssH TssL2doV SDOx Data Output Valid after — — 50 ns — SSx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specificiation. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 307 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-14: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SP60 SSx SP50 SCKx (CKP = 0) SP70 SCKx (CKP = 1) SP35 SP52 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI MSb In SP41 SP40 Note: Refer to Figure 28-1 for load conditions. Bit 14 - - - -1 LSb In SP72 LSb SP51 SP73 SP73 SP72 SP52 DS70293E-page 308 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-33: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 1, CKP = 1, SMP = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Input Frequency SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min — — — — — — 30 30 30 120 10 1.5 TCY + 40 — Typ(2) — — — — — 6 — — — — — — — Max 11 — — — — 20 — — — — 50 — 50 Units MHz ns ns ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — — — — — — See Note 4 — Param No. SP70 SP72 SP73 SP30 SP31 SP35 SP36 SP40 SP41 SP50 SP51 SP52 SP60 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx ↓ to SCKx ↑ or SCKx Input SSx ↑ to SDOx Output High-Impedance(4) TscH2ssH SSx after SCKx Edge TscL2ssH TssL2doV SDOx Data Output Valid after SSx Edge These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specificiation. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 309 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-15: SPIx SLAVE MODE (FULL-DUPLEX CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SCKX (CKP = 0) SP70 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP73 SP72 SP52 Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX MSb In SP41 SP40 Bit 14 - - - -1 Note: Refer to Figure 28-1 for load conditions. DS70293E-page 310 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-34: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 1, SMP = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Input Frequency SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min — — — — — — 30 30 30 120 10 1.5 TCY + 40 Typ(2) — — — — — 6 — — — — — — Max 15 — — — — 20 — — — — 50 — Units MHz ns ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — — — — — — See Note 4 Param No. SP70 SP72 SP73 SP30 SP31 SP35 SP36 SP40 SP41 SP50 SP51 SP52 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx ↓ to SCKx ↑ or SCKx Input SSx ↑ to SDOx Output High-Impedance(4) TscH2ssH SSx after SCKx Edge TscL2ssH These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 66.7 ns. Therefore, the SCK clock generated by the Master must not violate this specificiation. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 311 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-16: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS SSX SP50 SCKX (CKP = 0) SP70 SCKX (CKP = 1) SP35 SDOX MSb SP72 SP73 SP73 SP72 SP52 Bit 14 - - - - - -1 SP30,SP31 LSb SP51 LSb In SDIX MSb In SP41 SP40 Bit 14 - - - -1 Note: Refer to Figure 28-1 for load conditions. DS70293E-page 312 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-35: SPIx SLAVE MODE (FULL-DUPLEX, CKE = 0, CKP = 0, SMP = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+125°C for Extended Characteristic(1) Maximum SCK Input Frequency SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time SDOx Data Output Rise Time Min — — — — — — 30 30 30 120 10 1.5 TCY + 40 Typ(2) — — — — — 6 — — — — — — Max 11 — — — — 20 — — — — 50 — Units MHz ns ns ns ns ns ns ns ns ns ns ns Conditions See Note 3 See parameter DO32 and Note 4 See parameter DO31 and Note 4 See parameter DO32 and Note 4 See parameter DO31 and Note 4 — — — — — — See Note 4 Param No. SP70 SP72 SP73 SP30 SP31 SP35 SP36 SP40 SP41 SP50 SP51 SP52 Note 1: 2: 3: 4: Symbol TscP TscF TscR TdoF TdoR TscH2doV, SDOx Data Output Valid after TscL2doV SCKx Edge TdoV2scH, SDOx Data Output Setup to TdoV2scL First SCKx Edge TdiV2scH, TdiV2scL TscH2diL, TscL2diL TssL2scH, TssL2scL TssH2doZ Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge SSx ↓ to SCKx ↑ or SCKx Input SSx ↑ to SDOx Output High-Impedance(4) TscH2ssH SSx after SCKx Edge TscL2ssH These parameters are characterized, but are not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. The minimum clock period for SCKx is 91 ns. Therefore, the SCK clock generated by the Master must not violate this specificiation. Assumes 50 pF load on all SPIx pins. © 2011 Microchip Technology Inc. DS70293E-page 313 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-17: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 IM33 IM34 SDAx Start Condition Note: Refer to Figure 28-1 for load conditions. Stop Condition FIGURE 28-18: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 28-1 for load conditions. DS70293E-page 314 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-36: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min(1) Max Units Conditions Param Symbol No. IM10 IM11 IM20 IM21 IM25 IM26 IM30 IM31 IM33 IM34 IM40 IM45 IM50 IM51 Note TLO:SCL Clock Low Time 100 kHz mode TCY/2 (BRG + 1) — μs — 400 kHz mode TCY/2 (BRG + 1) — μs — — μs — 1 MHz mode(2) TCY/2 (BRG + 1) — μs — THI:SCL Clock High Time 100 kHz mode TCY/2 (BRG + 1) 400 kHz mode TCY/2 (BRG + 1) — μs — — μs — 1 MHz mode(2) TCY/2 (BRG + 1) SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be TF:SCL Fall Time from 10 to 400 pF 300 ns 400 kHz mode 20 + 0.1 CB (2) — 100 ns 1 MHz mode — 1000 ns CB is specified to be TR:SCL SDAx and SCLx 100 kHz mode Rise Time from 10 to 400 pF 300 ns 400 kHz mode 20 + 0.1 CB — 300 ns 1 MHz mode(2) 100 kHz mode 250 — ns — TSU:DAT Data Input Setup Time 400 kHz mode 100 — ns 1 MHz mode(2) 40 — ns 100 kHz mode 0 — μs — THD:DAT Data Input Hold Time 400 kHz mode 0 0.9 μs 1 MHz mode(2) 0.2 — μs — μs Only relevant for TSU:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) Setup Time Repeated Start — μs 400 kHz mode TCY/2 (BRG + 1) condition — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs After this period the THD:STA Start Condition 100 kHz mode TCY/2 (BRG + 1) Hold Time first clock pulse is — μs 400 kHz mode TCY/2 (BRG + 1) generated — μs 1 MHz mode(2) TCY/2 (BRG + 1) — μs — TSU:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) Setup Time 400 kHz mode TCY/2 (BRG + 1) — μs — μs 1 MHz mode(2) TCY/2 (BRG + 1) — ns — THD:STO Stop Condition 100 kHz mode TCY/2 (BRG + 1) Hold Time 400 kHz mode TCY/2 (BRG + 1) — ns — ns 1 MHz mode(2) TCY/2 (BRG + 1) 100 kHz mode — 3500 ns — TAA:SCL Output Valid From Clock 400 kHz mode — 1000 ns — 1 MHz mode(2) — 400 ns — 4.7 — μs Time the bus must be TBF:SDA Bus Free Time 100 kHz mode free before a new 400 kHz mode 1.3 — μs transmission can start 0.5 — μs 1 MHz mode(2) Bus Capacitive Loading — 400 pF — CB TPGD Pulse Gobbler Delay 65 390 ns See Note 3 1: BRG is the value of the I2C Baud Rate Generator. Refer to Section 19. “Inter-Integrated Circuit (I2C™)” (DS70235) in the “dsPIC33F/PIC24H Family Reference Manual”. Please see the Microchip website (www.microchip.com) for the latest dsPIC33F/PIC24H Family Reference Manual chapters. 2: Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). 3: Typical value for this parameter is 130 ns. © 2011 Microchip Technology Inc. DS70293E-page 315 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-19: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 IS33 IS34 SDAx Start Condition Stop Condition FIGURE 28-20: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out DS70293E-page 316 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-37: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic 100 kHz mode 400 kHz mode 1 MHz mode(1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS20 TF:SCL SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS21 TR:SCL SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS26 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS31 THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode(1) IS34 THD:ST O AC CHARACTERISTICS Param. Symbol IS10 Min 4.7 1.3 0.5 4.0 0.6 0.5 — 20 + 0.1 CB — — 20 + 0.1 CB — 250 100 100 0 0 0 4.7 0.6 0.25 4.0 0.6 0.25 4.7 0.6 0.6 4000 600 250 0 0 0 4.7 1.3 0.5 — Max — — — — — — 300 300 100 1000 300 300 — — — — 0.9 0.3 — — — — — — — — — — — 3500 1000 350 — — — 400 Units μs μs μs μs μs μs ns ns ns ns ns ns ns ns ns μs μs μs μs μs μs μs μs μs μs μs μs ns ns ns ns ns ns μs μs μs pF Conditions Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz — Device must operate at a minimum of 1.5 MHz Device must operate at a minimum of 10 MHz — CB is specified to be from 10 to 400 pF TLO:SCL Clock Low Time CB is specified to be from 10 to 400 pF — — Only relevant for Repeated Start condition After this period, the first clock pulse is generated — Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) 100 kHz mode 400 kHz mode 1 MHz mode(1) — IS40 TAA:SCL Output Valid From Clock — IS45 TBF:SDA Bus Free Time Time the bus must be free before a new transmission can start — IS50 Note 1: CB Bus Capacitive Loading Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). © 2011 Microchip Technology Inc. DS70293E-page 317 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 FIGURE 28-21: ECAN™ MODULE I/O TIMING CHARACTERISTICS CiTx Pin (output) Old Value CA10 CA11 New Value CiRx Pin (input) CA20 TABLE 28-38: ECAN™ MODULE I/O TIMING REQUIREMENTS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic(1) Port Output Fall Time Port Output Rise Time Pulse Width to Trigger CAN Wake-up Filter Min — — 120 Typ(2) — — Max — — Units ns ns ns Conditions See parameter D032 See parameter D031 — Param No. CA10 CA11 CA20 Note 1: 2: Symbol TioF TioR Tcwf These parameters are characterized but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS70293E-page 318 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-39: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Min. Typ Max. Units Conditions Param Symbol No. Characteristic Device Supply AD01 AVDD Module VDD Supply Greater of VDD – 0.3 or 3.0 VSS – 0.3 AVSS + 2.5 3.0 VREFL Reference Voltage Low AVSS 0 VREF IREF IAD Absolute Reference Voltage Current Drain Operating Current 2.5 — — — — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 AVDD – 2.5 0 3.6 10 9.0 3.2 V — V V V V V V μA mA mA VREFH = AVDD VREFL = AVSS = 0 VREF = VREFH - VREFL ADC off ADC operating in 10-bit mode, see Note 1 ADC operating in 12-bit mode, see Note 1 This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), positive input This voltage reflects Sample and Hold Channels 0, 1, 2, and 3 (CH0-CH3), negative input 10-bit ADC 12-bit ADC VREFH = AVDD VREFL = AVSS = 0 — AD02 AD05 AD05a AD06 AD06a AD07 AD08 AD09 AVSS VREFH Module VSS Supply Reference Voltage High — — — — — — — 7.0 2.7 Reference Inputs Analog Input AD12 VINH Input Voltage Range VINH VINL — VREFH V AD13 VINL Input Voltage Range VINL VREFL — AVSS + 1V V AD17 RIN Recommended Impedance of Analog Voltage Source — — — — 200 200 Ω Ω Note 1: These parameters are not characterized or tested in manufacturing. © 2011 Microchip Technology Inc. DS70293E-page 319 PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-40: ADC MODULE SPECIFICATIONS (12-BIT MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min. Typ Max. Units Conditions Param No. AD20a AD21a AD22a AD23a AD24a AD25a AD20a AD21a AD22a AD23a AD24a AD25a AD30a AD31a AD32a AD33a AD34a Note 1: Symbol ADC Accuracy (12-bit Mode) – Measurements with external VREF+/VREFNr INL DNL GERR EOFF — Nr INL DNL GERR EOFF — THD SINAD SFDR FNYQ ENOB Resolution(1) Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity Resolution(1) Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits -2 > -1 2 2 — — 68.5 80 — 11.09 -2 > -1 — — — 12 data bits — — 3.4 0.9 — 12 data bits — — 10.5 3.8 — — 69.5 — — 11.3 +2 (VDD + 0.3V) or VIL source < (VSS – 0.3V). DS70293E-page 320 © 2011 Microchip Technology Inc. PIC24HJ32GP302/304, PIC24HJ64GPX02/X04 AND PIC24HJ128GPX02/X04 TABLE 28-41: ADC MODULE SPECIFICATIONS (10-BIT MODE) AC CHARACTERISTICS Standard Operating Conditions: 3.0V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Characteristic Min. Typ Max. Units Conditions Param No. AD20b AD21b AD22b AD23b AD24b AD25b AD20b AD21b AD22b AD23b AD24b AD25b AD30b AD31b AD32b AD33b AD34b Note 1: Symbol ADC Accuracy (10-bit Mode) – Measurements with external VREF+/VREFNr INL DNL GERR EOFF — Nr INL DNL GERR EOFF — THD SINAD SFDR FNYQ ENOB Resolution(1) Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity Resolution(1) Integral Nonlinearity Differential Nonlinearity Gain Error Offset Error Monotonicity Total Harmonic Distortion Signal to Noise and Distortion Spurious Free Dynamic Range Input Signal Bandwidth Effective Number of Bits -1 > -1 3 1.5 — — 57 72 — 9.16 -1.5 > -1 — — — 10 data bits — — 3 2 — 10 data bits — — 7 3 — — 58.5 — — 9.4 +1