PIC24HJXXXGPX08A

PIC24HJXXXGPX06A/X08A/X10A Data Sheet High-Performance, 16-Bit Microcontrollers © 2009 Microchip Technology Inc. Preliminary DS70592A Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, rfPIC, SmartShunt and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, nanoWatt XLP, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70592A-page ii Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A High-Performance, 16-Bit Microcontrollers Operating Range: • Up to 40 MIPS operation (at 3.0-3.6V): - Industrial temperature range (-40°C to +85°C) - Extended temperature range (-40°C to +125°C) On-Chip Flash and SRAM: • Flash program memory, up to 256 Kbytes • Data SRAM, up to 16 Kbytes (includes 2 Kbytes of DMA RAM) System Management: • Flexible clock options: - External, crystal, resonator, internal RC - Fully integrated PLL - Extremely low jitter PLL • Power-up Timer • Oscillator Start-up Timer/Stabilizer • Watchdog Timer with its own RC oscillator • Fail-Safe Clock Monitor • Reset by multiple sources High-Performance CPU: • • • • • • • • • • • • • Modified Harvard architecture C compiler optimized instruction set 16-bit wide data path 24-bit wide instructions Linear program memory addressing up to 4M instruction words Linear data memory addressing up to 64 Kbytes 71 base instructions: mostly 1 word/1 cycle Sixteen 16-bit General Purpose Registers Flexible and powerful Indirect Addressing modes Software stack 16 x 16 multiply operations 32/16 and 16/16 divide operations Up to ±16-bit data shifts Power Management: • On-chip 2.5V voltage regulator • Switch between clock sources in real time • Idle, Sleep and Doze modes with fast wake-up Direct Memory Access (DMA): • 8-channel hardware DMA • 2 Kbytes dual ported DMA buffer area (DMA RAM) to store data transferred via DMA: - Allows data transfer between RAM and a peripheral while CPU is executing code (no cycle stealing) • Most peripherals support DMA Timers/Capture/Compare/PWM: • Timer/Counters, up to nine 16-bit timers: - Can pair up to make four 32-bit timers - One timer runs as Real-Time Clock with external 32.768 kHz oscillator - Programmable prescaler • Input Capture (up to eight channels): - Capture on up, down or both edges - 16-bit capture input functions - 4-deep FIFO on each capture • Output Compare (up to eight channels): - Single or Dual 16-Bit Compare mode - 16-bit Glitchless PWM mode Interrupt Controller: • • • • • • • • • • 5-cycle latency Up to 61 available interrupt sources Up to five external interrupts Seven programmable priority levels FIve processor exceptions Up to 85 programmable digital I/O pins Wake-up/Interrupt-on-Change on up to 24 pins Output pins can drive from 3.0V to 3.6V All digital input pins are 5V tolerant 4 mA sink on all I/O pins Digital I/O: © 2009 Microchip Technology Inc. Preliminary DS70592A-page 1 PIC24HJXXXGPX06A/X08A/X10A Communication Modules: • 3-wire SPI (up to two modules): - Framing supports I/O interface to simple codecs - Supports 8-bit and 16-bit data - Supports all serial clock formats and sampling modes • I2C™ (up to two modules): - Full Multi-Master Slave mode support - 7-bit and 10-bit addressing - Bus collision detection and arbitration - Integrated signal conditioning - Slave address masking • UART (up to two modules): - Interrupt on address bit detect - Interrupt on UART error - Wake-up on Start bit from Sleep mode - 4-character TX and RX FIFO buffers - LIN bus support - IrDA® encoding and decoding in hardware - High-Speed Baud mode - Hardware Flow Control with CTS and RTS • Enhanced CAN (ECAN™ module) 2.0B active (up to two modules): - Up to eight transmit and up to 32 receive buffers - 16 receive filters and 3 masks - Loopback, Listen Only and Listen All Messages modes for diagnostics and bus monitoring - Wake-up on CAN message - Automatic processing of Remote Transmission Requests - FIFO mode using DMA - DeviceNet™ addressing support Analog-to-Digital Converters: • Up to two Analog-to-Digital Converter (ADC) modules in a device • 10-bit, 1.1 Msps or 12-bit, 500 ksps conversion: - Two, four, or eight simultaneous samples - Up to 32 input channels with auto-scanning - Conversion start can be manual or synchronized with one of four trigger sources - Conversion possible in Sleep mode - ±1 LSb max integral nonlinearity - ±1 LSb max differential nonlinearity CMOS Flash Technology: • • • • • Low-power, high-speed Flash technology Fully static design 3.3V (±10%) operating voltage Industrial and extended temperature Low-power consumption Packaging: • 100-pin TQFP (14x14x1 mm and 12x12x1 mm) • 64-pin TQFP (10x10x1 mm) • 64-pin QFN (9x9x0.9 mm) Note: See the device variant tables for exact peripheral features per device. DS70592A-page 2 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A PIC24H PRODUCT FAMILIES The PIC24H Family of devices is ideal for a wide variety of 16-bit MCU embedded applications. The device names, pin counts, memory sizes and peripheral availability of each device are listed below, followed by their pinout diagrams. PIC24H Family Controllers Output Compare Std. PWM I/O Pins (Max)(2) DMA Channels Input Capture Timer 16-bit RAM(1) (KB) Program Flash Memory (KB) Packages PT, MR PF, PT PT, MR PF, PT PT, MR PF, PT PT, MR PF, PT PT, MR PF, PT PT, MR PF, PT PF, PT Codec Interface UART ADC I2C™ 1 2 2 2 2 2 2 2 2 2 2 2 2 CAN 0 0 1 1 0 0 1 1 0 0 0 0 2 Device Pins PIC24HJ64GP206A PIC24HJ64GP210A PIC24HJ64GP506A PIC24HJ64GP510A PIC24HJ128GP206A 64 100 64 100 64 64 64 64 64 128 128 128 128 128 128 256 256 256 8 8 8 8 8 8 8 8 16 16 16 16 16 8 8 8 8 8 8 8 8 8 8 8 8 8 9 9 9 9 9 9 9 9 9 9 9 9 9 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 ADC, 18 ch 1 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 1 ADC, 18 ch 1 ADC, 32 ch 2 ADC, 32 ch 2 2 2 2 2 2 2 2 2 2 2 2 2 SPI 2 2 2 2 2 2 2 2 2 2 2 2 2 53 85 53 85 53 85 53 85 53 85 53 85 85 PIC24HJ128GP210A 100 PIC24HJ128GP506A 64 PIC24HJ128GP510A 100 PIC24HJ128GP306A 64 PIC24HJ128GP310A 100 PIC24HJ256GP206A 64 PIC24HJ256GP210A 100 PIC24HJ256GP610A 100 Note 1: 2: RAM size is inclusive of 2 Kbytes DMA RAM. Maximum I/O pin count includes pins shared by the peripheral functions. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 3 PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP206A(2) PIC24HJ128GP206A PIC24HJ256GP206A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. 2: The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins. DS70592A-page 4 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ128GP306A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 5 PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin QFN(1) RG13 RG12 RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP506A PIC24HJ128GP506A 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 Note 1: The metal plane at the bottom of the device is not connected to any pins and should be connected to VSS externally. DS70592A-page 6 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP206A PIC24HJ128GP206A PIC24HJ256GP206A PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 Note: The PIC24HJ64GP206A device does not have the SCL2 and SDA2 pins. © 2009 Microchip Technology Inc. PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70592A-page 7 PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP RG13 RG12 RG14 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ128GP306A PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS70592A-page 8 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 64-Pin TQFP RG13 RG12 RG14 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/IC6/CN14/RD5 OC5/IC5/CN13/RD4 OC4/RD3 OC3/RD2 OC2/RD1 = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 RG15 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD AN5/IC8/CN7/RB5 AN4/IC7/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/VREF-/CN3/RB1 PGED3/AN0/VREF+/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PIC24HJ64GP506A PIC24HJ128GP506A PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/T4CK/CN1/RC13 OC1/RD0 IC4/INT4/RD11 IC3/INT3/RD10 IC2/U1CTS/INT2/RD9 IC1/INT1/RD8 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD SCL1/RG2 SDA1/RG3 U1RTS/SCK1/INT0/RF6 U1RX/SDI1/RF2 U1TX/SDO1/RF3 © 2009 Microchip Technology Inc. PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 AVDD AVSS U2CTS/AN8/RB8 AN9/RB9 TMS/AN10/RB10 TDO/AN11/RB11 VSS VDD TCK/AN12/RB12 TDI/AN13/RB13 U2RTS/AN14/RB14 AN15/OCFB/CN12/RB15 U2RX/SDA2/CN17/RF4 U2TX/SCL2/CN18/RF5 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Preliminary DS70592A-page 9 PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 RF1 RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 VSS PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PIC24HJ64GP210A PIC24HJ128GP210A PIC24HJ128GP310A PIC24HJ256GP210A 63 62 61 60 59 58 57 56 55 54 53 52 51 PGEC1/AN6/OCFA/RB6 26 PGED1PGED1/AN7/RB7 27 VREF-/RA9 28 VREF+/RA10 29 30 AVDD 31 AVSS 32 AN8/RB8 33 AN9/RB9 34 AN10/RB10 35 AN11/RB11 36 VSS VDD 37 38 TCK/RA1 U2RTS/RF13 39 40 U2CTS/RF12 41 AN12/RB12 42 AN13/RB13 43 AN14/RB14 44 AN15/OCFB/CN12/RB15 45 VSS 46 VDD 47 IC7/U1CTS/CN20/RD14 48 IC8/U1RTS/CN21/RD15 49 U2RX/CN17/RF4 50 U2TX/CN18/RF5 DS70592A-page 10 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 RG0 RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PIC24HJ64GP510A PIC24HJ128GP510A 63 62 61 60 59 58 57 56 55 54 53 52 51 © 2009 Microchip Technology Inc. PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Preliminary DS70592A-page 11 PIC24HJXXXGPX06A/X08A/X10A Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 AN28/RE4 AN27/RE3 AN26/RE2 RG13 RG12 RG14 AN25/RE1 AN24/RE0 AN23/CN23/RA7 AN22/CN22/RA6 C2RX/RG0 C2TX/RG1 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE OC8/CN16/RD7 OC7/CN15/RD6 OC6/CN14/RD5 OC5/CN13/RD4 IC6/CN19/RD13 IC5/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD AN29/RE5 AN30/RE6 AN31/RE7 AN16/T2CK/T7CK/RC1 AN17/T3CK/T6CK/RC2 AN18/T4CK/T9CK/RC3 AN19/T5CK/T8CK/RC4 SCK2/CN8/RG6 SDI2/CN9/RG7 SDO2/CN10/RG8 MCLR SS2/CN11/RG9 VSS VDD TMS/RA0 AN20/INT1/RA12 AN21/INT2/RA13 AN5/CN7/RB5 AN4/CN6/RB4 AN3/CN5/RB3 AN2/SS1/CN4/RB2 PGEC3/AN1/CN3/RB1 PGED3/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VSS PGEC2/SOSCO/T1CK/CN0/RC14 PGED2/SOSCI/CN1/RC13 OC1/RD0 IC4/RD11 IC3/RD10 IC2/RD9 IC1/RD8 INT4/RA15 INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKIN/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 SCL1/RG2 SDA1/RG3 SCK1/INT0/RF6 SDI1/RF7 SDO1/RF8 U1RX/RF2 U1TX/RF3 PIC24HJ256GP610A 64 63 62 61 60 59 58 57 56 55 54 53 52 51 PGEC1/AN6/OCFA/RB6 PGED1/AN7/RB7 VREF-/RA9 VREF+/RA10 AVDD AVSS AN8/RB8 AN9/RB9 AN10/RB10 AN11/RB11 VSS VDD TCK/RA1 U2RTS/RF13 U2CTS/RF12 AN12/RB12 AN13/RB13 AN14/RB14 AN15/OCFB/CN12/RB15 VSS VDD IC7/U1CTS/CN20/RD14 IC8/U1RTS/CN21/RD15 U2RX/CN17/RF4 U2TX/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS70592A-page 12 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A Table of Contents PIC24H Product Families....................................................................................................................................................................... 3 1.0 Device Overview ........................................................................................................................................................................ 15 2.0 Guidelines for Getting Started with 16-Bit Microcontrollers........................................................................................................ 19 3.0 CPU............................................................................................................................................................................................ 23 4.0 Memory Organization ................................................................................................................................................................. 29 5.0 Flash Program Memory.............................................................................................................................................................. 59 6.0 Reset ......................................................................................................................................................................................... 65 7.0 Interrupt Controller ..................................................................................................................................................................... 71 8.0 Direct Memory Access (DMA) .................................................................................................................................................. 115 9.0 Oscillator Configuration ............................................................................................................................................................ 125 10.0 Power-Saving Features............................................................................................................................................................ 135 11.0 I/O Ports ................................................................................................................................................................................... 143 12.0 Timer1 ...................................................................................................................................................................................... 145 13.0 Timer2/3, Timer4/5, Timer6/7 and Timer8/9 ............................................................................................................................ 147 14.0 Input Capture............................................................................................................................................................................ 153 15.0 Output Compare....................................................................................................................................................................... 155 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 159 17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 165 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 173 19.0 Enhanced CAN (ECAN™) Module........................................................................................................................................... 179 20.0 10-Bit/12-Bit Analog-to-Digital Converter (ADC) ...................................................................................................................... 205 21.0 Special Features ...................................................................................................................................................................... 217 22.0 Instruction Set Summary .......................................................................................................................................................... 225 23.0 Development Support............................................................................................................................................................... 233 24.0 Electrical Characteristics .......................................................................................................................................................... 237 25.0 Packaging Information.............................................................................................................................................................. 273 Appendix A: Migrating from PIC24HJXXXGPX06/X08/X10 Devices to PIC24HJXXXGPX06A/X08A/X10A Devices ....................... 283 Appendix B: Revision History............................................................................................................................................................. 284 Index ................................................................................................................................................................................................. 285 The Microchip Web Site ..................................................................................................................................................................... 289 Customer Change Notification Service .............................................................................................................................................. 289 Customer Support .............................................................................................................................................................................. 289 Reader Response .............................................................................................................................................................................. 290 Product Identification System ............................................................................................................................................................ 291 © 2009 Microchip Technology Inc. Preliminary DS70592A-page 13 PIC24HJXXXGPX06A/X08A/X10A TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS70592A-page 14 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 1.0 Note: DEVICE OVERVIEW This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the latest family reference sections of the “PIC24H Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). This makes these families suitable for a wide variety of high-performance digital signal control applications. The devices are pin compatible with the dsPIC33F family of devices, and also share a very high degree of compatibility with the dsPIC30F family devices. This allows easy migration between device families as may be necessitated by the specific functionality, computational resource and system cost requirements of the application. The PIC24HJXXXGPX06A/X08A/X10A device family employs a powerful 16-bit architecture, ideal for applications that rely on high-speed, repetitive computations, as well as control. The 17 x 17 multiplier, hardware support for division operations, multi-bit data shifter, a large array of 16-bit working registers and a wide variety of data addressing modes, together provide the PIC24HJXXXGPX06A/X08A/X10A Central Processing Unit (CPU) with extensive mathematical processing capability. Flexible and deterministic interrupt handling, coupled with a powerful array of peripherals, renders the PIC24HJXXXGPX06A/X08A/X10A devices suitable for control applications. Further, Direct Memory Access (DMA) enables overhead-free transfer of data between several peripherals and a dedicated DMA RAM. Reliable, field programmable Flash program memory ensures scalability of applications that use PIC24HJXXXGPX06A/X08A/X10A devices. Figure 1-1 shows a general block diagram of the various core and peripheral modules in the PIC24HJXXXGPX06A/X08A/X10A family of devices, while Table 1-1 lists the functions of the various pins shown in the pinout diagrams. This document contains device specific information for the following devices: • • • • • • • • • • • • • PIC24HJ64GP206A PIC24HJ64GP210A PIC24HJ64GP506A PIC24HJ64GP510A PIC24HJ128GP206A PIC24HJ128GP210A PIC24HJ128GP506A PIC24HJ128GP510A PIC24HJ128GP306A PIC24HJ128GP310A PIC24HJ256GP206A PIC24HJ256GP210A PIC24HJ256GP610A The PIC24HJXXXGPX06A/X08A/X10A device family includes devices with different pin counts (64 and 100 pins), different program memory sizes (64 Kbytes, 128 Kbytes and 256 Kbytes) and different RAM sizes (8 Kbytes and 16 Kbytes). © 2009 Microchip Technology Inc. Preliminary DS70592A-page 15 PIC24HJXXXGPX06A/X08A/X10A FIGURE 1-1: PSV and Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic X RAM Address Latch DMA 16 Address Generator Units Controller 16 PORTB PIC24HJXXXGPX06A/X08A/X10A GENERAL BLOCK DIAGRAM Data Bus 16 DMA Data Latch RAM PORTA 16 16 23 PORTC Address Latch Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data PORTD 16 Instruction Decode and Control Control Signals to Various Blocks OSC2/CLKO OSC1/CLKI Timing Generation FRC/LPRC Oscillators Precision Band Gap Reference Voltage Regulator Power-up Timer Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset Instruction Reg 16 PORTE 17 x 17 Multiplier 16 x 16 W Register Array 16 PORTF Divide Support 16-bit ALU 16 PORTG VCAP/VDDCORE VDD, VSS MCLR Timers 1-9 ADC1,2 ECAN1,2 UART1,2 IC1-8 OC/ PWM1-8 CN1-23 SPI1,2 I2C1,2 Note: Not all pins or features are implemented on all device pinout configurations. See pinout diagrams for the specific pins and features present on each device. DS70592A-page 16 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A TABLE 1-1: Pin Name AN0-AN31 AVDD AVSS CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Type I P P I O Buffer Type Analog P P Analog input channels. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Description ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST ST — ST — ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — Input change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. ECAN1 bus receive pin. ECAN1 bus transmit pin. ECAN2 bus receive pin. ECAN2 bus transmit pin. Data I/O pin for programming/debugging communication channel 1. Clock input pin for programming/debugging communication channel 1. Data I/O pin for programming/debugging communication channel 2. Clock input pin for programming/debugging communication channel 2. Data I/O pin for programming/debugging communication channel 3. Clock input pin for programming/debugging communication channel 3. Capture inputs 1 through 8. External interrupt 0. External interrupt 1. External interrupt 2. External interrupt 3. External interrupt 4. Master Clear (Reset) input. This pin is an active-low Reset to the device. Compare Fault A input (for Compare Channels 1, 2, 3 and 4). Compare Fault B input (for Compare Channels 5, 6, 7 and 8). Compare outputs 1 through 8. CN0-CN23 C1RX C1TX C2RX C2TX PGED1 PGEC1 PGED2 PGEC2 PGED3 PGEC3 IC1-IC8 INT0 INT1 INT2 INT3 INT4 MCLR OCFA OCFB OC1-OC8 OSC1 OSC2 RA0-RA7 RA9-RA10 RA12-RA15 RB0-RB15 RC1-RC4 RC12-RC15 RD0-RD15 RE0-RE7 RF0-RF8 RF12-RF13 RG0-RG3 RG6-RG9 RG12-RG15 I I O I O I/O I I/O I I/O I I I I I I I I/P I I O I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST ST ST ST ST ST ST ST ST ST ST ST PORTA is a bidirectional I/O port. PORTB is a bidirectional I/O port. PORTC is a bidirectional I/O port. PORTD is a bidirectional I/O port. PORTE is a bidirectional I/O port. PORTF is a bidirectional I/O port. PORTG is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels Analog = Analog input O = Output P = Power I = Input © 2009 Microchip Technology Inc. Preliminary DS70592A-page 17 PIC24HJXXXGPX06A/X08A/X10A TABLE 1-1: Pin Name SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 SCL1 SDA1 SCL2 SDA2 SOSCI SOSCO TMS TCK TDI TDO T1CK T2CK T3CK T4CK T5CK T6CK T7CK T8CK T9CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX VDD VCAP/VDDCORE VSS VREF+ VREF- PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Type I/O I O I/O I/O I O I/O I/O I/O I/O I/O I O I I I O I I I I I I I I I I O I O I O I O P P P I I Buffer Type ST ST — ST ST ST — ST ST ST ST ST Description Synchronous serial clock input/output for SPI1. SPI1 data in. SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2. SPI2 data in. SPI2 data out. SPI2 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. — 32.768 kHz low-power oscillator crystal output. ST ST ST — ST ST ST ST ST ST ST ST ST ST — ST — ST — ST — — — — Analog Analog JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. Timer6 external clock input. Timer7 external clock input. Timer8 external clock input. Timer9 external clock input. UART1 clear to send. UART1 ready to send. UART1 receive. UART1 transmit. UART2 clear to send. UART2 ready to send. UART2 receive. UART2 transmit. Positive supply for peripheral logic and I/O pins. CPU logic filter capacitor connection. Ground reference for logic and I/O pins. Analog voltage reference (high) input. Analog voltage reference (low) input. Analog = Analog input O = Output P = Power I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels DS70592A-page 18 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 2.0 GUIDELINES FOR GETTING STARTED WITH 16-BIT MICROCONTROLLERS This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, which is available from the Microchip website (www.microchip.com). 2.2 Decoupling Capacitors Note: The use of decoupling capacitors on every pair of power supply pins, such as VDD, VSS, AVDD and AVSS is required. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: Recommendation of 0.1 µF (100 nF), 10-20V. This capacitor should be a low-ESR and have resonance frequency in the range of 20 MHz and higher. It is recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended to place the capacitors on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. 2.1 Basic Connection Requirements Getting started with the PIC24HJXXXGPX06A/X08A/X10A family of 16-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins (regardless if ADC module is not used) (see Section 2.2 “Decoupling Capacitors”) • VCAP/VDDCORE (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.6 “External Oscillator Pins”) Additionally, the following pins may be required: • VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected independent of the ADC voltage reference source. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 19 PIC24HJXXXGPX06A/X08A/X10A FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. VDD VDD R R1 MCLR C VCAP/VDDCORE PIC24H VSS VDD VDD VSS AVDD AVSS VDD VSS VSS 0.1 µF Ceramic 0.1 µF Ceramic 10 Ω 0.1 µF Ceramic 0.1 µF Ceramic For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.2.1 TANK CAPACITORS FIGURE 2-2: On boards with power traces running longer than six inches in length, it is suggested to use a tank capacitor for integrated circuits including MCUs to supply a local power source. The value of the tank capacitor should be determined based on the trace resistance that connects the power supply source to the device, and the maximum current drawn by the device in the application. In other words, select the tank capacitor so that it meets the acceptable voltage sag at the device. Typical values range from 4.7 µF to 47 µF. EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR PIC24H 2.3 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) Note 1: A low-ESR (< 5 Ohms) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the voltage regulator output voltage. The VCAP/VDDCORE pin must not be connected to VDD, and must have a capacitor between 4.7 µF and 10 µF, 16V connected to ground. The type can be ceramic or tantalum. Refer to Section 24.0 “Electrical Characteristics” for additional information. The placement of this capacitor should be close to the VCAP/VDDCORE. It is recommended that the trace length not exceed one-quarter inch (6 mm). Refer to Section 21.2 “On-Chip Voltage Regulator” for details. R ≤ 10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. 2: DS70592A-page 20 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 2.5 ICSP Pins 2.6 External Oscillator Pins The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes, and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB ICD 3 or MPLAB REAL ICE™. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip website. • “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3 In-Circuit Debugger” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™” (poster) DS51749 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 9.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. FIGURE 2-3: SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT Main Oscillator 13 Guard Ring Guard Trace Secondary Oscillator 14 15 16 17 18 19 20 © 2009 Microchip Technology Inc. Preliminary DS70592A-page 21 PIC24HJXXXGPX06A/X08A/X10A 2.7 Oscillator Value Conditions on Device Start-up If the PLL of the target device is enabled and configured for the device start-up oscillator, the maximum oscillator source frequency must be limited to 4 MHz < FIN < 8 MHz to comply with device PLL start-up conditions. This means that if the external oscillator frequency is outside this range, the application must start-up in the FRC mode first. The default PLL settings after a POR with an oscillator frequency outside this range will violate the device operating speed. Once the device powers up, the application firmware can initialize the PLL SFRs, CLKDIV and PLLDBF to a suitable value, and then perform a clock switch to the Oscillator + PLL clock source. Note that clock switching must be enabled in the device Configuration word. 2.8 Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins, by setting all bits in the AD1PCFGL register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the AD1PCFGL register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the AD1PCFGL register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. 2.9 Unused I/Os Unused I/O pins should be configured as outputs and driven to a logic-low state. Alternatively, connect a 1k to 10k resistor to VSS on unused pins and drive the output to logic low. DS70592A-page 22 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 3.0 Note: CPU This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 2. “CPU” (DS70245), which is available from the Microchip website (www.microchip.com). 3.1 Data Addressing Overview The data space can be linearly addressed as 32K words or 64 Kbytes using an Address Generation Unit (AGU). The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K program word boundary defined by the 8-bit Program Space Visibility Page (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The data space also includes 2 Kbytes of DMA RAM, which is primarily used for DMA data transfers, but may be used as general purpose RAM. The PIC24HJXXXGPX06A/X08A/X10A CPU module has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and addressing modes. The CPU has a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M x 24 bits of user program memory space. The actual amount of program memory implemented varies by device. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double word move (MOV.D) instruction and the table instructions. Overhead-free, single-cycle program loop constructs are supported using the REPEAT instruction, which is interruptible at any point. The PIC24HJXXXGPX06A/X08A/X10A devices have sixteen, 16-bit working registers in the programmer’s model. Each of the working registers can serve as a data, address or address offset register. The 16th working register (W15) operates as a software Stack Pointer (SP) for interrupts and calls. The PIC24HJXXXGPX06A/X08A/X10A instruction set includes many addressing modes and is designed for optimum C compiler efficiency. For most instructions, the PIC24HJXXXGPX06A/X08A/X10A is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing A + B = C operations to be executed in a single cycle. A block diagram of the CPU is shown in Figure 3-1, and the programmer’s model for the PIC24HJXXXGPX06A/X08A/X10A is shown in Figure 3-2. 3.2 Special MCU Features The PIC24HJXXXGPX06A/X08A/X10A features a 17-bit by 17-bit, single-cycle multiplier. The multiplier can perform signed, unsigned and mixed-sign multiplication. Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit multiplication makes mixed-sign multiplication possible. The PIC24HJXXXGPX06A/X08A/X10A supports 16/16 and 32/16 integer divide operations. All divide instructions are iterative operations. They must be executed within a REPEAT loop, resulting in a total execution time of 19 instruction cycles. The divide operation can be interrupted during any of those 19 cycles without loss of data. A multi-bit data shifter is used to perform up to a 16-bit, left or right shift in a single cycle. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 23 PIC24HJXXXGPX06A/X08A/X10A FIGURE 3-1: PSV and Table Data Access Control Block Interrupt Controller 8 23 23 PCU PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 X Data Bus PIC24HJXXXGPX06A/X08A/X10A CPU CORE BLOCK DIAGRAM 16 16 Data Latch X RAM Address Latch DMA RAM 16 23 16 Address Latch Address Generator Units DMA Controller Program Memory EA MUX Data Latch 24 ROM Latch 16 Literal Data 16 Instruction Decode and Control Instruction Reg 17 x 17 Multiplier 16 Control Signals to Various Blocks Divide Support 16 x 16 W Register Array 16 16-bit ALU 16 To Peripheral Modules DS70592A-page 24 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A FIGURE 3-2: PIC24HJXXXGPX06A/X08A/X10A PROGRAMMER’S MODEL D15 W0/WREG W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14/Frame Pointer W15/Stack Pointer SPLIM Stack Pointer Limit Register Working Registers DO Shadow D0 PUSH.S Shadow Legend PC22 7 TBLPAG 7 PSVPAG 0 0 Data Table Page Address PC0 0 Program Counter Program Space Visibility Page Address 15 RCOUNT 0 REPEAT Loop Counter 15 CORCON 0 Core Configuration Register — — — — — — — DC IPL2 IPL1 IPL0 RA SRL N OV Z C STATUS Register SRH 3.3 CPU Control Registers © 2009 Microchip Technology Inc. Preliminary DS70592A-page 25 PIC24HJXXXGPX06A/X08A/X10A REGISTER 3-1: U-0 — bit 15 R/W-0(1) bit 7 Legend: C = Clear only bit S = Set only bit ‘1’ = Bit is set bit 15-9 bit 8 R = Readable bit W = Writable bit ‘0’ = Bit is cleared Unimplemented: Read as ‘0’ DC: MCU ALU Half Carry/Borrow bit 1 = A carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred 0 = No carry-out from the 4th low-order bit (for byte sized data) or 8th low-order bit (for word sized data) of the result occurred IPL: CPU Interrupt Priority Level Status bits(2) 111 = CPU Interrupt Priority Level is 7 (15), user interrupts disabled 110 = CPU Interrupt Priority Level is 6 (14) 101 = CPU Interrupt Priority Level is 5 (13) 100 = CPU Interrupt Priority Level is 4 (12) 011 = CPU Interrupt Priority Level is 3 (11) 010 = CPU Interrupt Priority Level is 2 (10) 001 = CPU Interrupt Priority Level is 1 (9) 000 = CPU Interrupt Priority Level is 0 (8) RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress N: MCU ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) OV: MCU ALU Overflow bit This bit is used for signed arithmetic (2’s complement). It indicates an overflow of the magnitude which causes the sign bit to change state. 1 = Overflow occurred for signed arithmetic (in this arithmetic operation) 0 = No overflow occurred Z: MCU ALU Zero bit 1 = An operation which affects the Z bit has set it at some time in the past 0 = The most recent operation which affects the Z bit has cleared it (i.e., a non-zero result) C: MCU ALU Carry/Borrow bit 1 = A carry-out from the Most Significant bit (MSb) of the result occurred 0 = No carry-out from the Most Significant bit of the result occurred U = Unimplemented bit, read as ‘0’ -n = Value at POR x = Bit is unknown R/W-0(2) IPL(2) R/W-0(2) R-0 RA R/W-0 N R/W-0 OV R/W-0 Z SR: CPU STATUS REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 DC bit 8 R/W-0 C bit 0 bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: The IPL bits are concatenated with the IPL bit (CORCON) to form the CPU Interrupt Priority Level. The value in parentheses indicates the IPL if IPL = 1. User interrupts are disabled when IPL = 1. 2: The IPL Status bits are read only when NSTDIS = 1 (INTCON1). DS70592A-page 26 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A REGISTER 3-2: U-0 — bit 15 U-0 — bit 7 Legend: R = Readable bit 0’ = Bit is cleared bit 15-4 bit 3 C = Clear only bit W = Writable bit ‘x = Bit is unknown CORCON: CORE CONTROL REGISTER U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 U-0 — U-0 — U-0 — R/C-0 IPL3(1) R/W-0 PSV U-0 — U-0 — bit 0 -n = Value at POR ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ bit 2 bit 1-0 Unimplemented: Read as ‘0’ IPL3: CPU Interrupt Priority Level Status bit 3(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space Unimplemented: Read as ‘0’ Note 1: The IPL3 bit is concatenated with the IPL bits (SR) to form the CPU interrupt priority level. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 27 PIC24HJXXXGPX06A/X08A/X10A 3.4 Arithmetic Logic Unit (ALU) 3.4.2 DIVIDER The PIC24HJXXXGPX06A/X08A/X10A ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2’s complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. Refer to the “dsPIC30F/33F Programmer’s Reference Manual” (DS70157) for information on the SR bits affected by each instruction. The PIC24HJXXXGPX06A/X08A/X10A CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. The divide block supports 32-bit/16-bit and 16-bit/16-bit signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn) and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. 3.4.3 MULTI-BIT DATA SHIFTER The multi-bit data shifter is capable of performing up to 16-bit arithmetic or logic right shifts, or up to 16-bit left shifts in a single cycle. The source can be either a working register or a memory location. The shifter requires a signed binary value to determine both the magnitude (number of bits) and direction of the shift operation. A positive value shifts the operand right. A negative value shifts the operand left. A value of ‘0’ does not modify the operand. 3.4.1 MULTIPLIER Using the high-speed 17-bit x 17-bit multiplier, the ALU supports unsigned, signed or mixed-sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS70592A-page 28 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 3. “Data Memory” (DS70237), which is available from the Microchip website (www.microchip.com). 4.1 Program Address Space The program address memory space of the PIC24HJXXXGPX06A/X08A/X10A devices is 4M instructions. The space is addressable by a 24-bit value derived from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping as described in Section 4.4 “Interfacing Program and Data Memory Spaces”. User access to the program memory space is restricted to the lower half of the address range (0x000000 to 0x7FFFFF). The exception is the use of TBLRD/TBLWT operations, which use TBLPAG to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24HJXXXGPX06A/X08A/ X10A family of devices are shown in Figure 4-1. The PIC24HJXXXGPX06A/X08A/X10A architecture features separate program and data memory spaces and buses. This architecture also allows the direct access of program memory from the data space during code execution. FIGURE 4-1: PROGRAM MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A FAMILY DEVICES PIC24HJ64XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ128XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table PIC24HJ256XXXXXA GOTO Instruction Reset Address Interrupt Vector Table Reserved Alternate Vector Table 0x000000 0x000002 0x000004 0x0000FE 0x000100 0x000104 0x0001FE 0x000200 User Memory Space User Program Flash Memory (22K instructions) User Program Flash Memory (44K instructions) User Program Flash Memory (88K instructions) 0x00ABFE 0x00AC00 0x0157FE 0x015800 Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) Unimplemented (Read ‘0’s) 0x7FFFFE 0x800000 0x02ABFE 0x02AC00 Reserved Configuration Memory Space Reserved Reserved Device Configuration Registers Device Configuration Registers Device Configuration Registers 0xF7FFFE 0xF80000 0xF80017 0xF80010 Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) 0xFEFFFE 0xFF0000 0xFFFFFE © 2009 Microchip Technology Inc. Preliminary DS70592A-page 29 PIC24HJXXXGPX06A/X08A/X10A 4.1.1 PROGRAM MEMORY ORGANIZATION 4.1.2 INTERRUPT AND TRAP VECTORS The program memory space is organized in wordaddressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 4-2). Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. All PIC24HJXXXGPX06A/X08A/X10A devices reserve the addresses between 0x00000 and 0x000200 for hard-coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 0x000000, with the actual address for the start of code at 0x000002. PIC24HJXXXGPX06A/X08A/X10A devices also have two interrupt vector tables, located from 0x000004 to 0x0000FF and 0x000100 to 0x0001FF. These vector tables allow each of the many device interrupt sources to be handled by separate Interrupt Service Routines (ISRs). A more detailed discussion of the interrupt vector tables is provided in Section 7.1 “Interrupt Vector Table”. FIGURE 4-2: msw Address 0x000001 0x000003 0x000005 0x000007 PROGRAM MEMORY ORGANIZATION most significant word 23 00000000 00000000 00000000 00000000 Program Memory ‘Phantom’ Byte (read as ‘0’) Instruction Width 16 least significant word 8 0 0x000000 0x000002 0x000004 0x000006 PC Address (lsw Address) DS70592A-page 30 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 4.2 Data Address Space The PIC24HJXXXGPX06A/X08A/X10A CPU has a separate 16-bit wide data memory space. The data space is accessed using separate Address Generation Units (AGUs) for read and write operations. Data memory maps of devices with different RAM sizes are shown in Figure 4-3 and Figure 4-4. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This arrangement gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA = 0) is used for implemented memory addresses, while the upper half (EA = 1) is reserved for the Program Space Visibility area (see Section 4.4.3 “Reading Data from Program Memory Using Program Space Visibility”). PIC24HJXXXGPX06A/X08A/X10A devices implement up to 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all-zero word or byte will be returned. All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap is generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write does not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte (MSB) is not modified. A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the Most Significant Byte of any W register by executing a zero-extend (ZE) instruction on the appropriate address. 4.2.1 DATA SPACE WIDTH 4.2.3 SFR SPACE The data memory space is organized in byte addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. The first 2 Kbytes of the Near Data Space, from 0x0000 to 0x07FF, is primarily occupied by Special Function Registers (SFRs). These are used by the PIC24HJXXXGPX06A/X08A/X10A core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control, and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as ‘0’. A complete listing of implemented SFRs, including their addresses, is shown in Table 4-1 through Table 4-33. Note: The actual set of peripheral features and interrupts varies by the device. Please refer to the corresponding device tables and pinout diagrams for device-specific information. 4.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT To maintain backward compatibility with PIC® MCU devices and improve data space memory usage efficiency, the PIC24HJXXXGPX06A/X08A/X10A instruction set supports both word and byte operations. As a consequence of byte accessibility, all effective address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Data byte reads will read the complete word that contains the byte, using the Least Significant bit (LSb) of any EA to determine which byte to select. The selected byte is placed onto the Least Significant Byte (LSB) of the data path. That is, data memory and registers are organized as two parallel byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 4.2.4 NEAR DATA SPACE The 8-Kbyte area between 0x0000 and 0x1FFF is referred to as the Near Data Space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing mode with a 16-bit address field, or by using Indirect Addressing mode using a working register as an Address Pointer. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 31 PIC24HJXXXGPX06A/X08A/X10A FIGURE 4-3: DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 8 KBS RAM MSB Address MSB 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 0x07FE 0x0800 8 Kbyte Near Data Space LSB Address LSB 0x0000 16 bits 8 Kbyte SRAM Space 0x1FFF 0x2001 0x27FF 0x2801 X Data RAM (X) 0x1FFE 0x2000 DMA RAM 0x27FE 0x2800 0x8001 0x8000 Optionally Mapped into Program Memory X Data Unimplemented (X) 0xFFFF 0xFFFE DS70592A-page 32 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A FIGURE 4-4: DATA MEMORY MAP FOR PIC24HJXXXGPX06A/X08A/X10A DEVICES WITH 16 KBS RAM MSB Address MSB 2 Kbyte SFR Space 0x0001 SFR Space 0x07FF 0x0801 LSB Address LSB 0x0000 0x07FE 0x0800 8 Kbyte Near Data Space 16 bits 0x1FFF X Data RAM (X) 16 Kbyte SRAM Space 0x3FFF 0x4001 0x47FF 0x4801 DMA RAM 0x1FFE 0x3FFE 0x4000 0x47FE 0x4800 0x8001 0x8000 X Data Unimplemented (X) Optionally Mapped into Program Memory 0xFFFF 0xFFFE 4.2.5 DMA RAM Every PIC24HJXXXGPX06A/X08A/X10A device contains 2 Kbytes of dual ported DMA RAM located at the end of data space. Memory locations in the DMA RAM space are accessible simultaneously by the CPU and the DMA controller module. DMA RAM is utilized by the DMA controller to store data to be transferred to various peripherals using DMA, as well as data transferred from various peripherals using DMA. The DMA RAM can be accessed by the DMA controller without having to steal cycles from the CPU. When the CPU and the DMA controller attempt to concurrently write to the same DMA RAM location, the hardware ensures that the CPU is given precedence in accessing the DMA RAM location. Therefore, the DMA RAM provides a reliable means of transferring DMA data without ever having to stall the CPU. Note: DMA RAM can be used for general purpose data storage if the DMA function is not required in an application. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 33 DS70592A-page 34 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-1: SFR Name WREG0 WREG1 WREG2 WREG3 WREG4 WREG5 WREG6 WREG7 WREG8 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT SR CORCON DISICNT BSRAM SSRAM SFR Addr 0000 0002 0004 0006 0008 000A 000C 000E 0010 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 0042 0044 0052 0750 0752 CPU CORE REGISTERS MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0800 xxxx 0000 Program Counter High Byte Register Table Page Address Pointer Register Program Memory Visibility Page Address Pointer Register IPL — — — — — — — — — RA — — — N IPL3 — — OV PSV IW_BSR IW_SSR Z — IR_BSR IR_SSR C — RL_BSR RL_SSR 0000 0000 0000 xxxx 0000 0000 xxxx 0000 0000 Working Register 0 Working Register 1 Working Register 2 Working Register 3 Working Register 4 Working Register 5 Working Register 6 Working Register 7 Working Register 8 Working Register 9 Working Register 10 Working Register 11 Working Register 12 Working Register 13 Working Register 14 Working Register 15 Stack Pointer Limit Register Program Counter Low Word Register — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — DC — — — Preliminary © 2009 Microchip Technology Inc. Repeat Loop Counter Register Disable Interrupts Counter Register Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-2: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX10A DEVICES Bit 15 CN15IE — — Bit 14 CN14IE — — Bit 13 CN13IE — — Bit 12 CN12IE — — Bit 11 CN11IE — — Bit 10 CN10IE — — Bit 9 CN9IE — CN9PUE — Bit 8 CN8IE — CN8PUE — Bit 7 CN7IE CN23IE CN7PUE Bit 6 CN6IE CN22IE CN6PUE Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-3: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX08A DEVICES Bit 15 CN15IE — — Bit 14 CN14IE — — Bit 13 CN13IE — — Bit 12 CN12IE — — Bit 11 CN11IE — — Bit 10 CN10IE — — Bit 9 CN9IE — CN9PUE — Bit 8 CN8IE — CN8PUE — Bit 7 CN7IE — CN7PUE — Bit 6 CN6IE — CN6PUE — Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE CN19IE CN3PUE Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 PIC24HJXXXGPX06A/X08A/X10A CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE Preliminary DS70592A-page 35 Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-4: SFR Name CNEN1 CNEN2 CNPU1 CNPU2 Legend: SFR Addr 0060 0062 0068 006A CHANGE NOTIFICATION REGISTER MAP FOR PIC24HJXXXGPX06A DEVICES Bit 15 CN15IE — — Bit 14 CN14IE — — Bit 13 CN13IE — — Bit 12 CN12IE — — Bit 11 CN11IE — — Bit 10 CN10IE — — Bit 9 CN9IE — CN9PUE — Bit 8 CN8IE — CN8PUE — Bit 7 CN7IE — CN7PUE — Bit 6 CN6IE — CN6PUE — Bit 5 CN5IE CN21IE CN5PUE Bit 4 CN4IE CN20IE CN4PUE Bit 3 CN3IE — CN3PUE — Bit 2 CN2IE CN18IE CN2PUE Bit 1 CN1IE CN17IE CN1PUE Bit 0 CN0IE CN16IE CN0PUE All Resets 0000 0000 0000 0000 CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN21PUE CN20PUE CN18PUE CN17PUE CN16PUE x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. DS70592A-page 36 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-5: SFR Name INTCON1 INTCON2 IFS0 IFS1 IFS2 IFS3 IFS4 IEC0 IEC1 IEC2 IEC3 IEC4 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 IPC8 IPC9 IPC10 IPC11 IPC12 IPC13 IPC14 IPC15 IPC16 IPC17 INTTREG Legend: SFR Addr 0080 0082 0084 0086 0088 008A 008C 0094 0096 0098 009A 009C 00A4 00A6 00A8 00AA 00AC 00AE 00B0 00B2 00B4 00B6 00B8 00BA 00BC 00BE 00C0 00C2 00C4 00C6 00E0 INTERRUPT CONTROLLER REGISTER MAP Bit 15 NSTDIS ALTIVT — U2TXIF T6IF — — — U2TXIE T6IE — — — — — — — — — — — — — — — — — — — — — — — — — — Bit 14 — DISI DMA1IF U2RXIF DMA4IF — — DMA1IE U2RXIE DMA4IE — — Bit 13 — — AD1IF INT2IF — DMA5IF — AD1IE INT2IE — DMA5IE — T1IP T2IP U1RXIP — CNIP IC8IP T4IP U2TXIP C1IP IC5IP OC7IP T6IP T8IP C2RXIP — — — C2TXIP — — — — — — Bit 12 — — U1TXIF T5IF OC8IF — — U1TXIE T5IE OC8IE — — Bit 11 — — U1RXIF T4IF OC7IF — — U1RXIE T4IE OC7IE — — — — — — — — — — — — — — — — — — — — — — — Bit 10 — — OC4IF OC6IF — — OC4IE OC6IE — — Bit 9 — — OC3IF OC5IF — — OC3IE OC5IE — — OC1IP OC2IP SPI1IP DMA1IP — IC7IP OC4IP U2RXIP C1RXIP IC4IP OC6IP DMA4IP MI2C2IP INT4IP — — U2EIP C1TXIP ILR — — — Bit 8 — — T3IF DMA2IF IC6IF C2IF — T3IE DMA2IE IC6IE C2IE — Bit 7 — — T2IF IC8IF IC5IF C2RXIF C2TXIF T2IE IC8IE IC5IE C2RXIE C2TXIE — — — — — — — — — — — — — — — — — — — — — Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 OSCFAIL INT1EP IC1IF MI2C1IF SPI2IF SI2C2IF U1EIF IC1IE SPI2IE SI2C2IE U1EIE INT0IP DMA0IP T3IP U1TXIP SI2C1IP INT1IP DMA2IP T5IP SPI2EIP DMA3IP IC6IP OC8IP T7IP T9IP C2IP — — — — DMA6IP — — Bit 0 — INT0EP INT0IF SI2C1IF SPI2EIF T7IF — INT0IE SPI2EIE T7IE — All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 4444 4444 4444 0444 4044 4444 4444 4444 4444 4444 4444 4404 4444 4444 0004 0040 0440 4444 0000 DIV0ERR DMACERR MATHERR ADDRERR STKERR — OC2IF IC7IF IC4IF INT4IF C1TXIF OC2IE IC7IE IC4IE INT4IE C1TXIE — IC2IF AD2IF IC3IF INT3IF DMA7IF IC2IE AD2IE IC3IE INT3IE DMA7IE IC1IP IC2IP SPI1EIP AD1IP MI2C1IP AD2IP OC3IP INT2IP SPI2IP IC3IP OC5IP — SI2C2IP INT3IP — DMA5IP U1EIP DMA7IP — — INT4EP DMA0IF INT1IF DMA3IF T9IF DMA6IF DMA0IE INT1IE DMA3IE T9IE DMA6IE INT3EP T1IF CNIF C1IF T8IF — T1IE CNIE C1IE T8IE — — — — — — — — — — — — — — — — — — — VECNUM INT2EP OC1IF — C1RXIF MI2C2IF U2EIF OC1IE — C1RXIE MI2C2IE U2EIE SPI1IF SPI1EIF SPI1IE SPI1EIE MI2C1IE SI2C1IE Preliminary © 2009 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-6: SFR Name TMR1 PR1 T1CON TMR2 TMR3HLD TMR3 PR2 PR3 T2CON T3CON TMR4 TMR5HLD TMR5 PR4 PR5 T4CON T5CON TMR6 TMR7HLD TMR7 PR6 PR7 T6CON T7CON TMR8 TMR9HLD TMR9 PR8 PR9 T8CON T9CON Legend: SFR Addr 0100 0102 0104 0106 0108 010A 010C 010E 0110 0112 0114 0116 0118 011A 011C 011E 0120 0122 0124 0126 0128 012A 012C 012E 0130 0132 0134 0136 0138 013A 013C TIMER REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx FFFF TGATE TCKPS — TSYNC TCS — 0000 xxxx xxxx xxxx FFFF Timer1 Register Period Register 1 TON — TSIDL — — — — — — Timer2 Register Timer3 Holding Register (for 32-bit timer operations only) Timer3 Register Period Register 2 Period Register 3 TON TON — — TSIDL TSIDL — — — — — — — — — — — — TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — PIC24HJXXXGPX06A/X08A/X10A FFFF 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 xxxx xxxx xxxx FFFF FFFF TGATE TGATE TCKPS TCKPS T32 — — — TCS TCS — — 0000 0000 Timer4 Register Timer5 Holding Register (for 32-bit operations only) Timer5 Register Period Register 4 Period Register 5 TON TON — — TSIDL TSIDL — — — — — — — — — — — — Preliminary DS70592A-page 37 Timer6 Register Timer7 Holding Register (for 32-bit operations only) Timer7 Register Period Register 6 Period Register 7 TON TON — — TSIDL TSIDL — — — — — — — — — — — — Timer8 Register Timer9 Holding Register (for 32-bit operations only) Timer9 Register Period Register 8 Period Register 9 TON TON — — TSIDL TSIDL — — — — — — — — — — — — x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. DS70592A-page 38 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-7: SFR Name IC1BUF IC1CON IC2BUF IC2CON IC3BUF IC3CON IC4BUF IC4CON IC5BUF IC5CON IC6BUF IC6CON IC7BUF IC7CON IC8BUF IC8CON Legend: SFR Addr 0140 0142 0144 0146 0148 014A 014C 014E 0150 0152 0154 0156 0158 015A 015C 015E INPUT CAPTURE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx ICI ICI ICI ICI ICI ICI ICI ICI ICOV ICOV ICOV ICOV ICOV ICOV ICOV ICOV ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICBNE ICM ICM ICM ICM ICM ICM ICM ICM 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 xxxx 0000 Input 1 Capture Register — — — — — — — — — — — — — — — — ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL ICSIDL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR ICTMR Input 2 Capture Register Input 3 Capture Register Input 4 Capture Register Input 5 Capture Register Input 6 Capture Register Input 7 Capture Register Input 8 Capture Register Preliminary © 2009 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-8: SFR Name OC1RS OC1R OC1CON OC2RS OC2R OC2CON OC3RS OC3R OC3CON OC4RS OC4R OC4CON OC5RS OC5R OC5CON OC6RS OC6R OC6CON OC7RS OC7R OC7CON OC8RS OC8R OC8CON Legend: SFR Addr 0180 0182 0184 0186 0188 018A 018C 018E 0190 0192 0194 0196 0198 019A 019C 019E 01A0 01A2 01A4 01A6 01A8 01AA 01AC 01AE OUTPUT COMPARE REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx xxxx — OCFLT OCTSEL OCM 0000 xxxx xxxx — OCFLT OCTSEL OCM 0000 xxxx Output Compare 1 Secondary Register Output Compare 1 Register — — OCSIDL — — — — — — — Output Compare 2 Secondary Register Output Compare 2 Register — — OCSIDL — — — — — — — Output Compare 3 Secondary Register Output Compare 3 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM Output Compare 4 Secondary Register Output Compare 4 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM Output Compare 5 Secondary Register Output Compare 5 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM Output Compare 6 Secondary Register Output Compare 6 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM Output Compare 7 Secondary Register Output Compare 7 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM Output Compare 8 Secondary Register Output Compare 8 Register — — OCSIDL — — — — — — — — OCFLT OCTSEL OCM PIC24HJXXXGPX06A/X08A/X10A xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000 xxxx xxxx 0000 Preliminary DS70592A-page 39 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. DS70592A-page 40 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-9: SFR Name I2C1RCV I2C1TRN I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK Legend: SFR Addr 0200 0202 0204 0206 0208 020A 020C I2C1 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — ACKDT D_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKEN P RCEN S Address Register Address Mask Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-10: SFR Name I2C2RCV SFR Addr 0210 0212 0214 0216 0218 021A 021C I2C2 REGISTER MAP Bit 15 — — — I2CEN ACKSTAT — — Bit 14 — — — — TRSTAT — — Bit 13 — — — I2CSIDL — — — Bit 12 — — — SCLREL — — — Bit 11 — — — IPMIEN — — — Bit 10 — — — A10M BCL — — Bit 9 — — — DISSLW GCSTAT SMEN ADD10 GCEN IWCOL STREN I2COV Bit 8 — — ACKDT D_A Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 00FF 0000 PEN R_W RSEN RBF SEN TBF 1000 0000 0000 0000 Receive Register Transmit Register Baud Rate Generator Register ACKEN P RCEN S Preliminary © 2009 Microchip Technology Inc. I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK Legend: Address Register Address Mask Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-11: SFR Name U1MODE U1STA U1TXREG U1RXREG U1BRG Legend: SFR Addr 0220 0222 0224 0226 0228 UART1 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — UTXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR URXISEL UART Transmit Register UART Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-12: SFR Name U2MODE U2STA U2TXREG U2RXREG U2BRG Legend: SFR Addr 0230 0232 0234 0236 0238 UART2 REGISTER MAP Bit 15 UARTEN UTXISEL1 — — Bit 14 — UTXINV — — Bit 13 USIDL UTXISEL0 — — Bit 12 IREN — — — Bit 11 RTSMD UTXBRK — — Bit 10 — UTXEN — — Bit 9 UEN1 UTXBF — — Baud Rate Generator Prescaler Bit 8 UEN0 TRMT Bit 7 WAKE Bit 6 LPBACK Bit 5 ABAUD ADDEN Bit 4 URXINV RIDLE Bit 3 BRGH PERR Bit 2 Bit 1 Bit 0 STSEL URXDA All Resets 0000 0110 xxxx 0000 0000 PDSEL FERR OERR URXISEL UART Transmit Register UART Receive Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. PIC24HJXXXGPX06A/X08A/X10A TABLE 4-13: SFR Name SPI1STAT SPI1CON1 SPI1CON2 SFR Addr 0240 0242 0244 0248 SPI1 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF FRMDLY Bit 0 SPIRBF — All Resets 0000 0000 0000 0000 PPRE Preliminary DS70592A-page 41 SPI1BUF Legend: SPI1 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-14: SFR Name SPI2STAT SPI2CON1 SPI2CON2 SPI2BUF Legend: SFR Addr 0260 0262 0264 0268 SPI2 REGISTER MAP Bit 15 SPIEN — FRMEN Bit 14 — — SPIFSD Bit 13 SPISIDL — FRMPOL Bit 12 — DISSCK — Bit 11 — DISSDO — Bit 10 — MODE16 — Bit 9 — SMP — Bit 8 — CKE — Bit 7 — SSEN — Bit 6 SPIROV CKP — Bit 5 — MSTEN — — Bit 4 — Bit 3 — SPRE — — Bit 2 — Bit 1 SPITBF FRMDLY Bit 0 SPIRBF — All Resets 0000 0000 0000 0000 PPRE SPI2 Transmit and Receive Buffer Register x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. DS70592A-page 42 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-15: File Name ADC1BUF0 AD1CON1 AD1CON2 AD1CON3 AD1CHS123 AD1CHS0 AD1PCFGH(1) AD1PCFGL AD1CSSH(1) AD1CSSL AD1CON4 Reserved Legend: Note 1: Addr 0300 0320 0322 0324 0326 0328 032A 032C 032E 0330 0332 ADC1 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC BUFS — CH0NA PCFG24 PCFG8 CSS24 CSS8 — — PCFG23 PCFG7 CSS23 CSS7 — — PCFG9 CSS25 CSS9 — — — — — PCFG22 PCFG6 CSS22 CSS6 — — — — PCFG21 PCFG5 CSS21 CSS5 — — PCFG20 PCFG4 CSS20 CSS4 — — PCFG3 CSS19 CSS3 — — — — SIMSAM ASAM SAMP BUFM CH123NA CH0SA PCFG19 PCFG18 PCFG17 PCFG2 CSS18 CSS2 PCFG1 CSS17 CSS1 DMABL — — PCFG16 PCFG0 CSS16 CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SMPI ADCS CH123SB — — ADC Data Buffer 0 ADON ADRC — CH0NB — VCFG — — — — — — PCFG29 PCFG13 CSS29 CSS13 — — PCFG28 PCFG12 CSS28 CSS12 — — — — ADSIDL ADDMABM — — — AD12B CSCNA SAMC CH123NB CH0SB PCFG27 PCFG26 PCFG25 PCFG11 PCFG10 CSS27 CSS11 — — CSS26 CSS10 — — FORM CHPS PCFG31 PCFG30 PCFG15 PCFG14 CSS31 CSS15 — — CSS30 CSS14 — — 0334033E x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. Not all ANx inputs are available on all devices. See the device pin diagrams for available ANx inputs. Preliminary © 2009 Microchip Technology Inc. TABLE 4-16: File Name ADC2BUF0 AD2CON1 AD2CON2 AD2CON3 AD2CHS123 AD2CHS0 Reserved AD2PCFGL Reserved AD2CSSL AD2CON4 Reserved Legend: Addr 0340 0360 0362 0364 0366 0368 036A 036C 036E 0370 0372 0374037E ADC2 REGISTER MAP Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx SSRC BUFS — CH0NA — PCFG8 — CSS8 — — — PCFG7 — CSS7 — — — — — — PCFG6 — CSS6 — — — — — PCFG5 — CSS5 — — — SIMSAM ASAM SAMP BUFM CH123NA CH0SA — PCFG3 — CSS3 — — — — PCFG2 — CSS2 — PCFG1 — CSS1 DMABL — — — PCFG0 — CSS0 DONE ALTS CH123SA 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 SMPI ADCS CH123SB — — — PCFG4 — CSS4 — — — ADC Data Buffer 0 ADON ADRC — CH0NB — — CSS15 — — — VCFG — — — — — CSS14 — — — — — — PCFG13 — CSS13 — — — — — PCFG12 — CSS12 — — — — CSS11 — — — ADSIDL ADDMABM — — — AD12B CSCNA SAMC CH123NB CH0SB — — CSS10 — — — PCFG9 — CSS9 — — PCFG11 PCFG10 FORM CHPS PCFG15 PCFG14 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-17: File Name Addr DMA0CON 0380 DMA0REQ 0382 DMA0STA DMA0STB DMA0PAD DMA0CNT 0384 0386 0388 038A DMA REGISTER MAP Bit 15 CHEN FORCE Bit 14 SIZE — Bit 13 DIR — Bit 12 HALF — Bit 11 NULLW — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE Bit 6 — Bit 5 Bit 4 Bit 3 — IRQSEL Bit 2 — Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 AMODE MODE DMA1CON 038C DMA1REQ 038E DMA1STA DMA1STB DMA1PAD DMA1CNT 0390 0392 0394 0396 PIC24HJXXXGPX06A/X08A/X10A 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DMA2CON 0398 DMA2REQ 039A DMA2STA DMA2STB DMA2PAD DMA2CNT 039C 039E 03A0 03A2 Preliminary DS70592A-page 43 DMA3CON 03A4 DMA3REQ 03A6 DMA3STA DMA3STB DMA3PAD 03A8 03AA 03AC DMA3CNT 03AE DMA4CON 03B0 DMA4REQ 03B2 DMA4STA DMA4STB DMA4PAD 03B4 03B6 03B8 DMA4CNT 03BA DMA5CON 03BC DMA5REQ 03BE DMA5STA DMA5STB Legend: 03C0 03C2 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-17: File Name Addr DMA5PAD 03C4 DMA REGISTER MAP (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 PAD — CHEN — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — CHEN FORCE — SIZE — — DIR — — HALF — — NULLW — — — — — — — — — — STA STB PAD — — — — — — — — — — XWCOL7 PPST7 DSADR LSTCH PPST6 CNT XWCOL6 XWCOL5 PPST5 XWCOL4 PPST4 XWCOL3 PPST3 XWCOL2 PPST2 XWCOL1 XWCOL0 PPST1 PPST0 — CNT AMODE — IRQSEL — MODE — CNT AMODE — IRQSEL — MODE Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DS70592A-page 44 PIC24HJXXXGPX06A/X08A/X10A DMA5CNT 03C6 DMA6CON 03C8 DMA6STA DMA6STB DMA6PAD 03CC 03CE 03D0 DMA6REQ 03CA FORCE DMA6CNT 03D2 DMA7CON 03D4 DMA7REQ 03D6 DMA7STA DMA7STB 03D8 03DA DMA7PAD 03DC DMA7CNT 03DE Preliminary © 2009 Microchip Technology Inc. DMACS0 DMACS1 DSADR Legend: 03E0 PWCOL7 PWCOL6 PWCOL5 PWCOL4 PWCOL3 PWCOL2 PWCOL1 PWCOL0 03E2 03E4 — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-18: File Name C1CTRL1 C1CTRL2 C1VEC C1FCTRL C1FIFO C1INTF C1INTE C1EC C1CFG1 C1CFG2 C1FEN1 Addr 0400 0402 0404 0406 0408 040A 040C 040E 0410 0412 ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 OR 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY Bit 15 — — — — — — — — Bit 14 — — — DMABS — — — — WAKFIL TXBO — — — TXBP — — — Bit 13 CSIDL — — — — FBP RXBP — — — F5MSK F13MSK TXWAR — — RXWAR — — SEG2PH FLTEN9 FLTEN8 F4MSK F12MSK EWARN — — Bit 12 ABAT — Bit 11 — — — FILHIT — — — Bit 10 Bit 9 REQOP — — — — — — IVRIF IVRIE — — WAKIF WAKIE ERRIF ERRIE — — — FIFOIF FIFOIE Bit 8 Bit 7 Bit 6 OPMODE — — Bit 5 Bit 4 — Bit 3 CANCAP ICODE FSA FNRB RBOVIF RBOVIE RBIF RBIE TBIF TBIE Bit 2 — Bit 1 — Bit 0 WIN All Resets 0480 0000 0000 0000 0000 0000 0000 0000 0000 PRSEG FLTEN2 FLTEN1 FLTEN0 F1MSK F9MSK F0MSK F8MSK 0000 FFFF 0000 0000 DNCNT TERRCNT SJW SEG2PHTS FLTEN7 SAM FLTEN6 RERRCNT BRP SEG1PH FLTEN5 FLTEN4 FLTEN3 F2MSK F10MSK 0414 FLTEN15 FLTEN14 FLTEN13 FLTEN12 FLTEN11 FLTEN10 F7MSK F15MSK F6MSK F14MSK C1FMSKSEL1 0418 C1FMSKSEL2 041A Legend: F3MSK F11MSK — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-19: File Name Addr 0400041E C1RXFUL1 C1RXFUL2 C1RXOVF1 C1RXOVF2 C1TR01CO N C1TR23CO N C1TR45CO N C1TR67CO N C1RXD C1TXD Legend: ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 0 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x RXFUL8 RXOVF8 RXFUL7 RXOVF7 TXEN0 TXEN2 TXEN4 TXEN6 RXFUL6 RXOVF6 TX ABAT0 TX ABAT2 TX ABAT4 TX ABAT6 RXFUL5 RXOVF5 TX LARB0 TX LARB2 TX LARB4 TX LARB6 RXFUL4 RXOVF4 TX ERR0 TX ERR2 TX ERR4 TX ERR6 RXFUL3 RXOVF3 TX REQ0 TX REQ2 TX REQ4 TX REQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 0000 0000 0000 0000 0000 0420 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 RXFUL9 0428 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 0430 0432 0434 0436 0440 0442 TXEN1 TXEN3 TXEN5 TXEN7 TX ABT1 TX ABT3 TX ABT5 TX ABT7 TX LARB1 TX LARB3 TX LARB5 TX LARB7 TX ERR1 TX ERR3 TX ERR5 TX ERR7 TX REQ1 TX REQ3 TX REQ5 TX REQ7 RTREN1 RTREN3 RTREN5 RTREN7 0422 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 042A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TX1PRI TX3PRI TX5PRI TX7PRI TX0PRI TX2PRI TX4PRI TX6PRI PIC24HJXXXGPX06A/X08A/X10A 0000 0000 xxxx xxxx xxxx Recieved Data Word Transmit Data Word Preliminary DS70592A-page 45 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-20: File Name ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets Addr 0400041E See definition when WIN = x F3BP F7BP F11BP F15BP SID EID SID EID SID EID SID EID SID SID SID SID SID F2BP F6BP F10BP F14BP F1BP F5BP F9BP F13BP SID — — — — — MIDE MIDE MIDE EXIDE EXIDE EID — — — — EID EID EID EID EID EID EID F0BP F4BP F8BP F12BP — EID 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx C1BUFPNT1 C1BUFPNT2 C1BUFPNT3 C1BUFPNT4 C1RXM0SID C1RXM0EID C1RXM1SID C1RXM1EID C1RXM2SID C1RXM2EID C1RXF0SID C1RXF0EID C1RXF1SID Legend: 0420 0422 0424 0426 0430 0432 0434 0436 0438 043A 0440 0442 0444 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-20: File Name C1RXF1EID C1RXF2SID C1RXF2EID C1RXF3SID C1RXF3EID C1RXF4SID C1RXF4EID C1RXF5SID C1RXF5EID C1RXF6SID C1RXF6EID C1RXF7SID C1RXF7EID C1RXF8SID ECAN1 REGISTER MAP WHEN C1CTRL1.WIN = 1 FOR PIC24HJXXXGP506A/510A/610A DEVICES ONLY (CONTINUED) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx — — — — — — — — — — — — — — EID EID EID EID EID EID EID EID EID EID EID EID EID EID xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx DS70592A-page 46 PIC24HJXXXGPX06A/X08A/X10A Addr 0446 0448 044A 044C 044E 0450 0452 0454 0456 0458 045A 045C 045E 0460 0462 0464 0466 0468 046A 046C 046E 0470 0472 0474 0476 0478 047A 047C 047E EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID SID SID SID SID SID SID SID SID SID SID SID SID SID EID — — — — — — — — — — — — — — EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EID EID EID EID EID EID EID EID EID EID EID EID EID EID Preliminary © 2009 Microchip Technology Inc. C1RXF8EID C1RXF9SID C1RXF9EID C1RXF10SID C1RXF10EID C1RXF11SID C1RXF11EID C1RXF12SID C1RXF12EID C1RXF13SID C1RXF13EID C1RXF14SID C1RXF14EID C1RXF15SID C1RXF15EID Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. © 2009 Microchip Technology Inc. TABLE 4-21: File Name C2CTRL1 C2CTRL2 C2VEC C2FCTRL C2FIFO C2INTF C2INTE C2EC C2CFG1 C2CFG2 C2FEN1 C2FMSKSEL1 C2FMSKSEL2 Legend: Addr 0500 0502 0504 0506 0508 050A 050C 050E 0510 0512 0514 0518 051A ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 OR 1 FOR PIC24HJ256GP610A DEVICES ONLY Bit 15 — — — — — — — — FLTEN15 Bit 14 — — — DMABS — — — — WAKFIL FLTEN14 TXBO — — — FLTEN13 TXBP — — — FLTEN12 Bit 13 CSIDL — — — — FBP RXBP — — — FLTEN11 F5MSK F13MSK TXWAR — — RXWAR EWARN — — SEG2PH FLTEN10 FLTEN9 FLTEN8 F4MSK F12MSK — — Bit 12 ABAT — Bit 11 — — — FILHIT — — — Bit 10 Bit 9 REQOP — — — — — — IVRIF IVRIE — — WAKIF WAKIE ERRIF ERRIE — — — FIFOIF FIFOIE Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 — — Bit 3 CANCAP ICODE FSA FNRB RBOVIF RBOVIE RBIF RBIE TBIF TBIE Bit 2 — Bit 1 — Bit 0 WIN All Resets 0480 0000 0000 0000 0000 0000 0000 OPMODE — DNCNT TERRCNT SJW SEG2PHTS FLTEN7 SAM RERRCNT BRP SEG1PH F2MSK F10MSK F1MSK F9MSK PRSEG FLTEN2 FLTEN1 FLTEN0 F0MSK F8MSK PIC24HJXXXGPX06A/X08A/X10A 0000 0000 0000 FFFF 0000 0000 FLTEN6 FLTEN5 FLTEN4 FLTEN3 F7MSK F15MSK F6MSK F14MSK F3MSK F11MSK — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. Preliminary DS70592A-page 47 TABLE 4-22: File Name Addr 0500051E C2RXFUL1 C2RXFUL2 C2RXOVF1 C2RXOVF2 ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 0 FOR PIC24HJ256GP610A DEVICES ONLY Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x RXFUL9 RXFUL8 RXFUL7 RXFUL6 RXOVF6 TX ABAT0 TX ABAT2 TX ABAT4 TX ABAT6 RXFUL5 RXOVF5 TX LARB0 TX LARB2 TX LARB4 TX LARB6 RXFUL4 RXOVF4 TX ERR0 TX ERR2 TX ERR4 TX ERR6 RXFUL3 RXOVF3 TX REQ0 TX REQ2 TX REQ4 TX REQ6 RXFUL2 RXOVF2 RTREN0 RTREN2 RTREN4 RTREN6 RXFUL1 RXOVF1 RXFUL0 RXOVF0 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx 0520 RXFUL15 RXFUL14 RXFUL13 RXFUL12 RXFUL11 RXFUL10 0522 RXFUL31 RXFUL30 RXFUL29 RXFUL28 RXFUL27 RXFUL26 RXFUL25 RXFUL24 RXFUL23 RXFUL22 RXFUL21 RXFUL20 RXFUL19 RXFUL18 RXFUL17 RXFUL16 0528 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF09 RXOVF08 RXOVF7 TXEN1 TXEN3 TXEN5 TXEN7 TX ABAT1 TX ABAT3 TX ABAT5 TX ABAT7 TX LARB1 TX LARB3 TX LARB5 TX LARB7 TX ERR1 TX ERR3 TX ERR5 TX ERR7 TX REQ1 TX REQ3 TX REQ5 TX REQ7 RTREN1 RTREN3 RTREN5 RTREN7 TX1PRI TX3PRI TX5PRI TX7PRI TXEN0 TXEN2 TXEN4 TXEN6 052A RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 TX0PRI TX2PRI TX4PRI TX6PRI C2TR01CON 0530 C2TR23CON 0532 C2TR45CON 0534 C2TR67CON 0536 C2RXD C2TXD Legend: 0540 0542 Recieved Data Word Transmit Data Word x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. DS70592A-page 48 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-23: File Name ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610A DEVICES ONLY Addr 0500051E Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets See definition when WIN = x F3BP F7BP F12BP F15BP SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID EID SID SID SID SID SID SID SID SID SID SID SID SID SID SID SID F2BP F6BP F10BP F14BP F1BP F5BP F9BP F13BP SID — — — — — — — — — — — — — — — MIDE MIDE MIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EXIDE EID — — — — — — — — — — — — — — EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID EID F0BP F4BP F8BP F12BP — EID 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx C2BUFPNT1 C2BUFPNT2 C2BUFPNT3 C2BUFPNT4 C2RXM0SID C2RXM0EID C2RXM1SID C2RXM1EID C2RXM2SID C2RXM2EID C2RXF0SID C2RXF0EID 0520 0522 0524 0526 0530 0532 0534 0536 0538 053A 0540 0542 0544 0546 0548 054A 054C 054E 0550 0552 0554 0556 0558 055A 055C 055E 0560 0562 0564 0566 0568 056A 056C Preliminary © 2009 Microchip Technology Inc. C2RXF1SID C2RXF1EID C2RXF2SID C2RXF2EID C2RXF3SID C2RXF3EID C2RXF4SID C2RXF4EID C2RXF5SID C2RXF5EID C2RXF6SID C2RXF6EID C2RXF7SID C2RXF7EID C2RXF8SID C2RXF8EID C2RXF9SID C2RXF9EID C2RXF10SID C2RXF10EID C2RXF11SID Legend: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. TABLE 4-23: File Name C2RXF11EID C2RXF12SID C2RXF12EID C2RXF13SID C2RXF13EID C2RXF14SID C2RXF14EID C2RXF15SID C2RXF15EID Legend: ECAN2 REGISTER MAP WHEN C2CTRL1.WIN = 1 FOR PIC24HJ256GP610A DEVICES ONLY (CONTINUED) Addr 056E 0570 0572 0574 0576 0578 057A 057C 057E Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 All Resets xxxx — — — — EID EID EID EID xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx © 2009 Microchip Technology Inc. EID SID EID SID EID SID EID SID EID SID SID SID SID EID — — — — EXIDE EXIDE EXIDE EXIDE EID EID EID EID PIC24HJXXXGPX06A/X08A/X10A x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. Preliminary DS70592A-page 49 TABLE 4-24: File Name TRISA PORTA LATA ODCA Legend: Note 1: Addr 02C0 02C2 02C4 06C0 PORTA REGISTER MAP(1) Bit 15 TRISA15 RA15 LATA15 ODCA15 Bit 14 TRISA14 RA14 LATA14 ODCA14 Bit 13 TRISA13 RA13 LATA13 — Bit 12 TRISA12 RA12 LATA12 — Bit 11 — — — — Bit 10 TRISA10 RA10 LATA10 — Bit 9 TRISA9 RA9 LATA9 — Bit 8 — — — — Bit 7 TRISA7 RA7 LATA7 — Bit 6 TRISA6 RA6 LATA6 — Bit 5 TRISA5 RA5 LATA5 ODCA5 Bit 4 TRISA4 RA4 LATA4 ODCA4 Bit 3 TRISA3 RA3 LATA3 ODCA3 Bit 2 TRISA2 RA2 LATA2 ODCA2 Bit 1 TRISA1 RA1 LATA1 ODCA1 Bit 0 TRISA0 RA0 LATA0 ODCA0 All Resets F6FF xxxx xxxx 0000 DS70592A-page 50 PIC24HJXXXGPX06A/X08A/X10A x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 4-25: File Name TRISB PORTB LATB Addr 02C6 02C8 02CA PORTB REGISTER MAP(1) Bit 15 TRISB15 RB15 LATB15 Bit 14 TRISB14 RB14 LATB14 Bit 13 TRISB13 RB13 LATB13 Bit 12 TRISB12 RB12 LATB12 Bit 11 TRISB11 RB11 LATB11 Bit 10 TRISB10 RB10 LATB10 Bit 9 TRISB9 RB9 LATB9 Bit 8 TRISB8 RB8 LATB8 Bit 7 TRISB7 RB7 LATB7 Bit 6 TRISB6 RB6 LATB6 Bit 5 TRISB5 RB5 LATB5 Bit 4 TRISB4 RB4 LATB4 Bit 3 TRISB3 RB3 LATB3 Bit 2 TRISB2 RB2 LATB2 Bit 1 TRISB1 RB1 LATB1 Bit 0 TRISB0 RB0 LATB0 All Resets FFFF xxxx xxxx Preliminary © 2009 Microchip Technology Inc. Legend: Note 1: x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 4-26: File Name TRISC PORTC LATC Legend: Note 1: Addr 02CC 02CE 02D0 PORTC REGISTER MAP(1) Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 — — — Bit 10 — — — Bit 9 — — — Bit 8 — — — Bit 7 — — — Bit 6 — — — Bit 5 — — — Bit 4 TRISC4 RC4 LATC4 Bit 3 TRISC3 RC3 LATC3 Bit 2 TRISC2 RC2 LATC2 Bit 1 TRISC1 RC1 LATC1 Bit 0 — — — All Resets F01E xxxx xxxx TRISC15 TRISC14 TRISC13 TRISC12 RC15 LATC15 RC14 LATC14 RC13 LATC13 RC12 LATC12 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 4-27: File Name TRISD PORTD LATD ODCD Legend: Note 1: Addr 02D2 02D4 02D6 06D2 PORTD REGISTER MAP(1) Bit 15 TRISD15 RD15 LATD15 ODCD15 Bit 14 TRISD14 RD14 LATD14 ODCD14 Bit 13 TRISD13 RD13 LATD13 ODCD13 Bit 12 TRISD12 RD12 LATD12 ODCD12 Bit 11 TRISD11 RD11 LATD11 ODCD11 Bit 10 TRISD10 RD10 LATD10 ODCD10 Bit 9 TRISD9 RD9 LATD9 ODCD9 Bit 8 TRISD8 RD8 LATD8 ODCD8 Bit 7 TRISD7 RD7 LATD7 ODCD7 Bit 6 TRISD6 RD6 LATD6 ODCD6 Bit 5 TRISD5 RD5 LATD5 ODCD5 Bit 4 TRISD4 RD4 LATD4 ODCD4 Bit 3 TRISD3 RD3 LATD3 ODCD3 Bit 2 TRISD2 RD2 LATD2 ODCD2 Bit 1 TRISD1 RD1 LATD1 ODCD1 Bit 0 TRISD0 RD0 LATD0 ODCD0 All Resets FFFF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 4-28: File Name TRISE PORTE LATE Legend: Note 1: Addr 02D8 02DA 02DC PORTE REGISTER MAP(1) Bit 15 — — — Bit 14 — — — Bit 13 — — — Bit 12 — — — Bit 11 — — — Bit 10 — — — Bit 9 — — — Bit 8 — — — Bit 7 TRISE7 RE7 LATE7 Bit 6 TRISE6 RE6 LATE6 Bit 5 TRISE5 RE5 LATE5 Bit 4 TRISE4 RE4 LATE4 Bit 3 TRISE3 RE3 LATE3 Bit 2 TRISE2 RE2 LATE2 Bit 1 TRISE1 RE1 LATE1 Bit 0 TRISE0 RE0 LATE0 All Resets 00FF xxxx xxxx © 2009 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. TABLE 4-29: File Name TRISF PORTF LATF ODCF(2) Legend: Note 1: Addr 02DE 02E0 02E2 06DE PORTF REGISTER MAP(1) PIC24HJXXXGPX06A/X08A/X10A Bit 15 — — — — Bit 14 — — — — Bit 13 TRISF13 RF13 LATF13 ODCF13 Bit 12 TRISF12 RF12 LATF12 ODCF12 Bit 11 — — — — Bit 10 — — — — Bit 9 — — — — Bit 8 TRISF8 RF8 LATF8 ODCF8 Bit 7 TRISF7 RF7 LATF7 ODCF7 Bit 6 TRISF6 RF6 LATF6 ODCF6 Bit 5 TRISF5 RF5 LATF5 ODCF5 Bit 4 TRISF4 RF4 LATF4 ODCF4 Bit 3 TRISF3 RF3 LATF3 ODCF3 Bit 2 TRISF2 RF2 LATF2 ODCF2 Bit 1 TRISF1 RF1 LATF1 ODCF1 Bit 0 TRISF0 RF0 LATF0 ODCF0 All Resets 31FF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. Preliminary DS70592A-page 51 TABLE 4-30: File Name TRISG PORTG LATG ODCG(2) Legend: Note 1: Addr 02E4 02E6 02E8 06E4 PORTG REGISTER MAP(1) Bit 15 TRISG15 RG15 LATG15 ODCG15 Bit 14 TRISG14 RG14 LATG14 ODCG14 Bit 13 TRISG13 RG13 LATG13 ODCG13 Bit 12 TRISG12 RG12 LATG12 ODCG12 Bit 11 — — — — Bit 10 — — — — Bit 9 TRISG9 RG9 LATG9 ODCG9 Bit 8 TRISG8 RG8 LATG8 ODCG8 Bit 7 TRISG7 RG7 LATG7 ODCG7 Bit 6 TRISG6 RG6 LATG6 ODCG6 Bit 5 — — — — Bit 4 — — — — Bit 3 TRISG3 RG3 LATG3 ODCG3 Bit 2 TRISG2 RG2 LATG2 ODCG2 Bit 1 TRISG1 RG1 LATG1 ODCG1 Bit 0 TRISG0 RG0 LATG0 ODCG0 All Resets F3CF xxxx xxxx 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. The actual set of I/O port pins varies from one device to another. Please refer to the corresponding pinout diagrams. DS70592A-page 52 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-31: File Name RCON OSCCON CLKDIV PLLFBD OSCTUN Legend: Note 1: 2: Addr 0740 0742 0744 0746 0748 SYSTEM CONTROL REGISTER MAP Bit 15 TRAPR — ROI — — — — Bit 14 IOPUWR Bit 13 — COSC DOZE — — — — Bit 12 — Bit 11 — — DOZEN — — — — Bit 10 — Bit 9 — NOSC FRCDIV — — — — — Bit 8 VREGS Bit 7 EXTR CLKLOCK Bit 6 SWR — Bit 5 SWDTEN LOCK — PLLDIV TUN Bit 4 WDTO — Bit 3 SLEEP CF Bit 2 IDLE — PLLPRE Bit 1 BOR LPOSCEN Bit 0 POR OSWEN All Resets xxxx(1) 0300(2) 3040 0030 0000 PLLPOST x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. RCON register Reset values dependent on type of Reset. OSCCON register Reset values dependent on the FOSC Configuration bits and by type of Reset. TABLE 4-32: File Name NVMCON NVMKEY Legend: Note 1: Addr 0760 0766 NVM REGISTER MAP Bit 15 WR — Bit 14 WREN — Bit 13 WRERR — Bit 12 — — Bit 11 — — Bit 10 — — Bit 9 — — Bit 8 — — Bit 7 — Bit 6 ERASE Bit 5 — Bit 4 — NVMKEY Bit 3 Bit 2 Bit 1 Bit 0 All Resets 0000(1) 0000 NVMOP Preliminary © 2009 Microchip Technology Inc. x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. TABLE 4-33: File Name PMD1 PMD2 PMD3 Legend: Addr 0770 0772 0774 PMD REGISTER MAP Bit 15 T5MD IC8MD T9MD Bit 14 T4MD IC7MD T8MD Bit 13 T3MD IC6MD T7MD Bit 12 T2MD IC5MD T6MD Bit 11 T1MD IC4MD — Bit 10 — IC3MD — Bit 9 — IC2MD — Bit 8 — IC1MD — Bit 7 I2C1MD OC8MD — Bit 6 U2MD OC7MD — Bit 5 U1MD OC6MD — Bit 4 SPI2MD OC5MD — Bit 3 SPI1MD OC4MD — Bit 2 C2MD OC3MD — Bit 1 C1MD OC2MD I2C2MD Bit 0 AD1MD OC1MD AD2MD All Resets 0000 0000 0000 x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal for PinHigh devices. PIC24HJXXXGPX06A/X08A/X10A 4.2.6 SOFTWARE STACK 4.2.7 DATA RAM PROTECTION FEATURE In addition to its use as a working register, the W15 register in the PIC24HJXXXGPX06A/X08A/X10A devices is also used as a software Stack Pointer. The Stack Pointer always points to the first available free word and grows from lower to higher addresses. It predecrements for stack pops and post-increments for stack pushes, as shown in Figure 4-5. For a PC push during any CALL instruction, the MSB of the PC is zeroextended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing concatenates the SRL register to the MSB of the PC prior to the push. The PIC24H product family supports Data RAM protection features that enable segments of RAM to be protected when used in conjunction with Boot and Secure Code Segment Security. BSRAM (Secure RAM segment for BS) is accessible only from the Boot Segment Flash code, when enabled. SSRAM (Secure RAM segment for RAM) is accessible only from the Secure Segment Flash code, when enabled. See Table 4-1 for an overview of the BSRAM and SSRAM SFRs. 4.3 Instruction Addressing Modes The Stack Pointer Limit register (SPLIM) associated with the Stack Pointer sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM is forced to ‘0’ because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 0x2000 in RAM, initialize the SPLIM with the value 0x1FFE. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0x0800. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. The addressing modes in Table 4-34 form the basis of the addressing modes optimized to support the specific features of individual instructions. The addressing modes provided in the MAC class of instructions are somewhat different from those in the other instruction types. 4.3.1 FILE REGISTER INSTRUCTIONS Most file register instructions use a 13-bit address field (f) to directly address data present in the first 8192 bytes of data memory (Near Data Space). Most file register instructions employ a working register, W0, which is denoted as WREG in these instructions. The destination is typically either the same file register or WREG (with the exception of the MUL instruction), which writes the result to a register or register pair. The MOV instruction allows additional flexibility and can access the entire data space. 4.3.2 MCU INSTRUCTIONS The 3-operand MCU instructions are of the form: Operand 3 = Operand 1 Operand 2 where Operand 1 is always a working register (i.e., the addressing mode can only be Register Direct) which is referred to as Wb. Operand 2 can be a W register, fetched from data memory, or a 5-bit literal. The result location can be either a W register or a data memory location. The following addressing modes are supported by MCU instructions: • • • • • Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified 5-bit or 10-bit Literal Note: Not all instructions support all the addressing modes given above. Individual instructions may support different subsets of these addressing modes. FIGURE 4-5: 0x0000 15 CALL STACK FRAME 0 Stack Grows Towards Higher Address PC 000000000 PC W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] © 2009 Microchip Technology Inc. Preliminary DS70592A-page 53 PIC24HJXXXGPX06A/X08A/X10A TABLE 4-34: FUNDAMENTAL ADDRESSING MODES SUPPORTED Description The address of the file register is specified explicitly. The contents of a register are accessed directly. The contents of Wn forms the EA. The contents of Wn forms the EA. Wn is post-modified (incremented or decremented) by a constant value. Wn is pre-modified (incremented or decremented) by a signed constant value to form the EA. The sum of Wn and a literal forms the EA. Addressing Mode File Register Direct Register Direct Register Indirect Register Indirect Post-Modified Register Indirect Pre-Modified Register Indirect with Register Offset The sum of Wn and Wb forms the EA. Register Indirect with Literal Offset 4.3.3 MOVE INSTRUCTIONS 4.4 Move instructions provide a greater degree of addressing flexibility than other instructions. In addition to the Addressing modes supported by most MCU instructions, move instructions also support Register Indirect with Register Offset Addressing mode, also referred to as Register Indexed mode. Note: For the MOV instructions, the Addressing mode specified in the instruction can differ for the source and destination EA. However, the 4-bit Wb (Register Offset) field is shared between both source and destination (but typically only used by one). Interfacing Program and Data Memory Spaces The PIC24HJXXXGPX06A/X08A/X10A architecture uses a 24-bit wide program space and a 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24HJXXXGPX06A/X08A/X10A architecture provides two methods by which program space can be accessed during operation: • Using table instructions to access individual bytes or words anywhere in the program space • Remapping a portion of the program space into the data space (Program Space Visibility) Table instructions allow an application to read or write to small areas of the program memory. This capability makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. In summary, the following Addressing modes are supported by move instructions: • • • • • • • • Register Direct Register Indirect Register Indirect Post-modified Register Indirect Pre-modified Register Indirect with Register Offset (Indexed) Register Indirect with Literal Offset 8-bit Literal 16-bit Literal Note: Not all instructions support all the Addressing modes given above. Individual instructions may support different subsets of these Addressing modes. 4.4.1 ADDRESSING PROGRAM SPACE 4.3.4 OTHER INSTRUCTIONS Besides the various addressing modes outlined above, some instructions use literal constants of various sizes. For example, BRA (branch) instructions use 16-bit signed literals to specify the branch destination directly, whereas the DISI instruction uses a 14-bit unsigned literal field. In some instructions, the source of an operand or result is implied by the opcode itself. Certain operations, such as NOP, do not have any operands. Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Page register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG = 0) or the configuration memory (TBLPAG = 1). DS70592A-page 54 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A For remapping operations, the 8-bit Program Space Visibility register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is ‘1’, PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 4-35 and Figure 4-6 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P refers to a program space word, whereas D refers to a data space word. TABLE 4-35: PROGRAM SPACE ADDRESS CONSTRUCTION Access Space User User Configuration Program Space Address 0 0xxx xxxx TBLPAG 0xxx xxxx TBLPAG 1xxx xxxx 0 0 PSVPAG xxxx xxxx PC xxxx xxxx xxxx xxx0 Data EA xxxx xxxx xxxx xxxx Data EA xxxx xxxx xxxx xxxx Data EA(1) xxx xxxx xxxx xxxx 0 Access Type Instruction Access (Code Execution) TBLRD/TBLWT (Byte/Word Read/Write) Program Space Visibility (Block Remap/Read) Note 1: User Data EA is always ‘1’ in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 55 PIC24HJXXXGPX06A/X08A/X10A FIGURE 4-6: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) 0 Program Counter 23 bits EA 0 1/0 Table Operations(2) 1/0 TBLPAG 8 bits 24 bits 16 bits Select Program Space Visibility(1) (Remapping) 0 PSVPAG 8 bits 1 EA 0 15 bits 23 bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as ‘0’ in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS70592A-page 56 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 4.4.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P) to a data address. Note that D, the ‘phantom byte’, will always be ‘0’. In Byte mode, it maps the upper or lower byte of the program word to D of the data address, as above. Note that the data will always be ‘0’ when the upper ‘phantom’ byte is selected (Byte Select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 5.0 “Flash Program Memory”. For all table operations, the area of program memory space to be accessed is determined by the Table Page register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG = 0, the table page is located in the user memory space. When TBLPAG = 1, the page is located in configuration space. The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two 16-bit, word wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P) to a data address (D). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when Byte Select is ‘1’; the lower byte is selected when it is ‘0’. FIGURE 4-7: TBLPAG ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space 23 15 0 02 0x000000 00000000 23 00000000 00000000 00000000 16 8 0 0x020000 0x030000 ‘Phantom’ Byte TBLRDH.B (Wn = 0) TBLRDL.B (Wn = 1) TBLRDL.B (Wn = 0) TBLRDL.W The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. 0x800000 © 2009 Microchip Technology Inc. Preliminary DS70592A-page 57 PIC24HJXXXGPX06A/X08A/X10A 4.4.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY 24-bit program word are used to contain the data. The upper 8 bits of any program space location used as data should be programmed with ‘1111 1111’ or ‘0000 0000’ to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This option provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is ‘1’ and program space visibility is enabled by setting the PSV bit in the Core Control register (CORCON). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 4-8), only the lower 16 bits of the For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions require one instruction cycle in addition to the specified execution time. All other instructions require two instruction cycles in addition to the specified execution time. For operations that use PSV, which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: • Execution in the first iteration • Execution in the last iteration • Execution prior to exiting the loop due to an interrupt • Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. FIGURE 4-8: PROGRAM SPACE VISIBILITY OPERATION When CORCON = 1 and EA = 1: Program Space PSVPAG 02 23 15 0 0x000000 0x010000 0x018000 The data in the page designated by PSVPAG is mapped into the upper half of the data memory space... Data Space 0x0000 Data EA 0x8000 PSV Area ...while the lower 15 bits of the EA specify an exact address within 0xFFFF the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. 0x800000 DS70592A-page 58 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A 5.0 Note: FLASH PROGRAM MEMORY This data sheet summarizes the features of the PIC24HJXXXGPX06A/X08A/X10A family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the “PIC24H Family Reference Manual”, Section 5. “Flash Programming” (DS70228), which is available from the Microchip website (www.microchip.com). ital signal controller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user can write program memory data either in blocks or ‘rows’ of 64 instructions (192 bytes) at a time, or single instructions and erase program memory in blocks or ‘pages’ of 512 instructions (1536 bytes) at a time. 5.1 The PIC24HJXXXGPX06A/X08A/X10A devices contain internal Flash program memory for storing and executing application code. The memory is readable, writable and erasable during normal operation over the entire VDD range. Flash memory can be programmed in two ways: 1. 2. In-Circuit Serial Programming™ (ICSP™) programming capability Run-Time Self-Programming (RTSP) Table Instructions and Flash Programming Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using bits of the TBLPAG register and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 5-1. The TBLRDL and the TBLWTL instructions are used to read or write to bits of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. The TBLRDH and TBLWTH instructions are used to read or write to bits of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ICSP programming capability allows a PIC24HJXXXGPX06A/X08A/X10A device to be serially programmed while in the end application circuit. This is simply done with two lines for programming clock and programming data (one of the alternate programming pin pairs: PGECx/PGEDx, and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the dig- FIGURE 5-1: ADDRESSING FOR TABLE REGISTERS 24 bits Using Program Counter 0 Program Counter 0 Working Reg EA Using Table Instruction 1/0 TBLPAG Reg 8 bits 16 bits User/Configuration Space Select 24-bit EA Byte Select © 2009 Microchip Technology Inc. Preliminary DS70592A-page 59 PIC24HJXXXGPX06A/X08A/X10A 5.2 RTSP Operation 5.3 Programming Operations The PIC24HJXXXGPX06A/X08A/X10A Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase a page of memory, which consists of eight rows (512 instructions) at a time, and to program one row or one word at a time. Table 24-12 displays typical erase and programming times. The 8-row erase pages and single row write rows are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. The program memory implements holding buffers that can contain 64 instructions of programming data. Prior to the actual programming operation, the write data must be loaded into the buffers in sequential order. The instruction words loaded must always be from a group of 64 boundary. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. A total of 64 TBLWTL and TBLWTH instructions are required to load the instructions. All of the table write operations are single-word writes (two instruction cycles) because only the buffers are written. A programming cycle is required for programming each row. A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. The processor stalls (waits) until the programming operation is finished. The programming time depends on the FRC accuracy (see Table 24-19) and the value of the FRC Oscillator Tuning register (see Register 9-4). Use the following formula to calculate the minimum and maximum values for the Row Write Time, Page Erase Time and Word Write Cycle Time parameters (see Table 24-12). EQUATION 5-1: PROGRAMMING TIME T ------------------------------------------------------------------------------------------------------------------------7.37 MHz × ( FRC Accuracy ) % × ( FRC Tuning ) % For example, if the device is operating at +125°C, the FRC accuracy will be ±5%. If the TUN bits (see Register 9-4) are set to ‘b111111, the Minimum Row Write Time is: 11064 Cycles T RW = --------------------------------------------------------------------------------------------- = 1.435 ms 7.37 MHz × ( 1 + 0.05 ) × ( 1 – 0.00375 ) and, the Maximum Row Write Time is: 11064 Cycles T RW = --------------------------------------------------------------------------------------------- = 1.586 ms 7.37 MHz × ( 1 – 0.05 ) × ( 1 – 0.00375 ) Setting the WR bit (NVMCON) starts the operation, and the WR bit is automatically cleared when the operation is finished. 5.4 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 5-1) controls which blocks are to be erased, which memory type is to be programmed and the start of the programming cycle. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 0x55 and 0xAA to the NVMKEY register. Refer to Section 5.3 “Programming Operations” for further details. DS70592A-page 60 Preliminary © 2009 Microchip Technology Inc. PIC24HJXXXGPX06A/X08A/X10A REGISTER 5-1: R/SO-0(1) WR bit 15 U-0 — bit 7 Legend: R = Readable bit -n = Value at POR bit 15 SO = Settable only bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown R/W-0(1) ERASE U-0 — U-0 — R/W-0(1) R/W-0(1) R/W-0(1) (2) NVMCON: FLASH MEMORY CONTROL REGISTER R/W-0(1) WREN R/W-0(1) WRERR U-0 — U-0 — U-0 — U-0 — U-0 — bit 8 R/W-0(1) bit 0 NVMOP WR: Write Control bit 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete 0 = Program or erase operation is complete and inactive WREN: Write Enable bit 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations WRERR: Write Sequence Error Flag bit 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally Unimplemented: Read as ‘0’ ERASE: Erase/Program Enable bit 1 = Perform the erase operation specified by NVMOP on the next WR command 0 = Perform the program operation specified by NVMOP on the next WR command Unimplemented: Read as ‘0’ NVMOP: NVM Operation Select bits(2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0) 1110 = Reserved 1101 = Erase General Segment and FGS Configuration Register (ERASE = 1) or no operation (ERASE = 0) 1100 = Erase Secure Segment and FSS Configuration Register (ERASE = 1) or no operation (ERASE = 0) 1011-0100 = Reserved 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) 0000 = Program or erase a single Configuration register byte bit 14 bit 13 bit 12-7 bit 6 bit 5-4 bit 3-0 Note 1: These bits can only be reset on POR. 2: All other combinations of NVMOP are unimplemented. © 2009 Microchip Technology Inc. Preliminary DS70592A-page 61 PIC24HJXXXGPX06A/X08A/X10A 5.4.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of program Flash memory at a time. To do this, it is necessary to erase the 8-row erase page that contains the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the page (see Example 5-1): a) Set the NVMOP bits (NVMCON) to ‘0010’ to configure for block erase. Set the ERASE (NVMCON) and WREN (NVMCON) bits. b) Write the starting address of the page to be erased into the TBLPAG and W registers. c) Perform a dummy table write operation (TBLWTL) to any address within the page that needs to be erased. d) Write 0x55 to NVMKEY. e) Write 0xAA to NVMKEY. f) Set the WR bit (NVMCON). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. Write the first 64 instructions from data RAM into the program memory buffers (see Example 5-2). Write the program block to Flash memory: a) Set the NVMOP bits to ‘0001’ to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 0x55 to NVMKEY. c) Write 0xAA to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. 6. For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 5-3. EXAMPLE 5-1: ERASING A PROGRAM MEMORY PAGE ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR Initialize PM Page Boundary SFR Initialize in-page EA pointer Set base address of erase block Block all interrupts with priority -1 2 2 — — 68.5 80 — 11.09 -2 >-1 1.25 1.25 — 12 data bits — — 1.5 1.52 — 12 data bits — — 3 3 — — 69.5 — — 11.3 +2 -1 1 1 — 10 data bits — — 3 2 — 10 data bits — — 5 2 — — 58.5 — — 9.4 +1