PIC32MX120F032D

PIC32MX1XX/2XX 32-bit Microcontrollers (up to 128 KB Flash and 32 KB SRAM) with Audio and Graphics Interfaces, USB, and Advanced Analog Operating Conditions • 2.3V to 3.6V, -40ºC to +105ºC, DC to 40 MHz Timers/Output Compare/Input Capture • Five General Purpose Timers: - Five 16-bit and up to two 32-bit Timers/Counters • Five Output Compare (OC) modules • Five Input Capture (IC) modules • Peripheral Pin Select (PPS) to allow function remap • Real-Time Clock and Calendar (RTCC) module Core: 40 MHz MIPS32® M4K® • • • • MIPS16e® mode for up to 40% smaller code size 1.56 DMIPS/MHz (Dhrystone 2.1) performance Code-efficient (C and Assembly) architecture Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply Clock Management • • • • • 0.9% internal oscillator Programmable PLLs and oscillator clock sources Fail-Safe Clock Monitor (FSCM) Independent Watchdog Timer Fast wake-up and start-up Communication Interfaces • USB 2.0-compliant Full-speed OTG controller • Two UART modules (10 Mbps) - Supports LIN 2.0 protocols and IrDA® support • Two 4-wire SPI modules (20 Mbps) • Two I2C modules (up to 1 Mbaud) with SMBus support • Peripheral Pin Select (PPS) to allow function remap • Parallel Master Port (PMP) Power Management • • • • Low-power management modes (Sleep, Idle) Integrated Power-on Reset and Brown-out Reset 0.5 mA/MHz dynamic current (typical) 20 μA IPD current (typical) Direct Memory Access (DMA) • Four channels of hardware DMA with automatic data size detection • Two additional channels dedicated for USB • Programmable Cyclic Redundancy Check (CRC) Audio Interface Features • Data communication: I2S, LJ, RJ, DSP modes • Control interface: SPI and I2C™ • Master clock: - Generation of fractional clock frequencies - Can be synchronized with USB clock - Can be tuned in run-time Input/Output • • • • 15 mA source/sink on all I/O pins 5V-tolerant pins Selectable open drain, pull-ups, and pull-downs External interrupts on all I/O pins Advanced Analog Features • ADC Module: - 10-bit 1.1 Msps rate with one S&H - Up to 10 analog inputs on 28-pin devices and 13 analog inputs on 44-pin devices • Flexible and independent ADC trigger sources • Charge Time Measurement Unit (CTMU): - Supports mTouch™ capacitive touch sensing - Provides high-resolution time measurement (1 ns) - On-chip temperature measurement capability • Comparators: - Up to three Analog Comparator modules - Programmable references with 32 voltage points Qualification and Class B Support • AEC-Q100 REVG (Grade 2 -40ºC to +105ºC) planned • Class B Safety Library, IEC 60730 Debugger Development Support • • • • In-circuit and in-application programming 4-wire MIPS® Enhanced JTAG interface Unlimited program and six complex data breakpoints IEEE 1149.2-compatible (JTAG) boundary scan Packages Type Pin Count I/O Pins (up to) Contact/Lead Pitch Dimensions Note: SOIC 28 21 1.27 17.90x7.50x2.65 SSOP 28 21 0.65 10.2x5.3x2 SPDIP 28 21 0.100'' 1.365x.285x.135'' 28 21 0.65 6x6x0.9 QFN 44 34 0.65 8x8x0.9 36 25 0.50 5x5x0.9 VTLA 44 34 0.50 6x6x0.9 TQFP 44 34 0.80 10x10x1 All dimensions are in millimeters (mm) unless specified. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 1 PIC32MX1XX/2XX TABLE 1: PIC32MX1XX GENERAL PURPOSE FAMILY FEATURES Timers(2)/Capture/Compare 10-bit 1 Msps ADC (Channels) DMA Channels (Programmable/Dedicated) Remappable Peripherals Program Memory (KB)(1) External Interrupts(3) USB On-The-Go (OTG) Analog Comparators Data Memory (KB) Remappable Pins SPI/I2S UART PIC32MX110F016B PIC32MX110F016C PIC32MX110F016D 28 36 44 16+3 16+3 16+3 4 4 4 20 24 32 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 N N N 2 2 2 Y Y Y 4/0 4/0 4/0 Y Y Y 10 12 13 Y Y Y 21 25 34 Y Y Y SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN PIC32MX120F032B PIC32MX120F032C PIC32MX120F032D 28 36 44 32+3 32+3 32+3 8 8 8 20 24 32 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 N N N 2 2 2 Y Y Y 4/0 4/0 4/0 Y Y Y 10 12 13 Y Y Y 21 25 34 Y Y Y PIC32MX130F064B PIC32MX130F064C PIC32MX130F064D 28 36 44 64+3 64+3 64+3 16 16 16 20 24 32 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 N N N 2 2 2 Y Y Y 4/0 4/0 4/0 Y Y Y 10 12 13 Y Y Y 21 25 34 Y Y Y PIC32MX150F128B PIC32MX150F128C PIC32MX150F128D Note 1: 2: 3: 28 128+3 32 36 128+3 32 44 128+3 32 20 24 32 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 N N N 2 2 2 Y Y Y 4/0 4/0 4/0 Y Y Y 10 12 13 Y Y Y 21 25 34 Y Y Y This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. DS61168D-page 2 Preliminary © 2011-2012 Microchip Technology Inc. Packages I/O Pins Device CTMU RTCC JTAG I2C™ PMP Pins PIC32MX1XX/2XX TABLE 2: PIC32MX2XX USB FAMILY FEATURES Timers(2)/Capture/Compare 10-bit 1 Msps ADC (Channels) DMA Channels (Programmable/Dedicated) Remappable Peripherals Program Memory (KB)(1) External Interrupts(3) USB On-The-Go (OTG) Analog Comparators Data Memory (KB) Remappable Pins SPI/I2S UART PIC32MX210F016B PIC32MX210F016C PIC32MX210F016D 28 36 44 16+3 16+3 16+3 4 4 4 19 23 31 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 Y Y Y 2 2 2 Y Y Y 4/2 4/2 4/2 Y Y Y 9 12 13 Y Y Y 19 23 33 Y Y Y SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN SOIC, SSOP, SPDIP, QFN VTLA VTLA, TQFP, QFN PIC32MX220F032B PIC32MX220F032C PIC32MX220F032D 28 36 44 32+3 32+3 32+3 8 8 8 19 23 31 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 Y Y Y 2 2 2 Y Y Y 4/2 4/2 4/2 Y Y Y 9 12 13 Y Y Y 19 23 33 Y Y Y PIC32MX230F064B PIC32MX230F064C PIC32MX230F064D 28 36 44 64+3 64+3 64+3 16 16 16 19 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 Y Y Y 2 2 2 Y Y Y 4/2 4/2 4/2 Y Y Y 9 12 13 Y Y Y 19 23 33 Y Y Y 23 31 PIC32MX250F128B PIC32MX250F128C PIC32MX250F128D Note 1: 2: 3: 28 128+3 32 36 128+3 32 44 128+3 32 19 5/5/5 5/5/5 5/5/5 2 2 2 2 2 2 5 5 5 3 3 3 Y Y Y 2 2 2 Y Y Y 4/2 4/2 4/2 Y Y Y 9 12 13 Y Y Y 19 23 33 Y Y Y 23 31 This device features 3 KB of boot Flash memory. Four out of five timers are remappable. Four out of five external interrupts are remappable. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 3 Packages I/O Pins Device CTMU RTCC JTAG I2C™ PMP Pins PIC32MX1XX/2XX Pin Diagrams 28-Pin SOIC, SPDIP, SSOP(1,2) = Pins are up to 5V tolerant MCLR MCLR VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD PGED3/RPB5/PMD7/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN11/RPB13/CTPLS/PMRD/RB13 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX150F128B MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD TMS/RPB5/USBID/RB5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AN11/RPB13/CTPLS/PMRD/RB13 VUSB3V3 PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 VBUS PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX250F128B Note 1: 2: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. DS61168D-page 4 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) = Pins are up to 5V tolerant 28 27 26 25 24 23 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 1 2 3 4 5 6 7 10 11 12 13 14 8 9 22 21 20 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 MCLR AVDD AVSS AN11/RPB13/CTPLS/PMRD/RB13 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 PIC32MX110F016B PIC32MX120F032B PIC32MX130F064B PIC32MX150F128B 19 18 17 16 15 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2011-2012 Microchip Technology Inc. Preliminary TCK/RPB8/SCL1/CTED10/PMD4/RB8 TDI/RPB7/CTED3/PMD5/INT0/RB7 SOSCI/RPB4/RB4 PGED3/RPB5/PMD7/RB5 PGEC3/RPB6/PMD6/RB6 VDD DS61168D-page 5 PIC32MX1XX/2XX Pin Diagrams (Continued) 28-Pin QFN(1,2,3) = Pins are up to 5V tolerant PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 MCLR 28 27 26 25 24 23 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 1 2 3 4 5 6 7 22 21 20 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 AVDD AVSS AN11/RPB13/CTPLS/PMRD/RB13 VUSB3V3 PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VCAP VSS TDO/RPB9/SDA1/CTED4/PMD3/RB9 PIC32MX210F016B PIC32MX220F032B PIC32MX230F064B PIC32MX250F128B 10 11 12 13 TDI/RPB7/CTED3/PMD5/INT0/RB7 14 TCK/RPB8/SCL1/CTED10/PMD4/RB8 19 18 17 16 15 8 9 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 VDD SOSCI/RPB4/RB4 Note 1: 2: 3: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61168D-page 6 Preliminary TMS/RPB5/USBID/RB5 VBUS © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 28 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 36 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 PGED(4)/AN6/RPC0/RC0 PGEC(4)/AN7/RPC1/RC1 VDD VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 1 2 3 4 5 6 7 8 9 35 34 33 32 31 30 29 AN11/RPB13/CTPLS/PMRD/RB13 27 26 25 24 AN12/PMD0/RB12 PGEC2/TMS/RPB11/PMD1/RB11 PGED2/RPB10/CTED11/PMD2/RB10 VDD VCAP VSS RPC9/CTED7/RC9 TDO/RPB9/SDA1/CTED4/PMD3/RB9 23 22 21 20 19 18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 MCLR AVDD PIC32MX110F016C PIC32MX120F032C PIC32MX130F064C PIC32MX150F128C AVSS 15 PGED3/RPB5/PMD7/RB5 10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 11 RPC3/RC3 12 VSS 13 VDD 14 VDD 16 17 PGEC3/RPB6/PMD6/RB6 TDI/RPB7/CTED3/PMD5/INT0/RB7 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064C and PIC32MX150F128C devices only. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 7 PIC32MX1XX/2XX Pin Diagrams (Continued) 36-Pin VTLA(1,2,3) = Pins are up to 5V tolerant PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 28 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 MCLR AVDD 36 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/RB2 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/RB3 PGED4(4)/AN6/RPC0/RC0 PGEC4(4)/AN7/RPC1/RC1 VDD VSS OSC1/CLKI/RPA2/RA2 OSC2/CLKO/RPA3/PMA0/RA3 SOSCI/RPB4/RB4 1 2 3 4 5 6 7 8 9 35 34 AVSS 33 32 31 30 29 AN11/RPB13/CTPLS/PMRD/RB13 27 26 25 24 VUSB3V3 PGEC2/RPB11/D-/RB11 PGED2/RPB10/D+/CTED11/RB10 VDD VCAP VSS RPC9/CTED7/RC9 TDO/RPB9/SDA1/CTED4/PMD3/RB9 23 22 21 20 19 18 TCK/RPB8/SCL1/CTED10/PMD4/RB8 PIC32MX210F016C PIC32MX220F032C PIC32MX230F064C PIC32MX250F128C 10 SOSCO/RPA4/T1CK/CTED9/PMA1/RA4 11 AN12/RPC3/RC3 12 VSS 13 VDD 14 VDD 15 TMS/RPB5/USBID/RB5 16 17 TDI/RPB7/CTED3/PMD5/INT0/RB7 VBUS Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064C and PIC32MX250F128C devices only. DS61168D-page 8 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3) = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 33 32 31 30 SOSCO/RPA4/T1CK/CTED9/RA4 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 TDI/RPA9/PMA9/RA9 RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 VDD VSS SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D 29 28 27 26 25 24 23 AVDD AVSS PGEC(4)/TCK/CTED8/PMA7/RA7 MCLR VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGED4(4)/TMS/PMA10/RA10 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. © 2011-2012 Microchip Technology Inc. Preliminary PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 DS61168D-page 9 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin QFN(1,2,3) = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB3V3 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 33 32 31 30 SOSCO/RPA4/T1CK/CTED9/RA4 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 TDI/RPA9/PMA9/RA9 RPB5/USBID/RB5 RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 VBUS VDD VSS SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D 29 28 27 26 25 24 23 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. DS61168D-page 10 Preliminary PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 PGED(4)/TMS/PMA10/RA10 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 PGEC(4)/TCK/CTED8/PMA7/RA7 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 AVDD AVSS MCLR © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 33 32 31 30 SOSCO/RPA4/T1CK/CTED9/RA4 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 TDI/RPA9/PMA9/RA9 RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 VDD VSS SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D 29 28 27 26 25 24 23 AVDD AVSS CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 MCLR Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. © 2011-2012 Microchip Technology Inc. Preliminary VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 PGEC(4)/TCK/CTED8/PMA7/RA7 PGED(4)/TMS/PMA10/RA10 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 DS61168D-page 11 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant SOSCO/RPA4/T1CK/CTED9/RA4 34 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 PGEC3/RPB6/PMD6/RB6 PGED3/RPB5/PMD7/RB5 TDI/RPA9/PMA9/RA9 44 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/CTED11/PMD2/RB10 PGEC2/RPB11/PMD1/RB11 AN12/PMD0/RB12 1 2 3 4 5 6 7 8 9 10 11 AN11/RPB13/CTPLS/PMRD/RB13 43 42 41 40 39 38 37 36 35 33 32 31 30 29 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/RB2 PIC32MX110F016D PIC32MX120F032D PIC32MX130F064D PIC32MX150F128D 28 27 26 25 24 23 12 PGED(4)/TMS/PMA10/RA10 13 PGEC /TCK/CTED8/PMA7/RA7 14 CVREF/AN10/C3INB/RPB14/SCK1/CTED5/PMWR/RB14 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 16 AVSS 17 AVDD 18 MCLR 19 VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/RA0 20 VREF-/CVREF-/AN1/RPA1/CTED2/RA1 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/RB0 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/RB1 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX130F064D and PIC32MX150F128D devices only. (4) DS61168D-page 12 Preliminary SOSCI/RPB4/RB4 RPC5/PMA3/RC5 RPC4/PMA4/RC4 RPC3/RC3 VDD VSS © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin TQFP(1,2,3) = Pins are up to 5V tolerant 44 43 42 41 40 39 38 37 36 35 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB3V3 AN11/RPB13/CTPLS/PMRD/RB13 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 34 33 32 31 30 29 28 27 26 25 24 23 SOSCO/RPA4/T1CK/CTED9/RA4 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 TDI/RPA9/PMA9/RA9 RPB5/USBID/RB5 RPC5/PMA3/RC5 RPC4/PMA4/RC4 AN12/RPC3/RC3 VBUS VDD VSS SOSCI/RPB4/RB4 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 AVDD AVSS MCLR PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 PGEC(4)/TCK/CTED8/PMA7/RA7 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 PGED(4)/TMS/PMA10/RA10 Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. © 2011-2012 Microchip Technology Inc. Preliminary PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 DS61168D-page 13 PIC32MX1XX/2XX Pin Diagrams (Continued) 44-Pin VTLA(1,2,3) = Pins are up to 5V tolerant SOSCO/RPA4/T1CK/CTED9/RA4 34 RPB8/SCL1/CTED10/PMD4/RB8 RPB7/CTED3/PMD5/INT0/RB7 TDI/RPA9/PMA9/RA9 RPB5/USBID/RB5 RPC4/PMA4/RC4 VSS AN12/RPC3/RC3 44 RPB9/SDA1/CTED4/PMD3/RB9 RPC6/PMA1/RC6 RPC7/PMA0/RC7 RPC8/PMA5/RC8 RPC9/CTED7/PMA6/RC9 VSS VCAP PGED2/RPB10/D+/CTED11/RB10 PGEC2/RPB11/D-/RB11 VUSB3V3 1 2 3 4 5 6 7 8 9 10 11 AN11/RPB13/CTPLS/PMRD/RB13 43 42 41 40 39 38 37 36 35 33 32 31 30 29 TDO/RPA8/PMA8/RA8 OSC2/CLKO/RPA3/RA3 OSC1/CLKI/RPA2/RA2 VSS VDD AN8/RPC2/PMA2/RC2 AN7/RPC1/RC1 AN6/RPC0/RC0 AN5/C1INA/C2INC/RTCC/RPB3/SCL2/PMWR/CNB3/RB3 AN4/C1INB/C2IND/RPB2/SDA2/CTED13/PMD2/CNB2/RB2 PIC32MX210F016D PIC32MX220F032D PIC32MX230F064D PIC32MX250F128D 28 27 26 25 24 23 12 PGED /TMS/PMA10/RA10 13 PGEC /TCK/CTED8/PMA7/RA7 14 CVREF/AN10/C3INB/RPB14/VBUSON/SCK1/CTED5/RB14 15 AN9/C3INA/RPB15/SCK2/CTED6/PMCS1/RB15 16 AVSS 17 AVDD 18 MCLR 19 PGED3/VREF+/CVREF+/AN0/C3INC/RPA0/CTED1/PMD7/RA0 20 PGEC3/VREF-/CVREF-/AN1/RPA1/CTED2/PMD6/RA1 21 PGED1/AN2/C1IND/C2INB/C3IND/RPB0/PMD0/RB0 22 PGEC1/AN3/C1INC/C2INA/RPB1/CTED12/PMD1/RB1 (4) Note 1: 2: 3: 4: The RPn pins can be used by remappable peripherals. See Table 1 for the available peripherals and Section 11.3 “Peripheral Pin Select” for restrictions. Every I/O port pin (RAx-RCx) can be used as a change notification pin (CNAx-CNCx). See Section 11.0 “I/O Ports” for more information. The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. This pin function is available on PIC32MX230F064D and PIC32MX250F128D devices only. (4) DS61168D-page 14 Preliminary SOSCI/RPB4/RB4 VBUS RPC5/PMA3/RC5 VDD © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 19 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 27 3.0 CPU............................................................................................................................................................................................ 33 4.0 Memory Organization ................................................................................................................................................................. 37 5.0 Flash Program Memory.............................................................................................................................................................. 79 6.0 Resets ........................................................................................................................................................................................ 83 7.0 Interrupt Controller ..................................................................................................................................................................... 87 8.0 Oscillator Configuration .............................................................................................................................................................. 95 9.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 105 10.0 USB On-The-Go (OTG)............................................................................................................................................................ 121 11.0 I/O Ports ................................................................................................................................................................................... 143 12.0 Timer1 ...................................................................................................................................................................................... 151 13.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 155 14.0 Input Capture............................................................................................................................................................................ 159 15.0 Output Compare....................................................................................................................................................................... 163 16.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 165 17.0 Inter-Integrated Circuit™ (I2C™).............................................................................................................................................. 173 18.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 179 19.0 Parallel Master Port (PMP)....................................................................................................................................................... 185 20.0 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 193 21.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 203 22.0 Comparator .............................................................................................................................................................................. 211 23.0 Comparator Voltage Reference (CVREF) ................................................................................................................................. 215 24.0 Charge Time Measurement Unit (CTMU) ............................................................................................................................... 217 25.0 Power-Saving Features ........................................................................................................................................................... 221 26.0 Special Features ...................................................................................................................................................................... 225 27.0 Instruction Set .......................................................................................................................................................................... 239 28.0 Development Support............................................................................................................................................................... 241 29.0 Electrical Characteristics .......................................................................................................................................................... 245 30.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 285 31.0 Packaging Information.............................................................................................................................................................. 289 The Microchip Web Site ..................................................................................................................................................................... 315 Customer Change Notification Service .............................................................................................................................................. 315 Customer Support .............................................................................................................................................................................. 315 Reader Response .............................................................................................................................................................................. 316 Product Identification System ............................................................................................................................................................ 317 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 15 PIC32MX1XX/2XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. DS61168D-page 16 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note: To access the documents listed below, browse to the documentation section of the Microchip web site (www.microchip.com). • • • • • • • • • • • • • • • • • • • • • • • • • • Section 1. “Introduction” (DS61127) Section 2. “CPU” (DS61113) Section 3. “Memory Organization” (DS61115) Section 5. “Flash Program Memory” (DS61121) Section 6. “Oscillator Configuration” (DS61112) Section 7. “Resets” (DS61118) Section 8. “Interrupt Controller” (DS61108) Section 9. “Watchdog Timer and Power-up Timer” (DS61114) Section 10. “Power-Saving Features” (DS61130) Section 12. “I/O Ports” (DS61120) Section 13. “Parallel Master Port (PMP)” (DS61128) Section 14. “Timers” (DS61105) Section 15. “Input Capture” (DS61122) Section 16. “Output Compare” (DS61111) Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) Section 19. “Comparator” (DS61110) Section 20. “Comparator Voltage Reference (CVREF)” (DS61109) Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) Section 23. “Serial Peripheral Interface (SPI)” (DS61106) Section 24. “Inter-Integrated Circuit™ (I2C™)” (DS61116) Section 27. “USB On-The-Go (OTG)” (DS61126) Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) Section 31. “Direct Memory Access (DMA) Controller” (DS61117) Section 32. “Configuration” (DS61124) Section 33. “Programming and Diagnostics” (DS61129) Section 37. “Charge Time Measurement Unit (CTMU)” (DS61167) © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 17 PIC32MX1XX/2XX NOTES: DS61168D-page 18 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX1XX/2XX devices. Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX1XX/2XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 1-1: BLOCK DIAGRAM(1) OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators PLL Dividers PLL-USB Timing Generation VCAP Power-up Timer Voltage Regulator Precision Band Gap Reference USBCLK SYSCLK PBCLK Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset CTMU Timer1-5 PWM OC1-5 VDD, VSS MCLR Peripheral Bus Clocked by SYSCLK PORTA JTAG BSCAN PORTB USB EJTAG PORTC 32 Remappable Pins INT Priority Interrupt Controller DMAC ICD 32 MIPS32® M4K® CPU Core IS 32 DS 32 32 Bus Matrix 32 128 Data RAM Peripheral Bridge 32 32 32 Peripheral Bus Clocked by PBCLK IC1-5 SPI1-2 I2C1-2 32 PMP 10-bit ADC 128-bit Wide Program Flash Memory Flash Controller UART1-2 RTCC Comparators 1-3 Note 1: Some features are not available on all device variants. Refer to the family features tables (Table 1 and Table 2) for availability. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 19 PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS Pin Number(1) Pin Name 28-pin QFN 27 28 1 2 3 4 — — — 23 22 21 20(2) 6 28-pin SSOP/ SPDIP/ SOIC 2 3 4 5 6 7 — — — 26 25 24 23(2) 9 36-pin VTLA 33 34 35 36 1 2 3 4 — 29 28 27 26(2) 11(3) 7 44-pin QFN/ TQFP/ VTLA 19 20 21 22 23 24 25 26 27 15 14 11 10(2) 36(3) 30 Pin Type Buffer Type Description AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 CLKI I I I I I I I I I I I I I I Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog input channels. ST/CMOS External clock source input. Always associated with OSC1 pin function. CLKO 7 10 8 31 O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. OSC1 6 9 7 30 I ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. OSC2 7 10 8 31 I/O — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI 8 11 9 33 I ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. SOSCO 9 12 10 34 O — 32.768 kHz low-power oscillator crystal output. REFCLKI PPS PPS PPS PPS I ST Reference Input Clock REFCLKO PPS PPS PPS PPS O — Reference Output Clock IC1 PPS PPS PPS PPS I ST Capture Inputs 1-5 IC2 PPS PPS PPS PPS I ST IC3 PPS PPS PPS PPS I ST IC4 PPS PPS PPS PPS I ST IC5 PPS PPS PPS PPS I ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168D-page 20 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN PPS PPS PPS PPS PPS PPS PPS 13 PPS PPS PPS PPS 27 28-pin SSOP/ SPDIP/ SOIC PPS PPS PPS PPS PPS PPS PPS 16 PPS PPS PPS PPS 2 36-pin VTLA PPS PPS PPS PPS PPS PPS PPS 17 PPS PPS PPS PPS 33 44-pin QFN/ TQFP/ VTLA PPS PPS PPS PPS PPS PPS PPS 43 PPS PPS PPS PPS 19 Pin Type Buffer Type Description ST PORTA is a bidirectional I/O port RA1 28 3 34 20 ST RA2 6 9 7 30 ST RA3 7 10 8 31 ST RA4 9 12 10 34 ST RA7 — — — 13 ST RA8 — — — 32 ST RA9 — — — 35 ST RA10 — — — 12 ST RB0 1 4 35 21 ST PORTB is a bidirectional I/O port RB1 2 5 36 22 ST RB2 3 6 1 23 ST RB3 4 7 2 24 ST RB4 8 11 9 33 ST RB5 11 14 15 41 ST 15(2) 16(2) 42(2) ST RB6 12(2) RB7 13 16 17 43 ST RB8 14 17 18 44 ST RB9 15 18 19 1 ST RB10 18 21 24 8 ST RB11 19 22 25 9 ST (2) (2) (2) (2) 23 26 10 ST RB12 20 RB13 21 24 27 11 ST RB14 22 25 28 14 ST RB15 23 26 29 15 ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. OC1 OC2 OC3 OC4 OC5 OCFA OCFB INT0 INT1 INT2 INT3 INT4 RA0 O O O O O I I I I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O — — — — — ST ST ST ST ST ST ST Output Compare Output 1 Output Compare Output 2 Output Compare Output 3 Output Compare Output 4 Output Compare Output 5 Output Compare Fault A Input Output Compare Fault B Input External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 21 PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN — — — — — — — — — — 9 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 22 PPS PPS PPS 23 PPS PPS PPS 28-pin SSOP/ SPDIP/ SOIC — — — — — — — — — — 12 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 25 PPS PPS PPS 26 PPS PPS PPS 36-pin VTLA 3 4 — 11 — — — — — 20 10 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 28 PPS PPS PPS 29 PPS PPS PPS 44-pin QFN/ TQFP/ VTLA 25 26 27 36 37 38 2 3 4 5 34 PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS PPS 14 PPS PPS PPS 15 PPS PPS PPS Pin Type Buffer Type Description RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RC8 RC9 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U2CTS U2RTS U2RX U2TX SCK1 SDI1 SDO1 SS1 SCK2 SDI2 SDO2 SS2 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I O I O I O I O I/O I O I/O I/O I O I/O ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST — ST — ST — ST ST — ST ST ST — ST PORTC is a bidirectional I/O port Timer1 external clock input Timer2 external clock input Timer3 external clock input Timer4 external clock input Timer5 external clock input UART1 clear to send UART1 ready to send UART1 receive UART1 transmit UART2 clear to send UART2 ready to send UART2 receive UART2 transmit Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 slave synchronization or frame pulse I/O SCL1 14 17 18 44 I/O ST Synchronous serial clock input/output for I2C1 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168D-page 22 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN 15 4 3 19(2) 11(3) 14 13 15 4 28 27 22 4 28-pin SSOP/ SPDIP/ SOIC 18 7 6 22(2) 14(3) 17 16 18 7 3 2 25 7 36-pin VTLA 19 2 1 25(2) 15(3) 18 17 19 2 34 33 28 2 44-pin QFN/ TQFP/ VTLA 1 24 23 12 13 35 32 24 20 19 14 24 Pin Type Buffer Type Description SDA1 SCL2 SDA2 TMS TCK TDI TDO RTCC CVREFCVREF+ CVREFOUT C1INA I/O I/O I/O I I O O I I I O ST ST ST ST ST — — ST Analog Analog Analog Synchronous serial data input/output for I2C1 Synchronous serial clock input/output for I2C2 Synchronous serial data input/output for I2C2 JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Real-Time Clock alarm output Comparator Voltage Reference (low) Comparator Voltage Reference (high) Comparator Voltage Reference output I Analog Comparator Inputs C1INB 3 6 1 23 I Analog C1INC 2 5 36 22 I Analog C1IND 1 4 35 21 I Analog C2INA 2 5 36 22 I Analog C2INB 1 4 35 21 I Analog C2INC 4 7 2 24 I Analog C2IND 3 6 1 23 I Analog C3INA 23 26 29 15 I Analog C3INB 22 25 28 14 I Analog C3INC 27 2 33 19 I Analog C3IND 1 4 35 21 I Analog C1OUT PPS PPS PPS PPS O — Comparator Outputs C2OUT PPS PPS PPS PPS O — C3OUT PPS PPS PPS PPS O — Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 23 PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN 7 28-pin SSOP/ SPDIP/ SOIC 10 36-pin VTLA 8 44-pin QFN/ TQFP/ VTLA 3 Pin Type Buffer Type Description PMA0 I/O TTL/ST PMA1 9 12 10 2 I/O TTL/ST PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMCS1 PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMRD PMWR VBUS VUSB3V3 23 20(2) 1(3) 19(2) 2(3) 18(2) 3(3) 15 14 13 12(2) 28(3) 11(2) 27(3) 21 22(2) 4(3) 12 20 — — — — — — — — — 26 23(2) 4(3) 22(2) 5(3) 21(2) 6(3) 18 17 16 15(2) 3(3) 14(2) 2(3) 24 25(2) 7(3) 15 23 — — — — — — — — — 29 26(2) 35(3) 25(2) 36(3) 24(2) 1(3) 19 18 17 16(2) 34(3) 15(2) 33(3) 27 28(2) 2(3) 16 26 27 38 37 4 5 13 32 35 12 15 10(2) 21(3) 9(2) 22(3) 8(2) 23(3) 1 44 43 42(2) 20(3) 41(2) 19(3) 11 14(2) 24(3) 42 10 O O O O O O O O O O I/O I/O I/O I/O I/O I/O I/O I/O O O I P — — — — — — — — — — TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST — — Analog — Parallel Master Port Address bit 0 input (Buffered Slave modes) and output (Master modes) Parallel Master Port Address bit 1 input (Buffered Slave modes) and output (Master modes) Parallel Master Port address (Demultiplexed Master modes) Parallel Master Port Chip Select 1 strobe Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes) Parallel Master Port read strobe Parallel Master Port write strobe USB bus power monitor USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. 22 25 28 14 O — USB Host and OTG bus power control VBUSON output D+ 18 21 24 8 I/O Analog USB D+ D19 22 25 9 I/O Analog USB DLegend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. DS61168D-page 24 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN 11 27 28 13 15 22 23 — — 9 14 18 2 3 21 1 2 28-pin SSOP/ SPDIP/ SOIC 14 2 3 16 18 25 26 — — 12 17 21 5 6 24 4 5 36-pin VTLA 15 33 34 17 19 28 29 20 — 10 18 24 36 1 27 35 36 44-pin QFN/ TQFP/ VTLA 41 19 20 43 1 14 15 5 13 34 44 8 22 23 11 21 22 Pin Type Buffer Type Description USBID CTED1 CTED2 CTED3 CTED4 CTED5 CTED6 CTED7 CTED8 CTED9 CTED10 CTED11 CTED12 CTED13 CTPLS PGED1 PGEC1 I I I I I I I I I I I I I I O I/O I ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST ST USB OTG ID detect CTMU External Edge Input PGED2 PGEC2 18 19 21 22 24 25 8 9 I/O I ST ST PGED3 PGEC3 PGED4 Data I/O pin for Programming/Debugging Communication Channel 4 PGEC4 — — 4 13 Clock input pin for Programming/ I ST Debugging Communication Channel 4 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. I/O ST 11(2) 27(3) 12(2) 28(3) — 14(2) 2(3) 15(2) 3(3) — 15(2) 33(3) 16(2) 34(3) 3 41(2) 19(3) 42(2) 20(3) 12 I/O I ST ST CTMU Pulse Output Data I/O pin for Programming/Debugging Communication Channel 1 Clock input pin for Programming/Debugging Communication Channel 1 Data I/O pin for Programming/Debugging Communication Channel 2 Clock input pin for Programming/Debugging Communication Channel 2 Data I/O pin for Programming/Debugging Communication Channel 3 Clock input pin for Programming/ Debugging Communication Channel 3 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 25 PIC32MX1XX/2XX TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) Pin Name 28-pin QFN 26 28-pin SSOP/ SPDIP/ SOIC 1 36-pin VTLA 32 44-pin QFN/ TQFP/ VTLA 18 Pin Type Buffer Type Description Master Clear (Reset) input. This pin is an active-low Reset to the device. 25 28 31 17 P — Positive supply for analog modules. This AVDD pin must be connected at all times. 24 27 30 16 P — Ground reference for analog modules AVSS 10 13 5, 13, 14, 28, 40 P — Positive supply for peripheral logic and VDD 23 I/O pins 17 20 22 7 P — CPU logic filter capacitor connection VCAP VSS 5, 16 8, 19 6, 12, 21 6, 29, 39 P — Ground reference for logic and I/O pins. This pin must be connected at all times. 27 2 33 19 I Analog Analog voltage reference (high) input VREF+ 28 3 34 20 I Analog Analog voltage reference (low) input VREFLegend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer PPS = Peripheral Pin Select — = N/A Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: Pin number for PIC32MX1XX devices only. 3: Pin number for PIC32MX2XX devices only. MCLR I/P ST DS61168D-page 26 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (lowESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC32MX1XX/2XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins, even if the ADC module is not used (see Section 2.2 “Decoupling Capacitors”) • VCAP pin (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins, used for In-Circuit Serial Programming (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins, when external oscillator source is used (see Section 2.7 “External Oscillator Pins”) The following pin may be required, as well: VREF+/VREF- pins, used when external voltage reference for the ADC module is implemented. Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source. FIGURE 2-1: VDD RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic CBP VDD VSS VDD VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP AVDD AVSS VDD 0.1 µF Ceramic CBP VSS CEFC R1 MCLR C PIC32 VSS VDD VCAP R VUSB3V3(1) 0.1 µF Ceramic CBP 2.2 Decoupling Capacitors 10Ω The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Note 1: If the USB module is not used, this pin must be connected to VDD. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 27 PIC32MX1XX/2XX 2.2.1 BULK CAPACITORS 2.4 Master Clear (MCLR) Pin The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. 2.3 2.3.1 Capacitor on Internal Voltage Regulator (VCAP) INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP pin, which is used to stabilize the internal voltage regulator output. The VCAP pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 29.0 “Electrical Characteristics” for additional information on CEFC specifications. FIGURE 2-2: VDD R(1) EXAMPLE OF MCLR PIN CONNECTIONS R1(2) MCLR PIC32 JP C(3) Note 1: R ≤10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 2: 3: DS61168D-page 28 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 2.5 ICSP Pins 2.6 JTAG The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 3 or MPLAB REAL ICE™. For more information on ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Debugger User’s Guide” DS51616 • “Using MPLAB® REAL ICE™ Emulator” (poster) DS51749 The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 29 PIC32MX1XX/2XX 2.7 External Oscillator Pins 2.8 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 “Oscillator Configuration” for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the analog-todigital input pins (ANx) as “digital” pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the analogto-digital pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain analog-to-digital pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all analog-to-digital pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.9 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. DS61168D-page 30 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 2.10 Typical Application Connection Examples Examples of typical application connections are shown in Figure 2-4 and Figure 2-5. FIGURE 2-4: CAPACITIVE TOUCH SENSING WITH GRAPHICS APPLICATION PIC32MX120F032D Current Source To AN6 To AN0 AN0 R1 C1 ADC Read the Touch Sensors Microchip mTouch™ Library Process Samples AN11 User Application Display Data Microchip Graphics Library Parallel Master Port PMPD PMPWR LCD Controller Frame Buffer Display Controller LCD Panel AN1 To AN1 R2 C1 R2 C2 R2 C3 R2 C4 R2 C5 R1 C2 R1 C3 R1 C4 R1 C5 To AN7 To AN8 To AN9 To AN11 CTMU AN9 To AN5 R3 C1 R3 C2 R3 C3 R3 C4 R3 C5 FIGURE 2-5: AUDIO PLAYBACK APPLICATION PMPD USB PMP PMPWR Display USB Host PIC32MX220F032D I2S 3 Audio Codec SPI 3 Speaker Stereo Headphones 3 MMC SD SDI © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 31 PIC32MX1XX/2XX NOTES: DS61168D-page 32 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS61113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The the MIPS32® M4K® Processor Core is the heart of the PIC32MX1XX/2XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. - Programmable exception vector base - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e® code compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple dual bus interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous multiply/divide unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG debug and instruction trace - Support for single stepping - Virtual instruction and data address/value - Breakpoints • • • • 3.1 Features • 5-stage pipeline • 32-bit address and data paths • MIPS32® Enhanced Architecture (Release 2) - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts • • FIGURE 3-1: CPU MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM EJTAG TAP Execution Core (RF/ALU/Shift) Off-Chip Debug I/F Dual Bus I/F Bus Matrix DS61168D-page 33 MDU FMT Bus Interface System Coprocessor Power Management © 2011-2012 Microchip Technology Inc. Preliminary PIC32MX1XX/2XX 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The MIPS32® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller The MIPS32® M4K® processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. 3.2.1 EXECUTION UNIT The MIPS32® M4K® processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and store aligner TABLE 3-1: MIPS32® M4K® PROCESSOR CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32 MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU DS61168D-page 34 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32® architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2. TABLE 3-2: Register Number 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2: COPROCESSOR 0 REGISTERS Register Name Function Reserved in the PIC32MX1XX/2XX family core. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved in the PIC32MX1XX/2XX family core. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved in the PIC32MX1XX/2XX family core. Debug control and exception status. Program counter at last debug exception. Reserved in the PIC32MX1XX/2XX family core. Program counter at last error. Reserved HWREna BadVAddr(1) Count(1) Reserved Compare(1) Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Debug handler scratchpad register. Registers used in exception processing. Registers used during debug. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 35 PIC32MX1XX/2XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL MIPS32® M4K® PROCESSOR CORE EXCEPTION TYPES Description Assertion MCLR or a Power-on Reset (POR). EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. 3.3 Power Management MIPS® M4K® 3.4 EJTAG Debug Support The processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 25.0 “Power-Saving Features”. The MIPS® M4K® processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the M4K® core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. DS61168D-page 36 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source.For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 4.1 PIC32MX1XX/2XX Memory Layout PIC32MX1XX/2XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX1XX/2XX devices are illustrated in Figure 4-1 and Figure 4-2. PIC32MX1XX/2XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX1XX/2XX devices to execute from data memory. Key features include: • 32-bit native data width • Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space • Flexible program Flash memory partitioning • Flexible data RAM partitioning for data and program space • Separate boot Flash memory for protected code • Robust bus exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable (KSEG0) and non-cacheable (KSEG1) address regions © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 37 PIC32MX1XX/2XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX11X/21X DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD004000 0xBD003FFF Program Flash(2) 0xBD000000 0xA0001000 0xA0000FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF Boot Flash 0x9FC00000 Reserved 0x9D003FFF Program Flash(2) 0x9D000000 0x80001000 0x80000FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00001000 0x00000FFF 0x00000000 KSEG0 0x9D004000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF SFRs 0x1F800000 Reserved 0x1D004000 0x1D003FFF 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61168D-page 38 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX12X/22X DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD008000 0xBD007FFF Program Flash(2) 0xBD000000 0xA0002000 0xA0001FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF Boot Flash 0x9FC00000 Reserved 0x9D007FFF Program Flash(2) 0x9D000000 0x80002000 0x80001FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC00C00 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF SFRs KSEG0 0x1F800000 Reserved 0x1D008000 Reserved 0x1D007FFF Program Flash(2) 0x1D000000 0x00002000 0x00001FFF 0x00000000 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x9D008000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 39 PIC32MX1XX/2XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX13X/23X DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF Boot Flash 0x9FC00000 Reserved 0x9D00FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 KSEG0 0x9D010000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF SFRs 0x1F800000 Reserved 0x1D010000 0x1D00FFFF 0x1FC00C00 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61168D-page 40 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX15X/25X DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC00C00 0xBFC00BFF 0xBFC00BF0 0xBFC00BEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC00C00 0x9FC00BFF 0x9FC00BF0 0x9FC00BEF Boot Flash 0x9FC00000 Reserved 0x9D01FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC00C00 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF SFRs KSEG0 0x1F800000 Reserved 0x1D020000 Reserved 0x1D01FFFF Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 0x1FC00BFF 0x1FC00BF0 0x1FC00BEF 0x9D020000 Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 41 4.1.1 PERIPHERAL REGISTERS LOCATIONS Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 2010 2020 BMXCON(1) BMXDKPBA(1) BMXDUDBA(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — BMXWSDRM — — — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F — — — — — — — — — — — BMXARB — — — — — — 0041 0000 0000 0000 0000 0000 0000 xxxx xxxx BMXDKPBA BMXDUDBA BMXDUPBA BMXDRMSZ — — — — — — — — — — — — BMXPUPBA 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2050 2060 BMXPUPBA(1) BMXPFMSZ 0000 0000 xxxx xxxx 0000 3000 BMXPUPBA BMXPFMSZ BMXBOOTSZ 2070 BMXBOOTSZ Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. All Resets DS61168D-page 42 PIC32MX1XX/2XX Table 4-1 through Table 4-27 contain the peripheral address maps for the PIC32MX1XX/2XX devices. TABLE 4-1: BUS MATRIX REGISTER MAP Bits Preliminary © 2011-2012 Microchip Technology Inc. TABLE 4-2: Virtual Address (BF88_#) Register Name INTERRUPT REGISTER MAP(1) Bits Bit Range All Resets 0000 0000 0000 0000 0000 0000 OC4IF IC1IF U2RXIF SPI1TXIF OC4IE IC1IE U2RXIE SPI1TXIE — — — — — — — — — — — — — — — — IC4IF IC1EIF U2EIF SPI1RXIF IC4IE IC1EIE U2EIE SPI1RXIE — — — — — — — — — — — — — — — — IC4EIF T1IF SPI1EIF IC4EIE T1IE SPI1EIE T4IF INT0IF INT3IF CS1IF OC3IF CS0IF IC3IF CTIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 31:16 15:0 — — — — — — — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — VEC — — — — SS0 — INT2EP INT1EP INT0EP 31:16 1010 INTSTAT(3) 15:0 1020 1030 1040 1060 IPTMR IFS0 IFS1 IEC0 IEC1 IPC0 IPC1 IPC2 IPC3 IPC4 IPC5 IPC6 IPC7 31:16 15:0 31:16 15:0 15:0 31:16 15:0 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 IPTMR FCEIF IC3EIF CNCIF FCEIE IC3EIE CNCIE — — — — — — — — — — — — — — — — RTCCIF T3IF DMA2IF CNBIF RTCCIE T3IE DMA2IE CNBIE — — — — — — — — — — — — — — — — FSCMIF INT2IF DMA1IF CNAIF FSCMIE INT2IE DMA1IE CNAIE — — — — — — — — — — — — — — — — AD1IF OC2IF DMA0IF I2C1MIF AD1IE OC2IE DMA0IE I2C1MIE OC5IF IC2IF CTMUIF I2C1SIF OC5IE IC2IE CTMUIE I2C1SIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP INT4IP IC4IP AD1IP IC5IP CMP1IP RTCCIP SPI1IP CMP3IP IC5IF IC2EIF I2C2MIF I2C1BIF IC5IE IC2EIE I2C2MIE I2C1BIE IC5EIF T2IF I2C2SIF U1TXIF IC5EIE T2IE I2C2SIE U1TXIE T5IF INT1IF I2C2BIF U1RXIF T5IE INT1IE I2C2BIE U1RXIE INT4IF OC1IF U2TXIF U1EIF INT4IE OC1IE U2TXIE U1EIE — — — — — — — — — — — — — — — — 31:16 DMA3IF SPI2TXIF SPI2RXIF SPI2EIF PMPEIF PMPIF USBIF(2) CMP3IF CMP2IF CMP1IF T4IE INT0IE INT3IE CS1IE OC3IE CS0IE IC3IE CTIE Preliminary DS61168D-page 43 1070 1090 10A0 10B0 10C0 10D0 10E0 10F0 1100 Legend: Note 1: 31:16 DMA3IE SPI2TXIE SPI2RXIE SPI2EIE PMPEIE PMPIE USBIE(2) CMP3IE CMP2IE CMP1IE CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS OC4IS T4IS OC5IS T5IS FCEIS FSCMIS USBIS(2) CMP2IS CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP OC4IP T4IP OC5IP T5IP FCEIP FSCMIP USBIP(2) CMP2IP CS1IP INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS INT4IS IC4IS AD1IS IC5IS CMP1IS RTCCIS SPI1IS CMP3IS PIC32MX1XX/2XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX1XX devices. This register does not have associated CLR, SET, INV registers. 2: 3: TABLE 4-2: Virtual Address (BF88_#) Register Name INTERRUPT REGISTER MAP(1) (CONTINUED) Bits Bit Range All Resets DS61168D-page 44 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1110 1120 1130 Legend: Note 1: IPC8 IPC9 IPC10 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — PMPIP I2C1IP CTMUIP U2IP DMA3IP DMA1IP PMPIS I2C1IS CTMUIS U2IS DMA3IS DMA1IS — — — — — — — — — — — — — — — — — — CNIP U1IP I2C2IP SPI2IP DMA2IP DMA0IP CNIS U1IS I2C2IS SPI2IS DMA2IS DMA0IS 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX1XX devices. This register does not have associated CLR, SET, INV registers. 2: 3: Preliminary © 2011-2012 Microchip Technology Inc. TABLE 4-3: Virtual Address (BF80_#) Bit Range Register Name TIMER1-TIMER5 REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 — — — — — — — — — — — — — — — TCKPS — — — TCKPS — — — TCKPS — — — TCKPS — — — — — — — — — — — — — — — — — T32 — — — — — — — T32 — — — — — — — — — — — — — — — — — — — — — — — — — TCS — — — TCS — — — TCS — — — TCS — — — — — — — — — — — — — — — — — — — 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 T1CON 0610 0620 TMR1 PR1 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — ON — — — ON — — — ON — — — ON — — — — — — — — — — — — — — — — — — — — — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — TWDIS — — — — — — — — — — — — — — — — — — — TWIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — — — — — — — — — — — TSYNC — — TCS — — — — TCKPS TMR1 PR1 0800 T2CON 0810 0820 TMR2 PR2 TMR2 PR2 Preliminary DS61168D-page 45 0A00 T3CON 0A10 TMR3 0A20 PR3 TMR3 PR3 0C00 T4CON 0C10 TMR4 0C20 PR4 TMR4 PR4 PIC32MX1XX/2XX 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0E00 T5CON 0E10 TMR5 0E20 Legend: Note 1: PR5 TMR5 PR5 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-4: Virtual Address (BF80_#) Register Name INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP Bits All Resets Bit Range DS61168D-page 46 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 IC1CON(1) 2010 IC1BUF (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — SIDL — — — — — — — FEDGE — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx IC1BUF — ON — — — SIDL — — — — — — — FEDGE — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — 2200 IC2CON 2210 0000 0000 xxxx xxxx IC2BUF IC2BUF — ON — — — SIDL — — — — — — — FEDGE — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — 31:16 2400 IC3CON(1) 15:0 2410 IC3BUF (1) 0000 0000 xxxx xxxx 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — SIDL — — — — — — — FEDGE — ON — — — SIDL — — — — — — — FEDGE IC3BUF — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — 2600 IC4CON 2610 0000 0000 xxxx xxxx Preliminary © 2011-2012 Microchip Technology Inc. IC4BUF IC4BUF — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — 31:16 2800 IC5CON(1) 15:0 2810 Legend: Note 1: IC5BUF 31:16 15:0 0000 0000 xxxx xxxx IC5BUF x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-5: Virtual Address (BF80_#) Bit Range Register Name OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1) Bits All Resets 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 OC1CON 3010 3020 OC1R OC1RS 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — OC1R OC1RS — ON — — — SIDL — — — — — — — — — — — — 3200 OC2CON 3210 3220 OC2R OC2RS OC2R OC2RS — ON — — — SIDL — — — — — — — — — — — — Preliminary DS61168D-page 47 3400 OC3CON 3410 3420 OC3R OC3RS OC3R OC3RS — ON — — — SIDL — — — — — — — — — — — — 3600 OC4CON 3610 3620 OC4R OC4R OC4RS — ON — — — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — PIC32MX1XX/2XX 31:16 OC4RS 15:0 31:16 15:0 31:16 15:0 31:16 15:0 xxxx xxxx 0000 0000 xxxx xxxx xxxx xxxx 3800 OC5CON 3810 3820 OC5R OC5RS OC5R OC5RS Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-6: Virtual Address (BF80_#) Register Name I2C1 AND I2C2 REGISTER MAP(1) Bits All Resets Bit Range DS61168D-page 48 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 I2C1CON 5010 I2C1STAT 5020 I2C1ADD 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — — — — — — ON — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — STRICT — — — — — — — — — — — — STRICT — — — — — — — — — — — — A10M — BCL — — — — — — — — — — A10M — BCL — — — — — — — — — — DISSLW — GCSTAT — — — — — — — — DISSLW — GCSTAT — — — — — — — — SMEN — ADD10 — — — — — — — — SMEN — ADD10 — — — — — — — — GCEN — IWCOL — — — — — — GCEN — IWCOL — — — — — — STREN — I2COV — — — — — — STREN — I2COV — — — — — — ACKDT — D/A — — — — — — ACKDT — D/A — — — — — — ACKEN — P — — — — — — ACKEN — P — — — — — — RCEN — S — — — — — — RCEN — S — — — — — — PEN — R/W — — — — — — PEN — R/W — — — — — — RSEN — RBF — — — — — — RSEN — RBF — — — — — — SEN — TBF — — — — — — SEN — TBF — — — — — 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 15:0 ACKSTAT TRSTAT Address Register Address Mask Register Baud Rate Generator Register Transmit Register Receive Register 5030 I2C1MSK 5040 I2C1BRG 5050 I2C1TRN I2C1RCV Preliminary © 2011-2012 Microchip Technology Inc. 5060 5100 I2C2CON 5110 I2C2STAT 5120 I2C2ADD 15:0 ACKSTAT TRSTAT Address Register Address Mask Register Baud Rate Generator Register Transmit Register Receive Register 5130 I2C2MSK 5140 I2C2BRG 5150 5160 I2C2TRN I2C2RCV Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-7: Virtual Address (BF80_#) Register Name UART1 AND UART2 REGISTER MAP Bits All Resets 0000 0000 0000 FERR — — — — OERR — — — — URXDA — — — — STSEL URXDA — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK — ABAUD ADDEN — — — — RXINV RIDLE — — — — BRGH PERR — — — 0000 0000 0000 FERR — — — OERR — — — 0110 0000 0000 0000 0000 0000 0000 PDSEL Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 U1MODE(1) 6010 U1STA (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — ON — — — — — — — — — — — — — — — — — — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — RTSMD — UTXBRK — — — — — — RTSMD — UTXBRK — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — UTXBF — — — — — — — UTXBF — — — — — — ADM_EN TRMT — TX8 — RX8 — — ADM_EN TRMT — TX8 — RX8 — — WAKE — LPBACK — ABAUD ADDEN — — — — RXINV RIDLE — — — — BRGH PERR — — — — — — STSEL UEN PDSEL ADDR URXISEL — — — — WAKE — — — UTXISEL 6020 U1TXREG 6030 U1RXREG 6040 U1BRG(1) Transmit Register Receive Register Baud Rate Generator Prescaler UEN 6200 U2MODE(1) 6210 U2STA (1) ADDR URXISEL — — — — — — Preliminary DS61168D-page 49 UTXISEL 6220 U2TXREG 6230 U2RXREG 6240 U2BRG(1) Transmit Register Receive Register Baud Rate Generator Prescaler Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. PIC32MX1XX/2XX TABLE 4-8: Virtual Address (BF80_#) Bit Range Register Name SPI2 AND SPI2 REGISTER MAP(1) Bits All Resets DS61168D-page 50 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 SPI1CON 5810 SPI1STAT 5820 SPI1BUF 5830 SPI1BRG 5840 SPI1CON2 5A00 SPI2CON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 FRMEN ON — — FRMSYNC FRMPOL — — — SIDL — — MSSEN DISSDO FRMERR FRMSYPW MODE32 SPIBUSY FRMCNT MODE16 — SMP — CKE SPITUR MCLKSEL SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — DISSDI — — — SPIFE ENHBUF 0000 0000 0000 SPIRBF 0008 0000 0000 STXISEL TXBUFELM SPITBE — SRXISEL SPITBF RXBUFELM DATA — — — SPI SGNEXT FRMEN ON — — — — — — — — — — — — — SIDL — — FRMERR — — — FRM ERREN MSSEN DISSDO — — — SPI ROVEN FRMSYPW MODE32 SPIBUSY — — — SPI TUREN MODE16 — — — — IGNROV SMP — — IGNTUR CKE SPITUR — AUDEN MCLKSEL SSEN — SRMT — — — CKP — SPIROV — — — MSTEN — SPIRBE — — — — — — BRG — — — DISSDI — AUDMONO — — — — — — AUDMOD SPIFE SRXISEL SPITBF — — — — 0000 0000 0000 0000 0000 0000 FRMSYNC FRMPOL FRMCNT ENHBUF 0000 STXISEL TXBUFELM SPITBE — Preliminary © 2011-2012 Microchip Technology Inc. 5A10 SPI2STAT 5A20 SPI2BUF 5A30 SPI2BRG 5A40 SPI2CON2 Legend: Note 1: RXBUFELM SPIRBF 0008 0000 0000 DATA — — — SPI SGNEXT — — — — — — — — — — — FRM ERREN — — — SPI ROVEN — — — SPI TUREN — — — IGNROV — IGNTUR — AUDEN — — — — — — — — — BRG — — — AUD MONO — — — — AUDMOD — — — — 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-9: Virtual Address (BF80_#) Register Name ADC REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 AD1CON1(1) 9010 AD1CON2(1) 9020 AD1CON3(1) 9040 AD1CHS(1) 9050 AD1CSSL(1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB 31:16 — — — — SIDL 15:0 ON 31:16 — — — 15:0 VCFG 31:16 — — — — — 15:0 ADRC 31:16 CH0NB — — — — — 15:0 31:16 — — — 15:0 CSSL15 CSSL14 CSSL13 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — OFFCAL — — — — CSSL12 — — FORM — — — CSCNA — — — — — SAMC CH0SB — — — — — — — — CSSL11 CSSL10 CSSL9 CSSL8 — — — — — — — — BUFS — CH0NA — — CSSL7 — SSRC — — — — — — CSSL6 — — — — — — CSSL5 — — CLRASAM — — — SMPI — — ADCS — — — — — CSSL4 CSSL3 — ASAM — — — SAMP — BUFM — — DONE — ALTS — CH0SA — — — — CSSL2 CSSL1 — — CSSL0 ADC Result Word 0 (ADC1BUF0) ADC Result Word 1 (ADC1BUF1) ADC Result Word 2 (ADC1BUF2) ADC Result Word 3 (ADC1BUF3) ADC Result Word 4 (ADC1BUF4) ADC Result Word 5 (ADC1BUF5) ADC Result Word 6 (ADC1BUF6) ADC Result Word 7 (ADC1BUF7) ADC Result Word 8 (ADC1BUF8) ADC Result Word 9 (ADC1BUF9) ADC Result Word A (ADC1BUFA) ADC Result Word B (ADC1BUFB) Preliminary DS61168D-page 51 PIC32MX1XX/2XX 31:16 0000 ADC Result Word C (ADC1BUFC) 15:0 0000 31:16 0000 9140 ADC1BUFD ADC Result Word D (ADC1BUFD) 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details. 9130 ADC1BUFC TABLE 4-9: Virtual Address (BF80_#) Register Name ADC REGISTER MAP (CONTINUED) Bits All Resets Bit Range DS61168D-page 52 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 31:16 0000 ADC Result Word E (ADC1BUFE) 15:0 0000 31:16 0000 9160 ADC1BUFF ADC Result Word F (ADC1BUFF) 15:0 0000 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for details. 9150 ADC1BUFE Preliminary © 2011-2012 Microchip Technology Inc. TABLE 4-10: Virtual Address (BF88_#) Register Name DMA GLOBAL REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets Bit Range Virtual Address (BF88_#) Bit Range Register Name © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 DMACON 3010 DMASTAT 3020 DMAADDR Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RDWR — — — — — — DMACH(2) — — — SUSPEND DMABUSY DMAADDR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-11: DMA CRC REGISTER MAP(1) Bits Preliminary DS61168D-page 53 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 — — — — BYTO — WBO — PLEN — BITO — CRCEN — — — — — — — — CRCCH — CRCAPP CRCTYP DCRCDATA DCRCXOR PIC32MX1XX/2XX x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-12: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-3 REGISTER MAP(1) Bits All Resets Bit Range DS61168D-page 54 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 DCH0CON 3070 DCH0ECON 3080 DCH0INT 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — CHEN — CHAED — CHCHN PATEN CHDDIE CHDDIF — CHAEN SIRQEN CHDHIE CHDHIF — — AIRQEN CHBCIE CHBCIF — CHEDET — CHCCIE CHCCIF — — 0000 0000 00FF FF00 15:0 CHBUSY CHPRI — CHTAIE CHTAIF — CHAIRQ CFORCE CABORT CHSDIE CHSDIF CHSHIE CHSHIF CHSIRQ — — CHERIE 0000 CHERIF 0000 0000 0000 0000 0000 3090 DCH0SSA 30A0 DCH0DSA 30B0 DCH0SSIZ CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE CABORT — — CHSDIE CHSDIF CHSHIE CHSHIF PATEN CHDDIE CHDDIF — CHEN — CHAED — CHCHN — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — Preliminary © 2011-2012 Microchip Technology Inc. 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 3120 DCH1CON 3130 DCH1ECON 3140 DCH1INT 15:0 CHBUSY CHAIRQ CHSIRQ CHERIE 0000 CHERIF 0000 0000 0000 0000 0000 3150 DCH1SSA 3160 DCH1DSA Legend: Note 1: CHSSA CHDSA x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-12: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 — — — — — — — CHAED — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF — CHTAIE CHTAIF — FF00 CHERIE 0000 CHERIF 0000 0000 0000 0000 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHPRI CHPDAT — CHEN Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3170 DCH1SSIZ 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 DCH2INT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — — — — — — — — CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR Preliminary DS61168D-page 55 15:0 CHBUSY CHAIRQ CFORCE CABORT CHSDIE CHSDIF CHSHIE CHSHIF CHSIRQ — — 3210 DCH2SSA 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ Legend: Note 1: CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PIC32MX1XX/2XX CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-12: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-3 REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61168D-page 56 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3280 DCH2CPTR 3290 DCH2DAT 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — CHEN — — — CHAED — — — CHCHN PATEN CHDDIE CHDDIF — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — AIRQEN CHBCIE CHBCIF — — — CHEDET — CHCCIE CHCCIF — — — — — — 0000 0000 0000 0000 0000 0000 00FF FF00 CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — 15:0 CHBUSY CHAIRQ CFORCE CABORT CHSDIE CHSDIF CHSHIE CHSHIF CHSIRQ — — CHERIE 0000 CHERIF 0000 0000 0000 0000 0000 32D0 DCH3SSA CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — Preliminary © 2011-2012 Microchip Technology Inc. 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT Legend: Note 1: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-13: Virtual Address (BF80_#) Bit Range Register Name COMPARATOR REGISTER MAP(1) Bits All Resets 0000 00C3 0000 00C3 0000 00C3 0000 0000 0000 0000 All Resets Virtual Address (BF80_#) Bit Range Register Name © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 A000 CM1CON A010 CM2CON A020 CM3CON A060 CMSTAT Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ON — ON — — — COE — COE — COE — — — CPOL — CPOL — CPOL — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — COUT — COUT — COUT — — — — — — — — — — — — — — — — — — — — — CREF — CREF — CREF — — — — — — — — — — — — — — — — — C3OUT — — — — C2OUT — — — — C1OUT EVPOL EVPOL EVPOL CCH CCH CCH x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. Preliminary DS61168D-page 57 TABLE 4-14: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 CVRCON Legend: Note 1: 31:16 15:0 — ON — — — — — — — — — — — — — — — — — CVROE — CVRR — CVRSS — — — — CVR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. PIC32MX1XX/2XX TABLE 4-15: Virtual Address (BF80_#) Register Name FLASH CONTROLLER REGISTER MAP Bits All Resets Bit Range DS61168D-page 58 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F400 NVMCON(1) F410 NVMKEY 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — WR — WREN — WRERR — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 LVDERR LVDSTAT NVMOP NVMKEY NVMADDR NVMDATA NVMSRCADDR F420 NVMADDR(1) F430 F440 NVMDATA NVMSRC ADDR Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. Preliminary © 2011-2012 Microchip Technology Inc. TABLE 4-16: Virtual Address (BF80_#) Register Name SYSTEM CONTROL REGISTER MAP(1) Bits All Resets x1xx(2) OSWEN xxxx(2) — 0000 0000 0000 — — — — — — — — — — — — — — — CMR — — — — — — — — VREGS — — — — — — — — EXTR — — — — — SWR — — — — — — — — — — — — — — — — — — — — SWDTPS — WDTO — — — — — SLEEP — — — JTAGEN — IDLE — — — — — — — ROSEL — — — — — — — BOR — — — — — — — — POR — SWRST — TDOEN 0000 0000 0000 0000 0000 0000 xxxx(2) 0000 0000 0000 000B 0000 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — OC5MD IC5MD — T5MD — — — — — — — — OC4MD IC4MD — T4MD — — — — — — — CMP3MD OC3MD IC3MD — T3MD — — — — — — — OC2MD IC2MD — T2MD I2C1MD U2MD — — AD1MD — OC1MD IC1MD — T1MD I2C1MD U1MD PMPMD 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F000 OSCCON F010 OSCTUN F020 REFOCON F030 REFOTRIM 0000 WDTCON F600 RCON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — ON — — ON — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — PLLODIV COSC — — OE — — — — — — — — — — — RSLP ROTRIM — — — — — — — — — — — — FRCDIV NOSC — — — — — — — SOSCRDY PBDIVRDY SLOCK — — — PBDIV SLPEN — CF — — TUN PLLMULT UFRCEN(4) SOSCEN — CLKLOCK ULOCK(4) RODIV DIVSWEN ACTIVE — WDTWINEN WDTCLR Preliminary DS61168D-page 59 F610 RSWRST F200 CFGCON F230 F240 F250 F260 F270 F280 F290 Legend: Note 1: 2: 3: 4: SYSKEY(3) PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 IOLOCK PMDLOCK SYSKEY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CVRMD — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2MD — — — CTMUMD — — — — — — USB1MD SPI1MD — — — — — — — — — — — — — — CMP2MD CMP1MD PIC32MX1XX/2XX REFOMD RTCCMD x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of reset. This register does not have associated CLR, SET, INV registers. This bit is available on PIC32MX2XX devices only. TABLE 4-17: Virtual Address (BFC0_#) Bit Range Register Name DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Bits All Resets Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F220 DEVID 31:16 15:0 VER DEVID DEVID xxxx xxxx Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. All Resets Bit Range Register Name DS61168D-page 60 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend: Note 1: 31:16 FVBUSONID FUSBIDIO IOL1WAY PMDL1WAY 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — UPLLEN(1) — — — — — — — — — — — — — CP — — — — — — — — — OSCIOFNC — — — UPLLIDIV(1) — — — — — IESO — — — — — — FPLLMUL — FSOSCEN — — — — — — — — — FPLLODIV FPLLIDIV — xxxx xxxx xxxx xxxx xxxx xxxx USERID FWDTWINSZ FWDTEN WINDIS POSCMOD — — BWP — — — — WDTPS — — — — — JTAGEN FNOSC — — DEBUG FCKSM FPBDIV PWP xxxx xxxx ICESEL x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This bit is available on PIC32MX2XX devices only. TABLE 4-18: DEVICE AND REVISION ID SUMMARY(1) Bits Preliminary © 2011-2012 Microchip Technology Inc. TABLE 4-19: Virtual Address (BF88_#) Bit Range Register Name PORTA REGISTER MAP(1) Bits All Resets 0000 0003 0000 079F 0000 RA4 — LATA4 — — — CNPUA4 — CNPDA4 — — — CNIEA4 — RA3 — LATA3 — — — CNPUA3 — CNPDA3 — — — CNIEA3 — RA2 — LATA2 — — — CNPUA2 — CNPDA2 — — — CNIEA2 — RA1 — LATA1 — — — CNPUA1 — CNPDA1 — — — CNIEA1 — RA0 — LATA0 — — — — — — — CNIEA0 — xxxx 0000 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 ANSELA 6010 6020 6030 6040 6050 TRISA PORTA LATA ODCA CNPUA CNPDA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — ON — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISA10(2) — RA10(2) — LATA10(2) — ODCA10(2) — CNPUA10(2) — CNPDA10(2) — — — CNIEA10(2) — — — — TRISA9(2) — RA9(2) — LATA9(2) — ODCA9(2) — CNPUA9(2) — CNPDA9(2) — — — CNIEA9(2) — — — — TRISA8(2) — RA8(2) — LATA8(2) — ODCA8(2) — CNPUA8(2) — CNPDA8(2) — — — CNIEA8(2) — — — — TRISA7(2) — RA7(2) — LATA7(2) — ODCA7(2) — CNPUA7(2) — CNPDA7(2) — — — CNIEA7(2) — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISA4 — — — TRISA3 — — — TRISA2 — ANSA1 — TRISA1 — ANSA0 — TRISA0 CNPUA0 0000 CNPDA0 0000 Preliminary DS61168D-page 61 6060 6070 CNCONA 6080 CNENA 6090 CNSTATA Legend: Note 1: 2: CNSTATA10(2) CNSTATA9(2) CNSTATA8(2) CNSTATA7(2) CNSTATA4 CNSTATA3 CNSTATA2 CNSTATA1 CNSTATA0 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. This bit is available on 44-pin devices only. PIC32MX1XX/2XX TABLE 4-20: Virtual Address (BF88_#) Bit Range Register Name PORTB REGISTER MAP Bits All Resets DS61168D-page 62 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 ANSELB 6110 6120 6130 6140 6150 TRISB PORTB LATB ODCB CNPUB CNPDB 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 31:16 31:16 15:0 31:16 31:16 — ANSB15 — — RB15 — LATB15 — — — — — ON — — CN STATB15 — ANSB14 — TRISB14 — RB14 — LATB14 — — — — — — — CNIEB14 — CN STATB14 — ANSB13 — TRISB13 — RB13 — LATB13 — — — — — SIDL — CNIEB13 — CN STATB13 — ANSB12(2) — TRISB12(2) — RB12(2) — LATB12(2) — — — — — — — CNIEB11(2) — CN STATB12(2) — — — TRISB11 — RB11 — LATB11 — ODCB11 — — — — — CNIEB11 — CN STATB11 — — — TRISB10 — RB10 — LATB10 — ODCB10 — — — — — CNIEB10 — CN STATB10 — — — TRISB9 — RB9 — LATB9 — ODCB9 — — — — — CNIEB9 — CN STATB9 — — — TRISB8 — RB8 — LATB8 — ODCB8 — — — — — CNIEB8 — CN STATB8 — — — TRISB7 — RB7 — LATB7 — ODCB7 — — — — — CNIEB7 — CN STATB7 — — — TRISB6(2) — RC6(2) — LATB6(2) — ODCB6 — — — — — CNIEB6(2) — CN STATB6(2) — — — TRISB5 — RB5 — LATB5 — ODCB5 — — — — — CNIEB5 — CN STATB5 — — — TRISB4 RB4 — LATB4 — ODCB4 — — — — — CNIEB4 — CN STATB4 — ANSB3 — TRISB3 RB3 — LATB3 — — — — — — — CNIEB3 — CN STATB3 — ANSB2 — TRISB2 RB2 — LATB2 — — — — — — — CNIEB2 — CN STATB2 — ANSB1 — TRISB1 RB1 — LATB1 — — — — — — — CNIEB1 — CN STATB1 — ANSB0 — TRISB0 RB0 — LATB0 — — — — — — — CNIEB0 — CN STATB0 0000 E00F 0000 FFFF 0000 xxxx 0000 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 15:0 TRISB15 15:0 CNPUB15 CNPUB14 CNPUB13 CNPUB12(2) CNPUB11 CNPUB10 CNPUB9 CNPUB8 CNPUB7 CNPUB6(2) CNPUB5 CNPUB4 CNPUB3 CNPUB2 CNPUB1 CNPUB0 0000 15:0 CNPDB15 CNPDB14 CNPDB13 CNPDB12(2) CNPDB11 CNPDB10 CNPDB9 CNPDB8 CNPDB7 CNPDB6(2) CNPDB5 CNPDB4 CNPDB3 CNPDB2 CNPDB1 CNPDB0 0000 Preliminary © 2011-2012 Microchip Technology Inc. 6160 6170 CNCONB 6180 CNENB 15:0 CNIEB15 15:0 6190 CNSTATB Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. This bit is not available on PIC32MX2XX devices. The reset value for the TRISB register when this bit is not available is 0x0000EFBF. TABLE 4-21: Virtual Address (BF88_#) Bit Range Register Name PORTC REGISTER MAP(1,2) Bits All Resets 0000 000F 0000 03FF 0000 RC4(3) — LATC4(3) — ODCC4(3) — CNPUC4(3) — CNPDC4(3) — — — CNIEC4(3) — RC3 — LATC3 — — — CNPUC3 — CNPDC3 — — — CNIEC3 — RC2(3) — LATC2(3) — — — CNPUC2(3) — CNPDC2(3) — — — CNIEC2(3) — RC1 — LATC1 — — — CNPUC1 — CNPDC1 — — — CNIEC1 — RC0 — LATC0 — — — CNPUC0 — CNPDC0 — — — CNIEC0 — xxxx 0000 xxxx 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6200 ANSELC 6210 6220 6230 6240 6250 TRISC PORTC LATC ODCC CNPUC CNPDC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — ON — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISC9 — RC9 — LATC9 — ODCC9 — CNPUC9 — CNPDC9 — — — CNIEC9 — — — — TRISC8(3) — RC8(3) — LATC8(3) — ODCC8(3) — CNPUC8(3) — CNPDC8(3) — — — CNIEC8(3) — — — — TRISC7(3) — RC7(3) — LATC7(3) — ODCC7(3) — CNPUC7(3) — CNPDC7(3) — — — CNIEC7(3) — — — — TRISC6(3) — RC6(3) — LATC6(3) — ODCC6(3) — CNPUC6(3) — CNPDC6(3) — — — CNIEC6(3) — — — — TRISC5(3) — RC5(3) — LATC5(3) — ODCC5(3) — CNPUC5(3) — CNPDC5(3) — — — CNIEC5(3) — — — — TRISC4(3) — ANSC3 — TRISC3 — ANSC2(3) — TRISC2(3) — ANSC1 — TRISC1 — ANSC0 — TRISC0 Preliminary DS61168D-page 63 6260 6270 CNCONC 6280 CNENC 6290 CNSTATC Legend: Note 1: 2: 3: CNSTATC9 CNSTATC8(3) CNSTATC7(3) CNSTATC6(3) CNSTATC5(3) CNSTATC4(3) CNSTATC3 CNSTATC2(3) CNSTATC1 CNSTATC0 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. PORTC is not available on 28-pin devices. This bit is available on 44-pin devices only. PIC32MX1XX/2XX TABLE 4-22: Virtual Address (BF80_#) Register Name PERIPHERAL PIN SELECT INPUT REGISTER MAP Bits All Resets Bit Range DS61168D-page 64 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 FA04 FA08 FA0C FA10 FA18 INT1R INT2R INT3R INT4R T2CKR T3CKR T4CKR T5CKR IC1R IC2R IC3R IC4R IC5R OCFAR OCFBR U1RXR 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 INT1R INT2R INT3R INT4R T2CKR T3CKR T4CKR T5CKR IC1R IC2R IC3R IC4R IC5R OCFAR OCFBR U1RXR Preliminary © 2011-2012 Microchip Technology Inc. FA1C FA20 FA24 FA28 FA2C FA30 FA34 FA38 FA48 FA4C FA50 TABLE 4-22: Virtual Address (BF80_#) Register Name PERIPHERAL PIN SELECT INPUT REGISTER MAP (CONTINUED) Bits All Resets 0000 0000 — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 FA54 FA58 FA5C FA84 FA88 U1CTSR U2RXR U2CTSR SDI1R SS1R SDI2R SS2R 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — U1CTSR U2RXR U2CTSR SDI1R SS1R SDI2R SS2R REFCLKIR Preliminary DS61168D-page 65 FA90 FA94 FAB8 REFCLKIR PIC32MX1XX/2XX TABLE 4-23: Virtual Address (BF80_#) Register Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP Bits All Resets Bit Range DS61168D-page 66 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 FB00 FB04 FB08 FB0C FB10 FB20 FB24 FB2C FB30 FB34 FB38 RPA0R RPA1R RPA2R RPA3R RPA4R RPA8R(1) RPA9R(1) RPB0R RPB1R RPB2R RPB3R RPB4R RPB5R RPB6R(2) RPB7R RPB8R 1: 2: 3: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 RPA0 RPA1 RPA2 RPA3 RPA4 RPA8 RPA9 RPB0 RPB1 RPB2 RPB3 RPB4 RPB5 RPB6 RPB7 RPB8 Preliminary © 2011-2012 Microchip Technology Inc. FB3C FB40 FB44 FB48 FB4C Note This register is only available on 44-pin devices. This register is only available on PIC32MX1XX devices. This register is only available on 36-pin and 44-pin devices. TABLE 4-23: Virtual Address (BF80_#) Register Name PERIPHERAL PIN SELECT OUTPUT REGISTER MAP (CONTINUED) Bits All Resets 0000 0000 — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 FB50 FB54 FB58 FB60 FB64 FB68 RPB9R RPB10R RPB11R RPB13R RPB14R RPB15R RPC0R(3) RPC1R(3) RPC2R(1) RPC3R (3) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RPB9 RPB10 RPB11 RPB13 RPB14 RPB15 RPC0 RPC1 RPC2 RPC3 RPC4 RPC5 RPC6 RPC7 RPC8 RPC9 Preliminary DS61168D-page 67 FB6C FB70 FB74 FB78 FB7C FB80 FB84 FB88 FB8C FB90 Note PIC32MX1XX/2XX RPC4R(1) RPC5R(1) RPC6R (1) RPC7R(1) RPC8R(1) RPC9R(3) 1: 2: 3: This register is only available on 44-pin devices. This register is only available on PIC32MX1XX devices. This register is only available on 36-pin and 44-pin devices. TABLE 4-24: Virtual Address (BF80_#) Bit Range Register Name PARALLEL MASTER PORT REGISTER MAP(1) Bits All Resets DS61168D-page 68 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 PMCON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — BUSY — — — — — — CS1 — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — — — — ALP — — ADDR — — — — — CS1P — — — — — — — WRSP — — — RDSP — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADRMUX INCM PMPTTL PTWREN PTRDEN MODE CSF WAITB 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7050 PMDIN PMAEN PMSTAT IRQM WAITM WAITE DATAOUT DATAIN — — — IBF — PTEN14 — IBOV — — — — — — — — — — — IB3F — IB2F — IB1F — IB0F — OBE — OBUF — — — — — — PTEN — — — — — OB3E — OB2E — OB1E — OB0E — — — — — 0000 0000 0000 008F Preliminary © 2011-2012 Microchip Technology Inc. 7060 Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-25: Virtual Address (BF80_#) Register Name RTCC REGISTER MAP(1) Bits All Resets 0000 RTCWREN RTCSYNC HALFSEC RTCOE — — — — 0000 0000 0000 MIN01 — — — — — — — — — — — — — MONTH01 WDAY01 MIN01 — — — MONTH01 WDAY01 xxxx xx00 xxxx xx00 xxxx xx00 00xx xx0x All Resets Bit Range Virtual Address (BF80_#) Bit Range Register Name © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 RTCCON 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — CHIME — SIDL — PIV — — — ALRMSYNC — — — — — — — — — — RTSECSEL RTCCLKON — — MIN10 — — — — — — — MIN10 — — CAL — — — — 0210 RTCALRM 0220 RTCTIME 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: 15:0 ALRMEN AMASK HR01 SEC01 YEAR01 DAY01 HR01 SEC01 ARPT HR10 SEC10 YEAR10 DAY10 HR10 SEC10 — — — — — DAY10 MONTH10 — — MONTH10 DAY01 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. Preliminary DS61168D-page 69 TABLE 4-26: CTMU REGISTER MAP(1) Bits 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 PIC32MX1XX/2XX A200 CTMUCON Legend: Note 1: 31:16 EDG1MOD EDG1POL 15:0 ON — CTMUSIDL EDG1SEL TGEN EDG2STAT EDG1STAT EDG2MOD EDG2POL CTTRIG EDG2SEL ITRIM — — 0000 0000 EDGEN EDGSEQEN IDISSEN IRNG x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. TABLE 4-27: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) Bits All Resets Bit Range DS61168D-page 70 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 5050 U1OTGIR(2) U1OTGIE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — IDIF — IDIE — ID — — UACTPND(4) — STALLIF — STALLIE — BTSEF — BTSEE — — JSTATE — LSPDEN — — — — — — — — — — — — LSTATE — — — — — ACTVIF — ACTVIE — — — — — IDLEIF — IDLEIE — BTOEF — BTOEE — — USBRST — — BDTPTRL — — — SESVD — — — TRNIF — TRNIE — — — — SESEND — OTGEN — — — SOFIF — SOFIE — — — — — — — — VBUSCHG — — UERRIF — UERRIE — CRC5EF EOFEF — CRC5EE EOFEE — — — PPBRST — — — — — VBUSVD — VBUSDIS — — URSTIF — URSTIE — PIDEF — PIDEE — — — USBEN SOFEN — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 T1MSECIF LSTATEIF T1MSECIE LSTATEIE SESVDIF SESENDIF SESVDIE SESENDIE VBUSVDIF 0000 VBUSVDIE 0000 5060 U1OTGSTAT(3) 5070 5080 U1OTGCON U1PWRC U1IR(2) DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON USLPGRD USBBUSY USUSPEND USBPWR 5200 15:0 31:16 ATTACHIF RESUMEIF — — DETACHIF 0000 Preliminary © 2011-2012 Microchip Technology Inc. 5210 U1IE 15:0 31:16 ATTACHIE RESUMEIE — BMXEF — BMXEE — — SE0 — — — DMAEF — DMAEE — — PKTDIS TOKBUSY — — DETACHIE 0000 5220 U1EIR(2) 15:0 31:16 DFN8EF CRC16EF — — 5230 U1EIE (3) 15:0 31:16 15:0 31:16 DFN8EE CRC16EE — DIR — — PPBI — 5240 U1STAT ENDPT 5250 U1CON 15:0 31:16 15:0 31:16 15:0 HOSTEN RESUME — — — 5260 5270 U1ADDR U1BDTP1 DEVADDR — Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. TABLE 4-27: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 — — — — — — — — — — — — — — — — — — — — — — — — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — — FRMH — EP — CNT — — — UTEYE — LSPD — — — — — — — — — — — — — — — — — — — UOEMON — RETRYDIS — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — USBSIDL — — — — — — — — — — — — — — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — — — — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK BDTPTRH BDTPTRU — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 UASUSPND 0001 Bit Range © 2011-2012 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5280 5290 52A0 52B0 52C0 52D0 52E0 5300 5310 5320 5330 5340 5350 5360 5370 5380 U1FRML(3) U1FRMH(3) U1TOK U1SOF U1BDTP2 U1BDTP3 U1CNFG1 U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PID — — FRML — — — — — — — Preliminary DS61168D-page 71 EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN PIC32MX1XX/2XX Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. TABLE 4-27: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61168D-page 72 PIC32MX1XX/2XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5390 53A0 53B0 53C0 53D0 53E0 53F0 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN EPCONDIS EPRXEN Preliminary © 2011-2012 Microchip Technology Inc. Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. With the exception of those noted, all registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 11.2 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX1XX/2XX 4.2 Control Registers Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code. REGISTER 4-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 BMXCON: BUS MATRIX CONFIGURATION REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — R/W-1 — R/W-1 — R/W-1 — R/W-1 — R/W-1 — U-0 — U-0 — U-0 BMX ERRIXI U-0 BMX ERRICD U-0 BMX ERRDMA U-0 BMX ERRDS U-0 BMX ERRIS U-0 — U-0 — R/W-1 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-1 — BMX WSDRM — — — BMXARB Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared bit 31-21 Unimplemented: Read as ‘0’ bit 20 BMXERRIXI: Enable Bus Error from IXI bit 1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus 0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus BMXERRICD: Enable Bus Error from ICD Debug Unit bit 1 = Enable bus error exceptions for unmapped address accesses initiated from ICD 0 = Disable bus error exceptions for unmapped address accesses initiated from ICD BMXERRDMA: Bus Error from DMA bit 1 = Enable bus error exceptions for unmapped address accesses initiated from DMA 0 = Disable bus error exceptions for unmapped address accesses initiated from DMA BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode) 1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access 0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access Unimplemented: Read as ‘0’ BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit 1 = Data RAM accesses from CPU have one wait state for address setup 0 = Data RAM accesses from CPU have zero wait states for address setup Unimplemented: Read as ‘0’ BMXARB: Bus Matrix Arbitration Mode bits 111 = Reserved (using these Configuration modes will produce undefined behavior) • • • bit 19 bit 18 bit 17 bit 16 bit 15-7 bit 6 bit 5-3 bit 2-0 011 = Reserved (using these Configuration modes will produce undefined behavior) 010 = Arbitration Mode 2 001 = Arbitration Mode 1 (default) 000 = Arbitration Mode 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 73 PIC32MX1XX/2XX REGISTER 4-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R-0 — R-0 BMXDKPBA R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDKPBA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-11 BMXDKPBA: DRM Kernel Program Base Address bits When non-zero, this value selects the relative base address for kernel program space in RAM bit 10-0 BMXDKPBA: Read-Only bits Value is always ‘0’, which forces 1 KB increments At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. Note 1: 2: DS61168D-page 74 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 4-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R-0 — R-0 BMXDUDBA R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUDBA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-11 BMXDUDBA: DRM User Data Base Address bits When non-zero, the value selects the relative base address for User mode data space in RAM, the value must be greater than BMXDKPBA. bit 10-0 BMXDUDBA: Read-Only bits Value is always ‘0’, which forces 1 KB increments At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. Note 1: 2: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 75 PIC32MX1XX/2XX REGISTER 4-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R-0 — R-0 BMXDUPBA R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXDUPBA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-11 BMXDUPBA: DRM User Program Base Address bits When non-zero, the value selects the relative base address for User mode program space in RAM, BMXDUPBA must be greater than BMXDUDBA. bit 10-0 BMXDUPBA: Read-Only bits Value is always ‘0’, which forces 1 KB increments At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXDRMSZ. Note 1: 2: DS61168D-page 76 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 4-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R BMXDRMSZ: DATA RAM SIZE REGISTER Bit 30/22/14/6 R Bit 29/21/13/5 R Bit Bit 28/20/12/4 27/19/11/3 R R Bit 26/18/10/2 R Bit 25/17/9/1 R Bit 24/16/8/0 R BMXDRMSZ R R R R R R R R BMXDRMSZ R R R R R R R R BMXDRMSZ R R R R R R R R BMXDRMSZ Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown BMXDRMSZ: Data RAM Memory (DRM) Size bits Static value that indicates the size of the Data RAM in bytes: 0x00001000 = device has 4 KB RAM 0x00002000 = device has 8 KB RAM 0x00004000 = device has 16 KB RAM 0x00008000 = device has 32 KB RAM REGISTER 4-6: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS REGISTER(1,2) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 R/W-0 BMXPUPBA R-0 R-0 R-0 BMXPUPBA R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 BMXPUPBA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-20 Unimplemented: Read as ‘0’ bit 19-11 BMXPUPBA: Program Flash (PFM) User Program Base Address bits bit 10-0 BMXPUPBA: Read-Only bits Value is always ‘0’, which forces 2 KB increments At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal mode data usage. The value in this register must be less than or equal to BMXPFMSZ. Note 1: 2: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 77 PIC32MX1XX/2XX REGISTER 4-7: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER Bit 30/22/14/6 R Bit 29/21/13/5 R Bit Bit 28/20/12/4 27/19/11/3 R R Bit 26/18/10/2 R Bit 25/17/9/1 R Bit 24/16/8/0 R BMXPFMSZ R R R R R R R R BMXPFMSZ R R R R R R R R BMXPFMSZ R R R R R R R R BMXPFMSZ Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown BMXPFMSZ: Program Flash Memory (PFM) Size bits Static value that indicates the size of the PFM in bytes: 0x00004000 = device has 16 KB Flash 0x00008000 = device has 32 KB Flash 0x00010000 = device has 64 KB Flash 0x00020000 = device has 128 KB Flash REGISTER 4-8: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER Bit 30/22/14/6 R Bit 29/21/13/5 R Bit Bit 28/20/12/4 27/19/11/3 R R Bit 26/18/10/2 R Bit 25/17/9/1 R Bit 24/16/8/0 R BMXBOOTSZ R R R R R R R R BMXBOOTSZ R R R R R R R R BMXBOOTSZ R R R R R R R R BMXBOOTSZ Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown BMXBOOTSZ: Boot Flash Memory (BFM) Size bits Static value that indicates the size of the Boot PFM in bytes: 0x00000C00 = device has 3 KB boot Flash DS61168D-page 78 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 5.0 FLASH PROGRAM MEMORY Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 5. “Flash Program Memory” (DS61121) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX devices contain an internal Flash program memory for executing user code. There are three methods by which the user can program this memory: 1. 2. 3. Run-Time Self-Programming (RTSP) EJTAG Programming In-Circuit Serial Programming™ (ICSP™) RTSP is performed by software executing from either Flash or RAM memory. Information about RTSP techniques is available in Section 5. “Flash Program Memory” (DS61121) in the “PIC32 Family Reference Manual”. EJTAG is performed using the EJTAG port of the device and an EJTAG capable programmer. ICSP is performed using a serial data connection to the device and allows much faster programming times than RTSP. The EJTAG and ICSP methods are described in the “PIC32 Flash Programming Specification” (DS61145), which can be downloaded from the Microchip web site. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 79 PIC32MX1XX/2XX REGISTER 5-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 NVMCON: PROGRAMMING CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R-0 U-0 — R-0 U-0 — R-0 R/W-0 — U-0 — U-0 — U-0 WR U-0 WREN U-0 WRERR(1) LVDERR(1) LVDSTAT(1) — — — R/W-0 — R/W-0 — R/W-0 — — NVMOP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 WR: Write Control bit This bit is writable when WREN = 1 and the unlock sequence is followed. 1 = Initiate a Flash operation. Hardware clears this bit when the operation completes 0 = Flash operation complete or inactive bit 14 WREN: Write Enable bit 1 = Enable writes to WR bit and enables LVD circuit 0 = Disable writes to WR bit and disables LVD circuit This is the only bit in this register reset by a device Reset. bit 13 WRERR: Write Error bit(1) This bit is read-only and is automatically set by hardware. 1 = Program or erase sequence did not complete successfully 0 = Program or erase sequence completed normally bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set by hardware. 1 = Low-voltage detected (possible data corruption, if WRERR is set) 0 = Voltage level is acceptable for programming bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1) This bit is read-only and is automatically set, and cleared, by hardware. 1 = Low-voltage event active 0 = Low-voltage event NOT active bit 10-4 Unimplemented: Read as ‘0’ bit 3-0 NVMOP: NVM Operation bits These bits are writable when WREN = 0. 1111 = Reserved • • • 0111 = Reserved 0110 = No operation 0101 = Program Flash (PFM) erase operation: erases PFM, if all pages are not write-protected 0100 = Page erase operation: erases page selected by NVMADDR, if it is not write-protected 0011 = Row program operation: programs row selected by NVMADDR, if it is not write-protected 0010 = No operation 0001 = Word program operation: programs word selected by NVMADDR, if it is not write-protected 0000 = No operation Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR). DS61168D-page 80 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 5-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 W-0 NVMKEY: PROGRAMMING UNLOCK REGISTER(1) Bit 30/22/14/6 W-0 Bit 29/21/13/5 W-0 Bit Bit 28/20/12/4 27/19/11/3 W-0 W-0 Bit 26/18/10/2 W-0 Bit 25/17/9/1 W-0 Bit 24/16/8/0 W-0 NVMKEY W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0 NVMKEY Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown NVMKEY: Unlock Register bits These bits are write-only, and read as ‘0’ on any read This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM. Note 1: REGISTER 5-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 NVMADDR: FLASH ADDRESS REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 NVMADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMADDR Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown NVMADDR: Flash Address bits Bulk/Chip/PFM Erase: Address is ignored. Page Erase: Address identifies the page to erase. Row Program: Address identifies the row to program. Word Program: Address identifies the word to program. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 81 PIC32MX1XX/2XX REGISTER 5-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 NVMDATA: FLASH PROGRAM DATA REGISTER(1) Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 NVMDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMDATA Legend: R = Readable bit -n = Value at POR bit 31-0 Note 1: W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown NVMDATA: Flash Programming Data bits The bits in this register are only reset by a Power-on Reset (POR). REGISTER 5-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 NVMSRCADDR: SOURCE DATA ADDRESS REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 NVMSRCADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 NVMSRCADDR Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown NVMSRCADDR: Source Data Address bits The system physical address of the data to be programmed into the Flash when the NVMOP bits (NVMCON) are set to perform row programming. DS61168D-page 82 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 6.0 RESETS Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 7. “Resets” (DS61118) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Reset module combines all Reset sources and controls the device Master Reset signal, SYSRST. The following is a list of device Reset sources: • • • • • • POR: Power-on Reset MCLR: Master Clear Reset pin SWR: Software Reset WDTR: Watchdog Timer Reset BOR: Brown-out Reset CMR: Configuration Mismatch Reset A simplified block diagram of the Reset module is illustrated in Figure 6-1. FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM MCLR Glitch Filter Sleep or Idle Voltage Regulator Enabled VDD WDT Time-out Power-up Timer VDD Rise Detect Brown-out Reset BOR CMR SWR POR SYSRST MCLR WDTR Configuration Mismatch Reset Software Reset © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 83 PIC32MX1XX/2XX REGISTER 6-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 RCON: RESET CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0, HS — R/W-0 — R/W-0, HS — R/W-0, HS — U-0 — R/W-0, HS — R/W-0, HS — R/W-0, HS CMR R/W-1, HS (1) VREGS R/W-1, HS (1) EXTR SWR — WDTO SLEEP IDLE BOR POR Legend: R = Readable bit -n = Value at POR HS = Set by hardware W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-10 Unimplemented: Read as ‘0’ bit 9 CMR: Configuration Mismatch Reset Flag bit 1 = Configuration mismatch Reset has occurred 0 = Configuration mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit 1 = Regulator is enabled and is on during Sleep mode 0 = Regulator is disabled and is off during Sleep mode EXTR: External Reset (MCLR) Pin Flag bit 1 = Master Clear (pin) Reset has occurred 0 = Master Clear (pin) Reset has not occurred SWR: Software Reset Flag bit 1 = Software Reset was executed 0 = Software Reset as not executed Unimplemented: Read as ‘0’ WDTO: Watchdog Timer Time-out Flag bit 1 = WDT Time-out has occurred 0 = WDT Time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device was in Sleep mode 0 = Device was not in Sleep mode IDLE: Wake From Idle Flag bit 1 = Device was in Idle mode 0 = Device was not in Idle mode BOR: Brown-out Reset Flag bit(1) 1 = Brown-out Reset has occurred 0 = Brown-out Reset has not occurred POR: Power-on Reset Flag bit(1) 1 = Power-on Reset has occurred 0 = Power-on Reset has not occurred User software must clear this bit to view next detection. bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS61168D-page 84 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 6-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 RSWRST: SOFTWARE RESET REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — W-0, HC — — — — — — — SWRST(1) Legend: R = Readable bit -n = Value at POR bit 31-1 bit 0 HC = Cleared by hardware W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ SWRST: Software Reset Trigger bit(1) 1 = Enable software Reset event 0 = No effect The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 85 PIC32MX1XX/2XX NOTES: DS61168D-page 86 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 7.0 INTERRUPT CONTROLLER The PIC32MX1XX/2XX interrupt module includes the following features: • • • • • • • • • • • Up to 64 interrupt sources Up to 44 interrupt vectors Single and multi-vector mode operations Five external interrupts with edge polarity control Interrupt proximity timer Seven user-selectable priority levels for each vector Four user-selectable subpriority levels within each priority Dedicated shadow set for all priority levels(1) Software can generate any interrupt User-configurable interrupt vector table location User-configurable interrupt vector spacing Note: On PIC32MX1XX/2XX devices, the dedicated shadow set is not present. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 8. “Interrupt Controller” (DS61108) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. PIC32MX1XX/2XX devices generate interrupt requests in response to interrupt events from peripheral modules. The interrupt control module exists externally to the CPU logic and prioritizes the interrupt events before presenting them to the CPU. FIGURE 7-1: INTERRUPT CONTROLLER MODULE BLOCK DIAGRAM Interrupt Requests Vector Number Interrupt Controller Priority Level CPU Core © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 87 PIC32MX1XX/2XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION IRQ Vector # # Interrupt Bit Location Flag IFS0 IFS0 IFS0 IFS0 IFS0 IFS0 IFS0 IFS0 IFS0 IFS0 Enable IEC0 IEC0 IEC0 IEC0 IEC0 IEC0 IEC0 IEC0 IEC0 IEC0 Priority IPC0 IPC0 IPC0 IPC0 IPC1 IPC1 IPC1 IPC1 IPC1 IPC2 Sub-priority IPC0 IPC0 IPC0 IPC0 IPC1 IPC1 IPC1 IPC1 IPC1 IPC2 IPC2 IPC2 IPC2 IPC2 IPC3 IPC3 IPC3 IPC3 IPC3 IPC4 IPC4 IPC4 IPC4 IPC4 IPC5 IPC5 IPC5 IPC5 IPC5 IPC6 IPC6 IPC6 IPC6 IPC7 IPC7 IPC7 IPC7 IPC7 IPC7 Persistent Interrupt Interrupt Source(1) Highest Natural Order Priority CT – Core Timer Interrupt CS0 – Core Software Interrupt 0 CS1 – Core Software Interrupt 1 INT0 – External Interrupt T1 – Timer1 IC1E – Input Capture 1 Error IC1 – Input Capture 1 OC1 – Output Compare 1 INT1 – External Interrupt 1 T2 – Timer2 IC2E – Input Capture 2 IC2 – Input Capture 2 OC2 – Output Compare 2 INT2 – External Interrupt 2 T3 – Timer3 IC3E – Input Capture 3 IC3 – Input Capture 3 OC3 – Output Compare 3 INT3 – External Interrupt 3 T4 – Timer4 IC4E – Input Capture 4 Error IC4 – Input Capture 4 OC4 – Output Compare 4 INT4 – External Interrupt 4 T5 – Timer5 IC5E – Input Capture 5 Error IC5 – Input Capture 5 OC5 – Output Compare 5 AD1 – ADC1 Convert done FSCM – Fail-Safe Clock Monitor RTCC – Real-Time Clock and Calendar FCE – Flash Control Event CMP1 – Comparator Interrupt CMP2 – Comparator Interrupt CMP3 – Comparator Interrupt USB – USB Interrupts SPI1E – SPI1 Fault SPI1RX – SPI1 Receive Done SPI1TX – SPI1 Transfer Done Note 1: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 0 1 2 3 4 5 5 6 7 8 9 9 10 11 12 13 13 14 15 16 17 17 18 19 20 21 21 22 23 24 25 26 27 28 29 30 31 31 31 No No No No No Yes Yes No No No Yes Yes No No No Yes Yes No No No Yes Yes No No No Yes Yes No Yes No No No No No No Yes Yes Yes Yes IFS0 IEC0 IPC2 IFS0 IEC0 IPC2 IFS0 IEC0 IPC2 IFS0 IEC0 IPC2 IFS0 IEC0 IPC3 IFS0 IEC0 IPC3 IFS0 IEC0 IPC3 IFS0 IEC0 IPC3 IFS0 IEC0 IPC3 IFS0 IEC0 IPC4 IFS0 IEC0 IPC4 IFS0 IEC0 IPC4 IFS0 IEC0 IPC4 IFS0 IEC0 IPC4 IFS0 IEC0 IPC5 IFS0 IEC0 IPC5 IFS0 IEC0 IPC5 IFS0 IEC0 IPC5 IFS0 IEC0 IPC5 IFS0 IEC0 IPC6 IFS0 IEC0 IPC6 IFS0 IEC0 IPC6 IFS1 IFS1 IFS1 IFS1 IFS1 IFS1 IFS1 IEC1 IEC1 IEC1 IEC1 IEC1 IEC1 IEC1 IPC6 IPC7 IPC7 IPC7 IPC7 IPC7 IPC7 Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX General Purpose Family Features” and TABLE 2: “PIC32MX2XX USB Family Features” for the lists of available peripherals. DS61168D-page 88 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED) IRQ Vector # # 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 32 32 32 33 33 33 34 34 34 35 35 36 36 36 37 37 37 38 38 38 39 40 41 42 43 Interrupt Bit Location Flag IFS1 IFS1 IFS1 Enable IEC1 IEC1 IEC1 Priority IPC8 IPC8 IPC8 Sub-priority IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC8 IPC9 IPC9 IPC9 IPC9 IPC9 IPC9 IPC9 IPC9 IPC9 IPC9 IPC10 IPC10 Persistent Interrupt Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No Interrupt Source(1) U1E – UART1 Fault U1RX – UART1 Receive Done U1TX – UART1 Transfer Done I2C1B – I2C1 Bus Collision Event I2C1S – I2C1 Slave Event I2C1M – I2C1 Master Event CNA – PORTA Input Change Interrupt CNB – PORTB Input Change Interrupt CNC – PORTC Input Change Interrupt PMP – Parallel Master Port PMPE – Parallel Master Port Error SPI2E – SPI2 Fault SPI2RX – SPI2 Receive Done SPI2TX – SPI2 Transfer Done U2E – UART2 Error U2RX – UART2 Receiver U2TX – UART2 Transmitter I2C2B – I2C2 Bus Collision Event I2C2S – I2C2 Slave Event I2C2M – I2C2 Master Event CTMU – CTMU Event DMA0 – DMA Channel 0 DMA1 – DMA Channel 1 DMA2 – DMA Channel 2 DMA3 – DMA Channel 3 Note 1: IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IPC8 IFS1 IEC1 IFS1 IEC1 IFS1 IEC1 IPC9 IPC9 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC9 IFS1 IEC1 IPC10 IFS1 IEC1 IPC10 IFS1 IEC1 IPC10 IPC10 IFS1 IEC1 IPC10 IPC10 Lowest Natural Order Priority Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX1XX General Purpose Family Features” and TABLE 2: “PIC32MX2XX USB Family Features” for the lists of available peripherals. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 89 PIC32MX1XX/2XX REGISTER 7-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 INTCON: INTERRUPT CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — R/W-0 R/W-0 — R/W-0 SS0 R/W-0 R/W-0 — U-0 — U-0 — U-0 MVEC R/W-0 — R/W-0 TPC R/W-0 — — — INT4EP INT3EP INT2EP INT1EP INT0EP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-17 Unimplemented: Read as ‘0’ bit 16 SS0: Single Vector Shadow Register Set bit 1 = Single vector is presented with a shadow register set 0 = Single vector is not presented with a shadow register set bit 15-13 Unimplemented: Read as ‘0’ bit 12 MVEC: Multi Vector Configuration bit 1 = Interrupt controller configured for multi vectored mode 0 = Interrupt controller configured for single vectored mode bit 11 Unimplemented: Read as ‘0’ bit 10-8 TPC: Temporal Proximity Control bits 111 = Interrupts of group priority 7 or lower start the TP timer • • • bit 7-5 bit 4 bit 3 bit 2 bit 1 bit 0 010 = Interrupts of group priority 2 or lower start the TP timer 001 = Interrupts of group priority 1 start the IP timer 000 = Disables proximity timer Unimplemented: Read as ‘0’ INT4EP: External Interrupt 4 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT3EP: External Interrupt 3 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT2EP: External Interrupt 2 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT1EP: External Interrupt 1 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge INT0EP: External Interrupt 0 Edge Polarity Control bit 1 = Rising edge 0 = Falling edge DS61168D-page 90 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 7-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 INTSTAT: INTERRUPT STATUS REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 — R/W-0 — R/W-0 R/W-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 RIPL(1) R/W-0 — — VEC(1) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-11 Unimplemented: Read as ‘0’ bit 10-8 RIPL: Requested Priority Level bits(1) 000-111 = The priority level of the latest interrupt presented to the CPU bit 7-6 Unimplemented: Read as ‘0’ bit 5-0 VEC: Interrupt Vector bits(1) 00000-11111 = The interrupt vector that is presented to the CPU Note 1: This value should only be used when the interrupt controller is configured for Single Vector mode. REGISTER 7-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 TPTMR: TEMPORAL PROXIMITY TIMER REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 TPTMR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 TPTMR Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown TPTMR: Temporal Proximity Timer Reload bits Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by an interrupt event. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 91 PIC32MX1XX/2XX REGISTER 7-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 IFSx: INTERRUPT FLAG STATUS REGISTER(1) Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 IFS31 R/W-0 IFS30 R/W-0 IFS29 R/W-0 IFS28 R/W-0 IFS27 R/W-0 IFS26 R/W-0 IFS25 R/W-0 IFS24 R/W-0 IFS23 R/W-0 IFS22 R/W-0 IFS21 R/W-0 IFS20 R/W-0 IFS19 R/W-0 IFS18 R/W-0 IFS17 R/W-0 IFS16 R/W-0 IFS15 R/W-0 IFS14 R/W-0 IFS13 R/W-0 IFS12 R/W-0 IFS11 R/W-0 IFS10 R/W-0 IFS09 R/W-0 IFS08 R/W-0 IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00 Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IFS31-IFS00: Interrupt Flag Status bits 1 = Interrupt request has occurred 0 = No interrupt request has occurred This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit definitions. Note 1: REGISTER 7-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 IECx: INTERRUPT ENABLE CONTROL REGISTER(1) Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 IEC31 R/W-0 IEC30 R/W-0 IEC29 R/W-0 IEC28 R/W-0 IEC27 R/W-0 IEC26 R/W-0 IEC25 R/W-0 IEC24 R/W-0 IEC23 R/W-0 IEC22 R/W-0 IEC21 R/W-0 IEC20 R/W-0 IEC19 R/W-0 IEC18 R/W-0 IEC17 R/W-0 IEC16 R/W-0 IEC15 R/W-0 IEC14 R/W-0 IEC13 R/W-0 IEC12 R/W-0 IEC11 R/W-0 IEC10 R/W-0 IEC09 R/W-0 IEC08 R/W-0 IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00 Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown IEC31-IEC00: Interrupt Enable bits 1 = Interrupt is enabled 0 = Interrupt is disabled This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit definitions. Note 1: DS61168D-page 92 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 7-6: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 IPCx: INTERRUPT PRIORITY CONTROL REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 — U-0 — U-0 — U-0 R/W-0 IP03 R/W-0 R/W-0 IS03 R/W-0 R/W-0 — U-0 — U-0 — U-0 R/W-0 IP02 R/W-0 R/W-0 IS02 R/W-0 R/W-0 — U-0 — U-0 — U-0 R/W-0 IP01 R/W-0 R/W-0 IS01 R/W-0 R/W-0 — — — IP00 IS00 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-26 IP03: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 25-24 IS03: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpiority is 0 bit 23-21 Unimplemented: Read as ‘0’ bit 20-18 IP02: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled bit 17-16 IS02: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 bit 15-13 Unimplemented: Read as ‘0’ bit 12-10 IP01: Interrupt Priority bits 111 = Interrupt priority is 7 • • • 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled Note 1: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 93 PIC32MX1XX/2XX REGISTER 7-6: bit 9-8 IPCx: INTERRUPT PRIORITY CONTROL REGISTER(1) (CONTINUED) bit 7-5 bit 4-2 IS01: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 Unimplemented: Read as ‘0’ IP00: Interrupt Priority bits 111 = Interrupt priority is 7 • • • bit 1-0 010 = Interrupt priority is 2 001 = Interrupt priority is 1 000 = Interrupt is disabled IS00: Interrupt Subpriority bits 11 = Interrupt subpriority is 3 10 = Interrupt subpriority is 2 01 = Interrupt subpriority is 1 00 = Interrupt subpriority is 0 This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit definitions. Note 1: DS61168D-page 94 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 8.0 OSCILLATOR CONFIGURATION Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 6. “Oscillator Configuration” (DS61112) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC32MX1XX/2XX oscillator system has the following modules and features: • A Total of four external and internal oscillator options as clock sources • On-Chip PLL with user-selectable input divider, multiplier and output divider to boost operating frequency on select internal and external oscillator sources • On-Chip user-selectable divisor postscaler on select oscillator sources • Software-controllable switching between various clock sources • A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown • Dedicated On-Chip PLL for USB peripheral A block diagram of the oscillator system is provided in Figure 8-1. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 95 PIC32MX1XX/2XX FIGURE 8-1: PIC32MX1XX/2XX FAMILY CLOCK DIAGRAM USB PLL(5) UFIN USB Clock (48 MHz) div x PLL x24 div 2 UFRCEN UPLLEN REFCLKI POSC FRC LPRC SOSC PBCLK SYSCLK ROTRIM (M) OE REFCLKO UFIN = 4 MHz UPLLIDIV System USB PLL 4 MHz ≤FIN ≤5 MHz FIN div x PLL FPLLIDIV COSC PLLMULT div y PLLODIV M ÷ ⎛ N + ----------⎞ ⎝ 512⎠ RODIV (N) ROSEL To SPI XTPLL, HSPLL, ECPLL, FRCPLL Primary Oscillator (POSC) C1(3) OSC1 RF(2) XTAL RS(1) OSC2(4) div 2 To ADC FRC Oscillator 8 MHz typical TUN LPRC Oscillator Postscaler FRCDIV To Internal Logic Enable POSC (XT, HS, EC) Postscaler div x Peripherals PBCLK (TPB) FRC div 16 PBDIV C2(3) FRC/16 CPU and Select Peripherals SYSCLK FRCDIV 31.25 kHz typical LPRC Secondary Oscillator (SOSC) SOSCO 32.768 kHz SOSC SOSCEN and FSOSCEN SOSCI Clock Control Logic Fail-Safe Clock Monitor FSCM INT FSCM Event NOSC COSC FSCMEN OSWEN WDT, PWRT Timer1, RTCC Notes: 1. 2. 3. 4. 5. A series resistor, RS, may be required for AT strip cut crystals. The internal feedback resistor, RF, is typically in the range of 2 to 10 MΩ. Refer to Section 6. “Oscillator Configuration” (DS61112) in the “PIC32 Family Reference Manual” for help in determining the best oscillator components. PBCLK out is available on the OSC2 pin in certain clock modes. USB PLL is available on PIC32MX2XX devices only. DS61168D-page 96 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 OSCCON: OSCILLATOR CONTROL REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 R/W-y R-1 R-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-y R/W-y R/W-y U-0 Bit 26/18/10/2 R/W-0 R/W-y R/W-y R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-1 R/W-y R/W-y R/W-0 — U-0 — R-0 R-0 R-0 PLLODIV R/W-y R-0 R/W-0 FRCDIV R/W-y — U-0 SOSCRDY PBDIVRDY COSC R-0 PBDIV — R/W-0 PLLMULT R/W-y — R/W-0 NOSC R/W-y CLKLOCK ULOCK(2) SLOCK SLPEN CF UFRCEN(2) SOSCEN OSWEN Legend: R = Readable bit -n = Value at POR y = Value set from Configuration bits on POR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-27 PLLODIV: Output Divider for PLL 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 26-24 FRCDIV: Internal Fast RC (FRC) Oscillator Clock Divider bits 111 = FRC divided by 256 110 = FRC divided by 64 101 = FRC divided by 32 100 = FRC divided by 16 011 = FRC divided by 8 010 = FRC divided by 4 001 = FRC divided by 2 (default setting) 000 = FRC divided by 1 bit 23 Unimplemented: Read as ‘0’ bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit 1 = Indicates that the Secondary Oscillator is running and is stable 0 = Secondary Oscillator is still warming up or is turned off bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit 1 = PBDIV bits can be written 0 = PBDIV bits cannot be written bit 20-19 PBDIV: Peripheral Bus Clock (PBCLK) Divisor bits 11 = PBCLK is SYSCLK divided by 8 (default) 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 Note 1: 2: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. This bit is available on PIC32MX2XX devices only. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 97 PIC32MX1XX/2XX REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER(1) bit 18-16 PLLMULT: Phase-Locked Loop (PLL) Multiplier bits 111 = Clock is multiplied by 24 110 = Clock is multiplied by 21 101 = Clock is multiplied by 20 100 = Clock is multiplied by 19 011 = Clock is multiplied by 18 010 = Clock is multiplied by 17 001 = Clock is multiplied by 16 000 = Clock is multiplied by 15 bit 15 Unimplemented: Read as ‘0’ bit 14-12 COSC: Current Oscillator Selection bits 111 = Internal Fast RC (FRC) Oscillator divided by OSCCON bits 110 = Internal Fast RC (FRC) Oscillator divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (POSC) (XT, HS or EC) 001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast RC (FRC) Oscillator bit 11 Unimplemented: Read as ‘0’ bit 10-8 NOSC: New Oscillator Selection bits 111 = Internal Fast RC Oscillator (FRC) divided by OSCCON bits 110 = Internal Fast RC Oscillator (FRC) divided by 16 101 = Internal Low-Power RC (LPRC) Oscillator 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL) 010 = Primary Oscillator (XT, HS or EC) 001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL) 000 = Internal Fast Internal RC Oscillator (FRC) bit 7 On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1). CLKLOCK: Clock Selection Lock Enable bit If clock switching and monitoring is disabled (FCKSM = 1x): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified If clock switching and monitoring is enabled (FCKSM = 0x): Clock and PLL selections are never locked and may be modified. ULOCK: USB PLL Lock Status bit(2) 1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied 0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or USB PLL is disabled SLOCK: PLL Lock Status bit 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled SLPEN: Sleep Mode Enable bit 1 = Device will enter Sleep mode when a WAIT instruction is executed 0 = Device will enter Idle mode when a WAIT instruction is executed CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. This bit is available on PIC32MX2XX devices only. bit 6 bit 5 bit 4 bit 3 Note 1: 2: DS61168D-page 98 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-1: bit 2 OSCCON: OSCILLATOR CONTROL REGISTER(1) bit 1 bit 0 UFRCEN: USB FRC Clock Enable bit(2) 1 = Enable FRC as the clock source for the USB clock source 0 = Use the Primary Oscillator or USB PLL as the USB clock source SOSCEN: Secondary Oscillator (SOSC) Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to selection specified by NOSC bits 0 = Oscillator switch is complete Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. This bit is available on PIC32MX2XX devices only. Note 1: 2: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 99 PIC32MX1XX/2XX REGISTER 8-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 OSCTUN: FRC TUNING REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — R-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — — TUN(2) y = Value set from Configuration bits on POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Legend: R = Readable bit -n = Value at POR bit 31-6 bit 5-0 Unimplemented: Read as ‘0’ TUN: FRC Oscillator Tuning bits(2) 100000 = Center frequency -12.5% 100001 = • • • 111111 = 000000 = Center frequency. Oscillator runs at minimal frequency (8 MHz) 000001 = • • • 011110 = 011111 = Center frequency +12.5% Note 1: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. 2: OSCTUN functionality has been provided to help customers compensate for temperature effects on the FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither characterized, nor tested. DS61168D-page 100 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 — R/W-0 R/W-0 R/W-0 R/W-0 RODIV R/W-0 (3) R/W-0 R/W-0 R/W-0 RODIV R/W-0 U-0 R/W-0 R/W-0 (3) U-0 R/W-0, HC R-0, HS, HC R/W-0 ON U-0 — U-0 SIDL U-0 OE U-0 RSLP (2) — R/W-0 DIVSWEN R/W-0 ACTIVE R/W-0 R/W-0 — — — — ROSEL (1) Legend: R = Readable bit -n = Value at POR HC = Hardware Clearable HS = Hardware Settable W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 31 Unimplemented: Read as ‘0’ bit 30-16 RODIV Reference Clock Divider bits(1) 111111111111111 = Output clock is source clock frequency divided by 65,534 111111111111110 = Output clock is source clock frequency divided by 65,532 • • • 000000000000010 = Output clock is source clock frequency divided by 4 000000000000001 = Output clock is source clock frequency divided by 2 000000000000000 = Output clock is same frequency as source clock (no divider) bit 15 ON: Output Enable bit 1 = Reference Oscillator Module enabled 0 = Reference Oscillator Module disabled Unimplemented: Read as ‘0’ SIDL: Peripheral Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode OE: Reference Clock Output Enable bit 1 = Reference clock is driven out on REFCLKO pin 0 = Reference clock is not driven out on REFCLKO pin RSLP: Reference Oscillator Module Run in Sleep bit(2) 1 = Reference Oscillator Module output continues to run in Sleep 0 = Reference Oscillator Module output is disabled in Sleep Unimplemented: Read as ‘0’ DIVSWEN: Divider Switch Enable bit 1 = Divider switch is in progress 0 = Divider switch is complete ACTIVE: Reference Clock Request Status bit 1 = Reference clock request is active 0 = Reference clock request is not active The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result. This bit is ignored when the ROSEL bits = 0000 or 0001. While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 Note 1: 2: 3: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 101 PIC32MX1XX/2XX REGISTER 8-3: bit 7-4 bit 3-0 REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER Unimplemented: Read as ‘0’ ROSEL: Reference Clock Source Select bits(1) 1111 = Reserved; do not use • • • 1001 = Reserved; do not use 1000 = REFCLKI 0111 = System PLL output 0110 = USB PLL output 0101 = SOSC 0100 = LPRC 0011 = FRC 0010 = POSC 0001 = PBCLK 0000 = SYSCLK The ROSEL and RODIV bits should not be written while the ACTIVE bit is ‘1’, as undefined behavior may result. This bit is ignored when the ROSEL bits = 0000 or 0001. While the ON bit is set to ‘1’, writes to these bits do not take effect until the DIVSWEN bit is also set to’1’. Note 1: 2: 3: DS61168D-page 102 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 8-4: Bit Range 31:24 23:16 15:8 7:0 REFOTRIM: REFERENCE OSCILLATOR TRIM REGISTER(1,2) Bit 30/22/14/6 R/W-0 Bit 31/23/15/7 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 ROTRIM R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ROTRIM U-0 — R-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR y = Value set from Configuration bits on POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-23 ROTRIM: Reference Oscillator Trim bits 111111111 = 511/512 divisor added to RODIV value 111111110 = 510/512 divisor added to RODIV value • • • 100000000 = 256/512 divisor added to RODIV value • • • 000000010 = 2/512 divisor added to RODIV value 000000001 = 1/512 divisor added to RODIV value 000000000 = 0/512 divisor added to RODIV value bit 22-0 Unimplemented: Read as ‘0’ Note 1: While the ON bit (REFOCON) is ‘1’, writes to this register do not take effect until the DIVSWEN bit is also set to ‘1’. 2: This register is not available on all devices. Refer to the specific device data sheet for availability. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 103 PIC32MX1XX/2XX NOTES: DS61168D-page 104 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 9.0 DIRECT MEMORY ACCESS (DMA) CONTROLLER • Automatic word-size detection: - Transfer granularity, down to byte level - Bytes need not be word-aligned at source and destination • Fixed priority channel arbitration • Flexible DMA channel operating modes: - Manual (software) or automatic (interrupt) DMA requests - One-Shot or Auto-Repeat Block Transfer modes - Channel-to-channel chaining • Flexible DMA requests: - A DMA request can be selected from any of the peripheral interrupt sources - Each channel can select any (appropriate) observable interrupt as its DMA request source - A DMA transfer abort can be selected from any of the peripheral interrupt sources - Pattern (data) match transfer termination • Multiple DMA channel status interrupts: - DMA channel block transfer complete - Source empty or half empty - Destination full or half full - DMA transfer aborted due to an external event - Invalid DMA address generated • DMA debug support features: - Most recent address accessed by a DMA channel - Most recent DMA channel to transfer data • CRC Generation module: - CRC module can be assigned to any of the available channels - CRC module is highly configurable Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 31. “Direct Memory Access (DMA) Controller” (DS61117) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC32 Direct Memory Access (DMA) controller is a bus master module useful for data transfers between different devices without CPU intervention. The source and destination of a DMA transfer can be any of the memory mapped modules existent in the PIC32 (such as Peripheral Bus (PBUS) devices: SPI, UART, PMP, etc.) or memory itself. Following are some of the key features of the DMA controller module: • Four identical channels, each featuring: - Auto-increment source and destination address registers - Source and destination pointers - Memory to memory and memory to peripheral transfers FIGURE 9-1: INT Controller DMA BLOCK DIAGRAM System IRQ Peripheral Bus Address Decoder SE Channel 0 Control I0 L Channel 1 Control I1 I2 Y Bus Interface Device Bus + Bus Arbitration Global Control (DMACON) Channel n Control In SE L Channel Priority Arbitration © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 105 PIC32MX1XX/2XX REGISTER 9-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DMACON: DMA CONTROLLER CONTROL REGISTER Bit Bit Bit 30/22/14/6 29/21/13/5 28/20/12/4 U-0 U-0 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) U-0 — U-0 — U-0 — R/W-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 SUSPEND U-0 DMABUSY U-0 — U-0 — U-0 — U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: DMA On bit(1) 1 = DMA module is enabled 0 = DMA module is disabled SUSPEND: DMA Suspend bit 1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus 0 = DMA operates normally DMABUSY: DMA Module Busy bit(4) 1 = DMA module is active 0 = DMA module is disabled and not actively transferring data Unimplemented: Read as ‘0’ When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14-13 Unimplemented: Read as ‘0’ bit 12 bit 11 bit 10-0 Note 1: DS61168D-page 106 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DMASTAT: DMA STATUS REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — R-0 — R-0 — R-0 — — — — RDWR DMACH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-4 Unimplemented: Read as ‘0’ bit 3 RDWR: Read/Write Status bit 1 = Last DMA bus access was a read 0 = Last DMA bus access was a write DMACH: DMA Channel bits These bits contain the value of the most recent active DMA channel. bit 2-0 REGISTER 9-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R-0 DMAADDR: DMA ADDRESS REGISTER Bit 30/22/14/6 R-0 Bit 29/21/13/5 R-0 Bit 28/20/12/4 R-0 Bit 27/19/11/3 R-0 Bit 26/18/10/2 R-0 Bit 25/17/9/1 R-0 Bit 24/16/8/0 R-0 DMAADDR R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0 DMAADDR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DMAADDR: DMA Module Address bits These bits contain the address of the most recent DMA access. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 107 PIC32MX1XX/2XX REGISTER 9-4: Bit Range 31:24 23:16 15:8 7:0 DCRCCON: DMA CRC CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 R/W-0 — U-0 — U-0 BYTO U-0 U-0 WBO(1) U-0 — U-0 — U-0 BITO U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 U-0 U-0 PLEN R/W-0 R/W-0 R/W-0 CRCEN CRCAPP(1) CRCTYP — — CRCCH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-30 Unimplemented: Read as ‘0’ bit 29-28 BYTO: CRC Byte Order Selection bits 11 = Endian byte swap on half-word boundaries (i.e., source half-word order with reverse source byte order per half-word) 10 = Swap half-words on word boundaries (i.e., reverse source half-word order with source byte order per half-word) 01 = Endian byte swap on word boundaries (i.e., reverse source byte order) 00 = No swapping (i.e., source byte order) bit 27 WBO: CRC Write Byte Order Selection bit(1) 1 = Source data is written to the destination re-ordered as defined by BYTO 0 = Source data is written to the destination unaltered BITO: CRC Bit Order Selection bit(4) When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): 1 = The IP header checksum is calculated Least Significant bit (LSb) first (i.e., reflected) 0 = The IP header checksum is calculated Most Significant bit (MSb) first (i.e., not reflected) When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): 1 = The LFSR CRC is calculated Least Significant bit first (i.e., reflected) 0 = The LFSR CRC is calculated Most Significant bit first (i.e., not reflected) bit 23-13 Unimplemented: Read as ‘0’ bit 12-8 PLEN: Polynomial Length bits(1) When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): These bits are unused. When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): Denotes the length of the polynomial – 1. bit 7 CRCEN: CRC Enable bit 1 = CRC module is enabled and channel transfers are routed through the CRC module 0 = CRC module is disabled and channel transfers proceed normally When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. bit 26-25 Unimplemented: Read as ‘0’ bit 24 Note 1: DS61168D-page 108 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-4: bit 6 DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED) CRCAPP: CRC Append Mode bit(1) 1 = The DMA transfers data from the source into the CRC but NOT to the destination. When a block transfer completes the DMA writes the calculated CRC value to the location given by CHxDSA 0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the destination CRCTYP: CRC Type Selection bit 1 = The CRC module will calculate an IP header checksum 0 = The CRC module will calculate a LFSR CRC Unimplemented: Read as ‘0’ CRCCH: CRC Channel Select bits 111 = CRC is assigned to Channel 7 110 = CRC is assigned to Channel 6 101 = CRC is assigned to Channel 5 100 = CRC is assigned to Channel 4 011 = CRC is assigned to Channel 3 010 = CRC is assigned to Channel 2 001 = CRC is assigned to Channel 1 000 = CRC is assigned to Channel 0 When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set. bit 5 bit 4-3 bit 2-0 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 109 PIC32MX1XX/2XX REGISTER 9-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 DCRCDATA: DMA CRC DATA REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 DCRCDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCDATA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCDATA: CRC Data Register bits Writing to this register will seed the CRC generator. Reading from this register will return the current value of the CRC. Bits greater than PLEN will return ‘0’ on any read. When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written to this register is converted and read back in 1’s complement form (i.e., current IP header checksum value). When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): Bits greater than PLEN will return ‘0’ on any read. REGISTER 9-6: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 DCRCXOR: DMA CRCXOR ENABLE REGISTER(1,2,3) Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 DCRCXOR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 DCRCXOR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 DCRCXOR: CRC XOR Register bits When CRCTYP (DCRCCON) = 1 (CRC module is in IP Header mode): This register is unused. When CRCTYP (DCRCCON) = 0 (CRC module is in LFSR mode): 1 = Enable the XOR input to the Shift register 0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in the register DS61168D-page 110 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-7: Bit Range 31:24 23:16 15:8 7:0 DCHxCON: DMA CHANNEL x CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 CHBUSY CHEN R/W-0 (2) — R/W-0 — R/W-0 — R/W-0 — U-0 — R-0 — R/W-0 CHCHNS(1) R/W-0 CHAED CHCHN CHAEN — CHEDET CHPRI Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 CHBUSY: Channel Busy bit 1 = Channel is active or has been enabled 0 = Channel is inactive or has been disabled Unimplemented: Read as ‘0’ CHCHNS: Chain Channel Selection bit(1) 1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete) 0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete) CHEN: Channel Enable bit(2) 1 = Channel is enabled 0 = Channel is disabled CHAED: Channel Allow Events If Disabled bit 1 = Channel start/abort events will be registered, even if the channel is disabled 0 = Channel start/abort events will be ignored if the channel is disabled CHCHN: Channel Chain Enable bit 1 = Allow channel to be chained 0 = Do not allow channel to be chained CHAEN: Channel Automatic Enable bit 1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete 0 = Channel is disabled on block transfer complete Unimplemented: Read as ‘0’ CHEDET: Channel Event Detected bit 1 = An event has been detected 0 = No events have been detected CHPRI: Channel Priority bits 11 = Channel has priority 3 (highest) 10 = Channel has priority 2 01 = Channel has priority 1 00 = Channel has priority 0 The chain selection bit takes effect when chaining is enabled (i.e., CHCHN = 1). When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if available on the device variant) to see when the channel is suspended, as it may take some clock cycles to complete a current transaction before the channel is suspended. bit 14-9 bit 8 bit 7 bit 6 bit bit 4 bit 3 bit 2 bit 1-0 Note 1: 2: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 111 PIC32MX1XX/2XX REGISTER 9-8: Bit Range 31:24 23:16 15:8 7:0 DCHxECON: DMA CHANNEL x EVENT CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — R/W-1 R/W-1 S-0 — R/W-1 R/W-1 S-0 — R/W-1 R/W-1 R/W-0 — R/W-1 R/W-1 R/W-0 — R/W-1 (1) R/W-1 R/W-0 — R/W-1 R/W-1 U-0 — R/W-1 R/W-1 U-0 — R/W-1 R/W-1 U-0 CHAIRQ CHSIRQ(1) CFORCE CABORT PATEN SIRQEN AIRQEN — — — Legend: R = Readable bit -n = Value at POR S = Settable bit W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-16 CHAIRQ: Channel Transfer Abort IRQ bits(1) 11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag • • • bit 15-8 00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag 00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag CHSIRQ: Channel Transfer Start IRQ bits(1) 11111111 = Interrupt 255 will initiate a DMA transfer • • • bit 7 bit 6 bit 5 bit 4 bit 3 bit 2-0 Note 1: 00000001 = Interrupt 1 will initiate a DMA transfer 00000000 = Interrupt 0 will initiate a DMA transfer CFORCE: DMA Forced Transfer bit 1 = A DMA transfer is forced to begin when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ CABORT: DMA Abort Transfer bit 1 = A DMA transfer is aborted when this bit is written to a ‘1’ 0 = This bit always reads ‘0’ PATEN: Channel Pattern Match Abort Enable bit 1 = Abort transfer and clear CHEN on pattern match 0 = Pattern match is disabled SIRQEN: Channel Start IRQ Enable bit 1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs 0 = Interrupt number CHSIRQ is ignored and does not start a transfer AIRQEN: Channel Abort IRQ Enable bit 1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs 0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer Unimplemented: Read as ‘0’ See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources. DS61168D-page 112 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-9: Bit Range 31:24 23:16 15:8 7:0 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CHSDIE U-0 CHSHIE U-0 CHDDIE U-0 CHDHIE U-0 CHBCIE U-0 CHCCIE U-0 CHTAIE U-0 CHERIE U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23 CHSDIE: Channel Source Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHSHIE: Channel Source Half Empty Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDDIE: Channel Destination Done Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHDHIE: Channel Destination Half Full Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHBCIE: Channel Block Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHTAIE: Channel Transfer Abort Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled CHERIE: Channel Address Error Interrupt Enable bit 1 = Interrupt is enabled 0 = Interrupt is disabled Unimplemented: Read as ‘0’ CHSDIF: Channel Source Done Interrupt Flag bit 1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ) 0 = No interrupt is pending CHSHIF: Channel Source Half Empty Interrupt Flag bit 1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2) 0 = No interrupt is pending CHDDIF: Channel Destination Done Interrupt Flag bit 1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ) 0 = No interrupt is pending bit 22 bit 21 bit 20 bit 19 bit 18 bit 17 bit 16 bit 15-8 bit 7 bit 6 bit 5 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 113 PIC32MX1XX/2XX REGISTER 9-9: bit 4 DCHxINT: DMA CHANNEL x INTERRUPT CONTROL REGISTER (CONTINUED) CHDHIF: Channel Destination Half Full Interrupt Flag bit 1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2) 0 = No interrupt is pending CHBCIF: Channel Block Transfer Complete Interrupt Flag bit 1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a pattern match event occurs 0 = No interrupt is pending CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit 1 = A cell transfer has been completed (CHCSIZ bytes have been transferred) 0 = No interrupt is pending CHTAIF: Channel Transfer Abort Interrupt Flag bit 1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted 0 = No interrupt is pending CHERIF: Channel Address Error Interrupt Flag bit 1 = A channel address error has been detected Either the source or the destination address is invalid. 0 = No interrupt is pending bit 3 bit 2 bit 1 bit 0 DS61168D-page 114 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-10: Bit Range 31:24 23:16 15:8 7:0 DCHxSSA: DMA CHANNEL x SOURCE START ADDRESS REGISTER Bit 30/22/14/6 R/W-0 Bit 31/23/15/7 R/W-0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 R/W-0 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 CHSSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHSSA Legend: R = Readable bit -n = Value at POR bit 31-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CHSSA Channel Source Start Address bits Channel source start address. Note: This must be the physical address of the source. REGISTER 9-11: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 DCHxDSA: DMA CHANNEL x DESTINATION START ADDRESS REGISTER Bit 30/22/14/6 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 CHDSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CHDSA Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-0 CHDSA: Channel Destination Start Address bits Channel destination start address. Note: This must be the physical address of the destination. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 115 PIC32MX1XX/2XX REGISTER 9-12: Bit Range 31:24 23:16 15:8 7:0 DCHxSSIZ: DMA CHANNEL x SOURCE SIZE REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 CHSSIZ CHSSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSSIZ: Channel Source Size bits 1111111111111111 = 65,535 byte source size • • • 0000000000000010 = 2 byte source size 0000000000000001 = 1 byte source size 0000000000000000 = 65,536 byte source size REGISTER 9-13: Bit Range 31:24 23:16 15:8 7:0 DCHxDSIZ: DMA CHANNEL x DESTINATION SIZE REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 CHDSIZ CHDSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDSIZ: Channel Destination Size bits 1111111111111111 = 65,535 byte destination size • • • 0000000000000010 = 2 byte destination size 0000000000000001 = 1 byte destination size 0000000000000000 = 65,536 byte destination size DS61168D-page 116 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-14: Bit Range 31:24 23:16 15:8 7:0 DCHxSPTR: DMA CHANNEL x SOURCE POINTER REGISTER(1) Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 CHSPTR CHSPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHSPTR: Channel Source Pointer bits 1111111111111111 = Points to byte 65,535 of the source • • • 0000000000000001 = Points to byte 1 of the source 0000000000000000 = Points to byte 0 of the source Note 1: When in Pattern Detect mode, this register is reset on a pattern detect. REGISTER 9-15: Bit Range 31:24 23:16 15:8 7:0 DCHxDPTR: DMA CHANNEL x DESTINATION POINTER REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 CHDPTR CHDPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHDPTR: Channel Destination Pointer bits 1111111111111111 = Points to byte 65,535 of the destination • • • 0000000000000001 = Points to byte 1 of the destination 0000000000000000 = Points to byte 0 of the destination © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 117 PIC32MX1XX/2XX REGISTER 9-16: Bit Range 31:24 23:16 15:8 7:0 DCHxCSIZ: DMA CHANNEL x CELL-SIZE REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 — R/W-0 R/W-0 CHCSIZ CHCSIZ Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCSIZ: Channel Cell-Size bits 1111111111111111 = 65,535 bytes transferred on an event • • • 0000000000000010 = 2 bytes transferred on an event 0000000000000001= 1 byte transferred on an event 0000000000000000 = 65,536 bytes transferred on an event REGISTER 9-17: Bit Range 31:24 23:16 15:8 7:0 DCHxCPTR: DMA CHANNEL x CELL POINTER REGISTER(1) Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 — R-0 R-0 CHCPTR CHCPTR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CHCPTR: Channel Cell Progress Pointer bits 1111111111111111 = 65,535 bytes have been transferred since the last event • • • 0000000000000001 = 1 byte has been transferred since the last event 0000000000000000 = 0 bytes have been transferred since the last event Note 1: When in Pattern Detect mode, this register is reset on a pattern detect. DS61168D-page 118 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 9-18: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 DCHxDAT: DMA CHANNEL x PATTERN DATA REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CHPDAT Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CHPDAT: Channel Data Register bits Pattern Terminate mode: Data to be matched must be stored in this register to allow terminate on match. All other modes: Unused. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 119 PIC32MX1XX/2XX NOTES: DS61168D-page 120 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 10.0 USB ON-THE-GO (OTG) Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 27. “USB OnThe-Go (OTG)” (DS61126) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Universal Serial Bus (USB) module contains analog and digital components to provide a USB 2.0 full-speed and low-speed embedded host, full-speed device or OTG implementation with a minimum of external components. This module in Host mode is intended for use as an embedded host and therefore does not implement a UHCI or OHCI controller. The USB module consists of the clock generator, the USB voltage comparators, the transceiver, the Serial Interface Engine (SIE), a dedicated USB DMA controller, pull-up and pull-down resistors, and the register interface. A block diagram of the PIC32 USB OTG module is presented in Figure 10-1. The clock generator provides the 48 MHz clock required for USB full-speed and low-speed communication. The voltage comparators monitor the voltage on the VBUS pin to determine the state of the bus. The transceiver provides the analog translation between the USB bus and the digital logic. The SIE is a state machine that transfers data to and from the endpoint buffers and generates the hardware protocol for data transfers. The USB DMA controller transfers data between the data buffers in RAM and the SIE. The integrated pull-up and pull-down resistors eliminate the need for external signaling components. The register interface allows the CPU to configure and communicate with the module. The PIC32 USB module includes the following features: • • • • • • • • • USB Full-speed support for host and device Low-speed host support USB OTG support Integrated signaling resistors Integrated analog comparators for VBUS monitoring Integrated USB transceiver Transaction handshaking performed by hardware Endpoint buffering anywhere in system RAM Integrated DMA to access system RAM and Flash Note: The implementation and use of the USB specifications, as well as other third party specifications or technologies, may require licensing; including, but not limited to, USB Implementers Forum, Inc. (also referred to as USB-IF). The user is fully responsible for investigating and satisfying any applicable licensing obligations. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 121 PIC32MX1XX/2XX FIGURE 10-1: PIC32MX1XX/2XX FAMILY USB INTERFACE DIAGRAM FRC Oscillator 8 MHz Typical TUN(3) Primary Oscillator (POSC) OSC1 UFIN(4) Div x PLL Div 2 UPLLEN(5) UFRCEN(2) UPLLIDIV(5) OSC2 USB Module USB Voltage Comparators 48 MHz USB Clock(6) SRP Charge Bus SRP Discharge Full Speed Pull-up D+(1) Host Pull-down Transceiver Low Speed Pull-up Registers and Control Interface SIE D-(1) DMA Host Pull-down System RAM ID Pull-up ID(7) VBUSON(7) VUSB3V3 Transceiver Power 3.3V Note 1: 2: 3: 4: 5: 6: 7: Pins can be used as digital inputs when USB is not enabled. This bit field is contained in the OSCCON register. This bit field is contained in the OSCTRM register. USB PLL UFIN requirements: 4 MHz. This bit field is contained in the DEVCFG2 register. A 48 MHz clock is required for proper USB operation. Pins can be used as GPIO when the USB module is disabled. DS61168D-page 122 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 U1OTGIR: USB OTG INTERRUPT STATUS REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — U-0 — R/WC-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF Legend: R = Readable bit -n = Value at POR WC = Write ‘1’ to clear W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No change in ID state detected T1MSECIF: 1 Millisecond Timer bit 1 = 1 millisecond timer has expired 0 = 1 millisecond timer has not expired LSTATEIF: Line State Stable Indicator bit 1 = USB line state has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up 0 = Activity has not been detected SESVDIF: Session Valid Change Indicator bit 1 = VBUS voltage has dropped below the session end level 0 = VBUS voltage has not dropped below the session end level SESENDIF: B-Device VBUS Change Indicator bit 1 = A change on the session end input was detected 0 = No change on the session end input was detected Unimplemented: Read as ‘0’ VBUSVDIF: A-Device VBUS Change Indicator bit 1 = Change on the session valid input detected 0 = No change on the session valid input detected bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 123 PIC32MX1XX/2XX REGISTER 10-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — U-0 — R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 IDIE: ID Interrupt Enable bit 1 = ID interrupt enabled 0 = ID interrupt disabled T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = 1 millisecond timer interrupt enabled 0 = 1 millisecond timer interrupt disabled LSTATEIE: Line State Interrupt Enable bit 1 = Line state interrupt enabled 0 = Line state interrupt disabled ACTVIE: Bus Activity Interrupt Enable bit 1 = ACTIVITY interrupt enabled 0 = ACTIVITY interrupt disabled SESVDIE: Session Valid Interrupt Enable bit 1 = Session valid interrupt enabled 0 = Session valid interrupt disabled SESENDIE: B-Session End Interrupt Enable bit 1 = B-session end interrupt enabled 0 = B-session end interrupt disabled Unimplemented: Read as ‘0’ VBUSVDIE: A-VBUS Valid Interrupt Enable bit 1 = A-VBUS valid interrupt enabled 0 = A-VBUS valid interrupt disabled bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168D-page 124 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 U1OTGSTAT: USB OTG STATUS REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — U-0 — R-0 — U-0 — R-0 — R-0 — U-0 — R-0 ID — LSTATE — SESVD SESEND — VBUSVD Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 ID: ID Pin State Indicator bit 1 = No cable is attached or a type B cable has been plugged into the USB receptacle 0 = A “type A” OTG cable has been plugged into the USB receptacle Unimplemented: Read as ‘0’ LSTATE: Line State Stable Indicator bit 1 = USB line state (U1CON and U1CON) has been stable for the previous 1 ms 0 = USB line state (U1CON and U1CON) has not been stable for the previous 1 ms Unimplemented: Read as ‘0’ SESVD: Session Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A or B device 0 = VBUS voltage is below Session Valid on the A or B device SESEND: B-Session End Indicator bit 1 = VBUS voltage is below Session Valid on the B device 0 = VBUS voltage is above Session Valid on the B device Unimplemented: Read as ‘0’ VBUSVD: A-VBUS Valid Indicator bit 1 = VBUS voltage is above Session Valid on the A device 0 = VBUS voltage is below Session Valid on the A device bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 125 PIC32MX1XX/2XX REGISTER 10-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 U1OTGCON: USB OTG CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor is enabled 0 = D+ data line pull-up resistor is disabled DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor is enabled 0 = D- data line pull-up resistor is disabled DPPULDWN: D+ Pull-Down Enable bit 1 = D+ data line pull-down resistor is enabled 0 = D+ data line pull-down resistor is disabled DMPULDWN: D- Pull-Down Enable bit 1 = D- data line pull-down resistor is enabled 0 = D- data line pull-down resistor is disabled VBUSON: VBUS Power-on bit 1 = VBUS line is powered 0 = VBUS line is not powered OTGEN: OTG Functionality Enable bit 1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control 0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control VBUSCHG: VBUS Charge Enable bit 1 = VBUS line is charged through a pull-up resistor 0 = VBUS line is not charged through a resistor VBUSDIS: VBUS Discharge Enable bit 1 = VBUS line is discharged through a pull-down resistor 0 = VBUS line is not discharged through a resistor bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168D-page 126 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-5: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 7:0 U-0 U1PWRC: USB POWER CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — U-0 — U-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — R/W-0 UACTPND — — USLPGRD USBBUSY — USUSPEND USBPWR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 UACTPND: USB Activity Pending bit 1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet 0 = An interrupt is not pending Unimplemented: Read as ‘0’ USLPGRD: USB Sleep Entry Guard bit 1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending 0 = USB module does not block Sleep entry USBBUSY: USB Module Busy bit(1) 1 = USB module is active or disabled, but not ready to be enabled 0 = USB module is not active and is ready to be enabled Note: bit 2 bit 1 When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all USB module registers produce undefined results. bit 6-5 bit 4 bit 3 Unimplemented: Read as ‘0’ USUSPEND: USB Suspend Mode bit 1 = USB module is placed in Suspend mode (The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.) 0 = USB module operates normally USBPWR: USB Operation Enable bit 1 = USB module is turned on 0 = USB module is disabled (Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power consumption.) bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 127 PIC32MX1XX/2XX REGISTER 10-6: Bit Bit Range 31/23/15/7 31:24 23:16 15:8 U-0 U1IR: USB INTERRUPT REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R-0 — URSTIF R/WC-0, HS (5) 7:0 STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4) DETACHIF(6) Legend: R = Readable bit -n = Value at POR WC = Write ‘1’ to clear W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIF: STALL Handshake Interrupt bit 1 = In Host mode a STALL handshake was received during the handshake phase of the transaction In Device mode a STALL handshake was transmitted during the handshake phase of the transaction 0 = STALL handshake has not been sent ATTACHIF: Peripheral Attach Interrupt bit(1) 1 = Peripheral attachment was detected by the USB module 0 = Peripheral attachment was not detected RESUMEIF: Resume Interrupt bit(2) 1 = K-State is observed on the D+ or D- pin for 2.5 µs 0 = K-State is not observed IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected TRNIF: Token Processing Complete Interrupt bit(3) 1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information 0 = Processing of current token not complete SOFIF: SOF Token Interrupt bit 1 = SOF token received by the peripheral or the SOF threshold reached by the host 0 = SOF token was not received nor threshold reached UERRIF: USB Error Condition Interrupt bit(4) 1 = Unmasked error condition has occurred 0 = Unmasked error condition has not occurred This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for 2.5 µs, and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 Note 1: 2: 3: 4: 5: 6: DS61168D-page 128 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-6: bit 0 U1IR: USB INTERRUPT REGISTER (CONTINUED) URSTIF: USB Reset Interrupt bit (Device mode)(5) 1 = Valid USB Reset has occurred 0 = No USB Reset has occurred DETACHIF: USB Detach Interrupt bit (Host mode)(6) 1 = Peripheral detachment was detected by the USB module 0 = Peripheral detachment was not detected This bit is valid only if the HOSTEN bit is set (see Register 10-11), there is no activity on the USB for 2.5 µs, and the current bus state is not SE0. When not in Suspend mode, this interrupt should be disabled. Clearing this bit will cause the STAT FIFO to advance. Only error conditions enabled through the U1EIE register will set this bit. Device mode. Host mode. Note 1: 2: 3: 4: 5: 6: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 129 PIC32MX1XX/2XX REGISTER 10-7: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 U-0 U1IE: USB INTERRUPT ENABLE REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 7:0 STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1) URSTIE(2) DETACHIE(3) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = STALL interrupt enabled 0 = STALL interrupt disabled ATTACHIE: ATTACH Interrupt Enable bit 1 = ATTACH interrupt enabled 0 = ATTACH interrupt disabled RESUMEIE: RESUME Interrupt Enable bit 1 = RESUME interrupt enabled 0 = RESUME interrupt disabled IDLEIE: Idle Detect Interrupt Enable bit 1 = Idle interrupt enabled 0 = Idle interrupt disabled TRNIE: Token Processing Complete Interrupt Enable bit 1 = TRNIF interrupt enabled 0 = TRNIF interrupt disabled SOFIE: SOF Token Interrupt Enable bit 1 = SOFIF interrupt enabled 0 = SOFIF interrupt disabled UERRIE: USB Error Interrupt Enable bit(1) 1 = USB Error interrupt enabled 0 = USB Error interrupt disabled URSTIE: USB Reset Interrupt Enable bit(2) 1 = URSTIF interrupt enabled 0 = URSTIF interrupt disabled DETACHIE: USB Detach Interrupt Enable bit(3) 1 = DATTCHIF interrupt enabled 0 = DATTCHIF interrupt disabled For an interrupt to propagate USBIF, the UERRIE bit (U1IE) must be set. Device mode. Host mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS61168D-page 130 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-8: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 U-0 U1EIR: USB ERROR INTERRUPT STATUS REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS — R/WC-0, HS 7:0 BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF CRC5EF(3,4) EOFEF(5) PIDEF Legend: R = Readable bit -n = Value at POR WC = Write ‘1’ to clear W = Writable bit ‘1’ = Bit is set HS = Hardware Settable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Packet rejected due to bit stuff error 0 = Packet accepted BMXEF: Bus Matrix Error Flag bit 1 = The base address, of the BDT, or the address of an individual buffer pointed to by a BDT entry, is invalid. 0 = No address error DMAEF: DMA Error Flag bit(1) 1 = USB DMA error condition detected 0 = No DMA error BTOEF: Bus Turnaround Time-Out Error Flag bit(2) 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out DFN8EF: Data Field Size Error Flag bit 1 = Data field received is not an integral number of bytes 0 = Data field received is an integral number of bytes CRC16EF: CRC16 Failure Flag bit 1 = Data packet rejected due to CRC16 error 0 = Data packet accepted This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: 2: 3: 4: 5: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 131 PIC32MX1XX/2XX REGISTER 10-8: bit 1 U1EIR: USB ERROR INTERRUPT STATUS REGISTER (CONTINUED) CRC5EF: CRC5 Host Error Flag bit(3,4) 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted EOFEF: EOF Error Flag bit(5) 1 = EOF error condition detected 0 = No EOF error condition PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed This type of error occurs when the module’s request for the DMA bus is not granted in time to service the module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer size is not sufficient to store the received data packet causing it to be truncated. This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP) has elapsed. This type of error occurs when the module is transmitting or receiving data and the SOF counter has reached zero. Device mode. Host mode. bit 0 Note 1: 2: 3: 4: 5: DS61168D-page 132 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-9: Bit Range 31:24 23:16 15:8 Bit 31/23/15/7 U-0 U1EIE: USB ERROR INTERRUPT ENABLE REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 7:0 BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE CRC5EE(2) EOFEE(3) PIDEE Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = BTSEF interrupt enabled 0 = BTSEF interrupt disabled BMXEE: Bus Matrix Error Interrupt Enable bit 1 = BMXEF interrupt enabled 0 = BMXEF interrupt disabled DMAEE: DMA Error Interrupt Enable bit 1 = DMAEF interrupt enabled 0 = DMAEF interrupt disabled BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = BTOEF interrupt enabled 0 = BTOEF interrupt disabled DFN8EE: Data Field Size Error Interrupt Enable bit 1 = DFN8EF interrupt enabled 0 = DFN8EF interrupt disabled CRC16EE: CRC16 Failure Interrupt Enable bit 1 = CRC16EF interrupt enabled 0 = CRC16EF interrupt disabled CRC5EE: CRC5 Host Error Interrupt Enable bit(2) 1 = CRC5EF interrupt enabled 0 = CRC5EF interrupt disabled EOFEE: EOF Error Interrupt Enable bit(3) 1 = EOF interrupt enabled 0 = EOF interrupt disabled PIDEE: PID Check Failure Interrupt Enable bit 1 = PIDEF interrupt enabled 0 = PIDEF interrupt disabled For an interrupt to propagate USBIF, the UERRIE bit (U1IE) must be set. Device mode. Host mode. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 133 PIC32MX1XX/2XX REGISTER 10-10: U1STAT: USB STATUS REGISTER(1) Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-x — R-x — R-x — R-x — R-x — R-x — U-0 — U-0 ENDPT DIR PPBI — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 ENDPT: Encoded Number of Last Endpoint Activity bits (Represents the number of the BDT, updated by the last USB transfer.) 1111 = Endpoint 15 1110 = Endpoint 14 • • • 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = Last transaction was a transmit transfer (TX) 0 = Last transaction was a receive transfer (RX) PPBI: Ping-Pong BD Pointer Indicator bit 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank Unimplemented: Read as ‘0’ The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only valid when U1IR is active. Clearing the U1IR bit advances the FIFO. Data in register is invalid when U1IR = 0. bit 2 bit 1-0 Note 1: DS61168D-page 134 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER Bit Bit Bit Range 31/23/15/7 30/22/14/6 31:24 23:16 15:8 U-0 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-x — R-x — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 7:0 JSTATE SE0 PKTDIS(4) TOKBUSY(1,5) USBRST HOSTEN(2) RESUME(3) PPBRST USBEN(4) SOFEN(5) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 JSTATE: Live Differential Receiver JSTATE flag bit 1 = JSTATE detected on the USB 0 = No JSTATE detected SE0: Live Single-Ended Zero flag bit 1 = Single Ended Zero detected on the USB 0 = No Single Ended Zero detected PKTDIS: Packet Transfer Disable bit(4) 1 = Token and packet processing disabled (set upon SETUP token received) 0 = Token and packet processing enabled TOKBUSY: Token Busy Indicator bit(1,5) 1 = Token being executed by the USB module 0 = No token being executed USBRST: Module Reset bit(5) 1 = USB reset generated 0 = USB reset terminated HOSTEN: Host Mode Enable bit(2) 1 = USB host capability enabled 0 = USB host capability disabled RESUME: RESUME Signaling Enable bit(3) 1 = RESUME signaling activated 0 = RESUME signaling disabled Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: 2: 3: 4: 5: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 135 PIC32MX1XX/2XX REGISTER 10-11: U1CON: USB CONTROL REGISTER (CONTINUED) bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Even/Odd buffer pointers to the EVEN BD banks 0 = Even/Odd buffer pointers not being Reset USBEN: USB Module Enable bit(4) 1 = USB module and supporting circuitry enabled 0 = USB module and supporting circuitry disabled SOFEN: SOF Enable bit(5) 1 = SOF token sent every 1 ms 0 = SOF token disabled Software is required to check this bit before issuing another token command to the U1TOK register (see Register 10-15). All host control logic is reset any time that the value of this bit is toggled. Software must set RESUME for 10 ms if the part is a function, or for 25 ms if the part is a host, and then clear it to enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME signaling when this bit is cleared. Device mode. Host mode. bit 0 Note 1: 2: 3: 4: 5: DS61168D-page 136 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-12: U1ADDR: USB ADDRESS REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 LSPDEN DEVADDR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPDEN: Low Speed Enable Indicator bit 1 = Next token command to be executed at Low Speed 0 = Next token command to be executed at Full Speed DEVADDR: 7-bit USB Device Address bits bit 6-0 REGISTER 10-13: U1FRML: USB FRAME NUMBER LOW REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — R-0 — R-0 — R-0 — R-0 — R-0 — R-0 — R-0 FRML Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 FRML: The 11-bit Frame Number Lower bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 137 PIC32MX1XX/2XX REGISTER 10-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — R-0 — R-0 — — — — — FRMH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-3 Unimplemented: Read as ‘0’ bit 2-0 FRMH: The Upper 3 bits of the Frame Numbers bits The register bits are updated with the current frame number whenever a SOF TOKEN is received. REGISTER 10-15: U1TOK: USB TOKEN REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 PID(1) EP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-4 PID: Token Type Indicator bits(1) 0001 = OUT (TX) token type transaction 1001 = IN (RX) token type transaction 1101 = SETUP (TX) token type transaction Note: All other values are reserved and must not be used. EP: Token Command Endpoint Address bits The four bit value must specify a valid endpoint. All other values are reserved and must not be used. bit 3-0 Note 1: DS61168D-page 138 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-16: U1SOF: USB SOF THRESHOLD REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CNT Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 CNT: SOF Threshold Value bits Typical values of the threshold are: 01001010 = 64-byte packet 00101010 = 32-byte packet 00011010 = 16-byte packet 00010010 = 8-byte packet REGISTER 10-17: U1BDTP1: USB BDT PAGE 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — U-0 BDTPTRL — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-1 BDTPTRL: BDT Base Address bits This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. Unimplemented: Read as ‘0’ bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 139 PIC32MX1XX/2XX REGISTER 10-18: U1BDTP2: USB BDT PAGE 2 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 BDTPTRH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7-0 BDTPTRH: BDT Base Address bits This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. REGISTER 10-19: U1BDTP3: USB BDT PAGE 3 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 BDTPTRU Legend: R = Readable bit -n = Value at POR bit 31-8 bit 7-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ BDTPTRU: BDT Base Address bits This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location of the BDT in system memory. The 32-bit BDT base address is 512-byte aligned. DS61168D-page 140 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 10-20: U1CNFG1: USB CONFIGURATION 1 REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — R/W-0 UTEYE UOEMON — USBSIDL — — — UASUSPND Legend: R = Readable bit -n = Value at POR bit 31-8 bit 7 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ UTEYE: USB Eye-Pattern Test Enable bit 1 = Eye-Pattern Test enabled 0 = Eye-Pattern Test disabled UOEMON: USB OE Monitor Enable bit 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive Unimplemented: Read as ‘0’ USBSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as ‘0’ UASUSPND: Automatic Suspend Enable bit 1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit (U1PWRC) in Register 10-5. 0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the USUSPEND bit (U1PWRC) to suspend the module, including the USB 48 MHz clock bit 6 bit 5 bit 4 bit 3-1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 141 PIC32MX1XX/2XX REGISTER 10-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-8 Unimplemented: Read as ‘0’ bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled; hub required with PRE_PID RETRYDIS: Retry Disable bit (Host mode and U1EP0 only) 1 = Retry NAK’d transactions disabled 0 = Retry NAK’d transactions enabled; retry done in hardware Unimplemented: Read as ‘0’ EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN = 1 and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only TX and RX transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; TX and RX transfers also allowed Otherwise, this bit is ignored. EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint Handshake enabled 0 = Endpoint Handshake disabled (typically used for isochronous endpoints) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 DS61168D-page 142 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 11.0 I/O PORTS Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 12. “I/O Ports” (DS61120) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. General purpose I/O pins are the simplest of peripherals. They allow the PIC® MCU to monitor and control other devices. To add flexibility and functionality, some pins are multiplexed with alternate function(s). These functions depend on which peripheral features are on the device. In general, when a peripheral is functioning, that pin may not be used as a general purpose I/O pin. Following are some of the key features of this module: • Individual output pin open-drain enable/disable • Individual input pin weak pull-up and pull-down • Monitor selective inputs and generate interrupt when change in pin state is detected • Operation during CPU Sleep and Idle modes • Fast bit manipulation using CLR, SET and INV registers Figure 11-1 illustrates a block diagram of a typical multiplexed I/O port. FIGURE 11-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE Peripheral Module Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module RD ODC Data Bus SYSCLK WR ODC RD TRIS D Q ODC CK EN Q 1 0 D Q 1 0 Output Multiplexers D Q I/O Pin LAT CK EN Q 0 1 TRIS CK EN Q I/O Cell WR TRIS WR LAT WR PORT RD LAT 1 RD PORT 0 Sleep SYSCLK Synchronization Peripheral Input R Peripheral Input Buffer Q Q D CK Q Q D CK Legend: Note: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details. This block diagram is a general representation of a shared port/peripheral structure for illustration purposes only. The actual structure for any specific port/peripheral combination may be different than it is shown here. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 143 PIC32MX1XX/2XX 11.1 Parallel I/O (PIO) Ports 11.1.4 INPUT CHANGE NOTIFICATION All port pins have ten registers directly associated with their operation as digital I/O. The data direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a ‘1’, then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the latch (LATx) read the latch. Writes to the latch write the latch. Reads from the port (PORTx) read the port pins, while writes to the port pins write the latch. The input change notification function of the I/O ports allows the PIC32MX1XX/2XX devices to generate interrupt requests to the processor in response to a change-of-state on selected input pins. This feature can detect input change-of-states even in Sleep mode, when the clocks are disabled. Every I/O port pin can be selected (enabled) for generating an interrupt request on a change-of-state. Five control registers are associated with the CN functionality of each I/O port. The CNENx registers contain the CN interrupt enable control bits for each of the input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. The CNSTATx register indicates whether a change occurred on the corresponding pin since the last read of the PORTx bit. Each I/O pin also has a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source or sink source connected to the pin, and eliminate the need for external resistors when push-button or keypad devices are connected. The pull-ups and pull-downs are enabled separately using the CNPUx and the CNPDx registers, which contain the control bits for each of the pins. Setting any of the control bits enables the weak pull-ups and/or pull-downs for the corresponding pins. Note: Pull-ups and pull-downs on change notification pins should always be disabled when the port pin is configured as a digital output. 11.1.1 OPEN-DRAIN CONFIGURATION In addition to the PORTx, LATx, and TRISx registers for data control, some port pins can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired 5V-tolerant pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. See the “Pin Diagrams” section for the available pins and their functionality. 11.1.2 CONFIGURING ANALOG AND DIGITAL PORT PINS The ANSELx register controls the operation of the analog port pins. The port pins that are to function as analog inputs must have their corresponding ANSEL and TRIS bits set. In order to use port pins for I/O functionality with digital modules, such as Timers, UARTs, etc., the corresponding ANSELx bit must be cleared. The ANSELx register has a default value of 0xFFFF; therefore, all pins that share analog functions are analog (not digital) by default. If the TRIS bit is cleared (output) while the ANSELx bit is set, the digital output level (VOH or VOL) is converted by an analog peripheral, such as the ADC module or Comparator module. When the PORT register is read, all pins configured as analog input channels are read as cleared (a low level). Pins configured as digital inputs do not convert an analog input. Analog levels on any pin defined as a digital input (including the ANx pins) can cause the input buffer to consume current that exceeds the device specifications. An additional control register (CNCONx) is shown in Register 11-3. 11.2 CLR, SET and INV Registers Every I/O module register has a corresponding CLR (clear), SET (set) and INV (invert) register designed to provide fast atomic bit manipulations. As the name of the register implies, a value written to a SET, CLR or INV register effectively performs the implied operation, but only on the corresponding base register and only bits specified as ‘1’ are modified. Bits specified as ‘0’ are not modified. Reading SET, CLR and INV registers returns undefined values. To see the affects of a write operation to a SET, CLR or INV register, the base register must be read. 11.1.3 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically this instruction would be an NOP. DS61168D-page 144 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 11.3 Peripheral Pin Select A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. The challenge is even greater on low pin-count devices. In an application where more than one peripheral needs to be assigned to a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. Peripheral pin select configuration provides an alternative to these choices by enabling peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the device to their entire application, rather than trimming the application to fit the device. The peripheral pin select configuration feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of most digital peripherals to these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. When a remappable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Remappable peripherals never take priority over any analog functions associated with the pin. 11.3.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of SFRs: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral’s input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral-selectable pin is handled in two different ways, depending on whether an input or output is being mapped. 11.3.4 INPUT MAPPING 11.3.1 AVAILABLE PINS The number of available pins is dependent on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation “RPn” in their full pin designation, where “RP” designates a remappable peripheral and “n” is the remappable port number. The inputs of the peripheral pin select options are mapped on the basis of the peripheral. That is, a control register associated with a peripheral dictates the pin it will be mapped to. The [pin name]R registers, where [pin name] refers to the peripheral pins listed in Table 11-1, are used to configure peripheral input mapping (see Register 11-1). Each register contains sets of 4 bit fields. Programming these bit fields with an appropriate value maps the RPn pin with the corresponding value to that peripheral. For any given device, the valid range of values for any bit field is shown in Table 11-1. For example, Figure 11-2 illustrates the remappable pin selection for the U1RX input. 11.3.2 AVAILABLE PERIPHERALS FIGURE 11-2: The peripherals managed by the peripheral pin select are all digital-only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer-related peripherals (input capture and output compare) and interrupt-on-change inputs. In comparison, some digital-only peripheral modules are never included in the peripheral pin select feature. This is because the peripheral’s function requires special I/O circuitry on a specific port and cannot be easily connected to multiple pins. These modules include I2C among others. A similar requirement excludes all modules with analog inputs, such as the Analog-to-Digital Converter (ADC). A key difference between remappable and non-remappable peripherals is that remappable peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non-remappable peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. REMAPPABLE INPUT EXAMPLE FOR U1RX U1RXR 0 RPA2 1 RPB6 2 RPA4 U1RX input to peripheral n RPn Note: For input only, peripheral pin select functionality does not have priority over TRISx settings. Therefore, when configuring RPn pin for input, the corresponding bit in the TRISx register must also be configured for input (set to ‘1’). © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 145 PIC32MX1XX/2XX TABLE 11-1: INPUT PIN SELECTION [pin name]R SFR INT4R T2CKR IC4R SS1R REFCLKIR INT3R T3CKR IC3R U1CTSR U2RXR SDI1R INT2R T4CKR IC1R IC5R U1RXR U2CTSR SDI2R OCFBR INT1R T5CKR IC2R SS2R OCFAR [pin name]R bits INT4R T2CKR IC4R SS1R REFCLKIR INT3R T3CKR IC3R U1CTSR U2RXR SDI1R INT2R T4CKR IC1R IC5R U1RXR U2CTSR SDI2R OCFBR INT1R T5CKR IC2R SS2R OCFAR [pin name]R Value to RPn Pin Selection 0000 = RPA0 0001 = RPB3 0010 = RPB4 0011 = RPB15 0100 = RPB7 0101 = RPC7 0110 = RPC0 0111 = RPC5 1000 = Reserved • • • Peripheral Pin INT4 T2CK IC4 SS1 REFCLKI INT3 T3CK IC3 U1CTS U2RX SDI1 INT2 T4CK IC1 IC5 U1RX U2CTS SDI2 OCFB INT1 T5CK IC2 SS2 OCFA 1111 = Reserved 0000 = RPA1 0001 = RPB5 0010 = RPB1 0011 = RPB11 0100 = RPB8 0101 = RPA8 0110 = RPC8 0111 = RPA9 1000 = Reserved • • • 1111 = Reserved 0000 = RPA2 0001 = RPB6 0010 = RPA4 0011 = RPB13 0100 = RPB2 0101 = RPC6 0110 = RPC1 0111 = RPC3 1000 = Reserved • • • 1111 = Reserved 0000 = RPA3 0001 = RPB14 0010 = RPB0 0011 = RPB10 0100 = RPB9 0101 = RPC9 0110 = RPC2 0111 = RPC4 1000 = Reserved • • • 1111 = Reserved DS61168D-page 146 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 11.3.5 OUTPUT MAPPING 11.3.6.1 Control Register Lock In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPnR registers (Register 11-2) are used to control output mapping. Like the [pin name]R registers, each register contains sets of 4 bit fields. The value of the bit field corresponds to one of the peripherals, and that peripheral’s output is mapped to the pin (see Table 11-2 and Figure 11-3). A null output is associated with the output register reset value of ‘0’. This is done to ensure that remappable outputs remain disconnected from all output pins by default. Under normal operation, writes to the RPnR and [pin name]R registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK Configuration bit (CFGCON). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear the IOLOCK bit, an unlock sequence must be executed. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. 11.3.6.2 Configuration Bit Select Lock FIGURE 11-3: EXAMPLE OF MULTIPLEXING OF REMAPPABLE OUTPUT FOR RPA0 RPA0R Default U1TX Output U1RTS Output 0 1 2 Output Data RPA0 As an additional level of safety, the device can be configured to prevent more than one write session to the RPnR and [pin name]R registers. The IOL1WAY Configuration bit (DEVCFG3) blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. 14 15 11.3.6 CONTROLLING CONFIGURATION CHANGES Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to the peripheral map: • Control register lock sequence • Configuration bit select lock © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 147 PIC32MX1XX/2XX TABLE 11-2: OUTPUT PIN SELECTION RPnR SFR RPA0R RPB3R RPB4R RPB15R RPB7R RPC7R RPC0R RPC5R RPA1R RPB5R RPB1R RPB11R RPB8R RPA8R RPC8R RPA9R RPA2R RPB6R RPA4R RPB13R RPB2R RPC6R RPC1R RPC3R RPA3R RPB14R RPB0R RPB10R RPB9R RPC9R RPC2R RPC4R RPnR bits RPA0R RPB3R RPB4R RPB15R RPB7R RPC7R RPC0R RPC5R RPA1R RPB5R RPB1R RPB11R RPB8R RPA8R RPC8R RPA9R RPA2R RPB6R RPA4R RPB13R RPB2R RPC6R RPC1R RPC3R RPA3R RPB14R RPB0R RPB10R RPB9R RPC9R RPC2R RPC4R RPnR Value to Peripheral Selection 0000 = No Connect 0001 = U1TX 0010 = U2RTS 0011 = SS1 0100 = Reserved 0101 = OC1 0110 = Reserved 0111 = C2OUT 1000 = Reserved • • • RPn Port Pin RPA0 RPB3 RPB4 RPB15 RPB7 RPC7 RPC0 RPC5 RPA1 RPB5 RPB1 RPB11 RPB8 RPA8 RPC8 RPA9 RPA2 RPB6 RPA4 RPB13 RPB2 RPC6 RPC1 RPC3 RPA3 RPB14 RPB0 RPB10 RPB9 RPC9 RPC2 RPC4 1111 = Reserved 0000 = No Connect 0001 = Reserved 0010 = Reserved 0011 = SDO1 0100 = SDO2 0101 = OC2 0110 = Reserved • • • 1111 = Reserved 0000 = No Connect 0001 = Reserved 0010 = Reserved 0011 = SDO1 0100 = SDO2 0101 = OC4 0110 = OC5 0111 = REFCLKO 1000 = Reserved • • • 1111 = Reserved 0000 = No Connect 0001 = U1RTS 0010 = U2TX 0011 = Reserved 0100 = SS2 0101 = OC3 0110 = Reserved 0111 = C1OUT 1000 = Reserved • • • 1111 = Reserved DS61168D-page 148 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 11-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 [pin name]R: PERIPHERAL PIN SELECT INPUT REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — — — — [pin name]R Legend: R = Readable bit -n = Value at POR bit 31-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ [pin name]R: Peripheral Pin Select Input bits Where [pin name] refers to the pins that are used to configure peripheral input mapping. See Table 11-1 for input pin selection values. Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0. Note 1: REGISTER 11-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 RPnR: PERIPHERAL PIN SELECT OUTPUT REGISTER(1) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — — — — RPnR Legend: R = Readable bit -n = Value at POR bit 31-4 bit 3-0 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ RPnR: Peripheral Pin Select Output bits See Table 11-2 for output pin selection values. Register values can only be changed if the IOLOCK Configuration bit (CFGCON) = 0. Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 149 PIC32MX1XX/2XX REGISTER 11-3: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 CNCONx: CHANGE NOTICE CONTROL FOR PORTx REGISTER (x = A, B, C) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 ON U-0 — U-0 SIDL U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Change Notice (CN) Control ON bit 1 = CN is enabled 0 = CN is disabled Unimplemented: Read as ‘0’ SIDL: Stop in Idle Control bit 1 = CPU Idle Mode halts CN operation 0 = CPU Idle does not affect CN operation Unimplemented: Read as ‘0’ bit 14 bit 13 bit 12-0 DS61168D-page 150 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 12.0 TIMER1 Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS61105) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This family of PIC32 devices features one synchronous/asynchronous 16-bit timer that can operate as a free-running interval timer for various timing applications and counting external events. This timer can also be used with the Low-Power Secondary Oscillator (SOSC) for Real-Time Clock (RTC) applications. The following modes are supported: • • • • Synchronous Internal Timer Synchronous Internal Gated Timer Synchronous External Timer Asynchronous External Timer 12.1 Additional Supported Features • Selectable clock prescaler • Timer operation during CPU Idle and Sleep mode • Fast bit manipulation using CLR, SET and INV registers • Asynchronous mode can be used with the SOSC to function as a Real-Time Clock (RTC) FIGURE 12-1: TIMER1 BLOCK DIAGRAM(1) PR1 Equal 16-bit Comparator TSYNC 1 Sync Reset T1IF Event Flag 0 1 TGATE TMR1 0 Q Q D TGATE TCS ON SOSCO/T1CK SOSCEN SOSCI Gate Sync PBCLK x1 10 00 Prescaler 1, 8, 64, 256 2 TCKPS Note 1: The default state of the SOSCEN bit (OSCCON) during a device Reset is controlled by the FSOSCEN bit in Configuration Word, DEVCFG1. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 151 PIC32MX1XX/2XX REGISTER 12-1: Bit Range 31:24 23:16 15:8 7:0 T1CON: TYPE A TIMER CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — R/W-0 — R/W-0 — R-0 — U-0 — U-0 — U-0 ON(1) R/W-0 — U-0 SIDL R/W-0 TWDIS R/W-0 TWIP U-0 — R/W-0 — R/W-0 — U-0 TGATE — TCKPS — TSYNC TCS — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Timer On bit(1) 1 = Timer is enabled 0 = Timer is disabled Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode TWDIS: Asynchronous Timer Write Disable bit 1 = Writes to TMR1 are ignored until pending write operation completes 0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality) TWIP: Asynchronous Timer Write in Progress bit In Asynchronous Timer mode: 1 = Asynchronous write to TMR1 register in progress 0 = Asynchronous write to TMR1 register complete In Synchronous Timer mode: This bit is read as ‘0’. Unimplemented: Read as ‘0’ TGATE: Timer Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled Unimplemented: Read as ‘0’ TCKPS: Timer Input Clock Prescale Select bits 11 = 1:256 prescale value 10 = 1:64 prescale value 01 = 1:8 prescale value 00 = 1:1 prescale value When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14 bit 13 bit 12 bit 11 bit 10-8 bit 7 bit 6 bit 5-4 Note 1: DS61168D-page 152 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 12-1: bit 3 bit 2 T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED) Unimplemented: Read as ‘0’ TSYNC: Timer External Clock Input Synchronization Selection bit When TCS = 1: 1 = External clock input is synchronized 0 = External clock input is not synchronized When TCS = 0: This bit is ignored. TCS: Timer Clock Source Select bit 1 = External clock from TxCKI pin 0 = Internal peripheral clock Unimplemented: Read as ‘0’ When using 1:1 PBCmLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 1 bit 0 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 153 PIC32MX1XX/2XX NOTES: DS61168D-page 154 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 13.0 TIMER2/3, TIMER4/5 Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 14. “Timers” (DS61105) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This family of PIC32 devices features four synchronous 16-bit timers (default) that can operate as a freerunning interval timer for various timing applications and counting external events. The following modes are supported: • Synchronous internal 16-bit timer • Synchronous internal 16-bit gated timer • Synchronous external 16-bit timer Two 32-bit synchronous timers are available by combining Timer2 with Timer3 and Timer4 with Timer5. The 32-bit timers can operate in three modes: • Synchronous internal 32-bit timer • Synchronous internal 32-bit gated timer • Synchronous external 32-bit timer Note: In this chapter, references to registers, TxCON, TMRx and PRx, use ‘x’ to represent Timer2 through 5 in 16-bit modes. In 32-bit modes, ‘x’ represents Timer2 or 4; ‘y’ represents Timer3 or 5. 13.1 Additional Supported Features • Selectable clock prescaler • Timers operational during CPU idle • Time base for Input Capture and Output Compare modules (Timer2 and Timer3 only) • ADC event trigger (Timer3 only) • Fast bit manipulation using CLR, SET and INV registers FIGURE 13-1: TIMER2, 3, 4, 5 BLOCK DIAGRAM (16-BIT) TMRx Sync ADC Event Trigger(1) Equal Comparator x 16 PRx Reset TxIF Event Flag 0 1 TGATE Q Q D TGATE TCS ON TxCK Gate Sync PBCLK x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: ADC event trigger is available on Timer3 only. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 155 PIC32MX1XX/2XX FIGURE 13-2: TIMER2/3, 4/5 BLOCK DIAGRAM (32-BIT)(1) Reset TMRy TMRx LS Half Word Sync MS Half Word ADC Event Trigger(2) Equal 32-bit Comparator PRy TyIF Event Flag 0 1 TGATE PRx Q Q D TGATE TCS ON TxCK Gate Sync PBCLK x1 10 00 Prescaler 1, 2, 4, 8, 16, 32, 64, 256 3 TCKPS Note 1: 2: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5. ADC event trigger is available only on the Timer2/3 pair. DS61168D-page 156 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 13-1: Bit Range 31:24 23:16 15:8 7:0 TXCON: TYPE B TIMER CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 ON(1,3) R/W-0 — R/W-0 SIDL(4) R/W-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — U-0 TGATE(3) TCKPS(3) T32(2) — TCS(3) — Legend: R = Readable bit -n = Value at POR bit 31-16 bit 15 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Unimplemented: Read as ‘0’ ON: Timer On bit(1,3) 1 = Module is enabled 0 = Module is disabled Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit(4) 1 = Discontinue operation when device enters Idle mode 0 = Continue operation even in Idle mode Unimplemented: Read as ‘0’ TGATE: Timer Gated Time Accumulation Enable bit(3) When TCS = 1: This bit is ignored and is read as ‘0’. When TCS = 0: 1 = Gated time accumulation is enabled 0 = Gated time accumulation is disabled TCKPS: Timer Input Clock Prescale Select bits(3) 111 = 1:256 prescale value 110 = 1:64 prescale value 101 = 1:32 prescale value 100 = 1:16 prescale value 011 = 1:8 prescale value 010 = 1:4 prescale value 001 = 1:2 prescale value 000 = 1:1 prescale value When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. bit 14 bit 13 bit 12-8 bit 7 bit 6-4 Note 1: 2: 3: 4: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 157 PIC32MX1XX/2XX REGISTER 13-1: bit 3 TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED) T32: 32-Bit Timer Mode Select bit(2) 1 = Odd numbered and even numbered timers form a 32-bit timer 0 = Odd numbered and even numbered timers form a separate 16-bit timer Unimplemented: Read as ‘0’ TCS: Timer Clock Source Select bit(3) 1 = External clock from TxCK pin 0 = Internal peripheral clock Unimplemented: Read as ‘0’ When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit is available only on even numbered timers (Timer2 and Timer4). While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Timer5). All timer functions are set through the even numbered timers. While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer in Idle mode. bit 2 bit 1 bit 0 Note 1: 2: 3: 4: DS61168D-page 158 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 14.0 INPUT CAPTURE 1. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 15. “Input Capture” (DS61122) of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Input Capture module is useful in applications requiring frequency (period) and pulse measurement. The Input Capture module captures the 16-bit or 32-bit value of the selected Time Base registers when an event occurs at the ICx pin. The following events cause capture events: Simple capture event modes - Capture timer value on every falling edge of input at ICx pin - Capture timer value on every rising edge of input at ICx pin Capture timer value on every edge (rising and falling) Capture timer value on every edge (rising and falling), specified edge first. Prescaler capture event modes - Capture timer value on every 4th rising edge of input at ICx pin - Capture timer value on every 16th rising edge of input at ICx pin 2. 3. 4. Each input capture channel can select between one of two 16-bit timers (Timer2 or Timer3) for the time base, or two 16-bit timers (Timer2 and Timer3) together to form a 32-bit timer. The selected timer can use either an internal or external clock. Other operational features include: • Device wake-up from capture pin during CPU Sleep and Idle modes • Interrupt on input capture event • 4-word FIFO buffer for capture values Interrupt optionally generated after 1, 2, 3 or 4 buffer locations are filled • Input capture can also be used to provide additional sources of external interrupts FIGURE 14-1: INPUT CAPTURE BLOCK DIAGRAM FEDGE Specified/Every Edge Mode ICM 110 Prescaler Mode (16th Rising Edge) 101 TMR2 TMR3 C32/ICTMR Prescaler Mode (4th Rising Edge) 100 CaptureEvent To CPU FIFO CONTROL ICx pin Rising Edge Mode 011 ICxBUF Falling Edge Mode 010 FIFO ICI Edge Detection Mode 001 /N Sleep/Idle Wake-up Mode ICM Set Flag ICxIF (In IFSx Register) 001 111 Note: An ‘x’ in a signal, register or bit name denotes the number of the capture channel. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 159 PIC32MX1XX/2XX REGISTER 14-1: Bit Range 31:24 23:16 15:8 7:0 ICXCON: INPUT CAPTURE X CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit Bit Bit Bit 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 U-0 U-0 U-0 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) R/W-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 SIDL R/W-0 — R-0 — R-0 — R/W-0 FEDGE R/W-0 C32 R/W-0 ICTMR ICI ICOV ICBNE ICM Legend: R = Readable bit W = Writable bit U = Unimplemented bit P = Programmable bit r = Reserved bit -n = Bit Value at POR: (‘0’, ‘1’, x = unknown) bit 31-16 bit 15 Unimplemented: Read as ‘0’ ON: Input Capture Module Enable bit(1) 1 = Module enabled 0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications Unimplemented: Read as ‘0’ SIDL: Stop in Idle Control bit 1 = Halt in CPU Idle mode 0 = Continue to operate in CPU Idle mode Unimplemented: Read as ‘0’ FEDGE: First Capture Edge Select bit (only used in mode 6, ICM = 110) 1 = Capture rising edge first 0 = Capture falling edge first C32: 32-bit Capture Select bit 1 = 32-bit timer resource capture 0 = 16-bit timer resource capture ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON) is ‘1’) 0 = Timer3 is the counter source for capture 1 = Timer2 is the counter source for capture ICI: Interrupt Control bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event ICOV: Input Capture Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred ICBNE: Input Capture Buffer Not Empty Status bit (read-only) 1 = Input capture buffer is not empty; at least one more capture value can be read 0 = Input capture buffer is empty When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14 bit 13 bit 12-10 bit 9 bit 8 bit 7 bit 6-5 bit 4 bit 3 Note 1: DS61168D-page 160 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 14-1: bit 2-0 ICXCON: INPUT CAPTURE X CONTROL REGISTER (CONTINUED) ICM: Input Capture Mode Select bits 111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode) 110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter 101 = Prescaled Capture Event mode – every sixteenth rising edge 100 = Prescaled Capture Event mode – every fourth rising edge 011 = Simple Capture Event mode – every rising edge 010 = Simple Capture Event mode – every falling edge 001 = Edge Detect mode – every edge (rising and falling) 000 = Input Capture module is disabled When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 161 PIC32MX1XX/2XX NOTES: DS61168D-page 162 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 15.0 OUTPUT COMPARE Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 16. “Output Compare” (DS61111) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Output Compare module (OCMP) is used to generate a single pulse or a train of pulses in response to selected time base events. For all modes of operation, the OCMP module compares the values stored in the OCxR and/or the OCxRS registers to the value in the selected timer. When a match occurs, the OCMP module generates an event based on the selected mode of operation. The following are some of the key features: • Multiple Output Compare Modules in a device • Programmable interrupt generation on compare event • Single and Dual Compare modes • Single and continuous output pulse generation • Pulse-Width Modulation (PWM) mode • Hardware-based PWM Fault detection and automatic output disable • Programmable selection of 16-bit or 32-bit time bases • Can operate from either of two available 16-bit time bases or a single 32-bit time base FIGURE 15-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM Set Flag bit OCxIF(1) OCxRS(1) OCxR(1) Output Logic 3 OCM Mode Select S R Output Enable Q Output Enable Logic OCx(1) Comparator OCFA or OCFB(2) 0 1 OCTSEL 0 1 16 16 Timer2 Timer3 Timer2 Rollover Timer3 Rollover Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels, 1 through 5. 2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 163 PIC32MX1XX/2XX REGISTER 15-1: Bit Range 31:24 23:16 15:8 7:0 OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 SIDL R/W-0 — R-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — — OC32 OCFLT(2) OCTSEL OCM Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Output Compare Peripheral On bit(1) 1 = Output Compare peripheral is enabled 0 = Output Compare peripheral is disabled Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters Idle mode 0 = Continue operation in Idle mode Unimplemented: Read as ‘0’ OC32: 32-bit Compare Mode bit 1 = OCxR and/or OCxRS are used for comparisions to the 32-bit timer source 0 = OCxR and OCxRS are used for comparisons to the 16-bit timer source OCFLT: PWM Fault Condition Status bit(2) 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred OCTSEL: Output Compare Timer Select bit 1 = Timer3 is the clock source for this OCMP module 0 = Timer2 is the clock source for this OCMP module OCM: Output Compare Mode Select bits 111 = PWM mode on OCx; Fault pin enabled 110 = PWM mode on OCx; Fault pin disabled 101 = Initialize OCx pin low; generate continuous output pulses on OCx pin 100 = Initialize OCx pin low; generate single output pulse on OCx pin 011 = Compare event toggles OCx pin 010 = Initialize OCx pin high; compare event forces OCx pin low 001 = Initialize OCx pin low; compare event forces OCx pin high 000 = Output compare peripheral is disabled but continues to draw current When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit is only used when OCM = ‘111’. It is read as ‘0’ in all other modes. bit 14 bit 13 bit 12-6 bit 5 bit 4 bit 3 bit 2-0 Note 1: 2: DS61168D-page 164 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 16.0 SERIAL PERIPHERAL INTERFACE (SPI) The SPI module is a synchronous serial interface that is useful for communicating with external peripherals and other microcontroller devices. These peripheral devices may be Serial EEPROMs, Shift registers, display drivers, Analog-to-Digital Converters (ADC), etc. The PIC32 SPI module is compatible with Motorola® SPI and SIOP interfaces. Some of the key features of the SPI module are: • • • • • Master and Slave modes support Four different clock formats Enhanced Framed SPI protocol support User-configurable 8-bit, 16-bit and 32-bit data width Separate SPI FIFO buffers for receive and transmit - FIFO buffers act as 4/8/16-level deep FIFOs based on 32/16/8-bit data width • Programmable interrupt event on every 8-bit, 16-bit and 32-bit data transfer • Operation during CPU Sleep and Idle mode • Audio Codec Support: - I2S protocol - Left-justified - Right-justified - PCM Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 23. “Serial Peripheral Interface (SPI)” (DS61106) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 16-1: SPI MODULE BLOCK DIAGRAM Internal Data Bus SPIxBUF Read SPIxRXB FIFO Write SPIxTXB FIFO FIFOs Share Address SPIxBUF Transmit Receive SPIxSR SDIx SDOx Slave Select and Frame Sync Control bit 0 Shift Control Clock Control MCLKSEL Edge Select REFCLK Baud Rate Generator PBCLK MSTEN SSx/FSYNC SCKx Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 165 PIC32MX1XX/2XX REGISTER 16-1: Bit Range 31:24 23:16 15:8 7:0 SPIxCON: SPI CONTROL REGISTER Bit 30/22/14/6 R/W-0 Bit 31/23/15/7 R/W-0 Bit 29/21/13/5 R/W-0 Bit 28/20/12/4 R/W-0 Bit 27/19/11/3 R/W-0 Bit 26/18/10/2 R/W-0 U-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 R/W-0 FRMEN R/W-0 FRMSYNC U-0 FRMPOL U-0 MSSEN U-0 FRMSYPW U-0 FRMCNT R/W-0 MCLKSEL(2) R/W-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 SPIFE R/W-0 ENHBUF(2) R/W-0 ON(1) R/W-0 — R/W-0 SIDL R/W-0 DISSDO R/W-0 MODE32 R/W-0 MODE16 R/W-0 SMP R/W-0 CKE(3) R/W-0 SSEN CKP MSTEN DISSDI STXISEL SRXISEL Legend: R = Readable bit -n = Value at POR bit 31 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown FRMEN: Framed SPI Support bit 1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output) 0 = Framed SPI support is disabled bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (Framed SPI mode only) 1 = Frame sync pulse input (Slave mode) 0 = Frame sync pulse output (Master mode) bit 29 FRMPOL: Frame Sync Polarity bit (Framed SPI mode only) 1 = Frame pulse is active-high 0 = Frame pulse is active-low bit 28 MSSEN: Master Mode Slave Select Enable bit 1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in Master mode. Polarity is determined by the FRMPOL bit. 0 = Slave select SPI support is disabled. bit 27 FRMSYPW: Frame Sync Pulse Width bit 1 = Frame sync pulse is one character wide 0 = Frame sync pulse is one clock wide bit 26-24 FRMCNT: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per pulse. This bit is only valid in FRAMED_SYNC mode. 111 = Reserved; do not use 110 = Reserved; do not use 101 = Generate a frame sync pulse on every 32 data characters 100 = Generate a frame sync pulse on every 16 data characters 011 = Generate a frame sync pulse on every 8 data characters 010 = Generate a frame sync pulse on every 4 data characters 001 = Generate a frame sync pulse on every 2 data characters 000 = Generate a frame sync pulse on every data character bit 23 MCLKSEL: Master Clock Enable bit(2) 1 = REFCLK is used by the Baud Rate Generator 0 = PBCLK is used by the Baud Rate Generator bit 22-18 Unimplemented: Read as ‘0’ bit 17 SPIFE: Frame Sync Pulse Edge Select bit (Framed SPI mode only) 1 = Frame synchronization pulse coincides with the first bit clock 0 = Frame synchronization pulse precedes the first bit clock Note 1: 2: 3: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). DS61168D-page 166 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-1: bit 16 SPIxCON: SPI CONTROL REGISTER (CONTINUED) ENHBUF: Enhanced Buffer Enable bit(2) 1 = Enhanced Buffer mode is enabled 0 = Enhanced Buffer mode is disabled bit 15 ON: SPI Peripheral On bit(1) 1 = SPI Peripheral is enabled 0 = SPI Peripheral is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in Idle Mode bit 1 = Discontinue operation when CPU enters in Idle mode 0 = Continue operation in Idle mode bit 12 DISSDO: Disable SDOx pin bit 1 = SDOx pin is not used by the module. Pin is controlled by associated PORT register 0 = SDOx pin is controlled by the module bit 11-10 MODE: 32/16-Bit Communication Select bits When AUDEN = 1: MODE32 MODE16 Communication 1 1 24-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 1 0 32-bit Data, 32-bit FIFO, 32-bit Channel/64-bit Frame 0 1 16-bit Data, 16-bit FIFO, 32-bit Channel/64-bit Frame 0 0 16-bit Data, 16-bit FIFO, 16-bit Channel/32-bit Frame When AUDEN = 0: MODE32 MODE16 Communication 1 x 32-bit 0 1 16-bit 0 0 8-bit SMP: SPI Data Input Sample Phase bit Master mode (MSTEN = 1): 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode (MSTEN = 0): SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0. CKE: SPI Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit) 0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit) SSEN: Slave Select Enable (Slave mode) bit 1 = SSx pin used for Slave mode 0 = SSx pin not used for Slave mode, pin controlled by port function. CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode DISSDI: Disable SDI bit 1 = SDI pin is not used by the SPI module (pin is controlled by PORT function) 0 = SDI pin is controlled by the SPI module When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 Note 1: 2: 3: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 167 PIC32MX1XX/2XX REGISTER 16-1: bit 3-2 SPIxCON: SPI CONTROL REGISTER (CONTINUED) bit 1-0 STXISEL: SPI Transmit Buffer Empty Interrupt Mode bits 11 = Interrupt is generated when the buffer is not full (has one or more empty elements) 10 = Interrupt is generated when the buffer is empty by one-half or more 01 = Interrupt is generated when the buffer is completely empty 00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are complete SRXISEL: SPI Receive Buffer Full Interrupt Mode bits 11 = Interrupt is generated when the buffer is full 10 = Interrupt is generated when the buffer is full by one-half or more 01 = Interrupt is generated when the buffer is not empty 00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty) When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. This bit can only be written when the ON bit = 0. This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI mode (FRMEN = 1). Note 1: 2: 3: DS61168D-page 168 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-2: Bit Range 31:24 23:16 15:8 7:0 SPIxCON2: SPI CONTROL REGISTER 2 Bit Bit 30/22/14/6 29/21/13/5 U-0 U-0 Bit 31/23/15/7 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit Bit Bit 26/18/10/2 25/17/9/1 24/16/8/0 U-0 U-0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 U-0 — R/W-0 R/W-0 — R/W-0 SPISGNEXT R/W-0 — U-0 — U-0 FRMERREN U-0 SPIROVEN R/W-0 SPITUREN IGNROV — IGNTUR R/W-0 AUDEN(1) — — — AUDMONO(1,2) AUDMOD(1,2) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 SPISGNEXT: Sign Extend Read Data from the RX FIFO bit 1 = Data from RX FIFO is sign extended 0 = Data from RX FIFO is not sign extened bit 14-13 Unimplemented: Read as ‘0’ bit 12 FRMERREN: Enable Interrupt Events via FRMERR bit 1 = Frame Error overflow generates error events 0 = Frame Error does not generate error events bit 11 SPIROVEN: Enable Interrupt Events via SPIROV bit 1 = Receive overflow generates error events 0 = Receive overflow does not generate error events bit 10 SPITUREN: Enable Interrupt Events via SPITUR bit 1 = Transmit Underrun Generates Error Events 0 = Transmit Underrun Does Not Generates Error Events bit 9 IGNROV: Ignore Receive Overflow bit (for Audio Data Transmissions) 1 = A ROV is not a critical error; during ROV data in the fifo is not overwritten by receive data 0 = A ROV is a critical error which stop SPI operation bit 8 IGNTUR: Ignore Transmit Underrun bit (for Audio Data Transmissions) 1 = A TUR is not a critical error and zeros are transmitted until the SPIxTXB is not empty 0 = A TUR is a critical error which stop SPI operation bit 7 AUDEN: Enable Audio CODEC Support bit(1) 1 = Audio protocol enabled 0 = Audio protocol disabled bit 6-5 Unimplemented: Read as ‘0’ bit 3 AUDMONO: Transmit Audio Data Format bit(1,2) 1 = Audio data is mono (Each data word is transmitted on both left and right channels) 0 = Audio data is stereo bit 2 Unimplemented: Read as ‘0’ bit 1-0 AUDMOD: Audio Protocol Mode bit(1,2) 11 = PCM/DSP mode 10 = Right Justified mode 01 = Left Justified mode 00 = I2S mode Note 1: 2: This bit can only be written when the ON bit = 0. This bit is only valid for AUDEN = 1. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 169 PIC32MX1XX/2XX REGISTER 16-3: Bit Range 31:24 23:16 15:8 7:0 SPIxSTAT: SPI STATUS REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 R-0 Bit 27/19/11/3 R-0 Bit 26/18/10/2 R-0 Bit 25/17/9/1 R-0 Bit 24/16/8/0 R-0 — U-0 — U-0 — U-0 R-0 R-0 RXBUFELM R-0 R-0 R-0 — U-0 — U-0 — U-0 R/C-0, HS R-0 TXBUFELM U-0 U-0 R-0 — R-0 — R/W-0 — R-0 FRMERR U-0 SPIBUSY R-1 — U-0 — R-0 SPITUR R-0 SRMT SPIROV SPIRBE C = Clearable bit W = Writable bit ‘1’ = Bit is set — SPITBE — SPITBF SPIRBF Legend: R = Readable bit -n = Value at POR HS = Set in hardware U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-29 Unimplemented: Read as ‘0’ bit 28-24 RXBUFELM: Receive Buffer Element Count bits (valid only when ENHBUF = 1) bit 23-21 Unimplemented: Read as ‘0’ bit 20-16 TXBUFELM: Transmit Buffer Element Count bits (valid only when ENHBUF = 1) bit 15-13 Unimplemented: Read as ‘0’ bit 12 FRMERR: SPI Frame Error status bit 1 = Frame error detected 0 = No Frame error detected This bit is only valid when FRMEN = 1. SPIBUSY: SPI Activity Status bit 1 = SPI peripheral is currently busy with some transactions 0 = SPI peripheral is currently idle Unimplemented: Read as ‘0’ SPITUR: Transmit Under Run bit 1 = Transmit buffer has encountered an underrun condition 0 = Transmit buffer has no underrun condition This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling the module. SRMT: Shift Register Empty bit (valid only when ENHBUF = 1) 1 = When SPI module shift register is empty 0 = When SPI module shift register is not empty SPIROV: Receive Overflow Flag bit 1 = A new data is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred This bit is set in hardware; can only be cleared (= 0) in software. SPIRBE: RX FIFO Empty bit (valid only when ENHBUF = 1) 1 = RX FIFO is empty (CRPTR = SWPTR) 0 = RX FIFO is not empty (CRPTR ≠ SWPTR) Unimplemented: Read as ‘0’ bit 11 bit 10-9 bit 8 bit 7 bit 6 bit 5 bit 4 DS61168D-page 170 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 16-3: bit 3 SPIxSTAT: SPI STATUS REGISTER SPITBE: SPI Transmit Buffer Empty Status bit 1 = Transmit buffer, SPIxTXB is empty 0 = Transmit buffer, SPIxTXB is not empty Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR. Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB. Unimplemented: Read as ‘0’ SPITBF: SPI Transmit Buffer Full Status bit 1 = Transmit not yet started, SPITXB is full 0 = Transmit buffer is not full Standard Buffer Mode: Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB. Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR. Enhanced Buffer Mode: Set when CWPTR + 1 = SRPTR; cleared otherwise SPIRBF: SPI Receive Buffer Full Status bit 1 = Receive buffer, SPIxRXB is full 0 = Receive buffer, SPIxRXB is not full Standard Buffer Mode: Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB. Enhanced Buffer Mode: Set when SWPTR + 1 = CRPTR; cleared otherwise bit 2 bit 1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 171 PIC32MX1XX/2XX NOTES: DS61168D-page 172 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 17.0 INTER-INTEGRATED CIRCUIT™ (I2C™) The I2C module provides complete hardware support for both Slave and Multi-Master modes of the I2C serial communication standard. Figure 17-1 illustrates the I2C module block diagram. Each I2C module has a 2-pin interface: the SCLx pin is clock and the SDAx pin is data. Each I2C module offers the following key features: • I2C interface supporting both master and slave operation • I2C Slave mode supports 7-bit and 10-bit addressing • I2C Master mode supports 7-bit and 10-bit addressing • I2C port allows bidirectional transfers between master and slaves • Serial clock synchronization for the I2C port can be used as a handshake mechanism to suspend and resume serial transfer (SCLREL control) • I2C supports multi-master operation; detects bus collision and arbitrates accordingly • Provides support for address bit masking Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 24. “InterIntegrated Circuit™ (I2C™)” (DS61116) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 173 PIC32MX1XX/2XX FIGURE 17-1: I2C™ BLOCK DIAGRAM Internal Data Bus I2CxRCV Shift Clock I2CxRSR LSB SDAx Address Match Read SCLx Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Start and Stop Bit Generation Control Logic Write I2CxSTAT Read Write I2CxCON Read Collision Detect Acknowledge Generation Clock Stretching Write I2CxTRN LSB Shift Clock Reload Control Read Write I2CxBRG Read BRG Down Counter PBCLK DS61168D-page 174 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 17-1: Bit Range 31:24 23:16 15:8 7:0 I2CXCON: I2C™ CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) R/W-0 — U-0 — R/W-0 — R/W-1, HC — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 SIDL R/W-0 SCLREL R/W-0, HC STRICT R/W-0, HC A10M R/W-0, HC DISSLW R/W-0, HC SMEN R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN Legend: R = Readable bit -n = Value at POR HC = Cleared in Hardware W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: I2C Enable bit(1) 1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins 0 = Disables the I2C module; all I2C pins are controlled by PORT functions Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode SCLREL: SCLx Release Control bit (when operating as I2C slave) 1 = Release SCLx clock 0 = Hold SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software can only write ‘1’ to release clock). Hardware clear at beginning of slave transmission. bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit 1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate addresses in reserved address space. 0 = Strict I2C Reserved Address Rule not enabled A10M: 10-bit Slave Address bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled SMEN: SMBus Input Levels bit 1 = Enable I/O pin thresholds compliant with SMBus specification 0 = Disable SMBus input thresholds When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14 bit 13 bit 12 bit 10 bit 9 bit 8 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 175 PIC32MX1XX/2XX REGISTER 17-1: bit 7 I2CXCON: I2C™ CONTROL REGISTER (CONTINUED) GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enable interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enable software or receive clock stretching 0 = Disable software or receive clock stretching ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive) Value that is transmitted when the software initiates an Acknowledge sequence. 1 = Send NACK during Acknowledge 0 = Send ACK during Acknowledge ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master receive) 1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receive sequence not in progress PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress RSEN: Repeated Start Condition Enable bit (when operating as I2C master) 1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress SEN: Start Condition Enable bit (when operating as I2C master) 1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: DS61168D-page 176 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 17-2: Bit Range 31:24 23:16 15:8 7:0 I2CXSTAT: I2C™ STATUS REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0, HSC — R-0, HSC — U-0 — U-0 — U-0 — R/C-0, HS — R-0, HSC — R-0, HSC ACKSTAT R/C-0, HS TRSTAT R/C-0, HS — R-0, HSC — R/C-0, HSC — R/C-0, HSC BCL R-0, HSC GCSTAT R-0, HSC ADD10 R-0, HSC IWCOL I2COV D_A P S R_W RBF TBF Legend: R = Readable bit -n = Value at POR HS = Set in hardware W = Writable bit ‘1’ = Bit is set HSC = Hardware set/cleared U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared C = Clearable bit bit 31-16 Unimplemented: Read as ‘0’ bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C™ master, applicable to master transmit operation) 1 = NACK received from slave 0 = ACK received from slave Hardware set or clear at end of slave Acknowledge. TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. ADD10: 10-bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). D_A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by reception of slave byte. bit 14 bit 13-11 Unimplemented: Read as ‘0’ bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 177 PIC32MX1XX/2XX REGISTER 17-2: bit 4 I2CXSTAT: I2C™ STATUS REGISTER (CONTINUED) P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. R_W: Read/Write Information bit (when operating as I2C slave) 1 = Read – indicates data transfer is output from slave 0 = Write – indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. bit 3 bit 2 bit 1 bit 0 DS61168D-page 178 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 18.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) The primary features of the UART module are: • • • • • • • • • • • • • Full-duplex, 8-bit or 9-bit data transmission Even, Odd or No Parity options (for 8-bit data) One or two Stop bits Hardware auto-baud feature Hardware flow control option Fully integrated Baud Rate Generator (BRG) with 16-bit prescaler Baud rates ranging from 38 bps to 10 Mbps at 40 MHz 8-level deep First-In-First-Out (FIFO) transmit data buffer 8-level deep FIFO receive data buffer Parity, framing and buffer overrun error detection Support for interrupt-only on address detect (9th bit = 1) Separate transmit and receive interrupts Loopback mode for diagnostic support Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The UART module is one of the serial I/O modules available in PIC32MX1XX/2XX family devices. The UART is a full-duplex, asynchronous communication channel that communicates with peripheral devices and personal computers through protocols, such as RS-232, RS-485, LIN and IrDA®. The module also supports the hardware flow control option, with UxCTS and UxRTS pins, and also includes an IrDA encoder and decoder. • LIN Protocol support • IrDA encoder and decoder with 16x baud clock output for external IrDA encoder/decoder support Figure 18-1 illustrates a simplified block diagram of the UART. FIGURE 18-1: UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA® Hardware Flow Control UxRTS/BCLKx UxCTS UARTx Receiver UxRX UARTx Transmitter UxTX Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 179 PIC32MX1XX/2XX REGISTER 18-1: Bit Range 31:24 23:16 15:8 7:0 UxMODE: UARTx MODE REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) R/W-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — R/W-0 — R/W-0 SIDL R/W-0 IREN R/W-0 RTSMD R/W-0 — R/W-0 UEN R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL STSEL Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: UARTx Enable bit(1) 1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN and UTXEN control bits 0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx registers; UARTx power consumption is minimal Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue operation when device enters Idle mode 0 = Continue operation in Idle mode IREN: IrDA Encoder and Decoder Enable bit 1 = IrDA is enabled 0 = IrDA is disabled RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin is in Simplex mode 0 = UxRTS pin is in Flow Control mode Unimplemented: Read as ‘0’ UEN: UARTx Enable bits 11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits in the PORTx register 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by corresponding bits in the PORTx register WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit 1 = Wake-up enabled 0 = Wake-up disabled LPBACK: UARTx Loopback Mode Select bit 1 = Loopback mode is enabled 0 = Loopback mode is disabled When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14 bit 13 bit 12 bit 11 bit 10 bit 9-8 bit 7 bit 6 Note 1: DS61168D-page 180 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 18-1: bit 5 UxMODE: UARTx MODE REGISTER (CONTINUED) ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55); cleared by hardware upon completion 0 = Baud rate measurement disabled or completed RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is ‘0’ 0 = UxRX Idle state is ‘1’ BRGH: High Baud Rate Enable bit 1 = High-Speed mode – 4x baud clock enabled 0 = Standard Speed mode – 16x baud clock enabled PDSEL: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity STSEL: Stop Selection bit 1 = 2 Stop bits 0 = 1 Stop bit When using 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 4 bit 3 bit 2-1 bit 0 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 181 PIC32MX1XX/2XX REGISTER 18-2: Bit Range 31:24 23:16 15:8 7:0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown UxSTA: UARTx STATUS AND CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 ADM_EN R/W-0 ADDR R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-1 UTXISEL R/W-0 R/W-0 UTXINV R/W-0 URXEN R-1 UTXBRK R-0 UTXEN R-0 UTXBF R/W-0 TRMT R-0 URXISEL ADDEN RIDLE PERR FERR OERR URXDA bit 31-25 Unimplemented: Read as ‘0’ bit 24 ADM_EN: Automatic Address Detect Mode Enable bit 1 = Automatic Address Detect mode is enabled 0 = Automatic Address Detect mode is disabled bit 23-16 ADDR: Automatic Address Mask bits When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address detection. bit 15-14 UTXISEL: TX Interrupt Mode Selection bits 11 = Reserved, do not use 10 = Interrupt is generated and asserted while the transmit buffer is empty 01 = Interrupt is generated and asserted when all characters have been transmitted 00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space bit 13 UTXINV: Transmit Polarity Inversion bit If IrDA mode is disabled (i.e., IREN (UxMODE) is ‘0’): 1 = UxTX Idle state is ‘0’ 0 = UxTX Idle state is ‘1’ If IrDA mode is enabled (i.e., IREN (UxMODE) is ‘1’): 1 = IrDA encoded UxTX Idle state is ‘1’ 0 = IrDA encoded UxTX Idle state is ‘0’ bit 12 URXEN: Receiver Enable bit 1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1) 0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port. UTXBRK: Transmit Break bit 1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by hardware upon completion 0 = Break transmission is disabled or completed UTXEN: Transmit Enable bit 1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1) 0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is controlled by port. UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written TRMT: Transmit Shift Register is Empty bit (read-only) 1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer bit 11 bit 10 bit 9 bit 8 DS61168D-page 182 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 18-2: bit 7-6 UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) URXISEL: Receive Interrupt Mode Selection bit 11 = Reserved; do not use 10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (i.e., has 6 or more data characters) 01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (i.e., has 4 or more data characters) 00 = Interrupt flag bit is asserted while receive buffer is not empty (i.e., has at least 1 data character) ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect 0 = Address Detect mode is disabled RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Data is being received PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character 0 = Parity error has not been detected FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character 0 = Framing error has not been detected OERR: Receive Buffer Overrun Error Status bit. This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit resets the receiver buffer and RSR to empty state. 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 183 PIC32MX1XX/2XX Figure 18-2 and Figure 18-3 illustrate typical receive and transmit timing for the UART module. FIGURE 18-2: UART RECEPTION Char 1 Char 2-4 Char 5-10 Char 11-13 Read to UxRXREG Start 1 UxRX Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13 RIDLE Cleared by Software OERR Cleared by Software UxRXIF URXISEL = 00 Cleared by Software UxRXIF URXISEL = 01 UxRXIF URXISEL = 10 FIGURE 18-3: TRANSMISSION (8-BIT OR 9-BIT DATA) 8 into TxBUF Write to UxTXREG TSR BCLK/16 (Shift Clock) UxTX Start Bit 0 Bit 1 Pull from Buffer Stop Start Bit 1 UxTXIF UTXISEL = 00 UxTXIF UTXISEL = 01 UxTXIF UTXISEL = 10 DS61168D-page 184 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 19.0 PARALLEL MASTER PORT (PMP) Key features of the PMP module include: • Fully multiplexed address/data mode • Demultiplexed or partially multiplexed address/ data mode - up to 11 address lines with single chip select - up to 12 address lines without chip select • One Chip Select Line • Programmable Strobe Options - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe • Address Auto-Increment/Auto-Decrement • Programmable Address/Data Multiplexing • Programmable Polarity on Control Signals • Legacy Parallel Slave Port Support • Enhanced Parallel Slave Support - Address Support - 4-Byte Deep Auto-Incrementing Buffer • Programmable Wait States • Selectable Input Voltage Levels Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 13. “Parallel Master Port (PMP)” (DS61128) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PMP is a parallel 8-bit input/output module specifically designed to communicate with a wide variety of parallel devices, such as communications peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP module is highly configurable. FIGURE 19-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES Address Bus Data Bus Control Lines PMA PMALL PMA PMALH PMA PMA PMCS1 PIC32MX1XX/2XX Parallel Master Port Up to 12-bit Address Flash EEPROM SRAM PMRD PMRD/PMWR PMWR PMENB Microcontroller LCD FIFO Buffer PMD 8-bit Data (with or without multiplexed addressing) © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 185 PIC32MX1XX/2XX REGISTER 19-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 PMCON: PARALLEL PORT CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) R/W-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 SIDL R/W-0 ADRMUX U-0 R/W-0 PMPTTL U-0 PTWREN R/W-0 PTRDEN R/W-0 CSF(2) ALP(2) — CS1P(2) — WRSP RDSP Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Parallel Master Port Enable bit(1) 1 = PMP enabled 0 = PMP disabled, no off-chip access performed Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 14 bit 13 bit 12-11 ADRMUX: Address/Data Multiplexing Selection bits 11 = Lower 8 bits of address are multiplexed on PMD pins; upper 8 bits are not used 10 = All 16 bits of address are multiplexed on PMD pins 01 = Lower 8 bits of address are multiplexed on PMD pins, upper bits are on PMA and PMA 00 = Address and data appear on separate pins bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module uses TTL input buffers 0 = PMP module uses Schmitt Trigger input buffer PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled CSF: Chip Select Function bits(2) 11 = Reserved 10 = PMCS1 function as Chip Select 01 = PMCS1 functions as address bit 14 00 = PMCS1 function as address bit 14 ALP: Address Latch Polarity bit(2) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 9 bit 8 bit 7-6 bit 5 Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. DS61168D-page 186 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 19-1: bit 4 bit 3 PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) Unimplemented: Read as ‘0’ CS1P: Chip Select 0 Polarity bit(2) 1 = Active-high (PMCS1) 0 = Active-low (PMCS1) Unimplemented: Read as ‘0’ WRSP: Write Strobe Polarity bit For Slave Modes and Master mode 2 (PMMODE = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 2 bit 1 bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE = 00,01,10): 1 = Read Strobe active-high (PMRD) 0 = Read Strobe active-low (PMRD) For Master mode 1 (PMMODE = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON control bit. 2: These bits have no effect when their corresponding pins are used as address lines. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 187 PIC32MX1XX/2XX REGISTER 19-2: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 PMMODE: PARALLEL PORT MODE REGISTER Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — U-0 — R/W-0 — R/W-0 BUSY R/W-0 IRQM R/W-0 R/W-0 INCM R/W-0 R/W-0 — R/W-0 MODE R/W-0 R/W-0 WAITB(1) WAITM(1) WAITE(1) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy 0 = Port is not busy bit 14-13 IRQM: Interrupt Request Mode bits 11 = Reserved, do not use 10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA =11 (Addressable Slave mode only) 01 = Interrupt generated at the end of the read/write cycle 00 = No Interrupt generated bit 12-11 INCM: Increment Mode bits 11 = Slave mode read and write buffers auto-increment (PMMODE = 00 only) 10 = Decrement ADDR and ADDR by 1 every read/write cycle(2) 01 = Increment ADDR and ADDR by 1 every read/write cycle(2) 00 = No increment or decrement of address bit 10 bit 9-8 Unimplemented: Read as ‘0’ MODE: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMA, and PMD) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMA, and PMD) 01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD, and PMA) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD) WAITB: Data Setup to Read/Write Strobe Wait States bits(1) 11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB 10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB 01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB 00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default) bit 7-6 Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. DS61168D-page 188 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 19-2: bit 5-2 PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED) WAITM: Data Read/Write Strobe Wait States bits(1) 1111 = Wait of 16 TPB • • • 0001 = Wait of 2 TPB 0000 = Wait of 1 TPB (default) WAITE: Data Hold After Read/Write Strobe Wait States bits(1) 11 = Wait of 4 TPB 10 = Wait of 3 TPB 01 = Wait of 2 TPB 00 = Wait of 1 TPB (default) For Read operations: 11 = Wait of 3 TPB 10 = Wait of 2 TPB 01 = Wait of 1 TPB 00 = Wait of 0 TPB (default) bit 1-0 Note 1: Whenever WAITM = 0000, WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation. 2: Address bit A14 is not subject to auto-increment/decrement if configured as Chip Select CS1. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 189 PIC32MX1XX/2XX REGISTER 19-3: Bit Range 31:24 23:16 15:8 7:0 PMADDR: PARALLEL PORT ADDRESS REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CS1 R/W-0 — R/W-0 — R/W-0 — R/W-0 R/W-0 ADDR R/W-0 R/W-0 ADDR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 14 CS1: Chip Select 1 bit 1 = Chip Select 1 is active 0 = Chip Select 1 is inactive (pin functions as PMA) ADDR: Destination Address bits bit 13-11 Unimplemented: Read as ‘0’ bit 10-0 DS61168D-page 190 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 19-4: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 PMAEN: PARALLEL PORT PIN ENABLE REGISTER(1,2) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 PTEN14 R/W-0 — R/W-0 — R/W-0 — R/W-0 R/W-0 PTEN R/W-0 R/W-0 PTEN Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-15 Unimplemented: Read as ‘0’ bit 15-14 PTEN14: PMCS1 Strobe Enable bits 1 = PMA14 functions as either PMA14 or PMCS1(1) 0 = PMA14 functions as port I/O bit 13-11 Unimplemented: Read as ‘0’ bit 10-2 PTEN: PMP Address Port Enable bits 1 = PMA function as PMP address lines 0 = PMA function as port I/O PTEN: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA or PMALH and PMALL(2) 0 = PMA1 and PMA0 pads functions as port I/O bit 1-0 Note 1: The use of this pin as PMA14 or CS1 is selected by the CSF bits in the PMCON register. 2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode selected by bits ADRMUX in the PMCON register. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 191 PIC32MX1XX/2XX REGISTER 19-5: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 U-0 PMSTAT: PARALLEL PORT STATUS REGISTER (SLAVE MODES ONLY) Bit 30/22/14/6 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-0 — R/W-0, HSC — U-0 — U-0 — R-0 — R-0 — R-0 — R-0 IBF R-1 IBOV R/W-0, HSC — U-0 — U-0 IB3F R-1 IB2F R-1 IB1F R-1 IB0F R-1 OBE OBUF — — OB3E OB2E OB1E OB0E Legend: R = Readable bit -n = Value at POR HSC = Set by Hardware; Cleared by Software W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte buffer occurred (must be cleared in software) 0 = No overflow occurred IBxF: Input Buffer x Status Full bits 1 = Input Buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input Buffer does not contain any unread data OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full OBUF: Output Buffer Underflow Status bit 1 = A read occurred from an empty output byte buffer (must be cleared in software) 0 = No underflow occurred Unimplemented: Read as ‘0’ OBxE: Output Buffer x Status Empty bits 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted bit 14 bit 13-12 Unimplemented: Read as ‘0’ bit 11-8 bit 7 bit 6 bit 5-4 bit 3-0 DS61168D-page 192 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 20.0 REAL-TIME CLOCK AND CALENDAR (RTCC) Following are some of the key features of this module: • • • • • Time: hours, minutes and seconds 24-hour format (military time) Visibility of one-half second period Provides calendar: Weekday, date, month and year Alarm intervals are configurable for half of a second, one second, 10 seconds, one minute, 10 minutes, one hour, one day, one week, one month and one year Alarm repeat with decrementing counter Alarm with indefinite repeat: Chime Year range: 2000 to 2099 Leap year correction BCD format for smaller firmware overhead Optimized for long-term battery operation Fractional second synchronization User calibration of the clock crystal frequency with auto-adjust Calibration range: ±0.66 seconds error per month Calibrates up to 260 ppm of crystal error Requirements: External 32.768 kHz clock crystal Alarm pulse or seconds clock output on RTCC pin Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC32 RTCC module is intended for applications in which accurate time must be maintained for extended periods of time with minimal or no CPU intervention. Low-power optimization provides extended battery lifetime while keeping track of time. • • • • • • • • • • • • FIGURE 20-1: RTCC BLOCK DIAGRAM CAL 32.768 kHz Input from Secondary Oscillator (SOSC) RTCC Prescalers 0.5s RTCC Timer Alarm Event RTCVAL RTCTIME HR, MIN, SEC RTCDATE YEAR, MONTH, DAY, WDAY Comparator Compare Registers with Masks Repeat Counter ALRMTIME HR, MIN, SEC ALRMVAL ALRMDATE MONTH, DAY, WDAY Set RTCC Flag RTCC Interrupt Logic Alarm Pulse Seconds Pulse 0 1 RTCC RTSECSEL RTCOE © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 193 PIC32MX1XX/2XX REGISTER 20-1: Bit Range 31:24 23:16 15:8 7:0 RTCCON: RTC CONTROL REGISTER(1) Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit Bit 29/21/13/5 28/20/12/4 U-0 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CAL R/W-0 R/W-0 CAL R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 ON(2,3) R/W-0 — R-0 SIDL U-0 — U-0 — R/W-0 — R-0 — R-0 — R/W-0 RTSECSEL(4) RTCCLKON — — RTCWREN(5) RTCSYNC HALFSEC(6) RTCOE Legend: R = Readable bit -n = Value at POR bit 31-26 Unimplemented: Read as ‘0’ bit 25-16 CAL: RTC Drift Calibration bits, which contain a signed 10-bit integer value 0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute • • • W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown 0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute 0000000000 = No adjustment 1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute • • • 1000000000 = Minimum negative adjustment, subtracts 512 clock pulses every one minute bit 15 ON: RTCC On bit(2,3) 1 = RTCC module is enabled 0 = RTCC module is disabled Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode 0 = Continue normal operation in Idle mode Unimplemented: Read as ‘0’ RTSECSEL: RTCC Seconds Clock Output Select bit(4) 1 = RTCC Seconds Clock is selected for the RTCC pin 0 = RTCC Alarm Pulse is selected for the RTCC pin RTCCLKON: RTCC Clock Enable Status bit 1 = RTCC Clock is actively running 0 = RTCC Clock is not running Unimplemented: Read as ‘0’ This register is reset only on a Power-on Reset (POR). The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Requires RTCOE = 1 (RTCCON) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME). bit 14 bit 13 bit 12-8 bit 7 bit 6 bit 5-4 Note 1: 2: 3: 4: 5: 6: DS61168D-page 194 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-1: bit 3 RTCCON: RTC CONTROL REGISTER(1) (CONTINUED) RTCWREN: RTC Value Registers Write Enable bit(5) 1 = RTC Value registers can be written to by the user 0 = RTC Value registers are locked out from being written to by the user RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data read If the register is read twice and results in the same data, the data can be assumed to be valid 0 = RTC Value registers can be read without concern about a rollover ripple HALFSEC: Half-Second Status bit(6) 1 = Second half period of a second 0 = First half period of a second RTCOE: RTCC Output Enable bit 1 = RTCC clock output enabled – clock presented onto an I/O 0 = RTCC clock output disabled This register is reset only on a Power-on Reset (POR). The ON bit is only writable when RTCWREN = 1. When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Requires RTCOE = 1 (RTCCON) for the output to be active. The RTCWREN bit can be set only when the write sequence is enabled. This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME). bit 2 bit 1 bit 0 Note 1: 2: 3: 4: 5: 6: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 195 PIC32MX1XX/2XX REGISTER 20-2: Bit Range 31:24 23:16 15:8 7:0 RTCALRM: RTC ALARM CONTROL REGISTER(1) Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — PIV R/W-0 (3) R/W-0 — R-0 — R/W-0 — R/W-0 — R/W-0 (3) R/W-0 — R/W-0 ALRMEN(2,3) R/W-0 CHIME(3) R/W-0 ALRMSYNC(4) R/W-0 R/W-0 AMASK R/W-0 R/W-0 ARPT(3) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ALRMEN: Alarm Enable bit(2,3) 1 = Alarm is enabled 0 = Alarm is disabled CHIME: Chime Enable bit(3) 1 = Chime is enabled – ARPT is allowed to rollover from 0x00 to 0xFF 0 = Chime is disabled – ARPT stops once it reaches 0x00 PIV: Alarm Pulse Initial Value bit(3) When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse. When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse. ALRMSYNC: Alarm Sync bit(4) 1 = ARPT and ALRMEN may change as a result of a half second rollover during a read. The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple bits may be changing, which are then synchronized to the PB clock domain 0 = ARPT and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC clocks away from a half-second rollover AMASK: Alarm Mask Configuration bits(3) 0000 = Every half-second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29, once every four years) 1010 = Reserved; do not use 1011 = Reserved; do not use 11xx = Reserved; do not use This register is reset only on a Power-on Reset (POR). Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. bit 14 bit 13 bit 12 bit 11-8 Note 1: 2: 3: 4: DS61168D-page 196 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-2: bit 7-0 RTCALRM: RTC ALARM CONTROL REGISTER(1) (CONTINUED) ARPT: Alarm Repeat Counter Value bits(3) 11111111 = Alarm will trigger 256 times • • • 00000000 = Alarm will trigger one time The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1. Note 1: 2: 3: 4: This register is reset only on a Power-on Reset (POR). Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT = 00 and CHIME = 0. This field should not be written when the RTCC ON bit = ‘1’ (RTCCON) and ALRMSYNC = 1. This assumes a CPU read will execute in less than 32 PBCLKs. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 197 PIC32MX1XX/2XX REGISTER 20-3: Bit Range 31:24 23:16 15:8 7:0 RTCTIME: RTC TIME VALUE REGISTER(1) Bit 30/22/14/6 R/W-x Bit 31/23/15/7 R/W-x Bit 29/21/13/5 R/W-x Bit 28/20/12/4 R/W-x Bit 27/19/11/3 R/W-x Bit 26/18/10/2 R/W-x Bit 25/17/9/1 R/W-x Bit 24/16/8/0 R/W-x HR10 R/W-x R/W-x R/W-x R/W-x R/W-x HR01 R/W-x R/W-x R/W-x MIN10 R/W-x R/W-x R/W-x R/W-x R/W-x MIN01 R/W-x R/W-x R/W-x SEC10 U-0 U-0 U-0 U-0 U-0 SEC01 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 HR10: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 bit 7-0 Note 1: SEC01: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ This register is only writable when RTCWREN = 1 (RTCCON). DS61168D-page 198 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-4: Bit Range 31:24 23:16 15:8 7:0 RTCDATE: RTC DATE VALUE REGISTER(1) Bit 30/22/14/6 R/W-x Bit 31/23/15/7 R/W-x Bit 29/21/13/5 R/W-x Bit 28/20/12/4 R/W-x Bit 27/19/11/3 R/W-x Bit 26/18/10/2 R/W-x Bit 25/17/9/1 R/W-x Bit 24/16/8/0 R/W-x YEAR10 R/W-x R/W-x R/W-x R/W-x R/W-x YEAR01 R/W-x R/W-x R/W-x MONTH10 R/W-x R/W-x R/W-x R/W-x R/W-x MONTH01 R/W-x R/W-x R/W-x DAY10 U-0 U-0 U-0 U-0 R/W-x DAY01 R/W-x R/W-x R/W-x — — — — WDAY01 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 YEAR10: Binary-Coded Decimal Value of Years bits, 10 digits bit 27-24 YEAR01: Binary-Coded Decimal Value of Years bits, 1 digit bit 23-20 MONTH10: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3 bit 11-8 bit 7-4 bit 3-0 Note 1: DAY01: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ WDAY01: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6 This register is only writable when RTCWREN = 1 (RTCCON). © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 199 PIC32MX1XX/2XX REGISTER 20-5: Bit Range 31:24 23:16 15:8 7:0 ALRMTIME: ALARM TIME VALUE REGISTER Bit 30/22/14/6 R/W-x Bit 31/23/15/7 R/W-x Bit 29/21/13/5 R/W-x Bit 28/20/12/4 R/W-x Bit 27/19/11/3 R/W-x Bit 26/18/10/2 R/W-x Bit 25/17/9/1 R/W-x Bit 24/16/8/0 R/W-x HR10 R/W-x R/W-x R/W-x R/W-x R/W-x HR01 R/W-x R/W-x R/W-x MIN10 R/W-x R/W-x R/W-x R/W-x R/W-x MIN01 R/W-x R/W-x R/W-x SEC10 U-0 U-0 U-0 U-0 U-0 SEC01 U-0 U-0 U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 HR10: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2 bit 27-24 HR01: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9 bit 23-20 MIN10: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5 bit 19-16 MIN01: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9 bit 15-12 SEC10: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5 bit 11-8 bit 7-0 SEC01: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ DS61168D-page 200 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 20-6: Bit Range 31:24 23:16 15:8 7:0 ALRMDATE: ALARM DATE VALUE REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit Bit 27/19/11/3 26/18/10/2 U-0 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — R/W-x — R/W-x — R/W-x — R/W-x — R/W-x — R/W-x — R/W-x — R/W-x MONTH10 R/W-x R/W-x R/W-x R/W-x R/W-x MONTH01 R/W-x R/W-x R/W-x DAY10 U-0 U-0 U-0 U-0 R/W-x DAY01 R/W-x R/W-x R/W-x — — — — WDAY01 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-24 Unimplemented: Read as ‘0’ bit 23-20 MONTH10: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1 bit 19-16 MONTH01: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9 bit 15-12 DAY10: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3 bit 11-8 bit 7-4 bit 3-0 DAY01: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9 Unimplemented: Read as ‘0’ WDAY01: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 201 PIC32MX1XX/2XX NOTES: DS61168D-page 202 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 21.0 10-BIT ANALOG-TO-DIGITAL CONVERTER (ADC) The PIC32MX1XX/2XX 10-bit Analog-to-Digital Converter (ADC) includes the following features: • Successive Approximation Register (SAR) conversion • Up to 1 Msps conversion speed • Up to 13 analog input pins • External voltage reference input pins • One unipolar, differential Sample and Hold Amplifier (SHA) • Automatic Channel Scan mode • Selectable conversion trigger source • 16-word conversion result buffer • Selectable buffer fill modes • Eight conversion result format options • Operation during CPU Sleep and Idle modes A block diagram of the 10-bit ADC is illustrated in Figure 21-1. The 10-bit ADC has up to 13 analog input pins, designated AN0-AN12. In addition, there are two analog input pins for external voltage reference connections. These voltage reference inputs may be shared with other analog input pins and may be common to other analog module references. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 21-1: ADC1 MODULE BLOCK DIAGRAM CTMUI(3) AN0 VREF+(1) AVDD VREF-(1) AVSS AN12(2) CTMUT(3) IVREF(4) Open(5) Channel Scan CH0SA CSCNA AN1 VREFL CH0SB S&H + - VCFG ADC1BUF0 ADC1BUF1 VREFH VREFL ADC1BUF2 SAR ADC ADC1BUFE ADC1BUFF CH0NA CH0NB Alternate Input Selection Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs. 2: 3: 4: 5: AN8 is only available on 44-pin devices. AN6 and AN7 are not available on 28-pin devices. Connected to the CTMU module. See Section 24.0 “Charge Time Measurement Unit (CTMU)” for more information. See Section 23.0 “Comparator Voltage Reference (CVREF)” for more information. This selection is only used with CTMU capacitive and time measurement. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 203 PIC32MX1XX/2XX FIGURE 21-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM ADRC FRC(1) Div 2 ADCS 8 ADC Conversion Clock Multiplier 2, 4,..., 512 1 TAD 0 T PB(2) Note 1: 2: See Section 29.0 “Electrical Characteristics” for the exact FRC clock value. Refer to Figure 8-1 in Section 8.0 “Oscillator Configuration” for more information. DS61168D-page 204 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-1: Bit Range 31:24 23:16 15:8 7:0 AD1CON1: ADC CONTROL REGISTER 1 Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — R/W-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 ON(1) R/W-0 — R/W-0 SIDL R/W-0 — R/W-0 — U-0 R/W-0 FORM ASAM R/W-0, HSC (2) SSRC CLRASAM — SAMP R/C-0, HSC (3) DONE Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: ADC Operating Mode bit(1) 1 = ADC module is operating 0 = ADC module is not operating Unimplemented: Read as ‘0’ SIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode FORM: Data Output Format bits 011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000) 010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000) 001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd) 000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) 111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000) 110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000) 101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd) 100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd) SSRC: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto convert) 110 = Reserved 101 = Reserved 100 = Reserved 011 = CTMU ends sampling and starts conversion 010 = Timer 3 period match ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ≠ ‘0’, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. bit 14 bit 13 bit 12-11 Unimplemented: Read as ‘0’ bit 10-8 bit 7-5 Note 1: 2: 3: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 205 PIC32MX1XX/2XX REGISTER 21-1: bit 4 AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED) CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated) 1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the ADC interrupt is generated. 0 = Normal operation, buffer contents will be overwritten by the next conversion sequence Unimplemented: Read as ‘0’ ASAM: ADC Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set. 0 = Sampling begins when SAMP bit is set SAMP: ADC Sample Enable bit(2) 1 = The ADC sample and hold amplifier is sampling 0 = The ADC sample/hold amplifier is holding When ASAM = 0, writing ‘1’ to this bit starts sampling. When SSRC = 000, writing ‘0’ to this bit will end sampling and start conversion. DONE: Analog-to-Digital Conversion Status bit(3) 1 = Analog-to-digital conversion is done 0 = Analog-to-digital conversion is not done or has not started Clearing this bit will not affect any operation in progress. When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if ASAM = 1. If SSRC = 0, software can write a ‘0’ to end sampling and start conversion. If SSRC ≠ ‘0’, this bit is automatically cleared by hardware to end sampling and start conversion. This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation already in progress. This bit is automatically cleared by hardware at the start of a new conversion. bit 3 bit 2 bit 1 bit 0 Note 1: 2: 3: DS61168D-page 206 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-2: Bit Range 31:24 23:16 15:8 7:0 AD1CON2: ADC CONTROL REGISTER 2 Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 R-0 — R/W-0 — R/W-0 R/W-0 — R/W-0 — U-0 — R/W-0 — U-0 — U-0 VCFG U-0 OFFCAL R/W-0 — R/W-0 CSCNA R/W-0 — R/W-0 — R/W-0 BUFS — SMPI BUFM ALTS Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-13 VCFG: Voltage Reference Configuration bits VREFH 000 001 010 011 1xx bit 12 AVDD External VREF+ pin AVDD External VREF+ pin AVDD VREFL AVss AVSS External VREF- pin External VREF- pin AVSS bit 11 bit 10 bit 9-8 bit 7 bit 6 bit 5-2 OFFCAL: Input Offset Calibration Mode Select bit 1 = Enable Offset Calibration mode Positive and negative inputs of the sample and hold amplifier are connected to VREFL 0 = Disable Offset Calibration mode The inputs to the sample and hold amplifier are controlled by AD1CHS or AD1CSSL Unimplemented: Read as ‘0’ CSCNA: Input Scan Select bit 1 = Scan inputs 0 = Do not scan inputs Unimplemented: Read as ‘0’ BUFS: Buffer Fill Status bit Only valid when BUFM = 1. 1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7 0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF Unimplemented: Read as ‘0’ SMPI: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence • • • bit 1 bit 0 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence BUFM: ADC Result Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8 0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses Sample A input multiplexer settings for first sample, then alternates between Sample B and Sample A input multiplexer settings for all subsequent samples 0 = Always use Sample A input multiplexer settings © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 207 PIC32MX1XX/2XX REGISTER 21-3: Bit Range 31:24 23:16 15:8 7:0 AD1CON3: ADC CONTROL REGISTER 3 Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 ADRC R/W-0 — R/W-0 — R/W-0 R/W-0 SAMC(1) ADCS R/W-0 (2) R/W-0 R/W R/W-0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ADRC: ADC Conversion Clock Source bit 1 = Clock derived from FRC 0 = Clock derived from Peripheral Bus Clock (PBCLK) SAMC: Auto-Sample Time bits(1) 11111 = 31 TAD • • • 00001 = 1 TAD 00000 = 0 TAD (Not allowed) ADCS: ADC Conversion Clock Select bits(2) 11111111 =TPB • 2 • (ADCS + 1) = 512 • TPB = TAD • • • 00000001 =TPB • 2 • (ADCS + 1) = 4 • TPB = TAD 00000000 =TPB • 2 • (ADCS + 1) = 2 • TPB = TAD This bit is only used if the SSRC bits (AD1CON1) = 111. This bit is not used if the ADRC bit (AD1CON3) = 1. bit 14-13 Unimplemented: Read as ‘0’ bit 12-8 bit 7-0 Note 1: 2: DS61168D-page 208 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 21-4: Bit Range 31:24 23:16 15:8 7:0 AD1CHS: ADC INPUT SELECT REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 R/W-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 R/W-0 Bit 26/18/10/2 R/W-0 Bit 25/17/9/1 R/W-0 Bit 24/16/8/0 R/W-0 CH0NB R/W-0 — U-0 — U-0 — U-0 R/W-0 CH0SB R/W-0 R/W-0 R/W-0 CH0NA U-0 — U-0 — U-0 — U-0 U-0 CH0SA U-0 U-0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — — — — — — — — Legend: R = Readable bit -n = Value at POR bit 31 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown CH0NB: Negative Input Select bit for Sample B 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL Unimplemented: Read as ‘0’ CH0SB: Positive Input Select bits for Sample B 1111 = Channel 0 positive input is Open(1) 1110 = Channel 0 positive input is IVREF(2) 1101 = Channel 0 positive input is CTMU temperature sensor (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) • • • 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting(2) 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VREFL Unimplemented: Read as ‘0’ CH0SA: Positive Input Select bits for Sample A Multiplexer Setting 1111 = Channel 0 positive input is Open(1) 1110 = Channel 0 positive input is IVREF(2) 1101 = Channel 0 positive input is CTMU temperature (CTMUT)(3) 1100 = Channel 0 positive input is AN12(4) • • • 0001 = Channel 0 positive input is AN1 0000 = Channel 0 positive input is AN0 Unimplemented: Read as ‘0’ This selection is only used with CTMU capacitive and time measurement. See Section 23.0 “Comparator Voltage Reference (CVREF)” for more information. See Section 24.0 “Charge Time Measurement Unit (CTMU)” for more information. AN12 is only available on 44-pin devices. AN6-AN8 are not available on 28-pin devices. bit 30-28 bit 27-24 bit 23 bit 22-20 bit 19-16 bit 15-0 Note 1: 2: 3: 4: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 209 PIC32MX1XX/2XX REGISTER 21-5: Bit Range 31:24 23:16 15:8 7:0 AD1CSSL: ADC INPUT SCAN SELECT REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 CSSL15 R/W-0 CSSL14 R/W-0 CSSL13 R/W-0 CSSL12 R/W-0 CSSL11 R/W-0 CSSL10 R/W-0 CSSL9 R/W-0 CSSL8 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15-0 CSSL: ADC Input Pin Scan Selection bits(1,2) 1 = Select ANx for input scan 0 = Skip ANx for input scan CSSL = ANx, where x = 0-12; CSSL13 selects CTMU input for scan; CSSL14 selects IVREF for scan; CSSL15 selects VSS for scan. On devices with less than 13 analog inputs, all CSSLx bits can be selected; however, inputs selected for scan without a corresponding input on the device will convert to VREFL. Note 1: 2: DS61168D-page 210 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 22.0 COMPARATOR Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to S ection 19. “Comparator” (DS61110) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The PIC32MX1XX/2XX Analog Comparator module contains three comparators that can be configured in a variety of ways. Following are some of the key features of this module: • Selectable inputs available include: - Analog inputs multiplexed with I/O pins - On-chip internal absolute voltage reference (IVREF) - Comparator voltage reference (CVREF) • Outputs can be Inverted • Selectable interrupt generation A block diagram of the comparator module is provided in Figure 22-1. FIGURE 22-1: C1INB C1INC COMPARATOR BLOCK DIAGRAM CCH COE C1IND CREF C1INA CPOL CMSTAT CM1CON CMP1 C1OUT C2INB C2INC CCH To CTMU module (Pulse Generator) COE C2IND CREF C2INA CMP2 C2OUT CPOL CMSTAT CM2CON C3INB C3INC CCH COE C3IND CREF C3INA CVREF(1) Note 1: Internally connected. See Section 23.0 “Comparator Voltage Reference (CVREF)” for more information. CMP3 C3OUT CPOL CMSTAT CM3CON IVREF (1.2V) © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 211 PIC32MX1XX/2XX REGISTER 22-1: Bit Range 31:24 23:16 15:8 7:0 CMXCON: COMPARATOR CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) R/W-1 — R/W-0 — CPOL U-0 R/W-0 (2) — U-0 — U-0 — U-0 — U-0 — R-0 COE R/W-1 — R/W-0 — U-0 — U-0 — R/W-1 COUT R/W-1 EVPOL — CREF — — CCH Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Comparator ON bit(1) 1 = Module is enabled. Setting this bit does not affect the other bits in this register 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in this register COE: Comparator Output Enable bit 1 = Comparator output is driven on the output CxOUT pin 0 = Comparator output is not driven on the output CxOUT pin CPOL: Comparator Output Inversion bit(2) 1 = Output is inverted 0 = Output is not inverted Unimplemented: Read as ‘0’ COUT: Comparator Output bit 1 = Output of the Comparator is a ‘1’ 0 = Output of the Comparator is a ‘0’ EVPOL: Interrupt Event Polarity Select bits 11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output 10 = Comparator interrupt is generated on a high-to-low transition of the comparator output 01 = Comparator interrupt is generated on a low-to-high transition of the comparator output 00 = Comparator interrupt generation is disabled Unimplemented: Read as ‘0’ CREF: Comparator Positive Input Configure bit 1 = Comparator non-inverting input is connected to the internal CVREF 0 = Comparator non-inverting input is connected to the CXINA pin Unimplemented: Read as ‘0’ CCH: Comparator Negative Input Select bits for Comparator 11 = Comparator inverting input is connected to the IVREF 10 = Comparator inverting input is connected to the CxIND pin 01 = Comparator inverting input is connected to the CxINC pin 00 = Comparator inverting input is connected to the CxINB pin When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an interrupt being generated on the opposite edge from the one selected by EVPOL. bit 14 bit 13 bit 12-9 bit 8 bit 7-6 bit 5 bit 4 bit 3-2 bit 1-0 Note 1: 2: DS61168D-page 212 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 22-2: Bit Range 31:24 23:16 15:8 7:0 CMSTAT: COMPARATOR STATUS REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit Bit 28/20/12/4 27/19/11/3 U-0 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 SIDL U-0 — U-0 — U-0 — R-0 — R-0 — R-0 — — — — — C3OUT C2OUT C1OUT Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as ‘0’ bit 13 SIDL: Stop in IDLE Control bit 1 = All Comparator modules are disabled in IDLE mode 0 = All Comparator modules continue to operate in the IDLE mode Unimplemented: Read as ‘0’ C3OUT: Comparator Output bit 1 = Output of Comparator 3 is a ‘1’ 0 = Output of Comparator 3 is a ‘0’ C2OUT: Comparator Output bit 1 = Output of Comparator 2 is a ‘1’ 0 = Output of Comparator 2 is a ‘0’ C1OUT: Comparator Output bit 1 = Output of Comparator 1 is a ‘1’ 0 = Output of Comparator 1 is a ‘0’ bit 12-3 bit 2 bit 1 bit 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 213 PIC32MX1XX/2XX NOTES: DS61168D-page 214 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 23.0 COMPARATOR VOLTAGE REFERENCE (CVREF) The CVREF module is a 16-tap, resistor ladder network that provides a selectable reference voltage. Although its primary purpose is to provide a reference for the analog comparators, it also may be used independently of them. A block diagram of the module is illustrated in Figure 23-1. The resistor ladder is segmented to provide two ranges of voltage reference values and has a power-down function to conserve power when the reference is not being used. The module’s supply reference can be provided from either device VDD/VSS or an external voltage reference. The CVREF output is available for the comparators and typically available for pin output. The comparator voltage reference has the following features: • High and low range selection • Sixteen output levels available for each range • Internally connected to comparators to conserve device pins • Output can be connected to a pin Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 20. “Comparator Voltage Reference (CVREF)” (DS61109) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 23-1: VREF+ AVDD COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM CVRSS = 1 CVRSRC CVRSS = 0 8R R R R 16-to-1 MUX R 16 Steps CVR CVREF CVREN CVREFOUT CVRCON R R R CVRR VREFAVSS CVRSS = 1 8R CVRSS = 0 © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 215 PIC32MX1XX/2XX REGISTER 23-1: Bit Range 31:24 23:16 15:8 7:0 CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — R/W-0 — CVROE CVRR CVRSS CVR Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Comparator Voltage Reference On bit(1) 1 = Module is enabled Setting this bit does not affect other bits in the register. 0 = Module is disabled and does not consume current. Clearing this bit does not affect the other bits in the register. Unimplemented: Read as ‘0’ CVROE: CVREFOUT Enable bit 1 = Voltage level is output on CVREFOUT pin 0 = Voltage level is disconnected from CVREFOUT pin CVRR: CVREF Range Selection bit 1 = 0 to 0.67 CVRSRC, with CVRSRC/24 step size 0 = 0.25 CVRSRC to 0.75 CVRSRC, with CVRSRC/32 step size CVRSS: CVREF Source Selection bit 1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-) 0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS CVR: CVREF Value Selection 0 ≤CVR ≤15 bits When CVRR = 1: CVREF = (CVR/24) • (CVRSRC) When CVRR = 0: CVREF = 1/4 • (CVRSRC) + (CVR/32) • (CVRSRC) bit 14-7 bit 6 bit 5 bit 4 bit 3-0 Note 1: When using 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. DS61168D-page 216 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 24.0 CHARGE TIME MEASUREMENT UNIT (CTMU) on-chip analog modules, the CTMU can be used for high resolution time measurement, measure capacitance, measure relative changes in capacitance or generate output pulses with a specific time delay. The CTMU is ideal for interfacing with capacitive-based sensors. The module includes the following key features: • Up to 13 channels available for capacitive or time measurement input • On-chip precision current source • 16-edge input trigger sources • Selection of edge or level-sensitive inputs • Polarity control for each edge source • Control of edge sequence • Control of response to edges • High precision time measurement • Time delay of external or internal signal asynchronous to system clock • Integrated temperature sensing diode • Control of current source during auto-sampling • Four current source ranges • Time measurement resolution of one nanosecond A block diagram of the CTMU is shown in Figure 24-1. Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 37. “Charge Time Measurement Unit (CTMU)” (DS61167) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The Charge Time Measurement Unit (CTMU) is a flexible analog module that has a configurable current source with a digital configuration circuit built around it. The CTMU can be used for differential time measurement between pulse sources and can be used for generating an asynchronous pulse. By working with other FIGURE 24-1: CTMU BLOCK DIAGRAM CTMUCON1 or CTMUCON2 CTMUICON ITRIM IRNG Current Source CTED1 • • • CTED13 Timer1 OC1 IC1-IC3 CMP1-CMP3 PBCLK CTMUT (To ADC) Edge Control Logic EDG1STAT EDG2STAT TGEN Current Control CTMUP CTMU Control Logic ADC Trigger Pulse Generator CTPLS CTMUI (To ADC S&H capacitor) C2INB CDelay Comparator 2 External capacitor for pulse generation Temperature Sensor Current Control Selection CTMUT CTMUI CTMUP No Connect TGEN 0 0 1 1 EDG1STAT, EDG2STAT EDG1STAT = EDG2STAT EDG1STAT ≠ EDG2STAT EDG1STAT ≠ EDG2STAT EDG1STAT = EDG2STAT © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 217 PIC32MX1XX/2XX REGISTER 24-1: Bit Range 31:24 23:16 15:8 7:0 Bit 31/23/15/7 R/W-0 R/W-0 R/W-0 CTMUCON: CTMU CONTROL REGISTER Bit 30/22/14/6 R/W-0 R/W-0 U-0 Bit 29/21/13/5 R/W-0 R/W-0 R/W-0 Bit Bit 28/20/12/4 27/19/11/3 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Bit 26/18/10/2 R/W-0 R/W-0 R/W-0 Bit 25/17/9/1 R/W-0 U-0 Bit 24/16/8/0 R/W-0 U-0 EDG1MOD EDG1POL EDG2MOD EDG2POL ON R/W-0 EDG1SEL EDG2SEL CTMUSIDL R/W-0 EDG2STAT EDG1STAT — R/W-0 — R/W-0 — R/W-0 TGEN(1) R/W-0 EDGEN R/W-0 EDGSEQEN R/W-0 IDISSEN(2) R/W-0 CTTRIG R/W-0 ITRIM IRNG Legend: R = Readable bit -n = Value at POR bit 31 W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown EDG1MOD: Edge1 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 30 EDG1POL: Edge 1 Polarity Select bit 1 = Edge1 programmed for a positive edge response 0 = Edge1 programmed for a negative edge response bit 29-26 EDG1SEL: Edge 1 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = IC3 Capture Event is selected 1011 = IC2 Capture Event is selected 1010 = IC1 Capture Event is selected 1001 = CTED8 pin is selected 1000 = CTED7 pin is selected 0111 = CTED6 pin is selected 0110 = CTED5 pin is selected 0101 = CTED4 pin is selected 0100 = CTED3 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 25 EDG2STAT: Edge2 Status bit Indicates the status of Edge2 and can be written to control edge source 1 = Edge2 has occurred 0 = Edge2 has not occurred Note 1: 2: When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 “Electrical Characteristics” for current values. This bit setting is not available for the CTMU temperature diode. 3: 4: DS61168D-page 218 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 24-1: bit 24 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) EDG1STAT: Edge1 Status bit Indicates the status of Edge1 and can be written to control edge source 1 = Edge1 has occurred 0 = Edge1 has not occurred bit 23 EDG2MOD: Edge2 Edge Sampling Select bit 1 = Input is edge-sensitive 0 = Input is level-sensitive bit 22 EDG2POL: Edge 2 Polarity Select bit 1 = Edge2 programmed for a positive edge response 0 = Edge2 programmed for a negative edge response bit 21-18 EDG2SEL: Edge 2 Source Select bits 1111 = C3OUT pin is selected 1110 = C2OUT pin is selected 1101 = C1OUT pin is selected 1100 = PBCLK clock is selected 1011 = IC3 Capture Event is selected 1010 = IC2 Capture Event is selected 1001 = IC1 Capture Event is selected 1000 = CTED13 pin is selected 0111 = CTED12 pin is selected 0110 = CTED11 pin is selected 0101 = CTED10 pin is selected 0100 = CTED9 pin is selected 0011 = CTED1 pin is selected 0010 = CTED2 pin is selected 0001 = OC1 Compare Event is selected 0000 = Timer1 Event is selected bit 17-16 Unimplemented: Read as ‘0’ bit 15 ON: ON Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as ‘0’ bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit(1) 1 = Enables edge delay generation 0 = Disables edge delay generation bit 11 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked Note 1: 2: When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 “Electrical Characteristics” for current values. This bit setting is not available for the CTMU temperature diode. 3: 4: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 219 PIC32MX1XX/2XX REGISTER 24-1: bit 10 CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 9 bit 8 bit 7-2 EDGSEQEN: Edge Sequence Enable bit 1 = Edge1 must occur before Edge2 can occur 0 = No edge sequence is needed IDISSEN: Analog Current Source Control bit(2) 1 = Analog current source output is grounded 0 = Analog current source output is not grounded CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled ITRIM: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 • • • 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG 111111 = Minimum negative change from nominal current • • • bit 1-0 100010 100001 = Maximum negative change from nominal current IRNG: Current Range Select bits(3) 11 = 100 times base current 10 = 10 times base current 01 = Base current level 00 = 1000 times base current(4) When this bit is set for Pulse Delay Generation, the EDG2SEL bits must be set to ‘1110’ to select C2OUT. The ADC module Sample and Hold capacitor is not automatically discharged between sample/conversion cycles. Software using the ADC as part of a capacitive measurement, must discharge the ADC capacitor before conducting the measurement. The IDISSEN bit, when set to ‘1’, performs this function. The ADC module must be sampling while the IDISSEN bit is active to connect the discharge sink to the capacitor array. Refer to the CTMU Current Source Specifications (Table 29-39) in Section 29.0 “Electrical Characteristics” for current values. This bit setting is not available for the CTMU temperature diode. Note 1: 2: 3: 4: DS61168D-page 220 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 25.0 POWER-SAVING FEATURES Note 1: This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 10. “PowerSaving Features” (DS61130) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. This section describes power-saving features for the PIC32MX1XX/2XX. The PIC32 devices offer a total of nine methods and modes, organized into two categories, that allow the user to balance power consumption with device performance. In all of the methods and modes described in this section, powersaving is controlled by software. • LPRC Idle mode: the system clock is derived from the LPRC. Peripherals continue to operate, but can optionally be individually disabled. This is the lowest power mode for the device with a clock running. • Sleep mode: the CPU, the system clock source and any peripherals that operate from the system clock source are Halted. Some peripherals can operate in Sleep using specific clock sources. This is the lowest power mode for the device. 25.3 Power-Saving Operation Peripherals and the CPU can be Halted or disabled to further reduce power consumption. 25.3.1 SLEEP MODE Sleep mode has the lowest power consumption of the device power-saving operating modes. The CPU and most peripherals are Halted. Select peripherals can continue to operate in Sleep mode and can be used to wake the device from Sleep. See the individual peripheral module sections for descriptions of behavior in Sleep. Sleep mode includes the following characteristics: • The CPU is Halted. • The system clock source is typically shutdown. See Section 25.3.3 “Peripheral Bus Scaling Method” for specific information. • There can be a wake-up delay based on the oscillator selection. • The Fail-Safe Clock Monitor (FSCM) does not operate during Sleep mode. • The BOR circuit remains operative during Sleep mode. • The WDT, if enabled, is not automatically cleared prior to entering Sleep mode. • Some peripherals can continue to operate at limited functionality in Sleep mode. These peripherals include I/O pins that detect a change in the input signal, WDT, ADC, UART and peripherals that use an external clock input or the internal LPRC oscillator (e.g., RTCC, Timer1 and Input Capture). • I/O pins continue to sink or source current in the same manner as they do when the device is not in Sleep. • The USB module can override the disabling of the Posc or FRC. Refer to the USB section for specific details. • Modules can be individually disabled by software prior to entering Sleep in order to further reduce consumption. 25.1 Power Saving with CPU Running When the CPU is running, power consumption can be controlled by reducing the CPU clock frequency, lowering the PBCLK and by individually disabling modules. These methods are grouped into the following categories: • FRC Run mode: the CPU is clocked from the FRC clock source with or without postscalers. • LPRC Run mode: the CPU is clocked from the LPRC clock source. • SOSC Run mode: the CPU is clocked from the SOSC clock source. In addition, the Peripheral Bus Scaling mode is available where peripherals are clocked at the programmable fraction of the CPU clock (SYSCLK). 25.2 CPU Halted Methods The device supports two power-saving modes, Sleep and Idle, both of which Halt the clock to the CPU. These modes operate with all clock sources, as listed below: • POSC Idle mode: the system clock is derived from the POSC. The system clock source continues to operate. Peripherals continue to operate, but can optionally be individually disabled. • FRC Idle mode: the system clock is derived from the FRC with or without postscalers. Peripherals continue to operate, but can optionally be individually disabled. • SOSC Idle mode: the system clock is derived from the SOSC. Peripherals continue to operate, but can optionally be individually disabled. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 221 PIC32MX1XX/2XX The processor will exit, or ‘wake-up’, from Sleep on one of the following events: • On any interrupt from an enabled source that is operating in Sleep. The interrupt priority must be greater than the current CPU priority. • On any form of device Reset. • On a WDT time-out. If the interrupt priority is lower than or equal to the current priority, the CPU will remain Halted, but the PBCLK will start running and the device will enter into Idle mode. The device enters Idle mode when the SLPEN bit (OSCCON) is clear and a WAIT instruction is executed. The processor will wake or exit from Idle mode on the following events: • On any interrupt event for which the interrupt source is enabled. The priority of the interrupt event must be greater than the current priority of the CPU. If the priority of the interrupt event is lower than or equal to current priority of the CPU, the CPU will remain Halted and the device will remain in Idle mode. • On any form of device Reset • On a WDT time-out interrupt 25.3.2 IDLE MODE In Idle mode, the CPU is Halted but the System Clock (SYSCLK) source is still enabled. This allows peripherals to continue operation when the CPU is Halted. Peripherals can be individually configured to Halt when entering Idle by setting their respective SIDL bit. Latency, when exiting Idle mode, is very low due to the CPU oscillator source remaining active. Note 1: Changing the PBCLK divider ratio requires recalculation of peripheral timing. For example, assume the UART is configured for 9600 baud with a PB clock ratio of 1:1 and a POSC of 8 MHz. When the PB clock divisor of 1:2 is used, the input frequency to the baud clock is cut in half; therefore, the baud rate is reduced to 1/2 its former value. Due to numeric truncation in calculations (such as the baud rate divisor), the actual baud rate may be a tiny percentage different than expected. For this reason, any timing calculation required for a peripheral should be performed with the new PB clock frequency instead of scaling the previous value based on a change in the PB divisor ratio. 2: Oscillator start-up and PLL lock delays are applied when switching to a clock source that was disabled and that uses a crystal and/or the PLL. For example, assume the clock source is switched from POSC to LPRC just prior to entering Sleep in order to save power. No oscillator startup delay would be applied when exiting Idle. However, when switching back to POSC, the appropriate PLL and/or oscillator start-up/lock delays would be applied. 25.3.3 PERIPHERAL BUS SCALING METHOD Most of the peripherals on the device are clocked using the PBCLK. The peripheral bus can be scaled relative to the SYSCLK to minimize the dynamic power consumed by the peripherals. The PBCLK divisor is controlled by PBDIV (OSCCON), allowing SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All peripherals using PBCLK are affected when the divisor is changed. Peripherals such as the USB, Interrupt Controller, DMA, and the bus matrix are clocked directly from SYSCLK. As a result, they are not affected by PBCLK divisor changes. Changing the PBCLK divisor affects: • The CPU to peripheral access latency. The CPU has to wait for next PBCLK edge for a read to complete. In 1:8 mode, this results in a latency of one to seven SYSCLKs. • The power consumption of the peripherals. Power consumption is directly proportional to the frequency at which the peripherals are clocked. The greater the divisor, the lower the power consumed by the peripherals. To minimize dynamic power, the PB divisor should be chosen to run the peripherals at the lowest frequency that provides acceptable system performance. When selecting a PBCLK divider, peripheral clock requirements, such as baud rate accuracy, should be taken into account. For example, the UART peripheral may not be able to achieve all baud rate values at some PBCLK divider depending on the SYSCLK value. DS61168D-page 222 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 25.4 Peripheral Module Disable The Peripheral Module Disable (PMD) registers provide a method to disable a peripheral module by stopping all clock sources supplied to that module. When a peripheral is disabled using the appropriate PMD control bit, the peripheral is in a minimum power consumption state. The control and status registers associated with the peripheral are also disabled, so writes to those registers do not have effect and read values are invalid. To disable a peripheral, the associated PMDx bit must be set to ‘1’. To enable a peripheral, the associated PMDx bit must be cleared (default). See Table 25-1 for more information. Note: Disabling a peripheral module while it’s ON bit is set, may result in undefined behavior. The ON bit for the associated peripheral module must be cleared prior to disable a module via the PMDx bits. TABLE 25-1: ADC1 CTMU PERIPHERAL MODULE DISABLE BITS AND LOCATIONS(1) PMDx bit Name AD1MD CTMUMD CVRMD CMP1MD CMP2MD CMP3MD IC1MD IC2MD IC3MD IC4MD IC5MD OC1MD OC2MD OC3MD OC4MD OC5MD T1MD T2MD T3MD T4MD T5MD U1MD U2MD SPI1MD SPI2MD I2C1MD I2C2MD USBMD RTCCMD REFOMD PMPMD Register Name and Bit Location PMD1 PMD1 PMD1 PMD2 PMD2 PMD2 PMD3 PMD3 PMD3 PMD3 PMD3 PMD3 PMD3 PMD3 PMD3 PMD3 PMD4 PMD4 PMD4 PMD4 PMD4 PMD5 PMD5 PMD5 PMD5 PMD5 PMD5 PMD5 PMD6 PMD6 PMD6 Peripheral Comparator Voltage Reference Comparator 1 Comparator 2 Comparator 3 Input Capture 1 Input Capture 2 Input Capture 3 Input Capture 4 Input Capture 5 Output Compare 1 Output Compare 2 Output Compare 3 Output Compare 4 Output Compare 5 Timer1 Timer2 Timer3 Timer4 Timer5 UART1 UART2 SPI1 SPI2 I2C1 I2C2 USB(2) RTCC Reference Clock Output PMP Note 1: 2: Not all modules and associated PMDx bits are available on all devices. See TABLE 1: “PIC32MX1XX General Purpose Family Features” and TABLE 2: “PIC32MX2XX USB Family Features” for the lists of available peripherals. Module must not be busy after clearing the associated ON bit and prior to setting the USBMD bit. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 223 PIC32MX1XX/2XX 25.4.1 CONTROLLING CONFIGURATION CHANGES Because peripherals can be disabled during run time, some restrictions on disabling peripherals are needed to prevent accidental configuration changes. PIC32 devices include two features to prevent alterations to enabled or disabled peripherals: • Control register lock sequence • Configuration bit select lock 25.4.1.1 Control Register Lock Under normal operation, writes to the PMDx registers are not allowed. Attempted writes appear to execute normally, but the contents of the registers remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the PMDLOCK Configuration bit (CFGCON). Setting PMDLOCK prevents writes to the control registers; clearing PMDLOCK allows writes. To set or clear PMDLOCK, an unlock sequence must be executed. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. 25.4.1.2 Configuration Bit Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the PMDx registers. The PMDL1WAY Configuration bit (DEVCFG3) blocks the PMDLOCK bit from being cleared after it has been set once. If PMDLOCK remains set, the register unlock procedure does not execute, and the peripheral pin select control registers cannot be written to. The only way to clear the bit and re-enable PMD functionality is to perform a device Reset. DS61168D-page 224 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 26.0 Note: SPECIAL FEATURES This data sheet summarizes the features of the PIC32MX1XX/2XX family of devices. However, it is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 9. “Watchdog Timer and Power-up Timer” (DS61114), Section 32. “Configuration” (DS61124) and Section 33. “Programming and Diagnostics” (DS61129) in the “PIC32 Family Reference Manual” (DS61132), which is available from the Microchip web site (www.microchip.com/PIC32). 26.1 Configuration Bits The Configuration bits can be programmed using the following registers to select various device configurations. • • • • • DEVCFG0: Device Configuration Word 0 DEVCFG1: Device Configuration Word 1 DEVCFG2: Device Configuration Word 2 DEVCFG3: Device Configuration Word 3 CFGCON: Configuration Control Register In addition, the DEVID register (Register 26-6) provides device and revision information. PIC32MX1XX/2XX devices include several features intended to maximize application flexibility and reliability and minimize cost through elimination of external components. These are: • • • • Flexible device configuration Watchdog Timer (WDT) Joint Test Action Group (JTAG) interface In-Circuit Serial Programming™ (ICSP™) © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 225 PIC32MX1XX/2XX REGISTER 26-1: Bit Range 31:24 23:16 15:8 7:0 DEVCFG0: DEVICE CONFIGURATION WORD 0 Bit 30/22/14/6 r-1 Bit 31/23/15/7 r-0 Bit 29/21/13/5 r-1 Bit 28/20/12/4 R/P Bit 27/19/11/3 r-1 Bit 26/18/10/2 r-1 Bit 25/17/9/1 r-1 Bit 24/16/8/0 R/P — r-1 — r-1 — r-1 CP r-1 — r-1 — r-1 — r-1 BWP r-1 — R/P — R/P — R/P — R/P — R/P — R/P — r-1 — r-1 PWP r-1 r-1 r-1 R/P R/P R/P — R/P — R/P — — — r = Reserved bit W = Writable bit ‘1’ = Bit is set ICESEL(2) JTAGEN(1) DEBUG Legend: R = Readable bit -n = Value at POR bit 31 bit 28 Reserved: Write ‘0’ P = Programmable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 30-29 Reserved: Write ‘1’ CP: Code-Protect bit Prevents boot and program Flash memory from being read or modified by an external programming device. 1 = Protection is disabled 0 = Protection is enabled BWP: Boot Flash Write-Protect bit Prevents boot Flash memory from being modified during code execution. 1 = Boot Flash is writable 0 = Boot Flash is not writable bit 27-25 Reserved: Write ‘1’ bit 24 bit 23-16 Reserved: Write ‘1’ Note 1: 2: This bit sets the value for the JTAGEN bit in the CFGCON register. The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for availability. DS61168D-page 226 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED) bit 15-10 PWP: Program Flash Write-Protect bits Prevents selected program Flash memory pages from being modified during code execution. 111111 = Disabled 111110 = Memory below 0x0400 address is write-protected 111101 = Memory below 0x0800 address is write-protected 111100 = Memory below 0x0C00 address is write-protected 111011 = Memory below 0x1000 address is write-protected 111010 = Memory below 0x1400 address is write-protected 111001 = Memory below 0x1800 address is write-protected 111000 = Memory below 0x1C00 address is write-protected 110111 = Memory below 0x2000 address is write-protected 110110 = Memory below 0x2400 address is write-protected 110101 = Memory below 0x2800 address is write-protected 110100 = Memory below 0x2C00 address is write-protected 110011 = Memory below 0x3000 address is write-protected 110010 = Memory below 0x3400 address is write-protected 110001 = Memory below 0x3800 address is write-protected 110000 = Memory below 0x3C00 address is write-protected 101111 = Memory below 0x4000 address is write-protected 101110 = Memory below 0x4400 address is write-protected 101101 = Memory below 0x4800 address is write-protected 101100 = Memory below 0x4C00 address is write-protected 101011 = Memory below 0x5000 address is write-protected 101010 = Memory below 0x5400 address is write-protected 101001 = Memory below 0x5800 address is write-protected 101000 = Memory below 0x5C00 address is write-protected 100111 = Memory below 0x6000 address is write-protected 100110 = Memory below 0x6400 address is write-protected 100101 = Memory below 0x6800 address is write-protected 100100 = Memory below 0x6C00 address is write-protected 100011 = Memory below 0x7000 address is write-protected 100010 = Memory below 0x7400 address is write-protected 100001 = Memory below 0x7800 address is write-protected 100000 = Memory below 0x7C00 address is write-protected 011111 = Memory below 0x8000 address is write-protected bit 9-5 bit 4-3 Reserved: Write ‘1’ ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bits 11 = PGEC1/PGED1 pair is used 10 = PGEC2/PGED2 pair is used 01 = PGEC3/PGED3 pair is used 00 = PGEC4/PGED4 pair is used(2) JTAGEN: JTAG Enable bit(1) 1 = JTAG is enabled 0 = JTAG is disabled DEBUG: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled) 1x = Debugger is disabled 0x = Debugger is enabled This bit sets the value for the JTAGEN bit in the CFGCON register. The PGEC4/PGED4 pin pair is not available on all devices. Refer to the “Pin Diagrams” section for availability. bit 2 bit 1-0 Note 1: 2: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 227 PIC32MX1XX/2XX REGISTER 26-2: Bit Range 31:24 23:16 15:8 7:0 DEVCFG1: DEVICE CONFIGURATION WORD 1 Bit 30/22/14/6 r-1 Bit 31/23/15/7 r-1 Bit 29/21/13/5 r-1 Bit 28/20/12/4 r-1 Bit 27/19/11/3 r-1 Bit 26/18/10/2 r-1 Bit 25/17/9/1 R/P Bit 24/16/8/0 R/P — R/P — R/P — r-1 — R/P — R/P — R/P FWDTWINSZ R/P R/P FWDTEN R/P WINDIS R/P — R/P R/P r-1 WDTPS R/P R/P R/P FCKSM R/P r-1 FPBDIV R/P r-1 — r-1 OSCIOFNC R/P POSCMOD R/P R/P IESO — FSOSCEN r = Reserved bit W = Writable bit ‘1’ = Bit is set — — P = Programmable bit FNOSC Legend: R = Readable bit -n = Value at POR bit 31-26 Reserved: Write ‘1’ U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 25-24 FWDTWINSZ: Watchdog Timer Window Size bits 11 = Window size is 25% 10 = Window size is 37.5% 01 = Window size is 50% 00 = Window size is 75% bit 23 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled and cannot be disabled by software 0 = Watchdog Timer is not enabled; it can be enabled in software WINDIS: Watchdog Timer Window Enable bit 1 = Watchdog Timer is in non-Window mode 0 = Watchdog Timer is in Window mode Reserved: Write ‘1’ bit 22 bit 21 bit 20-16 WDTPS: Watchdog Timer Postscale Select bits 10100 = 1:1048576 10011 = 1:524288 10010 = 1:262144 10001 = 1:131072 10000 = 1:65536 01111 = 1:32768 01110 = 1:16384 01101 = 1:8192 01100 = 1:4096 01011 = 1:2048 01010 = 1:1024 01001 = 1:512 01000 = 1:256 00111 = 1:128 00110 = 1:64 00101 = 1:32 00100 = 1:16 00011 = 1:8 00010 = 1:4 00001 = 1:2 00000 = 1:1 All other combinations not shown result in operation = 10100 Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source. DS61168D-page 228 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED) bit 15-14 FCKSM: Clock Switching and Monitor Selection Configuration bits 1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled bit 13-12 FPBDIV: Peripheral Bus Clock Divisor Default Value bits 11 = PBCLK is SYSCLK divided by 8 10 = PBCLK is SYSCLK divided by 4 01 = PBCLK is SYSCLK divided by 2 00 = PBCLK is SYSCLK divided by 1 bit 11 bit 10 Reserved: Write ‘1’ OSCIOFNC: CLKO Enable Configuration bit 1 = CLKO output disabled 0 = CLKO output signal active on the OSCO pin; Primary Oscillator must be disabled or configured for the External Clock mode (EC) for the CLKO to be active (POSCMOD = 11 or 00) POSCMOD: Primary Oscillator Configuration bits 11 = Primary Oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = External Clock mode selected IESO: Internal External Switchover bit 1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled) 0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled) Reserved: Write ‘1’ FSOSCEN: Secondary Oscillator Enable bit 1 = Enable Secondary Oscillator 0 = Disable Secondary Oscillator Reserved: Write ‘1’ FNOSC: Oscillator Selection bits 111 = Fast RC Oscillator with divide-by-N (FRCDIV) 110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL) 010 = Primary Oscillator (XT, HS, EC)(1) 001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL) 000 = Fast RC Oscillator (FRC) Do not disable the POSC (POSCMOD = 11) when using this oscillator source. bit 9-8 bit 7 bit 6 bit 5 bit 4-3 bit 2-0 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 229 PIC32MX1XX/2XX REGISTER 26-3: Bit Range 31:24 23:16 15:8 7:0 DEVCFG2: DEVICE CONFIGURATION WORD 2 Bit 30/22/14/6 r-1 Bit 31/23/15/7 r-1 Bit 29/21/13/5 r-1 Bit 28/20/12/4 r-1 Bit 27/19/11/3 r-1 Bit 26/18/10/2 r-1 Bit 25/17/9/1 r-1 Bit 24/16/8/0 r-1 — r-1 — r-1 — r-1 — r-1 — r-1 — R/P — R/P — R/P — R/P — r-1 — r-1 — r-1 — r-1 R/P FPLLODIV R/P R/P UPLLEN(1) r-1 — R/P-1 — R/P — R/P-1 — r-1 R/P UPLLIDIV(1) R/P R/P — FPLLMUL r = Reserved bit W = Writable bit ‘1’ = Bit is set — P = Programmable bit FPLLIDIV Legend: R = Readable bit -n = Value at POR bit 31-19 Reserved: Write ‘1’ U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 18-16 FPLLODIV: Default PLL Output Divisor bits 111 = PLL output divided by 256 110 = PLL output divided by 64 101 = PLL output divided by 32 100 = PLL output divided by 16 011 = PLL output divided by 8 010 = PLL output divided by 4 001 = PLL output divided by 2 000 = PLL output divided by 1 bit 15 UPLLEN: USB PLL Enable bit(1) 1 = Disable and bypass USB PLL 0 = Enable USB PLL UPLLIDIV: USB PLL Input Divider bits(1) 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider Reserved: Write ‘1’ FPLLMUL: PLL Multiplier bits 111 = 24x multiplier 110 = 21x multiplier 101 = 20x multiplier 100 = 19x multiplier 011 = 18x multiplier 010 = 17x multiplier 001 = 16x multiplier 000 = 15x multiplier Reserved: Write ‘1’ This bit is available on PIC32MX2XX devices only. bit 14-11 Reserved: Write ‘1’ bit 10-8 bit 7 bit 6-4 bit 3 Note 1: DS61168D-page 230 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-3: bit 2-0 DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED) FPLLIDIV: PLL Input Divider bits 111 = 12x divider 110 = 10x divider 101 = 6x divider 100 = 5x divider 011 = 4x divider 010 = 3x divider 001 = 2x divider 000 = 1x divider This bit is available on PIC32MX2XX devices only. Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 231 PIC32MX1XX/2XX REGISTER 26-4: Bit Range 31:24 23:16 15:8 7:0 DEVCFG3: DEVICE CONFIGURATION WORD 3 Bit 30/22/14/6 R/P Bit 31/23/15/7 R/P Bit 29/21/13/5 R/P Bit 28/20/12/4 R/P Bit Bit 27/19/11/3 26/18/10/2 r-1 r-1 Bit 25/17/9/1 r-1 Bit 24/16/8/0 r-1 FVBUSONIO r-1 FUSBIDIO r-1 IOL1WAY r-1 PMDL1WAY r-1 — r-1 — r-1 — r-1 — r-1 — R/P R/P — R/P R/P — R/P R/P — R/P R/P — R/P R/P — R/P R/P — R/P R/P — R/P R/P USERID USERID r = Reserved bit W = Writable bit ‘1’ = Bit is set P = Programmable bit U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown Legend: R = Readable bit -n = Value at POR bit 31 FVBUSONIO: USB VBUS_ON Selection bit 1 = VBUSON pin is controlled by the USB module 0 = VBUSON pin is controlled by the port function bit 30 FUSBIDIO: USB USBID Selection bit 1 = USBID pin is controlled by the USB module 0 = USBID pin is controlled by the port function bit 29 IOL1WAY: Peripheral Pin Select Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 28 PMDl1WAY: Peripheral Module Disable Configuration bit 1 = Allow only one reconfiguration 0 = Allow multiple reconfigurations bit 27-16 Reserved: Write ‘1’ bit 15-0 USERID: This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG DS61168D-page 232 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX REGISTER 26-5: Bit Range 31:24 23:16 15:8 7:0 CFGCON: CONFIGURATION CONTROL REGISTER Bit 29/21/13/5 U-0 Bit Bit 31/23/15/7 30/22/14/6 U-0 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R/W-0 — R/W-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 IOLOCK(1) PMDLOCK(1) U-0 U-0 — R/W-1 — U-0 — U-1 — R/W-1 — — — — JTAGEN — — TDOEN Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-14 Unimplemented: Read as ‘0’ bit 13 IOLOCK: Peripheral Pin Select Lock bit(1) 1 = Peripheral Pin Select is locked. Writes to PPS registers is not allowed. 0 = Peripheral Pin Select is not locked. Writes to PPS registers is allowed. PMDLOCK: Peripheral Module Disable bit(1) 1 = Peripheral module is locked. Writes to PMD registers is not allowed. 0 = Peripheral module is not locked. Writes to PMD registers is allowed. Unimplemented: Read as ‘0’ JTAGEN: JTAG Port Enable bit 1 = Enable the JTAG port 0 = Disable the JTAG port Unimplemented: Read as ‘1’ TDOEN: TDO Enable for 2-Wire JTAG 1 = 2-wire JTAG protocol uses TDO 0 = 2-wire JTAG protocol does not use TDO To change this bit, the unlock sequence must be performed. Refer to Section 6. “Oscillator” (DS61112) in the “PIC32 Family Reference Manual” for details. bit 12 bit 11-4 bit 3 bit 2-1 bit 0 Note 1: © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 233 PIC32MX1XX/2XX REGISTER 26-6: Bit Range 31:24 23:16 15:8 7:0 DEVID: DEVICE AND REVISION ID REGISTER Bit 30/22/14/6 R Bit 31/23/15/7 R Bit 29/21/13/5 R Bit 28/20/12/4 R Bit 27/19/11/3 R Bit 26/18/10/2 R Bit 25/17/9/1 R Bit 24/16/8/0 R VER(1) R R R R R DEVID(1) R R R DEVID(1) R R R R R R R R DEVID(1) R R R R R R R R DEVID(1) Legend: R = Readable bit -n = Value at POR W = Writable bit ‘1’ = Bit is set U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-28 VER: Revision Identifier bits(1) bit 27-0 Note 1: DEVID: Device ID(1) See the “PIC32MX Flash Programming Specification” (DS61145) for a list of Revision and Device ID values. DS61168D-page 234 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 26.2 Watchdog Timer (WDT) This section describes the operation of the WDT and Power-up Timer of the PIC32MX1XX/2XX. The WDT, when enabled, operates from the internal Low-Power Oscillator (LPRC) clock source and can be used to detect system software malfunctions by resetting the device if the WDT is not cleared periodically in software. Various WDT time-out periods can be selected using the WDT postscaler. The WDT can also be used to wake the device from Sleep or Idle mode. The following are some of the key features of the WDT module: • Configuration or software controlled • User-configurable time-out period • Can wake the device from Sleep or Idle FIGURE 26-1: WATCHDOG AND POWER-UP TIMER BLOCK DIAGRAM LPRC Control PWRT Enable 1:64 Output 1 PWRT Enable WDT Enable LPRC Oscillator Clock WDTCLR = 1 WDT Enable Wake WDT Enable Reset Event 25-bit Counter 25 WDT Counter Reset 0 1 Power Save Decoder FWDTPS (DEVCFG1) PWRT Device Reset NMI (Wake-up) © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 235 PIC32MX1XX/2XX REGISTER 26-7: Bit Range 31:24 23:16 15:8 7:0 WDTCON: WATCHDOG TIMER CONTROL REGISTER(1,2,3) Bit 30/22/14/6 U-0 Bit 31/23/15/7 U-0 Bit 29/21/13/5 U-0 Bit 28/20/12/4 U-0 Bit 27/19/11/3 U-0 Bit 26/18/10/2 U-0 Bit 25/17/9/1 U-0 Bit 24/16/8/0 U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — ON R/W-0 (1,2) U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — U-0 — R-y — R-y — R-y — R-y — R-y — R/W-0 — R/W-0 — SWDTPS y = Values set from Configuration bits on POR W = Writable bit ‘1’ = Bit is set WDTWINEN WDTCLR Legend: R = Readable bit -n = Value at POR U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared x = Bit is unknown bit 31-16 Unimplemented: Read as ‘0’ bit 15 ON: Watchdog Timer Enable bit(1,2) 1 = Enables the WDT if it is not enabled by the device configuration 0 = Disable the WDT if it was enabled in software Unimplemented: Read as ‘0’ SWDTPS: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits On reset, these bits are set to the values of the WDTPS of Configuration bits. WDTWINEN: Watchdog Timer Window Enable bit 1 = Enable windowed Watchdog Timer 0 = Disable windowed Watchdog Timer WDTCLR: Watchdog Timer Reset bit 1 = Writing a ‘1’ will clear the WDT 0 = Software cannot force this bit to a ‘0’ A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software. When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in the SYSCLK cycle immediately following the instruction that clears the module’s ON bit. bit 14-7 bit 6-2 bit 1 bit 0 Note 1: 2: DS61168D-page 236 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 26.3 On-Chip Voltage Regulator 26.4 Programming and Diagnostics All PIC32MX1XX/2XX devices’ core and digital logic are designed to operate at a nominal 1.8V. To simplify system designs, most devices in the PIC32MX1XX/2XX family incorporate an on-chip regulator providing the required core logic voltage from VDD. A low-ESR capacitor (such as tantalum) must be connected to the VCAP pin (see Figure 26-2). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor is provided in Section 29.1 “DC Characteristics”. Note: It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. PIC32MX1XX/2XX devices provide a complete range of programming and diagnostic features that can increase the flexibility of any application using them. These features allow system designers to include: • Simplified field programmability using two-wire In-Circuit Serial Programming™ (ICSP™) interfaces • Debugging using ICSP • Programming and debugging capabilities using the EJTAG extension of JTAG • JTAG boundary scan testing for device and board diagnostics PIC32 devices incorporate two programming and diagnostic modules, and a trace controller, that provide a range of functions to the application developer. 26.3.1 ON-CHIP REGULATOR AND POR FIGURE 26-3: BLOCK DIAGRAM OF PROGRAMMING, DEBUGGING AND TRACE PORTS It takes a fixed delay for the on-chip regulator to generate an output. During this time, designated as TPU, code execution is disabled. TPU is applied every time the device resumes operation after any power-down, including Sleep mode. 26.3.2 ON-CHIP REGULATOR AND BOR PGEC1 PGED1 ICSP™ Controller PGEC4 PGED4 Core ICESEL TDI TDO TCK JTAG Controller PIC32MX1XX/2XX devices also have a simple brownout capability. If the voltage supplied to the regulator is inadequate to maintain a regulated level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON). The brown-out voltage levels are specific in Section 29.1 “DC Characteristics”. FIGURE 26-2: CONNECTIONS FOR THE ON-CHIP REGULATOR 3.3V(1) PIC32 VDD TMS JTAGEN DEBUG VCAP CEFC(2,3) (10 μF typ) Note 1: VSS 2: 3: These are typical operating voltages. Refer to Section 29.1 “DC Characteristics” for the full operating ranges of VDD. It is important that the low-ESR capacitor is placed as close as possible to the VCAP pin. The typical voltage on the VCAP pin is 1.8V. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 237 PIC32MX1XX/2XX NOTES: DS61168D-page 238 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 27.0 INSTRUCTION SET The PIC32MX1XX/2XX family instruction set complies with the MIPS32® Release 2 instruction set architecture. The PIC32 device family does not support the following features: • Core extend instructions • Coprocessor 1 instructions • Coprocessor 2 instructions Note: Refer to “MIPS32® Architecture for Programmers Volume II: The MIPS32® Instruction Set” at www.mips.com for more information. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 239 PIC32MX1XX/2XX NOTES: DS61168D-page 240 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 28.0 DEVELOPMENT SUPPORT 28.1 The PIC® microcontrollers and dsPIC® digital signal controllers are supported with a full range of software and hardware development tools: • Integrated Development Environment - MPLAB® IDE Software • Compilers/Assemblers/Linkers - MPLAB C Compiler for Various Device Families - HI-TECH C® for Various Device Families - MPASMTM Assembler - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB Assembler/Linker/Librarian for Various Device Families • Simulators - MPLAB SIM Software Simulator • Emulators - MPLAB REAL ICE™ In-Circuit Emulator • In-Circuit Debuggers - MPLAB ICD 3 - PICkit™ 3 Debug Express • Device Programmers - PICkit™ 2 Programmer - MPLAB PM3 Device Programmer • Low-Cost Demonstration/Development Boards, Evaluation Kits, and Starter Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16/32-bit microcontroller market. The MPLAB IDE is a Windows® operating system-based application that contains: • A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - In-Circuit Emulator (sold separately) - In-Circuit Debugger (sold separately) • A full-featured editor with color-coded context • A multiple project manager • Customizable data windows with direct edit of contents • High-level source code debugging • Mouse over variable inspection • Drag and drop variables from source to watch windows • Extensive on-line help • Integration of select third party tools, such as IAR C Compilers The MPLAB IDE allows you to: • Edit your source files (either C or assembly) • One-touch compile or assemble, and download to emulator and simulator tools (automatically updates all project information) • Debug using: - Source files (C or assembly) - Mixed C and assembly - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 241 PIC32MX1XX/2XX 28.2 MPLAB C Compilers for Various Device Families 28.5 MPLINK Object Linker/ MPLIB Object Librarian The MPLAB C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC18, PIC24 and PIC32 families of microcontrollers and the dsPIC30 and dsPIC33 families of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: • Efficient linking of single libraries instead of many smaller files • Enhanced code maintainability by grouping related modules together • Flexible creation of libraries with easy module listing, replacement, deletion and extraction 28.3 HI-TECH C for Various Device Families The HI-TECH C Compiler code development systems are complete ANSI C compilers for Microchip’s PIC family of microcontrollers and the dsPIC family of digital signal controllers. These compilers provide powerful integration capabilities, omniscient code generation and ease of use. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. The compilers include a macro assembler, linker, preprocessor, and one-step driver, and can run on multiple platforms. 28.6 MPLAB Assembler, Linker and Librarian for Various Device Families 28.4 MPASM Assembler The MPASM Assembler is a full-featured, universal macro assembler for PIC10/12/16/18 MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel® standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: • Integration into MPLAB IDE projects • User-defined macros to streamline assembly code • Conditional assembly for multi-purpose source files • Directives that allow complete control over the assembly process MPLAB Assembler produces relocatable machine code from symbolic assembly language for PIC24, PIC32 and dsPIC devices. MPLAB C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: • • • • • • Support for the entire device instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility DS61168D-page 242 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 28.7 MPLAB SIM Software Simulator 28.9 The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC® DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C Compilers, and the MPASM and MPLAB Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. MPLAB ICD 3 In-Circuit Debugger System MPLAB ICD 3 In-Circuit Debugger System is Microchip's most cost effective high-speed hardware debugger/programmer for Microchip Flash Digital Signal Controller (DSC) and microcontroller (MCU) devices. It debugs and programs PIC® Flash microcontrollers and dsPIC® DSCs with the powerful, yet easyto-use graphical user interface of MPLAB Integrated Development Environment (IDE). The MPLAB ICD 3 In-Circuit Debugger probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with a connector compatible with the MPLAB ICD 2 or MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3 supports all MPLAB ICD 2 headers. 28.8 MPLAB REAL ICE In-Circuit Emulator System 28.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express The MPLAB PICkit 3 allows debugging and programming of PIC® and dsPIC® Flash microcontrollers at a most affordable price point using the powerful graphical user interface of the MPLAB Integrated Development Environment (IDE). The MPLAB PICkit 3 is connected to the design engineer's PC using a full speed USB interface and can be connected to the target via an Microchip debug (RJ-11) connector (compatible with MPLAB ICD 3 and MPLAB REAL ICE). The connector uses two device I/O pins and the reset line to implement in-circuit debugging and In-Circuit Serial Programming™. The PICkit 3 Debug Express include the PICkit 3, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. MPLAB REAL ICE In-Circuit Emulator System is Microchip’s next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC® Flash MCUs and dsPIC® Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The emulator is connected to the design engineer’s PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with incircuit debugger systems (RJ11) or with the new highspeed, noise tolerant, Low-Voltage Differential Signal (LVDS) interconnection (CAT5). The emulator is field upgradable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, run-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 243 PIC32MX1XX/2XX 28.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express The PICkit™ 2 Development Programmer/Debugger is a low-cost development tool with an easy to use interface for programming and debugging Microchip’s Flash families of microcontrollers. The full featured Windows® programming interface supports baseline (PIC10F, PIC12F5xx, PIC16F5xx), midrange (PIC12F6xx, PIC16F), PIC18F, PIC24, dsPIC30, dsPIC33, and PIC32 families of 8-bit, 16-bit, and 32-bit microcontrollers, and many Microchip Serial EEPROM products. With Microchip’s powerful MPLAB Integrated Development Environment (IDE) the PICkit™ 2 enables in-circuit debugging on most PIC® microcontrollers. In-Circuit-Debugging runs, halts and single steps the program while the PIC microcontroller is embedded in the application. When halted at a breakpoint, the file registers can be examined and modified. The PICkit 2 Debug Express include the PICkit 2, demo board and microcontroller, hookup cables and CDROM with user’s guide, lessons, tutorial, compiler and MPLAB IDE software. 28.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEM™ and dsPICDEM™ demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ® security ICs, CAN, IrDA®, PowerSmart battery management, SEEVAL® evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Also available are starter kits that contain everything needed to experience the specified device. This usually includes a single application and debug capability, all on one board. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. 28.12 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSP™ cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an MMC card for file storage and data applications. DS61168D-page 244 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX 29.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC32MX1XX/2XX electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC32MX1XX/2XX devices are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these or any other conditions, above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings(1) Ambient temperature under bias.............................................................................................................-40°C to +105°C Storage temperature .............................................................................................................................. -65°C to +150°C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3) ......................................... -0.3V to (VDD + 0.3V) Voltage on any 5V tolerant pin with respect to VSS when VDD ≥ 2.3V (Note 3) ........................................ -0.3V to +5.5V Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3) ........................................ -0.3V to +3.6V Voltage on D+ or D- pin with respect to VUSB3V3 ..................................................................... -0.3V to (VUSB3V3 + 0.3V) Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V Maximum current out of VSS pin(s) .......................................................................................................................300 mA Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA Maximum output current sunk by any I/O pin..........................................................................................................15 mA Maximum output current sourced by any I/O pin ....................................................................................................15 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 2) ....................................................................................................200 mA Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions, above those indicated in the operation listings of this specification, is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2: Maximum allowable current is a function of device maximum power dissipation (see Table 29-2). 3: See the “Pin Diagrams” section for the 5V tolerant pins. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 245 PIC32MX1XX/2XX 29.1 DC Characteristics OPERATING MIPS VS. VOLTAGE VDD Range (in Volts) 2.3-3.6V 2.3-3.6V Temp. Range (in °C) -40°C to +85°C -40°C to +105°C Max. Frequency PIC32MX1XX/2XX 40 MHz 40 MHz TABLE 29-1: Characteristic DC5 DC5b TABLE 29-2: THERMAL OPERATING CONDITIONS Rating Symbol TJ TA TJ TA Min. -40 -40 -40 -40 Typical — — — — Max. +125 +85 +140 +105 Unit °C °C °C °C Industrial Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range V-temp Temperature Devices Operating Junction Temperature Range Operating Ambient Temperature Range Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD – S IOH) I/O Pin Power Dissipation: I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL)) Maximum Allowed Power Dissipation PD PINT + PI/O W PDMAX (TJ – TA)/θJA W TABLE 29-3: THERMAL PACKAGING CHARACTERISTICS Characteristics Symbol Typical θJA θJA θJA θJA θJA θJA θJA θJA 71 50 42 35 31 32 45 30 Max. — — — — — — — — Unit °C/W °C/W °C/W °C/W °C/W °C/W °C/W °C/W Notes 1 1 1 1 1 1 1 1 Package Thermal Resistance, 28-pin SSOP Package Thermal Resistance, 28-pin SOIC Package Thermal Resistance, 28-pin SPDIP Package Thermal Resistance, 28-pin QFN Package Thermal Resistance, 36-pin VTLA Package Thermal Resistance, 44-pin QFN Package Thermal Resistance, 44-pin TQFP Package Thermal Resistance, 44-pin VTLA Note 1: Junction to ambient thermal resistance, Theta-JA (θ JA) numbers are achieved by package simulations. DS61168D-page 246 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Min. Typical Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. Operating Voltage DC10 DC12 DC16 VDD VDR VPOR Supply Voltage RAM Data Retention Voltage (Note 1) VDD Start Voltage to Ensure Internal Power-on Reset Signal VDD Rise Rate to Ensure Internal Power-on Reset Signal 2.3 1.75 1.75 — — — 3.6 — 2.1 V V V — — — DC17 SVDD 0.00005 — 0.115 V/μs — Note 1: This is the limit to which VDD can be lowered without losing RAM data. TABLE 29-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Max. Units Conditions DC CHARACTERISTICS Parameter No. DC20 DC21 DC22 DC23 DC24 DC25 Note 1: Typical(3) Operating Current (IDD)(1,2) 2 7 10 15 20 100 3 10.5 15 23 30 150 mA mA mA mA mA µA +25ºC, 3.3V 4 MHz (Note 4) 10 MHz 20 MHz (Note 4) 30 MHz (Note 4) 40 MHz LPRC (32 kHz) (Note 4) 2: 3: 4: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors, such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate, oscillator type, as well as temperature, can have an impact on the current consumption. The test conditions for IDD measurements are as follows: Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by external square wave from rail-to-rail. CPU, Program Flash and SRAM data memory are operational. All peripheral modules are disabled (ON bit = 0) but the associated PMD bit is cleared. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 247 PIC32MX1XX/2XX TABLE 29-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Max. Units Conditions DC CHARACTERISTICS Parameter No. DC30a DC31a DC32a DC33a DC34a DC37a DC37b DC37c Note 1: Typical(2) Idle Current (IIDLE): Core Off, Clock on Base Current (Note 1) 1 2 4 5.5 7.5 100 250 380 1.5 3 6 8 11 — — — mA mA mA mA mA µA µA µA -40°C +25°C +85°C 3.3V 4 MHz (Note 3) 10 MHz 20 MHz (Note 3) 30 MHz (Note 3) 40 MHz LPRC (31 kHz) (Note 3) 2: 3: The test conditions for base IDLE current measurements are as follows: System clock is enabled and PBCLK divisor = 1:1. CPU in Idle mode (CPU core Halted). All peripheral modules are disabled (ON bit = 0), but the associated PMD bit is cleared. WDT and FSCM are disabled. All I/O pins are configured as inputs and pulled to VSS. MCLR = VDD. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. This parameter is characterized, but not tested in manufacturing. DS61168D-page 248 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Units Conditions DC CHARACTERISTICS Param. Typical(2) No. DC40k DC40l DC40n DC40m DC41e DC42e DC43d Note 1: 2: 3: 4: 10 44 168 335 5 23 1000 Max. Power-Down Current (IPD) (Note 1) 16 70 259 536 20 50 1100 μA μA μA µA μA μA μA -40°C +25°C +85°C +105ºC 3.6V 3.6V 3.6V Watchdog Timer Current: ΔIWDT (Note 3) RTCC + Timer1 w/32 kHz Crystal: ΔIRTCC (Note 3) ADC: ΔIADC (Notes 3,4) Base Power-Down Current Module Differential Current Base IPD is measured with all peripheral modules and clocks shut down (ON = 0, PMDx = 1), CPU clock is disabled. All I/Os are configured as inputs and pulled low. WDT and FSCM are disabled. Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The Δ current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 249 PIC32MX1XX/2XX TABLE 29-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. Typical(1) Max. Units Conditions DC CHARACTERISTICS Param. Symbol No. VIL DI10 DI18 DI19 VIH DI20 Characteristics Input Low Voltage I/O Pins with PMP I/O Pins SDAx, SCLx SDAx, SCLx Input High Voltage I/O Pins not 5V-tolerant(5) I/O Pins 5V-tolerant with PMP(5) I/O Pins 5V-tolerant(5) VSS VSS VSS VSS — — — — 0.15 VDD 0.2 VDD 0.3 VDD 0.8 V V V V SMBus disabled (Note 4) SMBus enabled (Note 4) (Note 4) (Note 4) 0.65 VDD 0.25 VDD + 0.8V 0.65 VDD 0.65 VDD 2.1 — — — — — VDD 5.5 5.5 5.5 5.5 V V V V V DI28 DI29 SDAx, SCLx SDAx, SCLx SMBus disabled (Note 4) SMBus enabled, 2.3V ≤VPIN ≤5.5 (Note 4) VDD = 3.3V, VPIN = VSS VDD = 3.3V, VPIN = VDD DI30 DI31 ICNPU ICNPD IIL Change Notification Pull-up Current Change Notification Pull-down Current(4) Input Leakage Current (Note 3) I/O Ports Analog Input Pins MCLR(2) OSC1 50 — 250 50 400 — μA µA DI50 DI51 DI55 DI56 Note 1: 2: — — — — — — — — +1 +1 +1 +1 μA μA μA μA VSS ≤VPIN ≤VDD, Pin at high-impedance VSS ≤VPIN ≤VDD, Pin at high-impedance VSS ≤VPIN ≤VDD VSS ≤VPIN ≤VDD, XT and HS modes 3: 4: 5: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. This parameter is characterized, but not tested in manufacturing. See the “Pin Diagrams” section for the 5V-tolerant pins. DS61168D-page 250 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +105°C for V-temp Characteristic Output Low Voltage DO10 VOL I/O Pins Output High Voltage DO20 VOH I/O Pins 1.5(1) 2.0(1) 2.4 3.0(1) Note 1: Parameters are characterized, but not tested. — — — — — — — — V IOH ≥ -14 mA, VDD = 3.3V IOH ≥ -12 mA, VDD = 3.3V IOH ≥ -10 mA, VDD = 3.3V IOH ≥ -7 mA, VDD = 3.3V — — 0.4 V IOL ≤10 mA, VDD = 3.3V Min. Typ. Max. Units Conditions DC CHARACTERISTICS Param. Symbol TABLE 29-10: ELECTRICAL CHARACTERISTICS: BOR DC CHARACTERISTICS Param. Symbol No. BO10 Note 1: VBOR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics BOR Event on VDD transition high-to-low Min.(1) Typical 2.0 — Max. 2.3 Units V Conditions — Parameters are for design guidance only and are not tested in manufacturing. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 251 PIC32MX1XX/2XX TABLE 29-11: DC CHARACTERISTICS: PROGRAM MEMORY(3) DC CHARACTERISTICS Param. Symbol No. D130 D131 D132 D134 D135 EP VPR VPEW TRETD IDDP TWW D136 TRW Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. Typical(1) Max. Units Conditions Characteristics Program Flash Memory Cell Endurance VDD for Read VDD for Erase or Write Characteristic Retention Supply Current during Programming Word Write Cycle Time Row Write Cycle Time (Note 2) (128 words per row) Page Erase Cycle Time Chip Erase Cycle Time 20,000 2.3 2.3 20 — 20 3 — — — — 10 — 4.5 — 3.6 3.6 — — 40 — E/W V V — — — Year Provided no other specifications are violated mA µs ms — — — D137 Note 1: 2: TPE TCE 20 80 — — — — ms ms — — 3: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default Arbitration mode is mode 1 (CPU has lowest priority). Refer to the “PIC32 Flash Programming Specification” (DS61145) for operating conditions during programming and erase cycles. DS61168D-page 252 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-12: COMPARATOR SPECIFICATIONS DC CHARACTERISTICS Param. Symbol No. D300 D301 VIOFF VICM Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Input Offset Voltage Input Common Mode Voltage Min. — 0 Typical ±7.5 — Max. ±25 VDD Units mV V Comments AVDD = VDD, AVSS = VSS AVDD = VDD, AVSS = VSS (Note 2) Max VICM = (VDD - 1)V (Note 2) AVDD = VDD, AVSS = VSS (Notes 1,2) Comparator module is configured before setting the comparator ON bit (Note 2) BGSEL = 00 — D302 D303 CMRR TRESP Common Mode Rejection Ratio Response Time 55 — — 150 — 400 dB ns D304 ON2OV Comparator Enabled to Output Valid — — 10 μs D305 D312 Note 1: 2: 3: IVREF TSET Internal Voltage Reference Internal Voltage Reference Setting time (Note 3) 1.14 — 1.2 — 1.26 10 V µs Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions from VSS to VDD. These parameters are characterized but not tested. Settling time measured while CVRR = 1 and CVR transitions from ‘0000’ to ‘1111’. This parameter is characterized, but not tested in manufacturing. TABLE 29-13: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS DC CHARACTERISTICS Param. No. D321 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics External Filter Capacitor Value Min. 8 Typical 10 Max. — Units μF Comments Capacitor must be low series resistance (1 ohm). Typical voltage on the VCAP pin is 1.8V. Symbol CEFC © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 253 PIC32MX1XX/2XX 29.2 AC Characteristics and Timing Parameters The information contained in this section defines PIC32MX1XX/2XX AC characteristics and timing parameters. FIGURE 29-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 2 – for OSC2 Load Condition 1 – for all pins except OSC2 VDD/2 RL Pin VSS CL Pin VSS CL RL = 464Ω CL = 50 pF for all pins 50 pF for OSC2 pin (EC mode) TABLE 29-14: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS AC CHARACTERISTICS Param. Symbol No. DO56 DO58 Note 1: CIO CB Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. — — Typical(1) — — Max. 50 400 Units pF pF EC mode In I2C™ mode Conditions Characteristics All I/O pins and OSC2 SCLx, SDAx Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-2: EXTERNAL CLOCK TIMING OS20 OS30 OS31 OSC1 OS30 OS31 DS61168D-page 254 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-15: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. OS10 FOSC Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics External CLKI Frequency (External clocks allowed only in EC and ECPLL modes) Oscillator Crystal Frequency Min. DC 4 3 4 10 10 32 TOSC TOSC = 1/FOSC = TCY (Note 2) — Typical(1) — — — — — — 32.768 — Max. 40 40 10 10 25 25 100 — Units MHz MHz MHz MHz MHz MHz kHz — Conditions EC (Note 4) ECPLL (Note 3) XT (Note 4) XTPLL (Notes 3,4) HS (Note 5) HSPLL (Notes 3,4) SOSC (Note 4) See parameter OS10 for FOSC value EC (Note 4) EC (Note 4) (Note 4) OS11 OS12 OS13 OS14 OS15 OS20 OS30 OS31 OS40 TOSL, TOSH TOSR, TOSF TOST External Clock In (OSC1) High or Low Time External Clock In (OSC1) Rise or Fall Time Oscillator Start-up Timer Period (Only applies to HS, HSPLL, XT, XTPLL and SOSC Clock Oscillator modes) Primary Clock Fail Safe Time-out Period External Oscillator Transconductance 0.45 x TOSC — — — — 1024 — 0.05 x TOSC — ns ns TOSC OS41 OS42 TFSCM GM — — 2 12 — — ms (Note 4) mA/V VDD = 3.3V, TA = +25°C (Note 4) Note 1: 2: 3: 4: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not tested. Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at “min.” values with an external clock applied to the OSC1/CLKI pin. PLL input requirements: 4 MHZ ≤FPLLIN ≤5 MHZ (use PLL prescaler to reduce FOSC). This parameter is characterized, but tested at 10 MHz only at manufacturing. This parameter is characterized, but not tested in manufacturing. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 255 PIC32MX1XX/2XX TABLE 29-16: PLL CLOCK TIMING SPECIFICATIONS AC CHARACTERISTICS Param. Symbol No. OS50 FPLLI Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) PLL Voltage Controlled Oscillator (VCO) Input Frequency Range On-Chip VCO System Frequency PLL Start-up Time (Lock Time) CLKO Stability (Period Jitter or Cumulative) (2) Min. 3.92 Typical — Max. 5 Units MHz Conditions ECPLL, HSPLL, XTPLL, FRCPLL modes — — Measured over 100 ms period OS51 OS52 OS53 Note 1: 2: FSYS TLOCK DCLK 60 — -0.25 — — — 120 2 +0.25 MHz ms % These parameters are characterized, but not tested in manufacturing. This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for individual time-bases on communication clocks, use the following formula: D CLK EffectiveJitter = -------------------------------------------------------------SYSCLK --------------------------------------------------------CommunicationClock For example, if SYSCLK = 40 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows: D CLK D CLK EffectiveJitter = ------------- = ------------1.41 40 ----20 TABLE 29-17: INTERNAL FRC ACCURACY Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. Typical Max. Units Conditions AC CHARACTERISTICS Param. No. F20b Note 1: FRC Characteristics Internal FRC Accuracy @ 8.00 MHz(1) -0.9 — +0.9 % — Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift. TABLE 29-18: INTERNAL LPRC ACCURACY AC CHARACTERISTICS Param. No. F21 Note 1: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. Typical Max. Units Conditions Characteristics LPRC @ 31.25 kHz(1) LPRC -15 — +15 % — Change of LPRC frequency as VDD changes. DS61168D-page 256 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-3: I/O Pin (Input) DI35 DI40 I/O Pin (Output) Note: Refer to Figure 29-1 for load conditions. DO31 DO32 I/O TIMING CHARACTERISTICS TABLE 29-19: I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. DO31 DO32 DI35 DI40 Note 1: 2: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(2) Port Output Rise Time Port Output Fall Time INTx Pin High or Low Time CNx High or Low Time (input) Min. — — TIOF TINP TRBP — — 10 2 Typical(1) 5 5 5 5 — — Max. 15 10 15 10 — — Units ns ns ns ns ns TSYSCLK Conditions VDD < 2.5V VDD > 2.5V VDD < 2.5V VDD > 2.5V — — Symbol TIOR Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. This parameter is characterized, but not tested in manufacturing. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 257 PIC32MX1XX/2XX FIGURE 29-4: POWER-ON RESET TIMING CHARACTERISTICS Internal Voltage Regulator Enabled Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) CPU Starts Fetching Code Internal Voltage Regulator Enabled Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) VDD VPOR (TSYSDLY) SY02 Power-up Sequence (Note 2) SY00 (TPU) (Note 1) Note 1: 2: SY10 (TOST) CPU Starts Fetching Code The power-up period will be extended if the power-up sequence completes before the device exits from BOR (VDD < VDDMIN). Includes interval voltage regulator stabilization delay. DS61168D-page 258 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-5: EXTERNAL RESET TIMING CHARACTERISTICS Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC) MCLR TMCLR (SY20) BOR TBOR (SY30) Reset Sequence (TSYSDLY) SY02 CPU Starts Fetching Code Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) Reset Sequence (TSYSDLY) SY02 TOST (SY10) CPU Starts Fetching Code TABLE 29-20: RESETS TIMING AC CHARACTERISTICS Param. Symbol No. SY00 SY02 TPU Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) Power-up Period Internal Voltage Regulator Enabled Min. — — Typical(2) 400 1 μs + 8 SYSCLK cycles Max. 600 — Units μs — Conditions — — TSYSDLY System Delay Period: Time Required to Reload Device Configuration Fuses plus SYSCLK Delay before First instruction is Fetched. TMCLR TBOR MCLR Pulse Width (low) BOR Pulse Width (low) SY20 SY30 Note 1: 2: 2 — — 1 — — μs μs — — These parameters are characterized, but not tested in manufacturing. Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 259 PIC32MX1XX/2XX FIGURE 29-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS TxCK Tx10 Tx15 OS60 TMRx Tx11 Tx20 Note: Refer to Figure 29-1 for load conditions. TABLE 29-21: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1) AC CHARACTERISTICS Param. No. TA10 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(2) TxCK High Time Synchronous, with prescaler Asynchronous, with prescaler TA11 TTXL TxCK Low Time Synchronous, with prescaler Asynchronous, with prescaler TA15 TTXP TxCK Synchronous, Input Period with prescaler Min. [(12.5 ns or 1 TPB)/N] + 25 ns 10 [(12.5 ns or 1 TPB)/N] + 25 ns 10 [(Greater of 25 ns or 2 TPB)/N] + 30 ns [(Greater of 25 ns or 2 TPB)/N] + 50 ns Asynchronous, with prescaler 20 50 OS60 FT1 SOSC1/T1CK Oscillator Input Frequency Range (oscillator enabled by setting TCS bit (T1CON)) 32 Typical Max. Units — — — — — — — — — — — — — — — — — 100 ns ns ns ns ns ns ns ns kHz Conditions Must also meet parameter TA15 — Must also meet parameter TA15 — VDD > 2.7V VDD < 2.7V VDD > 2.7V (Note 3) VDD < 2.7V (Note 3) — Symbol TTXH TA20 TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment — 1 TPB — Note 1: 2: 3: Timer1 is a Type A. This parameter is characterized, but not tested in manufacturing. N = Prescale Value (1, 8, 64, 256). DS61168D-page 260 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-22: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. TB10 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) TxCK Synchronous, with High Time prescaler TxCK Synchronous, with Low Time prescaler TxCK Input Period Synchronous, with prescaler Min. [(12.5 ns or 1 TPB)/N] + 25 ns [(12.5 ns or 1 TPB)/N] + 25 ns [(Greater of [(25 ns or 2 TPB)/N] + 30 ns [(Greater of [(25 ns or 2 TPB)/N] + 50 ns — Max. Units — ns Conditions Must also meet N = prescale parameter value TB15 (1, 2, 4, 8, Must also meet 16, 32, 64, 256) parameter TB15 TB15 TTXP — — 1 ns ns TPB VDD > 2.7V VDD < 2.7V — Symbol TTXH TB11 TTXL — ns TB20 Note 1: TCKEXTMRL Delay from External TxCK Clock Edge to Timer Increment These parameters are characterized, but not tested in manufacturing. FIGURE 29-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS ICx IC10 IC15 Note: Refer to Figure 29-1 for load conditions. IC11 TABLE 29-23: INPUT CAPTURE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. IC10 TCCL Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. [(12.5 ns or 1 TPB)/N] + 25 ns Max. — Units ns Conditions Must also meet parameter IC15. Must also meet parameter IC15. — N = prescale value (1, 4, 16) Characteristics(1) ICx Input Low Time IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] + 25 ns — ns IC15 Note 1: TCCP ICx Input Period [(25 ns or 2 TPB)/N] + 50 ns — ns These parameters are characterized, but not tested in manufacturing. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 261 PIC32MX1XX/2XX FIGURE 29-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS (Output Compare or PWM mode) OCx OC11 OC10 Note: Refer to Figure 29-1 for load conditions. TABLE 29-24: OUTPUT COMPARE MODULE TIMING REQUIREMENTS AC CHARACTERISTICS Param. Symbol No. OC10 OC11 Note 1: 2: TCCF TCCR Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. — — Typical(2) — — Max. — — Units ns ns Conditions See parameter DO32 See parameter DO31 Characteristics(1) OCx Output Fall Time OCx Output Rise Time These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. FIGURE 29-9: OCx/PWM MODULE TIMING CHARACTERISTICS OC20 OCFA/OCFB OC15 OCx Note: Refer to Figure 29-1 for load conditions. OCx is tri-stated TABLE 29-25: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS AC CHARACTERISTICS Param No. OC15 OC20 Note 1: 2: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) Fault Input to PWM I/O Change Fault Input Pulse Width Min — 50 Typical(2) — — Max 50 — Units ns ns Conditions — — Symbol TFD TFLT These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. DS61168D-page 262 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-10: SCKx (CKP = 0) SP11 SCKx (CKP = 1) SP35 SP20 MSb SP31 SDIx MSb In SP40 SP41 Note: Refer to Figure 29-1 for load conditions. Bit 14 - - - -1 Bit 14 - - - - - -1 SP30 LSb In SP21 LSb SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS SDOx TABLE 29-26: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP40 SP41 Note 1: 2: 3: 4: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) Min. TSCK/2 TSCK/2 — — — — — — 10 10 Typical(2) Max. — — — — — — — — — — — — — — — — 15 20 — — Units ns ns ns ns ns ns ns ns ns ns Conditions — — See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V — — Symbol TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 263 PIC32MX1XX/2XX FIGURE 29-11: SCKX (CKP = 0) SP11 SCKX (CKP = 1) SP10 SP21 SP20 SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS SP36 SP35 SP20 SP21 SDOX MSb Bit 14 - - - - - -1 SP30,SP31 LSb SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In Note: Refer to Figure 29-1 for load conditions. TABLE 29-27: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. SP10 SP11 SP20 SP21 SP30 SP31 SP35 SP36 SP40 SP41 Note 1: 2: 3: 4: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) SCKx Output Low Time (Note 3) SCKx Output High Time (Note 3) SCKx Output Fall Time (Note 4) SCKx Output Rise Time (Note 4) SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) Min. TSCK/2 TSCK/2 — — — — — — 15 15 20 15 20 Typ.(2) — — — — — — — — — — — — — Max. — — — — — — 15 20 — — — — — Units ns ns ns ns ns ns ns ns ns ns ns ns ns Conditions — — See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V — VDD > 2.7V VDD < 2.7V VDD > 2.7V VDD < 2.7V Symbol TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDOV2SC, SDOx Data Output Setup to TDOV2SCL First SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input to TDIV2SCL SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Therefore, the clock generated in Master mode must not violate this specification. Assumes 50 pF load on all SPIx pins. DS61168D-page 264 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-12: SSX SP50 SCKX (CKP = 0) SP71 SCKX (CKP = 1) SP35 SDOX MSb SP72 Bit 14 - - - - - -1 SP30,SP31 SDIX SP40 MSb In SP41 Bit 14 - - - -1 LSb In SP73 LSb SP51 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS Note: Refer to Figure 29-1 for load conditions. TABLE 29-28: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 SP51 SP52 Note 1: 2: 3: 4: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) SDOx Data Output Valid after SCKx Edge Setup Time of SDIx Data Input to SCKx Edge Hold Time of SDIx Data Input to SCKx Edge Min. TSCK/2 TSCK/2 — — — — — — 10 10 175 5 Typ.(2) — — — — — — — — — — — — Max. — — — — — — 15 20 — — — 25 Units ns ns ns ns ns ns ns ns ns ns ns ns Conditions — — See parameter DO32 See parameter DO31 See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V — — — — Symbol TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, TSCL2DOV TDIV2SCH, TDIV2SCL TSCH2DIL, TSCL2DIL TSSL2SCH, SSx ↓ to SCKx ↑ or SCKx Input TSSL2SCL TSSH2DOZ SSx ↑ to SDOx Output High-Impedance (Note 3) TSCH2SSH SSx after SCKx Edge TSCK + 20 — — ns — TSCL2SSH These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 265 PIC32MX1XX/2XX FIGURE 29-13: SSx SP50 SCKx (CKP = 0) SP71 SCKx (CKP = 1) SP35 SP72 SDOx MSb Bit 14 - - - - - -1 SP30,SP31 SDIx SDI SP40 MSb In SP41 Bit 14 - - - -1 LSb In LSb SP51 SP73 SP70 SP73 SP72 SP52 SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS SP60 Note: Refer to Figure 29-1 for load conditions. TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS AC CHARACTERISTICS Param. No. SP70 SP71 SP72 SP73 SP30 SP31 SP35 SP40 SP41 SP50 Note 1: 2: 3: 4: Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) SCKx Input Low Time (Note 3) SCKx Input High Time (Note 3) SCKx Input Fall Time SCKx Input Rise Time SDOx Data Output Fall Time (Note 4) SDOx Data Output Rise Time (Note 4) Min. TSCK/2 TSCK/2 — — — — — — 10 10 175 Typical(2) — — 5 5 — — — — — — — Max. — — 10 10 — — 20 30 — — — Units ns ns ns ns ns ns ns ns ns ns ns Conditions — — — — See parameter DO32 See parameter DO31 VDD > 2.7V VDD < 2.7V — — — Symbol TSCL TSCH TSCF TSCR TDOF TDOR TSCH2DOV, SDOx Data Output Valid after TSCL2DOV SCKx Edge TDIV2SCH, Setup Time of SDIx Data Input TDIV2SCL to SCKx Edge TSCH2DIL, TSCL2DIL Hold Time of SDIx Data Input to SCKx Edge TSSL2SCH, SSx ↓ to SCKx ↓ or SCKx ↑ Input TSSL2SCL These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. DS61168D-page 266 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-29: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Param. No. SP51 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics(1) Min. 5 Typical(2) — Max. 25 Units ns Conditions — Symbol TSSH2DOZ SSx ↑ to SDOX Output High-Impedance (Note 4) TSCH2SSH SSx ↑ after SCKx Edge TSCL2SSH TSSL2DOV SDOx Data Output Valid after SSx Edge SP52 SP60 Note 1: 2: 3: 4: TSCK + 20 — — — — 25 ns ns — — These parameters are characterized, but not tested in manufacturing. Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. The minimum clock period for SCKx is 50 ns. Assumes 50 pF load on all SPIx pins. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 267 PIC32MX1XX/2XX FIGURE 29-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) SCLx IM31 IM30 SDAx IM33 IM34 Start Condition Note: Refer to Figure 29-1 for load conditions. Stop Condition FIGURE 29-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE) IM20 IM11 IM10 IM11 IM26 IM21 SCLx IM10 IM25 IM33 SDAx In IM40 IM40 IM45 SDAx Out Note: Refer to Figure 29-1 for load conditions. DS61168D-page 268 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) AC CHARACTERISTICS Param. Symbol No. IM10 Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Min.(1) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) — 20 + 0.1 CB — — 20 + 0.1 CB — 250 100 100 0 0 0 TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) TPB * (BRG + 2) Max. — — — — — — 300 300 100 1000 300 300 — — — — 0.9 0.3 — — — — — — — — — — — — Units μs μs μs μs μs μs ns ns ns ns ns ns ns ns ns μs μs μs μs μs μs μs μs μs μs μs μs ns ns ns — Only relevant for Repeated Start condition After this period, the first clock pulse is generated — — — CB is specified to be from 10 to 400 pF Conditions — — — — — — CB is specified to be from 10 to 400 pF TLO:SCL Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM20 TF:SCL SDAx and SCLx 100 kHz mode Fall Time 400 kHz mode 1 MHz mode (Note 2) IM21 TR:SCL SDAx and SCLx 100 kHz mode Rise Time 400 kHz mode 1 MHz mode (Note 2) IM25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM26 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM31 THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM34 THD:STO Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) Note 1: 2: 3: BRG is the value of the I2C™ Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 269 PIC32MX1XX/2XX TABLE 29-30: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE) (CONTINUED) AC CHARACTERISTICS Param. Symbol No. IM40 TAA:SCL Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Output Valid from Clock 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 2) IM50 IM51 Note 1: 2: 3: CB TPGD Bus Capacitive Loading Pulse Gobbler Delay Min.(1) — — — 4.7 1.3 0.5 — 52 Max. 3500 1000 350 — — — 400 312 Units ns ns ns μs μs μs pF ns Conditions — — — The amount of time the bus must be free before a new transmission can start — See Note 3 BRG is the value of the I2C™ Baud Rate Generator. Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). The typical value for this parameter is 104 ns. DS61168D-page 270 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX FIGURE 29-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE) SCLx IS31 IS30 SDAx IS33 IS34 Start Condition Note: Refer to Figure 29-1 for load conditions. Stop Condition FIGURE 29-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE) IS20 IS11 IS10 IS30 IS26 IS21 SCLx IS31 IS25 IS33 SDAx In IS40 IS40 IS45 SDAx Out Note: Refer to Figure 29-1 for load conditions. © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 271 PIC32MX1XX/2XX TABLE 29-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Clock Low Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS11 THI:SCL Clock High Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS20 TF:SCL SDAx and SCLx Fall Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS21 TR:SCL SDAx and SCLx Rise Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS25 TSU:DAT Data Input Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS26 THD:DAT Data Input Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS30 TSU:STA Start Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS31 THD:STA Start Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS33 TSU:STO Stop Condition Setup Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) Note 1: Min. 4.7 1.3 0.5 4.0 0.6 0.5 — 20 + 0.1 CB — — 20 + 0.1 CB — 250 100 100 0 0 0 4700 600 250 4000 600 250 4000 600 600 Max. — — — — — — 300 300 100 1000 300 300 — — — — 0.9 0.3 — — — — — — — — — Units μs μs μs μs μs μs ns ns ns ns ns ns ns ns ns ns μs μs ns ns ns ns ns ns ns ns ns — After this period, the first clock pulse is generated Only relevant for Repeated Start condition — — CB is specified to be from 10 to 400 pF Conditions PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz — PBCLK must operate at a minimum of 800 kHz PBCLK must operate at a minimum of 3.2 MHz — CB is specified to be from 10 to 400 pF Param. No. IS10 Symbol TLO:SCL Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). DS61168D-page 272 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX TABLE 29-31: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE) (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.3V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Characteristics Stop Condition Hold Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS40 TAA:SCL Output Valid from 100 kHz mode Clock 400 kHz mode 1 MHz mode (Note 1) IS45 TBF:SDA Bus Free Time 100 kHz mode 400 kHz mode 1 MHz mode (Note 1) IS50 Note 1: CB Bus Capacitive Loading Min. 4000 600 250 0 0 0 4.7 1.3 0.5 — 3500 1000 350 — — — 400 Max. — — Units ns ns ns ns ns ns μs μs μs pF The amount of time the bus must be free before a new transmission can start — — Conditions — Param. No. IS34 Symbol THD:STO Maximum pin capacitance = 10 pF for all I2Cx pins (for 1 MHz mode only). © 2011-2012 Microchip Technology Inc. Preliminary DS61168D-page 273 PIC32MX1XX/2XX TABLE 29-32: ADC MODULE SPECIFICATIONS AC CHARACTERISTICS Param. No. AD01 Standard Operating Conditions: 2.5V to 3.6V (unless otherwise stated) Operating temperature -40°C ≤TA ≤+85°C for Industrial -40°C ≤TA ≤+105°C for V-temp Min. Typical Max. Units Conditions Symbol Characteristics Device Supply AVDD Module VDD Supply Greater of VDD – 0.3 or 2.5 VSS AVSS + 2.0 2.5 VREFL VREF IREF Reference Voltage Low Absolute Reference Voltage (VREFH – VREFL) Current Drain AVSS 2.0 — — Lesser of VDD + 0.3 or 3.6 VSS + 0.3 AVDD 3.6 VREFH – 2.0 AVDD 400 3 VREFH AVDD/2 AVDD + 0.3 +/-0.610 V — V V V V V μA μA V V V μA (Note 1) VREFH = AVDD (Note 3) (Note 1) (Note 3) ADC operating ADC off — — — VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3.3V Source Impedance = 10 kΩ (Note 1) — AD02 AD05 AD05a AD06 AD07 AD08 AVSS VREFH Module VSS Supply Reference Voltage High — — — — — 250 — — — — +/- 0.001 Reference Inputs Analog Input AD12 AD13 AD14 AD15 VINH-VINL Full-Scale Input Span VINL VIN Absolute VINL Input Voltage Absolute Input Voltage Leakage Current VREFL AVSS – 0.3 AVSS – 0.3 — AD17 RIN Recommended Impedance of Analog Voltage Source Resolution Integral Nonlinearity Differential Nonlinearity — — 5K Ω ADC Accuracy – Measurements with External VREF+/VREFAD20c Nr AD21c INL AD22c DNL 10 data bits > -1 > -1 — — -1 — — — — 4)1@ ZLWK  PP &RQWDFW /HQJWK 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS61168D-page 298 Preliminary © 2011-2012 Microchip Technology Inc. PIC32MX1XX/2XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2011-2012 Microchip Technology Inc. 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