PIC32MX675F256L

PIC32MX5XX/6XX/7XX Family Data Sheet High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers © 2009-2011 Microchip Technology Inc. DS61156G Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2009-2011, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-61341-150-6 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61156G-page 2 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers High-Performance 32-bit RISC CPU: • MIPS32® M4K® 32-bit core with 5-stage pipeline • 80 MHz maximum frequency • 1.56 DMIPS/MHz (Dhrystone 2.1) performance at zero Wait state Flash access • Single-cycle multiply and high-performance divide unit • MIPS16e® mode for up to 40% smaller code size • Two sets of 32 core register files (32-bit) to reduce interrupt latency • Prefetch Cache module to speed execution from Flash Peripheral Features (Continued): • Internal 8 MHz and 32 kHz oscillators • Six UART modules with: - RS-232, RS-485 and LIN support - IrDA® with on-chip hardware encoder and decoder • Up to four SPI modules • Up to five I2C™ modules • Separate PLLs for CPU and USB clocks • Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data, and up to 16 address lines • Hardware Real-Time Clock and Calendar (RTCC) • Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) • Five Capture inputs • Five Compare/PWM outputs • Five external interrupt pins • High-speed I/O pins capable of toggling at up to 80 MHz • High-current sink/source (18 mA/18 mA) on all I/O pins • Configurable open-drain output on digital I/O pins Microcontroller Features: • Operating voltage range of 2.3V to 3.6V • 64K to 512K Flash memory (plus an additional 12 KB of Boot Flash) • 16K to 128K SRAM memory • Pin-compatible with most PIC24/dsPIC® DSC devices • Multiple power management modes • Multiple interrupt vectors with individually programmable priority • Fail-Safe Clock Monitor mode • Configurable Watchdog Timer with on-chip Low-Power RC oscillator for reliable operation Debug Features: • Two programming and debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS® standard enhanced Joint Test Action Group (JTAG) interface • Unintrusive hardware-based instruction trace • IEEE Standard 1149.2 compatible (JTAG) boundary scan Peripheral Features: • Atomic SET, CLEAR and INVERT operation on select peripheral registers • Up to 8-channels of hardware DMA with automatic data size detection • USB 2.0-compliant full-speed device and On-The-Go (OTG) controller: - Dedicated DMA channels • 10/100 Mbps Ethernet MAC with MII and RMII interface: - Dedicated DMA channels • CAN module: - 2.0B Active with DeviceNet™ addressing support - Dedicated DMA channels • 3 MHz to 25 MHz crystal oscillator Analog Features: • Up to 16-channel, 10-bit Analog-to-Digital Converter: - 1 Msps conversion rate - Conversion available during Sleep and Idle • Two Analog Comparators © 2009-2011 Microchip Technology Inc. DS61156G-page 3 PIC32MX5XX/6XX/7XX TABLE 1: PIC32 USB AND CAN – FEATURES USB and CAN Timers/Capture/Compare Program Memory (KB) 10-bit 1 Msps ADC (Channels) Data Memory (KB) DMA Channels (Programmable/ Dedicated) Comparators PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H PIC32MX534F064L 64 64 64 64 64 100 64 + 12(1) 64 + 12(1) 128 + 12(1) 256 + 12(1) 512 + 12(1) 64 + 12(1) 16 32 32 64 64 16 1 1 1 1 1 1 1 1 1 1 1 1 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 4/4 4/4 4/4 8/4 8/4 4/4 6 6 6 6 6 6 3 3 3 3 3 4 4 4 4 4 4 5 16 16 16 16 16 16 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes PIC32MX564F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PIC32MX564F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PIC32MX575F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX575F512L Legend: Note 1: 2: 3: 4: 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF, PT = TQFP MR = QFN BG = XBGA This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more information. Refer to Section 32.0 “Packaging Information” for more information. DS61156G-page 4 © 2009-2011 Microchip Technology Inc. Packages(4) PT, MR PT, MR PT, MR PT, MR PT, MR PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PMP/PSP UART(2,3) I2C™(3) Device Trace JTAG SPI(3) CAN Pins USB PIC32MX5XX/6XX/7XX TABLE 2: PIC32 USB AND ETHERNET – FEATURES USB and Ethernet Timers/Capture/Compare Program Memory (KB) 10-bit 1 Msps ADC (Channels) Data Memory (KB) DMA Channels (Programmable/ Dedicated) Comparators PIC32MX664F064H PIC32MX664F128H PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H PIC32MX664F064L 64 64 64 64 64 100 64 + 12(1) 128 + 12(1) 256 + 12(1) 512 + 12(1) 512 + 12(1) 64 + 12(1) 32 32 64 64 128 32 1 1 1 1 1 1 1 1 1 1 1 1 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 4/4 4/4 8/4 8/4 8/4 4/4 6 6 6 6 6 6 3 3 3 3 3 4 4 4 4 4 4 5 16 16 16 16 16 16 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No Yes Yes PIC32MX664F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PIC32MX675F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX675F512L 100 512 + 12(1) 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX695F512L Legend: Note 1: 2: 3: 4: 100 128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF, PT = TQFP MR = QFN BG = XBGA This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more information. Refer to Section 32.0 “Packaging Information” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 5 Packages(4) PT, MR PT, MR PT, MR PT, MR PT, MR PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PMP/PSP UART(2,3) Ethernet I2C™(3) Device Trace JTAG SPI(3) USB Pins PIC32MX5XX/6XX/7XX TABLE 3: PIC32 USB, ETHERNET AND CAN – FEATURES USB, Ethernet and CAN Timers/Capture/Compare Program Memory (KB) 10-bit 1 Msps ADC (Channels) Data Memory (KB) DMA Channels (Programmable/ Dedicated) Comparators PIC32MX764F128H PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H PIC32MX764F128L 64 64 64 64 128 + 12(1) 256 + 12(1) 512 + 12(1) 32 64 64 1 1 1 1 1 1 1 1 1 1 1 2 2 2 1 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 4/6 8/8 8/8 8/8 4/6 6 6 6 6 6 3 3 3 3 4 4 4 4 4 5 16 16 16 16 16 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes No No No No 512 + 12(1) 128 32 100 128 + 12(1) Yes Yes Yes PIC32MX775F256L 100 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PIC32MX775F512L 100 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PIC32MX795F512L Legend: Note 1: 2: 3: 4: 100 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PF, PT = TQFP MR = QFN BG = XBGA This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more information. Refer to Section 32.0 “Packaging Information” for more information. DS61156G-page 6 © 2009-2011 Microchip Technology Inc. Packages(4) PT, MR PT, MR PT, MR PT, MR PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PMP/PSP UART(2,3) Ethernet I2C™(3) Device Trace JTAG SPI(3) CAN Pins USB PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN(1) = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2009-2011 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS61156G-page 7 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 PIC32MX664F064H 42 41 PIC32MX664F128H 40 PIC32MX675F256H 39 PIC32MX675F512H 38 PIC32MX695F512H 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 DS61156G-page 8 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) = Pins are up to 5V tolerant ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX775F256H 8 40 PIC32MX775F512H 9 39 PIC32MX795F512H 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. © 2009-2011 Microchip Technology Inc. ERXERR/PMD4/RE4 ERXCLK/EREFCLKPMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 DS61156G-page 9 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN(1) = Pins are up to 5V tolerant ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 1 47 2 46 3 45 4 44 5 43 6 42 7 41 PIC32MX764F128H 8 40 9 39 10 38 11 37 12 36 13 35 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 Note 1: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. ERXERR/PMD4/RE4 ERXCLK/EREFCLKPMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 DS61156G-page 10 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 © 2009-2011 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 C1TX/RF1 C1RX/RF0 VDD VCAP/VCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 SCK3/U4TX/U1RTS/OC2/RD1 PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX575F256H PIC32MX575F512H 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 DS61156G-page 11 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 PIC32MX664F064H 7 PIC32MX664F128H 8 PIC32MX675F256H 9 PIC32MX675F512H 10 PIC32MX695F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 DS61156G-page 12 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 PIC32MX775F256H 9 PIC32MX775F512H 10 PIC32MX795F512H 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/C2TX/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 © 2009-2011 Microchip Technology Inc. DS61156G-page 13 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 VDD VCAP/VCORE ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL3/SDO3/U1TX/OC4/RD3 SDA3/SDI3/U1RXU1RX/OC3/RD2 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1 = Pins are up to 5V tolerant ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 PIC32MX764F128H 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS4/U5RX/U2CTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 ERXERR/PMD4/RE4 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXD0/PMD1/RE1 ERXD1/PMD0/RE0 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 DS61156G-page 14 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VDD VCAP/VCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 SDA4/SDI2/U3RX/PMA4/CN9/RG7 SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX575F512L PIC32MX575F256L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 © 2009-2011 Microchip Technology Inc. PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD SS3/U4RX/U1CTS/CN20/RD14 SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS61156G-page 15 Pin Diagrams (Continued) 100-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 SCK4/U5TX/U2RTS/RF13 SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DS61156G-page 16 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are up to 5V tolerant PIC32MX664F064L PIC32MX664F128L PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 Pin Diagrams (Continued) 100-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 © 2009-2011 Microchip Technology Inc. DS61156G-page 17 = Pins are up to 5V tolerant AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD1 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 100-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK4/U5TX/U2RTS/RF13 AC1RX/SS4/U5RX/U2CTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS3/U4RX/U1CTS/CN20/RD14 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 DS61156G-page 18 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX = Pins are up to 5V tolerant PIC32MX764F128L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD1 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL3/SDO3/U1TX/RF8 SDA3/SDI3/U1RX/RF2 USBID/RF3 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin XBGA(1) PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L 1 2 3 4 5 6 7 8 9 10 11 = Pins are up to 5V tolerant A RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCAP/ VCORE RD5 RD3 VSS RC14 C D E F G H J K RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2 RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note 1: Refer to Table 4, Table 5 and Table 6 for full pin names. © 2009-2011 Microchip Technology Inc. DS61156G-page 19 PIC32MX5XX/6XX/7XX TABLE 4: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 C1TX/PMD10/RF1 VDD VSS IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) PMD14/CN15/RD6 PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6 T3CK/RC2 VDD PMD9/RG1 VSS PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 SDA1/INT4/RA15 RTCC/IC1/RD8 SS1/IC2/RD9 SCL1/INT3/RA14 MCLR SCL4/SDO2/U3TX/PMA3/CN10/RG8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 SDA4/SDI2/U3RX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 No Connect (NC) No Connect (NC) SCL3/SDO3/U1TX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Pin Name DS61156G-page 20 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS4/U5RX/U2CTS/RF12 AN14/PMALH/PMA1/RB14 VDD SCK3/U4TX/U1RTS/CN21/RD15 USBID/RF3 SDA3/SDI3/U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9 PIN NAMES: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK4/U5TX/U2RTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 SS3/U4RX/U1CTS/CN20/RD14 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 Full Pin Name © 2009-2011 Microchip Technology Inc. DS61156G-page 21 PIC32MX5XX/6XX/7XX TABLE 5: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 ETXD1/PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 T3CK/RC2 VDD ETXERR/PMD9/RG1 VSS PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/ U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2/U6RX/ U3CTS/PMA2/CN11/RG9 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL3/SDO3/U1TX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10 DS61156G-page 22 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 5: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) SS4/U5RX/U2CTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 USBID/RF3 SDA3/SDI3/U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9 PIN NAMES: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES (CONTINUED) Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 SCK4/U5TX/U2RTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 Full Pin Name © 2009-2011 Microchip Technology Inc. DS61156G-page 23 PIC32MX5XX/6XX/7XX TABLE 6: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 C2RX/PMD8/RG0 C1TX/ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/ETXD1/PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/AC2RX/RC3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 T3CK/AC2TX/RC2 VDD C2TX/ETXERR/PMD9/RG1 VSS PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL3/SDO3/U1TX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10 DS61156G-page 24 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 6: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS4/U5RX/U2CTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 USBID/RF3 SDA3/SDI3/U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9 PIN NAMES: PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED) Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK4/U5TX/U2RTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 Full Pin Name © 2009-2011 Microchip Technology Inc. DS61156G-page 25 PIC32MX5XX/6XX/7XX TABLE 7: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 C1TX/ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/ETXD1/PMD11/RF0 VCAP/VCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 T3CK/RC2 VDD ETXERR/PMD9/RG1 VSS PIN NAME: PIC32MX764F128L DEVICE Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/ U3TX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/ U3CTS/PMA2/CN11/RG9 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL3/SDO3/U1TX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10 DS61156G-page 26 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 7: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS4/U5RX/U2CTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 USBID/RF3 SDA3/SDI3/U1RX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9 PIN NAME: PIC32MX764F128L DEVICE (CONTINUED) Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK4/U5TX/U2RTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 SDA5/SDI4/U2RX/PMA9/CN17/RF4 SCL5/SDO4/U2TX/PMA8/CN18/RF5 Full Pin Name © 2009-2011 Microchip Technology Inc. DS61156G-page 27 PIC32MX5XX/6XX/7XX Table of Contents 1.0 Device Overview ........................................................................................................................................................................ 31 2.0 Guidelines for Getting Started with 32-bit Microcontrollers ........................................................................................................ 43 3.0 CPU............................................................................................................................................................................................ 49 4.0 Memory Organization ................................................................................................................................................................. 55 5.0 Flash Program Memory ............................................................................................................................................................ 117 6.0 Resets ...................................................................................................................................................................................... 119 7.0 Interrupt Controller ................................................................................................................................................................... 121 8.0 Oscillator Configuration ............................................................................................................................................................ 125 9.0 Prefetch Cache......................................................................................................................................................................... 127 10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 129 11.0 USB On-The-Go (OTG)............................................................................................................................................................ 131 12.0 I/O Ports ................................................................................................................................................................................... 133 13.0 Timer1 ...................................................................................................................................................................................... 135 14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 137 15.0 Input Capture............................................................................................................................................................................ 139 16.0 Output Compare....................................................................................................................................................................... 141 17.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 143 18.0 Inter-Integrated Circuit™ (I2C™) .............................................................................................................................................. 145 19.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 147 20.0 Parallel Master Port (PMP)....................................................................................................................................................... 149 21.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 151 22.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 153 23.0 Controller Area Network (CAN) ................................................................................................................................................ 155 24.0 Ethernet Controller ................................................................................................................................................................... 157 25.0 Comparator .............................................................................................................................................................................. 159 26.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 161 27.0 Power-Saving Features ........................................................................................................................................................... 163 28.0 Special Features ...................................................................................................................................................................... 165 29.0 Instruction Set .......................................................................................................................................................................... 177 30.0 Development Support............................................................................................................................................................... 179 31.0 Electrical Characteristics .......................................................................................................................................................... 183 32.0 Packaging Information.............................................................................................................................................................. 225 The Microchip Web Site ..................................................................................................................................................................... 253 Customer Change Notification Service .............................................................................................................................................. 253 Customer Support .............................................................................................................................................................................. 253 Reader Response .............................................................................................................................................................................. 254 Product Identification System............................................................................................................................................................. 255 DS61156G-page 28 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. © 2009-2011 Microchip Technology Inc. DS61156G-page 29 PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 30 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Figure 1-1 illustrates a general block diagram of the core and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 1-1: BLOCK DIAGRAM(1,2) OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators PLL Dividers PLL-USB Timing Generation VCAP/VCORE Power-up Timer Voltage Regulator Precision Band Gap Reference USBCLK SYSCLK PBCLK Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset CN1-22 Timer1-5 CAN1, CAN2 PWM OC1-5 VDD, VSS MCLR Peripheral Bus Clocked by SYSCLK PORTA JTAG BSCAN PORTB USB EJTAG MIPS32® PORTC 32 PORTD IS 32 INT M4K® DS 32 32 Bus Matrix 32 PORTE Prefetch Module PORTF 128 128-bit Wide Program Flash Memory Flash Controller Data RAM Peripheral Bridge 32 32 32 Priority Interrupt Controller 32 Peripheral Bus Clocked by PBCLK ETHERNET DMAC ICD IC1-5 CPU Core 32 32 32 32 SPI1-4 I2C1-5 PMP 10-bit ADC UART1-6 RTCC Comparators PORTG Note 1: 2: Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled. © 2009-2011 Microchip Technology Inc. DS61156G-page 31 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Number(1) 64-Pin QFN/TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 39 40 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 63 64 121-Pin XBGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 F9 F11 Pin Type I I I I I I I I I I I I I I I I I O Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Description Analog input channels. OSC1 OSC2 39 40 63 64 F9 F11 I I/O SOSCI 47 73 C10 I SOSCO 48 74 B11 O Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. — 32.768 kHz low-power oscillator crystal output. Analog = Analog input P = Power O = Output I = Input DS61156G-page 32 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 81 44 72 18 19 66 121-Pin XBGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 E9 E10 D11 C11 A9 L1 D9 A11 A10 B9 C8 L8 D9 G1 G2 E11 Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O I I I I I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — — — — ST ST ST ST ST Description Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Capture Inputs 1-5 Output Compare Fault A Input Output Compare Output 1 Output Compare Output 2 Output Compare Output 3 Output Compare Output 4 Output Compare Output 5 Output Compare Fault B Input External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 INT4 45 67 E8 I ST External Interrupt 4 Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 33 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Pin Type Buffer Type Description RA0 — 17 G3 I/O ST PORTA is a bidirectional I/O port RA1 — 38 J6 I/O ST RA2 — 58 H11 I/O ST RA3 — 59 G10 I/O ST RA4 — 60 G11 I/O ST RA5 — 61 G9 I/O ST RA6 — 91 C5 I/O ST RA7 — 92 B5 I/O ST RA9 — 28 L2 I/O ST RA10 — 29 K3 I/O ST RA14 — 66 E11 I/O ST RA15 — 67 E8 I/O ST RB0 16 25 K2 I/O ST PORTB is a bidirectional I/O port RB1 15 24 K1 I/O ST RB2 14 23 J2 I/O ST RB3 13 22 J1 I/O ST RB4 12 21 H2 I/O ST RB5 11 20 H1 I/O ST RB6 17 26 L1 I/O ST RB7 18 27 J3 I/O ST RB8 21 32 K4 I/O ST RB9 22 33 L4 I/O ST RB10 23 34 L5 I/O ST RB11 24 35 J5 I/O ST RB12 27 41 J7 I/O ST RB13 28 42 L7 I/O ST RB14 29 43 K7 I/O ST RB15 30 44 L8 I/O ST RC1 — 6 D1 I/O ST PORTC is a bidirectional I/O port RC2 — 7 E4 I/O ST RC3 — 8 E2 I/O ST RC4 — 9 E1 I/O ST RC12 39 63 F9 I/O ST RC13 47 73 C10 I/O ST RC14 48 74 B11 I/O ST RC15 40 64 F11 I/O ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156G-page 34 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 100-Pin TQFP 121-Pin XBGA Pin Type Buffer Type Description RD0 46 72 D9 I/O ST PORTD is a bidirectional I/O port RD1 49 76 A11 I/O ST RD2 50 77 A10 I/O ST RD3 51 78 B9 I/O ST RD4 52 81 C8 I/O ST RD5 53 82 B8 I/O ST RD6 54 83 D7 I/O ST RD7 55 84 C7 I/O ST RD8 42 68 E9 I/O ST RD9 43 69 E10 I/O ST RD10 44 70 D11 I/O ST RD11 45 71 C11 I/O ST RD12 — 79 A9 I/O ST RD13 — 80 D8 I/O ST RD14 — 47 L9 I/O ST RD15 — 48 K9 I/O ST RE0 60 93 A4 I/O ST PORTE is a bidirectional I/O port RE1 61 94 B4 I/O ST RE2 62 98 B3 I/O ST RE3 63 99 A2 I/O ST RE4 64 100 A1 I/O ST RE5 1 3 D3 I/O ST RE6 2 4 C1 I/O ST RE7 3 5 D2 I/O ST RE8 — 18 G1 I/O ST RE9 — 19 G2 I/O ST RF0 58 87 B6 I/O ST PORTF is a bidirectional I/O port RF1 59 88 A6 I/O ST RF2 — 52 K11 I/O ST RF3 33 51 K10 I/O ST RF4 31 49 L10 I/O ST RF5 32 50 L11 I/O ST RF8 — 53 J10 I/O ST RF12 — 40 K6 I/O ST RF13 — 39 L6 I/O ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 35 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK U1CTS U1RTS U1RX U1TX U3CTS U3RTS U3RX U3TX U2CTS U2RTS U2RX U2TX U4RX U4TX U6RX U6TX U5RX U5TX SCK1 SDI1 SDO1 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — — 4 5 6 8 — — — — 37 36 48 — — — — 43 49 50 51 8 4 5 6 21 29 31 32 43 49 8 4 21 29 — — — 100-Pin TQFP 90 89 10 11 12 14 96 97 95 1 57 56 74 6 7 8 9 47 48 52 53 14 10 11 12 40 39 49 50 47 48 14 10 40 39 70 9 72 121-Pin XBGA A5 E6 E3 F4 F2 F3 C3 A3 C4 B2 H10 J11 B11 D1 E4 E2 E1 L9 K9 K11 J10 F3 E3 F4 F2 K6 L6 L10 L11 L9 K9 F3 E3 K6 L6 D11 E1 D9 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I O I O I O I O I O I O I O I O I O I/O I O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST — ST — ST — ST — ST — ST — ST — ST — ST ST — Description PORTG is a bidirectional I/O port PORTG input pins Timer1 external clock input Timer2 external clock input Timer3 external clock input Timer4 external clock input Timer5 external clock input UART1 clear to send UART1 ready to send UART1 receive UART1 transmit UART3 clear to send UART3 ready to send UART3 receive UART3 transmit UART2 clear to send UART2 ready to send UART2 receive UART2 transmit UART4 receive UART4 transmit UART6 receive UART6 transmit UART5 receive UART5 transmit Synchronous serial clock input/output for SPI1 SPI1 data in SPI1 data out Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156G-page 36 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name SS1 SCK3 SDI3 SDO3 SS3 SCK2 SDI2 SDO2 SS2 SCK4 SDI4 SDO4 SS4 SCL1 SDA1 SCL3 SDA3 SCL2 SDA2 SCL4 SDA4 SCL5 SDA5 TMS TCK TDI TDO RTCC CVREFCVREF+ CVREFOUT PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — 49 50 51 43 4 5 6 8 29 31 32 21 44 43 51 50 — — 6 5 32 31 23 27 28 24 42 15 16 100-Pin TQFP 69 48 52 53 47 10 11 12 14 39 49 50 40 66 67 53 52 58 59 12 11 50 49 17 38 60 61 68 28 29 121-Pin XBGA E10 K9 K11 J10 L9 E3 F4 F2 F3 L6 L10 L11 K6 E11 E8 J10 K11 H11 G10 F2 F4 L11 L10 G3 J6 G11 G9 E9 L2 K3 Pin Type I/O I/O I O I/O I/O I O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O O I I Buffer Type ST ST ST — ST ST ST — ST ST ST — ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — Analog Analog Description SPI1 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI3 SPI3 data in SPI3 data out SPI3 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI2 SPI2 data in SPI2 data out SPI2 slave synchronization or frame pulse I/O Synchronous serial clock input/output for SPI4 SPI4 data in SPI4 data out SPI4 slave synchronization or frame pulse I/O Synchronous serial clock input/output for I2C1 Synchronous serial data input/output for I2C1 Synchronous serial clock input/output for I2C3 Synchronous serial data input/output for I2C3 Synchronous serial clock input/output for I2C2 Synchronous serial data input/output for I2C2 Synchronous serial clock input/output for I2C4 Synchronous serial data input/output for I2C4 Synchronous serial clock input/output for I2C5 Synchronous serial data input/output for I2C5 JTAG Test mode select pin JTAG test clock input pin JTAG test data input pin JTAG test data output pin Real-Time Clock alarm output Comparator Voltage Reference (low) Comparator Voltage Reference (high) 23 34 L5 O Analog Comparator Voltage Reference output C1IN12 21 H2 I Analog Comparator 1 negative input C1IN+ 11 20 H1 I Analog Comparator 1 positive input C1OUT 21 32 K4 O — Comparator 1 output C2IN14 23 J2 I Analog Comparator 2 negative input C2IN+ 13 22 J1 I Analog Comparator 2 positive input C2OUT 22 33 L4 O — Comparator 2 output Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 37 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name PMA0 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 30 100-Pin TQFP 44 121-Pin XBGA L8 Pin Type I/O Buffer Type TTL/ST Description Parallel Master Port Address bit 0 input (Buffered Slave modes) and output (Master modes) Parallel Master Port Address bit 1 input (Buffered Slave modes) and output (Master modes) Parallel Master Port address (Demultiplexed Master modes) PMA1 29 43 K7 I/O TTL/ST PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 8 6 5 4 16 22 32 31 28 27 24 23 45 44 45 44 14 12 11 10 29 28 50 49 42 41 35 34 71 70 71 70 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C11 D11 O O O O O O O O O O O O O O O O — — — — — — — — — — — — — — — — Parallel Master Port Chip Select 1 strobe Parallel Master Port Chip Select 2 strobe PMD0 60 93 A4 I/O TTL/ST Parallel Master Port data (Demultiplexed PMD1 61 94 B4 I/O TTL/ST Master mode) or address/data (Multiplexed Master modes) PMD2 62 98 B3 I/O TTL/ST PMD3 63 99 A2 I/O TTL/ST PMD4 64 100 A1 I/O TTL/ST PMD5 1 3 D3 I/O TTL/ST PMD6 2 4 C1 I/O TTL/ST PMD7 3 5 D2 I/O TTL/ST PMD8 — 90 A5 I/O TTL/ST PMD9 — 89 E6 I/O TTL/ST PMD10 — 88 A6 I/O TTL/ST PMD11 — 87 B6 I/O TTL/ST PMD12 — 79 A9 I/O TTL/ST PMD13 — 80 D8 I/O TTL/ST PMD14 — 83 D7 I/O TTL/ST PMD15 — 84 C7 I/O TTL/ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156G-page 38 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name PMALL PMALH PMRD PMWR VBUS VUSB PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 30 29 53 52 34 35 100-Pin TQFP 44 43 82 81 54 55 121-Pin XBGA L8 K7 B8 C8 H8 H9 Pin Type O O O O I P Buffer Type — — — — Analog — Description Parallel Master Port address latch enable low byte (Multiplexed Master modes) Parallel Master Port address latch enable high byte (Multiplexed Master modes) Parallel Master Port read strobe Parallel Master Port write strobe USB bus power monitor USB internal transceiver supply. If the USB module is not used, this pin must be connected to VDD. USB Host and OTG bus power control output USB D+ USB DUSB OTG ID detect CAN1 bus receive pin CAN1 bus transmit pin Alternate CAN1 bus receive pin Alternate CAN1 bus transmit pin CAN2 bus receive pin CAN2 bus transmit pin Alternate CAN2 bus receive pin Alternate CAN2 bus transmit pin Ethernet Receive Data 0(2) Ethernet Receive Data 1(2) Ethernet Receive Data 2(2) Ethernet Receive Data 3(2) Ethernet receive error input(2) Ethernet receive data valid(2) Ethernet carrier sense data valid(2) Ethernet receive clock(2) Ethernet reference clock(2) Ethernet Transmit Data 0(2) Ethernet Transmit Data 1(2) Ethernet Transmit Data 2(2) Ethernet Transmit Data 3(2) Ethernet transmit error(2) Ethernet transmit enable(2) Ethernet transmit clock(2) Ethernet collision detect(2) Ethernet carrier sense(2) VBUSON D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX ERXD0 ERXD1 ERXD2 ERXD3 ERXERR ERXDV ECRSDV ERXCLK EREFCLK ETXD0 ETXD1 ETXD2 ETXD3 ETXERR ETXEN ETXCLK ECOL ECRS 11 37 36 33 58 59 32 31 29 21 — — 61 60 59 58 64 62 62 63 63 2 3 43 42 54 1 55 44 45 20 57 56 51 87 88 40 39 90 89 8 7 41 42 43 44 35 12 12 14 14 88 87 79 80 89 83 84 10 11 H1 H10 J11 K10 B6 A6 K6 L6 A5 E6 E2 E4 J7 L7 K7 L8 J5 F2 F2 F3 F3 A6 B6 A9 D8 E6 D7 C7 E3 F4 O I/O I/O I I O I O I O 1 O I I I I I I I I I O O O O O O I I I — Analog Analog ST ST — ST — ST — ST — ST ST ST ST ST ST ST ST ST — — — — — — ST ST ST Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 39 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name EMDC EMDIO AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AERXDV AECRSDV AERXCLK AEREFCLK AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AETXEN AETXCLK AECOL AECRS AEMDC AEMDIO TRCLK TRD0 TRD1 TRD2 TRD3 PGED1 PGEC1 PGED2 PGEC2 MCLR PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 30 49 43 42 — — 55 — 44 — 45 59 58 — — — 54 — — — 30 49 — — — — — 16 15 18 17 7 100-Pin TQFP 71 68 18 19 28 29 1 12 12 14 14 47 48 44 43 35 67 66 42 41 71 68 91 97 96 95 92 25 24 27 26 13 121-Pin XBGA C11 E9 G1 G2 L2 K3 B2 F2 F2 F3 F3 L9 K9 L8 K7 J5 E8 E11 L7 J7 C11 E9 C5 A3 C3 C4 B5 K2 K1 J3 L1 F1 Pin Type O I/O I I I I I I I I I O O O O O O I I I O I/O O O O O O I/O I I/O I I/P Buffer Type — — ST ST ST ST ST ST ST ST ST — — — — — — ST ST ST — — — — — — — ST ST ST ST ST Description Ethernet management data clock(2) Ethernet management data(2) Alternate Ethernet Receive Data 0(2) Alternate Ethernet Receive Data 1(2) Alternate Ethernet Receive Data 2(2) Alternate Ethernet Receive Data 3(2) Alternate Ethernet receive error input(2) Alternate Ethernet receive data valid(2) Alternate Ethernet carrier sense data valid(2) Alternate Ethernet receive clock(2) Alternate Ethernet reference clock(2) Alternate Ethernet Transmit Data 0(2) Alternate Ethernet Transmit Data 1(2) Alternate Ethernet Transmit Data 2(2) Alternate Ethernet Transmit Data 3(2) Alternate Ethernet transmit error(2) Alternate Ethernet transmit enable(2) Alternate Ethernet transmit clock(2) Alternate Ethernet collision detect(2) Alternate Ethernet carrier sense(2) Alternate Ethernet Management Data clock(2) Alternate Ethernet Management Data(2) Trace clock Trace Data bits 0-3 Data I/O pin for Programming/Debugging Communication Channel 1 Clock input pin for Programming/Debugging Communication Channel 1 Data I/O pin for Programming/Debugging Communication Channel 2 Clock input pin for Programming/Debugging Communication Channel 2 Master Clear (Reset) input. This pin is an active-low Reset to the device. Analog = Analog input P = Power O = Output I = Input Legend: CMOS = CMOS compatible input or output ST = Schmitt Trigger input with CMOS levels TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156G-page 40 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name AVDD AVSS VDD PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 19 100-Pin TQFP 30 121-Pin XBGA J4 Pin Type P Buffer Type P Description Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules Positive supply for peripheral logic and I/O pins L3 P P A7, C2, P — C9, E5, K8, F8, G5, H4, H6 56 85 B7 P — Capacitor for Internal Voltage Regulator VCAP/VCORE VSS 9, 25, 41 15, 36, 45, A8, B10, P — Ground reference for logic and I/O pins. This 65, 75 D4, D5, pin must be connected at all times. E7, F5, F10, G6, G7, H3 16 29 K3 I Analog Analog voltage reference (high) input VREF+ VREF15 28 L2 I Analog Analog voltage reference (low) input Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. 20 31 10, 26, 38, 2, 16, 37, 57 46, 62, 86 © 2009-2011 Microchip Technology Inc. DS61156G-page 41 PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 42 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended to use ceramic capacitors. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within one-quarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum, thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC32MX5XX/6XX/7XX family of 32-bit Microcontrollers (MCUs) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins even if the ADC module is not used (see Section 2.2 “Decoupling Capacitors”) • VCAP/VCORE pin (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP/VCORE)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins when external oscillator source is used (see Section 2.8 “External Oscillator Pins”) The following pin may be required, as well: VREF+/VREF- pins used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected, regardless of the ADC use and the ADC voltage reference source. © 2009-2011 Microchip Technology Inc. DS61156G-page 43 PIC32MX5XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic CBP VDD VSS 2.4 Master Clear (MCLR) Pin pin provides two specific device The MCLR functions: VDD R R1 MCLR CEFC • Device Reset • Device Programming and Debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 illustrates a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as illustrated in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components illustrated in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. C VCAP/VCORE PIC32 VSS VDD VDD VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP AVDD AVSS VDD 0.1 µF Ceramic CBP VSS 0.1 µF Ceramic CBP 10 Ω 2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR PIC32 2.3 2.3.1 Capacitor on Internal Voltage Regulator (VCAP/VCORE) INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP/VCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 “Electrical Characteristics” for additional information on CEFC specifications. Note 1: R ≤10 kΩ is recommended. A suggested starting value is 10 kΩ. Ensure that the MCLR pin VIH and VIL specifications are met. R1 ≤ 470Ω will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during the POR. 2: 3: DS61156G-page 44 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.5 ICSP Pins 2.6 JTAG The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB® ICD 3 or MPLAB® REAL ICE™. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. • “MPLAB® ICD 2 In-Circuit Debugger User’s Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Emulator User’s Guide” DS51616 • “Using MPLAB® REAL ICE™ Emulator” (poster) DS51749 The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 Trace The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22Ω series resistor between the trace pins and the trace connector. © 2009-2011 Microchip Technology Inc. DS61156G-page 45 PIC32MX5XX/6XX/7XX 2.8 External Oscillator Pins 2.9 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator. Refer to Section 8.0 “Oscillator Configuration” for details. The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is illustrated in Figure 2-3. Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3 or REAL ICE is selected as a debugger, it automatically initializes all of the Analog-to-Digital input pins (ANx) as “digital” pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the Analogto-Digital pins that are initialized by MPLAB ICD 2, ICD 3 or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain ADC pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3 or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all ADC pins being recognized as analog input pins, resulting in the port value being read as a logic ‘0’, which may affect user application functionality. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. DS61156G-page 46 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.11 Referenced Sources This device data sheet is based on the following individual chapters of the “PIC32 Family Reference Manual”. These documents should be considered as the general reference for the operation of a particular module or device feature. Note 1: To access the documents listed below, browse to the documentation section of the PIC32MX795F512L product page on the Microchip web site (www.microchip.com) or select a family reference manual section from the following list. In addition to parameters, features, and other documentation, the resulting page provides links to the related family reference manual sections. • • • • • • • • • • • • • • • • • • • • • • • • • • • • Section 1. “Introduction” (DS61127) Section 2. “CPU” (DS61113) Section 4. “Prefetch Cache” (DS61119) Section 3. “Memory Organization” (DS61115) Section 5. “Flash Program Memory” (DS61121) Section 6. “Oscillator Configuration” (DS61112) Section 7. “Resets” (DS61118) Section 8. “Interrupt Controller” (DS61108) Section 9. “Watchdog Timer and Power-up Timer (DS61114) Section 10. “Power-Saving Features” (DS61130) Section 12. “I/O Ports” (DS61120) Section 13. “Parallel Master Port (PMP)” (DS61128) Section 14. “Timers” (DS61105) Section 15. “Input Capture” (DS61122) Section 16. “Output Capture” (DS61111) Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS61104) Section 19. “Comparator” (DS61110) Section 20. “Comparator Voltage Reference (CVREF)” (DS61109) Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS61107) Section 23. “Serial Peripheral Interface (SPI)” (DS61106) Section 24. “Inter-Integrated Circuit (I2C™)” (DS61116) Section 27. “USB On-The-Go (OTG)” (DS61126) Section 29. “Real-Time Clock and Calendar (RTCC)” (DS61125) Section 31. “Direct Memory Access (DMA) Controller” (DS61117) Section 32. “Configuration” (DS61124) Section 33. “Programming and Diagnostics” (DS61129) Section 34. “Controller Area Network (CAN)” (DS61154) Section 35. “Ethernet Controller” (DS61155) © 2009-2011 Microchip Technology Inc. DS61156G-page 47 PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 48 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 3.0 CPU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “CPU” (DS61113) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The MIPS32® M4K® Processor core is the heart of the PIC32MX5XX/6XX/7XX family processor. The CPU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e® code compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE and RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple dual bus interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous multiply/divide unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG debug and instruction trace - Support for single stepping - Virtual instruction and data address/value - Breakpoints - PC tracing with trace compression • • • • 3.1 Features • • 5-stage pipeline • 32-bit address and data paths • MIPS32 Enhanced Architecture (Release 2) - Multiply-accumulate and multiply-subtract instructions - Targeted multiply instruction - Zero/One detect instructions - WAIT instruction - Conditional move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base • FIGURE 3-1: CPU MIPS® M4K® PROCESSOR CORE BLOCK DIAGRAM EJTAG Trace TAP Trace I/F Off-Chip Debug I/F Dual Bus I/F Bus Matrix DS61156G-page 49 MDU Execution Core (RF/ALU/Shift) FMT Bus Interface System Coprocessor Power Management © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The MIPS® M4K® processor core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller MIPS M4K processor core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The PIC32 core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit wide rs, 15 iterations are skipped and for a 24 bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32 core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. 3.2.1 EXECUTION UNIT The MIPS M4K processor core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and store aligner DS61156G-page 50 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 3-1: MIPS® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2. © 2009-2011 Microchip Technology Inc. DS61156G-page 51 PIC32MX5XX/6XX/7XX TABLE 3-2: Register Number 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2: COPROCESSOR 0 REGISTERS Register Name Function Reserved. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved. Debug control and exception status. Program counter at last debug exception. Reserved. Program counter at last error. Debug handler scratchpad register. (1) Reserved HWREna BadVAddr(1) Count(1) Reserved Compare Status(1) IntCtl(1) SRSCtl(1) SRSMap(1) Cause(1) EPC(1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug(2) DEPC(2) Reserved ErrorEPC(1) DESAVE(2) Registers used in exception processing. Registers used during debug. DS61156G-page 52 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Description Assertion MCLR or a Power-on Reset (POR). EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare. © 2009-2011 Microchip Technology Inc. DS61156G-page 53 PIC32MX5XX/6XX/7XX 3.3 Power Management 3.4 EJTAG Debug Support The MIPS M4K Processor core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. The MIPS M4K Processor core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the MIPS M4K core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, single-step exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the MIPS M4K processor core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 “Power-Saving Features”. 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32 family uses extensive use of local gated clocks to reduce this dynamic power consumption. DS61156G-page 54 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32 Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 4.1 PIC32MX5XX/6XX/7XX Memory Layout PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX5XX/6XX/7XX devices to execute from data memory. Key features include: • 32-bit native data width • Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space • Flexible program Flash memory partitioning • Flexible data RAM partitioning for data and program space • Separate boot Flash memory for protected code • Robust bus exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable (KSEG0) and non-cacheable (KSEG1) address regions PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX5XX/6XX/7XX devices are illustrated in Figure 4-1 through Figure 4-6. 4.1.1 PERIPHERAL REGISTERS LOCATIONS Table 4-1 through Table 4-44 contain the peripheral address maps for the PIC32MX5XX/6XX/7XX devices. Peripherals located on the PB bus are mapped to 512-byte boundaries. Peripherals on the FPB bus are mapped to 4-Kbyte boundaries. © 2009-2011 Microchip Technology Inc. DS61156G-page 55 PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L, PIC32MX664F064H AND PIC32MX664F064L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D010000 0x9D00FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D010000 0x1D00FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61156G-page 56 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD010000 0xBD00FFFF Program Flash(2) 0xBD000000 0xA0004000 0xA0003FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D010000 0x9D00FFFF Program Flash(2) 0x9D000000 0x80004000 0x80003FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D010000 Reserved 0x1D00FFFF Program Flash(2) 0x1D000000 0x00004000 0x00003FFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. DS61156G-page 57 PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L, PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND PIC32MX764F128L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD020000 0xBD01FFFF Program Flash(2) 0xBD000000 0xA0008000 0xA0007FFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D020000 0x9D01FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00008000 0x00007FFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D020000 0x1D01FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61156G-page 58 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 Reserved 0x1D03FFFF Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. DS61156G-page 59 PIC32MX5XX/6XX/7XX FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80010000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61156G-page 60 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 0xA001FFFF RAM(2) 0xA0000000 0x9FC03000 0x9FC02FFF 0x9FC02FF0 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80020000 0x8001FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00020000 0x0001FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). © 2009-2011 Microchip Technology Inc. DS61156G-page 61 DS61156G-page 62 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-1: Virtual Address (BF88_#) Register Name BUS MATRIX REGISTER MAP Bit Range Bits All Resets 0041 — — — 0000 0000 — — — — — — — — — — 0000 0000 0000 0000 xxxx xxxx — — BMXPUPBA 0000 0000 xxxx xxxx 0000 3000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 BMXCON(1) 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — BMXCHEDMA — — — — — — — — — — — — — — — — — — — — BMXWSDRM — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F — — — — — BMXARB — 31:16 2010 BMXDKPBA(1) 15:0 31:16 2020 BMXDUDBA(1) 15:0 31:16 2030 BMXDUPBA(1) 15:0 2040 BMXDRMSZ 31:16 15:0 BMXDKPBA BMXDUDBA BMXDUPBA BMXDRMSZ — — — — — — — — — — 31:16 2050 BMXPUPBA(1) 15:0 2060 BMXPFMSZ 31:16 15:0 31:16 15:0 BMXPUPBA BMXPFMSZ BMXBOOTSZ 2070 BMXBOOTSZ Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. © 2009-2011 Microchip Technology Inc. DS61156G-page 63 TABLE 4-2: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) Bits Bit Range All Resets 0000 0000 0000 0000 0000 0000 — INT1IF U3TXIF I2C4MIF — U6RXIF — INT1IE U3TXIE I2C4MIE — U6RXIE — — — — OC5IF OC1IF U3RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — U4RXIE — U4EIE CTIP OC1IP T1IP CS1IP — — — IC4EIE 0000 0000 0000 0000 0000 0000 PMPEIE IC5EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE — — — IC4EIF T4IE CTIE 0000 0000 PMPEIF IC5EIF OC4IE CS1IE IC4IE CS0IE CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF OC4IF CS1IF IC4IF CS0IF T4IF CTIF 0000 0000 0000 Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — — VEC — — — — SS0 — INT3EP INT2EP INT1EP INT0EP 1010 INTSTAT(3) 1020 IPTMR IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF — — — U5TXIF U1RXIE SPI3RXIE I2C3SIE INT2IE — — — U5TXIE INT0IP CS0IP INT1IP IC1IP U1EIF SPI3EIF I2C3BIF OC2IF CAN1IF U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE CAN1IE U2TXIE SPI4TXIE I2C5MIE — U5RXIE IC2IE USBIE U2RXIE SPI4RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE — — IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF SPI2TXIF SPI2RXIF — — 1030 IFS0 31:16 I2C1MIF 15:0 31:16 INT3IF IC3EIF RTCCIF — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1BIF IC3IF IC1EIF — — — I2C1BIE IC3IE IC1EIE — — — — — — — SPI3TXIF I2C3MIF T3IF — — — — U1TXIE SPI3TXIE I2C3MIE T3IE — — — — 1040 IFS1 15:0 31:16 15:0 1050 IFS2 PIC32MX5XX/6XX/7XX 1060 IEC0 31:16 I2C1MIE I2C1SIE 15:0 31:16 INT3IE IC3EIE RTCCIE — — — — — — OC3IE IC2EIE FSCMIE — — — — — — 0000 0000 0000 DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE SPI2TXIE SPI2RXIE 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1080 1090 10A0 Legend: Note IEC2 IPC0 IPC1 INT0IS CS0IS INT1IS IC1IS CS1IS CTIS OC1IS T1IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX534/564/664/764 devices. This register does not have associated CLR, SET, and INV registers. 1: 2: 3: TABLE 4-2: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED) Bits Bit Range All Resets DS61156G-page 64 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10B0 10C0 10D0 10E0 IPC2 IPC3 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — INT2IP IC2IP INT3IP IC3IP INT4IP IC4IP — IC5IP AD1IP I2C1IP U3IP — INT2IS IC2IS INT3IS IC3IS INT4IS IC4IS — — IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — OC2IP T2IP OC3IP T3IP OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC2IS T2IS OC3IS T3IS OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) CAN1IS FCEIS U6IS — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) — USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) CAN1IP FCEIP U6IP — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) — — USBIS U5IS U4IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX534/564/664/764 devices. This register does not have associated CLR, SET, and INV registers. 1: 2: 3: © 2009-2011 Microchip Technology Inc. DS61156G-page 65 TABLE 4-3: Virtual Address (BF88_#) Bit Range INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF U3RXIF SPI2RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — — — — — U4RXIE — U4EIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP — PMPEIE — IC5EIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE DMA3IE — PMPEIF OC4IE CS1IE DMA2IE — IC5EIF IC4IE CS0IE DMA1IE — IC4EIF T4IE CTIE DMA0IE 0000 0000 0000 0000 0000 CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 1010 1020 INTCON INTSTAT(3) IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF — — — — I2C1BIE IC3IE IC1EIE — — — — — — — — — — — — U1TXIE U5TXIF U1RXIE I2C3SIE INT2IE — — — U5TXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP U1EIF SPI3EIF I2C3BIF OC2IF — U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE — U2TXIE IC2IE USBIE U2RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE INT1IE U3TXIE I2C4MIE — U6RXIE — — — — — — — — DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) SPI2TXIE SPI2RXIE — — — IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF INT1IF U3TXIF SPI2TXIF I2C4MIF — U6RXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) — — — 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2C1BIF IC3IF IC1EIF — SPI3TXIF I2C3MIF T3IF ETHIF — 1040 IFS1 15:0 31:16 15:0 1050 IFS2 1060 IEC0 31:16 I2C1MIE 15:0 31:16 INT3IE IC3EIE RTCCIE — — — — — — — — — — SPI3TXIE SPI3RXIE I2C3MIE T3IE ETHIE — — — PIC32MX5XX/6XX/7XX 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI4TXIE SPI4RXIE I2C5MIE — U5RXIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: 2: 3: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX664 devices. This register does not have associated CLR, SET, and INV registers. TABLE 4-3: Virtual Address (BF88_#) Bit Range INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) (CONTINUED) Bits All Resets DS61156G-page 66 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — INT4IP IC4IP — IC5IP AD1IP I2C1IP U3IP — INT4IS IC4IS — — IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) — — — FCEIS U6IS ETHIS 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) — USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) — FCEIP U6IP ETHIP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note 1: 2: 3: IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) — — USBIS U5IS U4IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX664 devices. This register does not have associated CLR, SET, and INV registers. © 2009-2011 Microchip Technology Inc. DS61156G-page 67 TABLE 4-4: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF U3RXIF SPI2RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — — — — — U4RXIE — U4EIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP — PMPEIE — IC5EIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE DMA3IE — PMPEIF OC4IE CS1IE DMA2IE — IC5EIF IC4IE CS0IE DMA1IE — IC4EIF T4IE CTIE DMA0IE 0000 0000 0000 0000 0000 CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — 1010 INTSTAT(3) 1020 IPTMR VEC IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF CAN2IF(2) — — U5TXIF U1RXIE I2C3SIE INT2IE CAN2IE(2) — — U5TXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP U1EIF SPI3EIF I2C3BIF OC2IF CAN1IF U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE CAN1IE U2TXIE IC2IE USBIE U2RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE INT1IE U3TXIE I2C4MIE — U6RXIE — — — — — — — — DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) SPI2TXIE SPI2RXIE — — — IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF INT1IF U3TXIF SPI2TXIF I2C4MIF — U6RXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) — — — 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2C1BIF IC3IF IC1EIF — — — I2C1BIE IC3IE IC1EIE — — — — — — — — — — — SPI3TXIF I2C3MIF T3IF ETHIF — — — U1TXIE 1040 IFS1 15:0 31:16 15:0 31:16 15:0 31:16 1050 IFS2 1060 IEC0 SPI3TXIE SPI3RXIE I2C3MIE T3IE ETHIE — — — PIC32MX5XX/6XX/7XX 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI4TXIE SPI4RXIE I2C5MIE — U5RXIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: 2: 3: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This bit is unimplemented on PIC32MX764F128H device. This register does not have associated CLR, SET, and INV registers. TABLE 4-4: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) (CONTINUED) Bits All Resets Bit Range DS61156G-page 68 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — INT4IP IC4IP — IC5IP AD1IP I2C1IP U3IP — INT4IS IC4IS — — IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) CAN1IS FCEIS U6IS ETHIS 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) CAN2IP(2) USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) CAN1IP FCEIP U6IP ETHIP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note 1: 2: 3: IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) CAN2IS(2) USBIS U5IS U4IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This bit is unimplemented on PIC32MX764F128H device. This register does not have associated CLR, SET, and INV registers. © 2009-2011 Microchip Technology Inc. DS61156G-page 69 TABLE 4-5: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF U3RXIF SPI2RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — — — — — U4RXIE — U4EIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP — PMPEIE — IC5EIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE DMA3IE — PMPEIF OC4IE CS1IE DMA2IE — IC5EIF IC4IE CS0IE DMA1IE — IC4EIF T4IE CTIE DMA0IE 0000 0000 0000 0000 0000 CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 1010 1020 INTCON INTSTAT(3) IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF — I2C2BIF — U5TXIF U1RXIE I2C3SIE INT2IE — I2C2BIE — U5TXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP U1EIF SPI3EIF I2C3BIF OC2IF CAN1IF U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE CAN1IE U2TXIE IC2IE USBIE U2RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE INT1IE U3TXIE I2C4MIE — U6RXIE — — — — — — — — DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) SPI2TXIE SPI2RXIE SPI1TXIE SPI1RXIE SPI1EIE IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF INT1IF U3TXIF SPI2TXIF I2C4MIF — U6RXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) SPI1TXIF SPI1RXIF SPI1EIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2C1BIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — SPI3TXIF I2C3MIF T3IF — I2C2SIF — — U1TXIE 1040 IFS1 15:0 31:16 15:0 31:16 15:0 31:16 1050 IFS2 1060 IEC0 SPI3TXIE SPI3RXIE I2C3MIE T3IE — I2C2SIE — — PIC32MX5XX/6XX/7XX 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI4TXIE SPI4RXIE I2C5MIE — U5RXIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: 2: 3: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX534/564 devices. This register does not have associated CLR, SET, and INV registers. TABLE 4-5: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED) Bits All Resets Bit Range DS61156G-page 70 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — INT4IP IC4IP SPI1IP IC5IP AD1IP I2C1IP U3IP INT4IS IC4IS SPI1IS IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) — — — USBIS U5IS U4IS — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) CAN1IS FCEIS U6IS — — — 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) — USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) CAN1IP FCEIP U6IP — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note 1: 2: 3: IPC9 IPC10 IPC11 IPC12 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX534/564 devices. This register does not have associated CLR, SET, and INV registers. © 2009-2011 Microchip Technology Inc. DS61156G-page 71 TABLE 4-6: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF U3RXIF SPI2RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — — — — — U4RXIE — U4EIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP — PMPEIE — IC5EIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE DMA3IE — PMPEIF OC4IE CS1IE DMA2IE — IC5EIF IC4IE CS0IE DMA1IE — IC4EIF T4IE CTIE DMA0IE 0000 0000 0000 0000 0000 CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 1010 1020 INTCON INTSTAT(3) IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF — I2C2BIF — U5TXIF U1RXIE I2C3SIE INT2IE — I2C2BIE — U5TXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP U1EIF SPI3EIF I2C3BIF OC2IF — U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE — U2TXIE IC2IE USBIE U2RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE INT1IE U3TXIE I2C4MIE — U6RXIE — — — — — — — — DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) SPI2TXIE SPI2RXIE SPI1TXIE SPI1RXIE SPI1EIE IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF INT1IF U3TXIF SPI2TXIF I2C4MIF — U6RXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) SPI1TXIF SPI1RXIF SPI1EIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2C1BIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — SPI3TXIF I2C3MIF T3IF ETHIF I2C2SIF — — U1TXIE 1040 IFS1 15:0 31:16 15:0 31:16 15:0 31:16 1050 IFS2 1060 IEC0 SPI3TXIE SPI3RXIE I2C3MIE T3IE ETHIE I2C2SIE — — PIC32MX5XX/6XX/7XX 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI4TXIE SPI4RXIE I2C5MIE — U5RXIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: 2: 3: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX664 devices. This register does note have associated CLR, SET, and INV registers. TABLE 4-6: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) (CONTINUED) Bits All Resets Bit Range DS61156G-page 72 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — INT4IP IC4IP SPI1IP IC5IP AD1IP I2C1IP U3IP INT4IS IC4IS SPI1IS IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) — — — USBIS U5IS U4IS — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) — — — FCEIS U6IS ETHIS 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) — USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) — FCEIP U6IP ETHIP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note 1: 2: 3: IPC9 IPC10 IPC11 IPC12 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX664 devices. This register does note have associated CLR, SET, and INV registers. © 2009-2011 Microchip Technology Inc. DS61156G-page 73 TABLE 4-7: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF U3RXIF SPI2RXIF I2C4SIF — U6EIF OC5IE OC1IE U3RXIE I2C4SIE — U6EIE — — — — — — — — IC5IF IC1IF U3EIF SPI2EIF I2C4BIF — U4TXIF IC5IE IC1IE U3EIE SPI2EIE I2C4BIE — U4TXIE — — — — — — — — — U4RXIE — U4EIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP — PMPEIE — IC5EIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CMP2IE CMP1IE PMPIE AD1IE CNIE 0000 — U4RXIF T5IE T1IE — U4EIF INT4IE INT0IE DMA3IE — PMPEIF OC4IE CS1IE DMA2IE — IC5EIF IC4IE CS0IE DMA1IE — IC4EIF T4IE CTIE DMA0IE 0000 0000 0000 0000 0000 CMP2IF CMP1IF PMPIF AD1IF CNIF 0000 T5IF T1IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 1010 1020 INTCON INTSTAT(3) IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — SRIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1TXIF U1RXIF SPI3RXIF I2C3SIF INT2IF CAN2IF(2) I2C2BIF — U5TXIF U1RXIE I2C3SIE INT2IE CAN2IE(2) I2C2BIE — U5TXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP U1EIF SPI3EIF I2C3BIF OC2IF CAN1IF U2TXIF SPI4TXIF I2C5MIF — U5RXIF U1EIE SPI3EIE I2C3BIE OC2IE CAN1IE U2TXIE IC2IE USBIE U2RXIE I2C5SIE — U5EIE T2IE FCEIE U2EIE SPI4EIE I2C5BIE — U6TXIE INT1IE U3TXIE I2C4MIE — U6RXIE — — — — — — — — DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) SPI2TXIE SPI2RXIE SPI1TXIE SPI1RXIE SPI1EIE IC2IF USBIF U2RXIF SPI4RXIF I2C5SIF — U5EIF T2IF FCEIF U2EIF SPI4EIF I2C5BIF — U6TXIF INT1IF U3TXIF SPI2TXIF I2C4MIF — U6RXIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) SPI1TXIF SPI1RXIF SPI1EIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2C1SIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2C1BIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — SPI3TXIF I2C3MIF T3IF ETHIF I2C2SIF — — U1TXIE 1040 IFS1 15:0 31:16 15:0 31:16 15:0 31:16 1050 IFS2 1060 IEC0 SPI3TXIE SPI3RXIE I2C3MIE T3IE ETHIE I2C2SIE — — PIC32MX5XX/6XX/7XX 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI4TXIE SPI4RXIE I2C5MIE — U5RXIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: 2: 3: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This bit is unimplemented on PIC32MX764F128L device. This register does not have associated CLR, SET, and INV registers. TABLE 4-7: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) Bits All Resets Bit Range DS61156G-page 74 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — INT4IP IC4IP SPI1IP IC5IP AD1IP I2C1IP U3IP INT4IS IC4IS SPI1IS IC5IS AD1IS I2C1IS U3IS SPI2IS I2C4IS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS(2) DMA5IS(2) CAN2IS(2) USBIS U5IS U4IS — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1IP SPI3IP I2C3IP OC4IS T4IS OC5IS T5IS CNIS U1IS SPI3IS I2C3IS CMP2IS PMPIS FSCMIS U2IS SPI4IS I2C5IS DMA2IS DMA0IS DMA6IS(2) DMA4IS(2) CAN1IS FCEIS U6IS ETHIS 0000 0000 0000 0000 0000 0000 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2IP I2C4IP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP(2) DMA5IP(2) CAN2IP(2) USBIP U5IP U4IP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U2IP SPI4IP I2C5IP DMA2IP DMA0IP DMA6IP(2) DMA4IP(2) CAN1IP FCEIP U6IP ETHIP 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 1120 1130 1140 1150 Legend: Note 1: 2: 3: IPC9 IPC10 IPC11 IPC12 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This bit is unimplemented on PIC32MX764F128L device. This register does not have associated CLR, SET, and INV registers. TABLE 4-8: Virtual Address (BF80_#) Bit Range Register Name TIMER1-TIMER5 REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 — — — — — — — — — — — — — — — TCKPS — — — TCKPS — — — TCKPS — — — TCKPS — — — — — — — — — — — — — — — — — T32 — — — — — — — T32 — — — — — — — — — — — — — — — — — — — — — — — — — TCS(2) — — — TCS(2) — — — TCS(2) — — — TCS(2) — — — — — — — — — — — — — — — — — — — 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF © 2009-2011 Microchip Technology Inc. DS61156G-page 75 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 T1CON 0610 0620 TMR1 PR1 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — ON — — — ON — — — ON — — — ON — — — FRZ — — — FRZ — — — FRZ — — — FRZ — — — FRZ — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — TWDIS — — — — — — — — — — — — — — — — — — — TWIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — — — — — — — — — — — TSYNC — — TCS — — — — TCKPS TMR1 PR1 0800 T2CON 0810 0820 TMR2 PR2 TMR2 PR2 0A00 T3CON 0A10 0A20 TMR3 PR3 TMR3 PR3 0C00 T4CON 0C10 0C20 TMR4 PR4 PIC32MX5XX/6XX/7XX TMR4 PR4 0E00 T5CON 0E10 0E20 Legend: Note 1: 2: TMR5 PR5 TMR5 PR5 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on 64-pin devices. DS61156G-page 76 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-9: Virtual Address (BF80_#) Register Name INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP Bits All Resets 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 2010 2200 2210 2400 2410 2600 2610 2800 2810 IC1CON(1) IC1BUF IC2CON(1) IC2BUF IC3CON(1) IC3BUF IC4CON(1) IC4BUF IC5CON(1) IC5BUF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — IC1BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC2BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC3BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC4BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC5BUF Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-10: Virtual Address (BF80_#) Bit Range Register Name OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1) Bits All Resets 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx © 2009-2011 Microchip Technology Inc. DS61156G-page 77 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 OC1CON 3010 3020 OC1R OC1RS 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — OC1R OC1RS — ON — FRZ — SIDL — — — — — — — — — — — — 3200 OC2CON 3210 3220 OC2R OC2RS OC2R OC2RS — ON — FRZ — SIDL — — — — — — — — — — — — 3400 OC3CON 3410 3420 OC3R OC3RS OC3R OC3RS — ON — FRZ — SIDL — — — — — — — — — — — — 3600 OC4CON 3610 3620 OC4R OC4RS PIC32MX5XX/6XX/7XX OC4R OC4RS — ON — FRZ — SIDL — — — — — — — — — — — — 3800 OC5CON 3810 3820 Legend: Note 1: OC5R OC5RS OC5R OC5RS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-11: Virtual Address (BF80_#) Register Name I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1) Bits All Resets Bit Range DS61156G-page 78 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 5010 5020 5030 5040 5050 5060 5100 5110 5120 5130 5140 5150 5160 5200 5210 I2C3CON I2C3STAT I2C5DD I2C3MSK I2C3BRG I2C3TRN I2C3RCV I2C4CON I2C4STAT I2C4ADD I2C4MSK I2C4BRG I2C4TRN I2C4RCV I2C5CON I2C5STAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ACKSTAT — — — — — — — — — — — ON — ACKSTAT — — — — — — — — — — — ON — ACKSTAT — FRZ — TRSTAT — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — FRZ — TRSTAT — SIDL — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — SIDL — — — SCLREL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — SCLREL — — — STRICT — — — — — — — — — — — — STRICT — — — — — — — — — — — — STRICT — — — A10M — BCL — — — — — — — — — — A10M — BCL — — — — — — — — — — A10M — BCL — DISSLW — GCSTAT — — — — — — — — DISSLW — GCSTAT — — — — — — — — DISSLW — GCSTAT — SMEN — ADD10 — — — — — — — — SMEN — ADD10 — — — — — — — — SMEN — ADD10 — GCEN — IWCOL — — — — — — GCEN — IWCOL — — — — — — GCEN — IWCOL — STREN — I2COV — — — — — — STREN — I2COV — — — — — — STREN — I2COV — ACKDT — D/A — — — — — — ACKDT — D/A — — — — — — ACKDT — D/A — ACKEN — P — — — — — — ACKEN — P — — — — — — ACKEN — P — RCEN — S — — — — — — RCEN — S — — — — — — RCEN — S — PEN — R/W — — — — — — PEN — R/W — — — — — — PEN — R/W — RSEN — RBF — — — — — — RSEN — RBF — — — — — — RSEN — RBF — SEN — TBF — — — — — — SEN — TBF — — — — — — SEN — TBF 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1000 0000 0000 ADD MSK Baud Rate Generator Register Transmit Register Receive Register ADD MSK Baud Rate Generator Register Transmit Register Receive Register Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-11: Virtual Address (BF80_#) Register Name I2C1, I2C3, I2C4 AND I2C5 REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 — — — — — RCEN — S — — — — — — — — — — PEN — R/W — — — — — — — — — — RSEN — RBF — — — — — — — — — — SEN — TBF — — — — — 0000 0000 0000 0000 — — — ACKEN — P — — — — — 0000 0000 0000 0000 0000 1000 0000 0000 0000 0000 0000 0000 0000 Transmit Register — — GCEN — IWCOL — — — — — — — STREN — I2COV — — — — — — — ACKDT — D/A — — — — — ADD — — — — — — — — — — — — MSK Baud Rate Generator Register — — — — — — — — Transmit Register Receive Register Receive Register © 2009-2011 Microchip Technology Inc. DS61156G-page 79 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5220 5230 5240 5250 5260 5300 5310 5320 5330 5340 5350 5360 Legend: Note I2C5ADD I2C5MSK I2C5BRG I2C5TRN I2C5RCV I2C1CON I2C1STAT I2C3DD I2C1MSK I2C1BRG I2C1TRN I2C1RCV 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — ON — ACKSTAT — — — — — — — — — — — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — — — — — — — — — — STRICT — — — — — — — — — — — — — — — — — A10M — BCL — — — — — — — — — — — — — DISSLW — GCSTAT — — — — — — — — — SMEN — ADD10 — — — — — — — — — — — — — — — — — — — — ADD MSK Baud Rate Generator Register PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5400 I2C2CON 5410 I2C2STAT 5420 I2C4DD 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ACKSTAT — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — SIDL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — STRICT — — — — — — — — — — — — A10M — BCL — — — — — — — — — — DISSLW — GCSTAT — — — — — — — — SMEN — ADD10 — — — — — — — — GCEN — IWCOL — — — — — — STREN — I2COV — — — — — — ACKDT — D/A — — — — — — ACKEN — P — — — — — — RCEN — S — — — — — — PEN — R/W — — — — — — RSEN — RBF — — — — — — SEN — TBF — — — — — 0000 1000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADD MSK Baud Rate Generator Register Transmit Register Receive Register 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN 5460 I2C2RCV Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156G-page 80 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-12: I2C2 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits © 2009-2011 Microchip Technology Inc. DS61156G-page 81 TABLE 4-13: Virtual Address (BF80_#) Register Name UART1 THROUGH UART6 REGISTER MAP Bits All Resets 0000 0000 0000 FERR — — — — OERR — — — — URXDA — — — — STSEL URXDA — — — — STSEL URXDA — — — — STSEL URXDA — 0110 0000 0000 0000 0000 0000 0000 — LPBACK — ABAUD ADDEN — — — — ABAUD ADDEN — — — — ABAUD ADDEN — — RXINV RIDLE — — — — RXINV RIDLE — — — — RXINV RIDLE — — BRGH PERR — — — — BRGH PERR — — — — BRGH PERR — 0000 0000 0000 FERR — — — — OERR — — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK 0000 0000 0000 FERR — — — — OERR — — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK 0000 0000 0000 FERR — OERR — 0110 0000 0000 PDSEL PDSEL PDSEL Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 U1MODE(1) 6010 6020 6030 6040 U1STA(1) U1TXREG U1RXREG U1BRG(1) (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — ON — — — — — — — ON — — — — — — — ON — — — — FRZ — — — — — — — FRZ — — — — — — — FRZ — — — — — — — FRZ — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — UTXBF — — — — — — — — UTXBF — — — — — — — UTXBF — — — — — — — — UTXBF — — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — RX8 — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — WAKE — LPBACK — ABAUD ADDEN — — — — RXINV RIDLE — — — — BRGH PERR — — — — — — STSEL UEN PDSEL ADDR URXISEL — — — — WAKE — — — UTXISEL Transmit Register Receive Register BRG 6200 U4MODE 6210 6220 6230 6240 6400 6410 6420 6430 6440 6600 6610 6620 U4STA(1) U4TXREG U4RXREG U4BRG(1) U3MODE(1) U3STA(1) U3TXREG U3RXREG U3BRG (1) ADDR URXISEL — — — — WAKE — — — UTXISEL Transmit Register Receive Register PIC32MX5XX/6XX/7XX BRG UEN ADDR URXISEL — — — — WAKE — — — UTXISEL Transmit Register Receive Register BRG U6MODE(1) U6STA(1) U6TXREG ADDR URXISEL — — UTXISEL Transmit Register Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-13: Virtual Address (BF80_#) Register Name UART1 THROUGH UART6 REGISTER MAP (CONTINUED) Bits All Resets Bit Range DS61156G-page 82 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6630 6640 U6RXREG U6BRG(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — ON — — — — — — — ON — — — — — — — — — — FRZ — — — — — — — FRZ — — — — — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — — — UTXBF — — — — — — — — UTXBF — — — — — — RX8 — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — RX8 — — — — WAKE — — — LPBACK — — — ABAUD ADDEN — — — — ABAUD ADDEN — — — — — — RXINV RIDLE — — — — RXINV RIDLE — — — — — — BRGH PERR — — — — BRGH PERR — — — — — — — — — — — — STSEL URXDA — — — — STSEL URXDA — — — 0000 0000 0000 0000 0000 0000 0000 0110 0000 0000 0000 0000 0000 0000 0000 0000 0000 0110 0000 0000 0000 0000 0000 0000 Receive Register BRG UEN PDSEL FERR — — — — OERR — — — — 6800 U2MODE(1) 6810 6820 6830 6840 U2STA(1) U2TXREG U2RXREG U2BRG(1) ADDR URXISEL — — — — WAKE — — — — LPBACK UTXISEL Transmit Register Receive Register BRG PDSEL FERR — — — OERR — — — 6A00 U5MODE(1) 6A10 6A20 6A30 6A40 Legend: Note 1: U5STA(1) U5TXREG U5RXREG U5BRG(1) ADDR URXISEL — — — — — — UTXISEL Transmit Register Receive Register BRG x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-14: Virtual Address (BF80_#) Bit Range Register Name SPI2, SPI3 AND SPI4 REGISTER MAP(1) Bits All Resets 0000 0000 SPIRBF 0008 0000 0000 — — CKP — SPIROV — — MSTEN — SPIRBE — — BRG — CKE SPITUR SSEN — — SRMT — — — — TXBUFELM SPITBE — SPITBF SPIRBF SPIFE STXISEL SRXISEL — — — — 0000 0000 ENHBUF 0000 0000 0000 0008 0000 0000 — — CKP — SPIROV — — MSTEN — SPIRBE — — BRG — CKE SPITUR SSEN — — SRMT — — — — TXBUFELM SPITBE — SPITBF SPIRBF SPIFE STXISEL SRXISEL — — — — 0000 0000 ENHBUF 0000 0000 0000 0008 0000 0000 — — — BRG — — — — 0000 0000 © 2009-2011 Microchip Technology Inc. DS61156G-page 83 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 SPI3CON 5810 SPI3STAT 5820 5830 SPI3BUF SPI3BRG 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 FRMEN ON — — FRMSYNC FRMPOL FRZ — — SIDL — — MSSEN DISSDO — FRMSYPW MODE32 SPIBUSY FRMCNT MODE16 — SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — TXBUFELM SPIFE ENHBUF 0000 STXISEL SPITBE — SRXISEL SPITBF RXBUFELM DATA — — FRMEN ON — — — — FRZ — — — — SIDL — — — — — MSSEN DISSDO — — FRMSYPW MODE32 SPIBUSY — — MODE16 — — — FRMCNT SMP — — 5A00 SPI2CON 5A10 SPI2STAT 5A20 SPI2BUF FRMSYNC FRMPOL RXBUFELM DATA — — FRMEN ON — — — — FRZ — — — — SIDL — — — — — MSSEN DISSDO — — FRMSYPW MODE32 SPIBUSY — — MODE16 — — — FRMCNT SMP — — 5A30 SPI2BRG 5C00 SPI4CON 5C10 SPI4STAT 5C20 SPI4BUF FRMSYNC FRMPOL RXBUFELM PIC32MX5XX/6XX/7XX DATA — — — — — — — — — — — — — — — — 5C30 SPI4BRG Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF80_#) Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5E00 SPI1CON 5E10 SPI1STAT 5E20 SPI1BUF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 FRMEN ON — — FRMSYNC FRMPOL FRZ — — SIDL — — MSSEN DISSDO — FRMSYPW MODE32 SPIBUSY FRMCNT MODE16 — SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — TXBUFELM SPIFE ENHBUF 0000 0000 0000 SPIRBF 0008 0000 0000 STXISEL SPITBE — SRXISEL SPITBF RXBUFELM DATA — — — — — — — — — — — — — — — — — — — BRG — — — — 5E30 SPI1BRG Legend: Note 1: 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range DS61156G-page 84 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-15: SPI1 REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits © 2009-2011 Microchip Technology Inc. DS61156G-page 85 TABLE 4-16: Virtual Address (BF80_#) Register Name Bit Range ADC REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 CH0SA — — PCFG3 — CSSL3 — — PCFG2 — CSSL2 — — PCFG1 — CSSL1 — — PCFG0 — CSSL0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 AD1CON1(1) 9010 9020 AD1CON2(1) AD1CON3(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — VCFG2 — ADRC CH0NB — — PCFG15 — CSSL15 — FRZ — VCFG1 — — — — — PCFG14 — CSSL14 — SIDL — VCFG0 — — — — — PCFG13 — CSSL13 — — — OFFCAL — — — — PCFG12 — CSSL12 — — — — — — — CSCNA — SAMC — FORM — — — — — — — — — BUFS — CH0NA — SSRC — — — — — — PCFG6 — CSSL6 — — — — — — PCFG5 — CSSL5 — CLRASAM — — — — — PCFG4 — CSSL4 — — — — — ASAM — — — SAMP — BUFM — — DONE — ALTS — SMPI ADCS 9040 AD1CHS(1) 9060 AD1PCFG(1) 9050 AD1CSSL (1) CH0SB — — PCFG11 — CSSL11 — — PCFG10 — CSSL10 — — PCFG9 — CSSL9 — — PCFG8 — CSSL8 — — PCFG7 — CSSL7 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB Legend: Note 1: ADC Result Word 0 (ADC1BUF0) ADC Result Word 1 (ADC1BUF1) ADC Result Word 2 (ADC1BUF2) ADC Result Word 3 (ADC1BUF3) ADC Result Word 4 (ADC1BUF4) ADC Result Word 5 (ADC1BUF5) ADC Result Word 6 (ADC1BUF6) ADC Result Word 7 (ADC1BUF7) ADC Result Word 8 (ADC1BUF8) ADC Result Word 9 (ADC1BUF9) ADC Result Word A (ADC1BUFA) ADC Result Word B (ADC1BUFB) PIC32MX5XX/6XX/7XX x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-16: Virtual Address (BF80_#) Register Name Bit Range ADC REGISTER MAP (CONTINUED) Bits All Resets DS61156G-page 86 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ADC Result Word C (ADC1BUFC) ADC Result Word D (ADC1BUFD) ADC Result Word E (ADC1BUFE) ADC Result Word F (ADC1BUFF) 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 87 TABLE 4-17: Virtual Address (BF88_#) Register Name DMA GLOBAL REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 DMACON(1) 3010 DMASTAT 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — FRZ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RDWR — — — — — — DMACH(2) — — — SUSPEND DMABUSY 3020 DMAADDR Legend: Note 1: 2: DMAADDR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMACH bit is not available on PIC32MX534/564/664/764 devices. TABLE 4-18: DMA CRC REGISTER MAP(1) Bits PIC32MX5XX/6XX/7XX 3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 — — — — BYTO — WBO — PLEN — BITO — CRCEN — CRCAPP — CRCTYP — — — — — — CRCCH — 0000 0000 0000 0000 0000 0000 DCRCDATA DCRCXOR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) Bits All Resets Bit Range DS61156G-page 88 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — CHEN CFORCE — CHAED CABORT CHSHIE CHSHIF — CHCHN PATEN CHDDIE CHDDIF — CHAEN SIRQEN CHDHIE CHDHIF — — AIRQEN CHBCIE CHBCIF — CHEDET — CHCCIE CHCCIF — — 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHPRI — CHTAIE CHTAIF — CHERIE CHERIF CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE — — CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF — CHEN — CHAED — CHCHN — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF 3120 DCH1CON 3130 DCH1ECON 3140 3150 DCH1INT DCH1SSA CHAIRQ CHSIRQ CHSSA CHDSA — — — — — — — — — — — — — — — — 3160 DCH1DSA 3170 DCH1SSIZ Legend: Note 1: 2: 0000 0000 CHSSIZ x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) Bits All Resets 0000 0000 — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 0000 0000 CHPRI CHPDAT — CHEN CFORCE — — — — — — CHSDIE CHSDIF © 2009-2011 Microchip Technology Inc. DS61156G-page 89 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 3210 DCH2INT DCH2SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — — — — — — — CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHAIRQ CHSIRQ CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ 3280 DCH2CPTR Legend: Note 1: 2: CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) Bits All Resets Bit Range DS61156G-page 90 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3290 DCH2DAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — CHEN CFORCE — — CHAED CABORT CHSHIE CHSHIF — — CHCHN PATEN CHDDIE CHDDIF — — CHAEN SIRQEN CHDHIE CHDHIF — — — AIRQEN CHBCIE CHBCIF — — CHEDET — CHCCIE CHCCIF — — — — 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT CHAIRQ CHSDIE CHSDIF CHSIRQ — — 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE — — CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF — CHEN — CHAED — CHCHN — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF 3360 DCH4CON 3370 DCH4ECON 3380 3390 DCH4INT DCH4SSA CHAIRQ CHSIRQ CHSSA CHDSA 33A0 DCH4DSA Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) Bits All Resets 0000 0000 — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 CHPRI CHPDAT — CHEN CFORCE — — — — — — CHSDIE CHSDIF © 2009-2011 Microchip Technology Inc. DS61156G-page 91 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 33B0 DCH4SSIZ 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DCH4DAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — — — — — — — — CHSSIZ15:0> CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR 3420 DCH5CON 3430 DCH5ECON 3440 3450 DCH5INT DCH5SSA CHAIRQ CHSIRQ PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 3460 DCH5DSA 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR 34B0 DCH5CSIZ 34C0 DCH5CPTR Legend: Note 1: 2: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) Bits All Resets Bit Range DS61156G-page 92 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 34D0 DCH5DAT 34E0 DCH6CON 34F0 DCH6ECON 3500 3510 DCH6INT DCH6SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — CHEN CFORCE — — CHAED CABORT CHSHIE CHSHIF — — CHCHN PATEN CHDDIE CHDDIF — — CHAEN SIRQEN CHDHIE CHDHIF — — — AIRQEN CHBCIE CHBCIF — — CHEDET — CHCCIE CHCCIF — — — — 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE — — CHSDIE CHSDIF CABORT CHSHIE CHSHIF PATEN CHDDIE CHDDIF — CHEN — CHAED — CHCHN — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR 3590 DCH6DAT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF 35A0 DCH7CON 35B0 DCH7ECON 35C0 DCH7INT CHAIRQ CHSIRQ 35D0 DCH7SSA 35E0 DCH7DSA Legend: Note 1: 2: CHSSA CHDSA x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1,2) (CONTINUED) Bits All Resets 0000 0000 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHPDAT © 2009-2011 Microchip Technology Inc. DS61156G-page 93 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 35F0 DCH7SSIZ 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DCH7DAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. DMA channels 4-7 are note available on PIC32MX534/564/664/764 devices. PIC32MX5XX/6XX/7XX TABLE 4-20: Virtual Address (BF80_#) Bit Range Register Name COMPARATOR REGISTER MAP(1) Bits All Resets Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9800 CVRCON Legend: Note 1: 2: 31:16 15:0 — ON — — — — — — — — — VREFSEL(2) — — — — — CVROE — CVRR — CVRSS — — — — 0000 0100 BGSEL(2) CVR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. These bits are not available on PIC32MX575/675/695/775 devices. On these devices, reset value for CVRCON is 0000. All Resets Bit Range Register Name DS61156G-page 94 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 A000 CM1CON A010 CM2CON A060 CMSTAT Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ON — — — COE — COE — FRZ — CPOL — CPOL — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — COUT — COUT — — — — — — — — — — — — — — — — — CREF — CREF — — — — — — — — — — — — — — — — — C2OUT — — — C1OUT 0000 00C3 0000 00C3 0000 0000 EVPOL EVPOL CCH CCH x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1) Bits Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets(2) Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 95 TABLE 4-22: Virtual Address (BF80_#) Register Name FLASH CONTROLLER REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F400 NVMCON(1) F410 F420 F430 F440 Legend: Note 1: NVMKEY NVMADDR(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — WR — WREN — WRERR — LVDERR — LVDSTAT — — — — — — — — — — — — — — — — — — NVMOP NVMKEY NVMADDR NVMDATA NVMSRCADDR NVMDATA NVMSRC ADDR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-23: SYSTEM CONTROL REGISTER MAP(1,2) Bits PIC32MX5XX/6XX/7XX F000 OSCCON F010 OSCTUN 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — ON — — — — — — — — — — — — — — — — — — — — — PLLODIV COSC — — — — — — — — — — — — — — — — — — — — — — — — — FRCDIV NOSC — — — — — CMR — — — — — — — VREGS — — — CLKLOCK — — — — — EXTR — — SOSCRDY ULOCK — — — — SWR — — — SLOCK — — — — — — PBDIV SLPEN — — SWDTPS — WDTO — — — SLEEP — — — IDLE — — CF — — — — PLLMULT UFRCEN SOSCEN — — — — BOR — — OSWEN — — WDTCLR — POR — SWRST 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TUN 0000 WDTCON F600 RCON F610 RSWRST F230 SYSKEY SYSKEY Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset. Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 6010 6020 6030 Legend: Note TRISA PORTA LATA ODCA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISA15 — RA15 — LATA15 — ODCA15 — TRISA14 — RA14 — LATA14 — ODCA14 — — — — — — — — — — — — — — — — — — — — — — — — — TRISA10 — RA10 — LATA10 — ODCA10 — TRISA9 — RA9 — LATA9 — ODCA9 — — — — — — — — — TRISA7 — RA7 — LATA7 — ODCA7 — TRISA6 — RA6 — LATA6 — ODCA6 — TRISA5 — RA5 — LATA5 — ODCA5 — TRISA4 — RA4 — LATA4 — ODCA4 — TRISA3 — RA3 — LATA3 — ODCA3 — TRISA2 — RA2 — LATA2 — ODCA2 — TRISA1 — RA1 — LATA1 — ODCA1 — TRISA0 — RA0 — LATA0 — ODCA0 0000 C6FF 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: TABLE 4-25: Virtual Address (BF88_#) Bit Range Register Name PORTB REGISTER MAP(1) Bits All Resets 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6040 6050 6060 6070 Legend: Note TRISB PORTB LATB ODCB 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISB15 — RB15 — LATB15 — ODCB15 — TRISB14 — RB14 — LATB14 — ODCB14 — TRISB13 — RB13 — LATB13 — ODCB13 — TRISB12 — RB12 — LATB12 — ODCB12 — TRISB11 — RB11 — LATB11 — ODCB11 — TRISB10 — RB10 — LATB10 — ODCB10 — TRISB9 — RB9 — LATB9 — ODCB9 — TRISB8 — RB8 — LATB8 — ODCB8 — TRISB7 — RB7 — LATB7 — ODCB7 — TRISB6 — RB6 — LATB6 — ODCB6 — TRISB5 — RB5 — LATB5 — ODCB5 — TRISB4 — RB4 — LATB4 — ODCB4 — TRISB3 — RB3 — LATB3 — ODCB3 — TRISB2 — RB2 — LATB2 — ODCB2 — TRISB1 — RB1 — LATB1 — ODCB1 — TRISB0 — RB0 — LATB0 — ODCB0 0000 FFFF 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: All Resets Bit Range Register Name DS61156G-page 96 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-24: PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 TRISC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISC15 — RC15 — LATC15 — ODCC15 — TRISC14 — RC14 — LATC14 — ODCC14 — TRISC13 — RC13 — LATC13 — ODCC13 — TRISC12 — RC12 — LATC12 — ODCC12 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISC4 — RC4 — LATC4 — ODCC4 — TRISC3 — RC3 — LATC3 — ODCC3 — TRISC2 — RC2 — LATC2 — ODCC2 — TRISC1 — RC1 — LATC1 — ODCC1 — — — — — — — — 0000 F00F 0000 xxxx 0000 xxxx 0000 0000 6090 PORTC 60A0 60B0 LATC ODCC Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 2: All Resets Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 97 TABLE 4-26: PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 F000 0000 xxxx 0000 xxxx 0000 0000 Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 6090 60A0 60B0 Legend: Note TRISC PORTC LATC ODCC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISC15 — RC15 — LATC15 — ODCC15 — TRISC14 — RC14 — LATC14 — ODCC14 — TRISC13 — RC13 — LATC13 — ODCC13 — TRISC12 — RC12 — LATC12 — ODCC12 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: TABLE 4-27: PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60C0 60D0 60E0 60F0 Legend: Note TRISD PORTD LATD ODCD 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISD11 — RD11 — LATD11 — ODCD11 — TRISD10 — RD10 — LATD10 — ODCD10 — TRISD9 — RD9 — LATD9 — ODCD9 — TRISD8 — RD8 — LATD8 — ODCD8 — TRISD7 — RD7 — LATD7 — ODCD7 — TRISD6 — RD6 — LATD6 — ODCD6 — TRISD5 — RD5 — LATD5 — ODCD5 — TRISD4 — RD4 — LATD4 — ODCD4 — TRISD3 — RD3 — LATD3 — ODCD3 — TRISD2 — RD2 — LATD2 — ODCD2 — TRISD1 — RD1 — LATD1 — ODCD1 — TRISD0 — RD0 — LATD0 — ODCD0 0000 0FFF 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60C0 TRISD 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISD15 — RD15 — LAT15 — ODCD15 — TRISD14 — RD14 — LAT14 — ODCD14 — TRISD13 — RD13 — LAT13 — ODCD13 — TRISD12 — RD12 — LAT12 — ODCD12 — TRISD11 — RD11 — LATD11 — ODCD11 — TRISD10 — RD10 — LATD10 — ODCD10 — TRISD9 — RD9 — LATD9 — ODCD9 — TRISD8 — RD8 — LATD8 — ODCD8 — TRISD7 — RD7 — LATD7 — ODCD7 — TRISD6 — RD6 — LATD6 — ODCD6 — TRISD5 — RD5 — LATD5 — ODCD5 — TRISD4 — RD4 — LATD4 — ODCD4 — TRISD3 — RD3 — LATD3 — ODCD3 — TRISD2 — RD2 — LATD2 — ODCD2 — TRISD1 — RD1 — LATD1 — ODCD1 — TRISD0 — RD0 — LATD0 — ODCD0 0000 FFFF 0000 xxxx 0000 xxxx 0000 0000 60D0 PORTD 60E0 60F0 Legend: Note 1: LATD ODCD x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156G-page 98 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-28: PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 6110 6120 6130 TRISE PORTE LATE ODCE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISE9 — RE9 — LATE9 — ODCE9 — TRISE8 — RE8 — LATE8 — ODCE8 — TRISE7 — RE7 — LATE7 — ODCE7 — TRISE6 — RE6 — LATE6 — 0DCE6 — TRISE5 — RE5 — LATE5 — ODCE5 — TRISE4 — RE4 — LATE4 — ODCE4 — TRISE3 — RE3 — LATE3 — ODCE3 — TRISE2 — RE2 — LATE2 — ODCE2 — TRISE1 — RE1 — LATE1 — ODCE1 — TRISE0 — RE0 — LATE0 — ODCE0 0000 03FF 0000 xxxx 0000 xxxx 0000 0000 Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 99 TABLE 4-30: PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 00FF 0000 xxxx 0000 xxxx 0000 0000 Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 6110 6120 6130 Legend: Note TRISE PORTE LATE ODCE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISE7 — RE7 — LATE7 — ODCE7 — TRISE6 — RE6 — LATE6 — 0DCE6 — TRISE5 — RE5 — LATE5 — ODCE5 — TRISE4 — RE4 — LATE4 — ODCE4 — TRISE3 — RE3 — LATE3 — ODCE3 — TRISE2 — RE2 — LATE2 — ODCE2 — TRISE1 — RE1 — LATE1 — ODCE1 — TRISE0 — RE0 — LATE0 — ODCE0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: TABLE 4-31: PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 TRISF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISF5 — RF5 — LATF5 — ODCF5 — TRISF4 — RF4 — LATF4 — ODCF4 — TRISF3 — RF3 — LATF3 — ODCF3 — — — — — — — — — TRISF1 — RF1 — LATF1 — ODCF1 — TRISF0 — RF0 — LATF0 — ODCF0 0000 003B 0000 xxxx 0000 xxxx 0000 0000 6150 PORTF 6160 6170 Legend: Note 1: LATF ODCF x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-33: PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 6150 6160 6170 Legend: Note TRISF PORTF LATF ODCF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — TRISF13 — RF13 — LATF13 — ODCF13 — TRISF12 — RF12 — LATF12 — ODCF12 — — — — — — — — — — — — — — — — — — — — — — — — — TRISF8 — RF8 — LATF8 — ODCF8 — — — — — — — — — — — — — — — — — TRISF5 — RF5 — LATF5 — ODCF5 — TRISF4 — RF4 — LATF4 — ODCF4 — TRISF3 — RF3 — LATF3 — ODCF3 — TRISF2 — RF2 — LATF2 — ODCF2 — TRISF1 — RF1 — LATF1 — ODCF1 — TRISF0 — RF0 — LATF0 — ODCF0 0000 313F 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: All Resets Bit Range Register Name DS61156G-page 100 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-32: PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 TRISG 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISG15 — RG15 — LATG15 — ODCG15 — TRISG14 — RG14 — LATG14 — ODCG14 — TRISG13 — RG13 — LATG13 — ODCG13 — TRISG12 — RG12 — LATG12 — ODCG12 — — — — — — — — — — — — — — — — — TRISG9 — RG9 — LATG9 — ODCG9 — TRISG8 — RG8 — LATG8 — ODCG8 — TRISG7 — RG7 — LATG7 — ODCG7 — TRISG6 — RG6 — LATG6 — ODCG6 — — — — — — — — — — — — — — — — — TRISG3 — RG3 — LATG3 — ODCG3 — TRISG2 — RG2 — LATG2 — ODCG2 — TRISG1 — RG1 — LATG1 — ODCG1 — TRISG0 — RG0 — LATG0 — ODCG0 0000 F3CF 0000 xxxx 0000 xxxx 0000 0000 6190 PORTG 61A0 61B0 Legend: Note 1: LATG ODCG x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 101 TABLE 4-34: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 03CC 0000 xxxx 0000 xxxx 0000 0000 Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 TRISG 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISG9 — RG9 — LATG9 — ODCG9 — TRISG8 — RG8 — LATG8 — ODCG8 — TRISG7 — RG7 — LATG7 — ODCG7 — TRISG6 — RG6 — LATG6 — ODCG6 — — — — — — — — — — — — — — — — — TRISG3 — RG3 — LATG3 — ODCG3 — TRISG2 — RG2 — LATG2 — ODCG2 — — — — — — — — — — — — — — — — 6190 PORTG 61A0 61B0 LATG ODCG Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61C0 CNCON 61D0 61E0 Legend: Note 1: CNEN CNPUE 31:16 15:0 31:16 15:0 31:16 15:0 — ON — CNEN15 — — FRZ — CNEN14 — — SIDL — CNEN13 — — — — CNEN12 — — — — CNEN11 — — — — CNEN10 — — — — CNEN9 — CNPUE9 — — — CNEN8 — CNPUE8 — — — CNEN7 — CNPUE7 — — — CNEN6 — CNPUE6 — — CNEN21 CNEN5 CNPUE21 CNPUE5 — — CNEN20 CNEN4 CNPUE20 CNPUE4 — — CNEN19 CNEN3 CNPUE3 — — CNEN18 CNEN2 CNPUE2 — — CNEN17 CNEN1 CNPUE1 — — CNEN16 CNEN0 CNPUE0 0000 0000 0000 0000 0000 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-37: Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61C0 CNCON 61D0 CNEN CNPUE 31:16 15:0 31:16 15:0 31:16 15:0 — ON — CNEN15 — — FRZ — CNEN14 — — SIDL — CNEN13 — — — — CNEN12 — — — — CNEN11 — — — — CNEN10 — — — — CNEN9 — CNPUE9 — — — CNEN8 — CNPUE8 — — — CNEN7 — CNPUE7 — — — CNEN6 — CNPUE6 — — — CNEN5 — CNPUE5 — — — CNEN4 — CNPUE4 — — — CNEN3 — CNPUE3 — — CNEN18 CNEN2 CNPUE2 — — CNEN17 CNEN1 CNPUE1 — — CNEN16 CNEN0 CNPUE0 0000 0000 0000 0000 0000 61E0 Legend: Note CNPUE18 CNPUE17 CNPUE16 0000 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: All Resets Bit Range Register Name DS61156G-page 102 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-36: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1) Bits TABLE 4-38: Virtual Address (BF80_#) Bit Range Register Name PARALLEL MASTER PORT REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — OBUF — — — — — — — — OB3E — — OB2E — — OB1E — — OB0E 0000 0000 0000 008F Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F200 DDPCON Legend: 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — JTAGEN — TROEN — — — TDOEN 0000 0008 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All Resets Bit Range Register Name © 2009-2011 Microchip Technology Inc. DS61156G-page 103 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 PMCON 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — BUSY — — FRZ — — — SIDL — — — — — — — — — PMPTTL — MODE16 — — PTWREN — — — PTRDEN — — — — — — — — — ALP — — — CS2P — — — CS1P — — — — — — — WRSP — — — RDSP — — ADRMUX INCM CSF WAITB ADDR 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7050 7060 Legend: Note 1: PMDIN PMAEN PMSTAT IRQM MODE WAITM WAITE 15:0 CS2EN/A15 CS1EN/A14 DATAOUT DATAIN — — IBF — — IBOV — — — — — — — — IB3F — — IB2F — — IB1F — — IB0F — — OBE PTEN x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. PIC32MX5XX/6XX/7XX TABLE 4-39: PROGRAMMING AND DIAGNOSTICS REGISTER MAP Bits TABLE 4-40: Virtual Address (BF88_#) Register Name PREFETCH REGISTER MAP Bits All Resets Bit Range DS61156G-page 104 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 CHECON(1,2) 4010 CHEACC(1) 4020 CHETAG(1) 31:16 15:0 15:0 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — LMASK — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PFMWS — CHECOH 0000 0007 — 0000 0000 00xx — — — xxx2 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx DCSZ PREFEN 31:16 CHEWEN 31:16 LTAGBOOT — CHEIDX LVALID LLOCK — — LTYPE — — LTAG — — — — — — — LTAG 4030 CHEMSK(1) 4040 4050 4060 4070 4080 4090 40A0 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS CHEW0 CHEW1 CHEW2 CHEW3 — — — — — — — CHELRU CHEHIT CHEMIS CHEPFABT CHELRU 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx 40C0 CHEPFABT Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Reset value is dependent on DEVCFGx configuration. TABLE 4-41: Virtual Address (BF80_#) Bit Range Register Name RTCC REGISTER MAP(1) Bits All Resets 0000 — — RTCWREN RTCSYNC HALFSEC — — — RTCOE — 0000 0000 0000 MIN01 — — — — — — — — — MONTH01 WDAY01 MIN01 — — — MONTH01 WDAY01 xxxx xx00 xxxx xx00 xxxx xx00 00xx xx0x © 2009-2011 Microchip Technology Inc. DS61156G-page 105 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 RTCCON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ALRMEN — FRZ — CHIME — SIDL — PIV — — — ALRMSYNC — — — — — — — — — — RTSECSEL RTCCLKON — — CAL — — 0210 RTCALRM 0220 RTCTIME AMASK HR01 SEC01 YEAR01 DAY01 HR01 SEC01 — — — — — MIN10 — — — — — — — — MONTH10 MIN10 MONTH10 ARPT HR10 SEC10 YEAR10 DAY10 HR10 SEC10 — — — — — DAY10 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: Note 1: — — DAY01 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. PIC32MX5XX/6XX/7XX TABLE 4-42: Virtual Address (BFC0_#) Bit Range Register Name DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Bits All Resets Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F220 DEVID 31:16 15:0 VER DEVID DEVID xxxx xxxx Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information. All Resets Bit Range Register Name DS61156G-page 106 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend: 31:16 FVBUSIO FUSBIDIO 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — UPLLEN — — — — — — — — — — — — — — — CP — — — — — — — FCANIO — — OSCIOFNC — — FETHIO — UPLLIDIV — — — FMIIEN — — BWP — — — — FWDTEN IESO — — — — — — — — — — FPLLMUL — FSOSCEN — — — — — — — FSRSSEL FPLLODIV FPLLIDIV WDTPS FNOSC PWP — DEBUG xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx USERID FCKSM FPBDIV POSCMOD — — — — ICESEL PWP x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-43: DEVICE AND REVISION ID SUMMARY(1) Bits TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — — — — — — — 0000 0000 0000 0000 © 2009-2011 Microchip Technology Inc. DS61156G-page 107 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 5050 U1OTGIR(2) U1OTGIE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — IDIF — IDIE — ID — DPPULUP — UACTPND(4) — STALLIF — STALLIE — BTSEF — BTSEE — — JSTATE — LSPDEN — — (4) — — — — — — — — — — — LSTATE — — — — — ACTVIF — ACTVIE — — — — — IDLEIF — IDLEIE — BTOEF — BTOEE — — USBRST — — BDTPTRL — FRML — — — SESVD — — — TRNIF — TRNIE — DFN8EF — DFN8EE — DIR — HOSTEN — DEVADDR — — — — SESEND — OTGEN — — — SOFIF — SOFIE — CRC16EF — CRC16EE — PPBI — RESUME — — — — — — — — VBUSCHG — — UERRIF — UERRIE — CRC5EF EOFEF — CRC5EE EOFEE — — — PPBRST — — — — VBUSVD — VBUSDIS — — URSTIF — URSTIE — PIDEF — PIDEE — — — USBEN SOFEN — T1MSECIF LSTATEIF T1MSECIE LSTATEIE SESVDIF SESENDIF SESVDIE SESENDIE VBUSVDIF 0000 VBUSVDIE 0000 5060 U1OTGSTAT(3) 5070 5080 U1OTGCON U1PWRC DMPULUP DPPULDWN DMPULDWN VBUSON USLPGRD USBBUSY USUSPEND USBPWR 5200 U1IR(2) 15:0 31:16 ATTACHIF RESUMEIF — — DETACHIF 0000 5210 U1IE 15:0 31:16 ATTACHIE RESUMEIE — BMXEF — BMXEE — — SE0 (4) DETACHIE 0000 — DMAEF — DMAEE — — PKTDIS TOKBUSY — — — 5220 U1EIR(2) 15:0 31:16 PIC32MX5XX/6XX/7XX 5230 U1EIE 15:0 31:16 15:0 31:16 5240 U1STAT (3) ENDPT(4) 5250 U1CON 15:0 31:16 15:0 31:16 15:0 31:16 15:0 5260 5270 5280 U1ADDR U1BDTP1 U1FRML (3) — — — Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61156G-page 108 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5290 52A0 52B0 52C0 52D0 52E0 5300 5310 5320 5330 5340 5350 5360 5370 5380 5390 53A0 U1FRMH(3) U1TOK U1SOF U1BDTP2 U1BDTP3 U1CNFG1 U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 U1EP9 U1EP10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — UTEYE — LSPD — — — — — — — — — — — — — — — — — — — — — — — PID — — — — UOEMON — RETRYDIS — — — — — — — — — — — — — — — — — — — — — — — — — — — USBFRZ — — — — — — — — — — — — — — — — — — — — — — — — — — CNT — — — USBSIDL — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — — — — — — — — — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — — EP — — — — — — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — FRMH — — — — — — — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — — — — — — — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 BDTPTRH BDTPTRU UASUSPND 0001 Legend: Note 1: 2: 3: 4: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 © 2009-2011 Microchip Technology Inc. DS61156G-page 109 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 53B0 53C0 53D0 53E0 53F0 Legend: Note 1: 2: 3: 4: U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. This register does not have associated SET and INV registers. This register does not have associated CLR, SET and INV registers. Reset value for this bit is undefined. PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 B000 B010 B020 B030 B040 B050 B060 B070 B080 B090 B0A0 C1CON C1CFG C1INT C1VEC C1TREC C1FSTAT C1RXOVF C1TMR C1RXM0 C1RXM1 C1RXM2 C1RXM3 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 — ON — IVRIE IVRIF — — — — FRZ — SAM WAKIE WAKIF — — — FIFOIP30 FIFOIP14 — SIDLE — CERRIE CERRIF — — — — — — SEG1PH SERRIE SERRIF — — ABAT CANBUSY — RBOVIE RBOVIF — — — — — — — REQOP — — PRSEG — — — — FIFOIP25 FIFOIP9 RXOVF9 — — — — FIFOIP24 FIFOIP8 RXOVF24 RXOVF8 — — — — — — — — — FIFOIP23 FIFOIP7 RXOVF7 OPMOD — WAKFIL — — — — FIFOIP22 FIFOIP6 RXOVF6 — — — — — TXBO FIFOIP21 FIFOIP5 RXOVF5 CANCAP — — — — TXBP FIFOIP20 FIFOIP4 RXOVF4 — — BRP MODIE MODIF — ICODE RXBP FIFOIP19 FIFOIP3 RXOVF3 — DNCNT — SEG2PH — 0480 0000 0000 0000 15:0 SEG2PHTS SJW CTMRIE CTMRIF — RBIE RBIF — TBIE TBIF — 0000 0000 0000 0040 FILHIT — FIFOIP26 FIFOIP10 TERRCNT TXWARN RXWARN EWARN 0000 0000 RERRCNT FIFOIP2 RXOVF2 FIFOIP1 RXOVF1 31:16 FIFOIP31 15:0 FIFOIP15 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP18 FIFOIP17 FIFOIP16 0000 FIFOIP0 0000 RXOVF0 0000 0000 0000 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 15:0 15:0 FLTEN3 FLTEN1 FLTEN7 FLTEN5 FLTEN9 FLTEN13 MSEL3 MSEL1 MSEL7 MSEL5 MSEL11 MSEL9 MSEL15 MSEL13 FSEL3 FSEL1 FSEL7 FSEL5 FSEL11 FSEL9 FSEL15 FSEL13 SID SID SID SID RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 CANTS CANTSPRE -— EID -— EID -— EID -— EID FLTEN2 FLTEN0 FLTEN6 FLTEN4 FLTEN10 FLTEN8 FLTEN14 FLTEN12 MSEL2 MSEL0 MSEL6 MSEL4 MSEL10 MSEL8 MSEL14 MSEL12 FSEL2 FSEL0 FSEL6 FSEL4 FSEL10 FSEL8 FSEL14 FSEL12 MIDE — EID MIDE — EID MIDE — EID MIDE — EID xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 B0B0 B0C0 C1FLTCON0 B0D0 C1FLTCON1 B0E0 C1FLTCON2 B0F0 C1FLTCON3 Legend: Note 1: 31:16 FLTEN11 31:16 FLTEN15 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156G-page 110 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H, PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 EID xxxx xxxx 0000 0000 — TXABAT — — — TXLARB — — TXERR — — TXREQ FSIZE RTREN TXPRI 0000 0000 © 2009-2011 Microchip Technology Inc. DS61156G-page 111 Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 B100 C1FLTCON4 B110 C1FLTCON5 B120 C1FLTCON6 B130 C1FLTCON7 B140 B340 C1RXFn (n = 0-31) C1FIFOBA 31:16 FLTEN19 15:0 15:0 15:0 15:0 31:16 15:0 31:16 15:0 — — — — FLTEN17 FLTEN21 FLTEN25 FLTEN29 31:16 FLTEN23 31:16 FLTEN27 31:16 FLTEN31 MSEL19 MSEL17 MSEL23 MSEL21 MSEL27 MSEL25 MSEL31 MSEL29 FSEL19 FSEL17 FSEL23 FSEL21 FSEL27 FSEL25 FSEL31 FSEL29 SID FLTEN18 FLTEN16 FLTEN22 FLTEN20 FLTEN26 FLTEN24 FLTEN30 FLTEN28 EID C1FIFOBA MSEL18 MSEL16 MSEL22 MSEL20 MSEL26 MSEL24 MSEL30 MSEL28 -— EXID FSEL18 FSEL16 FSEL22 FSEL20 FSEL26 FSEL24 FSEL30 FSEL28 — C1FIFOCONn 31:16 B350 (n = 0-31) 15:0 B360 C1FIFOINTn (n = 0-31) 31:16 15:0 — FRESET — — — UINC — — — DONLY — — — — — — — — — — — — — TXEN — — TXNFULLIE TXHALFIE TXEMPTYIE TXNFULLIF TXHALFIF TXEMPTYIF RXN RXOVFLIE RXFULLIE RXHALFIE 0000 EMPTYIE RXOVFLIF RXFULLIF RXHALFIF RXN 0000 EMPTYIF 0000 0000 PIC32MX5XX/6XX/7XX B370 B380 C1FIFOUAn 31:16 (n = 0-31) 15:0 C1FIFOCIn 31:16 (n = 0-31) 15:0 — — — — — — — — — — — — — — C1FIFOUA — — — — — — — — — — — C1FIFOCI — — 0000 0000 Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) DS61156G-page 112 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4-46: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0480 0000 0000 0000 RBIE RBIF — RXWARN FIFOIP17 FIFOIP1 RXOVF1 TBIE TBIF — EWARN 0000 0000 0000 0040 TXWARN FIFOIP18 FIFOIP2 RXOVF2 0000 0000 FIFOIP16 0000 FIFOIP0 RXOVF0 0000 0000 0000 0000 -— EID SID EID SID EID SID EID FLTEN3 FLTEN1 FLTEN7 FLTEN5 FLTEN9 FLTEN13 MSEL3 MSEL1 MSEL7 MSEL5 MSEL11 MSEL9 MSEL15 MSEL13 FSEL3 FSEL1 FSEL7 FSEL5 FSEL11 FSEL9 FSEL15 FSEL13 FLTEN2 FLTEN0 FLTEN6 FLTEN4 FLTEN10 FLTEN8 FLTEN14 FLTEN12 MSEL2 MSEL0 MSEL6 MSEL4 MSEL10 MSEL8 MSEL14 MSEL12 FSEL2 FSEL0 FSEL6 FSEL4 FSEL10 FSEL8 FSEL14 FSEL12 -— MIDE — EID -— MIDE — EID -— MIDE — EID MIDE — EID xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 C000 C010 C020 C030 C040 C050 C060 C070 C080 C0A0 C0B0 C0B0 C2CON C2CFG C2INT C2VEC C2TREC C2FSTAT C2RXOVF C2TMR C2RXM0 C2RXM1 C2RXM2 C2RXM3 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 — ON — IVRIE IVRIF — — — — FRZ — SAM WAKIE WAKIF — — — — SIDLE — CERRIE CERRIF — — — — — — SEG1PH SERRIE SERRIF — — ABAT CANBUSY — RBOVIE RBOVIF — — FIFOIP27 FIFOIP11 — — — — — REQOP — — PRSEG — — — — FIFOIP25 FIFOIP9 RXOVF9 — — — — FIFOIP24 FIFOIP8 RXOVF24 RXOVF8 — — — — — — — — — FIFOIP23 FIFOIP7 RXOVF7 OPMOD — WAKFIL — — — — FIFOIP22 FIFOIP6 RXOVF6 — — — — — TXBO FIFOIP21 FIFOIP5 RXOVF5 CANCAP — — — — TXBP FIFOIP20 FIFOIP4 RXOVF4 — — — DNCNT — SEG2PH — 15:0 SEG2PHTS SJW BRP MODIE MODIF — ICODE RXBP FIFOIP19 FIFOIP3 RXOVF3 RERRCNT CTMRIE CTMRIF — FILHIT — FIFOIP26 FIFOIP10 TERRCNT 31:16 FIFOIP31 15:0 FIFOIP15 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP14 FIFOIP13 FIFOIP12 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 15:0 15:0 SID RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 CANTS CANTSPRE C0C0 C2FLTCON0 C0D0 C2FLTCON1 C0E0 C2FLTCON2 C0F0 C2FLTCON3 Legend: Note 1: 31:16 FLTEN11 31:16 FLTEN15 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-46: Virtual Address (BF88_#) CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 EID xxxx xxxx 0000 0000 — TXABAT — — — TXLARB — — TXERR — — TXREQ FSIZE RTREN TXPRI 0000 0000 © 2009-2011 Microchip Technology Inc. DS61156G-page 113 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 C100 C2FLTCON4 C110 C2FLTCON5 C120 C2FLTCON6 C130 C2FLTCON7 C140 C340 C2RXFn (n = 0-31) C2FIFOBA 31:16 FLTEN19 15:0 15:0 15:0 15:0 31:16 15:0 31:16 15:0 — — — — FLTEN17 FLTEN21 FLTEN25 FLTEN29 31:16 FLTEN23 31:16 FLTEN27 31:16 FLTEN31 MSEL19 MSEL17 MSEL23 MSEL21 MSEL27 MSEL25 MSEL31 MSEL29 FSEL19 FSEL17 FSEL23 FSEL21 FSEL27 FSEL25 FSEL31 FSEL29 SID FLTEN18 FLTEN16 FLTEN22 FLTEN20 FLTEN26 FLTEN24 FLTEN30 FLTEN28 EID C2FIFOBA MSEL18 MSEL16 MSEL22 MSEL20 MSEL26 MSEL24 MSEL30 MSEL28 -— EXID FSEL18 FSEL1674)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS61156G-page 228 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± [[ PP %RG\  PP >74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 NOTE 2 A c β φ L A1 L1 A2 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E   ƒ ƒ ƒ ±    0,1 0,//,0(7(56 120   %6& ±  ±   5() ƒ  %6&  %6&  %6&  %6& ±  ƒ ƒ   ƒ ƒ ƒ     0$; 1RWHV  3LQ  YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD  &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\  'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG  PP SHU VLGH  'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( 74)3@ 1RWH )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWSZZZPLFURFKLSFRPSDFNDJLQJ DS61156G-page 232 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS61156G-page 233 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 234 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS61156G-page 235 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 236 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging © 2009-2011 Microchip Technology Inc. DS61156G-page 237 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156G-page 238 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES Table A-1 outlines the peripherals and associated interrupts that are implemented differently on PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX devices. In addition, on the SPI module, the IRQ numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25. This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below. A.1 DMA not support PIC32MX5XX/6XX/7XX devices do stopping DMA transfers in Idle mode. A.2 Interrupts PIC32MX5XX/6XX/7XX devices have persistent interrupts for some of the peripheral modules. This means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. For example, to clear a UART receive interrupt, the user application must first read the UART Receive register to clear the interrupt condition and then clear the associated UxIF flag to clear the pending UART interrupt. In other words, the UxIF flag cannot be cleared by software until the UART Receive register is read. TABLE A-1: Module PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION DIFFERENCES Interrupt Implementation Input Capture SPI To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ICI bits). Receive and transmit interrupts are controlled by the SRXISEL and STXISEL bits, respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF register to obtain the number of data to receive/transmit below the level specified by the SRXISEL and STXISEL bits. TX interrupt will be generated as soon as the UART module is enabled. Receive and transmit interrupts are controlled by the URXISEL and UTXISEL bits, respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or UxTXREG registers to obtain the number of data to receive/transmit below the level specified by the URXISEL and UTXISEL bits. All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source. To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT) register. UART ADC PMP © 2009-2011 Microchip Technology Inc. DS61156G-page 239 PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision B (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits. Other major changes are referenced by their respective chapter/section in Table B-1. Revision A (August 2009) This is the initial released version of this document. TABLE B-1: MAJOR SECTION UPDATES Update Description Section Name “High-Performance, USB, CAN and Added the following devices: Ethernet 32-bit Flash - PIC32MX575F256L Microcontrollers” - PIC32MX695F512L - PIC32MX695F512H The 100-pin TQFP pin diagrams have been updated to reflect the current pin name locations (see the “Pin Diagrams” section). Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: “PIC32 USB and CAN – Features” Added the following tables: - Table 4: “Pin Names: PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L and PIC32MX575F512L Devices” - Table 5: “Pin Names: PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L Devices” - Table 6: “Pin Names: PIC32MX775F256L, PIC32MX775F512L and PIC32MX795F512L Devices” Updated the following pins as 5V tolerant: - 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2) 2.0 “Guidelines for Getting Started with 32-bit Microcontrollers” Removed the last sentence of 2.3.1 “Internal Regulator Mode”. Removed Section 2.3.2 “External Regulator Mode” DS61156G-page 240 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name 4.0 “Memory Organization” Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-4 to include the PIC32MX575F256L device. Updated the title of Figure 4-6 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device. Updated the title of Table 4-5 to include the PIC32MX575F5256L device. Updated the title of Table 4-6 to include the PIC32MX695F512L device. Reversed the order of Table 4-11 and Table 4-12. Reversed the order of Table 4-14 and Table 4-15. Updated the title of Table 4-15 to include the PIC32MX575F256L and PIC32MX695F512L devices. Updated the title of Table 4-45 to include the PIC32MX575F256L device. Updated the title of Table 4-47 to include the PIC32MX695F512H and PIC32MX695F512L devices. 12.0 “I/O Ports” 22.0 “10-bit Analog-to-Digital Converter (ADC)” 28.0 “Special Features” Updated the second paragraph of 12.1.2 “Digital Inputs” and removed Table 12-1. Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). Removed references to the ENVREG pin in 28.3 “On-Chip Voltage Regulator”. Updated the first sentence of 28.3.1 “On-Chip Regulator and POR” and 28.3.2 “On-Chip Regulator and BOR”. Updated the Connections for the On-Chip Regulator (see Figure 28-2). 31.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 31-3). Updated the Operating Current (IDD) DC Characteristics (see Table 31-5). Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6). Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7). Removed Note 1 from the Program Flash Memory Wait State Characteristics (see Table 31-12). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 31-13). 32.0 “Packaging Information” “Product Identification System” Added the 121-pin XBGA package marking information and package details. Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed. © 2009-2011 Microchip Technology Inc. DS61156G-page 241 PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Update Description Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Added the following devices: • • • • • • • • • • PIC32MX675F256H PIC32MX775F256H PIC32MX775F512H PIC32MX675F256L PIC32MX775F256L PIC32MX775F512L EREFCLK ECRSDV AEREFCLK AECRSDV Added the following pins: 1.0 “Device Overview” Added the EREFCLK and ECRSDV pins to Table 5 and Table 6. Updated the pin number pinout I/O descriptions for the following pin names in Table 1-1: • SCL3 • SDA3 • SCL2 • SDA2 • SCL4 • SDA4 • SCL5 • SDA5 • TMS • TCK • TDI • TDO • RTCC • CVREF• CVREF+ • CVREFOUT • C1IN• C1IN+ • C1OUT • C2IN• C2IN+ • C2OUT • PMA0 • PMA1 Added the following pins to the Pinout I/O Descriptions table (Table 1-1): • EREFCLK • ECRSDV • AEREFCLK • AECRSDV Added new devices and updated the virtual and physical memory map values in Figure 4-4. Added new devices to Figure 4-5. Added new devices to the following register maps: • • • • • • • • Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps) Table 4-12 (I2C2 Register Map) Table 4-15 (SPI1 Register Map) Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps) Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps) Table 4-45 (CAN1 Register Map) Table 4-46 (CAN2 Register Map) Table 4-47 (Ethernet Controller Register Map) 4.0 “Memory Organization” 28.0 “Special Features” Appendix A: “Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices” Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device Configuration Word Summary). Changed all references of POSCMD to POSCMOD in the Device Configuration Word 1 register (see Register 28-2). Added the new section Appendix . DS61156G-page 242 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Revision D (May 2010) The revision includes the following updates, as described in Table B-3: TABLE B-3: MAJOR SECTION UPDATES Update Description Section Name “High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers” Updated the initial Flash memory range to 64K. Updated the initial SRAM memory range to 16K. Added the following devices (see Table 1, Table 2, Table 3 and the Pin Diagrams): • • • • • • • • • • • • PIC32MX534F064H PIC32MX564F064H PIC32MX664F064H PIC32MX564F128H PIC32MX664F128H PIC32MX764F128H PIC32MX534F064L PIC32MX564F064L PIC32MX664F064L PIC32MX564F128L PIC32MX664F128L PIC32MX764F128L 4.0 “Memory Organization” Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3). The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was changed to I2C1BIF in the Interrupt Register Map tables (Table 4-2, Table 4-3, Table 4-4, Table 4-5, Table 4-6 and Table 4-7) Added the following devices to the Interrupt Register Map (Table 4-2): • PIC32MX534F064H • PIC32MX564F064H • PIC32MX564F128H Added the following devices to the Interrupt Register Map (Table 4-3): • PIC32MX664F064H • PIC32MX664F128H Added the following device to the Interrupt Register Map (Table 4-4): • PIC32MX764F128H Added the following devices to the Interrupt Register Map (Table 4-5): • PIC32MX534F064L • PIC32MX564F064L • PIC32MX564F128L Added the following devices to the Interrupt Register Map (Table 4-6): • PIC32MX664F064L • PIC32MX664F128L Added the following device to the Interrupt Register Map (Table 4-7): • PIC32MX764F128L © 2009-2011 Microchip Technology Inc. DS61156G-page 243 PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name 4.0 “Memory Organization” (Continued) Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 Register Map (Table 4-11): • • • • • • • I2C3BRG SFR: I2C1BRG was changed to I2C3BRG I2C4BRG SFR: I2C1BRG was changed to I2C4BRG I2C5BRG SFR: I2C1BRG was changed to I2C5BRG I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA I2C4RCV SFR: I2CR2DATA was changed to I2CR2ADATA I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA I2C5RCV SFR: I2CR1DATA was changed to I2CR3ADATA Added the RTSMD bit and UEN bits to the UART1A, UART1B, UART2A, UART2B, UART3A and UART3B Register Map (Table 4-13) Added the SIDL bit to the DMA Global Register Map (Table 4-17). Changed the CM bit to CMR in the System Control Register Map (Table 4-23). Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD, PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12, Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35 and Table 4-36): • • • • • • PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX664F064L PIC32MX664F128L PIC32MX764F128L Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30, Table 4-32, Table 4-34 and Table 4-37): • • • • • • • • • • • • • • • • • • • • PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX664F064H PIC32MX664F128H PIC32MX764F128H PIC32MX534F064H PIC32MX564F064H PIC32MX564F128H PIC32MX764F128H PIC32MX534F064L PIC32MX564F064L PIC32MX564F128L PIC32MX764F128L PIC32MX664F064H PIC32MX664F128H PIC32MX764F128H PIC32MX664F064L PIC32MX664F128L PIC32MX764F128L Added the following devices to the CAN1 Register Map (Table 4-45): Added the following devices to the Ethernet Controller Register Map (Table 4-47): DS61156G-page 244 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-3: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name 31.0 “Electrical Characteristics” Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in Table 31-5. Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in Table 31-6. Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD) in Table 31-7. Added DC Characteristics: Program Memory parameters D130a and D132a in Table 31-11. Added the Internal Voltage Reference parameter (D305) to the Comparator Specifications in Table 31-13. © 2009-2011 Microchip Technology Inc. DS61156G-page 245 PIC32MX5XX/6XX/7XX Revision E (July 2010) Minor corrections were incorporated throughout the document. Revision F (December 2010) The revision includes the following global update: VCAP/VDDCORE has been changed to: VCAP/VCORE Other major changes are referenced by their respective chapter/section in Table B-4: TABLE B-4: SECTION UPDATES Update Description Section Name Removed the following Analog Feature: FV tolerant input pins High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers (digital pins only) Updated the term LIN 1.2 support as LIN support for the peripheral feature: Six UART modules with: RS-232, RS-485, and LIN support Updated the value of 64-pin QFN/TQFP pin number for the following pin names: PMA0, PMA1 and ECRSDV The following register map tables were updated: • Table 4-2: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8-24/10 to SRIPL in INTSTAT - Changed bits 25/9/-24/8 to U5IS in IPC12 - Added note 2 • Table 4-3 through Table 4-7: - Changed bits 24/8-24/10 to SRIPL in INTSTAT - Changed bits 25/9-24/8 to U5IS in IPC12 • Table 4-3: - Changed bits 24/8 to I2C5BIF in IFS1 - Added note 2 • Table 4-4: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8 to I2C5BIE in IEC1 - Added note 2 references • Table 4-5: - Changed bits 24/8 to I2C5BIF in IFS1 - Changed bits 24/8 to I2C5BIE in IEC1 - Added note 2 references • Table 4-6: - Changed bit 24/8 to I2C5BIF in IFS1 - Updated the bit value of bit 24/8 as I2C5BIE for the IEC1 register. - Added note 2 • Table 4-7: - Changed bit 25/9 to I2C5SIF in IFS1 - Changed bit 24/8 as I2C5BIF in IFS1 - Changed bit 25/9 as I2C5SIE in IEC1 - Changed bit 24/8 as I2C5BIE in IEC1 - Added note 2 references • Added note 2 to Table 4-8 • Updated the All Resets values for the following registers in Table 4-11: I2C3CON, I2C4CON, I2C5CON and I2C1CON. • Updated the All Resets values for the I2C2CON register in Table 4-12 1.0 “Device Overview” 4.0 “Memory Organization” DS61156G-page 246 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Update Description Section Name 4.0 “Memory Organization” (Continued) • Table 4-13: - Changed register U4RG to U1BRG - Changed register U5RG to U3BRG - Changed register U6RG to U2BRG • Table 4-14: - Updated the All Resets values for the following registers: SPI3STAT, SPI2STAT and SPI4STAT • Table 4-15: Updated the All Resets values for the SPI1STAT register • Table 4-17: Added note 2 • Table 4-19: Added note 2 • Table 4-20: Updated the All Resets values for the CM1CON and CM2CON registers • Table 4-21: - Updated the All Resets values as 0000 for the CVRCON register - Updated note 2 • Table 4-38: Updated the All Resets values for the PMSTAT register • Table 4-40: Updated the All Resets values for the CHECON and CHETAG registers • Table 4-42: Updated the bit value of bit 29/13 as ‘—’ for the DEVCFG3 register • Table 4-44: - Updated the note references in the entire table - Changed existing note 1 to note 4 - Added notes 1, 2 and 3 - Changed bits 23/7 in U1PWRC to UACTPND - Changed register U1DDR to U1ADDR - Changed register U4DTP1 to U1BDTP1 - Changed register U4DTP2 to U1BDTP2 - Changed register U4DTP3 to U1BDTP3 • Table 4-45: - Updated the All Resets values for the C1CON and C1VEC registers - Changed bits 30/14 in C1CON to FRZ - Changed bits 27/11 in C1CON to CANBUSY - Changed bits 22/6-16/0 in C1VEC to ICODE - Changed bits 22/6-16/0 in C1TREC to RERRCNT - Changed bits 31/15-24/8 in C1TREC to TERRCNT • Table 4-46: - Updated the All Resets values for the C2CON and C2VEC registers - Changed bits 30/14 in C1CON to FRZ - Changed bits 27/11 in C1CON to CANBUSY - Changed bits 22/6-16/0 in C1VEC register to ICODE - Changed bits 22/6-16/0 in C1TREC register to RERRCNT - Changed bits 31/15-24/8 in C1TREC to TERRCNT © 2009-2011 Microchip Technology Inc. DS61156G-page 247 PIC32MX5XX/6XX/7XX TABLE B-4: SECTION UPDATES (CONTINUED) Update Description Section Name 7.0 “Interrupt Controller” 8.0 “Oscillator Configuration” 16.0 “Output Compare” 24.0 “Ethernet Controller” 26.0 “Comparator Voltage Reference (CVREF)” 28.0 “Special Features” 31.0 “Electrical Characteristics” • Updated the following Interrupt Sources in Table 7-1: - Changed IC2AM – I2C4 Master Event to: IC4M – I2C4 Master Event - Changed IC3AM – I2C5 Master Event to: IC5M – I2C4 Master Event - Changed U1E – UART1A Error to: U1E – UART1 Error - Changed U4E – UART1B Error to: U4E – UART4 Error - Changed U1RX – UART1A Receiver to: U1RX – UART1 Receiver - Changed U4RX – UART1B Receiver to: U4RX – UART4 Receiver - Changed U1TX – UART1A Transmitter to: U1TX – UART1 Transmitter - Changed U4TX – UART1B Transmitter to: U4TX – UART4 Transmitter - Changed U6E – UART2B Error to: U6E – UART6 Error - Changed U6RX – UART2B Receiver to: U6RX – UART6 Receiver - Changed U6TX – UART2B Transmitter to: U6TX – UART6 Transmitter - Changed U5E – UART3B Error to: U5E – UART5 Error - Changed U5RX – UART3B Receiver to: U5RX – UART5 Receiver - Changed U5TX – UART3B Transmitter to: U5TX – UART5 Transmitter Updated Figure 8-1 Updated Figure 16-1 Added a note on using the Ethernet controller pins (see note above Table 24-3) Updated the note in Figure 26-1 Updated the bit description for bit 10 in Register 28-2 Added notes 1 and 2 to Register 28-4 Updated the Absolute Maximum Ratings: • Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V 0.3V to +3.6V was updated • Voltage on VBUS with respect to VSS - 0.3V to +5.5V was added Updated the maximum value of DC16 as 2.1 in Table 31-4 Updated the Typical values for the following parameters: DC20b, DC20c, DC21c, DC22c and DC23c (see Table 31-5) Updated Table 31-11: • Removed the following DC Characteristics: Programming temperature 0°C ≤TA ≤+70°C (25°C recommended) • Updated the Minimum value for the Parameter number D131 as 2.3 • Removed the Conditions for the following Parameter numbers: D130, D131, D132, D135, D136 and D137 • Updated the condition for the parameter number D130a and D132a Updated the Minimum, Typical and Maximum values for parameter D305 in Table 31-13 Added note 2 to Table 31-18 Updated the Minimum and Maximum values for parameter F20b (see Table 31-19) Updated the following figures: • Figure 31-4 • Figure 31-9 • Figure 31-19 • Figure 31-20 Removed the A.3 Pin Assignments sub-section. Appendix A: “Migrating from PIC32MX3XX/4XX to PIC32MX5XX/ 6XX/7XX Devices” DS61156G-page 248 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Revision G (May 2011) The revision includes the following global update: • All references to VDDCORE/VCAP have been changed to: VCORE/VCAP • Added references to the new V-Temp temperature range: -40ºC to +105ºC This revision also includes minor typographical and formatting changes throughout the data sheet text. Major updates are referenced by their respective section in the following table. TABLE B-5: MAJOR SECTION UPDATES Section Name Update Description High-Performance, USB, CAN and Ethernet 32-bit Flash Microcontrollers 1.0 “Device Overview” Removed the shading for all D- and D+ pins in all pin diagrams. Updated the VBUS description in Table 1-1. 2.0 “Guidelines for Getting Started with Added 2.11 “Referenced Sources”. 32-bit Microcontrollers” 4.0 “Memory Organization” Added Note 3 to the Interrupt Register Map tables (see Table 4-2 through Table 4-7. 22.0 “10-bit Analog-to-Digital Converter Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). (ADC)” 26.0 “Comparator Voltage Reference (CVREF)” 28.0 “Special Features” 31.0 “Electrical Characteristics” Updated the Comparator Voltage Reference Block Diagram (see Figure 26-1). Removed the second paragraph from 28.3.1 “On-Chip Regulator and POR”. Added the new V-Temp temperature range (-40ºC to +105ºC) to the heading of all specification tables. Updated the Ambient temperature under bias, updated the Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added Voltage on VBUS with respect to Vss in Absolute Maximum Ratings. Added the characteristic, DC5a to Operating MIPS vs. Voltage (see Table 31-1). Updated or added the following parameters to the Operating Current (IDD) DC Characteristics: DC20, DC20b, DC23, and DC23b (see Table 31-5). Added the following parameters to the Idle Current (IIDLE) DC Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see Table 31-6). Added the following parameters to the Power-down Current (IPD) DC Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 31-7). Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing Requirements (Master Mode) (see Table 31-32). Updated the 10-bit ADC Conversion Rate Parameters (see Table 31-37). Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion Timing Requirements (see Table 31-38). 32.0 “Packaging Information” Product Identification System Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) – 9x9x0.9 mm Body [QFN] packing diagram. Added the new V-Temp (V) temperature information. © 2009-2011 Microchip Technology Inc. DS61156G-page 249 PIC32MX5XX/6XX/7XX NOTES: DS61156G-page 250 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX INDEX A AC Characteristics ............................................................ 194 10-bit Conversion Rate Parameters.......................... 216 ADC Specifications ................................................... 214 Analog-to-Digital Conversion Requirements............. 217 EJTAG Timing Requirements ................................... 224 Ethernet .................................................................... 213 Internal FRC Accuracy.............................................. 196 Internal RC Accuracy ................................................ 197 OTG Electrical Specifications ................................... 223 Parallel Master Port Read Requirements ................. 221 Parallel Master Port Write ......................................... 222 Parallel Master Port Write Requirements.................. 222 Parallel Slave Port Requirements ............................. 220 PLL Clock Timing...................................................... 196 Analog-to-Digital Converter (ADC).................................... 153 Assembler MPASM Assembler................................................... 180 D DC Characteristics............................................................ 184 I/O Pin Input Specifications ...................................... 189 I/O Pin Output Specifications.................................... 190 Idle Current (IIDLE) .................................................... 186 Operating Current (IDD) ............................................ 185 Power-Down Current (IPD)........................................ 187 Program Memory...................................................... 191 Temperature and Voltage Specifications.................. 184 Development Support ....................................................... 179 Direct Memory Access (DMA) Controller.......................... 129 E Electrical Characteristics .................................................. 183 AC............................................................................. 194 Errata .................................................................................. 29 Ethernet Controller............................................................ 157 External Clock Timer1 Timing Requirements ................................... 200 Timer2, 3, 4, 5 Timing Requirements ....................... 201 Timing Requirements ............................................... 195 B Block Diagrams ADC Module.............................................................. 153 Comparator I/O Operating Modes............................. 159 Comparator Voltage Reference ................................ 161 Connections for On-Chip Voltage Regulator............. 174 Core and Peripheral Modules ..................................... 31 DMA .......................................................................... 129 Ethernet Controller.................................................... 157 I2C Circuit ................................................................. 146 Input Capture ............................................................ 139 Interrupt Controller .................................................... 121 JTAG Programming, Debugging and Trace Ports .... 175 MCU............................................................................ 49 Output Compare Module........................................... 141 PIC32 CAN Module................................................... 155 PMP Pinout and Connections to External Devices ... 149 Prefetch Module........................................................ 127 Reset System............................................................ 119 RTCC ........................................................................ 151 SPI Module ............................................................... 143 Timer1....................................................................... 135 Timer2/3/4/5 (16-Bit) ................................................. 137 Typical Multiplexed Port Structure ............................ 133 UART ........................................................................ 147 WDT and Power-up Timer ........................................ 173 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 174 F Flash Program Memory .................................................... 117 RTSP Operation ....................................................... 117 I I/O Ports ........................................................................... 133 Parallel I/O (PIO) ...................................................... 134 Instruction Set................................................................... 177 Inter-Integrated Circuit (I2C) ............................................. 145 Internal Voltage Reference Specifications........................ 193 Internet Address ............................................................... 253 Interrupt Controller............................................................ 121 IRG, Vector and Bit Location .................................... 122 M MCU Architecture Overview ................................................ 50 Coprocessor 0 Registers ............................................ 52 Core Exception Types ................................................ 53 EJTAG Debug Support............................................... 54 Power Management ................................................... 54 MCU Module....................................................................... 49 Memory Map....................................................................... 60 Memory Maps ............................................. 56, 57, 58, 59, 61 Memory Organization ......................................................... 55 Layout......................................................................... 55 Microchip Internet Web Site.............................................. 253 Migration PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 239 MPLAB ASM30 Assembler, Linker, Librarian ................... 180 MPLAB Integrated Development Environment Software.. 179 MPLAB PM3 Device Programmer .................................... 182 MPLAB REAL ICE In-Circuit Emulator System ................ 181 MPLINK Object Linker/MPLIB Object Librarian ................ 180 C C Compilers MPLAB C18 .............................................................. 180 Clock Diagram .................................................................. 125 Comparator Specifications............................................................ 192 Comparator Module .......................................................... 159 Comparator Voltage Reference (CVref ............................. 161 Configuration Bit ............................................................... 165 Controller Area Network (CAN)......................................... 155 CPU Module........................................................................ 43 Customer Change Notification Service ............................. 253 Customer Notification Service........................................... 253 Customer Support ............................................................. 253 O Open-Drain Configuration................................................. 134 Oscillator Configuration .................................................... 125 Output Compare ............................................................... 141 P Packaging ......................................................................... 225 © 2009-2011 Microchip Technology Inc. DS61156G-page 251 PIC32MX5XX/6XX/7XX Details ....................................................................... 227 Marking ..................................................................... 225 Parallel Master Port (PMP) ............................................... 149 PIC32 Family USB Interface Diagram............................... 132 Pinout I/O Descriptions (table) ............................................ 32 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 174 Power-Saving Features..................................................... 163 CPU Halted Methods ................................................ 163 Operation .................................................................. 163 with CPU Running..................................................... 163 Prefetch Cache ................................................................. 127 Program Flash Memory Wait State Characteristics......................................... 192 I/O Characteristics .................................................... 197 I2Cx Bus Data (Master Mode) .................................. 208 I2Cx Bus Data (Slave Mode) .................................... 210 I2Cx Bus Start/Stop Bits (Master Mode)................... 208 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 210 Input Capture (CAPx) ............................................... 201 OCx/PWM................................................................. 202 Output Compare (OCx)............................................. 202 Parallel Master Port Read......................................... 221 Parallel Master Port Write......................................... 222 Parallel Slave Port .................................................... 220 SPIx Master Mode (CKE = 0) ................................... 203 SPIx Master Mode (CKE = 1) ................................... 204 SPIx Slave Mode (CKE = 0) ..................................... 205 SPIx Slave Mode (CKE = 1) ..................................... 206 Timer1, 2, 3, 4, 5 External Clock .............................. 200 UART Reception....................................................... 148 UART Transmission (8-bit or 9-bit Data) .................. 148 Timing Requirements CLKO and I/O ........................................................... 197 Timing Specifications CAN I/O Requirements ............................................. 212 I2Cx Bus Data Requirements (Master Mode)........... 209 I2Cx Bus Data Requirements (Slave Mode)............. 211 Input Capture Requirements..................................... 201 Output Compare Requirements................................ 202 Simple OCx/PWM Mode Requirements ................... 202 SPIx Master Mode (CKE = 0) Requirements............ 203 SPIx Master Mode (CKE = 1) Requirements............ 204 SPIx Slave Mode (CKE = 1) Requirements.............. 206 SPIx Slave Mode Requirements (CKE = 0).............. 205 R Reader Response ............................................................. 254 Real-Time Clock and Calendar (RTCC)............................ 151 Register Maps ............................................................. 62–116 Registers DDPCON (Debug Data Port Control)........................ 176 DEVCFG0 (Device Configuration Word 0 ................. 166 DEVCFG1 (Device Configuration Word 1 ................. 168 DEVCFG2 (Device Configuration Word 2 ................. 170 DEVCFG3 (Device Configuration Word 3 ................. 171 DEVID (Device and Revision ID) .............................. 172 Resets ............................................................................... 119 Revision History ................................................................ 240 S Serial Peripheral Interface (SPI) ....................................... 143 Software Simulator (MPLAB SIM)..................................... 181 Special Features ............................................................... 165 U UART ................................................................................ 147 USB On-The-Go (OTG) .................................................... 131 T Timer1 Module .................................................................. 135 Timer2/3, Timer4/5 Modules ............................................. 137 Timing Diagrams 10-bit Analog-to-Digital Conversion (ASAM = 0, SSRC = 000) ................................................ 218 10-bit Analog-to-Digital Conversion (CHPS = 01, ASAM = 1, SSRC = 111, SAMC = 00001)............................................................... 219 CAN I/O..................................................................... 212 EJTAG ...................................................................... 224 External Clock ........................................................... 194 V VCAP/VCORE pin ................................................................ 174 Voltage Reference Specifications..................................... 193 Voltage Regulator (On-Chip) ............................................ 174 W Watchdog Timer (WDT).................................................... 173 WWW Address ................................................................. 253 WWW, On-Line Support ..................................................... 29 DS61156G-page 252 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX THE MICROCHIP WEB SITE Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions. © 2009-2011 Microchip Technology Inc. DS61156G-page 253 PIC32MX5XX/6XX/7XX READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. TO: RE: Technical Publications Manager Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ Application (optional): Would you like a reply? Y N Literature Number: DS61156G FAX: (______) _________ - _________ Device: PIC32MX5XX/6XX/7XX Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS61156G-page 254 © 2009-2011 Microchip Technology Inc. PIC32MX5XX/6XX/7XX PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Example: PIC32MX575F256H-80I/PT: General purpose PIC32, 32-bit RISC MCU, 256 KB program memory, 64-pin, Industrial temperature, TQFP package. Flash Memory Family Architecture Product Groups MX = 32-bit RISC MCU core 5XX = General purpose microcontroller family 6XX = General purpose microcontroller family 7XX = General purpose microcontroller family F = Flash program memory Flash Memory Family Program Memory Size 256 = 256K 512 = 512K Pin Count H L 80 I V PT PT PF MR BG = 64-pin = 100-pin = 80 MHz = -40°C to +85°C (Industrial) = -40°C to +105°C (V-Temp) = = = = = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array) Speed Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample © 2009-2011 Microchip Technology Inc. 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