PIC32MX7XX

PIC32MX5XX/6XX/7XX Family Data Sheet High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers  2010 Microchip Technology Inc. Preliminary DS61156C Note the following details of the code protection feature on Microchip devices: • • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PIC32 logo, rfPIC and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, HI-TIDE, In-Circuit Serial Programming, ICSP, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit, PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2010, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. ISBN: 978-1-60932-037-9 Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS61156C-page 2 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers High-Performance 32-Bit RISC CPU: • MIPS32® M4K™ 32-bit core with 5-stage pipeline • 80 MHz maximum frequency • 1.56 DMIPS/MHz (Dhrystone 2.1) performance at zero Wait state Flash access • Single-cycle multiply and high-performance divide unit • MIPS16e™ mode for up to 40% smaller code size • Two sets of 32 core register files (32-bit) to reduce interrupt latency • Prefetch Cache module to speed execution from Flash Peripheral Features (Continued): • Internal 8 MHz and 32 kHz oscillators • Six UART modules with: - RS-232, RS-485 and LIN 1.2 support - IrDA® with on-chip hardware encoder and decoder • Up to four SPI modules • Up to five I2C™ modules • Separate PLLs for CPU and USB clocks • Parallel Master and Slave Port (PMP/PSP) with 8-bit and 16-bit data, and up to 16 address lines • Hardware Real-Time Clock/Calendar (RTCC) • Five 16-bit Timers/Counters (two 16-bit pairs combine to create two 32-bit timers) • Five Capture inputs • Five Compare/PWM outputs • Five external interrupt pins • High-speed I/O pins capable of toggling at up to 80 MHz • High-current sink/source (18 mA/18 mA) on all I/O pins • Configurable open-drain output on digital I/O pins Microcontroller Features: • Operating voltage range of 2.3V to 3.6V • 256K to 512K Flash memory (plus an additional 12 KB of Boot Flash) • 64K to 128K SRAM memory • Pin-compatible with most PIC24/dsPIC® devices • Multiple power management modes • Multiple interrupt vectors with individually programmable priority • Fail-Safe Clock Monitor mode • Configurable Watchdog Timer with on-chip Low-Power RC oscillator for reliable operation Debug Features: • Two programming and debugging Interfaces: - 2-wire interface with unintrusive access and real-time data exchange with application - 4-wire MIPS® standard enhanced JTAG interface • Unintrusive hardware-based instruction trace • IEEE Standard 1149.2 compatible (JTAG) boundary scan Peripheral Features: • Atomic Set, Clear and Invert operation on select peripheral registers • 8-channel hardware DMA with automatic data size detection • USB 2.0-compliant full-speed device and On-The-Go (OTG) controller: - Dedicated DMA channels • 10/100 Mbps Ethernet MAC with MII and RMII interface: - Dedicated DMA channels • CAN module: - 2.0B Active with DeviceNet™ addressing support - Dedicated DMA channels • 3 MHz to 25 MHz crystal oscillator Analog Features: • Up to 16-channel, 10-bit Analog-to-Digital Converter: - 1 Msps conversion rate - Conversion available during Sleep and Idle • Two Analog Comparators • 5V tolerant input pins (digital pins only)  2010 Microchip Technology Inc. Preliminary DS61156C-page 3 PIC32MX5XX/6XX/7XX TABLE 1: PIC32MX FEATURES Timers/Capture/Compare Program Memory (KB) 10-Bit 1 Msps ADC (Channels) Data Memory (KB) DMA Channels (Programmable/ Dedicated) Comparators PIC32MX575F256H PIC32MX675F256H PIC32MX775F256H PIC32MX575F512H PIC32MX675F512H PIC32MX695F512H PIC32MX775F512H PIC32MX795F512H PIC32MX575F256L 64 64 64 64 64 64 64 64 256 + 12(1) 256 + 12(1) 256 + 12(1) 512 + 12(1) 512 + 12(1) 64 64 64 64 64 1 1 1 1 1 1 1 1 1 0 1 1 0 1 1 1 1 0 1 0 2 1 0 0 2 2 1 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 5/5/5 8/4 8/4 8/8 8/4 8/4 8/4 8/8 8/8 8/4 6 6 6 6 6 6 6 6 6 3 3 3 3 3 3 3 3 4 4 4 4 4 4 4 4 4 5 16 16 16 16 16 16 16 16 16 2 2 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes No No No No No No No No PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, MR PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG PT, PF, BG 512 + 12(1) 128 512 + 12(1) 64 512 + 12(1) 128 64 100 256 + 12(1) Yes Yes Yes PIC32MX675F256L 100 256 + 12(1) 64 1 1 0 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX775F256L 100 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PIC32MX575F512L 100 512 + 12(1) 64 1 0 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX675F512L 100 512 + 12(1) 512 + 12(1) 64 1 1 0 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX695F512L 100 128 1 1 0 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PIC32MX775F512L 100 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PIC32MX795F512L Legend: Note 1: 2: 3: 4: 100 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes PF, PT = TQFP MR = QFN BG = XBGA This device features 12 KB boot Flash memory. CTS and RTS pins may not be available for all UART modules. Refer to the “Pin Diagrams” section for more information. Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Pin Diagrams” section for more information. Refer to Section 32.0 “Packaging Information” for detailed information. DS61156C-page 4 Preliminary  2010 Microchip Technology Inc. Packages(4) PMP/PSP UART(2,3) Ethernet I2C™(3) Device Trace SPI(3) JTAG CAN Pins USB PIC32MX5XX/6XX/7XX Pin Diagrams 64-Pin QFN = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 PIC32MX575F256H PIC32MX575F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2010 Microchip Technology Inc. Preliminary DS61156C-page 5 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 = Pins are up to 5V tolerant SCL1A/SDO1A/U1ATX/OC4/RD3 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 ERXERR/PMD4/RE4 ERXD0/PMD1/RE1 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 VCAP/VDDCORE SDA1A/SDI1A/U1ARX/OC3/RD2 ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 OC5/IC5/PMWR/CN13/RD4 ERXD1/PMD0/RE0 PMRD/CN14/RD5 VDD SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AVSS PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VDD VSS TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TCK/AN12/PMA11/RB12 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally. DS61156C-page 6 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin QFN = Pins are up to 5V tolerant ERXCLK/EREFCLKPMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXERR/PMD4/RE4 ERXD0/PMD1/RE1 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 OC5/IC5/PMWR/CN13/RD4 ERXD1/PMD0/RE0 PMRD/CN14/RD5 VCAP/VDDCORE VDD SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H 42 41 40 39 38 37 36 35 10 11 12 13 14 34 15 33 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 TMS/AN10/CVREFOUT/PMA13/RB10 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 TCK/AN12/PMA11/RB12 PGED2/AN7/RB7 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AVSS AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8 PGEC2/AN6/OCFA/RB6 VDD VSS TDI/AN13/PMA10/RB13 Note: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.  2010 Microchip Technology Inc. Preliminary AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 TDO/AN11/PMA12/RB11 AN9/C2OUT/PMA7/RB9 AVDD DS61156C-page 7 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD5/RE5 PMD6/RE6 PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 C1TX/RF1 C1RX/RF0 VDD VCAP/VDDCORE CN16/RD7 CN15/RD6 PMRD/CN14/RD5 OC5/IC5/PMWR/CN13/RD4 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 SCK1A/U1BTX/U1ARTS/OC2/RD1 PMD4/RE4 PMD3/RE3 PMD2/RE2 PMD1/RE1 PMD0/RE0 PIC32MX575F256H PIC32MX575F512H 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 IC4/PMCS1/PMA14/INT4/RD11 SCL1/IC3/PMCS2/PMA15/INT3/RD10 SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 AVDD AVSS AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN9/C2OUT/PMA7/RB9 TMS/AN10/CVREFOUT/PMA13/RB10 TDO/AN11/PMA12/RB11 VSS VDD TCK/AN12/PMA11/RB12 TDI/AN13/PMA10/RB13 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 DS61156C-page 8 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP = Pins are up to 5V tolerant ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 ERXERR/PMD4/RE4 ERXD0/PMD1/RE1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 TCK/AN12/PMA11/RB12 PGED2/AN7/RB7 AN14/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 AN8/SS3A/U3BRX/U3ACTS/C1OUT/RB8 EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 SCL1A/SDO1A/U1ATX/OC4/RD3 SDA1A/SDI1A/U1ARX/OC3/RD2 ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 OC5/IC5/PMWR/CN13/RD4 AETXD0/ERXD2/RF1 AETXD1/ERXD3/RF0 ERXD1/PMD0/RE0 PMRD/CN14/RD5 VCAP/VDDCORE VDD 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 PIC32MX675F256H PIC32MX675F512H PIC32MX695F512H SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 TMS/AN10/CVREFOUT/PMA13/RB10 AVSS TDO/AN11/PMA12/RB11 PGEC2/AN6/OCFA/RB6 VDD  2010 Microchip Technology Inc. Preliminary SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 AN9/C2OUT/PMA7/RB9 TDI/AN13/PMA10/RB13 AVDD VSS DS61156C-page 9 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 64-Pin TQFP EMDIO/AEMDIO/SCK1A/U1BTX/U1ARTS/OC2/RD1 = Pins are up to 5V tolerant SCL1A/SDO1A/U1ATX/OC4/RD3 ERXCLK/EREFCLK/PMD3/RE3 ERXDV/ECRSDV/PMD2/RE2 C1TX/AETXD0/ERXD2/RF1 C1RX/AETXD1/ERXD3/RF0 ERXERR/PMD4/RE4 ERXD0/PMD1/RE1 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 ETXEN/PMD5/RE5 ETXD0/PMD6/RE6 ETXD1/PMD7/RE7 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 AVDD AVSS TMS/AN10/CVREFOUT/PMA13/RB10 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VDD VSS AN9/C2OUT/PMA7/RB9 TDO/AN11/PMA12/RB11 TDI/AN13/PMA10/RB13 AN14/C2RX/SCK3A/U3BTX/U3ARTS/PMALH/PMA1/RB14 TCK/AN12/PMA11/RB12 AC1TX/SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 AN8/C2TX/SS3A/U3BRX/U3ACTS/C1OUT/RB8 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 AC1RX/SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 48 47 46 45 44 43 SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 OC1/INT0/RD0 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10 AERXD0/ETXD2/SS1A/U1BRX/U1ACTS/SDA1/IC2/INT2/RD9 RTCC/AERXD1/ETXD3/IC1/INT1/RD8 Vss OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD D+/RG2 D-/RG3 VUSB VBUS USBID/RF3 VCAP/VDDCORE SDA1A/SDI1A/U1ARX/OC3/RD2 ETXCLK/AERXERR/CN16/RD7 AETXEN/ETXERR/CN15/RD6 OC5/IC5/PMWR/CN13/RD4 ERXD1/PMD0/RE0 PMRD/CN14/RD5 VDD PIC32MX775F256H PIC32MX775F512H PIC32MX795F512H 42 41 40 39 38 37 36 35 34 33 DS61156C-page 10 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 100-Pin TQFP = Pins are up to 5V tolerant 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 PMD9/RG1 C1TX/PMD10/RF1 C1RX/PMD11/RF0 VDD VCAP/VDDCORE PMD15/CN16/RD7 PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 PMD13/CN19/RD13 IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 INT1/RE8 INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/IC1/RD8 SDA1/INT4/RA15 SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3 PIC32MX575F512L PIC32MX575F256L 63 62 61 60 59 58 57 56 55 54 53 52 51 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/PMA7/RA9 VREF+/CVREF+/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/PMA11/RB12 AN13/PMA10/RB13 AN14/PMALH/PMA1/RB14 AN15/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD SS1A/U1BRX/U1ACTS/CN20/RD14 SCK1A/U1BTX/U1ARTS/CN21/RD15  2010 Microchip Technology Inc. Preliminary SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS61156C-page 11 Pin Diagrams (Continued) 100-Pin TQFP PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 PMD8/RG0 ETXERR/PMD9/RG1 ETXD0/PMD10/RF1 ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 SCK3A/U3BTX/U3ARTS/RF13 SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DS61156C-page 12 PIC32MX5XX/6XX/7XX = Pins are up to 5V tolerant AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/RC2 T4CK/RC3 T5CK/SDI1/RC4 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 PIC32MX675F256L PIC32MX675F512L PIC32MX695F512L 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3 Preliminary  2010 Microchip Technology Inc. Pin Diagrams (Continued) PMD4/RE4 PMD3/RE3 PMD2/RE2 TRD0/RG13 TRD1/RG12 TRD2/RG14 PMD1/RE1 PMD0/RE0 TRD3/RA7 TRCLK/RA6 C2RX/PMD8/RG0 C2TX/ETXERR/PMD9/RG1 C1TX/ETXD0/PMD10/RF1 C1RX/ETXD1/PMD11/RF0 VDD VCAP/VDDCORE ETXCLK/PMD15/CN16/RD7 ETXEN/PMD14/CN15/RD6 PMRD/CN14/RD5 OC5/PMWR/CN13/RD4 ETXD3/PMD13/CN19/RD13 ETXD2/IC5/PMD12/RD12 OC4/RD3 OC3/RD2 OC2/RD1 PGEC2/AN6/OCFA/RB6 PGED2/AN7/RB7 VREF-/CVREF-/AERXD2/PMA7/RA9 VREF+/CVREF+/AERXD3/PMA6/RA10 AVDD AVSS AN8/C1OUT/RB8 AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AN11/ERXERR/AETXERR/PMA12/RB11 VSS VDD TCK/RA1 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN12/ERXD0/AECRS/PMA11/RB12 AN13/ERXD1/AECOL/PMA10/RB13 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 VSS VDD AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 PGED1/AN0/CN2/RB0 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50  2010 Microchip Technology Inc. 100-Pin TQFP = Pins are up to 5V tolerant 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VSS SOSCO/T1CK/CN0/RC14 SOSCI/CN1/RC13 SDO1/OC1/INT0/RD0 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 SCK1/IC3/PMCS2/PMA15/RD10 SS1/IC2/RD9 RTCC/EMDIO/AEMDIO/IC1/RD8 AERXERR/RG15 VDD PMD5/RE5 PMD6/RE6 PMD7/RE7 T2CK/RC1 T3CK/AC2TX/RC2 T4CK/AC2RX/RC3 T5CK/SDI1/RC4 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 MCLR ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 VSS VDD TMS/RA0 AERXD0/INT1/RE8 AERXD1/INT2/RE9 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGEC1/AN1/CN3/RB1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PIC32MX775F256L PIC32MX775F512L PIC32MX795F512L AETXEN/SDA1/INT4/RA15 AETXCLK/SCL1/INT3/RA14 VSS OSC2/CLKO/RC15 OSC1/CLKI/RC12 VDD TDO/RA5 TDI/RA4 SDA2/RA3 SCL2/RA2 Preliminary DS61156C-page 13 PIC32MX5XX/6XX/7XX D+/RG2 D-/RG3 VUSB VBUS SCL1A/SDO1A/U1ATX/RF8 SDA1A/SDI1A/U1ARX/RF2 USBID/RF3 PIC32MX5XX/6XX/7XX Pin Diagrams (Continued) 121-Pin XBGA(1) PIC32MX575F256L PIC32MX675F256L PIC32MX775F256L PIC32MX575F512L PIC32MX675F512L PIC32MX695F512L PIC32MX775F512L PIC32MX795F512L 1 2 3 4 5 6 7 8 9 10 11 = Pins are up to 5V tolerant A RE4 RE3 RG13 RE0 RG0 RF1 VDD VSS RD12 RD2 RD1 B NC RG15 RE2 RE1 RA7 RF0 VCAP/ VDDCORE RD5 RD3 VSS RC14 C RE6 VDD RG12 RG14 RA6 NC RD7 RD4 VDD RC13 RD11 D RC1 RE7 RE5 VSS VSS NC RD6 RD13 RD0 NC RD10 E RC4 RC3 RG6 RC2 VDD RG1 VSS RA15 RD8 RD9 RA14 F MCLR RG8 RG9 RG7 VSS NC NC VDD RC12 VSS RC15 G RE8 RE9 RA0 NC VDD VSS VSS NC RA5 RA3 RA4 H RB5 RB4 VSS VDD NC VDD NC VBUS VUSB RG2 RA2 J RB3 RB2 RB7 AVDD RB11 RA1 RB12 NC NC RF8 RG3 K RB1 RB0 RA10 RB8 NC RF12 RB14 VDD RD15 RF3 RF2 L RB6 RA9 AVSS RB9 RB10 RF13 RB13 RB15 RD14 RF4 RF5 Note 1: Refer to Table 2, Table 3 and Table 4 for full pin names. DS61156C-page 14 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 2: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 C1TX/PMD10/RF1 VDD VSS IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) PMD14/CN15/RD6 PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/RC2 VDD PMD9/RG1 VSS PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 SDA1/INT4/RA15 RTCC/IC1/RD8 SS1/IC2/RD9 SCL1/INT3/RA14 MCLR SCL2A/SDO2A/U2ATX/PMA3/CN10/RG8 SS2A/U2BRX/U2ACTS/PMA2/CN11/RG9 SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 INT1/RE8 INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/PMA12/RB11 TCK/RA1 AN12/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/PMA6/RA10 Full Pin Name  2010 Microchip Technology Inc. Preliminary DS61156C-page 15 PIC32MX5XX/6XX/7XX TABLE 2: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN14/PMALH/PMA1/RB14 VDD SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/PMA7/RA9 PIN NAMES: PIC32MX575F256L AND PIC32MX575F512L DEVICES (CONTINUED) Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/PMA10/RB13 AN15/OCFB/PMALL/PMA0/CN12/RB15 SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name DS61156C-page 16 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 3: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 PMD8/RG0 ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/RC3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/RC2 VDD EXTERR/PMD9/RG1 VSS PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV//SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK//SS2A/U2BRX/ U2ACTS/PMA2/CN11/RG9 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10  2010 Microchip Technology Inc. Preliminary DS61156C-page 17 PIC32MX5XX/6XX/7XX TABLE 3: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) SS3A/U3BRX/U3ACTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9 PIN NAMES: PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name DS61156C-page 18 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 4: Pin Number A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 E1 E2 E3 E4 E5 E6 E7 PMD4/RE4 PMD3/RE3 TRD0/RG13 PMD0/RE0 C2RX/PMD8/RG0 C1TX/ETXD0/PMD10/RF1 VDD VSS ETXD2/IC5/PMD12/RD12 OC3/RD2 OC2/RD1 No Connect (NC) AERXERR/RG15 PMD2/RE2 PMD1/RE1 TRD3/RA7 C1RX/ETXD1/PMD11/RF0 VCAP/VDDCORE PMRD/CN14/RD5 OC4/RD3 VSS SOSCO/T1CK/CN0/RC14 PMD6/RE6 VDD TRD1/RG12 TRD2/RG14 TRCLK/RA6 No Connect (NC) ETXCLK/PMD15/CN16/RD7 OC5/PMWR/CN13/RD4 VDD SOSCI/CN1/RC13 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 T2CK/RC1 PMD7/RE7 PMD5/RE5 VSS VSS No Connect (NC) ETXEN/PMD14/CN15/RD6 ETXD3/PMD13/CN19/RD13 SDO1/OC1/INT0/RD0 No Connect (NC) SCK1/IC3/PMCS2/PMA15/RD10 T5CK/SDI1/RC4 T4CK/AC2RX/RC3 ECOL/SCK2A/U2BTX/U2ARTS/PMA5/CN8/RG6 T3CK/AC2TX/RC2 VDD C2TX/EXTERR/PMD9/RG1 VSS PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES Full Pin Name Pin Number E8 E9 E10 E11 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 J11 K1 K2 K3 Full Pin Name AETXEN/SDA1/INT4/RA15 RTCC/EMDIO/AEMDIO/IC1/RD8 SS1/IC2/RD9 AETXCLK/SCL1/INT3/RA14 MCLR ERXDV/AERXDV/ECRSDV/AECRSDV/SCL2A/SDO2A/ U2ATX/PMA3/CN10/RG8 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2A/U2BRX/ U2ACTS/PMA2/CN11/RG9 ECRS/SDA2A/SDI2A/U2ARX/PMA4/CN9/RG7 VSS No Connect (NC) No Connect (NC) VDD OSC1/CLKI/RC12 VSS OSC2/CLKO/RC15 AERXD0/INT1/RE8 AERXD1/INT2/RE9 TMS/RA0 No Connect (NC) VDD VSS VSS No Connect (NC) TDO/RA5 SDA2/RA3 TDI/RA4 AN5/C1IN+/VBUSON/CN7/RB5 AN4/C1IN-/CN6/RB4 VSS VDD No Connect (NC) VDD No Connect (NC) VBUS VUSB D+/RG2 SCL2/RA2 AN3/C2IN+/CN5/RB3 AN2/C2IN-/CN4/RB2 PGED2/AN7/RB7 AVDD AN11/ERXERR/AETXERR/PMA12/RB11 TCK/RA1 AN12/ERXD0/AECRS/PMA11/RB12 No Connect (NC) No Connect (NC) SCL1A/SDO1A/U1ATX/RF8 D-/RG3 PGEC1/AN1/CN3/RB1 PGED1/AN0/CN2/RB0 VREF+/CVREF+/AERXD3/PMA6/RA10  2010 Microchip Technology Inc. Preliminary DS61156C-page 19 PIC32MX5XX/6XX/7XX TABLE 4: Pin Number K4 K5 K6 K7 K8 K9 K10 K11 L1 L2 AN8/C1OUT/RB8 No Connect (NC) AC1RX/SS3A/U3BRX/U3ACTS/RF12 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 VDD AETXD1/SCK1A/U1BTX/U1ARTS/CN21/RD15 USBID/RF3 SDA1A/SDI1A/U1ARX/RF2 PGEC2/AN6/OCFA/RB6 VREF-/CVREF-/AERXD2/PMA7/RA9 PIN NAMES: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L AND DEVICES Full Pin Name Pin Number L3 L4 L5 L6 L7 L8 L9 L10 L11 AVSS AN9/C2OUT/RB9 AN10/CVREFOUT/PMA13/RB10 AC1TX/SCK3A/U3BTX/U3ARTS/RF13 AN13/ERXD1/AECOL/PMA10/RB13 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 AETXD0/SS1A/U1BRX/U1ACTS/CN20/RD14 SDA3A/SDI3A/U3ARX/PMA9/CN17/RF4 SCL3A/SDO3A/U3ATX/PMA8/CN18/RF5 Full Pin Name DS61156C-page 20 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Table of Contents 1.0 2.0 3.0 4.0 5.0 6.0 7.0 8.0 9.0 10.0 11.0 12.0 13.0 14.0 15.0 16.0 17.0 18.0 19.0 20.0 21.0 22.0 23.0 24.0 25.0 26.0 27.0 28.0 29.0 30.0 31.0 32.0 Device Overview ........................................................................................................................................................................ 23 Guidelines for Getting Started with 32-Bit Microcontrollers........................................................................................................ 35 PIC32MX MCU........................................................................................................................................................................... 39 Memory Organization ................................................................................................................................................................. 45 Flash Program Memory............................................................................................................................................................ 105 Resets ...................................................................................................................................................................................... 107 Interrupt Controller ................................................................................................................................................................... 109 Oscillator Configuration ............................................................................................................................................................ 113 Prefetch Cache......................................................................................................................................................................... 115 Direct Memory Access (DMA) Controller ................................................................................................................................ 117 USB On-The-Go (OTG)............................................................................................................................................................ 119 I/O Ports ................................................................................................................................................................................... 121 Timer1 ...................................................................................................................................................................................... 123 Timer2/3, Timer4/5 ................................................................................................................................................................... 125 Input Capture............................................................................................................................................................................ 127 Output Compare....................................................................................................................................................................... 129 Serial Peripheral Interface (SPI)............................................................................................................................................... 131 Inter-Integrated Circuit (I2C™) ................................................................................................................................................. 133 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 135 Parallel Master Port (PMP) ...................................................................................................................................................... 137 Real-Time Clock and Calendar (RTCC)................................................................................................................................... 139 10-Bit Analog-to-Digital Converter (ADC)................................................................................................................................. 141 Controller Area Network (CAN) ................................................................................................................................................ 143 Ethernet Controller ................................................................................................................................................................... 145 Comparator .............................................................................................................................................................................. 147 Comparator Voltage Reference (CVref) ................................................................................................................................... 149 Power-Saving Features ........................................................................................................................................................... 151 Special Features ...................................................................................................................................................................... 153 Instruction Set .......................................................................................................................................................................... 165 Development Support............................................................................................................................................................... 167 Electrical Characteristics .......................................................................................................................................................... 171 Packaging Information.............................................................................................................................................................. 213 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: • Microchip’s Worldwide Web site; http://www.microchip.com • Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products.  2010 Microchip Technology Inc. Preliminary DS61156C-page 21 PIC32MX5XX/6XX/7XX NOTES: DS61156C-page 22 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 1.0 DEVICE OVERVIEW This document contains device-specific information for PIC32MX5XX/6XX/7XX devices. Figure 1-1 shows a general block diagram of the core and peripheral modules in the PIC32MX5XX/6XX/7XX family of devices. Table 1-1 lists the functions of the various pins shown in the pinout diagrams. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. FIGURE 1-1: BLOCK DIAGRAM(1,2) OSC2/CLKO OSC1/CLKI OSC/SOSC Oscillators FRC/LPRC Oscillators PLL Dividers PLL-USB Timing Generation VCAP/VDDCORE Power-up Timer Voltage Regulator Precision Band Gap Reference USBCLK SYSCLK PBCLK Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset CN1-22 Timer1-5 CAN1, CAN2 PWM OC1-5 VDD, VSS MCLR Peripheral Bus Clocked by SYSCLK PORTA JTAG BSCAN PORTB USB EJTAG PORTC 32 PORTD INT Priority Interrupt Controller 32 Peripheral Bus Clocked by PBCLK ETHERNET DMAC ICD MIPS32® M4K™ CPU Core IS 32 DS 32 32 IC1-5 32 32 32 32 SPI1,1A,2A,3A Bus Matrix 32 32 32 I2C1,2,1A, 2A,3A 32 PORTE Prefetch Module PORTF 128 128-Bit Wide Program Flash Memory Flash Controller Data RAM Peripheral Bridge PMP 10-Bit ADC UART1A,1B,2A, 2B,3A,3B RTCC Comparators PORTG Note 1: 2: Some features are not available on all device variants. BOR functionality is provided when the on-board voltage regulator is enabled.  2010 Microchip Technology Inc. Preliminary DS61156C-page 23 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 CLKI CLKO PINOUT I/O DESCRIPTIONS Pin Number(1) 64-Pin QFN/TQFP 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 39 40 100-Pin TQFP 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 63 64 121-Pin XBGA K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 F9 F11 Pin Type I I I I I I I I I I I I I I I I I O Buffer Type Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog ST/CMOS External clock source input. Always associated with OSC1 pin function. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. Always associated with OSC2 pin function. Description Analog input channels. OSC1 OSC2 39 40 63 64 F9 F11 I I/O ST/CMOS Oscillator crystal input. ST buffer when configured in RC mode; CMOS otherwise. — Oscillator crystal output. Connects to crystal or resonator in Crystal Oscillator mode. Optionally functions as CLKO in RC and EC modes. SOSCI SOSCO 47 48 73 74 C10 B11 I O ST/CMOS 32.768 kHz low-power oscillator crystal input; CMOS otherwise. — 32.768 kHz low-power oscillator crystal output. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156C-page 24 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name CN0 CN1 CN2 CN3 CN4 CN5 CN6 CN7 CN8 CN9 CN10 CN11 CN12 CN13 CN14 CN15 CN16 CN17 CN18 CN19 CN20 CN21 IC1 IC2 IC3 IC4 IC5 OCFA OC1 OC2 OC3 OC4 OC5 OCFB INT0 INT1 INT2 INT3 INT4 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 48 47 16 15 14 13 12 11 4 5 6 8 30 52 53 54 55 31 32 — — — 42 43 44 45 52 17 46 49 50 51 52 30 46 42 43 44 45 100-Pin TQFP 74 73 25 24 23 22 21 20 10 11 12 14 44 81 82 83 84 49 50 80 47 48 68 69 70 71 79 26 72 76 77 78 81 44 72 18 19 66 67 121-Pin XBGA B11 C10 K2 K1 J2 J1 H2 H1 E3 F4 F2 F3 L8 C8 B8 D7 C7 L10 L11 D8 L9 K9 E9 E10 D11 C11 A9 L1 D9 A11 A10 B9 C8 L8 D9 G1 G2 E11 E8 Pin Type I I I I I I I I I I I I I I I I I I I I I I I I I I I I O O O O O I I I I I I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — — — — ST ST ST ST ST ST Output Compare Fault A input. Output Compare Output 1. Output Compare Output 2 Output Compare Output 3. Output Compare Output 4. Output Compare Output 5. Output Compare Fault B input. External Interrupt 0. External Interrupt 1. External Interrupt 2. External Interrupt 3. External Interrupt 4. Capture Inputs 1-5. Description Change notification inputs. Can be software programmed for internal weak pull-ups on all inputs. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information.  2010 Microchip Technology Inc. Preliminary DS61156C-page 25 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 RA9 RA10 RA14 RA15 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RB8 RB9 RB10 RB11 RB12 RB13 RB14 RB15 RC1 RC2 RC3 RC4 RC12 RC13 RC14 RC15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — — — — — — — — — — — — 16 15 14 13 12 11 17 18 21 22 23 24 27 28 29 30 — — — — 39 47 48 40 100-Pin TQFP 17 38 58 59 60 61 91 92 28 29 66 67 25 24 23 22 21 20 26 27 32 33 34 35 41 42 43 44 6 7 8 9 63 73 74 64 121-Pin XBGA G3 J6 H11 G10 G11 G9 C5 B5 L2 K3 E11 E8 K2 K1 J2 J1 H2 H1 L1 J3 K4 L4 L5 J5 J7 L7 K7 L8 D1 E4 E2 E1 F9 C10 B11 F11 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTC is a bidirectional I/O port. PORTB is a bidirectional I/O port. Description PORTA is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156C-page 26 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RD8 RD9 RD10 RD11 RD12 RD13 RD14 RD15 RE0 RE1 RE2 RE3 RE4 RE5 RE6 RE7 RE8 RE9 RF0 RF1 RF2 RF3 RF4 RF5 RF8 RF12 RF13 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 46 49 50 51 52 53 54 55 42 43 44 45 — — — — 60 61 62 63 64 1 2 3 — — 58 59 — 33 31 32 — — — 100-Pin TQFP 72 76 77 78 81 82 83 84 68 69 70 71 79 80 47 48 93 94 98 99 100 3 4 5 18 19 87 88 52 51 49 50 53 40 39 121-Pin XBGA D9 A11 A10 B9 C8 B8 D7 C7 E9 E10 D11 C11 A9 D8 L9 K9 A4 B4 B3 A2 A1 D3 C1 D2 G1 G2 B6 A6 K11 K10 L10 L11 J10 K6 L6 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST PORTF is a bidirectional I/O port. PORTE is a bidirectional I/O port. Description PORTD is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information.  2010 Microchip Technology Inc. Preliminary DS61156C-page 27 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name RG0 RG1 RG6 RG7 RG8 RG9 RG12 RG13 RG14 RG15 RG2 RG3 T1CK T2CK T3CK T4CK T5CK U1ACTS U1ARTS U1ARX U1ATX U2ACTS U2ARTS U2ARX U2ATX U3ACTS U3ARTS U3ARX U3ATX U1BRX U1BTX U2BRX U2BTX U3BRX U3BTX SCK1 SDI1 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — — 4 5 6 8 — — — — 37 36 48 — — — — 43 49 50 51 8 4 5 6 21 29 31 32 43 49 8 4 21 29 — — 100-Pin TQFP 90 89 10 11 12 14 96 97 95 1 57 56 74 6 7 8 9 47 48 52 53 14 10 11 12 40 39 49 50 47 48 14 10 40 39 70 9 121-Pin XBGA A5 E6 E3 F4 F2 F3 C3 A3 C4 B2 H10 J11 B11 D1 E4 E2 E1 L9 K9 K11 J10 F3 E3 F4 F2 K6 L6 L10 L11 L9 K9 F3 E3 K6 L6 D11 E1 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I O I O I O I O I O I O I O I O I O I/O I Buffer Type ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST ST — ST — ST — ST — ST — ST — ST — ST — ST — ST ST Timer1 external clock input. Timer2 external clock input. Timer3 external clock input. Timer4 external clock input. Timer5 external clock input. UART1A clear to send. UART1A ready to send. UART1A receive. UART1A transmit. UART2A clear to send. UART2A ready to send. UART2A receive. UART2A transmit. UART3A clear to send. UART3A ready to send. UART3A receive. UART3A transmit. UART1B receive. UART1B transmit. UART2B receive. UART2B transmit. UART3B receive. UART3B transmit. Synchronous serial clock input/output for SPI1. SPI1 data in. PORTG input pins. Description PORTG is a bidirectional I/O port. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156C-page 28 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name SDO1 SS1 SCK1A SDI1A SDO1A SS1A SCK2A SDI2A SDO2A SS2A SCK3A SDI3A SDO3A SS3A SCL1 SDA1 SCL1A SDA1A SCL2 SDA2 SCL2A SDA2A SCL3A SDA3A TMS TCK TDI TDO RTCC PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — — 49 50 51 43 4 5 6 8 29 31 32 21 44 43 51 50 — — 6 5 32 31 23 27 28 24 42 100-Pin TQFP 72 69 48 52 53 47 10 11 12 14 39 49 50 40 66 67 53 52 58 59 12 11 50 49 17 38 60 61 68 121-Pin XBGA D9 E10 K9 K11 J10 L9 E3 F4 F2 F3 L6 L10 L11 K6 E11 E8 J10 K11 H11 G10 F2 F4 L11 L10 G3 J6 G11 G9 E9 Pin Type O I/O I/O I O I/O I/O I O I/O I/O I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I O O Buffer Type — ST ST ST — ST ST ST — ST ST ST — ST ST ST ST ST ST ST ST ST ST ST ST ST ST — — SPI1 data out. SPI1 slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI1A. SPI1A data in. SPI1A data out. SPI1A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI2A. SPI2A data in. SPI2A data out. SPI2A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for SPI3A. SPI3A data in. SPI3A data out. SPI3A slave synchronization or frame pulse I/O. Synchronous serial clock input/output for I2C1. Synchronous serial data input/output for I2C1. Synchronous serial clock input/output for I2C1A. Synchronous serial data input/output for I2C1A. Synchronous serial clock input/output for I2C2. Synchronous serial data input/output for I2C2. Synchronous serial clock input/output for I2C2A. Synchronous serial data input/output for I2C2A. Synchronous serial clock input/output for I2C3A. Synchronous serial data input/output for I2C3A. JTAG Test mode select pin. JTAG test clock input pin. JTAG test data input pin. JTAG test data output pin. Real-Time Clock alarm output. Description Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information.  2010 Microchip Technology Inc. Preliminary DS61156C-page 29 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name CVREFCVREF+ CVREFOUT C1INC1IN+ C1OUT C2INC2IN+ C2OUT PMA0 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 15 16 23 12 11 21 14 13 22 — 100-Pin TQFP 28 29 34 21 20 32 23 22 33 44 121-Pin XBGA L2 K3 L5 H2 H1 K4 J2 J1 L4 L8 Pin Type I I O I I O I I O I/O Buffer Type Analog Analog Analog Analog Analog — Analog Analog — TTL/ST Description Comparator Voltage Reference (low). Comparator Voltage Reference (high). Comparator Voltage Reference output. Comparator 1 negative input. Comparator 1 positive input. Comparator 1 output. Comparator 2 negative input. Comparator 2 positive input. Comparator 2 output. Parallel Master Port Address Bit 0 input (Buffered Slave modes) and output (Master modes). Parallel Master Port Address Bit 1 input (Buffered Slave modes) and output (Master modes). Parallel Master Port address (Demultiplexed Master modes). PMA1 — 43 K7 I/O TTL/ST PMA2 PMA3 PMA4 PMA5 PMA6 PMA7 PMA8 PMA9 PMA10 PMA11 PMA12 PMA13 PMA14 PMA15 PMCS1 PMCS2 8 6 5 4 16 22 32 31 28 27 24 23 45 44 45 44 14 12 11 10 29 28 50 49 42 41 35 34 71 70 71 70 F3 F2 F4 E3 K3 L2 L11 L10 L7 J7 J5 L5 C11 D11 C11 D11 O O O O O O O O O O O O O O O O — — — — — — — — — — — — — — — — Parallel Master Port Chip Select 1 strobe. Parallel Master Port Chip Select 2 strobe. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156C-page 30 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name PMD0 PMD1 PMD2 PMD3 PMD4 PMD5 PMD6 PMD7 PMD8 PMD9 PMD10 PMD11 PMD12 PMD13 PMD14 PMD15 PMALL PMALH PMRD PMWR VBUS VUSB VBUSON D+ DUSBID C1RX C1TX AC1RX AC1TX C2RX C2TX AC2RX AC2TX ERXD0 ERXD1 ERXD2 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 60 61 62 63 64 1 2 3 — — — — — — — — 30 29 53 52 34 35 11 37 36 33 58 59 32 31 29 21 — — 61 60 59 100-Pin TQFP 93 94 98 99 100 3 4 5 90 89 88 87 79 80 83 84 44 43 82 81 54 55 20 57 56 51 87 88 40 39 90 89 8 7 41 42 43 121-Pin XBGA A4 B4 B3 A2 A1 D3 C1 D2 A5 E6 A6 B6 A9 D8 D7 C7 L8 K7 B8 C8 H8 H9 H1 H10 J11 K10 B6 A6 K6 L6 A5 E6 E2 E4 J7 L7 K7 Pin Type I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O O O O O I P O I/O I/O I I O I O I O 1 O I I I Buffer Type TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST TTL/ST — — — — Analog — — Analog Analog ST ST — ST — ST — ST — ST ST ST Parallel Master Port address latch enable low byte (Multiplexed Master modes). Parallel Master Port address latch enable high byte (Multiplexed Master modes). Parallel Master Port read strobe. Parallel Master Port write strobe. USB bus power monitor. USB internal transceiver supply. USB Host and OTG bus power control output. USB D+. USB D-. USB OTG ID detect. CAN1 bus receive pin. CAN1 bus transmit pin. Alternate CAN1 bus receive pin. Alternate CAN1 bus transmit pin. CAN2 bus receive pin. CAN2 bus transmit pin. Alternate CAN2 bus receive pin. Alternate CAN2 bus transmit pin. Ethernet Receive Data 0.(2) Ethernet Receive Data 1.(2) Ethernet Receive Data 2.(2) Description Parallel Master Port data (Demultiplexed Master mode) or address/data (Multiplexed Master modes). Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information.  2010 Microchip Technology Inc. Preliminary DS61156C-page 31 PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name ERXD3 ERXERR ERXDV ECRSDV ERXCLK EREFCLK ETXD0 ETXD1 ETXD2 ETXD3 ETXERR ETXEN ETXCLK ECOL ECRS EMDC EMDIO AERXD0 AERXD1 AERXD2 AERXD3 AERXERR AERXDV AECRSDV AERXCLK AEREFCLK AETXD0 AETXD1 AETXD2 AETXD3 AETXERR AETXEN AETXCLK AECOL AECRS TRCLK PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP 58 64 62 61 63 63 2 3 43 42 54 1 55 44 45 30 49 43 42 — — 55 44 44 45 45 59 58 — — — 54 — — — — 100-Pin TQFP 44 35 12 12 14 14 88 87 79 80 89 83 84 10 11 71 68 18 19 28 29 1 — — — — 47 48 44 43 35 67 66 42 41 91 121-Pin XBGA L8 J5 F2 F2 F3 F3 A6 B6 A9 D8 E6 D7 C7 E3 F4 C11 E9 G1 G2 L2 K3 B2 — — — — L9 K9 L8 K7 J5 E8 E11 L7 J7 C5 Pin Type I I I I I I O O O O O O I I I O I/O I I I I I I I I I O O O O O O I I I O Buffer Type ST ST ST ST ST ST — — — — — — ST ST ST — — ST ST ST ST ST ST ST ST ST — — — — — — ST ST ST — Description Ethernet Receive Data 3.(2) Ethernet receive error input.(2) Ethernet receive data valid.(2) Ethernet carrier sense data valid.(2) Ethernet receive clock.(2) Ethernet reference clock.(2) Ethernet Transmit Data 0.(2) Ethernet Transmit Data 1.(2) Ethernet Transmit Data 2.(2) Ethernet Transmit Data 3.(2) Ethernet transmit error.(2) Ethernet transmit enable.(2) Ethernet transmit clock.(2) Ethernet collision detect.(2) Ethernet carrier sense.(2) Ethernet management data clock.(2) Ethernet management data.(2) Alternate Ethernet Receive Data 0.(2) Alternate Ethernet Receive Data 1.(2) Alternate Ethernet Receive Data 2.(2) Alternate Ethernet Receive Data 3.(2) Alternate Ethernet receive error input.(2) Alternate Ethernet receive data valid.(2) Alternate Ethernet carrier sense data valid.(2) Alternate Ethernet receive clock.(2) Alternate Ethernet reference clock.(2) Alternate Ethernet Transmit Data 0.(2) Alternate Ethernet Transmit Data 1.(2) Alternate Ethernet Transmit Data 2.(2) Alternate Ethernet Transmit Data 3.(2) Alternate Ethernet transmit error.(2) Alternate Ethernet transmit enable.(2) Alternate Ethernet transmit clock.(2) Alternate Ethernet collision detect.(2) Alternate Ethernet carrier sense.(2) Trace clock. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information. DS61156C-page 32 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 1-1: Pin Name TRD0 TRD1 TRD2 TRD3 PGED1 PGEC1 PGED2 PGEC2 MCLR AVDD AVSS VDD PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number(1) 64-Pin QFN/TQFP — — — — 16 15 18 17 7 19 20 100-Pin TQFP 97 96 95 92 25 24 27 26 13 30 31 121-Pin XBGA A3 C3 C4 B5 K2 K1 J3 L1 F1 J4 L3 A7, C2, C9, E5, K8, F8, G5, H4, H6 B7 A8, B10, D4, D5, E7, F5, F10, G6, G7, H3 K3 L2 Pin Type O O O O I/O I I/O I I/P P P P Buffer Type — — — — ST ST ST ST ST P P — Data I/O pin for Programming/Debugging Communication Channel 1. Clock input pin for Programming/Debugging Communication Channel 1. Data I/O pin for Programming/Debugging Communication Channel 2. Clock input pin for Programming/Debugging Communication Channel 2. Master Clear (Reset) input. This pin is an active-low Reset to the device. Positive supply for analog modules. This pin must be connected at all times. Ground reference for analog modules. Positive supply for peripheral logic and I/O pins. Description Trace Data Bits 0-3. 10, 26, 38, 2, 16, 37, 57 46, 62, 86 VCAP/ VDDCORE VSS 56 9, 25, 41 85 15, 36, 45, 65, 75 P P — — CPU logic filter capacitor connection. Ground reference for logic and I/O pins. This pin must be connected at all times. VREF+ VREF- 16 15 29 28 I I Analog Analog Analog voltage reference (high) input. Analog voltage reference (low) input. Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power ST = Schmitt Trigger input with CMOS levels O = Output I = Input TTL = TTL input buffer Note 1: Pin numbers are provided for reference only. See the “Pin Diagrams” section for device pin availability. 2: See Section 24.0 “Ethernet Controller” for more information.  2010 Microchip Technology Inc. Preliminary DS61156C-page 33 PIC32MX5XX/6XX/7XX NOTES: DS61156C-page 34 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.0 GUIDELINES FOR GETTING STARTED WITH 32-BIT MICROCONTROLLERS 2.2 Decoupling Capacitors The use of decoupling capacitors on power supply pins, such as VDD, VSS, AVDD and AVSS is required. See Figure 2-1. Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A value of 0.1 µF (100 nF), 10-20V is recommended. The capacitor should be a low Equivalent Series Resistance (low-ESR) capacitor and have resonance frequency in the range of 20 MHz and higher. It is further recommended that ceramic capacitors be used. • Placement on the printed circuit board: The decoupling capacitors should be placed as close to the pins as possible. It is recommended that the capacitors be placed on the same side of the board as the device. If space is constricted, the capacitor can be placed on another layer on the PCB using a via; however, ensure that the trace length from the pin to the capacitor is within onequarter inch (6 mm) in length. • Handling high frequency noise: If the board is experiencing high frequency noise, upward of tens of MHz, add a second ceramic-type capacitor in parallel to the above described decoupling capacitor. The value of the second capacitor can be in the range of 0.01 µF to 0.001 µF. Place this second capacitor next to the primary decoupling capacitor. In high-speed circuit designs, consider implementing a decade pair of capacitances as close to the power and ground pins as possible. For example, 0.1 µF in parallel with 0.001 µF. • Maximizing performance: On the board layout from the power supply circuit, run the power and return traces to the decoupling capacitors first, and then to the device pins. This ensures that the decoupling capacitors are first in the power chain. Equally important is to keep the trace length between the capacitor and the power pins to a minimum thereby reducing PCB track inductance. Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to the related section of the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32) 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. 2.1 Basic Connection Requirements Getting started with the PIC32MX5XX/6XX/7XX family of 32-bit Microcontrollers (MCU) requires attention to a minimal set of device pin connections before proceeding with development. The following is a list of pin names, which must always be connected: • All VDD and VSS pins (see Section 2.2 “Decoupling Capacitors”) • All AVDD and AVSS pins–even if the ADC module is not used (see Section 2.2 “Decoupling Capacitors”) • VCAP/VDDCORE pin (see Section 2.3 “Capacitor on Internal Voltage Regulator (VCAP/VDDCORE)”) • MCLR pin (see Section 2.4 “Master Clear (MCLR) Pin”) • PGECx/PGEDx pins–used for In-Circuit Serial Programming (ICSP™) and debugging purposes (see Section 2.5 “ICSP Pins”) • OSC1 and OSC2 pins–when external oscillator source is used (see Section 2.8 “External Oscillator Pins”) The following pin may be required, as well: VREF+/VREF- pins–used when external voltage reference for ADC module is implemented Note: The AVDD and AVSS pins must be connected, regardless of ADC use and the ADC voltage reference source.  2010 Microchip Technology Inc. Preliminary DS61156C-page 35 PIC32MX5XX/6XX/7XX FIGURE 2-1: RECOMMENDED MINIMUM CONNECTION 0.1 µF Ceramic CBP VDD VSS 2.4 Master Clear (MCLR) Pin The MCLR pin provides for two specific device functions: • Device Reset • Device programming and debugging Pulling The MCLR pin low generates a device Reset. Figure 2-2 shows a typical MCLR circuit. During device programming and debugging, the resistance and capacitance that can be added to the pin must be considered. Device programmers and debuggers drive the MCLR pin. Consequently, specific voltage levels (VIH and VIL) and fast signal transitions must not be adversely affected. Therefore, specific values of R and C will need to be adjusted based on the application and PCB requirements. For example, as shown in Figure 2-2, it is recommended that the capacitor C, be isolated from the MCLR pin during programming and debugging operations. Place the components shown in Figure 2-2 within one-quarter inch (6 mm) from the MCLR pin. VDD R R1 MCLR VCAP/VDDCORE CEFC C PIC32MX VSS VDD VDD VSS 0.1 µF Ceramic CBP 0.1 µF Ceramic CBP AVDD AVSS VDD 0.1 µF Ceramic CBP VSS 0.1 µF Ceramic CBP 10  2.2.1 BULK CAPACITORS The use of a bulk capacitor is recommended to improve power supply stability. Typical values range from 4.7 µF to 47 µF. This capacitor should be located as close to the device as possible. FIGURE 2-2: EXAMPLE OF MCLR PIN CONNECTIONS VDD R R1 JP C MCLR PIC32MX 2.3 2.3.1 Capacitor on Internal Voltage Regulator (VCAP/VDDCORE) INTERNAL REGULATOR MODE A low-ESR (1 ohm) capacitor is required on the VCAP/VDDCORE pin, which is used to stabilize the internal voltage regulator output. The VCAP/VDDCORE pin must not be connected to VDD, and must have a CEFC capacitor, with at least a 6V rating, connected to ground. The type can be ceramic or tantalum. Refer to Section 31.0 "Electrical Characteristics" for additional information on CEFC specifications. Note 1: R  10 k is recommended. A suggested starting value is 10 k. Ensure that the MCLR pin VIH and VIL specifications are met. R1  470 will limit any current flowing into MCLR from the external capacitor C, in the event of MCLR pin breakdown, due to Electrostatic Discharge (ESD) or Electrical Overstress (EOS). Ensure that the MCLR pin VIH and VIL specifications are met. The capacitor can be sized to prevent unintentional Resets from brief glitches or to extend the device Reset period during POR. 2: 3: DS61156C-page 36 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 2.5 ICSP Pins 2.6 JTAG The PGECx and PGEDx pins are used for In-Circuit Serial Programming™ (ICSP™) and debugging purposes. It is recommended to keep the trace length between the ICSP connector and the ICSP pins on the device as short as possible. If the ICSP connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the PGECx and PGEDx pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. Ensure that the “Communication Channel Select” (i.e., PGECx/PGEDx pins) programmed into the device matches the physical connections for the ICSP to MPLAB® ICD 2, MPLAB ICD 3, or MPLAB REAL ICE™. For more information on ICD 2, ICD 3 and REAL ICE connection requirements, refer to the following documents that are available on the Microchip web site. • “MPLAB® ICD 2 In-Circuit Debugger User's Guide” DS51331 • “Using MPLAB® ICD 2” (poster) DS51265 • “MPLAB® ICD 2 Design Advisory” DS51566 • “Using MPLAB® ICD 3” (poster) DS51765 • “MPLAB® ICD 3 Design Advisory” DS51764 • “MPLAB® REAL ICE™ In-Circuit Debugger User's Guide” DS51616 • “Using MPLAB® REAL ICE™ Emulator” (poster) DS51749 The TMS, TDO, TDI and TCK pins are used for testing and debugging according to the Joint Test Action Group (JTAG) standard. It is recommended to keep the trace length between the JTAG connector and the JTAG pins on the device as short as possible. If the JTAG connector is expected to experience an ESD event, a series resistor is recommended, with the value in the range of a few tens of Ohms, not to exceed 100 Ohms. Pull-up resistors, series diodes and capacitors on the TMS, TDO, TDI and TCK pins are not recommended as they will interfere with the programmer/debugger communications to the device. If such discrete components are an application requirement, they should be removed from the circuit during programming and debugging. Alternatively, refer to the AC/DC characteristics and timing requirements information in the respective device Flash programming specification for information on capacitive loading limits and pin input voltage high (VIH) and input low (VIL) requirements. 2.7 Trace The trace pins can be connected to a hardware-traceenabled programmer to provide a compress real time instruction trace. When used for trace the TRD3, TRD2, TRD1, TRD0 and TRCLK pins should be dedicated for this use. The trace hardware requires a 22 ohm series resistor between the trace pins and the trace connector.  2010 Microchip Technology Inc. Preliminary DS61156C-page 37 PIC32MX5XX/6XX/7XX 2.8 External Oscillator Pins 2.9 Many MCUs have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator (refer to Section 8.0 "Oscillator Configuration" for details). The oscillator circuit should be placed on the same side of the board as the device. Also, place the oscillator circuit close to the respective oscillator pins, not exceeding one-half inch (12 mm) distance between them. The load capacitors should be placed next to the oscillator itself, on the same side of the board. Use a grounded copper pour around the oscillator circuit to isolate them from surrounding circuits. The grounded copper pour should be routed directly to the MCU ground. Do not run any signal traces or power traces inside the ground pour. Also, if using a two-sided board, avoid any traces on the other side of the board where the crystal is placed. A suggested layout is shown in Figure 2-3. Configuration of Analog and Digital Pins During ICSP Operations If MPLAB ICD 2, ICD 3, or REAL ICE is selected as a debugger, it automatically initializes all of the A/D input pins (ANx) as “digital” pins by setting all bits in the ADPCFG register. The bits in this register that correspond to the A/D pins that are initialized by MPLAB ICD 2, ICD 3, or REAL ICE, must not be cleared by the user application firmware; otherwise, communication errors will result between the debugger and the device. If your application needs to use certain A/D pins as analog input pins during the debug session, the user application must clear the corresponding bits in the ADPCFG register during initialization of the ADC module. When MPLAB ICD 2, ICD 3, or REAL ICE is used as a programmer, the user application firmware must correctly configure the ADPCFG register. Automatic initialization of this register is only done during debugger operation. Failure to correctly configure the register(s) will result in all A/D pins being recognized as analog input pins, resulting in the port value being read as a logic '0', which may affect user application functionality. FIGURE 2-3: SUGGESTED OSCILLATOR CIRCUIT PLACEMENT Oscillator Secondary Guard Trace Guard Ring Main Oscillator 2.10 Unused I/Os Unused I/O pins should not be allowed to float as inputs. They can be configured as outputs and driven to a logic-low state. Alternatively, inputs can be reserved by connecting the pin to VSS through a 1k to 10k resistor and configuring the pin as an input. DS61156C-page 38 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 3.0 PIC32MX MCU Note 1: This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. To complement the information in this data sheet, refer to Section 2. “MCU” (DS61113) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). Resources for the MIPS32® M4K® Processor Core are available at http://www.mips.com. 2: Some registers and associated bits described in this section may not be available on all devices. Refer to Section 4.0 “Memory Organization” in this data sheet for device-specific register and bit information. The MCU module is the heart of the PIC32MX5XX/6XX/7XX family processor. The MCU fetches instructions, decodes each instruction, fetches source operands, executes each instruction and writes the results of instruction execution to the proper destinations. - Atomic interrupt enable/disable - GPR shadow registers to minimize latency for interrupt handlers - Bit field manipulation instructions MIPS16e™ Code Compression - 16-bit encoding of 32-bit instructions to improve code density - Special PC-relative instructions for efficient loading of addresses and constants - SAVE & RESTORE macro instructions for setting up and tearing down stack frames within subroutines - Improved support for handling 8 and 16-bit data types Simple Fixed Mapping Translation (FMT) mechanism Simple Dual Bus Interface - Independent 32-bit address and data busses - Transactions can be aborted to improve interrupt latency Autonomous Multiply/Divide Unit - Maximum issue rate of one 32x16 multiply per clock - Maximum issue rate of one 32x32 multiply every other clock - Early-in iterative divide. Minimum 11 and maximum 33 clock latency (dividend (rs) sign extension-dependent) Power Control - Minimum frequency: 0 MHz - Low-Power mode (triggered by WAIT instruction) - Extensive use of local gated clocks EJTAG Debug and Instruction Trace - Support for single stepping - Virtual instruction and data address/value - Breakpoints - PC tracing with trace compression • • • • 3.1 Features • • 5-Stage Pipeline • 32-Bit Address and Data Paths • MIPS32 Enhanced Architecture (Release 2) - Multiply-Accumulate and Multiply-Subtract instructions - Targeted Multiply instruction - Zero/One Detect instructions - WAIT instruction - Conditional Move instructions (MOVN, MOVZ) - Vectored interrupts - Programmable exception vector base • FIGURE 3-1: MCU MCU BLOCK DIAGRAM EJTAG Trace TAP Trace I/F Off-Chip Debug I/F Dual Bus I/F Bus Matrix DS61156C-page 39 MDU Execution Core (RF/ALU/Shift) FMT Bus Interface System Coprocessor Power Management  2010 Microchip Technology Inc. Preliminary PIC32MX5XX/6XX/7XX 3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU) The PIC32MX5XX/6XX/7XX family core contains several logic blocks working together in parallel, providing an efficient high-performance computing engine. The following blocks are included with the core: • • • • • • • • Execution Unit Multiply/Divide Unit (MDU) System Control Coprocessor (CP0) Fixed Mapping Translation (FMT) Dual Internal Bus interfaces Power Management MIPS16e Support Enhanced JTAG (EJTAG) Controller The PIC32MX5XX/6XX/7XX family core includes a Multiply/Divide Unit (MDU) that contains a separate pipeline for multiply and divide operations. This pipeline operates in parallel with the Integer Unit (IU) pipeline and does not stall when the IU pipeline stalls. This allows MDU operations to be partially masked by system stalls and/or other integer unit instructions. The high-performance MDU consists of a 32x16 booth recoded multiplier, result/accumulation registers (HI and LO), a divide state machine, and the necessary multiplexers and control logic. The first number shown (‘32’ of 32x16) represents the rs operand. The second number (‘16’ of 32x16) represents the rt operand. The PIC32MX core only checks the value of the latter (rt) operand to determine how many times the operation must pass through the multiplier. The 16x16 and 32x16 operations pass through the multiplier once. A 32x32 operation passes through the multiplier twice. The MDU supports execution of one 16x16 or 32x16 multiply operation every clock cycle; 32x32 multiply operations can be issued every other clock cycle. Appropriate interlocks are implemented to stall the issuance of back-to-back 32x32 multiply operations. The multiply operand size is automatically determined by logic built into the MDU. Divide operations are implemented with a simple 1 bit per clock iterative algorithm. An early-in detection checks the sign extension of the dividend (rs) operand. If rs is 8 bits wide, 23 iterations are skipped. For a 16-bit wide rs, 15 iterations are skipped and for a 24-bit wide rs, 7 iterations are skipped. Any attempt to issue a subsequent MDU instruction while a divide is still active causes an IU pipeline stall until the divide operation is completed. Table 3-1 lists the repeat rate (peak issue rate of cycles until the operation can be reissued) and latency (number of cycles until a result is available) for the PIC32MX core multiply and divide instructions. The approximate latency and repeat rates are listed in terms of pipeline clocks. 3.2.1 EXECUTION UNIT The PIC32MX5XX/6XX/7XX family core execution unit implements a load/store architecture with single-cycle ALU operations (logical, shift, add, subtract) and an autonomous multiply/divide unit. The core contains thirty-two 32-bit General Purpose Registers (GPRs) used for integer operations and address calculation. One additional register file shadow set (containing thirty-two registers) is added to minimize context switching overhead during interrupt/exception processing. The register file consists of two read ports and one write port and is fully bypassed to minimize operation latency in the pipeline. The execution unit includes: • 32-bit adder used for calculating the data address • Address unit for calculating the next instruction address • Logic for branch determination and branch target address calculation • Load aligner • Bypass multiplexers used to avoid stalls when executing instruction streams where data producing instructions are followed closely by consumers of their results • Leading Zero/One detect unit for implementing the CLZ and CLO instructions • Arithmetic Logic Unit (ALU) for performing bitwise logical operations • Shifter and store aligner DS61156C-page 40 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE 3-1: PIC32MX5XX/6XX/7XX FAMILY CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT LATENCIES AND REPEAT RATES Opcode MULT/MULTU, MADD/MADDU, MSUB/MSUBU MUL DIV/DIVU Operand Size (mul rt) (div rs) 16 bits 32 bits 16 bits 32 bits 8 bits 16 bits 24 bits 32 bits The MIPS architecture defines that the result of a multiply or divide operation be placed in the HI and LO registers. Using the Move-From-HI (MFHI) and MoveFrom-LO (MFLO) instructions, these values can be transferred to the General Purpose Register file. In addition to the HI/LO targeted operations, the MIPS32 architecture also defines a multiply instruction, MUL, which places the least significant results in the primary register file instead of the HI/LO register pair. By avoiding the explicit MFLO instruction required when using the LO register, and by supporting multiple destination registers, the throughput of multiply-intensive operations is increased. Two other instructions, Multiply-Add (MADD) and Multiply-Subtract (MSUB), are used to perform the multiply-accumulate and multiply-subtract operations. The MADD instruction multiplies two numbers and then adds the product to the current contents of the HI and LO registers. Similarly, the MSUB instruction multiplies two operands and then subtracts the product from the HI and LO registers. The MADD and MSUB operations are commonly used in DSP algorithms. Latency 1 2 2 3 12 19 26 33 Repeat Rate 1 2 1 2 11 18 25 32 3.2.3 SYSTEM CONTROL COPROCESSOR (CP0) In the MIPS architecture, CP0 is responsible for the virtual-to-physical address translation, the exception control system, the processor’s diagnostics capability, the operating modes (Kernel, User and Debug) and whether interrupts are enabled or disabled. Configuration information, such as presence of options like MIPS16e, is also available by accessing the CP0 registers, listed in Table 3-2.  2010 Microchip Technology Inc. Preliminary DS61156C-page 41 PIC32MX5XX/6XX/7XX TABLE 3-2: Register Number 0-6 7 8 9 10 11 12 12 12 12 13 14 15 15 16 16 16 16 17-22 23 24 25-29 30 31 Note 1: 2: COPROCESSOR 0 REGISTERS Register Name Function Reserved in the PIC32MX5XX/6XX/7XX family core. Enables access via the RDHWR instruction to selected hardware registers. Reports the address for the most recent address-related exception. Processor cycle count. Reserved in the PIC32MX5XX/6XX/7XX family core. Timer interrupt control. Processor status and control. Interrupt system status and control. Shadow register set status and control. Provides mapping from vectored interrupt to a shadow set. Cause of last general exception. Program counter at last exception. Processor identification and revision. Exception vector base register. Configuration register. Configuration Register 1. Configuration Register 2. Configuration Register 3. Reserved in the PIC32MX5XX/6XX/7XX family core. Debug control and exception status. Program counter at last debug exception. Reserved in the PIC32MX5XX/6XX/7XX family core. Program counter at last error. Debug handler scratchpad register. (1) Reserved HWREna BadVAddr(1) Count(1) Reserved Compare Status(1) IntCtl (1) SRSCtl(1) SRSMap(1) Cause(1) EPC (1) PRId EBASE Config Config1 Config2 Config3 Reserved Debug (2) DEPC(2) Reserved ErrorEPC(1) DESAVE (2) Registers used in exception processing. Registers used during debug. DS61156C-page 42 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Coprocessor 0 also contains the logic for identifying and managing exceptions. Exceptions can be caused by a variety of sources, including alignment errors in data, external events or program errors. Table 3-3 lists the exception types in order of priority. TABLE 3-3: Exception Reset DSS DINT NMI Interrupt DIB AdEL IBE DBp Sys Bp RI CpU CEU Ov Tr DDBL/DDBS AdEL AdES DBE DDBL PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES Description Assertion MCLR or a Power-on Reset (POR). EJTAG debug single step. EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the EjtagBrk bit in the ECR register. Assertion of NMI signal. Assertion of unmasked hardware or software interrupt signal. EJTAG debug hardware instruction break matched. Fetch address alignment error. Fetch reference to protected address. Instruction fetch bus error. EJTAG breakpoint (execution of SDBBP instruction). Execution of SYSCALL instruction. Execution of BREAK instruction. Execution of a reserved instruction. Execution of a coprocessor instruction for a coprocessor that is not enabled. Execution of a CorExtend instruction when CorExtend is not enabled. Execution of an arithmetic instruction that overflowed. Execution of a trap (when trap condition is true). EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value). Load address alignment error. Load reference to protected address. Store address alignment error. Store to protected address. Load or store bus error. EJTAG data hardware breakpoint matched in load data compare.  2010 Microchip Technology Inc. Preliminary DS61156C-page 43 PIC32MX5XX/6XX/7XX 3.3 Power Management 3.4 EJTAG Debug Support The PIC32MX5XX/6XX/7XX family core offers a number of power management features, including low-power design, active power management and power-down modes of operation. The core is a static design that supports slowing or Halting the clocks, which reduces system power consumption during Idle periods. The PIC32MX5XX/6XX/7XX family core provides for an Enhanced JTAG (EJTAG) interface for use in the software debug of application and kernel code. In addition to standard User mode and Kernel modes of operation, the PIC32MX5XX/6XX/7XX family core provides a Debug mode that is entered after a debug exception (derived from a hardware breakpoint, singlestep exception, etc.) is taken and continues until a Debug Exception Return (DERET) instruction is executed. During this time, the processor executes the debug exception handler routine. The EJTAG interface operates through the Test Access Port (TAP), a serial communication port used for transferring test data in and out of the PIC32MX5XX/6XX/7XX family core. In addition to the standard JTAG instructions, special instructions defined in the EJTAG specification define which registers are selected and how they are used. 3.3.1 INSTRUCTION-CONTROLLED POWER MANAGEMENT The mechanism for invoking Power-Down mode is through execution of the WAIT instruction. For more information on power management, see Section 27.0 “Power-Saving Features”. 3.3.2 LOCAL CLOCK GATING The majority of the power consumed by the PIC32MX5XX/6XX/7XX family core is in the clock tree and clocking registers. The PIC32MX family uses extensive use of local gated clocks to reduce this dynamic power consumption. DS61156C-page 44 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX 4.0 Note: MEMORY ORGANIZATION This data sheet summarizes the features of the PIC32MX5XX/6XX/7XX family of devices. It is not intended to be a comprehensive reference source. For detailed information, refer to Section 3. “Memory Organization” (DS61115) in the “PIC32MX Family Reference Manual”, which is available from the Microchip web site (www.microchip.com/PIC32). 4.1 PIC32MX5XX/6XX/7XX Memory Layout PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB of unified virtual memory address space. All memory regions, including program, data memory, SFRs and Configuration registers, reside in this address space at their respective unique addresses. The program and data memories can be optionally partitioned into user and kernel memories. In addition, the data memory can be made executable, allowing PIC32MX5XX/6XX/7XX devices to execute from data memory. Key features include: • 32-bit native data width • Separate User (KUSEG) and Kernel (KSEG0/KSEG1) mode address space • Flexible program Flash memory partitioning • Flexible data RAM partitioning for data and program space • Separate boot Flash memory for protected code • Robust bus exception handling to intercept runaway code • Simple memory mapping with Fixed Mapping Translation (FMT) unit • Cacheable (KSEG0) and non-cacheable (KSEG1) address regions PIC32MX5XX/6XX/7XX microcontrollers implement two address schemes: virtual and physical. All hardware resources, such as program memory, data memory and peripherals, are located at their respective physical addresses. Virtual addresses are exclusively used by the CPU to fetch and execute instructions as well as access peripherals. Physical addresses are used by bus master peripherals, such as DMA and the Flash controller, that access memory independently of the CPU. The memory maps for the PIC32MX5XX/6XX/7XX devices are shown in Figure 4-1, Figure 4-2 and Figure 4-3. 4.1.1 PERIPHERAL REGISTERS LOCATIONS Table 4-1 through Table 4-44 contain the peripheral address maps for the PIC32MX5XX/6XX/7XX devices. Peripherals located on the PB bus are mapped to 512-byte boundaries. Peripherals on the FPB bus are mapped to 4-Kbyte boundaries.  2010 Microchip Technology Inc. Preliminary DS61156C-page 45 PIC32MX5XX/6XX/7XX FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L, PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND PIC32MX775F256L DEVICES(1) Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD040000 0xBD03FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D040000 0x9D03FFFF Program Flash(2) 0x9D000000 0x80008000 0x80007FFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D040000 0x1D03FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61156C-page 46 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L, PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND PIC32MX775F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0010000 0xA000FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80010000 0x8000FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM (2) Physical Memory Map 0xFFFFFFFF Reserved Device Configuration Registers Reserved Reserved Reserved KSEG1 SFRs Reserved 0x1FC03000 Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 Reserved 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 Reserved 0x1D07FFFF Program Flash(2) 0x1D000000 0x00010000 0x0000FFFF 0x00000000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information).  2010 Microchip Technology Inc. Preliminary DS61156C-page 47 PIC32MX5XX/6XX/7XX FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L, PIC32MX795F512H AND PIC32MX795F512L DEVICES Virtual Memory Map 0xFFFFFFFF 0xBFC03000 0xBFC02FFF 0xBFC02FF0 0xBFC02FEF Boot Flash 0xBFC00000 0xBF900000 0xBF8FFFFF 0xBF800000 0xBD080000 0xBD07FFFF Program Flash(2) 0xBD000000 0xA0020000 0xA001FFFF RAM(2) 0xA0000000 0x9FC02FF0 0x9FC02FFF 0x9FC02FEF 0x9FC02FEF Boot Flash 0x9FC00000 Reserved 0x9D080000 0x9D07FFFF Program Flash(2) 0x9D000000 0x80020000 0x8001FFFF RAM(2) 0x80000000 0x00000000 Note 1: 2: Reserved Reserved RAM(2) Reserved Program Flash(2) 0x1D000000 0x00020000 0x0001FFFF 0x00000000 Reserved Reserved Device Configuration Registers Device Configuration Registers Boot Flash 0x1FC00000 0x1F900000 0x1F8FFFFF KSEG0 SFRs 0x1F800000 Reserved 0x1D080000 0x1D07FFFF 0x1FC03000 0x1FC02FFF 0x1FC02FF0 0x1FC02FEF Reserved Reserved KSEG1 SFRs Reserved Reserved Reserved Device Configuration Registers Physical Memory Map 0xFFFFFFFF Memory areas are not shown to scale. The size of this memory region is programmable (see Section 3. “Memory Organization” (DS61115)) and can be changed by initialization code provided by end user development tools (refer to the specific development tool documentation for information). DS61156C-page 48 Preliminary  2010 Microchip Technology Inc.  2010 Microchip Technology Inc. TABLE 4-1: Virtual Address (BF88_#) Register Name BUS MATRIX REGISTER MAP Bit Range Bits All Resets 0040 — — — 0000 0000 — — — — — — — — — — 0000 0000 0000 0000 xxxx xxxx — — — — — — — — — — — — BMXPUPBA 0000 0000 xxxx xxxx BMXBOOTSZ 0000 3000 BMXPUPBA BMXPFMSZ 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 BMXCON(1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — BMXCHEDMA — — — — — — — — — — — — — — — — — — — — BMXWSDRM — — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F — — — — — BMXARB — 2010 BMXDKPBA(1) 2020 BMXDUDBA(1) 2030 BMXDUPBA(1) 2040 BMXDRMSZ 2050 BMXPUPBA(1) 2060 BMXPFMSZ BMXDKPBA BMXDUDBA BMXDUPBA BMXDRMSZ Preliminary DS61156C-page 49 PIC32MX5XX/6XX/7XX 2070 BMXBOOTSZ Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-2: Virtual Address (BF88_#) Bit Range Register Name INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) Bits All Resets DS61156C-page 50 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — VEC — INT2EP — — INT1EP — SS0 — 0000 INT0EP 0000 0000 0000 0000 0000 IPTMR U1ATXIF U1ARXIF I2C1ASIF INT2IF — — — U3BTXIF U1ARXIE I2C1ASIE INT2IE — — — U3BTXIE INT0IP CS0IP INT1IP IC1IP U1AEIF — IC2IF USBIF U3ARXIF — T2IF FCEIF U3AEIF — INT1IF DMA7IF U2ATXIF OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE I2C2ASIE — U2BEIE — — — — IC5IF IC1IF DMA5IF U2AEIF CMP2IF — CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE CNIF — T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF T4IF CTIF 1030 IFS0 31:16 I2C1MIF 15:0 31:16 INT3IF IC3EIF RTCCIF — — I2CSIF OC3IF IC2EIF FSCMIF — — I2CBIF IC3IF IC1EIF — — — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF — — — — U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF 0000 0000 DMA1IF DMA0IF 0000 Preliminary  2010 Microchip Technology Inc. 1040 IFS1 15:0 31:16 15:0 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C3ASIF I2C3ASIF I2C2AMIF — U3BEIF — IC2IE USBIE U3ARXIE — U2BTXIF — T2IE FCEIE U3AEIE — U2BRXIF — INT1IE DMA7IE U2ATXIE I2C2ABIF — — U3BRXIF U1AEIE IC5IE IC1IE DMA5IE U2AEIE 0000 1050 IFS2 0000 U1BTXIF U1BRXIF T5IE T1IE DMA4IE CMP2IE — IC4EIF 0000 T4IE CTIE 1060 IEC0 31:16 I2C1MIE I2C1SIE 15:0 31:16 INT3IE IC3EIE RTCCIE — — — — — — OC3IE IC2EIE FSCMIE — — — — — — I2C1BIE SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE IC3IE IC1EIE — — — — — — — T3IE — — — — I2C1ABIE OC2IE CAN1IE U3ATXIE 0000 0000 DMA1IE DMA0IE 0000 AD1IE — IC5EIE CNIE — 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE — U3BEIE — U2BTXIE — U2BRXIE — — — — I2C2ABIE — — — — — — U3BRXIE 0000 1080 1090 10A0 Legend: IEC2 IPC0 IPC1 0000 U1BTXIE U1BRXIE IC4EIE 0000 0000 0000 0000 0000 INT0IS CS0IS INT1IS IC1IS CS1IS CTIS OC1IS T1IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Note 1: TABLE 4-2: Virtual Address (BF88_#) Bit Range Register Name INTERRUPT REGISTER MAP FOR THE PIC32MX575F256H AND PIC32MX575F512H DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10B0 10C0 10D0 10E0 IPC2 IPC3 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — INT2IP IC2IP INT3IP IC3IP INT4IP IC4IP — IC5IP AD1IP I2C1IP U2AIP — INT2IS IC2IS INT3IS IC3IS INT4IS IC4IS — — IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — OC2IP T2IP OC3IP T3IP OC4IP T4IP OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC2IS T2IS OC3IS T3IS OC4IS T4IS OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS CAN1IS FCEIS U2BIS — — — 10F0 IPC6 15:0 Preliminary DS61156C-page 51 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP DMA5IP — USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP CAN1IP FCEIP U2BIP — PIC32MX5XX/6XX/7XX 0000 0000 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 0000 1120 1130 1140 1150 IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS DMA5IS — — USBIS U3BIS U1BIS 0000 0000 0000 0000 0000 0000 0000 0000 Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) DS61156C-page 52 PIC32MX5XX/6XX/7XX TABLE 4-3: INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF — U1BRXIF T5IE T1IE DMA4IE CMP2IE — U1BRXIE CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE DMA1IE AD1IE — IC5EIE CNIF — IC4EIF T4IE CTIE DMA0IE CNIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF — U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE — U1BTXIE — — — — — — — — T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1ATXIF U1ARXIF U1AEIF — IC2IF USBIF U3ARXIF I2C3ASIF — U3BEIF — IC2IE USBIE U3ARXIE — T2IF FCEIF U3AEIF I2C3ASIF — U2BTXIF — T2IE FCEIE U3AEIE — INT1IF DMA7IF U2ATXIF I2C2AMIF — U2BRXIF — INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF — U3ATXIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2CSIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2CBIF IC3IF IC1EIF — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF — INT2IF — — — 1040 IFS1 Preliminary  2010 Microchip Technology Inc. 15:0 31:16 15:0 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF — U3BRXIF U1AEIE I2C1ABIE OC2IE — U3ATXIE 1050 IFS2 — I2C1BIE IC3IE IC1EIE — — — — — — — — — — — — U1ATXIE U3BTXIF U1ARXIE 1060 IEC0 31:16 I2C1MIE 15:0 31:16 INT3IE IC3EIE RTCCIE — — — — — — — — — — SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE — — — INT2IE — — — U3BTXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE — U2BTXIE — U2BRXIE — — — — — — — — — U2BEIE — — — — — — — — — U3BRXIE — U3BEIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-3: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR THE PIC32MX675F256H, PIC32MX675F512H AND PIC32MX695F512H DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — INT4IP IC4IP — IC5IP AD1IP I2C1IP U2AIP — INT4IS IC4IS — — IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC4IS T4IS OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS — — — FCEIS U2BIS ETHIS 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP DMA5IP — USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP — FCEIP U2BIP ETHIP Preliminary DS61156C-page 53 31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 PIC32MX5XX/6XX/7XX 1120 1130 1140 1150 Legend: Note 1: IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS DMA5IS — — USBIS U3BIS U1BIS 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) DS61156C-page 54 PIC32MX5XX/6XX/7XX TABLE 4-4: INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF — U1BRXIF T5IE T1IE DMA4IE CMP2IE — U1BRXIE CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE DMA1IE AD1IE — IC5EIE CNIF — IC4EIF T4IE CTIE DMA0IE CNIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF — U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE — U1BTXIE — — — — — — — — T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF — — U3BTXIF U1ARXIE U1AEIF — IC2IF USBIF U3ARXIF I2C3ASIF — U3BEIF — IC2IE USBIE U3ARXIE — T2IF FCEIF U3AEIF I2C3ASIF — U2BTXIF — T2IE FCEIE U3AEIE — INT1IF DMA7IF U2ATXIF I2C2AMIF — U2BRXIF — INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2CSIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2CBIF IC3IF IC1EIF — — — I2C1BIE IC3IE IC1EIE — — — — — — — — — — — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF — — — U1ATXIE 1040 IFS1 Preliminary  2010 Microchip Technology Inc. 15:0 31:16 15:0 31:16 15:0 31:16 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF — U3BRXIF U1AEIE I2C1ABIE OC2IE CAN1IE U3ATXIE 1050 IFS2 1060 IEC0 SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE ETHIE — — — INT2IE CAN2IE — — U3BTXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE — U2BTXIE — U2BRXIE — — — — — — — — — U2BEIE — — — — — — — — — U3BRXIE — U3BEIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-4: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — INT4IP IC4IP — IC5IP AD1IP I2C1IP U2AIP — INT4IS IC4IS — — IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS — — — — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC4IS T4IS OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS CAN1IS FCEIS U2BIS ETHIS 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP — DMA3IP DMA1IP DMA7IP DMA5IP CAN2IP USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP CAN1IP FCEIP U2BIP ETHIP Preliminary DS61156C-page 55 31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 PIC32MX5XX/6XX/7XX 1120 1130 1140 1150 Legend: Note 1: IPC9 IPC10 IPC11 IPC12 DMA3IS DMA1IS DMA7IS DMA5IS CAN2IS USBIS U3BIS U1BIS 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-5: Virtual Address (BF88_#) Bit Range Register Name INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) Bits All Resets DS61156C-page 56 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — 0000 0000 0000 0000 0000 0000 VEC IPTMR U1ATXIF U1ARXIF I2C1ASIF INT2IF — I2C2BIF — U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF — U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF — U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF — U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF — U1BRXIF T5IE T1IE DMA4IE CMP2IE — U1BRXIE CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP OC4IP T4IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE DMA1IE AD1IE — IC5EIE CNIF — IC4EIF T4IE CTIE DMA0IE CNIE — IC4EIE T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — — — I2CSIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — — — I2CBIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — — — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF — I2C2SIF — — U1ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 1040 IFS1 15:0 31:16 15:0 31:16 15:0 31:16 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF I2C2ABIF — U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE — U1BTXIE — — — — — — — — — — — U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE I2C1ABIE OC2IE CAN1IE U3ATXIE Preliminary  2010 Microchip Technology Inc. 1050 IFS2 1060 IEC0 SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE T3IE — I2C2SIE — — INT2IE — I2C2BIE — U3BTXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP INT4IP IC4IP 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE — U3BRXIE — U3BEIE — U2BTXIE — U2BRXIE — — — — — — — — — — — U2BEIE — — — — — — — — — — 1080 1090 10A0 10B0 10C0 10D0 Legend: Note 1: IEC2 IPC0 IPC1 IPC2 IPC3 IPC4 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS INT4IS IC4IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS OC4IS T4IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-5: Virtual Address (BF88_#) Bit Range Register Name INTERRUPT REGISTER MAP FOR THE PIC32MX575F512L AND PIC32MX575F256L DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10E0 IPC5 31:16 15:0 31:16 — — — — — — — — — — — — SPI1IP IC5IP AD1IP I2C1IP U2AIP SPI1IS IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS DMA5IS — — — USBIS U3BIS U1BIS — — — — — — — — — — — — OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS CAN1IS FCEIS U2BIS — — — 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP DMA5IP — USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP CAN1IP FCEIP U2BIP — 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 Preliminary DS61156C-page 57 1120 1130 1140 1150 Legend: Note 1: IPC9 IPC10 IPC11 IPC12 PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) DS61156C-page 58 PIC32MX5XX/6XX/7XX TABLE 4-6: INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF — U1BRXIF T5IE T1IE DMA4IE CMP2IE — U1BRXIE CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE DMA1IE AD1IE — IC5EIE CNIF — IC4EIF T4IE CTIE DMA0IE CNIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF — U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE — U1BTXIE — — — — — — — — T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1ATXIF U1ARXIF U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF — U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF — U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF — U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF — U3ATXIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2CSIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2CBIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF I2C1ASIF T3IF ETHIF I2C2SIF — — U1ATXIE INT2IF — I2C2BIF — U3BTXIF U1ARXIE 1040 IFS1 Preliminary  2010 Microchip Technology Inc. 15:0 31:16 15:0 31:16 15:0 31:16 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF — U3BRXIF U1AEIE I2C1ABIE OC2IE — U3ATXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE 1050 IFS2 1060 IEC0 SPI1ATXIE SPI1ARXIE SPI1AEIE SPI1TXIE SPI1RXIE I2C1AMIE I2C1ASIE T3IE ETHIE I2C2SIE — — INT2IE — I2C2BIE — U3BTXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE — U2BTXIE — U2BRXIE — — — — — — — — — U2BEIE — — — — — — — — — U3BRXIE — U3BEIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-6: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX675F256L, PIC32MX675F512L AND PIC32MX695F512L DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — INT4IP IC4IP SPI1IP IC5IP AD1IP I2C1IP U2AIP INT4IS IC4IS SPI1IS IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS DMA5IS — — — USBIS U3BIS U1BIS — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC4IS T4IS OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS — — — FCEIS U2BIS ETHIS 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP DMA5IP — USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP — FCEIP U2BIP ETHIP Preliminary DS61156C-page 59 31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 PIC32MX5XX/6XX/7XX 1120 1130 1140 1150 Legend: Note 1: IPC9 IPC10 IPC11 IPC12 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF88_#) DS61156C-page 60 PIC32MX5XX/6XX/7XX TABLE 4-7: INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 OC5IF OC1IF DMA6IF U2ARXIF I2C2ASIF — U2BEIF OC5IE OC1IE DMA6IE U2ARXIE IC5IF IC1IF DMA5IF U2AEIF CMP2IF — U1BRXIF T5IE T1IE DMA4IE CMP2IE — U1BRXIE CMP1IF — U1BEIF INT4IE INT0IE DMA3IE CMP1IE — U1BEIE CS1IP CTIP OC1IP T1IP OC2IP T2IP OC3IP T3IP PMPIF — PMPEIF OC4IE CS1IE DMA2IE PMPIE — PMPEIE AD1IF — IC5EIF IC4IE CS0IE DMA1IE AD1IE — IC5EIE CNIF — IC4EIF T4IE CTIE DMA0IE CNIE — IC4EIE 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2C2ABIF — U1BTXIF IC5IE IC1IE DMA5IE U2AEIE I2C2ABIE — U1BTXIE — — — — — — — — T5IF T1IF DMA4IF INT4IF INT0IF DMA3IF OC4IF CS1IF DMA2IF IC4IF CS0IF DMA1IF T4IF CTIF DMA0IF 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 1000 INTCON 1010 INTSTAT 1020 IPTMR 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — FRZ — — — — — — — MVEC — — — — — — — — — TPC — RIPL — — — — — — — — — — — — — — INT4EP — — INT3EP — — INT2EP — — INT1EP — SS0 INT0EP — VEC IPTMR U1ATXIF U1ARXIF I2C1ASIF INT2IF CAN2IF I2C2BIF — U3BTXIF U1ARXIE U1AEIF SPI1TXIF IC2IF USBIF U3ARXIF I2C3ASIF — U3BEIF SPI1RXIF T2IF FCEIF U3AEIF I2C3ASIF — U2BTXIF SPI1EIF INT1IF DMA7IF U2ATXIF I2C2AMIF — U2BRXIF SPI1EIE INT1IE DMA7IE U2ATXIE I2C1ABIF OC2IF CAN1IF U3ATXIF 1030 IFS0 31:16 15:0 31:16 I2C1MIF INT3IF IC3EIF RTCCIF — — I2C1MIE INT3IE IC3EIE RTCCIE — — — — — — — — — — I2CSIF OC3IF IC2EIF FSCMIF — — I2C1SIE OC3IE IC2EIE FSCMIE — — — — — — — — — — I2CBIF IC3IF IC1EIF I2C2MIF — — I2C1BIE IC3IE IC1EIE I2C2MIE — — — — — — — — — — SPI1ATXIF SPI1ARXIF SPI1AEIF I2C1AMIF T3IF ETHIF I2C2SIF — — U1ATXIE 1040 IFS1 Preliminary  2010 Microchip Technology Inc. 15:0 31:16 15:0 31:16 15:0 31:16 SPI3ATXIF SPI3ARXIF SPI3AEIF SPI2ATXIF SPI2ARXIF SPI2AEIF I2C3AMIF — U3BRXIF U1AEIE SPI1TXIE SPI1RXIE IC2IE USBIE U3ARXIE T2IE FCEIE U3AEIE 1050 IFS2 1060 IEC0 SPI1ATXIE SPI1ARXIE SPI1AEIE I2C1AMIE I2C1ASIE I2C1ABIE T3IE ETHIE I2C2SIE — — INT2IE CAN2IE I2C2BIE — U3BTXIE INT0IP CS0IP INT1IP IC1IP INT2IP IC2IP INT3IP IC3IP OC2IE CAN1IE U3ATXIE 1070 IEC1 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 SPI3ATXIE SPI3ARXIE SPI3AEIE SPI2ATXIE SPI2ARXIE SPI2AEIE I2C3AMIE I2C3ASIE I2C3ASIE I2C2AMIE I2C2ASIE — U2BTXIE — U2BRXIE — — — — — — — — — U2BEIE — — — — — — — — — U3BRXIE — U3BEIE 1080 1090 10A0 10B0 10C0 Legend: Note 1: IEC2 IPC0 IPC1 IPC2 IPC3 INT0IS CS0IS INT1IS IC1IS INT2IS IC2IS INT3IS IC3IS CS1IS CTIS OC1IS T1IS OC2IS T2IS OC3IS T3IS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-7: Virtual Address (BF88_#) INTERRUPT REGISTER MAP FOR PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 10D0 10E0 IPC4 IPC5 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — INT4IP IC4IP SPI1IP IC5IP AD1IP I2C1IP U2AIP INT4IS IC4IS SPI1IS IC5IS AD1IS I2C1IS U2AIS SPI2AIS I2C2AIS CMP1IS RTCCIS I2C2IS DMA3IS DMA1IS DMA7IS DMA5IS CAN2IS USBIS U3BIS U1BIS — — — — — — — — — — — — — — — — — — OC4IP T4IP OC5IP T5IP CNIP U1AIP SPI1AIP I2C1AIP OC4IS T4IS OC5IS T5IS CNIS U1AIS SPI1AIS I2C1AIS CMP2IS PMPIS FSCMIS U3AIS SPI3AIS I2C3AIS DMA2IS DMA0IS DMA6IS DMA4IS CAN1IS FCEIS U2BIS ETHIS 10F0 IPC6 15:0 1100 IPC7 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — SPI2AIP I2C2AIP CMP1IP RTCCIP I2C2IP DMA3IP DMA1IP DMA7IP DMA5IP CAN2IP USBIP U3BIP U1BIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CMP2IP PMPIP FSCMIP U3AIP SPI3AIP I2C3AIP DMA2IP DMA0IP DMA6IP DMA4IP CAN1IP FCEIP U2BIP ETHIP Preliminary DS61156C-page 61 31:16 1110 IPC8 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 PIC32MX5XX/6XX/7XX 1120 1130 1140 1150 Legend: Note 1: IPC9 IPC10 IPC11 IPC12 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-8: Virtual Address (BF80_#) Bit Range Register Name TIMER1-TIMER5 REGISTER MAP(1) Bits All Resets DS61156C-page 62 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0600 T1CON 0610 0620 TMR1 PR1 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — ON — — — ON — — — ON — — — ON — — — FRZ — — — FRZ — — — FRZ — — — FRZ — — — FRZ — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — SIDL — — — TWDIS — — — — — — — — — — — — — — — — — — — TWIP — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — TGATE — — — — — — — — — — — — — — — — — — — — — — TCKPS — — — TCKPS — — — TCKPS — — — TCKPS — — — — — — — — — — — — — — — — — — — — — — T32 — — — — — — — T32 — — — — — — — TSYNC — — — — — — — — — — — — — — — — — — — TCS — — — TCS — — — TCS — — — TCS — — — TCS — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF 0000 0000 0000 0000 0000 FFFF TCKPS TMR1 PR1 0800 T2CON 0810 0820 TMR2 PR2 TMR2 PR2 0A00 T3CON 0A10 0A20 TMR3 PR3 Preliminary  2010 Microchip Technology Inc. TMR3 PR3 0C00 T4CON 0C10 0C20 TMR4 PR4 TMR4 PR4 0E00 T5CON 0E10 0E20 Legend: Note 1: TMR5 PR5 TMR5 PR5 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  2010 Microchip Technology Inc. TABLE 4-9: Virtual Address (BF80_#) Register Name INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP Bits All Resets 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx — ICI — — ICOV — ICBNE — — ICM — 0000 0000 xxxx xxxx Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2000 2010 2200 2210 2400 2410 2600 2610 2800 2810 IC1CON(1) IC1BUF IC2CON(1) IC2BUF IC3CON (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR — ICI — — ICOV — ICBNE — — ICM — IC1BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC2BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR IC3BUF IC4CON (1) IC3BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR Preliminary DS61156C-page 63 IC4BUF IC5CON(1) IC5BUF IC4BUF — ON — FRZ — SIDL — — — — — — — FEDGE — C32 — ICTMR PIC32MX5XX/6XX/7XX IC5BUF Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-10: Virtual Address (BF80_#) Bit Range Register Name OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP(1) Bits All Resets DS61156C-page 64 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 OC1CON 3010 3020 OC1R OC1RS 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — 0000 0000 xxxx xxxx xxxx xxxx OC1R OC1RS — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — 3200 OC2CON 3210 3220 OC2R OC2RS 0000 0000 xxxx xxxx xxxx xxxx OC2R OC2RS — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — 3400 OC3CON 3410 3420 OC3R OC3RS 0000 0000 xxxx xxxx xxxx xxxx Preliminary  2010 Microchip Technology Inc. OC3R OC3RS — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — 3600 OC4CON 3610 3620 OC4R OC4RS 0000 0000 xxxx xxxx xxxx xxxx OC4R OC4RS — ON — FRZ — SIDL — — — — — — — — — — — — — — — OC32 — OCFLT — OCTSEL — — OCM — 3800 OC5CON 3810 3820 Legend: Note 1: OC5R OC5RS 0000 0000 xxxx xxxx xxxx xxxx OC5R OC5RS x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-11: Virtual Address (BF80_#) Register Name I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 0000 0000 — — — — — RCEN — S — — — — — — RCEN — S — — — — — PEN — R/W — — — — — — PEN — R/W — — — — — RSEN — RBF — — — — — — RSEN — RBF — — — — — SEN — TBF — — — — — — SEN — TBF 0000 0000 0000 0000 — — — ACKEN — P — — — — — — ACKEN — P 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 I2CT1DATA — — GCEN — IWCOL — — STREN — I2COV — — ACKDT — D/A I2CR1DATA I2CT1DATA — — GCEN — IWCOL — — — — — — STREN — I2COV — — — — — — ACKDT — D/A — — — — ADD — — — — — — — DISSLW — GCSTAT — — — — — — — SMEN — ADD10 MSK I2C1BRG — — — — — STRICT — — — — — — — A10M — BCL I2CR1DATA  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5000 I2C1ACON 5010 I2C1ASTAT 5020 I2C1AADD 5030 I2C1AMSK 5040 I2C1ABRG 5050 I2C1ATRN 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ACKSTAT — — — — — — — — — — — ON — ACKSTAT — — — — — — — — — — — ON — ACKSTAT — FRZ — TRSTAT — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — FRZ — TRSTAT — SIDL — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — SIDL — — — SCLREL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — SCLREL — — — STRICT — — — — — — — — — — — — STRICT — — — — — — — — A10M — BCL — — — — — — — — — — A10M — BCL — — — — — — DISSLW — GCSTAT — — — — — — — — DISSLW — GCSTAT — — SMEN — ADD10 — — — — — — — — SMEN — ADD10 — — GCEN — IWCOL — — — — — STREN — I2COV — — — — — ACKDT — D/A — — — — — ACKEN — P — — — — RCEN — S — — PEN — R/W — — RSEN — RBF — — SEN — TBF — ADD MSK I2C1BRG 5060 I2C1ARCV 5100 I2C2ACON 5110 I2C2ASTAT 5120 I2C2AADD 5130 I2C2AMSK 5140 I2C2ABRG 5150 I2C2ATRN Preliminary DS61156C-page 65 PIC32MX5XX/6XX/7XX 5160 I2C2ARCV 5200 I2C3ACON 5210 I2C3ASTAT Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-11: Virtual Address (BF80_#) Register Name I2C1, I2C1A, I2C2A AND I2C3A REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61156C-page 66 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5220 I2C3AADD 5230 I2C3AMSK 5240 I2C3ABRG 5250 I2C3ATRN 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — ON — ACKSTAT — — — — — — — — — — — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — — — — — — — — — — — SIDL — — — — — — — — — — — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — — — — — — — — — — STRICT — — — — — — — — — — — — — — — — — — — — — A10M — BCL — — — — — — — — — — — — — — — — — DISSLW — GCSTAT — — — — — — — — — — — — — — — SMEN — ADD10 — — — — — — — — — — — — — GCEN — IWCOL — — — — — — — — — — — STREN — I2COV — — — — — — — — — — — ACKDT — D/A — — — — — — — — — — — ACKEN — P — — — — — — — — — — — RCEN — S — — — — — — — — — — — PEN — R/W — — — — — — — — — — — RSEN — RBF — — — — — — — — — — — SEN — TBF — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADD MSK I2C1BRG I2CT1DATA I2CR1DATA 5260 I2C3ARCV 5300 5310 5320 5330 5340 5350 5360 Legend: Note 1: I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C1BRG I2C1TRN I2C1RCV Preliminary  2010 Microchip Technology Inc. ADD MSK I2C1BRG I2CT1DATA I2CR1DATA x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  2010 Microchip Technology Inc. TABLE 4-12: Virtual Address (BF80_#) I2C2 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 0000 — — — — — — — — — — — — — — — — 0000 0000 0000 0000 — — 0000 0000 0000 0000 I2CT1DATA — — — I2CR1DATA Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5400 I2C2CON 5410 I2C2STAT 5420 I2C2ADD 5430 I2C2MSK 5440 I2C2BRG 5450 I2C2TRN 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — — — — — — FRZ — TRSTAT — — — — — — — — — — — SIDL — — — — — — — — — — — — — SCLREL — — — — — — — — — — — — — STRICT — — — — — — — — — — — — A10M — BCL — — — — — — — — — — DISSLW — GCSTAT — — — — — — — — SMEN — ADD10 — — — — — — — — GCEN — IWCOL — — — — — STREN — I2COV — — — — — ACKDT — D/A — — — — — ACKEN — P — — — — RCEN — S — — PEN — R/W — — RSEN — RBF — — SEN — TBF — 15:0 ACKSTAT ADD MSK I2C2BRG Preliminary DS61156C-page 67 5460 I2C2RCV Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. PIC32MX5XX/6XX/7XX DS61156C-page 68 PIC32MX5XX/6XX/7XX TABLE 4-13: Virtual Address (BF80_#) Register Name UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP Bits All Resets 0000 0000 0000 FERR — — — — OERR — — — — URXDA — — — — STSEL URXDA — — — — STSEL URXDA — — — — STSEL URXDA — 0110 0000 0000 0000 0000 0000 0000 — LPBACK — ABAUD ADDEN — — — — ABAUD ADDEN — — — — ABAUD ADDEN — — RXINV RIDLE — — — — RXINV RIDLE — — — — RXINV RIDLE — — BRGH PERR — — — — BRGH PERR — — — — BRGH PERR — 0000 0000 0000 FERR — — — — OERR — — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK 0000 0000 0000 FERR — — — — OERR — — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK 0000 0000 0000 FERR — OERR — 0110 0000 0000 PDSEL PDSEL PDSEL Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 U1AMODE(1) 6010 U1ASTA (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — — — — — ON — — — — — — — ON — — — — — — — ON — — — — FRZ — — — — — — — FRZ — — — — — — — FRZ — — — — — — — FRZ — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — UTXBF — — — — — — — — UTXBF — — — — — — — UTXBF — — — — — — — — UTXBF — — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — RX8 — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — WAKE — LPBACK — ABAUD ADDEN — — — — RXINV RIDLE — — — — BRGH PERR — — — — — — STSEL UEN PDSEL ADDR URXISEL — — — — WAKE — — — UTXISEL 6020 U1ATXREG 6030 U1ARXREG 6040 U1ABRG (1) Transmit Register Receive Register BRG 6200 U1BMODE 6210 (1) U1BSTA(1) ADDR URXISEL — — — — WAKE — — — Preliminary  2010 Microchip Technology Inc. UTXISEL 6220 U1BTXREG 6230 U1BRXREG 6240 U1BBRG(1) (1) Transmit Register Receive Register BRG UEN 6400 U2AMODE 6410 U2ASTA (1) ADDR URXISEL — — — — WAKE — — — UTXISEL 6420 U2ATXREG 6430 U2ARXREG 6440 U2ABRG 6600 6610 (1) Transmit Register Receive Register BRG U2BMODE(1) U2BSTA (1) ADDR URXISEL — — UTXISEL 6620 U2BTXREG Legend: Note 1: Transmit Register x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-13: Virtual Address (BF80_#) Register Name UART1A, UART1B, UART2A, UART2B, UART3A AND UART3B REGISTER MAP (CONTINUED) Bits All Resets 0000 0000 — — — — — — STSEL URXDA — — — — STSEL URXDA — — — 0000 0000 — LPBACK — ABAUD ADDEN — — — — ABAUD ADDEN — — — — RXINV RIDLE — — — — RXINV RIDLE — — — — BRGH PERR — — — — BRGH PERR — — — 0000 0000 0000 FERR — — — — OERR — — — — 0110 0000 0000 0000 0000 0000 0000 — LPBACK 0000 0000 0000 PDSEL FERR — — — OERR — — — PDSEL  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6630 U2BRXREG 6640 U2BBRG (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — ON — — — — — — — ON — — — — — — — — — — FRZ — — — — — — — FRZ — — — — — — — — — — SIDL — UTXINV — — — — — — SIDL — UTXINV — — — — — — — — — IREN — URXEN — — — — — — IREN — URXEN — — — — — — — — — RTSMD — UTXBRK — — — — — — — — UTXBRK — — — — — — — — — — — UTXEN — — — — — — — — UTXEN — — — — — — — — — — UTXBF — — — — — — — — UTXBF — — — — — — RX8 — — ADM_EN TRMT — TX8 — RX8 — — — ADM_EN TRMT — TX8 — RX8 — — — — WAKE — — — — — — — — — — — Receive Register BRG UEN 6800 U3AMODE 6810 (1) U3ASTA(1) ADDR URXISEL — — — — WAKE — — — UTXISEL 6820 U3ATXREG 6830 U3ARXREG 6840 U3ABRG(1) (1) Transmit Register Receive Register BRG Preliminary DS61156C-page 69 6A00 U3BMODE 6A10 U3BSTA (1) ADDR URXISEL — — — — — — PIC32MX5XX/6XX/7XX UTXISEL 0110 0000 0000 0000 0000 0000 0000 6A20 U3BTXREG 6A30 U3BRXREG 6A40 U3BBRG Legend: Note 1: (1) Transmit Register Receive Register BRG x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-14: Virtual Address (BF80_#) Bit Range Register Name SPI1A, SPI2A AND SPI3A REGISTER MAP(1) Bits All Resets DS61156C-page 70 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5800 SPI1ACON 5810 SPI1ASTAT 5820 SPI1ABUF 5830 SPI1ABRG 5A00 SPI2ACON 5A10 SPI2ASTAT 5A20 SPI2ABUF 5A30 SPI2ABRG 5C00 SPI3ACON 5C10 SPI3ASTAT 5C20 SPI3ABUF 5C30 SPI3ABRG Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 FRMEN ON — — FRMSYNC FRMPOL FRZ — — SIDL — — MSSEN DISSDO — FRMSYPW MODE32 SPIBUSY FRMCNT MODE16 — SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — TXBUFELM SPIFE ENHBUF 0000 0000 0000 SPIRBF 0000 0000 0000 STXISEL SPITBE — SRXISEL SPITBF RXBUFELM DATA — — FRMEN ON — — — — FRZ — — — — SIDL — — — — — MSSEN DISSDO — — FRMSYPW MODE32 SPIBUSY — — MODE16 — — — FRMCNT SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — — BRG — — — — TXBUFELM SPITBE — SPITBF SPIRBF SPIFE STXISEL SRXISEL — — — — 0000 0000 FRMSYNC FRMPOL ENHBUF 0000 0000 0000 0000 0000 0000 RXBUFELM DATA — — FRMEN ON — — — — FRZ — — — — SIDL — — — — — MSSEN DISSDO — — FRMSYPW MODE32 SPIBUSY — — MODE16 — — — FRMCNT SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — — BRG — — — — TXBUFELM SPITBE — SPITBF SPIRBF SPIFE STXISEL SRXISEL — — — — Preliminary  2010 Microchip Technology Inc. 0000 0000 FRMSYNC FRMPOL ENHBUF 0000 0000 0000 0000 0000 0000 RXBUFELM DATA — — — — — — — — — — — — — — — — — — — BRG — — — — 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.  2010 Microchip Technology Inc. TABLE 4-15: Virtual Address (BF80_#) SPI1 REGISTER MAP FOR PIC32MX575F512L, PIC32MX575F256L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 0000 SPIRBF 0000 0000 0000 — — — BRG — — — — 0000 0000 Register Name Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5E00 SPI1CON 5E10 SPI1STAT 5E20 SPI1BUF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 FRMEN ON — — FRMSYNC FRMPOL FRZ — — SIDL — — MSSEN DISSDO — FRMSYPW MODE32 SPIBUSY FRMCNT MODE16 — SMP — CKE SPITUR — SSEN — SRMT — CKP — SPIROV — MSTEN — SPIRBE — — — — — TXBUFELM SPIFE ENHBUF 0000 STXISEL SPITBE — SRXISEL SPITBF RXBUFELM DATA — — — — — — — — — — — — — — — — 5E30 SPI1BRG Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary DS61156C-page 71 PIC32MX5XX/6XX/7XX DS61156C-page 72 PIC32MX5XX/6XX/7XX TABLE 4-16: Virtual Address (BF80_#) Register Name Bit Range ADC REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 CH0SA — — PCFG3 — CSSL3 — — PCFG2 — CSSL2 — — PCFG1 — CSSL1 — — PCFG0 — CSSL0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9000 AD1CON1(1) 9010 AD1CON2 9020 AD1CON3 9040 (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — VCFG2 — ADRC CH0NB — — PCFG15 — CSSL15 — FRZ — VCFG1 — — — — — PCFG14 — CSSL14 — SIDL — VCFG0 — — — — — PCFG13 — CSSL13 — — — OFFCAL — — — — PCFG12 — CSSL12 — — — — — — — CSCNA — SAMC — FORM — — — — — — — — — BUFS — CH0NA — SSRC — — — — — — PCFG6 — CSSL6 — — — — — — PCFG5 — CSSL5 — CLRASAM — — — — — PCFG4 — CSSL4 — — — — — ASAM — — — SAMP — BUFM — — DONE — ALTS — SMPI ADCS (1) AD1CHS(1) CH0SB — — PCFG11 — CSSL11 — — PCFG10 — CSSL10 — — PCFG9 — CSSL9 — — PCFG8 — CSSL8 — — PCFG7 — CSSL7 9060 AD1PCFG(1) 9050 AD1CSSL (1) 9070 ADC1BUF0 9080 ADC1BUF1 9090 ADC1BUF2 90A0 ADC1BUF3 90B0 ADC1BUF4 90C0 ADC1BUF5 90D0 ADC1BUF6 90E0 ADC1BUF7 ADC Result Word 0 (ADC1BUF0) ADC Result Word 1 (ADC1BUF1) ADC Result Word 2 (ADC1BUF2) ADC Result Word 3 (ADC1BUF3) ADC Result Word 4 (ADC1BUF4) ADC Result Word 5 (ADC1BUF5) ADC Result Word 6 (ADC1BUF6) ADC Result Word 7 (ADC1BUF7) ADC Result Word 8 (ADC1BUF8) ADC Result Word 9 (ADC1BUF9) ADC Result Word A (ADC1BUFA) ADC Result Word B (ADC1BUFB) Preliminary  2010 Microchip Technology Inc. 90F0 ADC1BUF8 9100 ADC1BUF9 9110 ADC1BUFA 9120 ADC1BUFB Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-16: Virtual Address (BF80_#) Register Name Bit Range ADC REGISTER MAP (CONTINUED) Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 9130 ADC1BUFC 9140 ADC1BUFD 9150 ADC1BUFE 9160 ADC1BUFF Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 ADC Result Word C (ADC1BUFC) ADC Result Word D (ADC1BUFD) ADC Result Word E (ADC1BUFE) ADC Result Word F (ADC1BUFF) x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary DS61156C-page 73 PIC32MX5XX/6XX/7XX Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3030 DCRCCON 3040 DCRCDATA 3050 DCRCXOR Legend: Note 1: 31:16 15:0 31:16 15:0 31:16 15:0 — — — — BYTO — WBO — PLEN — BITO — CRCEN — CRCAPP — CRCTYP — — — — — — CRCCH — 0000 0000 0000 0000 0000 0000 DCRCDATA DCRCXOR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156C-page 74 PIC32MX5XX/6XX/7XX TABLE 4-17: Virtual Address (BF88_#) Register Name DMA GLOBAL REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3000 DMACON(1) 3010 DMASTAT 31:16 15:0 31:16 15:0 31:16 15:0 — ON — — — FRZ — — — — — — — SUSPEND — — — BUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — RDWR — — — — — — DMACH — — — 3020 DMAADDR Legend: Note 1: DMAADDR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-18: DMA CRC REGISTER MAP(1) Bits Preliminary  2010 Microchip Technology Inc. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) Bits All Resets 0000 0000 00FF — CHCCIE CHCCIF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — 0000 0000 CHPRI CHPDAT — CHEN CFORCE — — — — — — CHSDIE CHSDIF  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3060 DCH0CON 3070 DCH0ECON 3080 3090 DCH0INT DCH0SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — CHEN CFORCE — CHAED CABORT CHSHIE CHSHIF — CHCHN PATEN CHDDIE CHDDIF — CHAEN SIRQEN CHDHIE CHDHIF — — AIRQEN CHBCIE CHBCIF — CHEDET — — CHPRI CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — 30A0 DCH0DSA 30B0 DCH0SSIZ 30C0 DCH0DSIZ 30D0 DCH0SPTR 30E0 DCH0DPTR 30F0 DCH0CSIZ 3100 DCH0CPTR 3110 DCH0DAT CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR Preliminary DS61156C-page 75 PIC32MX5XX/6XX/7XX 3120 DCH1CON 3130 DCH1ECON 3140 3150 DCH1INT DCH1SSA CHAIRQ CHSIRQ CHSSA CHDSA — — — — — — — — — 3160 DCH1DSA 3170 DCH1SSIZ Legend: Note 1: CHSSIZ x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61156C-page 76 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3180 DCH1DSIZ 3190 DCH1SPTR 31A0 DCH1DPTR 31B0 DCH1CSIZ 31C0 DCH1CPTR 31D0 DCH1DAT 31E0 DCH2CON 31F0 DCH2ECON 3200 3210 DCH2INT DCH2SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — CHEN CFORCE — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF Preliminary  2010 Microchip Technology Inc. CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 3220 DCH2DSA 3230 DCH2SSIZ 3240 DCH2DSIZ 3250 DCH2SPTR 3260 DCH2DPTR 3270 DCH2CSIZ 3280 DCH2CPTR 3290 DCH2DAT 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 00FF — CHCCIE CHCCIF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 32A0 DCH3CON 32B0 DCH3ECON 32C0 DCH3INT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — CHEN CFORCE — CHAED CABORT CHSHIE CHSHIF — CHCHN PATEN CHDDIE CHDDIF — CHAEN SIRQEN CHDHIE CHDHIF — — AIRQEN CHBCIE CHBCIF — CHEDET — — CHPRI CHAIRQ CHSDIE CHSDIF CHSIRQ — — 32D0 DCH3SSA 32E0 DCH3DSA 32F0 DCH3SSIZ 3300 DCH3DSIZ 3310 DCH3SPTR 3320 DCH3DPTR 3330 DCH3CSIZ 3340 DCH3CPTR 3350 DCH3DAT CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE — — CHSDIE CHSDIF — CHEN — — — — — — — CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF Preliminary DS61156C-page 77 PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — 0000 0000 3360 DCH4CON 3370 DCH4ECON 3380 3390 DCH4INT DCH4SSA CHAIRQ CHSIRQ CHSSA CHDSA — — — — — — — — — 33A0 DCH4DSA 33B0 DCH4SSIZ Legend: Note 1: CHSSIZ15:0> x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61156C-page 78 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 33C0 DCH4DSIZ 33D0 DCH4SPTR 33E0 DCH4DPTR 33F0 DCH4CSIZ 3400 DCH4CPTR 3410 DCH4DAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — — — — — — — CHEN CFORCE — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF 3420 DCH5CON 3430 DCH5ECON 3440 3450 3460 DCH5INT DCH5SSA DCH5DSA Preliminary  2010 Microchip Technology Inc. CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 3470 DCH5SSIZ 3480 DCH5DSIZ 3490 DCH5SPTR 34A0 DCH5DPTR 34B0 DCH5CSIZ 34C0 DCH5CPTR 34D0 DCH5DAT Legend: Note 1: 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED) Bits All Resets 0000 0000 00FF — CHCCIE CHCCIF — CHTAIE CHTAIF — CHERIE CHERIF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — — CHAED CABORT CHSHIE CHSHIF — — — — — — — — CHCHN PATEN CHDDIE CHDDIF — — — — — — — — CHAEN SIRQEN CHDHIE CHDHIF — — — — — — — — — AIRQEN CHBCIE CHBCIF — — — — — — — — CHEDET — CHCCIE CHCCIF — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 34E0 DCH6CON 34F0 DCH6ECON 3500 3510 DCH6INT DCH6SSA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — — CHEN CFORCE — CHAED CABORT CHSHIE CHSHIF — CHCHN PATEN CHDDIE CHDDIF — CHAEN SIRQEN CHDHIE CHDHIF — — AIRQEN CHBCIE CHBCIF — CHEDET — — CHPRI CHAIRQ CHSDIE CHSDIF CHSIRQ — — CHSSA CHDSA — — — — — — — — — CHBUSY — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CHCHNS — CFORCE — — CHSDIE CHSDIF — CHEN — — — — — — — 3520 DCH6DSA 3530 DCH6SSIZ 3540 DCH6DSIZ 3550 DCH6SPTR 3560 DCH6DPTR 3570 DCH6CSIZ 3580 DCH6CPTR 3590 DCH6DAT CHSSIZ CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT CHPRI — CHTAIE CHTAIF — CHERIE CHERIF Preliminary DS61156C-page 79 PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 00FF FF00 0000 0000 0000 0000 0000 0000 — — — — — — — 0000 0000 35A0 DCH7CON 35B0 DCH7ECON 35C0 DCH7INT CHAIRQ CHSIRQ 35D0 DCH7SSA 35E0 DCH7DSA 35F0 DCH7SSIZ Legend: Note 1: CHSSA CHDSA — — — — — — — — — CHSSIZ x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-19: Virtual Address (BF88_#) Register Name DMA CHANNELS 0-7 REGISTER MAP(1) (CONTINUED) Bits All Resets Bit Range DS61156C-page 80 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 3600 DCH7DSIZ 3610 DCH7SPTR 3620 DCH7DPTR 3630 DCH7CSIZ 3640 DCH7CPTR 3650 DCH7DAT 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 CHDSIZ CHSPTR CHDPTR CHCSIZ CHCPTR CHPDAT Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary  2010 Microchip Technology Inc. TABLE 4-20: Virtual Address (BF80_#) Bit Range Register Name COMPARATOR REGISTER MAP(1) Bits All Resets 0000 0000 0000 0000 0000 0000 Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name  2010 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 A000 CM1CON A010 CM2CON A060 CMSTAT 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ON — — — COE — COE — FRZ — CPOL — CPOL — SIDL — — — — — — — — — — — — — — — — — — — — — — — — — COUT — COUT — — — — — — — — — — — — — — — — — CREF — CREF — — — — — — — — — — — — — — — — — C2OUT — — — C1OUT EVPOL EVPOL CCH CCH Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-21: COMPARATOR VOLTAGE REFERENCE REGISTER MAP(1) Bits Preliminary DS61156C-page 81 PIC32MX5XX/6XX/7XX 9800 CVRCON Legend: Note 1: 31:16 15:0 — ON — — — — — — — — — — — — — — — — — CVROE — CVRR — CVRSS — — — — 0000 0000 CVR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F000 OSCCON F010 OSCTUN 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — ON — — — — — — — — — — — — — — — — — — — — — PLLODIV COSC — — — — — — — — — — — — — — — — — — — — — — — — — RCDIV NOSC — — — — — CM — — — — — — — VREGS — — — CLKLOCK — — — — — EXTR — — SOSCRDY ULOCK — — — — SWR — — — LOCK — — — — — — PBDIV SLPEN — — SWDTPS — WDTO — — — SLEEP — — — IDLE — — CF — — — — PLLMULT UFRCEN SOSCEN — — — — BOR — — OSWEN — — WDTCLR — POR — SWRST 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 TUN 0000 WDTCON F600 RCON F610 RSWRST Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset. All Resets(2) Bit Range Register Name DS61156C-page 82 PIC32MX5XX/6XX/7XX TABLE 4-22: Virtual Address (BF80_#) Register Name FLASH CONTROLLER REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F400 NVMCON(1) F410 NVMKEY (1) 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — WR — WREN — WRERR — LVDERR — LVDSTAT — — — — — — — — — — — — — — — — — — NVMOP NVMKEY NVMADDR NVMDATA NVMSRCADDR F420 NVMADDR F430 F440 Legend: Note 1: NVMDATA NVMSRC ADDR x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary  2010 Microchip Technology Inc. TABLE 4-23: SYSTEM CONTROL REGISTER MAP(1,2) Bits Virtual Address (BF88_#) All Resets Bit Range Register Name  2010 Microchip Technology Inc. TABLE 4-24: Virtual Address (BF88_#) PORTA REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 C6FF 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6000 6010 6020 6030 Legend: Note TRISA PORTA LATA ODCA 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISA15 — RA15 — LATA15 — ODCA15 — TRISA14 — RA14 — LATA14 — ODCA14 — — — — — — — — — — — — — — — — — — — — — — — — — TRISA10 — RA10 — LATA10 — ODCA10 — TRISA9 — RA9 — LATA9 — ODCA9 — — — — — — — — — TRISA7 — RA7 — LATA7 — ODCA7 — TRISA6 — RA6 — LATA6 — ODCA6 — TRISA5 — RA5 — LATA5 — ODCA5 — TRISA4 — RA4 — LATA4 — ODCA4 — TRISA3 — RA3 — LATA3 — ODCA3 — TRISA2 — RA2 — LATA2 — ODCA2 — TRISA1 — RA1 — LATA1 — ODCA1 — TRISA0 — RA0 — LATA0 — ODCA0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Preliminary DS61156C-page 83 TABLE 4-25: PORTB REGISTER MAP(1) Bits PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6040 6050 6060 6070 Legend: Note TRISB PORTB LATB ODCB 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISB15 — RB15 — LATB15 — ODCB15 — TRISB14 — RB14 — LATB14 — ODCB14 — TRISB13 — RB13 — LATB13 — ODCB13 — TRISB12 — RB12 — LATB12 — ODCB12 — TRISB11 — RB11 — LATB11 — ODCB11 — TRISB10 — RB10 — LATB10 — ODCB10 — TRISB9 — RB9 — LATB9 — ODCB9 — TRISB8 — RB8 — LATB8 — ODCB8 — TRISB7 — RB7 — LATB7 — ODCB7 — TRISB6 — RB6 — LATB6 — ODCB6 — TRISB5 — RB5 — LATB5 — ODCB5 — TRISB4 — RB4 — LATB4 — ODCB4 — TRISB3 — RB3 — LATB3 — ODCB3 — TRISB2 — RB2 — LATB2 — ODCB2 — TRISB1 — RB1 — LATB1 — ODCB1 — TRISB0 — RB0 — LATB0 — ODCB0 0000 FFFF 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Virtual Address (BF88_#) Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 TRISC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISC15 — RC15 — LATC15 — ODCC15 — TRISC14 — RC14 — LATC14 — ODCC14 — TRISC13 — RC13 — LATC13 — ODCC13 — TRISC12 — RC12 — LATC12 — ODCC12 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISC4 — RC4 — LATC4 — ODCC4 — TRISC3 — RC3 — LATC3 — ODCC3 — TRISC2 — RC2 — LATC2 — ODCC2 — TRISC1 — RC1 — LATC1 — ODCC1 — — — — — — — — 0000 F00F 0000 xxxx 0000 xxxx 0000 0000 6090 PORTC 60A0 60B0 LATC ODCC Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156C-page 84 PIC32MX5XX/6XX/7XX TABLE 4-26: PORTC REGISTER MAP FOR PIC32MX575F256H, PIC32MX675F256H, PIC32MX575F512H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 F000 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6080 6090 60A0 60B0 Legend: Note TRISC PORTC LATC ODCC 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISC15 — RC15 — LATC15 — ODCC15 — TRISC14 — RC14 — LATC14 — ODCC14 — TRISC13 — RC13 — LATC13 — ODCC13 — TRISC12 — RC12 — LATC12 — ODCC12 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Preliminary  2010 Microchip Technology Inc. TABLE 4-27: PORTC REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60C0 TRISD 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISD15 — RD15 — LAT15 — ODCD15 — TRISD14 — RD14 — LAT14 — ODCD14 — TRISD13 — RD13 — LAT13 — ODCD13 — TRISD12 — RD12 — LAT12 — ODCD12 — TRISD11 — RD11 — LATD11 — ODCD11 — TRISD10 — RD10 — LATD10 — ODCD10 — TRISD9 — RD9 — LATD9 — ODCD9 — TRISD8 — RD8 — LATD8 — ODCD8 — TRISD7 — RD7 — LATD7 — ODCD7 — TRISD6 — RD6 — LATD6 — ODCD6 — TRISD5 — RD5 — LATD5 — ODCD5 — TRISD4 — RD4 — LATD4 — ODCD4 — TRISD3 — RD3 — LATD3 — ODCD3 — TRISD2 — RD2 — LATD2 — ODCD2 — TRISD1 — RD1 — LATD1 — ODCD1 — TRISD0 — RD0 — LATD0 — ODCD0 0000 FFFF 0000 xxxx 0000 xxxx 0000 0000 60D0 PORTD 60E0 60F0 Legend: Note 1: LATD ODCD x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name  2010 Microchip Technology Inc. TABLE 4-28: Virtual Address (BF88_#) PORTD REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 0FFF 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 60C0 60D0 60E0 60F0 Legend: Note TRISD PORTD LATD ODCD 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISD11 — RD11 — LATD11 — ODCD11 — TRISD10 — RD10 — LATD10 — ODCD10 — TRISD9 — RD9 — LATD9 — ODCD9 — TRISD8 — RD8 — LATD8 — ODCD8 — TRISD7 — RD7 — LATD7 — ODCD7 — TRISD6 — RD6 — LATD6 — ODCD6 — TRISD5 — RD5 — LATD5 — ODCD5 — TRISD4 — RD4 — LATD4 — ODCD4 — TRISD3 — RD3 — LATD3 — ODCD3 — TRISD2 — RD2 — LATD2 — ODCD2 — TRISD1 — RD1 — LATD1 — ODCD1 — TRISD0 — RD0 — LATD0 — ODCD0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Preliminary DS61156C-page 85 TABLE 4-29: PORTD REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) PIC32MX5XX/6XX/7XX Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 6110 6120 6130 Legend: Note TRISE PORTE LATE ODCE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISE9 — RE9 — LATE9 — ODCE9 — TRISE8 — RE8 — LATE8 — ODCE8 — TRISE7 — RE7 — LATE7 — ODCE7 — TRISE6 — RE6 — LATE6 — 0DCE6 — TRISE5 — RE5 — LATE5 — ODCE5 — TRISE4 — RE4 — LATE4 — ODCE4 — TRISE3 — RE3 — LATE3 — ODCE3 — TRISE2 — RE2 — LATE2 — ODCE2 — TRISE1 — RE1 — LATE1 — ODCE1 — TRISE0 — RE0 — LATE0 — ODCE0 0000 03FF 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: All Resets Bit Range Register Name  2010 Microchip Technology Inc. TABLE 4-30: Virtual Address (BF88_#) PORTE REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 00FF 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6100 6110 6120 6130 Legend: Note TRISE PORTE LATE ODCE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISE7 — RE7 — LATE7 — ODCE7 — TRISE6 — RE6 — LATE6 — 0DCE6 — TRISE5 — RE5 — LATE5 — ODCE5 — TRISE4 — RE4 — LATE4 — ODCE4 — TRISE3 — RE3 — LATE3 — ODCE3 — TRISE2 — RE2 — LATE2 — ODCE2 — TRISE1 — RE1 — LATE1 — ODCE1 — TRISE0 — RE0 — LATE0 — ODCE0 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: Preliminary DS61156C-page 86 TABLE 4-31: PORTE REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) PIC32MX5XX/6XX/7XX Bits Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 6150 6160 6170 Legend: Note TRISF PORTF LATF ODCF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — TRISF13 — RF13 — LATF13 — ODCF13 — TRISF12 — RF12 — LATF12 — ODCF12 — — — — — — — — — — — — — — — — — — — — — — — — — TRISF8 — RF8 — LATF8 — ODCF8 — — — — — — — — — — — — — — — — — TRISF5 — RF5 — LATF5 — ODCF5 — TRISF4 — RF4 — LATF4 — ODCF4 — TRISF3 — RF3 — LATF3 — ODCF3 — TRISF2 — RF2 — LATF2 — ODCF2 — TRISF1 — RF1 — LATF1 — ODCF1 — TRISF0 — RF0 — LATF0 — ODCF0 0000 313F 0000 xxxx 0000 xxxx 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. 1: All Resets Bit Range Register Name  2010 Microchip Technology Inc. TABLE 4-32: Virtual Address (BF88_#) PORTF REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 003B 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6140 TRISF 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISF5 — RF5 — LATF5 — ODCF5 — TRISF4 — RF4 — LATF4 — ODCF4 — TRISF3 — RF3 — LATF3 — ODCF3 — — — — — — — — — TRISF1 — RF1 — LATF1 — ODCF1 — TRISF0 — RF0 — LATF0 — ODCF0 6150 PORTF 6160 6170 Legend: Note 1: LATF ODCF x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary DS61156C-page 87 TABLE 4-33: PORTF REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) PIC32MX5XX/6XX/7XX Bits Virtual Address (BF88_#) Virtual Address (BF88_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 TRISG 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — TRISG15 — RG15 — LATG15 — ODCG15 — TRISG14 — RG14 — LATG14 — ODCG14 — TRISG13 — RG13 — LATG13 — ODCG13 — TRISG12 — RG12 — LATG12 — ODCG12 — — — — — — — — — — — — — — — — — TRISG9 — RG9 — LATG9 — ODCG9 — TRISG8 — RG8 — LATG8 — ODCG8 — TRISG7 — RG7 — LATG7 — ODCG7 — TRISG6 — RG6 — LATG6 — ODCG6 — — — — — — — — — — — — — — — — — TRISG3 — RG3 — LATG3 — ODCG3 — TRISG2 — RG2 — LATG2 — ODCG2 — TRISG1 — RG1 — LATG1 — ODCG1 — TRISG0 — RG0 — LATG0 — ODCG0 0000 F3CF 0000 xxxx 0000 xxxx 0000 0000 6190 PORTG 61A0 61B0 Legend: Note 1: LATG ODCG x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. All Resets Bit Range Register Name DS61156C-page 88 PIC32MX5XX/6XX/7XX TABLE 4-34: PORTG REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits All Resets 0000 03CC 0000 xxxx 0000 xxxx 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 6180 TRISG 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — TRISG9 — RG9 — LATG9 — ODCG9 — TRISG8 — RG8 — LATG8 — ODCG8 — TRISG7 — RG7 — LATG7 — ODCG7 — TRISG6 — RG6 — LATG6 — ODCG6 — — — — — — — — — — — — — — — — — TRISG3 — RG3 — LATG3 — ODCG3 — TRISG2 — RG2 — LATG2 — ODCG2 — — — — — — — — — — — — — — — — 6190 PORTG 61A0 61B0 LATG ODCG Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Preliminary  2010 Microchip Technology Inc. TABLE 4-35: PORTG REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits Virtual Address (BF88_#) All Resets Bit Range Register Name  2010 Microchip Technology Inc. TABLE 4-36: Virtual Address (BF88_#) CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256L, PIC32MX575F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES(1) Bits All Resets 0000 0000 0000 0000 0000 Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61C0 CNCON 61D0 61E0 Legend: Note 1: CNEN CNPUE 31:16 15:0 31:16 15:0 31:16 15:0 — ON — CNEN15 — — FRZ — CNEN14 — — SIDL — CNEN13 — — — — CNEN12 — — — — CNEN11 — — — — CNEN10 — — — — CNEN9 — CNPUE9 — — — CNEN8 — CNPUE8 — — — CNEN7 — CNPUE7 — — — CNEN6 — CNPUE6 — — CNEN21 CNEN5 CNPUE21 CNPUE5 — — CNEN20 CNEN4 CNPUE20 CNPUE4 — — CNEN19 CNEN3 CNPUE3 — — CNEN18 CNEN2 CNPUE2 — — CNEN17 CNEN1 CNPUE1 — — CNEN16 CNEN0 CNPUE0 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-37: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES(1) Bits Preliminary DS61156C-page 89 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 61C0 CNCON 61D0 61E0 Legend: Note 1: CNEN CNPUE 31:16 15:0 31:16 15:0 31:16 15:0 — ON — CNEN15 — — FRZ — CNEN14 — — SIDL — CNEN13 — — — — CNEN12 — — — — CNEN11 — — — — CNEN10 — — — — CNEN9 — CNPUE9 — — — CNEN8 — CNPUE8 — — — CNEN7 — CNPUE7 — — — CNEN6 — CNPUE6 — — — CNEN5 — CNPUE5 — — — CNEN4 — CNPUE4 — — — CNEN3 — CNPUE3 — — CNEN18 CNEN2 CNPUE2 — — CNEN17 CNEN1 CNPUE1 — — CNEN16 CNEN0 CNPUE0 0000 0000 0000 0000 0000 CNPUE18 CNPUE17 CNPUE16 0000 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-38: Virtual Address (BF80_#) Bit Range Register Name PARALLEL MASTER PORT REGISTER MAP(1) Bits All Resets Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 F200 DDPCON 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — JTAGEN — TROEN — — — — 0000 0008 Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All Resets Bit Range Register Name DS61156C-page 90 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 7000 PMCON 31:16 15:0 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — BUSY — — FRZ — — — SIDL — — — — — — — — — PMPTTL — MODE16 — — PTWREN — — — PTRDEN — — — — — — — — — ALP — — — CS2P — — — CS1P — — — — — — — WRSP — — — RDSP — — 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 ADRMUX INCM CSF WAITB ADDR 7010 PMMODE 7020 PMADDR 7030 PMDOUT 7040 7050 7060 Legend: Note 1: PMDIN PMAEN PMSTAT IRQM MODE WAITM WAITE 15:0 CS2EN/A15 CS1EN/A14 DATAOUT DATAIN — — IBF — — IBOV — — — — — — — — IB3F — — IB2F — — IB1F — — IB0F — — OBE — — OBUF — — — — — — — — OB3E — — OB2E — — OB1E — — OB0E 0000 0000 0000 0080 PTEN Preliminary  2010 Microchip Technology Inc. x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. TABLE 4-39: PROGRAMMING AND DIAGNOSTICS REGISTER MAP Bits TABLE 4-40: Virtual Address (BF88_#) Register Name PREFETCH REGISTER MAP Bits All Resets 0000 — 0000 0000 00xx LLOCK — — LTYPE — — — — — xxx0 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx CHELRU CHELRU CHEHIT CHEMIS CHEPFABT 0000  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 4000 CHECON(1,2) 4010 CHEACC (1) 31:16 15:0 15:0 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — LMASK — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — PFMWS — CHECOH 0000 DCSZ PREFEN 31:16 CHEWEN 31:16 LTAGBOOT — CHEIDX LVALID 4020 CHETAG(1) 4030 CHEMSK(1) 4040 4050 4060 4070 4080 4090 40A0 CHEW0 CHEW1 CHEW2 CHEW3 CHELRU CHEHIT CHEMIS LTAG — — — — — — — LTAG CHEW0 CHEW1 CHEW2 CHEW3 — — — — — — — Preliminary DS61156C-page 91 PIC32MX5XX/6XX/7XX 0000 xxxx xxxx xxxx xxxx xxxx xxxx 40C0 CHEPFABT Legend: Note 1: 2: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information. Reset value is dependent on DEVCFGx configuration. TABLE 4-41: Virtual Address (BF80_#) Bit Range Register Name RTCC REGISTER MAP(1) Bits All Resets DS61156C-page 92 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 0200 RTCCON 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — ON — ALRMEN — FRZ — CHIME — SIDL — PIV — — — ALRMSYNC — — — — — — — — — — RTSECSEL RTCCLKON — — CAL — — — — RTCWREN RTCSYNC HALFSEC — — — RTCOE — 0000 0000 0000 0000 MIN01 — — — — — — — — — MONTH01 WDAY01 MIN01 — — — MONTH01 WDAY01 xxxx xx00 xxxx xx00 xxxx xx00 00xx xx0x 0210 RTCALRM 0220 RTCTIME AMASK HR01 SEC01 YEAR01 DAY01 HR01 SEC01 — — — — — MIN10 — — — — — — — — MONTH10 MIN10 MONTH10 ARPT HR10 SEC10 YEAR10 DAY10 HR10 SEC10 — — — — — DAY10 0230 RTCDATE 0240 ALRMTIME 0250 ALRMDATE Legend: — — DAY01 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Preliminary  2010 Microchip Technology Inc. TABLE 4-42: Virtual Address (BFC0_#) Bit Range Register Name DEVCFG: DEVICE CONFIGURATION WORD SUMMARY Bits All Resets xxxx xxxx — — — — — — FPLLMULT — FSOSCEN — — — — — ICESEL — — — — — FPLLODIV FPLLIDIV WDTPS FNOSC PWP DEBUG xxxx xxxx xxxx xxxx xxxx xxxx Virtual Address (BF80_#) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 All Resets Bit Range Register Name  2010 Microchip Technology Inc. 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 2FF0 DEVCFG3 2FF4 DEVCFG2 2FF8 DEVCFG1 2FFC DEVCFG0 Legend: 31:16 FVBUSIO FUSBIDIO 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — FUPLLEN — — — — — — FSCMIO — — — — — — — — CP — — — — — — — FCANIO — — OSCIOFNC — — FETHIO — FMIIEN — — BWP — — — — FWDTEN IESO — — — — — — FSRSSEL USERID FUPLLIDIV — — — POSCMOD FCKSM FPBDIV PWP x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-43: DEVICE AND REVISION ID SUMMARY(1) Bits Preliminary DS61156C-page 93 PIC32MX5XX/6XX/7XX F220 DEVID 31:16 15:0 VER DEVID DEVID xxxx xxxx Legend: Note 1: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Reset values are dependent on the device variant. Refer to the “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80480) for more information. DS61156C-page 94 PIC32MX5XX/6XX/7XX TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP Bits All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 — — — — EP — — — FRMH — — — — — — — — — — 0000 0000 0000 0000 0000 0000 0000 0000 Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 5040 5050 U1OTGIR U1OTGIE 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — IDIF — IDIE — ID — — UACTPND — STALLIF — STALLIE — BTSEF — BTSEE — — JSTATE — LSPDEN — — — — — — — — — — — — — — — — LSTATE — — — — — ACTVIF — ACTVIE — — — — — IDLEIF — IDLEIE — BTOEF — BTOEE — — USBRST — — BDTPTRL — — — — — — — SESVD — — — TRNIF — TRNIE — DFN8EF — DFN8EE — DIR — HOSTEN — DEVADDR — — — — SESEND — OTGEN — — — SOFIF — SOFIE — CRC16EF — CRC16EE — PPBI — RESUME — — — — — — — — VBUSCHG — — UERRIF — UERRIE — CRC5EF EOFEF — CRC5EE EOFEE — — — PPBRST — — — — VBUSVD — VBUSDIS — — URSTIF — URSTIE — PIDEF — PIDEE — — — USBEN SOFEN — T1MSECIF LSTATEIF T1MSECIE LSTATEIE SESVDIF SESENDIF SESVDIE SESENDIE VBUSVDIF 0000 VBUSVDIE 0000 5060 U1OTGSTAT 5070 U1OTGCON 5080 U1PWRC DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON USLPGRD USBBUSY USUSPEND USBPWR 5200 U1IR 15:0 31:16 ATTACHIF RESUMEIF — — DETACHIF 0000 Preliminary  2010 Microchip Technology Inc. 5210 U1IE 15:0 31:16 ATTACHIE RESUMEIE — BMXEF — BMXEE — — SE0 — — — — — — — DMAEF — DMAEE — — PKTDIS TOKBUSY — — — — — — PID DETACHIE 0000 5220 U1EIR 15:0 31:16 5230 U1EIE 15:0 31:16 15:0 31:16 5240 U1STAT ENDPT 5250 U1CON 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 5260 5270 5280 5290 52A0 Legend: U1ADDR U1BDTP1 U1FRML U1FRMH U1TOK FRML x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP (CONTINUED) Bits All Resets 0000 0000 — — — — — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — EPRXEN — — — — — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — EPTXEN — — — — — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — EPSTALL — — — — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK — EPHSHK 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 UASUSPND 0001  2010 Microchip Technology Inc. Bit Range 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 52B0 52C0 52D0 52E0 5300 5310 5320 5330 5340 5350 5360 5370 5380 5390 53A0 53B0 53C0 53D0 Legend: U1SOF U1BDTP2 U1BDTP3 U1CNFG1 U1EP0 U1EP1 U1EP2 U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — UTEYE — LSPD — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — UOEMON — RETRYDIS — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — USBFRZ — — — — — — — — — — — — — — — — — — — — — — — — — — — — — CNT — — — USBSIDL — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — EPCONDIS — — — — BDTPTRH BDTPTRU Preliminary DS61156C-page 95 PIC32MX5XX/6XX/7XX 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. TABLE 4-44: Virtual Address (BF88_#) Register Name USB REGISTER MAP (CONTINUED) Bits All Resets Bit Range DS61156C-page 96 PIC32MX5XX/6XX/7XX 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 53E0 53F0 Legend: U1EP14 U1EP15 31:16 15:0 31:16 15:0 — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — — EPCONDIS — EPCONDIS — EPRXEN — EPRXEN — EPTXEN — EPTXEN — EPSTALL — EPSTALL — EPHSHK — EPHSHK 0000 0000 0000 0000 x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal. Preliminary  2010 Microchip Technology Inc.  2010 Microchip Technology Inc. TABLE 4-45: CAN1 REGISTER SUMMARY FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX575F256L, PIC32MX575F512L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES(1) Bits All Resets 0400 0000 0000 0000 RBIE RBIF — RXWARN TBIE TBIF — 0000 0000 0000 0000 TXWARN EWARN 0000 0000 FIFOIP17 FIFOIP16 0000 FIFOIP1 RXOVF1 FIFOIP0 0000 RXOVF0 0000 FIFOIP2 RXOVF2 Virtual Address (BF88_#) Bit Range Register Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0 B000 B010 B020 B030 B040 C1CON C1CFG C1INT C1VEC C1TREC C1FSTAT C1RXOVF C1TMR C1RXM0 C1RXM1 C1RXM2 C1RXM3 31:16 15:0 31:16 31:16 15:0 31:16 15:0 31:16 15:0 — ON — IVRIE IVRIF — — — — — — SAM WAKIE WAKIF — — — FIFOIP30 FIFOIP14 — SIDLE — CERRIE CERRIF — — — — — — SEG1PH SERRIE SERRIF — — ABAT BUSY — RBOVIE RBOVIF — — TEC — — — — — REQOP — — PRSEG — — — — FIFOIP25 FIFOIP9 RXOVF9 — — — — FIFOIP24 FIFOIP8 RXOVF24 RXOVF8 — — — — — — — — — FIFOIP23 FIFOIP7 RXOVF7 OPMOD — WAKFIL — — — — — — — — — TXBO CANCAP — — — — TXBP — — BRP MODIE MODIF — ICOD RXBP — DNCNT — SEG2PH — 15:0 SEG2PHTS SJW CTMRIE CTMRIF — FILHIT — FIFOIP26 FIFOIP10 REC FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP6 RXOVF6 FIFOIP5 RXOVF5 FIFOIP4 RXOVF4 FIFOIP3 RXOVF3 B050 B060 B070 B080 B090 B0A0 B0B0 31:16 FIFOIP31 15:0 FIFOIP15 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP13 FIFOIP12 FIFOIP11 Preliminary DS61156C-page 97 31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 31:16 15:0 15:0 15:0 15:0 FLTEN3 FLTEN1 FLTEN7 FLTEN5 FLTEN9 FLTEN13 FLTEN17 MSEL3 MSEL1 MSEL7 MSEL5 MSEL11 MSEL9 MSEL15 MSEL13 MSEL19 MSEL17 FSEL3 FSEL1 FSEL7 FSEL5 FSEL11 FSEL9 FSEL15 FSEL13 FSEL19 FSEL17 SID SID SID SID RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000 CANTS CANTSPRE -— EID -— EID -— EID -— EID FLTEN2 FLTEN0 FLTEN6 FLTEN4 FLTEN10 FLTEN8 FLTEN14 FLTEN12 FLTEN18 FLTEN16 MSEL2 MSEL0 MSEL6 MSEL4 MSEL10 MSEL8 MSEL14 MSEL12 MSEL18 MSEL16 FSEL2 FSEL0 FSEL6 FSEL4 FSEL10 FSEL8 FSEL14 FSEL12 FSEL18 FSEL1674)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156C-page 216 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E1 E b N α NOTE 1 1 23 NOTE 2 A c β φ L A1 L1 A2 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E ƒ ƒ ƒ ± 0,1 0,//,0(7(56 120 %6& ± ± 5() ƒ %6& %6& %6& %6& ± ƒ ƒ ƒ ƒ ƒ 0$; 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & %  2010 Microchip Technology Inc. Preliminary DS61156C-page 217 PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 3) ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156C-page 218 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ D D1 e E E1 b N 1 23 NOTE 1 c NOTE 2 α A β φ L 8QLWV 'LPHQVLRQ /LPLWV 1XPEHU RI /HDGV /HDG 3LWFK 2YHUDOO +HLJKW 0ROGHG 3DFNDJH 7KLFNQHVV 6WDQGRII )RRW /HQJWK )RRWSULQW )RRW $QJOH 2YHUDOO :LGWK 2YHUDOO /HQJWK 0ROGHG 3DFNDJH :LGWK 0ROGHG 3DFNDJH /HQJWK /HDG 7KLFNQHVV /HDG :LGWK 0ROG 'UDIW $QJOH 7RS 0ROG 'UDIW $QJOH %RWWRP 1 H $ $ $ / / I ( ' ( ' F E D E ƒ ƒ ƒ ƒ ƒ ƒ ± ƒ 5() ƒ %6& %6& %6& %6& ƒ ± ± %6& ± 0,1 A1 L1 0,//,0(7(56 120 0$; A2 1RWHV 3LQ YLVXDO LQGH[ IHDWXUH PD\ YDU\ EXW PXVW EH ORFDWHG ZLWKLQ WKH KDWFKHG DUHD &KDPIHUV DW FRUQHUV DUH RSWLRQDO VL]H PD\ YDU\ 'LPHQVLRQV ' DQG ( GR QRW LQFOXGH PROG IODVK RU SURWUXVLRQV 0ROG IODVK RU SURWUXVLRQV VKDOO QRW H[FHHG 'LPHQVLRQLQJ DQG WROHUDQFLQJ SHU $60( < 0 %6& %DVLF 'LPHQVLRQ 7KHRUHWLFDOO\ H[DFW YDOXH VKRZQ ZLWKRXW WROHUDQFHV 5() 5HIHUHQFH 'LPHQVLRQ XVXDOO\ ZLWKRXW WROHUDQFH IRU LQIRUPDWLRQ SXUSRVHV RQO\ PP SHU VLGH 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ & %  2010 Microchip Technology Inc. Preliminary DS61156C-page 219 PIC32MX5XX/6XX/7XX /HDG 3ODVWLF 7KLQ 4XDG )ODWSDFN 37 ± 1RWH [ [ PP %RG\ PP >74)3@ )RU WKH PRVW FXUUHQW SDFNDJH GUDZLQJV SOHDVH VHH WKH 0LFURFKLS 3DFNDJLQJ 6SHFLILFDWLRQ ORFDWHG DW KWWS ZZZ PLFURFKLS FRP SDFNDJLQJ DS61156C-page 220 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. Preliminary DS61156C-page 221 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156C-page 222 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. Preliminary DS61156C-page 223 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156C-page 224 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2010 Microchip Technology Inc. Preliminary DS61156C-page 225 PIC32MX5XX/6XX/7XX Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS61156C-page 226 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX DEVICES A.3 Pin Assignments PIC32MX5XX/6XX/7XX devices have the same pin assignment for peripherals as PIC32MX4XX devices with the following exceptions: • Pins associated with the UART1 and UART2 modules on PIC32MX4XX devices are now associated with the UART1A and UART3A modules, respectively on PIC32MX5XX/6XX/7XX devices • Pins associated with the SPI2 module on PIC32MX4XX devices are now associated with the SPI2A module on PIC32MX5XX/6XX/7XX devices This appendix provides an overview of considerations for migrating from PIC32MX3XX/4XX devices to the PIC32MX5XX/6XX/7XX family of devices. The code developed for the PIC32MX3XX/4XX devices can be ported to the PIC32MX5XX/6XX/7XX devices after making the appropriate changes outlined below. A.1 DMA not support PIC32MX5XX/6XX/7XX devices do stopping DMA transfers in Idle mode. A.2 Interrupts PIC32MX5XX/6XX/7XX devices have persistent interrupts for some of the peripheral modules. This means that the interrupt condition for these peripherals must be cleared before the interrupt flag can be cleared. For example, to clear a UART receive interrupt, the user application must first read the UART Receive register to clear the interrupt condition and then clear the associated UxIF flag to clear the pending UART interrupt. In other words, the UxIF flag cannot be cleared by software until the UART Receive register is read. Table A-1 outlines the peripherals and associated interrupts that are implemented differently on PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX devices. In addition, on the SPI module, the IRQ numbers for the receive done interrupts were changed from 25 to 24 and the transfer done interrupts were changed from 24 to 25. TABLE A-1: Module PIC32MX3XX/4XX vs. PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION DIFFERENCES Interrupt Implementation Input Capture SPI To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of capture results in the buffer that are below the interrupt threshold (specified by ICI bits). Receive and transmit interrupts are controlled by the SRXISEL and STXISEL bits, respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF register to obtain the number of data to receive/transmit below the level specified by the SRXISEL and STXISEL bits. TX interrupt will be generated as soon as the UART module is enabled. Receive and transmit interrupts are controlled by the URXISEL and UTXISEL bits, respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or UxTXREG registers to obtain the number of data to receive/transmit below the level specified by the URXISEL and UTXISEL bits. All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source. To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT) register. UART ADC PMP  2010 Microchip Technology Inc. Preliminary DS61156C-page 227 PIC32MX5XX/6XX/7XX APPENDIX B: REVISION HISTORY Revision A (August 2009) This is the initial revision of this document. Revision B (November 2009) The revision includes the following global update: • Added Note 2 to the shaded table that appears at the beginning of each chapter. This new note provides information regarding the availability of registers and their associated bits Other major changes are referenced by their respective chapter/section in Table B-1. TABLE B-1: MAJOR SECTION UPDATES Update Description Section Name “High-Performance, USB, CAN and Added the following devices: Ethernet 32-Bit Flash - PIC32MX575F256L Microcontrollers” - PIC32MX695F512L - PIC32MX695F512H The 100-pin TQFP pin diagrams have been updated to reflect the current pin name locations (see the “Pin Diagrams” section). Added the 121-pin Ball Grid Array (XBGA) pin diagram. Updated Table 1: “PIC32MX Features” Added the following tables: - Table 2: “Pin Names: PIC32MX575F256L and PIC32MX575F512L Devices”, - Table 3: “Pin Names: PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L Devices” - Table 4: “Pin Names: PIC32MX775F256L, PIC32MX775F512L, PIC32MX795F512L and Devices” Updated the following pins as 5V tolerant: - 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2) - 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2) Section 2.0 “Guidelines for Getting Removed the last sentence of Section 2.3.1 “Internal Regulator Mode”. Started with 32-Bit Removed Section 2.3.2 “External Regulator Mode” Microcontrollers” DS61156C-page 228 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-1: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name Section 4.0 “Memory Organization” Updated all register tables to include the Virtual Address and All Resets columns. Updated the title of Figure 4-1 to include the PIC32MX575F256L device. Updated the title of Figure 4-3 to include the PIC32MX695F512L and PIC32MX695F512H devices. Also changed PIC32MX795F512L to PIC32MX795F512H. Updated the title of Table 4-3 to include the PIC32MX695F512H device. Updated the title of Table 4-5 to include the PIC32MX575F5256L device. Updated the title of Table 4-6 to include the PIC32MX695F512L device. Reversed the order of Table 4-11 and Table 4-12. Reversed the order of Table 4-14 and Table 4-15. Updated the title of Table 4-15 to include the PIC32MX575F256L and PIC32MX695F512L devices. Updated the title of Table 4-45 to include the PIC32MX575F256L device. Updated the title of Table 4-47 to include the PIC32MX695F512H and PIC32MX695F512L devices. Section 12.0 “I/O Ports” Section 22.0 “10-Bit Analog-toDigital Converter (ADC)” Section 28.0 “Special Features” Updated the second paragraph of Section 12.1.2 “Digital Inputs” and removed Table 12-1. Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2). Removed references to the ENVREG pin in Section 28.3 “On-Chip Voltage Regulator”. Updated the first sentence of Section 28.3.1 “On-Chip Regulator and POR” and Section 28.3.2 “On-Chip Regulator and BOR”. Updated the Connections for the On-Chip Regulator (see Figure 28-2). Section 31.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings and added Note 3. Added Thermal Packaging Characteristics for the 121-pin XBGA package (see Table 31-3). Updated the Operating Current (IDD) DC Characteristics (see Table 31-5). Updated the Idle Current (IIDLE) DC Characteristics (see Table 31-6). Updated the Power-Down Current (IPD) DC Characteristics (see Table 31-7). Removed Note 1 from the Program Flash Memory Wait State Characteristics (see Table 31-11). Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics, changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 31-13). Section 32.0 “Packaging Information” “Product Identification System” Added the 121-pin XBGA package marking information and package details. Added the definition for BG (121-lead 10x10x1.1 mm, XBGA). Added the definition for Speed.  2010 Microchip Technology Inc. Preliminary DS61156C-page 229 PIC32MX5XX/6XX/7XX Revision C (February 2010) The revision includes the following updates, as described in Table B-2: TABLE B-2: MAJOR SECTION UPDATES Update Description Section Name “High-Performance, USB, CAN and Ethernet 32-Bit Flash Microcontrollers” Added the following devices: • • • • • • • • • • PIC32MX675F256H PIC32MX775F256H PIC32MX775F512H PIC32MX675F256L PIC32MX775F256L PIC32MX775F512L EREFCLK ECRSDV AEREFCLK AECRSDV Added the following pins: Added the EREFCLK and ECRSDV pins to Table 3 and Table 4. Section 1.0 “Device Overview” Updated the pin number pinout I/O descriptions for the following pin names in Table 1-1: • SCL1A • SDA1A • SCL2 • SDA2 • SCL2A • SDA2A • SCL3A • SDA3A • TMS • TCK • TDI • TDO • RTCC • CVREF• CVREF+ • CVREFOUT • C1IN• C1IN+ • C1OUT • C2IN• C2IN+ • C2OUT • PMA0 • PMA1 Added the following pins to the Pinout I/O Descriptions table (Table 1-1): • • • • EREFCLK ECRSDV AEREFCLK AECRSDV DS61156C-page 230 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX TABLE B-2: MAJOR SECTION UPDATES (CONTINUED) Update Description Section Name Section 4.0 “Memory Organization” Added new devices and updated the virtual and physical memory map values in Figure 4-1. Added new devices to Figure 4-2. Added new devices to the following register maps: • • • • • • • • Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps) Table 4-12 (I2C2 Register Map) Table 4-15 (SPI1 Register Map) Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps) Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps) Table 4-45 (CAN1 Register Map) Table 4-46 (CAN2 Register Map) Table 4-47 (Ethernet Controller Register Map) Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device Configuration Word Summary). Section 28.0 “Special Features” Appendix A: “Migrating from PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX Devices” Changed all references of POSCMD to POSCMOD in the Device Configuration Word 1 register (see Register 28-2). Added the new section A.3 “Pin Assignments”.  2010 Microchip Technology Inc. Preliminary DS61156C-page 231 PIC32MX5XX/6XX/7XX NOTES: DS61156C-page 232 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX INDEX A AC Characteristics ............................................................ 180 10-Bit Conversion Rate Parameters ......................... 204 A/D Conversion Requirements ................................. 205 ADC Specifications ................................................... 202 EJTAG Timing Requirements ................................... 212 Ethernet .................................................................... 201 Internal FRC Accuracy.............................................. 182 Internal RC Accuracy ................................................ 182 OTG Electrical Specifications ................................... 211 Parallel Master Port Read Requirements ................. 209 Parallel Master Port Write ......................................... 210 Parallel Master Port Write Requirements.................. 210 Parallel Slave Port Requirements ............................. 208 PLL Clock Timing...................................................... 182 Assembler MPASM Assembler................................................... 168 D DC Characteristics............................................................ 172 I/O Pin Input Specifications ...................................... 176 I/O Pin Output Specifications.................................... 177 Idle Current (IIDLE) .................................................... 174 Operating Current (IDD) ............................................ 173 Power-Down Current (IPD)........................................ 175 Program Memory...................................................... 177 Temperature and Voltage Specifications.................. 172 Development Support ....................................................... 167 Direct Memory Access (DMA) Controller.......................... 117 E Electrical Characteristics .................................................. 171 AC............................................................................. 180 Errata .................................................................................. 21 Ethernet Controller............................................................ 145 External Clock Timer1 Timing Requirements ................................... 186 Timer2, 3, 4, 5 Timing Requirements ....................... 187 Timing Requirements ............................................... 181 B Block Diagrams A/D Module ............................................................... 141 Comparator I/O Operating Modes............................. 147 Comparator Voltage Reference ................................ 149 Connections for On-Chip Voltage Regulator............. 162 Core and Peripheral Modules ..................................... 23 DMA .......................................................................... 117 Ethernet Controller.................................................... 145 I2C Circuit ................................................................. 134 Input Capture ............................................................ 127 Interrupt Controller .................................................... 109 JTAG Programming, Debugging and Trace Ports ....................................................... 163 MCU............................................................................ 39 Output Compare Module........................................... 129 PIC32MX CAN Module ............................................. 143 PMP Pinout and Connections to External Devices ............................................................. 137 Prefetch Module........................................................ 115 Reset System............................................................ 107 RTCC ........................................................................ 139 SPI Module ............................................................... 131 Timer1....................................................................... 123 Timer2/3/4/5 (16-Bit) ................................................. 125 Typical Multiplexed Port Structure ............................ 121 UART ........................................................................ 135 WDT and Power-up Timer ........................................ 161 Brown-out Reset (BOR) and On-Chip Voltage Regulator................................ 162 F Flash Program Memory .................................................... 105 RTSP Operation ....................................................... 105 I I/O Ports ........................................................................... 121 Parallel I/O (PIO) ...................................................... 122 Instruction Set................................................................... 165 Inter-Integrated Circuit (I2C .............................................. 133 Internal Voltage Reference Specifications........................ 179 Interrupt Controller............................................................ 109 IRG, Vector and Bit Location .................................... 110 M MCU Architecture Overview ................................................ 40 Coprocessor 0 Registers ............................................ 42 Core Exception Types ................................................ 43 EJTAG Debug Support............................................... 44 Power Management ................................................... 44 MCU Module....................................................................... 39 Memory Maps ............................................................... 46–48 Memory Organization ......................................................... 45 Layout......................................................................... 45 Migration PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 227 MPLAB ASM30 Assembler, Linker, Librarian ................... 168 MPLAB Integrated Development Environment Software .............................................. 167 MPLAB PM3 Device Programmer .................................... 170 MPLAB REAL ICE In-Circuit Emulator System ................ 169 MPLINK Object Linker/MPLIB Object Librarian ................ 168 C C Compilers MPLAB C18 .............................................................. 168 Clock Diagram .................................................................. 113 Comparator Specifications............................................................ 178 Comparator Module .......................................................... 147 Comparator Voltage Reference (CVREF ........................... 149 Configuration Bit ............................................................... 153 Controller Area Network (CAN)......................................... 143 CPU Module........................................................................ 35 O Open-Drain Configuration................................................. 122 Oscillator Configuration .................................................... 113 Output Compare ............................................................... 129  2010 Microchip Technology Inc. Preliminary DS61156C-page 233 PIC32MX5XX/6XX/7XX P Packaging ......................................................................... 213 Details ....................................................................... 215 Marking ..................................................................... 213 Parallel Master Port (PMP) ............................................... 137 PIC32MX Family USB Interface Diagram ......................... 120 Pinout I/O Descriptions (table) ............................................ 24 Power-on Reset (POR) and On-Chip Voltage Regulator ................................ 162 Power-Saving Features..................................................... 151 CPU Halted Methods ................................................ 151 Operation .................................................................. 151 with CPU Running..................................................... 151 Prefetch Cache ................................................................. 115 Program Flash Memory Wait State Characteristics......................................... 178 Timing Requirements CLKO and I/O ........................................................... 183 Timing Specifications CAN I/O Requirements ............................................. 200 I2Cx Bus Data Requirements (Master Mode)........... 195 I2Cx Bus Data Requirements (Slave Mode)............. 198 Input Capture Requirements..................................... 187 Output Compare Requirements................................ 188 Simple OCx/PWM Mode Requirements ................... 188 SPIx Master Mode (CKE = 0) Requirements............ 189 SPIx Master Mode (CKE = 1) Requirements............ 190 SPIx Slave Mode (CKE = 1) Requirements.............. 192 SPIx Slave Mode Requirements (CKE = 0).............. 191 U UART ................................................................................ 135 USB On-The-Go (OTG) .................................................... 119 R Real-Time Clock and Calendar (RTCC)............................ 139 Register Maps ............................................................. 49–103 Registers DDPCON (Debug Data Port Control)........................ 164 DEVCFG0 (Device Configuration Word 0 ................. 153 DEVCFG1 (Device Configuration Word 1 ................. 155 DEVCFG2 (Device Configuration Word 2 ................. 157 DEVCFG3 (Device Configuration Word 3 ................. 159 DEVID (Device and Revision ID) .............................. 160 Resets ............................................................................... 107 Revision History ................................................................ 228 V VCAP/VDDCORE pin............................................................ 162 Voltage Reference Specifications..................................... 179 Voltage Regulator (On-Chip) ............................................ 162 W Watchdog Timer (WDT).................................................... 161 WWW, On-Line Support ..................................................... 21 S Serial Peripheral Interface (SPI) ....................................... 131 Software Simulator (MPLAB SIM)..................................... 169 Special Features ............................................................... 153 T Timer1 Module .................................................................. 123 Timer2/3, Timer4/5 Modules ............................................. 125 Timing Diagrams 10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 206 10-Bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 1, SSRC = 111, SAMC = 00001)........ 207 CAN I/O..................................................................... 200 EJTAG ...................................................................... 212 External Clock ........................................................... 180 I/O Characteristics .................................................... 183 I2Cx Bus Data (Master Mode) .................................. 194 I2Cx Bus Data (Slave Mode) .................................... 197 I2Cx Bus Start/Stop Bits (Master Mode) ................... 194 I2Cx Bus Start/Stop Bits (Slave Mode) ..................... 197 Input Capture (CAPx)................................................ 187 OCx/PWM ................................................................. 188 Output Compare (OCx) ............................................. 188 Parallel Master Port Read ......................................... 209 Parallel Master Port Write ......................................... 210 Parallel Slave Port .................................................... 208 SPIx Master Mode (CKE = 0).................................... 189 SPIx Master Mode (CKE = 1).................................... 190 SPIx Slave Mode (CKE = 0)...................................... 191 SPIx Slave Mode (CKE = 1)...................................... 192 Timer1, 2, 3, 4, 5 External Clock............................... 186 UART Reception ....................................................... 136 UART Transmission (8-Bit or 9-Bit Data) .................. 136 DS61156C-page 234 Preliminary  2010 Microchip Technology Inc. PIC32MX5XX/6XX/7XX Product Identification System To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Microchip Brand Architecture Product Groups Flash Memory Family Program Memory Size (KB) Pin Count Tape and Reel Flag (if applicable) Speed Temperature Range Package Pattern Example: PIC32MX575F256H-80I/PT: General purpose PIC32MX, 256 KB program memory, 64-pin, Industrial temperature, TQFP package. Flash Memory Family Architecture Product Groups MX = 32-bit RISC MCU core 5XX = General purpose microcontroller family 6XX = General purpose microcontroller family 7XX = General purpose microcontroller family F = Flash program memory Flash Memory Family Program Memory Size 256 = 256K 512 = 512K Pin Count H L 80 I PT PT PF MR BG = 64-pin = 100-pin = 80 MHz = -40°C to +85°C (Industrial) = = = = = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack) 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack) 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat) 121-Lead (10x10x1.1 mm) XBGA (Plastic Thin Profile Ball Grid Array) Speed Temperature Range Package Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample  2010 Microchip Technology Inc. Preliminary DS61156C-page 235 WORLDWIDE SALES AND SERVICE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Cleveland Independence, OH Tel: 216-447-0464 Fax: 216-447-0643 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Chongqing Tel: 86-23-8980-9588 Fax: 86-23-8980-9500 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 ASIA/PACIFIC India - Bangalore Tel: 91-80-3090-4444 Fax: 91-80-3090-4123 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 Taiwan - Hsin Chu Tel: 886-3-6578-300 Fax: 886-3-6578-370 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 EUROPE Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 01/05/10 DS61156C-page 236 Preliminary  2010 Microchip Technology Inc.