RFHCS362F

rfHCS362G/362F KEELOQ® Code Hopping Encoder with UHF ASK/FSK Transmitter General • Combination encoder and synthesized UHF ASK/FSK transmitter in a single package • Operates on a single lithium coin cell - VLOW LED LED OPERATION (LED = 1) TLEDON TLEDOFF TLEDOFF = 500 ms A logic 0 on the SHIFT input pin will select the second encryption key. FIGURE 3-9: USING DUAL ENCODER OPERATION VDD The same configuration option determines whether when the VDD Voltage drops below the selected VLOW trip point the LED will blink only once or stop blinking. FIGURE 3-8: S[3210] VDD > VLOW LED LED OPERATION (LED = 0) VDD TLEDON TLEDOFF LED/SHIFT DATA TLEDON = 200 ms VDD < VLOW TLEDOFF = 800 ms VSS 1 kΩ SHIFT LED Note: When the rfHCS362 encoder is used as a Dual Encoder the LED pin is used as a SHIFT input (Figure 3-9). In such a configuration the LED is always ON during transmission. To keep power consumption low, it is recommended to use a series resistor of relatively high value. VLOW information is not available when using the second Encryption Key. © 2011 Microchip Technology Inc. DS41189B-page 17 rfHCS362G/362F FIGURE 3-10: SEED CODE WORD FORMAT With QUEN = 1 Fixed Portion (9 bits) QUE CRC VLOW (2 bits) (2 bits) (1-bit) Q1 Q0 C1 C0 1 BUT (4 bits) 1 1 1 Transmission Direction LSB First SEED Code (60 bits) SEED 3.4 Seed Code Word Data Format TABLE 3-1: SEED OPTIONS (SEEDC = 0) Seed 1.6 s Delayed Seed S[3210] A seed transmission transmits a unencrypted code word that consists of 60 bits of fixed data that is stored in the EEPROM. This can be used for secure learning of encoders or whenever a fixed code transmission is required. The seed code word further contains the function code and the status information (VLOW, CRC and QUEUE) as configured for normal code hopping code words. The seed code word format is shown in Figure 3-10. The function code for seed code words is always ‘1111b’. Seed code words can be configured as follows: • Enabled permanently. • Disabled permanently. • Enabled until the synchronization counter is greater than 7Fh, this configuration is often referred to as Limited Seed. • The time before the seed code word is transmitted can be set to 1.6 s or 3.2 s, this configuration is often referred to as Delayed Seed. When this option is selected, the rfHCS362 will transmit a code hopping code word for 1.6 s or 3.2 s, before the seed code word is transmitted. SEED S[3210] 00 01 10 11 Note: 0101* 0101 0101 *Limited Seed 0001* 0001 - TABLE 3-2: SEED OPTIONS (SEEDC = 1) Seed 3.2 s Delayed Seed S[3210] SEED S[3210] 00 01 10 11 Note: 1001* 1001 1001 *Limited Seed 0011* 0011 - 3.4.1 SEED OPTIONS The button combination (S[3210]) for transmitting a Seed code word can be selected with the Seed and SeedC (SEED[0..1] and SEEDC) configuration options as shown in Table 3-1 and Table 3-2: Example A): Selecting SEEDC = 1 and SEED = 11: makes SEED transmission available every time the combination of buttons S3 and S0 is pressed simultaneously, but Delayed Seed mode is not available. Example B): Selecting SEEDC = 0 and SEED = 01: makes SEED transmission available only for a limited time (only up to 128 times). The combination of buttons S2 and S0 produces an immediate transmission of the SEED code. Pressing and holding for more than 1.6 seconds the S0 button alone produces the SEED code word transmission (Delayed Seed). DS41189B-page 18 © 2011 Microchip Technology Inc. rfHCS362G/362F 3.5 RF Enable and Transmitter Interface transmitter crystal oscillator and PLL time to startup (TPLL). The RFENOUT signal will go LOW one guard time after the end of the last code word. When the RF Enable output is selected, the S3 pin can still be used as a button input. However, only minimum code words will be transmitted. An alternative solution for more than three push buttons can be the switching diode circuit described in Section 1.2. In typical implementations of the rfHCS362G/362F, the encoder RFENOUT pin is connected to the transmitter RFENIN pin. The S3/RFENOUT pin of the rfHCS362 can be configured to function as an RF Enable output signal. This is selected by the RF Enable Output (RFEN) configuration option as described in Section 4.5.13. When enabled, this pin will be driven HIGH before data is transmitted through the DATA pin. The RFENOUT and DATA pins are synchronized to interface with the transmitter. Figure 3-11 shows the start-up sequence. A button is debounced and the EEPROM counter advanced during the power-up delay (TPU). Then the RFENOUT pin goes high to enable the transmitter. The DATA output is delayed to give the FIGURE 3-11: PLL INTERFACE Button Press S[3210] RFENOUT Button Release DATA TPU TPLL 1st CODE WORD 2nd CODE WORD Guard Time TG © 2011 Microchip Technology Inc. DS41189B-page 19 rfHCS362G/362F 4.0 EEPROM MEMORY ORGANIZATION 4.1 KEY_0 - KEY_3 (64-bit Encryption Key) The rfHCS362G/362F contains 288 bits (18 x 16-bit words) of EEPROM memory (Table 4-1). This EEPROM array is used to store the encryption key information and synchronization value. Further descriptions of the memory array is given in the following sections. TABLE 4-1: Word Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 EEPROM MEMORY MAP Field Description 64-bit Encryption Key1 (Word 0) LSB 64-bit Encryption Key1 (Word 1) 64-bit Encryption Key1 (Word 2) 64-bit Encryption Key1 (Word 3) MSB 64-bit Encryption Key2 (Word 0) LSB 64-bit Encryption Key2 (Word 1) 64-bit Encryption Key2 (Word 2) 64-bit Encryption Key2 (Word 3) MSB Seed value (Word 0) LSB Seed value (Word 1) Seed value (Word 2) Seed value (Word 3) MSB Configuration Word (Word 0) Configuration Word (Word 1) Serial Number (Word 0) LSB Serial Number (Word 1) MSB Synchronization counter Reserved – Set to zero The 64-bit encryption key is used to create the encrypted message. This key is calculated and programmed during production using a key generation algorithm. The key generation algorithm may be different from the KEELOQ algorithm. Inputs to the key generation algorithm are typically the transmitter’s serial number and the 64-bit manufacturer’s code. While the key generation algorithm supplied from Microchip is the typical method used, a user may elect to create their own method of key generation. 4.2 SYNC (Synchronization Counter) KEY1_0 KEY1_1 KEY1_2 KEY1_3 KEY2_0 KEY2_1 KEY2_2 KEY2_3 SEED_0 SEED_1 SEED_2 SEED_3 CONFIG_0 CONFIG_1 SERIAL_0 SERIAL_1 SYNC RES This is the 16-bit synchronization value that is used to create the hopping code for transmission. This value will be incremented after every transmission. 4.3 SEED_0, SEED_1, SEED_2, and SEED 3 (Seed Word) This is the four word (60 bits) seed code that will be transmitted when seed transmission is selected. This allows the system designer to implement the secure learn feature or use this fixed code word as part of a different key generation/tracking process or purely as a fixed code transmission. Note: Upper four Significant bits of SEED_3 contains extra configuration information (see Table 4-5). 4.4 SERIAL_0, SERIAL_1 (Encoder Serial Number) SERIAL_0 and SERIAL_1 are the lower and upper words of the device serial number, respectively. There are 32 bits allocated for the serial number and a selectable configuration bit determines whether 32 or 28 bits will be transmitted. The serial number is meant to be unique for every transmitter. DS41189B-page 20 © 2011 Microchip Technology Inc. rfHCS362G/362F TABLE 4-2: Bit Address 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 CONFIG_0 Field Description Oscillator adjust Values OSC_0 OSC_1 OSC_2 OSC_3 VLOW_0 VLOW_1 VLOW_2 BSEL_0 BSEL_1 MTX_0 MTX_1 GUARD_0 GUARD_1 TIMOUT_0 TIMOUT_1 CTSEL 0000 - nominal 1000 - fastest 0111 - slowest VLOW select nominal values Bit rate select Minimum number of code words Guard time select Time-out select CTSEL 000 - 2.0V 100 - 4.0V 001 - 2.1V 101 - 4.2V 010 - 2.2V 110 - 4.4V 011 - 2.3V 111 - 4.6V 00 - TE = 100 μs 01 - TE = 200 μs 10 - TE = 400 μs 11 - TE = 800 μs 00 - 1 01 - 2 10 - 4 11 - 8 00 - 0 ms (1 TE) 01 - 6.4 ms + 2 TE 10 - 25.6 ms + 2 TE 11 - 76.8 ms + 2 TE 00 - No Time-out 01 - 0.8 s to 0.8 s + 1 code word 10 - 3.2 s to 3.2 s + 1 code word 11 - 25.6 s to 25.6 s + 1 code word 0 = TIME bits 1 = CRC bits BSEL[0..1] 4.5 Configuration Words 4.5.3 There are 36 configuration bits stored in the EEPROM array. They are used by the device to determine transmission speed, format, delays and Guard times. They are grouped in three Configuration Words: CONFIG_0, CONFIG_1 and the upper nybble of the SEED_3 word. A description of each of the bits follows this section. 4.5.1 OSC The basic timing element TE, determines the actual transmission Baud Rate. This translates to different code word lengths depending on the encoding format selected (Manchester or PWM), the Header length selection and the Guard time selection, from approximately 40 ms up to 220 ms. Refer to Table 4-2 for bit rate configuration. Refer to Figure 10-3 through Figure 10-6 for code word timing. The internal oscillator can be tuned to ±10%. (0000 selects the nominal value, 1000 the fastest value and 0111 the slowest). When programming the device, it is the programmer’s responsibility to determine the optimal calibration value. 4.5.4 MTX[0..1] MTX selects the minimum number of code words that will be transmitted. A minimum of 1, 2, 4 or 8 code words will be transmitted. Note: If MTX and BSEL settings in combination require a transmission sequence to exceed the TIMOUT setting, TIMOUT will take priority. 4.5.2 VLOW[0..2] The low voltage threshold can be programmed to be any of the values shown in Table 4-2. © 2011 Microchip Technology Inc. DS41189B-page 21 rfHCS362G/362F TABLE 4-3: Bit Address 0 1 2 ... 8 9 10 11 12 13 CONFIG_1 Field Description Discrimination bits Values DISC_0 DISC_1 DISC_2 ... DISC_8 DISC_9 OVR_0 OVR_1 XSER SEEDC DISC[9:0] Overflow Extended Serial Number Seed Control OVR[1:0] 0 - Disable 1 - Enable 0 = Seed transmission on: S[3210] = 0001 (delay 1.6 s) S[3210] = 0101 (immediate) 1 = Seed transmission on: S[3210] = 0011 (delay 3.2 s) S[3210] = 1001 (immediate) 14 15 SEED_0 SEED_1 Seed options 00 01 10 11 - No Seed Limited Seed (Permanent and Delayed) Permanent and Delayed Seed Permanent Seed only 4.5.5 GUARD The Guard time between code words can be set to 0 ms, 6.4 ms, 25.6 ms and 76.8 ms. If during a series of code words, the output changes from Hopping Code to Seed the Guard time will increase by 3 x TE. logical “1” the two overflow bits OVL0 and OVL1. The overflow bits form part of the encrypted transmission, and therefore can be examined by receiver firmware. Table 4-4 shows how the overflow bits act when they are set to one during initial device configuration. 4.5.6 TIMOUT[0..1] TABLE 4-4: Sync. Counter No overflow 0-FFFFH First overflow 2nd 0-FFFFH Second overflow Third 0-FFFFH Subsequent overflows OVL0 1 0 0 0 OVL1 1 1 0 0 The transmission time-out can be set to 0.8 s, 3.2 s, 25.6 s or no time-out. After the time-out period, the encoder will stop transmission and enter a low power Shutdown mode. 4.5.7 DISC[0..9] The discrimination bits are used to validate the decrypted code word. The discrimination value is typically programmed with the 10 Least Significant bits of the serial number or a fixed value. 4.5.8 OVR[0..1] The automatically incrementing synchronization counter is at the core of generating the varying code. Since the counter is limited to 16 bits, it overflows after 65536 increments, after which the code hopping sequence repeats. In practice, this allows 20+ operations per day for ten years before repeating the sequence. In addition, two overflow bits allow the sequence to be extended further. The feature is enabled by setting to As can be seen from the table, the counter is effectively extended by one bit, that is OVL0. In addition, OVL1 provides indication of the second counter overflow. After the second overflow, OVL0 and OVL1 remain zero, providing permanent evidence of the first and second overflow events. DS41189B-page 22 © 2011 Microchip Technology Inc. rfHCS362G/362F 4.5.9 XSER If XSER is enabled a 32-bit serial number is transmitted. If XSER is disabled a 28-bit serial number and a 4-bit function code are transmitted. In limited Seed mode, the device will output the seed if the sync counter (Section 4.2) is from 00hex to 7Fhex. For a counter higher than 7F, a normal hopping code will be output. Note: Whenever a SEED code word is output, the 4 function bits (Figure 3-10) will be set to all ones [1,1,1,1]. 4.5.10 SEED[0..1] The seed value which is transmitted on key combinations (0011) and (1001) can be disabled, enabled or enabled for a limited number of transmissions determined by the initial counter value. 4.5.11 SEEDC SEEDC selects between seed transmission on 0001 and 0101 (SEEDC = 0) and 0011 and 1001 (SEEDC = 1). The delay before seed transmission is 1.6 s for (SEEDC = 0) and 3.2 s for (SEEDC = 1). TABLE 4-5: Bit Address 0 1 2 ... 9 10 11 12 SEED_3 Field Description Seed Most Significant word — Values SEED_48 SEED_49 SEED_50 ... SEED_57 SEED_58 SEED_59 LED LED output timing 0 = VBOT>VLOW LED blink 200/800 ms VBOTVLOW LED blink 25/500 ms VBOT