TC1303B-DF0EMFTR

TC1303B 500 mA Synchronous Buck Regulator, + 300 mA LDO with Power-Good Output Features • Dual-Output Regulator (500 mA Buck Regulator and 300 mA Low-Dropout Regulator) • Power-Good Output with 300 ms Delay • Total Device Quiescent Current = 65 µA, Typ. • Independent Shutdown for Buck and LDO Outputs • Both Outputs Internally Compensated • Synchronous Buck Regulator: - Over 90% Typical Efficiency - 2.0 MHz Fixed Frequency PWM (Heavy Load) - Low Output Noise - Automatic PWM to PFM mode transition - Adjustable (0.8V to 4.5V) and Standard Fixed Output Voltages (0.8V, 1.2V, 1.5V, 1.8V, 2.5V, 3.3V) • Low-Dropout Regulator: - Low-Dropout Voltage = 137 mV Typ. @ 200 mA - Standard Fixed Output Voltages (1.5V, 1.8V, 2.5V, 3.3V) • Power-Good Function: - Monitors LDO Output Function (TC1303B) - 300 ms Delay Used for Processor Reset • Small 10-pin 3X3 DFN or MSOP Package Options • Operating Junction Temperature Range: - -40°C to +125°C • Undervoltage Lockout (UVLO) • Output Short Circuit Protection • Overtemperature Protection Description The TC1303B combines a 500 mA synchronous buck regulator and 300 mA Low-Dropout Regulator (LDO) with a power-good monitor to provide a highly integrated solution for devices that require multiple supply voltages. The unique combination of an integrated buck switching regulator and low-dropout linear regulator provides the lowest system cost for dual-output voltage applications that require one lower processor core voltage and one higher bias voltage. The 500 mA synchronous buck regulator switches at a fixed frequency of 2.0 MHz when the load is heavy providing a low noise, small-size solution. When the load on the buck output is reduced to light levels, it changes operation to a Pulse Frequency Modulation (PFM) mode to minimize quiescent current draw from the battery. No intervention is necessary for smooth transition from one mode to another. The LDO provides a 300 mA auxiliary output that requires a single 1 µF ceramic output capacitor, minimizing board area and cost. The typical dropout voltage for the LDO output is 137 mV for a 200 mA load. For the TC1303B, the power-good output logic level is based on the regulation of the LDO output only. The buck regulator can be turned on and off without affecting the power-good signal. The TC1303B is available in either the 10-pin DFN or MSOP package. Additional protection features include: UVLO, overtemperature and overcurrent protection on both outputs. For a complete listing of TC1303B standard parts, consult your Microchip representative. Applications • • • • • Cellular Phones Portable Computers USB Powered Devices Handheld Medical Instruments Organizers and PDAs Package Type 10-Lead DFN SHDN2 1 VIN2 2 VOUT2 3 PG 4 AGND 5 10 PGND 9 LX 8 VIN1 7 SHDN1 6 VFB1/VOUT1 10-Lead MSOP SHDN2 1 VIN2 2 VOUT2 3 PG 4 AGND 5 10 PGND 9 LX 8 VIN1 7 SHDN1 6 VFB1/VOUT1 © 2005 Microchip Technology Inc. DS21949A-page 1 TC1303B Functional Block Diagram VREF Undervoltage Lockout (UVLO) UVLO Synchronous BUCK Regulator VIN1 VIN2 PDRV LX SHDN1 Control Driver NDRV PGND PGND VOUT1/VFB1 PGND AGND PG TC1303B PG Generator with Delay VREF UVLO VOUT2 LDO SHDN2 AGND DS21949A-page 2 © 2005 Microchip Technology Inc. TC1303B Typical Application Circuits TC1303B Fixed Output Application 10-Lead MSOP 4.7µH VIN 2.7V to 4.2V 4.7 µF 8 2 7 1 4 Processor RESET VIN1 VIN2 SHDN1 SHDN2 PG LX 9 4.7 µF PGND 10 VOUT1 VOUT2 AGND 6 3 5 1 µF VOUT2 2.5V @ 300 mA VOUT1 1.5V @ 500 mA TC1303B Adjustable Output Application 10-Lead DFN Input Voltage 4.5V to 5.5V *Optional Capacitor VIN2 1.0 µF 4.7 µH 8 4.7 µF 2 7 1 4 Processor RESET VIN1 VIN2 SHDN1 SHDN2 PG LX 9 4.7 µF 200 kΩ VOUT2 1 µF 3.3V @ 300 mA 4.99 kΩ 33 pF 121 kΩ PGND 10 VOUT1 6 VOUT2 AGND 3 5 Note VOUT1 2.1V @ 500 mA Note: Connect DFN package exposed pad to AGND. © 2005 Microchip Technology Inc. DS21949A-page 3 TC1303B 1.0 ELECTRICAL CHARACTERISTICS † Notice: Stresses above those listed under “Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings † VIN - AGND ......................................................................6.0V All Other I/O .............................. (AGND - 0.3V) to (VIN + 0.3V) LX to PGND .............................................. -0.3V to (VIN + 0.3V) PGND to AGND................................................... -0.3V to +0.3V Output Short Circuit Current ................................. Continuous Power Dissipation (Note 7) ..........................Internally Limited Storage temperature .....................................-65°C to +150°C Ambient Temp. with Power Applied.................-40°C to +85°C Operating Junction Temperature...................-40°C to +125°C ESD protection on all pins (HBM) ....................................... 3 kV DC CHARACTERISTICS Electrical Characteristics: VIN1 =VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, IOUT1 = 100 ma, IOUT2 = 0.1 mA TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. Parameters Input/Output Characteristics Input Voltage Maximum Output Current Maximum Output Current Shutdown Current Combined VIN1 and VIN2 Current TC1303B Operating IQ Synchronous Buck IQ LDO IQ + Voltage Monitor IQ SHDN1,SHDN2, Logic Input Voltage Low SHDN1,SHDN2, Logic Input Voltage High SHDN1,SHDN2, Input Leakage Current Thermal Shutdown Thermal Shutdown Hysteresis Undervoltage Lockout (VOUT1 and VOUT2) Undervoltage Lockout Hysteresis Note 1: 2: 3: 4: 5: 6: VIL VIH IIN VIN IOUT1_MAX IOUT2_MAX IIN_SHDN IQ 2.7 500 300 — — — — — 45 -1.0 — — — 0.05 65.0 38 46 — — ±0.01 5.5 — — 1 110 — — 15 — 1.0 V mA mA µA µA µA µA %VIN %VIN µA Note 1, Note 2, Note 8 Note 1 Note 1 SHDN1 = SHDN2 = GND SHDN1 = SHDN2 = VIN2 IOUT1 = 0 mA, IOUT2 = 0 mA SHDN1 = VIN, SHDN2 = GND SHDN1 = GND, SHDN2 = VIN2 VIN1 =VIN2 = 2.7V to 5.5V VIN1 =VIN2 = 2.7V to 5.5V VIN1 =VIN2 = 2.7V to 5.5V SHDNX = GND SHDNY = VIN Note 6, Note 7 VIN1 Falling Sym Min Typ Max Units Conditions Shutdown/UVLO/Thermal Shutdown Characteristics TSHD TSHD-HYS UVLO UVLO-HYS — — 2.4 — 165 10 2.55 200 — — 2.7 — °C °C V mV 7: 8: The Minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VRX + VDROPOUT, VRX = VR1 or VR2. VRX is the regulator output voltage setting. TCVOUT2 = ((VOUT2max – VOUT2min) * 106)/(VOUT2 * DT). Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. The integrated MOSFET switches have an integral diode from the LX pin to VIN, and from LX to PGND. In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is not able to limit the junction temperature for these cases. VIN1 and VIN2 are supplied by the same input source. DS21949A-page 4 © 2005 Microchip Technology Inc. TC1303B DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: VIN1 =VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, IOUT1 = 100 ma, IOUT2 = 0.1 mA TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. Parameters Sym Min Typ Max Units Conditions Synchronous Buck Regulator (VOUT1) Adjustable Output Voltage Range Adjustable Reference Feedback Voltage (VFB1) Feedback Input Bias Current (IFB1) Output Voltage Tolerance Fixed (VOUT1) Line Regulation (VOUT1) Load Regulation (VOUT1) Dropout Voltage VOUT1 Internal Oscillator Frequency Start Up Time RDSon P-CHANNEL RDSon N-CHANNEL LX Pin Leakage Current Positive Current Limit Threshold LDO Output (VOUT2) Output Voltage Tolerance (VOUT2) Temperature Coefficient Line Regulation Load Regulation, VOUT2 ≥ 2.5V Load Regulation, VOUT2 < 2.5V Dropout Voltage VOUT2 > 2.5V Power Supply Rejection Ratio Output Noise Output Short Circuit Current (Average) Note 1: 2: 3: 4: 5: 6: VOUT2 TCVOUT ΔVOUT2/ ΔVIN ΔVOUT2/ IOUT2 ΔVOUT2/ IOUT2 VIN – VOUT2 PSRR eN IOUTsc2 -2.5 — -0.2 -0.75 -0.90 — — — — ±0.3 25 ±0.02 0.1 0.1 137 205 62 1.8 240 +2.5 — +0.2 +0.75 +0.90 300 500 — — — % ppm/°C %/V % % mV dB µV/(Hz)½ mA Note 2 Note 3 (VR+1V) ≤ VIN ≤ 5.5V IOUT2 = 0.1 mA to 300 mA (Note 4) IOUT2 = 0.1 mA to 300 mA (Note 4) IOUT2 = 200 mA (Note 5) IOUT2 = 300 mA f ≤ 100 Hz, IOUT1 = IOUT2 = 50 mA, CIN = 0 µF f ≤ 1 kHz, IOUT2 = 50 mA, SHDN1 = GND RLOAD2 ≤ 1Ω VOUT1 VFB1 IVFB1 VOUT1 VLINE-REG VLOAD-REG VIN – VOUT1 FOSC TSS RDSon-P RDSon-N ILX +ILX(MAX) 0.8 0.78 — -2.5 — — — 1.6 — — — -1.0 — — 0.8 -1.5 ±0.3 0.2 0.2 280 2.0 0.5 450 450 ±0.01 700 4.5 0.82 — +2.5 — — — 2.4 — 650 650 1.0 — V V nA % %/V % mV MHz ms mΩ mΩ μA mA TR = 10% to 90% IP=100 mA IN=100 mA SHDN = 0V, VIN = 5.5V, LX = 0V, LX = 5.5V Note 2 VIN =VR+1V to 5.5V, ILOAD = 100 mA VIN = VR + 1.5V, ILOAD = 100 mA to 500 mA (Note 1) IOUT1 = 500 mA, VOUT1 = 3.3V (Note 5) 7: 8: The Minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VRX + VDROPOUT, VRX = VR1 or VR2. VRX is the regulator output voltage setting. TCVOUT2 = ((VOUT2max – VOUT2min) * 106)/(VOUT2 * DT). Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. The integrated MOSFET switches have an integral diode from the LX pin to VIN, and from LX to PGND. In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is not able to limit the junction temperature for these cases. VIN1 and VIN2 are supplied by the same input source. © 2005 Microchip Technology Inc. DS21949A-page 5 TC1303B DC CHARACTERISTICS (CONTINUED) Electrical Characteristics: VIN1 =VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, IOUT1 = 100 ma, IOUT2 = 0.1 mA TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. Parameters Wake-Up Time (From SHDN2 mode), (VOUT2) Settling Time (From SHDN2 mode), (VOUT2) Power-Good Voltage Range PG VPG 1.0 1.2 — 89 — — — 140 — 5.5 5.5 96 — — — — 560 V TA = 0°C to +70°C TA = -40°C to +85°C VIN ≤ 2.7 ISINK = 100 µA On Rising VOUT1 or VOUT2 VOUTX = VOUT1 or VOUT2 On Falling VOUT1 or VOUT2 VOUTX = VOUT1 or VOUT2 VOUTX = VOUT1 or VOUT2 Sym tWK tS Min — — Typ 31 100 Max 100 — Units µs µs Conditions IOUT1 = IOUT2 = 50 mA IOUT1 = IOUT2 = 50 mA PG Threshold High (VOUT1 or VOUT2) PG Threshold Low (VOUT1 or VOUT2) PG Threshold Hysteresis (VOUT1 and VOUT2) PG Threshold Tempco PG Delay PG Active Time-out Period VTH_H VTH_L VTH_HYS ΔVTH/ΔT tRPD tRPU 94 92 2 30 165 262 % of VOUTX % of VOUTX % of VOUTX ppm/°C µs ms VOUT1 or VOUT2 = (VTH + 100 mV) to (VTH - 100 mV) VOUT1 or VOUT2 = VTH - 100 mV to VTH + 100 mV, ISINK = 1.2 mA VOUT1 or VOUT2 = VTH - 100 mV, IPG= 1.2 mA VIN2 > 2.7V IPG = 100 µA, 1.0V < VIN2 < 2.7V VOUT1 or VOUT2 = VTH + 100 mV VOUT2 ≥ 1.8V, IPG = - 500 µA VOUT2 < 1.8V,IPG = - 300 µA PG Output Voltage Low PG_VOL — — 0.2 V PG Output Voltage High PG_VOH 0.9* VOUT2 — — V Note 1: 2: 3: 4: 5: 6: 7: 8: The Minimum VIN has to meet two conditions: VIN ≥ 2.7V and VIN ≥ VRX + VDROPOUT, VRX = VR1 or VR2. VRX is the regulator output voltage setting. TCVOUT2 = ((VOUT2max – VOUT2min) * 106)/(VOUT2 * DT). Regulation is measured at a constant junction temperature using low duty cycle pulse testing. Load regulation is tested over a load range from 0.1 mA to the maximum specified output current. Dropout voltage is defined as the input to output voltage differential at which the output voltage drops 2% below its nominal value measured at a 1V differential. The maximum allowable power dissipation is a function of ambient temperature, the maximum allowable junction temperature and the thermal resistance from junction to air. (i.e. TA, TJ, θJA). Exceeding the maximum allowable power dissipation causes the device to initiate thermal shutdown. The integrated MOSFET switches have an integral diode from the LX pin to VIN, and from LX to PGND. In cases where these diodes are forward-biased, the package power dissipation limits must be adhered to. Thermal protection is not able to limit the junction temperature for these cases. VIN1 and VIN2 are supplied by the same input source. DS21949A-page 6 © 2005 Microchip Technology Inc. TC1303B TEMPERATURE SPECIFICATIONS Electrical Specifications: Unless otherwise indicated, all limits are specified for: VIN = +2.7V to +5.5V Parameters Temperature Ranges Operating Junction Temperature Range Storage Temperature Range Maximum Junction Temperature Thermal Package Resistances Thermal Resistance, 10L-DFN θJA — 41 — °C/W Typical 4-layer board with Internal Ground Plane and 2 Vias in Thermal Pad °C/W Typical 4-layer board with Internal Ground Plane TJ TA TJ -40 -65 — — — — +125 +150 +150 °C °C °C Transient Steady state Sym Min Typ Max Units Conditions Thermal Resistance, 10L-MSOP θJA — 113 — © 2005 Microchip Technology Inc. DS21949A-page 7 TC1303B 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 80 IQ Switcher and LDO (µA) 76 VIN = 5.5V IOUT1 = IOUT2 = 0 mA VOUT1 Efficiency (%) SHDN1 = VIN2 SHDN2 = VIN2 72 68 64 60 -40 -25 -10 5 VIN = 4.2V VIN = 3.6V 100 95 90 85 80 75 70 65 60 55 50 2.7 IOUT1 = 100 mA SHDN1 = VIN2 SHDN2 = AGND IOUT1 = 250 mA IOUT1 = 500 mA 20 35 50 65 80 95 110 125 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 Ambient Temperature (°C) Input Voltage (V) FIGURE 2-1: IQ Switcher and LDO Current vs. Ambient Temperature. 55 50 45 40 VIN = 4.2V SHDN1 = VIN2 SHDN2 = AGND FIGURE 2-4: VOUT1 Output Efficiency vs. Input Voltage (VOUT1 = 1.2V). 100 VOUT1 Efficiency(%) 95 90 85 80 75 70 0.005 VIN1 = 3.6V VIN1 = 4.2V VIN1 = 3.0V SHDN1 = VIN2 SHDN2 = AGND IOUT1 = 0 mA VIN = 5.5V IQ Switcher (µA) 35 30 -40 -25 -10 5 VIN = 3.6V 20 35 50 65 80 95 110 125 0.104 0.203 0.302 0.401 0.5 Ambient Temperature (°C) IOUT1 (A) FIGURE 2-2: IQ Switcher Current vs. Ambient Temperature. 55 50 IQ LDO (µA) 45 VIN = 3.6V VIN = 4.2V FIGURE 2-5: VOUT1 Output Efficiency vs. IOUT1 (VOUT1 = 1.2V). 100 95 VOUT1 Efficiency(%) 90 85 80 75 70 65 60 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 IOUT1 = 250 mA IOUT1 = 500 mA IOUT1 = 100 mA SHDN1 = VIN2 SHDN2 = AGND IOUT2 = 0 mA VIN = 5.5V 40 35 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 SHDN1 = AGND SHDN2 = VIN2 Ambient Temperature (°C) Input Voltage (V) FIGURE 2-3: Temperature. IQ LDO Current vs. Ambient FIGURE 2-6: VOUT1 Output Efficiency vs. Input Voltage (VOUT1 = 1.8V). DS21949A-page 8 © 2005 Microchip Technology Inc. TC1303B Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 100 VOUT1 Efficiency(%) 95 90 85 80 75 0.005 VIN = 3.6V VIN = 3.0V SHDN1 = VIN2 SHDN2 = AGND 1.21 1.206 VOUT1 (V) 1.202 1.198 1.194 1.19 0.005 VIN1 = 3.6V SHDN1 = VIN2 SHDN2 = AGND VIN = 4.2V 0.104 0.203 0.302 0.401 0.5 0.104 0.203 0.302 0.401 0.5 IOUT1 (A) IOUT1 (A) FIGURE 2-7: VOUT1 Output Efficiency vs. IOUT1 (VOUT1 = 1.8V). 100 VOUT1 Efficiency (%) 96 92 88 IOUT1 = 500 mA IOUT1 = 100 mA SHDN1 = VIN2 SHDN2 = AGND FIGURE 2-10: (VOUT1 = 1.2V). 1.82 1.815 VOUT1 (V) 1.81 1.805 1.8 1.795 1.79 0.005 VOUT1 vs. IOUT1 VIN1 = 3.6V SHDN1 = VIN2 SHDN2 = AGND IOUT1 = 250 mA 84 80 3.60 3.92 4.23 4.55 4.87 5.18 5.50 0.104 0.203 0.302 0.401 0.5 Input Voltage (V) IOUT1 (A) FIGURE 2-8: VOUT1 Output Efficiency vs. Input Voltage (VOUT1 = 3.3V). 100 VOUT1 Efficiency (%) 95 90 VIN1 = 3.6V FIGURE 2-11: (VOUT1 = 1.8V). 3.4 3.36 VOUT1 (V) VOUT1 vs. IOUT1 SHDN1 = VIN2 SHDN2 = AGND VIN1 = 4.2V 85 80 75 70 65 60 0.005 VIN1 = 4.2V 3.32 3.28 3.24 3.2 0.005 SHDN1 = VIN2 SHDN2 = AGND VIN1 = 5.5V 0.104 0.203 0.302 0.401 0.5 0.104 0.203 0.302 0.401 0.5 IOUT1 (A) IOUT1 (A) FIGURE 2-9: VOUT1 Output Efficiency vs. IOUT1 (VOUT1 = 3.3V). FIGURE 2-12: (VOUT1 = 3.3V). VOUT1 vs. IOUT1 © 2005 Microchip Technology Inc. DS21949A-page 9 TC1303B VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C t o +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 2.20 VOUT1 Frequency (MHz) 2.15 2.10 2.05 2.00 1.95 1.90 2.7 3.1 3.5 3.9 4.3 4.7 5.1 5.5 Input Voltage (V) Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µ F, L = 4.7 µH, VOUT1 Switch Resistance (Ω) SHDN1 = VIN2 SHDN2 = AGND 0.6 0.55 0.5 0.45 0.4 0.35 0.3 TA = 25 °C SHDN1 = VIN2 SHDN2 = AGND N-Channel P-Channel 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Input Voltage (V) FIGURE 2-13: vs. Input Voltage. 2.00 VOUT1 Frequency (MHz) 1.98 1.96 1.94 1.92 1.90 VOUT1 Switching Frequency FIGURE 2-16: vs. Input Voltage. VOUT1 Switch Resistance (Ω) 0.65 0.6 0.55 0.5 0.45 0.4 0.35 0.3 VOUT1 Switch Resistance SHDN1 = VIN2 SHDN2 = AGND VIN1 = 3.6V SHDN1 = VIN2 SHDN2 = AGND P-Channel N-Channel 20 35 50 65 80 -40 -25 -10 95 5 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ambient Temperature (°C ) Ambient Temperature (°C) FIGURE 2-14: VOUT1 Switching Frequency vs. Ambient Temperature. 0.820 VOUT1 FB Voltage (V) 0.815 0.810 0.805 0.800 0.795 0.790 110 125 20 35 50 65 80 -40 -25 -10 95 5 VIN1 = 3.6V FIGURE 2-17: Buck Regulator Switch Resistance vs. Ambient Temperature. 0.4 VOUT1 Dropout Voltage (V) 0.35 0.3 0.25 0.2 0.15 0.1 5 20 35 50 65 80 95 110 125 -40 -25 -10 VOUT1 = 3.3V IOUT1 = 500 mA SHDN1 = VIN2 SHDN2 = AGND SHDN1 = VIN2 SHDN2 = AGND Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-15: VOUT1 Adjustable Feedback Voltage vs. Ambient Temperature. FIGURE 2-18: VOUT1 Dropout Voltage vs. Ambient Temperature. DS21949A-page 10 2005 Microchip Technology Inc. TC1303B Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 1.802 VOUT2 Output Voltage (V) IOUT2 = 150 mA 1.800 1.798 1.796 1.794 1.792 SHDN1 = AGND SHDN2 = VIN2 TA = + 85°C TA = + 25°C TA = - 40°C 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 Input Voltage (V) FIGURE 2-19: VOUT1 and VOUT2 Heavy Load Switching Waveforms vs. Time. FIGURE 2-22: VOUT2 Output Voltage vs. Input Voltage (VOUT2 = 1.8V). 2.508 VOUT2 Output Voltage (V) 2.506 2.504 2.502 2.500 2.498 2.496 3.3 3.5 3.7 3.9 4.1 4.3 4.5 4.7 4.9 5.1 5.3 5.5 Input Voltage (V) TA = - 40°C TA = + 85°C SHDN1 = AGND SHDN2 = VIN2 IOUT2 = 150 mA TA = + 25°C FIGURE 2-20: VOUT1 and VOUT2 Light Load Switching Waveforms vs. Time. 1.492 VOUT2 Output Voltage(V) 1.49 1.488 1.486 1.484 1.482 2.7 3.05 3.4 3.75 4.1 4.45 4.8 5.15 5.5 TA = - 40°C IOUT2 = 150 mA FIGURE 2-23: VOUT2 Output Voltage vs. Input Voltage (VOUT2 = 2.5V). 3.298 VOUT2 Output Voltage (V) 3.297 TA = + 85°C SHDN1 = AGND SHDN2 = VIN2 IOUT2 = 150 mA TA = + 85°C 3.296 3.295 3.294 3.293 3.292 3.60 TA = - 40°C TA = + 25°C TA = + 25°C SHDN1 = AGND SHDN2 = VIN2 3.92 4.23 4.55 4.87 5.18 5.50 Input Voltage (V) Input Voltage (V) FIGURE 2-21: VOUT2 Output Voltage vs. Input Voltage (VOUT2 = 1.5V). FIGURE 2-24: VOUT2 Output Voltage vs. Input Voltage (VOUT2 = 3.3V). © 2005 Microchip Technology Inc. DS21949A-page 11 TC1303B Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 0.30 VOUT2 Dropout Voltage (V) 0.25 0.20 0.15 0.10 0.05 -40 -25 -10 5 110 125 20 35 50 65 80 95 IOUT2 = 200 mA VOUT2 Load Regulation (%) 0.1 VIN2 = 3.6V SHDN1 = AGND SHDN2 = VIN2 IOUT2 = 300 mA 0.0 -0.1 -0.2 -0.3 -0.4 5 VOUT2 = 3.3V SHDN1 = AGND SHDN2 = VIN2 VOUT2 = 2.6V VOUT2 = 1.5V 20 35 50 65 80 95 110 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-25: VOUT2 Dropout Voltage vs. Ambient Temperature (VOUT2 = 2.5V). 0.3 VOUT2 Dropout Voltage (V) SHDN1 = AGND SHDN2 = VIN2 FIGURE 2-28: VOUT2 Load Regulation vs. Ambient Temperature. 350 325 300 275 250 225 200 PG Active Delay Time (ms) VIN = 3.6V SHDN1 = VIN2 SHDN2 = VIN2 0.2 IOUT2 = 300 mA 0.1 IOUT2 = 200 mA 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ambient Temperature (°C) -40 -25 -10 5 20 35 50 65 80 95 110 125 Ambient temperature (°C) FIGURE 2-26: VOUT2 Dropout Voltage vs. Ambient Temperature (VOUT2 = 3.3V). 0.005 0.000 -0.005 -0.010 -0.015 -0.020 -0.025 -0.030 -0.035 -40 -25 -10 5 20 35 50 65 80 95 110 125 VOUT2 = 1.5V VOUT2 = 2.5V VOUT2 = 3.3V SHDN1 = AGND SHDN2 = VIN2 FIGURE 2-29: PG Active Delay Time-out vs. Ambient Temperature. 96 VIN = 3.6V VOUT2 Line Regulation (%/V) PG Threshold (% of V OUT2) 95 94 93 92 91 90 -40 -25 -10 5 PG Threshold Low PG Threshold Hi SHDN1 = VIN2 SHDN2 = VIN2 IOUT2 = 100 µA 20 35 50 65 80 95 110 125 Ambient Temperature (°C) Ambient Temperature (°C) FIGURE 2-27: VOUT2 Line Regulation vs. Ambient Temperature. FIGURE 2-30: PG Threshold Voltage vs. Ambient Temperature. DS21949A-page 12 © 2005 Microchip Technology Inc. 125 -40 -25 -10 TC1303B Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. 0.02 VIN = 3.6V 10 VOUT2 Noise (μV/ Hz) SHDN1 = VIN2 SHDN2 = VIN2 0.018 PG VOL (V) 0.016 0.014 0.012 0.01 -40 -25 -10 5 IOL = 1.2 mA SHDN1 = AGND SHDN2 = VIN2 1 0.1 VIN = 3.6V VOUT2 = 2.5V IOUT2 = 50 mA 0.01 0.01 110 125 20 35 50 65 80 95 0.1 1 10 100 1000 10000 Ambient Temperature (°C) Frequency (kHz) FIGURE 2-31: PG Output Voltage Level Low vs. Ambient Temperature. 3.0 2.5 VOUT2 = 2.5V VOUT2 = 2.8V FIGURE 2-34: VOUT2 Noise vs. Frequency. PG VOH (V) 2.0 1.5 VOUT2 = 1.5V 1.0 0.5 0.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Ambient Temperature (°C) VIN = 3.6V IOH = 500 µA SHDN1 = VIN2 SHDN2 = VIN2 FIGURE 2-32: PG Output Voltage Level High vs. Ambient Temperature. 0 -10 VOUT2 PSRR (dB) -20 -30 -40 -50 -60 -70 -80 0.01 0.1 1 10 100 1000 COUT2 = 4.7 µF SHDN1 = GND VOUT2 = 1.5V IOUT2 = 30 mA CIN = 0 µF COUT2 = 1.0 µF FIGURE 2-35: vs. Time. VOUT1 Load Step Response Frequency (kHz) FIGURE 2-33: VOUT2 Power Supply Ripple Rejection vs. Frequency. FIGURE 2-36: vs. Time. VOUT2 Load Step Response © 2005 Microchip Technology Inc. DS21949A-page 13 TC1303B Note: Unless otherwise indicated, VIN1 = VIN2 = SHDN1,2 = 3.6V, COUT1 = CIN = 4.7 µF, COUT2 = 1 µF, L = 4.7 µH, VOUT1 (ADJ) = 1.8V, TA = +25°C. Boldface specifications apply over the TA range of -40°C to +85°C. TA = +25°C. Adjustable or fixed output voltage options can be used to generate the Typical Performance Characteristics. FIGURE 2-37: VOUT1 and VOUT2 Line Step Response vs. Time. FIGURE 2-39: Waveforms. VOUT1 and VOUT2 Shutdown FIGURE 2-38: Waveforms. VOUT1 and VOUT2 Startup FIGURE 2-40: Power-Good Output Timing. DS21949A-page 14 © 2005 Microchip Technology Inc. TC1303B 3.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 3-1. TABLE 3-1: Pin No. 1 2 3 4 5 6 7 8 9 10 EP PIN FUNCTION TABLE Name SHDN2 VIN2 VOUT2 PG AGND SHDN1 VIN1 LX PGND Exposed Pad Function Active Low Shutdown Input for LDO Output Pin Analog Input Supply Voltage Pin LDO Output Voltage Pin Power-good Output Pin Analog Ground Pin VFB / VOUT1 Buck Feedback Voltage (Adjustable Version) / Buck Output Voltage (Fixed Version) Pin Active Low Shutdown Input for Buck Regulator Output Pin Buck Regulator Input Voltage Pin Buck Inductor Output Pin Power Ground Pin For the DFN package, the center exposed pad is a thermal path to remove heat from the device. Electrically this pad is at ground potential and should be connected to AGND. 3.1 LDO Shutdown Input Pin (SHDN2) 3.7 SHDN2 is a logic level input used to turn the LDO Regulator on and off. A logic high (> 45% of VIN), will enable the regulator output. A logic low (< 15% of VIN) will ensure that the output is turned off. Buck Regulator Shutdown Input Pin (SHDN1) 3.2 LDO Input Voltage Pin (VIN2) SHDN1 is a logic level input used to turn the buck regulator on and off. A logic-high (> 45% of VIN), will enable the regulator output. A logic-low (< 15% of VIN) will ensure that the output is turned off. VIN2 is a LDO power input supply pin. Connect variable input voltage source to VIN2. Connect VIN1 and VIN2 together with board traces as short as possible. VIN2 provides the input voltage for the LDO regulator. An additional capacitor can be added to lower the LDO regulator input ripple voltage. 3.8 Buck Regulator Input Voltage Pin (VIN1) 3.3 LDO Output Voltage Pin (VOUT2) VIN1 is the buck regulator power input supply pin. Connect a variable input voltage source to VIN1. Connect VIN1 and VIN2 together with board traces as short as possible. VOUT2 is a regulated LDO output voltage pin. Connect a 1 µF or larger capacitor to VOUT2 and AGND for proper operation. 3.9 Buck Inductor Output Pin (LX) 3.4 Power-Good Output Pin (PG) Connect LX directly to the buck inductor. This pin carries large signal-level current; all connections should be made as short as possible. PG is an output level indicating that VOUT2 (LDO) is within 94% of regulation. The PG output is configured as a push-pull for the TC1303B. 3.10 Power Ground Pin (PGND) 3.5 Analog Ground Pin (AGND) AGND is the analog ground connection. Tie AGND to the analog portion of the ground plane (AGND). See the physical layout information in Section 5.0 “Application Circuits/Issues” for grounding recommendations. Connect all large-signal level ground returns to PGND. These large-signal, level ground traces should have a small loop area and length to prevent coupling of switching noise to sensitive traces. Please see the physical layout information supplied in Section 5.0 “Application Circuits/Issues” for grounding recommendations. 3.11 Exposed Pad (EP) 3.6 Buck Regulator Output Sense Pin (VFB/VOUT1) For the DFN package, connect the EP to AGND with vias into the AGND plane. For VOUT1 adjustable output voltage options, connect the center of the output voltage divider to the VFB pin. For fixed-output voltage options, connect the output of the buck regulator to this pin (VOUT1). © 2005 Microchip Technology Inc. DS21949A-page 15 TC1303B 4.0 4.1 DETAILED DESCRIPTION Device Overview 4.2.1 FIXED FREQUENCY PWM MODE The TC1303B combines a 500 mA synchronous buck regulator with a 300 mA LDO and a power-good output. This unique combination provides a tiny, low-cost solution for applications that require two or more voltage rails. The buck regulator can deliver highoutput current over a wide range of input-to-output voltage ratios while maintaining high efficiency. This is typically used for the lower-voltage, high-current processor core. The LDO is a minimal parts-count solution, (single-output capacitor), providing a regulated voltage for an auxiliary rail. The typical LDO dropout voltage (137 mV @ 200 mA) allows the use of very low input-to-output LDO differential voltages, minimizing the power loss internal to the LDO pass transistor. A power-good output is provided, indicating that the LDO output is in regulation (TC1303B). Additional features include independent shutdown inputs, UVLO, overcurrent and overtemperature shutdown. While operating in Pulse Width Modulation (PWM) mode, the TC1303B buck regulator switches at a fixed 2.0 MHz frequency. The PWM mode is suited for higher load current operation, maintaining low output noise and high conversion efficiency. PFM to PWM mode transition is initiated for any of the following conditions. • Continuous inductor current is sensed • Inductor peak current exceeds 100 mA • The buck regulator output voltage has dropped out of regulation (step load has occurred) The typical PFM-to-PWM threshold is 80 mA. 4.2.2 PFM MODE 4.2 Synchronous Buck Regulator The synchronous buck regulator is capable of supplying a 500 mA continuous output current over a wide range of input and output voltages. The output voltage range is from 0.8V (min) to 4.5V (max). The regulator operates in three different modes and automatically selects the most efficient mode of operation. During heavy load conditions, the TC1303B buck converter operates at a high, fixed frequency (2.0 MHz) using current mode control. This minimizes output ripple and noise (less than 8 mV peak-to-peak ripple) while maintaining high efficiency (typically > 90%). For standby or light load applications, the buck regulator will automatically switch to a power-saving Pulse Frequency Modulation (PFM) mode. This minimizes the quiescent current draw on the battery, while keeping the buck output voltage in regulation. The typical buck PFM mode current is 38 µA. The buck regulator is capable of operating at 100% duty cycle, minimizing the voltage drop from input to output for wide input batterypowered applications. For fixed-output voltage applications, the feedback divider and control loop compensation components are integrated, eliminating the need for external components. The buck regulator output is protected against overcurrent, short circuit and overtemperature. While shut down, the synchronous buck N-channel and P-channel switches are off, so the LX pin is in a high-impedance state (this allows for connecting a source on the output of the buck regulator as long as its voltage does not exceed the input voltage). PFM mode is entered when the output load on the buck regulator is very light. Once detected, the converter enters the PFM mode automatically and begins to skip pulses to minimize unnecessary quiescent current draw by reducing the number of switching cycles per second. The typical quiescent current for the switching regulator is less than 35 µA. The transition from PWM to PFM mode occurs when discontinuous inductor current is sensed, or the peak inductor current is less than 60 mA (typ.). The typical PWM to PFM mode threshold is 30 mA. For low input-to-output differential voltages, the PWM to PFM mode threshold can be low due to the lack of ripple current. It is recommended that VIN1 be one volt greater than VOUT1 for PWM to PFM transitions. 4.3 Low Drop Out Regulator (LDO) The LDO output is a 300 mA low-dropout linear regulator that provides a regulated output voltage with a single 1 µF external capacitor. The output voltage is available in fixed options only, ranging from 1.5V to 3.3V. The LDO is stable using ceramic output capacitors that inherently provide lower output noise and reduce the size and cost of the regulator solution. The quiescent current consumed by the LDO output is typically less than 20 µA, with a typical dropout voltage of 137 mV at 200 mA. The LDO output is protected against overcurrent and overtemperature. DS21949A-page 16 © 2005 Microchip Technology Inc. TC1303B 4.4 Power-Good 4.5 Soft Start A power-good (PG) output signal is generated based off of the LDO output voltage (VOUT2). A fixed delay time of approximately 300 ms is generated once the LDO output voltage is above the power-good threshold (typically 94% of VOUT2). As VOUT2 falls out of regulation, the falling PG threshold is typically 92% of VOUT2. The PG output signal is pulled up to VOUT2 indicating that power is good and pulled low indicating that VOUT2 is out of regulation. The typical quiescent current draw for power-good circuitry is less than 10 µA. If the LDO output voltage falls below the power-good threshold, the power-good output will transition to the low state. The power-good circuitry has a 165 µs delay when detecting a falling output voltage. This helps to increase the noise immunity of the power-good output and avoiding false triggering of the PG signal during line and load transients. Both outputs of the TC1303B are controlled during startup. Less than 1% of VOUT1 or VOUT2 overshoot is observed during startup from VIN rising above the UVLO voltage or SHDN1 or SHDN2 being enabled. 4.6 Overtemperature Protection The TC1303B has an integrated overtemperature protection circuit that monitors the device junction temperature and shuts the device off if the junction temperature exceeds the typical 165°C threshold. If the overtemperature threshold is reached, the soft start is reset so that once the junction temperature cools to approximately 155°C, the device will automatically restart. VTH_H VOUT2 tRPU VOH tRPD PG VOL FIGURE 4-1: Power-Good Timing. © 2005 Microchip Technology Inc. DS21949A-page 17 TC1303B 5.0 5.1 APPLICATION CIRCUITS/ISSUES Typical Applications An additional VIN2 capacitor can be added to reduce high frequency noise on the LDO input voltage pin (VIN2). This additional capacitor (1 µF on page 3) is not necessary for typical applications. The TC1303B 500 mA buck regulator + 300 mA LDO with power-good operates over a wide input voltage range (2.7V to 5.5V) and is ideal for single-cell Li-Ion battery-powered applications, USB-powered applications, three-cell NiMH or NiCd applications and 3V to 5V regulated input applications. The 10-pin MSOP and 3X3 DFN packages provide a small footprint with minimal external components. 5.4 Input and Output Capacitor Selection 5.2 Fixed Output Application A typical VOUT1 fixed output voltage application is shown in “Typical Application Circuits” on page 3. A 4.7 µF VIN1 ceramic input capacitor, 4.7 µF VOUT1 ceramic capacitor, 1.0 µF ceramic VOUT2 capacitor and 4.7 µH inductor make up the entire external component solution for this dual-output application. No external dividers or compensation components are necessary. For this application, the input voltage range is 2.7V to 4.2V, VOUT1 = 1.5V at 500 mA, while VOUT2 = 2.5V at 300 mA. As with all buck-derived dc-dc switching regulators, the input current is pulled from the source in pulses. This places a burden on the TC1303B input filter capacitor. In most applications, a minimum of 4.7 µF is recommended on VIN1 (buck regulator input voltage pin). In applications that have high source impedance or have long leads (10 inches) connecting to the input source, additional capacitance should be used. The capacitor type can be electrolytic (aluminum, tantalum, POSCAP, OSCON) or ceramic. For most portable electronic applications, ceramic capacitors are preferred due to their small size and low cost. For applications that require very low noise on the LDO output, an additional capacitor (typically 1 µF) can be added to the VIN2 pin (LDO input voltage pin). Low ESR electrolytic or ceramic can be used for the buck regulator output capacitor. Again, ceramic is recommended because of its physical attributes and cost. For most applications, a 4.7 µF is recommended. Refer to Table 5-1 for recommended values. Larger capacitors (up to 22 µF) can be used. There are some advantages in load step performance when using larger value capacitors. Ceramic materials X7R and X5R have low temperature coefficients and are well within the acceptable ESR range required. 5.3 Adjustable Output Application A typical VOUT1 adjustable output application is also shown in “Typical Application Circuits” on page 3. For this application, the buck regulator output voltage is adjustable by using two external resistors as a voltage divider. For adjustable output voltages, it is recommended that the top resistor divider value be 200 kΩ. The bottom resistor divider can be calculated using the following formula: TABLE 5-1: TC1303B RECOMMENDED CAPACITOR VALUES C(VIN2) none none COUT1 4.7 µF 22 µF COUT2 1 µF 10 µF EQUATION 5-1: V FB R BOT = R TOP × ⎛ ------------------------------- ⎞ ⎝ VOUT1 – V FB⎠ Example: RTOP = 200 kΩ VOUT1 = 2.1V VFB = 0.8V RBOT = 200 kΩ x (0.8V/(2.1V – 0.8V)) RBOT = 123 kΩ (Standard Value = 121 kΩ) For adjustable output applications, an additional R-C compensation is necessary for the buck regulator control loop stability. Recommended values are: RCOMP = 4.99 kΩ CCOMP = 33 pF C(VIN1) min max 4.7 µF none DS21949A-page 18 © 2005 Microchip Technology Inc. TC1303B 5.5 Inductor Selection TABLE 5-2: For most applications, a 4.7 µH inductor is recommended to minimize noise. There are many different magnetic core materials and package options to select from. That decision is based on size, cost and acceptable radiated energy levels. Toroid and shielded ferrite pot cores will have low radiated energy but tend to be larger and higher is cost. With a typical 2.0 MHz switching frequency, the inductor ripple current can be calculated based on the following formulas. TC1303B RECOMMENDED INDUCTOR VALUES DCR MAX Ω IDC (A) (MAX) 0.091 0.108 0.154 0.075 0.104 0.118 ® Part Number Value (µH) Size WxLxH (mm) Coiltronics® SD10 SD10 SD10 Coiltronics SD12 SD12 SD12 CMD411 CMD411 CMD411 Coilcraft ® 2.2 3.3 4.7 2.2 3.3 4.7 2.2 3.3 4.7 4.7 4.7 1.35 1.24 1.04 1.80 1.42 1.29 5.2, 5.2, 1.0 max. 5.2, 5.2, 1.0 max. 5.2, 5.2, 1.0 max. 5.2, 5.2, 1.2 max. 5.2, 5.2, 1.2 max. 5.2, 5.2, 1.2 max. EQUATION 5-2: V OUT DutyCycle = ------------V IN Duty cycle represents the percentage of switch-on time. Sumida Corporation 0.116 0.174 0.216 0.35 0.11 0.950 4.4, 5.8, 1.2 max. 0.770 4.4, 5.8, 1.2 max. 0.750 4.4, 5.8, 1.2 max. 1.0 1.15 3.8,3.8,2.74 max. 5.9,5.0, 3.81 max EQUATION 5-3: 1 T ON = DutyCycle × --------F SW Where: FSW = Switching Frequency. The inductor ac ripple current can be calculated using the following relationship: 1008PS 1812PS 5.6 5.6.1 Thermal Calculations BUCK REGULATOR OUTPUT (VOUT1) EQUATION 5-4: Δ IL V L = L × -------Δt Where: VL = voltage across the inductor (VIN – VOUT) Δt = on-time of P-channel MOSFET Solving for ΔIL = yields: The TC1303B is available in two different 10-pin packages (MSOP and 3X3 DFN). By calculating the power dissipation and applying the package thermal resistance, (θJA), the junction temperature is estimated. The maximum continuous junction temperature rating for the TC1303B is 125°C. To quickly estimate the internal power dissipation for the switching buck regulator, an empirical calculation using measured efficiency can be used. Given the measured efficiency (Section 2.0 “Typical Performance Curves”), the internal power dissipation is estimated below. EQUATION 5-5: VL Δ I L = ----- × Δ t L When considering inductor ratings, the maximum DC current rating of the inductor should be at least equal to the maximum buck regulator load current (IOUT1), plus one half of the peak-to-peak inductor ripple current (1/2 * ΔIL). The inductor DC resistance can add to the buck converter I2R losses. A rating of less than 200 mΩ is recommended. Overall efficiency will be improved by using lower DC resistance inductors. EQUATION 5-6: ⎛ V OUT1 × I OUT1⎞ – ( V ------------------------------------OUT1 × I OUT1 ) = P Dissipation ⎝ Efficiency ⎠ The first term is equal to the input power (definition of efficiency, POUT/PIN = Efficiency). The second term is equal to the delivered power. The difference is internal power dissipation. This is an estimate assuming that most of the power lost is internal to the TC1303B. There is some percentage of power lost in the buck inductor, with very little loss in the input and output capacitors. © 2005 Microchip Technology Inc. DS21949A-page 19 TC1303B As an example, for a 3.6V input, 1.8V output with a load of 400 mA, the efficiency taken from Figure 2-7 is approximately 84%. The internal power dissipation is approximately 171 mW. placed near their respective pins to minimize trace length. The CIN1 and COUT1 capacitor returns are connected closely together at the PGND plane. The LDO optional input capacitor (CIN2) and LDO output capacitor COUT2 are returned to the AGND plane. The analog ground plane and power ground plane are connected at one point (shown near L1). All other signals (SHDN1, SHDN2, feedback in the adjustable output case) should be referenced to AGND and have the AGND plane underneath them. - Via AGND to PGND +VOUT1 L1 5.6.2 LDO OUTPUT (VOUT2) The internal power dissipation within the TC1303B LDO is a function of input voltage, output voltage and output current. The following equation can be used to calculate the internal power dissipation for the LDO. EQUATION 5-7: PLDO = ( V IN ( MAX ) ) – V OUT2 ( MIN ) ) × I OUT2 ( MAX ) ) Where: PLDO = LDO Pass device internal power dissipation * CIN2 Optional COUT1 AGND CIN2 +VIN2 +VOUT2 COUT2 VIN(MAX) = Maximum input voltage VOUT(MIN) = LDO minimum output voltage The maximum power dissipation capability for a package can be calculated given the junction-toambient thermal resistance and the maximum ambient temperature for the application. The following equation can be used to determine the package’s maximum internal power dissipation. PGND 1 2 3 4 5 10 9 8 7 TC1303B 6 AGND Plane PGND Plane CIN1 +VIN1 AGND 5.6.3 LDO POWER DISSIPATION EXAMPLE FIGURE 5-1: Component Placement, Fixed 10-Pin MSOP. There will be some difference in layout for the 10-pin DFN package due to the thermal pad. A typical fixedoutput DFN layout is shown below. For the DFN layout, the VIN1 to VIN2 connection is routed on the bottom of the board around the TC1303B thermal pad. - Via +VOUT1 Input Voltage VIN = 5V±10% LDO Output Voltage and Current VOUT = 3.3V IOUT = 300 mA Internal Power Dissipation PLDO(MAX) = (VIN(MAX) – VOUT(MIN)) x IOUT(MAX) PLDO = (5.5V) – (0.975 x 3.3V)) x 300 mA PLDO = 684.8 mW AGND to PGND * CIN2 Optional AGND PGND CIN2 +VIN2 1 2 3 4 5 10 9 8 7 6 PGND CIN1 COUT1 L1 5.7 PCB Layout Information +VOUT2 COUT2 +VIN1 Some basic design guidelines should be used when physically placing the TC1303B on a Printed Circuit Board (PCB). The TC1303B has two ground pins, identified as AGND (analog ground) and PGND (power ground). By separating grounds, it is possible to minimize the switching frequency noise on the LDO output. The first priority, while placing external components on the board, is the input capacitor (CIN1). Wiring should be short and wide; the input current for the TC1303B can be as high as 800 mA. The next priority would be the buck regulator output capacitor (COUT1) and inductor (L1). All three of these components are AGND TC1303B PGND Plane AGND Plane FIGURE 5-2: Component Placement, Fixed 10-Pin DFN. DS21949A-page 20 © 2005 Microchip Technology Inc. TC1303B 5.8 Design Example VOUT1 = 2.0V @ 500 mA VOUT2 = 3.3V @ 300 mA VIN = 5V±10% L = 4.7µH Calculate PWM mode inductor ripple current Nominal Duty Cycle = 2.0V/5.0V = 40% P-channel Switch-on time = 0.40 x 1/(2 MHz) = 200 ns VL = (VIN-VOUT1) = 3V ΔIL = (VL/L) x TON = 128 mA Peak inductor current: IL(PK) = IOUT1+1/2ΔIL = 564 mA Switcher power loss: Use efficiency estimate for 1.8V from Figure 2-7 Efficiency = 84%, PDISS1 = 171 mW Resistor Divider: RTOP = 200 kΩ RBOT = 133 kΩ LDO Output: PDISS2 = (VIN(MAX) – VOUT2(MIN)) x IOUT2(MAX) PDISS2 = (5.5V – (0.975) x 3.3V) x 300 mA PDISS2 = 684.8 mW Total Dissipation = 171 mW + 685 mW = 856 mW Junction Temp Rise and Maximum Ambient Operating Temperature Calculations 10-Pin MSOP (4-Layer Board with internal Planes) RθJA = 113° C/Watt Junction Temp. Rise = 856 mW x 113° C/Watt = 96.7°C Max. Ambient Temperature = 125°C - 96.7°C Max. Ambient Temperature = 28.3°C 10-Pin DFN RθJA = 41° C/Watt (4-Layer Board with internal planes and 2 vias) Junction Temp. Rise = 856 mW x 41° C/Watt = 35.1°C Max. Ambient Temperature = 125°C - 35.1°C Max. Ambient Temperature = 89.9°C This is above the 85°C max. ambient temperature. © 2005 Microchip Technology Inc. DS21949A-page 21 TC1303B 6.0 6.1 PACKAGING INFORMATION Package Marking Information Example: — 1 = TC1303B — 1 = 1.375V VOUT1 — H = 2.6V VOUT2 — 0 = Default 10-Lead DFN XXXX YYWW NNN Example: 11H0 0520 256 10-Lead MSOP* XXXXXX YWWNNN 11H0/E 520256 * The MSOP package for this device has not been qualified at the time of this publication. Contact your Microchip sales office for availability. Second letter represents VOUT1 configuration: Code A B C D E F G H I VOUT1 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT1 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Code S T U V W X Y Z 1 VOUT1 1.5V 1.4V 1.3V 1.2V 1.1V 1.0V 0.9V Adj 1.375V Third letter represents VOUT2 configuration: Code A B C D E F G H I VOUT2 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V Code J K L M N O P Q R VOUT1 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V Code S T U V W X Y Z VOUT2 1.5V — — — — — — — Fourth letter represents +50 mV Increments: Code 0 1 Default +50 mV to V1 Code 2 3 +50 mV to V2 +50 mV to V1 and V2 Legend: XX...X Y YY WW NNN e3 * Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. DS21949A-page 22 © 2005 Microchip Technology Inc. TC1303B 10-Lead Plastic Dual Flat No Lead Package (MF) 3x3x0.9 mm Body (DFN) – Saw Singulated p E b n L D D2 PIN 1 ID INDEX AREA (NOTE 2) EXPOSED METAL PAD E2 2 1 TOP VIEW BOTTOM VIEW A A3 A1 EXPOSED TIE BAR (NOTE 1) INCHES NOM 10 .020 BSC .035 .001 .008 REF. .118 -.118 -.010 .016 MILLIMETERS* NOM 10 0.50 BSC 0.80 0.90 0.00 0.02 0.20 REF. 2.85 3.00 1.39 -2.85 3.00 1.20 -0.18 0.25 0.30 0.40 Number of Pins Pitch Overall Height Standoff Lead Thickness Overall Length Exposed Pad Length Overall Width Exposed Pad Width Lead Width Lead Length Units Dimension Limits n e A A1 A3 E E2 D D2 b L MIN MAX MIN MAX .031 .000 .112 .055 .112 .047 .008 .012 .039 .002 .124 .096 .124 .069 .015 .020 1.00 0.05 3.15 2.45 3.15 1.75 0.30 0.50 (Note 3) (Note 3) *Controlling Parameter Notes: 1. Package may have one or more exposed tie bars at ends. 2. Pin 1 visual index feature may vary, but must be located within the hatched area. 3. Exposed pad dimensions vary with paddle size. 4. JEDEC equivalent: Not registered Drawing No. C04-063 Revised 05/24/04 © 2005 Microchip Technology Inc. DS21949A-page 23 TC1303B 10-Lead Plastic Micro Small Outline Package (UN) (MSOP*) E E1 p D B n 2 1 α φ c A2 A1 (F) β L1 L A Number of Pins Pitch .043 Overall Height A .037 Molded Package Thickness A2 .030 Standoff .006 A1 .000 Overall Width E Molded Package Width E1 Overall Length D Foot Length .031 L .016 Footprint F φ Foot Angle 0° 8° c Lead Thickness .009 .003 Lead Width .012 B .006 α Mold Draft Angle Top 5° 15° β Mold Draft Angle Bottom 5° 15° *Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MO-187 Drawing No. C04-021 Units Dimension Limits n p MIN INCHES NOM 10 .020 TYP .033 .193 BSC .118 BSC .118 BSC .024 .037 REF .009 - MAX MIN MILLIMETERS* NOM 10 0.50 TYP. 0.85 0.75 0.00 4.90 BSC 3.00 BSC 3.00 BSC 0.60 0.40 0.95 REF 0° 0.08 0.15 0.23 5° 5° MAX 1.10 0.95 0.15 0.80 8° 0.23 0.30 15° 15° * The MSOP package for the TC1303B has not been qualified at the time of this publication. Contact your Microchip sales office for availability. DS21949A-page 24 © 2005 Microchip Technology Inc. TC1303B APPENDIX A: REVISION HISTORY Revision A (June 2005) • Original Release of this Document. © 2005 Microchip Technology Inc. DS21949A-page 25 TC1303B NOTES: DS21949A-page 26 © 2005 Microchip Technology Inc. TC1303B PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. TC1303 XX X X X XX Package XX Tube or Tape & Reel Examples: a) TC1303B-IA0EMF: TC1303B-ZA0EUN: TC1303B-PG0EMFTR: 2.5V, 3.3V, Default, 10LD DFN pkg. Adj, 3.3V, Default, 10LD MSOP pkg. 1.8V, 2.7V, Default, 10LD DFN pkg. Tape and Reel Type VOUT1 VOUT2 +50 mV Temp Increments Range B b) c) Device: TC1303B: PWM/LDO combo with Power-Good. Options Code A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 1 VOUT1 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V 1.5V 1.4V 1.3V 1.2V 1.1V 1.0V 0.9V Adjustable 1.375V Code A B C D E F G H I J K L M N O P Q R S T U V W X Y Z 1 VOUT2 3.3V 3.2V 3.1V 3.0V 2.9V 2.8V 2.7V 2.6V 2.5V 2.4V 2.3V 2.2V 2.1V 2.0V 1.9V 1.8V 1.7V 1.6V 1.5V Code 0 1 2 3 +50 mV Default +50 mV to V1 +50 mV to V2 +50 mV to V1 and V2 * Contact Factory for Alternate Output Voltage and Reset Voltage Configurations. Temperature Range: E = -40°C to +85°C Package: MF UN = Dual Flat, No Lead (3x3 mm body), 10-lead = Plastic Micro Small Outline (MSOP), 10-lead (The MSOP package for this device has not been qualified at the time of this publication. Contact your Microchip sales office for availability.) Tube or Tape and Reel: Blank TR = Tube = Tape and Reel © 2005 Microchip Technology Inc. DS21949A-page 27 TC1303B NOTES: DS21949A-page 28 © 2005 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2005 Microchip Technology Inc. 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