TC510CPE

TC500/A/510/514 Precision Analog Front Ends Features: • Precision (up to 17 bits) A/D Converter “Front End” • 3-Pin Control Interface to Microprocessor • Flexible: User Can Trade-off Conversion Speed for Resolution • Single-Supply Operation (TC510/TC514) • 4 Input, Differential Analog MUX (TC514) • Automatic Input Voltage Polarity Detection • Low Power Dissipation: - (TC500/TC500A): 10 mW - (TC510/TC514): 18 mW • Wide Analog Input Range: - ±4.2V (TC500A/TC510) • Directly Accepts Bipolar and Differential Input Signals General Description: TheTC500/A/510/514 family are precision analog front ends that implement dual slope A/D converters having a maximum resolution of 17 bits plus sign. As a minimum, each device contains the integrator, zero crossing comparator and processor interface logic. The TC500 is the base (16-bit max) device and requires both positive and negative power supplies. The TC500A is identical to the TC500 with the exception that it has improved linearity, allowing it to operate to a maximum resolution of 17 bits. The TC510 adds an onboard negative power supply converter for singlesupply operation. The TC514 adds both a negative power supply converter and a 4-input differential analog multiplexer. Each device has the same processor control interface consisting of 3 wires: control inputs (A and B) and zerocrossing comparator output (CMPTR). The processor manipulates A, B to sequence the TC5XX through four phases of conversion: auto-zero, integrate, de-integrate and integrator zero. During the auto-zero phase, offset voltages in the TC5XX are corrected by a closed loop feedback mechanism. The input voltage is applied to the integrator during the integrate phase. This causes an integrator output dv/dt directly proportional to the magnitude of the input voltage. The higher the input voltage, the greater the magnitude of the voltage stored on the integrator during this phase. At the start of the de-integrate phase, an external voltage reference is applied to the integrator and, at the same time, the external host processor starts its on-board timer. The processor maintains this state until a transition occurs on the CMPTR output, at which time the processor halts its timer. The resulting timer count is the converted analog data. Integrator zero (the final phase of conversion) removes any residue remaining in the integrator in preparation for the next conversion. The TC500/A/510/514 offer high resolution (up to 17 bits), superior 50/60 Hz noise rejection, low-power operation, minimum I/O connections, low input bias currents and lower cost compared to other converter technologies having similar conversion speeds. Applications: • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements © 2006 Microchip Technology Inc. DS21428D-page 1 TC500/A/510/514 Package Types 16-Pin PDIP/SOIC/CERDIP CINT 1 VSS CAZ BUF ACOM 2 3 4 5 16 VDD 15 DGND 14 CMPTR OUT VOUT – CINT CAZ BUF ACOM CREF – CREF+ VREF – VREF+ CH4– CH3– CH2– CH1– N/C 28-Pin PDIP/SOIC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 CAP– 27 DGND 26 CAP+ 25 VDD 24 OSC 23 CMPTR OUT TC500/ TC500A 13 B 12 A 11 VIN+ 10 VIN – 9 VREF+ CREF – 6 CREF+ 7 VREF − 8 TC514 22 A 21 B 20 A0 19 A1 18 CH1+ 17 CH2+ 16 CH3+ 15 CH4+ 24-Pin PDIP/SOIC VOUT – CINT CAZ BUF ACOM CREF – CREF+ VREF – VREF+ 1 2 3 4 5 6 7 8 9 24 23 22 21 20 CAP– DGND CAP+ VDD OSC CMPTR OUT A B VIN+ VIN – N/C N/C TC510 19 18 17 16 15 14 13 N/C 10 N/C 11 N/C 12 Typical Application CREF A0 A1 VREF+ VREFCREFBuffer + SWRI- SWRI+ + SWZ SWIZ SWZ SWRI+ SWRISW1 Analog Switch Control Signals VOUTCAP- CAP+ VSS (TC500 TC500A) A B Control Logic Phase Decoding Logic DGND Polarity Detection RINT CAZ BUF CAZ Integrator CINT CINT A 0 0 1 1 B 0 1 0 1 Control Logic Converter Sate Zero Integrator Output Auto-Zero Signal Integrate De-integrate CREF+ CH1+ CH2+ CH3+ CH4+ CH1CH2CH3CH4ACOM SWR SWR DIF. MUX (TC514) SWI TC500 TC500A TC510 CMPTR 1 CMPTR 2 TC514 + Level Shift CMPTR Output SWI VSS OSC DC-TO-DC Converter (TC510 & TC514) 1.0 μF COUT- 1.0 μF DS21428D-page 2 © 2006 Microchip Technology Inc. TC500/A/510/514 1.0 ELECTRICAL CHARACTERISTICS † Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings† TC510/TC514 Positive Supply Voltage (VDD to GND) ......................................... +10.5V TC500/TC500A Supply Voltage (VDD to VSS) .............................................. +18V TC500/TC500A Positive Supply Voltage (VDD to GND) ............................................ +12V TC500/TC500A Negative Supply Voltage (VSS to GND)................................................-8V Analog Input Voltage (VIN+ or VIN-) ............VDD to VSS Logic Input Voltage...............VDD +0.3V to GND - 0.3V Voltage on OSC: ........................... -0.3V to (VDD +0.3V) for VDD < 5.5V Ambient Operating Temperature Range: ................................................................ 0°C to +70°C Storage Temperature Range: ............. -65°C to +150°C DC CHARACTERISTICS Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V. CAZ = CREF = 0.47 μF. Parameters Analog Resolution Zero-scale Error with Auto-zero Phase End Point Linearity ZSE ENL 60 — — — — Best-Case Straight Line Linearity Zero-scale Temp. Coefficient Full-scale Symmetry Error (Rollover Error) Full-scale Temperature Coefficient Input Current Common Mode Voltage Range Integrator Output Swing Analog Input Signal Range Note 1: 2: 3: NL — — ZSTC SYE FSTC — — — — — — 0.005 — 0.003 — — 0.01 — — 0.005 0.003 0.015 0.010 0.008 0.005 — — — — — — — — — — — — — — 0.005 0.003 0.015 0.010 — — 1 0.03 10 — 0.012 0.009 0.060 0.045 — — 2 — — % F.S. % F.S. % F.S. % F.S. μV/°C μV Sym Min. TA = +25°C Typ. Max. TA = 0°C to 70°C Min. Typ. Max. Units Conditions Note 1 TC500/TC510/TC514 TC500A TC500/TC510/TC514 Note 1, Note 2, TC500A TC500/TC510/TC514, Note 1, Note 2 TC500A Over Operating Temperature Range Note 1 % F.S. % F.S. ppm/°C Over Operating Temperature Range; External Reference TC = 0 ppm/°C pA V V V ACOM = GND = 0V VIN = 0V IIN VCMR — VSS + 1.5 VSS + 0.9 VSS + 1.5 6 — — — — VDD – 1.5 VDD – 0.9 — VSS + 1.5 VSS + 0.9 — — — — — VDD – 1.5 VSS + 0.9 VSS + 1.5 VDD – 1.5 VSS + 1.5 Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics. © 2006 Microchip Technology Inc. DS21428D-page 3 TC500/A/510/514 DC CHARACTERISTICS (CONTINUED) Electrical Specifications: Unless otherwise specified, TC510/TC514: VDD = +5V, TC500/TC500A: VSS = ±5V. CAZ = CREF = 0.47 μF. Parameters Voltage Reference Range Digital Comparator Logic 1, Output High Comparator Logic 0, Output Low Logic 1, Input High Voltage Logic 0, Input Low Voltage Logic Input Current Comparator Delay Multiplexer (TC514 Only) Maximum Input Voltage Drain/Source ON Resistance Supply Current Power Dissipation Positive Supply Operating Voltage Range Operating Source Resistance Oscillator Frequency Maximum Current Out Supply Current Power Dissipation Positive Supply Operating Range Negative Supply Operating Range Note 1: 2: 3: IOUT RDSON -2.5 — — 6 2.5 10 -2.5 — — — 2.5 — V kΩ VDD = 5V VDD = 5V VOH VOL VIH VIL IL tD 4 — 3.5 — — — — — — — — 2 — 0.4 — 1 — — 4 — 3.5 — — — — — — — 0.3 3 — — 0.4 — 1 V V V V μA μsec Sym Min. VREF VSS +1 TA = +25°C Typ. — Max. VDD – 1 TA = 0°C to 70°C Min. VSS +1 Typ. — Max. VDD – 1 Units V Conditions VREF- VREF+ ISOURCE = 400 μA ISINK = 2.1 mA Logic ‘1’ or ‘0’ Power (TC510/TC514 Only) IS PD VDD — — 4.5 1.8 18 — 2.4 — 5.5 — — 4.5 — — — 3.5 — 5.5 mA mW V VDD = 5V, A = 1, B = 1 VDD = 5V ROUT — — — 60 100 — 85 — -10 — — — — — — 100 — -10 Ω kHz mA IOUT = 10 mA Note 1 VDD = 5V Power (TC500/TC500A Only) IS PD VDD VSS — — 4.5 -4.5 1 10 — — 1.5 — 7.5 -7.5 — — 4.5 - 4.5 — — — — 2.5 — 7.5 -7.5 mA mW V V VS = ±5V, A = B = 1 VDD = 5V, VSS = -5V Integrate time ≥ 66 msec, auto-zero time ≥ 66 msec, VINT (peak) ≈ 4V. End point linearity at ±1/4, ±1/2, ±3/4 F.S. after full-scale adjustment. Rollover error is related to CINT, CREF, CAZ characteristics. DS21428D-page 4 © 2006 Microchip Technology Inc. TC500/A/510/514 2.0 Note: TYPICAL PERFORMANCE CURVES The graphs and tables provided following this note are a statistical summary based on a limited number of samples and are provided for informational purposes only. The performance characteristics listed herein are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified operating range (e.g., outside specified power supply range) and therefore outside the warranted range. -0 TA = +25°C V+ = 5V TA = +25°C 5 4 3 Output Voltage (V) 2 1 0 -1 -2 -3 -4 -5 0 -1 Output Voltage (V) -2 -3 -4 -5 -6 -7 -8 Slope 60Ω 10 20 30 40 60 50 Load Current (mA) 70 80 0 2 4 6 8 10 12 14 Output Current (mA) 16 18 20 FIGURE 2-1: Current. 200 Output Ripple (mV PK-PK) 175 150 125 100 75 50 25 0 0 1 2 3 Output Voltage vs. Load FIGURE 2-4: Current. 100 Output Source Resistance (Ω) V+ = 5V IOUT = 10 mA Output Voltage vs. Output V+ = 5V, TA = +25°C Osc. Freq. = 100 kHz 90 80 70 60 50 40 -50 CAP = 1 µF CAP = 10 µF 4 5 6 7 Load Current (mA) 8 9 10 -25 0 25 50 Temperature (°C) 75 100 FIGURE 2-2: Current. 100 Oscillator Frequency (kHz) Output Ripple vs. Load FIGURE 2-5: vs. Temperature. 150 Oscillator Frequency (kHz) Output Source Resistance TA = +25°C V+ = 5V V+ = 5V 125 10 100 75 50 -50 1 1 10 100 Oscillator Capacitance (pF) 1000 -25 0 25 75 50 Temperature (°C) 100 125 FIGURE 2-3: Capacitance. Oscillator Frequency vs. FIGURE 2-6: Temperature. Oscillator Frequency vs. © 2006 Microchip Technology Inc. DS21428D-page 5 TC500/A/510/514 3.0 PIN DESCRIPTIONS PIN FUNCTION TABLE The descriptions of the pins are listed in Table 3-1. TABLE 3-1: TC500, TC500A 1 2 3 4 5 6 7 8 9 10 11 12 13 Pin No. TC510 2 Not Used 3 4 5 6 7 8 9 15 16 18 17 TC514 2 Not Used 3 4 5 6 7 8 9 Not Used Not Used 22 21 Symbol CINT VSS CAZ BUF ACOM CREFCREF+ VREFVREF+ VINVIN+ A B Function Integrator output. Integrator capacitor connection. Negative power supply input (TC500/TC500A only). Auto-zero input. The auto-zero capacitor connection. Buffer output. The Integrator capacitor connection. This pin is grounded in most applications. It is recommended that ACOM and the input common pin (Ven- or CHn-) be within the analog Common Mode Range (CMR). Input. Negative reference capacitor connection. Input. Positive reference capacitor connection. Input. External voltage reference (-) connection. Input. External voltage reference (+) connection. Negative analog input. Positive analog input. Input. Converter phase control MSB. (See input B.) Input. Converter phase control LSB. The states of A, B place the TC5XX in one of four required phases. A conversion is complete when all four phases have been executed: Phase control input pins: AB = 00: Integrator zero 01: Auto-zero 10: Integrate 11: De-integrate 14 19 23 CMPTR Zero crossing comparator output. CMPTR is high during the integration phase when OUT a positive input voltage is being integrated and is low when a negative input voltage is being integrated. A high-to-low transition on CMPTR signals the processor that the De-integrate phase is completed. CMPTR is undefined during the auto-zero phase. It should be monitored to time the integrator zero phase. DGND VDD CAP+ CAPVOUTInput. Digital ground. Input. Power supply positive connection. Input. Negative power supply converter capacitor (+) connection. Input. Negative power supply converter capacitor (-) connection. Output. Negative power supply converter output and reservoir capacitor connection. This output can be used to power other devices in the circuit requiring a negative bias voltage. Oscillator control input. The negative power supply converter normally runs at a frequency of 100 kHz. The converter oscillator frequency can be slowed down (to reduce quiescent current) by connecting an external capacitor between this pin and VDD (see Section 2.0 “Typical Performance Curves”). Positive analog input pin. MUX channel 1. Negative analog input pin. MUX channel 1. Positive analog input pin. MUX channel 2. Negative analog input pin. MUX channel 2. Positive analog input pin. MUX channel 3. Negative analog input pin. MUX channel 3. Positive analog input pin. MUX channel 4. Negative analog input pin. MUX channel 4 Multiplexer input channel select input LSB (see A1). Multiplexer input channel select input MSB. Phase control input pins: A1, A0 = 00 = Channel 1 01 = Channel 2 10 = Channel 3 11 = Channel 4 15 16 — — — 23 21 22 24 1 27 25 26 28 1 — 20 24 OSC — — — — — — — — — — — — — — — — — — — — 18 13 17 12 16 11 15 10 20 19 CH1+ CH1CH2+ CH2CH3+ CH3CH4+ CH4A0 A1 DS21428D-page 6 © 2006 Microchip Technology Inc. TC500/A/510/514 4.0 4.1 DETAILED DESCRIPTION Dual Slope Conversion Principles multiples of the integration period are, theoretically, completely removed, since the average value of a sine wave of frequency (1/T) averaged over a period (T) is zero. Integrating converters often establish the integration period to reject 50/60 Hz line frequency interference signals. The ability to reject such signals is shown by a normal mode rejection plot (Figure 4-1). Normal mode rejection is limited in practice to 50 to 65 dB, since the line frequency can deviate by a few tenths of a percent (Figure 4-2). Actual data conversion is accomplished in two phases: input signal integration and reference voltage de-integration. The integrator output is initialized to 0V prior to the start of integration. During integration, analog switch S1 connects VIN to the integrator input where it is maintained for a fixed time period (TINT). The application of VIN causes the integrator output to depart 0V at a rate determined by the magnitude of VIN and a direction determined by the polarity of VIN. The de-integration phase is initiated immediately at the expiration of TINT. During de-integration, S1 connects a reference voltage (having a polarity opposite that of VIN) to the integrator input. At the same time, an external precision timer is started. The de-integration phase is maintained until the comparator output changes state, indicating the integrator has returned to its starting point of 0V. When this occurs, the precision timer is stopped. The deintegration time period (TDEINT), as measured by the precision timer, is directly proportional to the magnitude of the applied input voltage (see Figure 4-3). A simple mathematical equation relates the input signal, reference voltage and integration time: Normal Mode Rejection (dB) 30 T = Measurment Period 20 10 0 0.1/T 1/T Input Frequency 10/T FIGURE 4-1: Integrating Converter Normal Mode Rejection. 80 EQUATION 4-1: Normal Mode Rejeciton (dB) V REF C DEINT T 1 ----------------------- ∫ INT V IN ( T ) DT = ------------------------------RINT C INT R INT C INT 0 Where: VREF = Reference Voltage TINT = Signal Integration time (fixed) tDEINT = Reference Voltage Integration time (variable) For a constant VIN: 70 t = 0.1 sec 60 50 40 30 DEV SIN 60 p t (1 ± 100 ) 60 p t (1 ± DEV) 100 DEV = Deviation from 60 Hz t = Integration Period Normal Mode = 20 LOG REJECTION EQUATION 4-2: VIN T DEINT = V REF ----------------T INT 20 0.01 0.1 1.0 Line Frequency Deviation from 60 Hz (%) The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values as long as they are stable during a measurement cycle. An inherent benefit is noise immunity. Input noise spikes are integrated (averaged to zero) during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high noise environments. Integrating converters provide inherent noise rejection with at least a 20dB/decade attenuation rate. Interference signals with frequencies at integral FIGURE 4-2: Line Frequency Deviation. © 2006 Microchip Technology Inc. DS21428D-page 7 TC500/A/510/514 CINT Analog Input (VIN) S1 Switch Driver Polarity Control RINT Integrator – + + Phase Control ± Ref Voltage TC510 VINT – Comparator CMPTR Out Control Logic A Integrator Output VSUPPLY VINT B I/O VIN ≈ VREF VIN ≈ 1/2 VREF TINT TDEINT Microcomputer ROM RAM Timer Counter FIGURE 4-3: Basic Dual Slope Converter. DS21428D-page 8 © 2006 Microchip Technology Inc. TC500/A/510/514 5.0 TC500/A/510/514 CONVERTER OPERATION The internal analog switch status for each of these phases is summarized in Table 5-1. This table references the Typical Application. The TC500/A/510/514 incorporates an auto-zero and Integrator phase in addition to the input signal Integrate and reference De-integrate phases. The addition of these phases reduce system errors, calibration steps and shorten overrange recovery time. A typical measurement cycle uses all four phases in the following order: 1. 2. 3. 4. Auto-zero. Input signal integration. Reference de-integration. Integrator output zero. TABLE 5-1: INTERNAL ANALOG GATE STATUS SWI — Closed — — SW–RI SWR+ — — * Closed — SWR— — — — SWZ Closed — — — SWR Closed — — Closed SW1 Closed — Closed Closed SWIZ — — — Closed Conversion Phase Auto-zero (A = 0, B = 1) Input Signal Integration (A = 1, B = 0) Reference Voltage De-integration (A =1, B = 1) Integrator Output Zero (A = 0, B = 0) * Assumes a positive polarity input signal. would be closed for a negative input signal. 5.1 Auto-zero Phase (AZ) 5.3 During this phase, errors due to buffer, integrator and comparator offset voltages are nulled out by charging CAZ (auto-zero capacitor) with a compensating error voltage. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to analog common. The reference capacitor is charged to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the capacitor (CAZ) with a voltage to compensate for buffer amplifier, integrator and comparator offset voltages. Reference Voltage De-integration Phase (DINT) The previously charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero. An externally-provided, precision timer is used to measure the duration of this phase. The resulting time measurement is proportional to the magnitude of the applied input voltage. 5.4 Integrator Output Zero Phase (IZ) 5.2 Analog Input Signal Integration Phase (INT) The TC5XX integrates the differential voltage between the VIN+ and VIN– inputs. The differential voltage must be within the device’s Common mode range VCMR. The input signal polarity is normally checked via software at the end of this phase: CMPTR = 1 for positive polarity; CMPTR = 0 for negative polarity. This phase ensures the integrator output is at 0V when the auto-zero phase is entered, and that only system offset voltages are compensated. This phase is used at the end of the reference voltage de-integration phase and MUST be used for ALL TC5XX applications having resolutions of 12-bits or more. If this phase is not used, the value of the auto-zero capacitor (CAZ) must be about 2 to 3 times the value of the integration capacitor (CINT) to reduce the effects of charge sharing. The integrator output zero phase should be programmed to operate until the output of the comparator returns high. The overall timing system is shown in Figure 5-1. © 2006 Microchip Technology Inc. DS21428D-page 9 TC500/A/510/514 TTIME Converter Status Auto-zero Integrate Full-scale Input Reference De-integrate Overshoot Integrator Output Zero Integrator 0 Voltage VINT Comparator Delay Comparator Output Undefined 0 For Negative Input 1 For Positive Input A A=0 AB Inputs B=1 B A=1 A=1 A=0 B=0 B=1 B=0 Controller Operation Begin Conversion with Auto-Zero Phase Time Input Integration Phase Sample Input Polarity Capture De-integration Time Integrator Ready for Next Output Conversion Zero Phase (Auto-Zero is Complete Idle State) Typically = TINT (Positive Input Shown) TINT Comparator Delay + Processor Latency Minimizing Overshoot will Minimize I.O.Z. Time Notes: The length of this phase is chosen almost arbitrarily but needs to be long enough to null out worst case errors (see text). FIGURE 5-1: Typical Dual Slope A/D Converter System Timing. DS21428D-page 10 © 2006 Microchip Technology Inc. TC500/A/510/514 6.0 6.1 ANALOG SECTION Differential Inputs (VIN+, VIN–) The difference in reference for (+) or (-) input voltages will cause a rollover error. This error can be minimized by using a large reference capacitor in comparison to the stray capacitance. The TC5XX operates with differential voltages within the input amplifier Common mode range. The amplifier Common mode range extends from 1.5V below positive supply to 1.5V above negative supply. Within this Common mode voltage range, Common mode rejection is typically 80 dB. Full accuracy is maintained, however, when the inputs are no less than 1.5V from either supply. The integrator output also follows the Common mode voltage. The integrator output must not be allowed to saturate. A worst-case condition exists, for example, when a large, positive Common mode voltage, with a near full-scale negative differential input voltage, is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced. The integrator output can swing within 0.9V of either supply without loss of linearity. 6.4 Phase Control Inputs (A, B) The A, B unlatched logic inputs select the TC5XX operating phase. The A, B inputs are normally driven by a microprocessor I/O port or external logic. 6.5 Comparator Output By monitoring the comparator output during the fixed signal integrate time, the input signal polarity can be determined by the microprocessor controlling the conversion. The comparator output is high for positive signals and low for negative signals during the signal integrate phase (see Figure 6-1). During the reference de-integrate phase, the comparator output will make a high-to-low transition as the integrator output ramp crosses zero. The transition is used to signal the processor that the conversion is complete. The internal comparator delay is 2 μsec, typically. Figure 6-1 shows the comparator output for large positive and negative signal inputs. For signal inputs at or near zero volts, however, the integrator swing is very small. If Common mode noise is present, the comparator can switch several times during the beginning of the signal integrate period. To ensure that the polarity reading is correct, the comparator output should be read and stored at the end of the signal integrate phase. The comparator output is undefined during the autozero phase and is used to time the integrator output zero phase. (See Section 8.6 “Integrator Output Zero Phase”). 6.2 Analog Common Analog common is used as VIN return during system zero and reference de-integrate. If VIN– is different from analog common, a Common mode voltage exists in the system. This signal is rejected by the excellent CMR of the converter. In most applications, VIN– will be set at a fixed known voltage (i.e., power supply common). A Common mode voltage will exist when VIN– is not connected to analog common. 6.3 Differential Reference (VREF+, VREF–) The reference voltage can be anywhere within 1V of the power supply voltage of the converter. Rollover error is caused by the reference capacitor losing or gaining charge due to stray capacitance on its nodes. Signal Integrate Integrator Output Reference Deintegrate Zero Crossing Signal Integrate Reference De-integrate Integrator Output Comparator Output Zero Crossing Comparator Output A. Positive Input Signal B. Negative Input Signal FIGURE 6-1: Comparator Output. © 2006 Microchip Technology Inc. DS21428D-page 11 TC500/A/510/514 7.0 7.1 TYPICAL APPLICATIONS Component Value Selection TABLE 7-1: Conversions Per Second >7 2 to 7 2 or less CREF AND CAZ SELECTION Typical Value of CREF, CAZ (μF) 0.1 0.22 0.47 Suggested* Part Number SMR5 104K50J01L4 SMR5 224K50J02L4 SMR5 474K50J04L4 The procedure outlined below allows the user to arrive at values for the following TC5XX design variables: 1. 2. 3. 4. Integration Phase Timing. Integrator Timing Components (RINT, CINT). Auto-zero and Reference Capacitors. Voltage Reference. * Manufactured by Evox Rifa, Inc. 7.6 Calculate Integrating Capacitor (CINT) 7.2 Select Integration Time Integration time must be picked as a multiple of the period of the line frequency. For example, TINT times of 33 msec, 66 msec and 132 msec maximize 60 Hz line rejection. 7.3 DINT and IZ Phase Timing The integrating capacitor must be selected to maximize integrator output voltage swing. The integrator output voltage swing is defined as the absolute value of VDD (or VSS) less 0.9V (i.e., IVDD - 0.9VI or IVSS + 0.9VI). Using the 20 μA buffer maximum output current, the value of the integrating capacitor is calculated using the following equation. The duration of the DINT phase is a function of the amount of voltage stored on the integrator during TINT and the value of VREF. The DINT phase must be initiated immediately following INT and terminated when an integrator output zero-crossing is detected. In general, the maximum number of counts chosen for DINT is twice that of INT (with VREF chosen at VIN(MAX) /2). EQUATION 7-2: ( T INT ) ( 20 × 10 ) C INT = -------------------------------------------( VS – 0.9 ) Where: TINT = Integration Period VS = IVDDI or IVSSI, whichever is less (TC500/A) VS = IVDDI (TC510, TC514) It is critical that the integrating capacitor has a very low dielectric absorption. Polypropylene capacitors are an example of one such dialectic. Polyester and polybicarbonate capacitors may also be used in less critical applications. Table 7-2 summarizes recommended capacitors for CINT. –6 7.4 Calculate Integrating Resistor (RINT) The desired full-scale input voltage and amplifier output current capability determine the value of RINT. The buffer and integrator amplifiers each have a full-scale current of 20 μA. The value of RINT is, therefore, directly calculated in the following equation: TABLE 7-2: EQUATION 7-1: VIN ( MAX ) RINT ( in M Ω ) = ---------------------20 Where: VIN(MAX) = Maximum input voltage (full count voltage) RINT = Integrating Resistor (in MΩ) For loop stability, RINT should be ≥ 50 kΩ. Value 0.1 0.22 0.33 0.47 RECOMMENDED CAPACITOR FOR CINT Suggested Part Number* SMR5 104K50J01L4 SMR5 224K50J02L4 SMR5 334K50J03L4 SMR5 474K50J04L4 * Manufactured by Evox Rifa, Inc. 7.5 Select Reference (CREF) and Autozero (CAZ) Capacitors 7.7 Calculate VREF CREF and CAZ must be low leakage capacitors (such as polypropylene). The slower the conversion rate, the larger the value CREF must be. Recommended capacitors for CREF and CAZ are shown in Table 7-1. Larger values for CAZ and CREF may also be used to limit rollover errors. The reference de-integration voltage is calculated using the following equation: EQUATION 7-3: ( V S – 0.9 ) ( C INT ) ( RINT ) V REF = ---------------------------------------------------------- V 2 ( R INT ) DS21428D-page 12 © 2006 Microchip Technology Inc. TC500/A/510/514 8.0 8.1 DESIGN CONSIDERATIONS Noise 8.4 Input Signal Integrate Phase The threshold noise (NTH) is the algebraic sum of the integrator and comparator noise and is typically 30 μV. Figure 8-1 illustrates how the value of the reference voltage can affect the final count. Such errors can be reduced by increased integration times, in the same way that 50/60 Hz noise is rejected. The signal-tonoise ratio is related to the integration time (TINT) and the integration time constant (RINT, CINT) as follows: EQUATION 8-1: tINT ⎛ V IN ⎞ S/N (dB) = 20 log ⎜ ---------------------- • -------------------------------------- ⎟ –6 ( R ⎝ 30 × 10 INT ) • ( C INT )⎠ The length of this phase is constant from one conversion to the next and depends on system parameters and component value selections. The calculation of TINT is shown elsewhere in this data sheet. At some point near the end of this phase, the microcontroller should sample CMPTR to determine the input signal polarity. This value is, in effect, the Sign Bit for the overall conversion result. Optimally, CMPTR should be sampled just before this phase is terminated by changing AB from 10 to 11. The consideration here is that, during the initial stage of input integration when the integrator voltage is low, the comparator may be affected by noise and its output unreliable. Once integration is well underway, the comparator will be in a defined state. 8.2 System Timing 8.5 Reference De-integration To obtain maximum performance from the TC5XX, the overshoot at the end of the de-integration phase must be minimized. Also, the integrator output zero phase must be terminated as soon as the comparator output returns high (see Figure 5-1). Figure 5-1 shows the overall timing for a typical system in which a TC5XX is interfaced to a microcontroller. The microcontroller drives the A, B inputs with I/O lines and monitors the comparator output (CMPTR) using an I/O line or dedicated timer capture control pin. It may be necessary to monitor the state of the CMPTR output in addition to having it control a timer directly for the Reference de-integration phase (this is further explained below.) The timing diagram in Figure 5-1 is not to scale, as the timing in a real system depends on many system parameters and component value selections. There are four critical timing events (as shown in Figure 5-1): sampling the input polarity, capturing the de-integration time, minimizing overshoot and properly executing the integrator output zero phase. The length of this phase must be precisely measured from the transition of AB from 10 to 11 to the fallingedge of CMPTR. The comparator delay contributes some error in timing this phase. The typical delay is specified to be 2 μsec. This should be considered in the context of the length of a single count when determining overall system performance and possible single count errors. Additionally, overshoot will result in charge accumulating on the integrator once its output crosses zero. This charge must be nulled during the integrator output zero phase. 8.3 Auto-zero Phase The length of this phase is usually set to be equal to the input signal integration time. This decision is virtually arbitrary since the magnitudes of the various system errors are not known. Setting the auto-zero time equal to the Input Integrate time should be more than adequate to null out system errors. The system may remain in this phase indefinitely (i.e., auto-zero is the appropriate Idle state for a TC5XX device). © 2006 Microchip Technology Inc. DS21428D-page 13 TC500/A/510/514 S S 30V S NTH Low VREF NTH Normal VREF VREF N = Noise Threshold RINT CINT TH NTH High VREF Slope (S) = FIGURE 8-1: Noise Threshold. 8.6 Integrator Output Zero Phase 8.7 8.7.1 Using the TC510/TC514 NEGATIVE SUPPLY VOLTAGE CONVERTER (TC510, TC514) The comparator delay and the controller’s response latency may result in overshoot, causing charge buildup on the integrator at the end of a conversion. This charge must be removed or performance will degrade. The integrator output zero phase should be activated (AB = 00) until CMPTR goes high. It is absolutely critical that this phase be terminated immediately so that overshoot is not allowed to occur in the opposite direction. At this point, it can be assured that the integrator is near zero. Auto-zero should be entered (AB = 01) and the TC5XX held in this state until the next cycle is begun (see Figure 8-2). A capacitive charge pump is employed to invert the voltage on VDD for negative bias within the TC510/ TC514. This voltage is also available on the VOUT- pin to provide negative bias elsewhere in the system. Two external capacitors are required to perform the conversion. Timing is generated by an internal state machine driven from an on-board oscillator. During the first phase, capacitor CF is switched across the power supply and charged to VS+. This charge is transferred to capacitor COUT- during the second phase. The oscillator normally runs at 100 kHz to ensure minimum output ripple. This frequency can be reduced by placing a capacitor from OSC to VDD. The relationship between the capacitor value is shown in Section 2.0 “Typical Performance Curves”. Integrator Output Zero Crossing Overshoot Comparator Output Comp Integrate Phase De-integrate Phase Integrator Zero Phase 8.7.2 ANALOG INPUT MULTIPLEXER (TC514) The TC514 is equipped with a four-input differential analog multiplexer. Input channels are selected using select inputs (A1, A0). These are high-true control signals (i.e., channel 0 is selected when (A1, A0 = 00). FIGURE 8-2: Overshoot. DS21428D-page 14 © 2006 Microchip Technology Inc. TC500/A/510/514 9.0 Given: DESIGN EXAMPLES Required Resolution: 16 bits (65,536 counts). Maximum VIN: ±2V Power Supply Voltage: +5V 60 Hz System Refer to Figures 9-1 to 9-4. Step 1. Pick integration time (tINT) as a multiple of the line frequency: 1/60 Hz = 16.6 msec. Use 4x line frequency. = 66 msec Step 2. Calculate RINT: RINT = VIN(MAX) /20 μA 2 /20 μA = 100 kΩ Step 3. Calculate CINT for maximum (4V) integrator output swing. CINT = (tINT) (20 x 10 –6) / (VS - 0.9) = (.066) (20 x 10 –6) / (4.1) = 0.32 μF (use closest value: 0.33 μF) Note: Step 4. Microchip recommended capacitor: Evox Rifa p/n: 5MR5 334K50J03L4. Choose CREF and CAZ based on conversion rate. Conversions/sec: = 1/(TAZ + TINT + 2 TINT + 2 msec) = 1/(66 msec +66 msec +132 msec +2 msec) = 3.7 conversions/sec From which CAZ = CREF = 0.22 μF (see Table 7-1) Note: Step 5. Microchip recommended capacitor: Evox Rifa p/n: 5MR5 224K50J02L4 Calculate VREF: EQUATION 9-1: ( V S – 0.9 ) ( C INT ) ( RINT ) V REF = ---------------------------------------------------------2 ( T INT ) = ( 4.1 ) ( 0.33 × 1 ) ( 10 ) ------------------------------------------------------------2 ( 0.66 ) = 1.025 –6 5 © 2006 Microchip Technology Inc. DS21428D-page 15 TC500/A/510/514 1 VOUTCINT 0.33 μF 2 CINT CAZ 0.22 μF 3 CAZ 4 RINT 100 kΩ CREF R2 0.22 μF 10 kΩ R3, 10 kΩ C1 0.01 μF 5 6 7 BUF ACOM CREFCREF+ CMPTR A B VIN+ 19 18 17 16 INPUT+ INPUTVINPin 19 Pin 2 CAPDGND 24 23 22 21 +5V PICmicro Microcontroller ® 1 μF 1 μF +5V Typical Waveforms Pin 2 VIN+ Pin 19 TC510 CAP+ VDD +5V MCP1525 1 μF 9V REF+ 8 VREF- VIN- 15 FIGURE 9-1: TC510 Design Sample. 1 1 μF CINT 0.33 μF CAZ 0.22 μF 28 27 26 25 22 19 23 22 21 18 13 17 12 16 INPUT 3+ 11 15 10 INPUT 3INPUT4+ INPUT4PIN 2 VINPIN 23 PIN 23 INPUT 1+ INPUT 1Typical Waveforms CH2+ CH2CH3+ CH3CH4+ CH4INPUT 2+ INPUT 2VIN+ PIN 2 Analog Mux Logic +5V PICmicro® Microcontroller VOUT- CAPDGND 2C INT 3 4 1 μF +5V CAZ BUF CAP+ +5V TC514 VDD A0 RINT 100 kΩ CREF R2 0.22 μF 10 kΩ R3, 10 kΩ C1 0.01 μF 5 6 7 ACOM CREFCREF+ A1 CMPTR A B CH1+ CH1- MCP1525 1 μF 9V REF+ 8 VREF- FIGURE 9-2: TC514 Design Example. DS21428D-page 16 © 2006 Microchip Technology Inc. TC500/A/510/514 +5V 21 VDD 1 VOUT1 μF 1 μF CAP- 24 CAP+ 22 7 CREF+ CREF- 6 VREF+ 9 0.22 μF 10 kΩ MCP1525 10 kΩ 1 μF TC510 VREFPC Printer Port PORT 0378 Hex BUF 2 3 10 18 17 A B 8 0.01 μF 4 100 kΩ 0.22 μF CAZ 3 CINT 2 VIN+ 16 VIN- 15 ACOM 5 0.33 μF 100 kΩ + 0.01 μF Input – 19 CMPTR DGND 23 FIGURE 9-3: TC510 To IBM® Compatible Printer Port. © 2006 Microchip Technology Inc. DS21428D-page 17 TC500/A/510/514 +5V 18 13 17 25 1 28 CH1+ VDD VOUT CAP– CH1– CH2+ CREF+ 7 CREF- 6 VREF+ 9 0.22 μF 10 kΩ CAP+ 26 1 μF 1 μF 10 kΩ + Input 1 – + Input 2 – + Input 3 – + Input 4 – Analog Mux Control Logic IBM® Printer Port 2 Port 0378 Hex 3 10 12 CH2– 16 CH3+ 11 15 CH3– CH4+ MCP1525 10 CH4– 20 19 22 21 23 A0 A1 A B CMPTR TC514 VREF- 0.01 μF 8 10 kΩ BUF 4 CAZ 3 100 kΩ 0.22 μF CINT 2 0.33 μF ACOM DGND 27 5 FIGURE 9-4: TC514 To IBM® Compatible Printer Port. DS21428D-page 18 © 2006 Microchip Technology Inc. TC500/A/510/514 10.0 10.1 PACKAGING INFORMATION Package Marking Information 16-Lead CERDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC500AIJE 0441256 16-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC500CPE 0441256 16-Lead SOIC (300 mil) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN TC500ACOE 0441256 Legend: XX...X YY WW NNN Customer specific information* Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line thus limiting the number of available characters for customer specific information. * Standard marking consists of Microchip part number, year code, week code, traceability code. For marking beyond this, certain price adders apply. Please check with your Microchip Sales Office. © 2006 Microchip Technology Inc. DS21428D-page 19 TC500/A/510/514 Package Marking Information (Continued) 24-Lead PDIP (300 mil) Example: XXXXXXXXXXXXX YYWWNNN TC510CPF 0441256 24-Lead SOIC (300 mil) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN TC510COG 0441256 28-Lead PDIP (300 mil) Example: XXXXXXXXXXXXXX XXXXXXXXXXXXXX YYWWNNN TC514CPJ 0441256 28-Lead SOIC (300 mil) Example: XXXXXXXXXXXXX XXXXXXXXXXXXX XXXXXXXXXXXXX YYWWNNN TC514COI 0441256 DS21428D-page 20 © 2006 Microchip Technology Inc. TC500/A/510/514 16-Lead Ceramic Dual In-line (JE) – 300 mil (CERDIP) E1 D 2 n 1 E A2 A c A1 eB B Units Dimension Limits n p A A1 E E1 D L c B1 B eB INCHES* NOM 18 .100 .180 .030 .305 .288 .760 .163 .012 .055 .018 .360 L B1 p MILLIMETERS NOM 18 2.54 4.06 4.57 0.38 0.76 7.37 7.75 7.11 7.32 19.10 19.30 4.14 3.18 0.20 0.30 1.14 1.40 0.38 0.46 8.25 9.14 MIN MAX MIN MAX Number of Pins Pitch Top to Seating Plane Standoff § Shoulder to Shoulder Width Ceramic Pkg. Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing *Controlling Parameter JEDEC Equivalent: MS-030 Drawing No. C04-003 .160 .015 .290 .280 .752 .125 .008 .045 .015 .325 .200 .040 .325 .296 .780 .200 .014 .065 .021 .410 5.08 1.02 8.25 7.52 19.81 5.08 0.36 1.65 0.53 10.41 © 2006 Microchip Technology Inc. DS21428D-page 21 TC500/A/510/514 16-Lead Plastic Dual In-line (PE) – 300 mil (PDIP) E1 D 2 α n 1 E A2 A c β eB A1 L B1 B p Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom n p A A2 A1 E E1 D L c B1 B eB α β .140 .115 .015 .300 .240 .740 .125 .008 .045 .014 .310 5 5 MIN INCHES* NOM 16 .100 .155 .130 .313 .250 .750 .130 .012 .058 .018 .370 10 10 .170 .145 .325 .260 .760 .135 .015 .070 .022 .430 15 15 3.56 2.92 0.38 7.62 6.10 18.80 3.18 0.20 1.14 .036 7.87 MAX MIN MILLIMETERS NOM 16 2.54 3.94 3.30 7.94 6.35 19.05 3.30 0.29 1.46 0.46 9.40 5 5 10 10 4.32 3.68 8.26 6.60 19.30 3.43 0.38 1.78 0.56 10.92 15 15 MAX * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 Drawing No. C04-017 Revised 07-21-05 DS21428D-page 22 © 2006 Microchip Technology Inc. TC500/A/510/514 16-Lead Plastic Small Outline (OE) – Wide, 300 mil (SOIC) E p E1 D 2 n B h 1 α 45 ° c A A2 β Units Dimension Limits n p φ L A1 INCHES* NOM 16 .050 .099 .091 .008 .407 .295 .406 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 16 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.39 7.49 10.10 10.30 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 MAX Number of Pins Pitch Overall Height A .093 .104 2.64 Molded Package Thickness A2 .088 .094 2.39 Standoff § .004 .012 0.30 A1 Overall Width E .394 .420 10.67 Molded Package Width E1 .291 .299 7.59 Overall Length D .398 .413 10.49 Chamfer Distance h .010 .029 0.74 Foot Length L .016 .050 1.27 φ Foot Angle 0 8 8 c Lead Thickness .009 .013 0.33 Lead Width B .014 .020 0.51 α Mold Draft Angle Top 0 15 15 β Mold Draft Angle Bottom 0 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-102 MIN MAX MIN © 2006 Microchip Technology Inc. DS21428D-page 23 TC500/A/510/514 24-Lead Skinny Plastic Dual In-line (PF) – 300 mil (PDIP) E1 D 2 n 1 E A c A1 β eB Units Dimension Limits Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top Mold Draft Angle Bottom n p A A2 A1 E E1 D L c B1 B eB α β .140 .115 .015 .295 .240 1.245 .120 .008 .045 .014 .310 5 5 .310 .250 1.250 .125 .012 .053 .018 .370 10 10 .325 .260 1.255 .130 .015 .060 .022 .430 15 15 MIN B1 B INCHES* NOM 24 .100 .150 .130 .160 .145 3.56 2.92 0.38 7.49 6.10 31.62 3.05 0.20 1.14 0.36 7.87 5 5 7.87 6.35 31.75 3.18 0.29 1.33 0.46 9.40 10 10 8.26 6.60 31.88 3.30 0.38 1.52 0.56 10.92 15 15 MAX MIN MILLIMETERS NOM 24 2.54 3.81 3.30 4.06 3.68 MAX p A2 L α * Controlling Parameter Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. JEDEC Equivalent: MS-001 AF Drawing No. C04-043 Revised 09-14-05 DS21428D-page 24 © 2006 Microchip Technology Inc. TC500/A/510/514 24-Lead Plastic Small Outline (OG) – Wide, 300 mil (SOIC) E E1 e D B 2 n 1 α h c h A φ β L A1 A2 Units Dimension Limits Number of Pins Pitch Overall Height Molded Package Thickness Standoff Overall Width Molded Package Width Overall Length Chamfer Distance Foot Length Foot Angle Lead Thickness Lead Width Mold Draft Angle Top Mold Draft Angle Bottom n e A A2 A1 E E1 D h L φ c B α β .010 .016 0° .008 .012 5° 5° .093 .081 .004 MIN INCHES NOM 24 .050 BSC ---.406 BSC .295 BSC .607 BSC -------.030 .050 8° .013 .020 15° 15° 0.25 0.40 .104 .100 .012 2.35 2.05 0.10 MAX MIN MILLIMETERS* NOM 24 1.27 BSC ---10.30 BSC 7.50 BSC 15.40 BSC -------0.75 1.27 8° 0.33 0.51 15° 15° 2.65 2.55 0.30 MAX 0° 0.20 0.31 5° 5° * Controlling Parameter per JEDEC MS-103 Revision C. Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" (0.254mm) per side. BSC: Basic Dimension. Theoretically exact value shown without tolerances. See ASME Y14.5M JEDEC Equivalent: MS-013 AD Revised 07-19-05 Drawing No. C04-025 © 2006 Microchip Technology Inc. DS21428D-page 25 TC500/A/510/514 28-Lead Skinny Plastic Dual In-line (PJ) – 300 mil (PDIP) E1 D 2 n 1 α E A2 A L A1 B1 B p c β eB Units Number of Pins Pitch Top to Seating Plane Molded Package Thickness Base to Seating Plane Shoulder to Shoulder Width Molded Package Width Overall Length Tip to Seating Plane Lead Thickness Upper Lead Width Lower Lead Width Overall Row Spacing Mold Draft Angle Top § Dimension Limits n p A A2 A1 E E1 D L c B1 B eB α MIN INCHES* NOM 28 .100 .140 .125 .015 .300 .275 1.345 .125 .008 .040 .016 .320 .310 .285 1.365 .130 .012 .053 .019 .350 .325 .295 1.385 .135 .015 .065 .022 .430 .150 .130 .160 .135 MAX MIN MILLIMETERS NOM 28 2.54 3.56 3.18 0.38 7.62 6.99 34.16 3.18 0.20 1.02 0.41 8.13 7.87 7.24 34.67 3.30 0.29 1.33 0.48 8.89 8.26 7.49 35.18 3.43 0.38 1.65 0.56 10.92 3.81 3.30 4.06 3.43 MAX 5 10 15 5 10 15 β Mold Draft Angle Bottom 5 10 15 5 10 15 * Controlling Parameter § Significant Characteristic Notes: Dimension D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MO-095 Drawing No. C04-070 DS21428D-page 26 © 2006 Microchip Technology Inc. TC500/A/510/514 28-Lead Plastic Small Outline (OI) – Wide, 300 mil (SOIC) E E1 p D B n h 45° c A φ β Units Dimension Limits n p L A1 INCHES* NOM 28 .050 .099 .091 .008 .407 .295 .704 .020 .033 4 .011 .017 12 12 MILLIMETERS NOM 28 1.27 2.36 2.50 2.24 2.31 0.10 0.20 10.01 10.34 7.32 7.49 17.65 17.87 0.25 0.50 0.41 0.84 0 4 0.23 0.28 0.36 0.42 0 12 0 12 A2 2 1 α MAX Number of Pins Pitch Overall Height A .093 .104 2.64 Molded Package Thickness A2 .088 .094 2.39 Standoff § A1 .004 .012 0.30 Overall Width E .394 .420 10.67 Molded Package Width E1 .288 .299 7.59 Overall Length D .695 .712 18.08 Chamfer Distance h .010 .029 0.74 Foot Length L .016 .050 1.27 φ Foot Angle Top 0 8 8 c Lead Thickness .009 .013 0.33 Lead Width B .014 .020 0.51 α Mold Draft Angle Top 0 15 15 β Mold Draft Angle Bottom 0 15 15 * Controlling Parameter § Significant Characteristic Notes: Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010” (0.254mm) per side. JEDEC Equivalent: MS-013 Drawing No. C04-052 MIN MAX MIN © 2006 Microchip Technology Inc. DS21428D-page 27 TC500/A/510/514 10.2 Product Tape and Reel Specifications Component Taping Orientation for 16-Pin SOIC (Wide) Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 16-Pin SOIC (W) 16 mm 12 mm 1000 13 in Component Taping Orientation for 24-Pin SOIC (Wide) Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 24-Pin SOIC (W) 24 mm 12 mm 1000 13 in DS21428D-page 28 © 2006 Microchip Technology Inc. TC500/A/510/514 Product Tape and Reel Specifications (Continued) Component Taping Orientation for 28-Pin SOIC (Wide) Devices User Direction of Feed Pin 1 W P Standard Reel Component Orientation for 713 Suffix Device Carrier Tape, Number of Components Per Reel and Reel Size Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 28-Pin SOIC (W) 24 mm 12 mm 1000 13 in © 2006 Microchip Technology Inc. DS21428D-page 29 TC500/A/510/514 NOTES: DS21428D-page 30 © 2006 Microchip Technology Inc. TC500/A/510/514 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PART NO. Device X Temperature Range /XX Package Examples: a) b) Device TC500 TC500A TC510 TC514 16 Bit Analog Processor 16 Bit Analog Processor Precision Analog Front End Precision Analog Front End TC500ACOE: TC500ACOE713: Commercial Temp., 16LD SOIC package. Commercial Temp., 16LD SOIC package, Tape and Reel. Commercial Temp., 16LD PDIP package. Industrial Temp., 16LD CERDIP package. Commercial Temp., 16LD SOIC package. Commercial Temp., 16LD SOIC package, Tape and Reel. Commercial Temp., 16LD PDIP package. Industrial Temp., 16LD CERDIP package. Commercial Temp., 24LD PDIP package. Commercial Temp., 24LD PDIP package, Tape and Reel. Commercial Temp., 24LD PDIP package. Commercial Temp., 28LD PDIP package. Commercial Temp., 28LD PDIP package, Tape and Reel. Commercial Temp., 28LD PDIP package. c) d) a) TC500ACPE: TC500AIJE: TC500COE: TC500COE713: Temperature Range C I = = 0°C to +70°C (Commercial) -25°C to +85°C (Industrial) b) Package: JE PE OE OE713 PF OG OG713 PJ OI OI713 = = = = = = = = = = Ceramic Dual In-line, (300 mil Body), 16-lead Plastic DIP, (300 mil Body), 16-lead Plastic SOIC, (300 mil Body), 16-lead Plastic SOIC, (300 mil Body), 16-lead (Tape and Reel) Plastic DIP, (300 mil Body), 24-lead Plastic SOIC, (300 mil Body), 24-lead Plastic SOIC, (300 mil Body), 24-lead (Tape and Reel) Plastic DIP, (300 mil Body), 28-lead Plastic SOIC, (300 mil Body), 28-lead Plastic SOIC, (300 mil Body), 28-lead (Tape and Reel) c) d) a) b) TC500CPE: TC500IJE: TC510COG: TC510COG713: c) a) b) TC510CPF: TC514COI: TC514COI713: c) TC514CPJ: Sales and Support Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. © 2006 Microchip Technology Inc. DS21428D-page 31 TC500/A/510/514 NOTES: DS21428D-page 32 © 2006 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices: • • Microchip products meet the specification contained in their particular Microchip Data Sheet. Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. Microchip is willing to work with the customer who is concerned about the integrity of their code. Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” • • • Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, Real ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and Zena are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2006, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October 2003. The Company’s quality system processes and procedures are for its PICmicro® 8-bit MCUs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. © 2006 Microchip Technology Inc. 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