TC7135CPI

TC7135 4-1/2 Digit A/D Converter Features • • • • • • • • • • • • • Low Rollover Error: ±1 Count Max Nonlinearity Error: ±1 Count Max Reading for 0V Input True Polarity Indication at Zero for Null Detection Multiplexed BCD Data Output TTL-Compatible Outputs Differential Input Control Signals Permit Interface to UARTs and Microprocessors Blinking Display Visually Indicates Overrange Condition Low Input Current: 1pA Low Zero Reading Drift: 2µV/°C Auto-Ranging Supported with Overrange and Underrange Signals Available in PDIP and Surface-Mount Packages General Description The TC7135 4-1/2 digit A/D converter (ADC) offers 50ppm (1 part in 20,000) resolution with a maximum nonlinearity error of 1 count. An auto zero cycle reduces zero error to below 10µV and zero drift to 0.5µV/°C. Source impedance errors are minimized by a 10pA maximum input current. Rollover error is limited to ±1 count. Microprocessor based measurement systems are supported by BUSY, STROBE and RUN/HOLD control signals. Remote data acquisition systems with data transfer via UARTs are also possible. The additional control pins and multiplexed BCD outputs make the TC7135 the ideal converter for display or microprocessor based measurement systems. Functional Block Diagram SET VREF = 1V VREF IN 100k Ω –5V 1 2 V- TC7135 UNDERRANGE 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Clock Input 120kHz Applications • Precision Analog Signal Processor • Precision Sensor Interface • High Accuracy DC Measurements Device Selection Table Part Number TC7135CLI TC7135CPI TC7135CBU Package 28-Pin PLCC 28-Pin PDIP 64-Pin PQFP Temperature Range 0°C to +70°C 0°C to +70°C 0°C to +70°C REF IN OVERRANGE 3 ANALOG STROBE COMMON Analog GND 4 RUN/HOLD INT OUT 1µF 0.47µF 5 DIGTAL GND AZ IN 6 BUFF OUT POLARITY 100k Ω 7 CLOCK IN C 100 Signal 1µF 8 REF kΩ BUSY Input CREF+ 9 -INPUT (LSD) D1 0.1µF 10 D2 +INPUT 11 D3 +5V V+ 12 D5 (MSD) D4 13 B1 (LSB) (MSB) B8 14 B2 B4 2002 Microchip Technology Inc. DS21460B-page 1 © TC7135 Package Types 28-Pin PDIP INT OUT ANALOG COM REF IN STROBE VREF IN ANALOG COM INT OUT 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY AZ IN BUFF OUT C REFCREF+ – INPUT 1 2 3 4 5 6 7 8 9 28-Pin PDIP 28 UNDERRANGE 27 OVERRANGE V– OR UR 26 STROBE 25 RUN/HOLD 24 DIGTAL GND 23 POLARITY 4 AZ IN 5 BUFF OUT 6 REF CAP– 7 REF CAP+ 8 –INPUT 9 +INPUT 10 V + 11 3 2 1 28 27 26 TC7135 22 CLOCK IN 21 BUSY 20 D1 (LSD) 19 D2 TC7135 22 CLOCK IN 21 BUSY 20 19 18 D1 (LSD) D2 D3 +INPUT 10 V+ 11 (MSD) D5 12 (LSB) B1 13 B2 14 12 13 14 15 16 17 18 D4 (MSD) D5 (MSB) B8 (LSB) B1 D3 B2 B4 17 D4 16 B8 (MSB) 15 B4 64-Pin PQFP RUN/HOLD CLOCK IN STROBE DGND POL BUSY NC NC NC NC NC NC NC NC 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 OVERRANGE 7 UNDERRANGE 8 NC 9 V- 10 REF IN 11 ANALOG COM 12 NC 13 NC 14 NC 15 NC 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 l 48 NC 47 NC 46 NC 45 D3 44 D4 43 B8 42 B4 TC7135 NC 41 B2 40 NC 39 B1 38 D5 37 NC 36 NC 35 NC 34 NC 33 NC D1 –INPUT BUFF OUT D2 +INPUT INT OUT AZ IN NC NC NC NC NC NC NOTE: NC = No internal connection. © DS21460B-page 2 C REF + C REF - NC V+ 2002 Microchip Technology Inc. TC7135 1.0 ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings* Positive Supply Voltage..........................................+6V Negative Supply Voltage ....................................... - 9V Analog Input Voltage (Pin 9 or 10) .... V+ to V- (Note 2) Reference Input Voltage (Pin 2) ...................... V+ to VClock Input Voltage ........................................ 0V to V+ Operating Temperature Range ............... 0°C to +70°C Storage Temperature Range ............ – 65°C to +150°C Package Power Dissipation; (TA ≤ 70°C) 28-Pin PDIP ..................................... 1.14Ω 28-Pin PLCC .................................... 1.00Ω 64-Pin PQFP .....................................1.14Ω *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. TC7135 ELECTRICAL SPECIFICATIONS Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Parameter Min Typ Max Unit Test Conditions Analog Display Reading with Zero Volt Input TC Z TC FS NL DNL ±FSE IIN eN Digital IIL IIH VOL V OH Input Low Current Input High Current Output Low Voltage Output High Voltage; B1, B2, B4, B8, D 1 –D5 Busy, Polarity, Overrange, Underrange, Strobe Clock Frequency — — — 2.4 4.9 10 0.08 0.2 4.4 4.99 100 10 0.4 5 5 Zero Reading Temperature Coefficient Full Scale Temperature Coefficient Nonlinearity Error Differential Linearity Error Display Reading in Ratiometric Operation ± Full Scale Symmetry Error (Rollover Error) Input Leakage Current Noise -0.0000 — — — — +0.9996 — — — ±0.0000 0.5 — 0.5 0.01 +0.9999 0.5 1 15 +0.0000 2 5 1 — +1.0000 1 10 — Display Reading Note 2 and Note 3 VIN = 0V, (Note 4) VIN = 2V, (Note 4 and Note 5) Note 6 Note 6 VIN = VREF, (Note 2) -VIN = +VIN, (Note 7) Note 3 Peak-to-Peak Value not Exceeded 95% of Time VIN = 0V VIN = +5V IOL = 1.6mA IOH = 1mA IOH = 10µA µV/°C ppm/°C Count LSB Display Reading Count pA µVP-P µA µA V V V FCLK Note 1: 2: 3: 4: 5: 6: 7: 8: 0 200 1200 kHz Note 8 Limit input current to under 100µA if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30°C ≤ TA ≤ +70°C .External reference temperature coefficient less than 0.01ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. 2002 Microchip Technology Inc. DS21460B-page 3 © TC7135 TC7135 ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: TA = +25°C, FCLOCK = 120kHz, V+ = +5V, V- = -5V, unless otherwise specified (see Functional Block Diagram). Symbol Power Supply V+ VI+ IPD Note 1: 2: 3: 4: 5: 6: 7: 8: Positive Supply Voltage Negative Supply Voltage Positive Supply Current Negative Supply Current Power Dissipation 4 -3 — — — 5 -5 1 0.7 8.5 6 -8 3 3 30 V V mA mA mW FCLK = 0Hz FCLK = 0Hz FCLK = 0Hz Parameter Min Typ Max Unit Test Conditions Limit input current to under 100µA if input voltages exceed supply voltage. Full scale voltage = 2V. VIN = 0V. 30°C ≤ TA ≤ +70°C .External reference temperature coefficient less than 0.01ppm/°C. -2V ≤ VIN ≤ +2V. Error of reading from best fit straight line. IVIN| = 1.9959. Specification related to clock frequency range over which the TC7135 correctly performs its various functions. Increased errors result at higher operating frequencies. © DS21460B-page 4 2002 Microchip Technology Inc. TC7135 2.0 PIN DESCRIPTIONS The description of the pins are listed in Table 2-1. TABLE 2-1: Pin Number 28-Pin PDIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 PIN FUNCTION TABLE Symbol VREF IN ANALOG COMMON INT OUT AZ IN BUFF OUT CREFCREF+ -INPUT +INPUT V+ D5 B1 B2 B4 B8 D4 D3 D2 D1 BUSY CLOCK IN POLARITY Negative power supply input. External reference input. Reference point for REF IN. Integrator output. Integrator capacitor connection. Auto zero inpt. Auto-zero capacitor connection. Analog input buffer output. Integrator resistor connection. Reference capacitor input. Reference capacitor negative connection. Reference capacitor input. Reference capacitor positive connection. Analog input. Analog input negative connection. Analog input. Analog input positive connection. Positive power supply input. Digit drive output. Most Significant Digit (MSD) Binary Coded Decimal (BCD) output. Least Significant Bit (LSB) BCD output. BCD output. BCD output. Most Significant Bit (MSB) Digit drive output. Digit drive output. Digit drive output. Digit drive output. Least Significant Digit (LSD) Busy output. At the beginning of the signal-integration phase, BUSY goes High and remains High until the first clock pulse after the integrator zero crossing. Clock input. Conversion clock connection. Polarity output. A positive input is indicated by a logic High output. The polarity output is valid at the beginning of the reference integrate phase and remains valid until determined during the next conversion. Digital logic reference input. Run / Hold input. When at a logic High, conversions are performed continuously. A logic Low holds the current data as long as the Low condition exists. Strobe output. The STROBE output pulses low in the center of the digit drive outputs. Over range output. A logic High indicates that the analog input exceeds the full scale input range. Under range output. A logic High indicates that the analog input is less than 9% of the full scale input range. Description 24 25 26 27 28 DGND RUN/HOLD STROBE OVERRANGE UNDERRANGE 2002 Microchip Technology Inc. DS21460B-page 5 © TC7135 3.0 3.1 DETAILED DESCRIPTION Dual Slope Conversion Principles (All Pin Designations Refer to 28-Pin DIP) ent benefit is noise immunity. Noise spikes are integrated, or averaged, to zero during the integration periods. Integrating ADCs are immune to the large conversion errors that plague successive approximation converters in high-noise environments (see Figure 3-1). The TC7135 is a dual slope, integrating A/D converter. An understanding of the dual slope conversion technique will aid in following the detailed TC7135 operational theory. The conventional dual slope converter measurement cycle has two distinct phases: 1. 2. Input signal integration Reference voltage integration (de-integration) FIGURE 3-1: BASIC DUAL SLOPE CONVERTER Integrator Comparator + Clock Control Logic Counter VIN ≈ VREF VIN ≈ 1/2 VREF Variable Reference Integrate Time Switch Drive Analog Input Signal The input signal being converted is integrated for a fixed time period. Time is measured by counting clock pulses. An opposite polarity constant reference voltage is then integrated until the integrator output voltage returns to zero. The reference integration time is directly proportional to the input signal. In a simple dual slope converter, a complete conversion requires the integrator output to "ramp-up" and "ramp-down." A simple mathematical equation relates the input signal, reference voltage, and integration time: REF Voltage Phase Control Polarity Control Display Integrator Output EQUATION 3-1: TINT VREF T DEINT 1 VIN(T)DT = R C RINTC INT 0 INT INT where: VREF TINT = Reference voltage = Signal integration time (fixed) ∫ Fixed Signal Integrate Time 3.2 TC7135 Operational Theory TDEINT = Reference voltage integration time (variable). For a constant VIN: The TC7135 incorporates a system zero phase and integrator output voltage zero phase to the normal twophase dual-slope measurement cycle. Reduced system errors, fewer calibration steps, and a shorter overrange recovery time result. The TC7135 measurement cycle contains four phases: 1. 2. 3. 4. System zero Analog input signal integration Reference voltage integration Integrator output zero EQUATION 3-2: VIN = VREF TDEINT TINT The dual slope converter accuracy is unrelated to the integrating resistor and capacitor values, as long as they are stable during a measurement cycle. An inher- Internal analog gate status for each phase is shown in Figure 3-1. TABLE 3-1: INTERNAL ANALOG GATE STATUS SWI Closed Closed* Closed Closed Closed SWRI+ SWRISWZ Closed SWR Closed SW1 Closed SWIZ Reference Figures Figure 3-2 Figure 3-3 Figure 3-4 Figure 3-5 Conversion Cycle Phase System Zero Input Signal Integration Reference Voltage Integration Integrator Output Zero *Note: Assumes a positive polarity input signal. SWRI would be closed for a negative input signal. © DS21460B-page 6 + 2002 Microchip Technology Inc. TC7135 3.2.1 SYSTEM ZERO 3.2.3 During this phase, errors due to buffer, integrator, and comparator offset voltages are compensated for by charging CAZ (auto zero capacitor) with a compensating error voltage. With a zero input voltage the integrator output will remain at zero. The external input signal is disconnected from the internal circuitry by opening the two SWI switches. The internal input points connect to ANALOG COMMON. The reference capacitor charges to the reference voltage potential through SWR. A feedback loop, closed around the integrator and comparator, charges the CAZ capacitor with a voltage to compensate for buffer amplifier, integrator, and comparator offset voltages (see Figure 3-2). REFERENCE VOLTAGE INTEGRATION The previously-charged reference capacitor is connected with the proper polarity to ramp the integrator output back to zero (see Figure 3-4). The digital reading displayed is: EQUATION 3-3: Reading = 10,000 [Differential Input] VREF FIGURE 3-4: REFERENCE VOLTAGE INTEGRATION CYCLE Analog Input Buffer + RINT CINT SWI FIGURE 3-2: SWI +IN SWRI- SWRI+ SYSTEM ZERO PHASE Analog Input Buffer + CSZ SWIZ SWZ RINT CINT +IN SWRI- SWRI+ CSZ SWIZ SWZ SWZ SWZ Integrator SWZ SWRI+ SWRI- SWZ Integrator Analog Common SWI – IN SW1 Switch Open Switch Closed 3.2.2 ANALOG INPUT SIGNAL INTEGRATION The TC7135 integrates the differential voltage between the +INPUT and -INPUT pins. The differential voltage must be within the device Common mode range; - 1V from either supply rail, typically. The input signal polarity is determined at the end of this phase. See Figure 2-3 FIGURE 3-3: INPUT SIGNAL INTEGRATION PHASE Analog Input Buffer + RINT CINT SWRI- SWRI+ CSZ SWIZ SWZ SWZ SWRI+ SWRI- SWZ Integrator SWZ SWZ SWRI+ SWRI- Integrator Analog Common SWI – IN SW1 Switch Open Switch Closed . 2002 Microchip Technology Inc. - + REF IN + SWR - CREF Comparator To Digital Section Analog Common SWI – IN SW1 Switch Open Switch Closed DS21460B-page 7 - - + REF IN + +IN - SWI - + REF IN + - SWR CREF Comparator Analog Common SWRI+ SWRI- To Digital Section – IN SWI SW1 Switch Open Switch Closed 3.2.4 INTEGRATOR OUTPUT ZERO This phase ensures the integrator output is at 0V when the system zero phase is entered. It also ensures that the true system offset voltages are compensated for. This phase normally lasts 100 to 200 clock cycles. If an overrange condition exists, the phase is extended to 6200 clock cycles (see Figure 3-5). FIGURE 3-5: INTEGRATOR OUTPUT ZERO PHASE Analog Input Buffer + RINT CINT CSZ SWIZ SWZ SWI + IN SWRI- SWRI+ SWR CREF + + REF IN SWR CREF Comparator To Digital Section Comparator To Digital Section © TC7135 4.0 4.1 ANALOG SECTION FUNCTIONAL DESCRIPTION Differential Inputs FIGURE 4-1: USING AN EXTERNAL REFERENCE V+ The TC7135 operates with differential voltages (+INPUT, pin 10 and -INPUT, pin 9) within the input amplifier Common mode range, which extends from 1V below the positive supply to 1V above the negative supply. Within this Common mode voltage range, an 86dB Common mode rejection ratio is typical. The integrator output also follows the Common mode voltage and must not be allowed to saturate. A worstcase condition exists, for example, when a large positive Common mode voltage with a near full scale negative differential input voltage is applied. The negative input signal drives the integrator positive when most of its swing has been used up by the positive Common mode voltage. For these critical applications, the integrator swing can be reduced to less than the recommended 4V full scale swing, with some loss of accuracy. The integrator output can swing within 0.3V of either supply without loss of linearity. V+ TC7135 REF IN ANALOG COMMON 10k MCP1525 2.5 VREF 1µF 10k Analog Ground 4.2 Analog Common Input ANALOG COMMON is used as the -INPUT return during auto zero and de-integrate. If -INPUT is different from ANALOG COMMON, a Common mode voltage exists in the system. However, this signal is rejected by the excellent CMRR of the converter. In most applications, –INPUT will be set at a fixed, known voltage (power supply common, for instance). In this application, ANALOG COMMON should be tied to the same point, thus removing the Common mode voltage from the converter. The reference voltage is referenced to ANALOG COMMON. 4.3 Reference Voltage Input The reference voltage input (REF IN) must be a positive voltage with respect to ANALOG COMMON. A reference voltage circuit is shown in Figure 4-1. © DS21460B-page 8 2002 Microchip Technology Inc. TC7135 5.0 DIGITAL SECTION FUNCTIONAL DESCRIPTION The major digital subsystems within the TC7135 are illustrated in Figure 5-1, with timing relationships shown in Figure 5-2. The multiplexed BCD output data can be displayed on LCD or LED displays. The digital section is best described through a discussion of the control signals and data outputs. FIGURE 5-1: DIGITAL SECTION FUNCTIONAL DIAGRAM Polarity D5 MSB D4 Digit D3 Drive Multiplexer D2 Signal D1 LSB 13 B1 14 B2 Data 15 B4 Output 16 B8 From Analog Section Polarity FF Zero Cross Detect Latch Latch Latch Latch Latch Counters Control Logic 24 DGND 22 Clock In 25 RUN/ HOLD 27 28 26 STROBE 21 Busy Overrange Underrange 2002 Microchip Technology Inc. DS21460B-page 9 © TC7135 FIGURE 5-2: TIMING DIAGRAMS FOR OUTPUTS 5.2 STROBE Output Integrator Output Signal System Integrate Reference 10,000 Zero Integrate 10,001 Counts 20,001 Counts (Fixed) Counts (Max) Full Measurement Cycle 40,002 Counts During the measurement cycle, the STROBE control line is pulsed low five times. The five low pulses occur in the center of the digit drive signals (D 1, D2, D3, D5) (see Figure 5-3). D 5 (MSD) goes high for 201 counts when the measurement cycles end. In the center of the D5 pulse, 101 clock pulses after the end of the measurement cycle, the first STROBE occurs for one half clock pulse. After the D5 digit strobe, D 4 goes high for 200 clock pulses. The STROBE then goes low 100 clock pulses after D4 goes high. This continues through the D 1 digit drive pulse. The digit drive signals will continue to permit display scanning. STROBE pulses are not repeated until a new measurement is completed. The digit drive signals will not continue if the previous signal resulted in an overrange condition. The active low STROBE pulses aid BCD data transfer to UARTs, processors and external latches. For more information, please refer to Application Note 784. Busy Overrange when Applicable Underrange when Applicable Expanded Scale Below Digit Scan D5 D4 D3 D2 D1 * First D5 of System Zero and Reference Integrate One Count Longer Signal Integrate * D4 D3 D2 Reference Integrate 100 Counts STROBE Auto Zero Digit Scan for Overrange * D5 FIGURE 5-3: STROBE SIGNAL LOW FIVE TIMES PER CONVERSION TC835 Outputs Busy * End of Conversion D1 B1–B8 D5 (MSD) Data D4 Data D3 Data D2 Data D1 (LSD) Data D5 Data 5.1 RUN/HOLD Input STROBE 200 Counts Note Absence of STROBE 200 Counts When left open, this pin assumes a logic "1" level. With a RUN/HOLD = 1, the TC7135 performs conversions continuously, with a new measurement cycle beginning every 40,002 clock pulses. When RUN/HOLD changes to a logic "0," the measurement cycle in progress will be completed, data held and displayed, as long as the logic "0" condition exists. A positive pulse (>300nsec) at RUN/HOLD initiates a new measurement cycle. The measurement cycle in progress when RUN/HOLD initially assumed the logic "0" state must be completed before the positive pulse can be recognized as a single conversion run command. The new measurement cycle begins with a 10,001count auto zero phase. At the end of this phase the busy signal goes high. D5 201 Counts 200 Counts 200 Counts 200 Counts 200 Counts D4 D3 D2 D1 *Delay between Busy going Low and First STROBE pulse is dependent on Analog Input. © DS21460B-page 10 2002 Microchip Technology Inc. TC7135 5.3 BUSY Output At the beginning of the signal integration phase, BUSY goes high and remains high until the first clock pulse after the integrator zero crossing. BUSY returns to the logic "0" state after the measurement cycle ends in an overrange condition. The internal display latches are loaded during the first clock pulse after BUSY and are latched at the clock pulse end. The BUSY signal does not go high at the beginning of the measurement cycle, which starts with the auto zero cycle. 5.4 OVERRANGE Output If the input signal causes the reference voltage integration time to exceed 20,000 clock pulses, the OVERRANGE output is set to a logic "1." The overrange output register is set when BUSY goes low and is reset at the beginning of the next reference integration phase. 5.5 UNDERRANGE Output If the output count is 9% of full scale or less (-1800 counts), the underrange register bit is set at the end of BUSY. The bit is set low at the next signal integration phase. 5.6 POLARITY Output A positive input is registered by a logic "1" polarity signal. The polarity bit is valid at the beginning of reference integrate and remains valid until determined during the next conversion. The polarity bit is valid even for a zero reading. Signals less than the converter's LSB will have the signal polarity determined correctly. This is useful in null applications. 5.7 Digit Drive Outputs Digit drive signals are positive-going signals. The scan sequence is D5 to D1. All positive pulses are 200 clock pulses wide, with the exception D5, which is 201 clock pulses wide. All five digits are scanned continuously, unless an overrange condition occurs. In an overrange condition, all digit drives are held low from the final STROBE pulse until the beginning of the next reference integrate phase. The scanning sequence is then repeated. This provides a blinking visual display indication. 5.8 BCD Data Outputs The binary coded decimal (BCD) bits B8, B4, B2, and B1 are positive-true logic signals. The data bits become active at the same time as the digit drive signals. In an overrange condition, all data bits are at a logic "0" state. 2002 Microchip Technology Inc. DS21460B-page 11 © TC7135 6.0 6.1 6.1.1 TYPICAL APPLICATIONS Component Value Selection INTEGRATING RESISTOR The dielectric absorption of the reference and auto zero capacitors are only important at power-on or when the circuit is recovering from an overload. Smaller or cheaper capacitors can be used if accurate readings are not required for the first few seconds of recovery. The integrating resistor RINT is determined by the full scale input voltage and the output current of the buffer used to charge the integrator capacitor, CINT. Both the buffer amplifier and the integrator have a class A output stage, with 100µA of quiescent current. A 20µA drive current gives negligible linearity errors. Values of 5µA to 40µA give good results. The exact value of an integrating resistor for a 20µA current is easily calculated. 6.1.4 REFERENCE VOLTAGE The analog input required to generate a full scale output is VIN = 2 VREF. The stability of the reference voltage is a major factor in the overall absolute accuracy of the converter. For this reason, it is recommended that a high-quality reference be used where high-accuracy absolute measurements are being made. EQUATION 6-1: RINT = Full scale voltage 20 µA 6.2 6.2.1 Conversion Timing LINE FREQUENCY REJECTION 6.1.2 INTEGRATING CAPACITOR (C INT) The product of integrating resistor and capacitor should be selected to give the maximum voltage swing that ensures the tolerance buildup will not saturate the integrator swing (approximately 0.3V from either supply). For ±5V supplies and ANALOG COMMON tied to supply ground, a ±3.5V to ±4V full scale integrator swing is adequate. A 0.10µF to 0.47µF is recommended. In general, the value of CINT is given by: A signal integration period at a multiple of the 60Hz line frequency will maximize 60Hz "line noise" rejection. A 100kHz clock frequency will reject 50Hz, 60Hz and 400Hz noise. This corresponds to five readings per second (see Table 6-1 and Table 6-2). TABLE 6-1: CONVERSION RATE VS. CLOCK FREQUENCY Conversion Rate (Conv./Sec.) 2.5 3 5 7.5 10 20 30 Oscillator Frequency (kHz) 100 120 200 300 400 800 1200 EQUATION 6-2: CINT = [10,000 x clock period] x IINT Integrator output voltage swing (10,000) (clock period) (20µA) Integrator output voltage swing A very important characteristic of the integrating capacitor C INT is that it has low dielectric absorption to prevent rollover or ratiometric errors. A good test for dielectric absorption is to use the capacitor with the input tied to the reference. This ratiometric condition should read half scale 0.9999, with any deviation probably due to dielectric absorption. Polypropylene capacitors give undetectable errors at reasonable cost. Polystyrene and polycarbonate capacitors may also be used in less critical applications. = 6.1.3 AUTO ZERO AND REFERENCE CAPACITORS The size of the auto zero capacitor has some influence on the noise of the system. A large capacitor reduces the noise. The reference capacitor should be large enough such that stray capacitance to ground from its nodes is negligible. © DS21460B-page 12 2002 Microchip Technology Inc. TC7135 TABLE 6-2: LINE FREQUENCY REJECTION VS. CLOCK FREQUENCY Line Frequency Rejection (Hz) 60 Oscillator Frequency (kHz) 300 200 150 120 100 40 33-1/3 250 166-2/3 125 100 100 ator delay can be compensated and the maximum clock frequency extended by approximately a factor of 3. At higher frequencies, ringing and second-order breaks will cause significant nonlinearities in the first few counts of the instrument. The minimum clock frequency is established by leakage on the auto zero and reference capacitors. With most devices, measurement cycles as long as 10 seconds give no measurable leakage error. The clock used should be free from significant phase or frequency jitter. Several suitable low-cost oscillators are shown in Section 6.0, Typical Applications. The multiplexed output means that if the display takes significant current from the logic supply, the clock should have good PSRR. 50 6.4 50, 60,400 Zero Crossing Flip Flop The conversion rate is easily calculated: EQUATION 6-3: Reading 1/sec = Clock Frequency (Hz) 4000 6.3 High Speed Operation The maximum conversion rate of most dual slope A/D converters is limited by the frequency response of the comparator. The comparator in this circuit follows the integrator ramp with a 3µsec delay, at a clock frequency of 160 kHz (6µsec period), Half of the first reference integrate clock period is lost in delay. This means that the meter reading will change from 0 to 1 with a 50µV input, 1 to 2 with 150µV, 2 to 3 at 250µV, etc. This transition at midpoint is considered desirable by most users. However, if the clock frequency is increased appreciably above 200kHz, the instrument will flash "1" on noise peaks, even when the input is shorted. For many dedicated applications where the input signal is always of one polarity, the delay of the comparator need not be a limitation. Since the nonlinearity and noise do not increase substantially with frequency, clock rates of up to ~1MHz may be used. For a fixed clock frequency, the extra count, or counts, caused by comparator delay, will be a constant and can be subtracted out digitally. The clock frequency may be extended above 160kHz without this error, however, by using a low value resistor in series with the integrating capacitor. The effect of the resistor is to introduce a small pedestal voltage on to the integrator output at the beginning of the reference integrate phase. By careful selection of the ratio between this resistor and the integrating resistor (a few tens of ohms in the recommended circuit), the compar- The flip flop interrogates the data once every clock pulse after the transients of the previous clock pulse and half clock pulse have died down. False zero crossings caused by clock pulses are not recognized. Of course, the flip flop delays the true zero crossing by up to one count in every instance. If a correction were not made, the display would always be one count too high. Therefore, the counter is disabled for one clock pulse at the beginning of the reference integrate (de-integrate) phase. This one-count delay compensates for the delay of the zero crossing flip flop and allows the correct number to be latched into the display. Similarly, a one-count delay at the beginning of auto zero gives an overload display of 0000 instead of 0001. No delay occurs during signal integrate so that true ratiometric readings result. 6.5 Generating a Negative Supply A negative voltage can be generated from the positive supply by using a TC7660 (see Figure 6-1). FIGURE 6-1: NEGATIVE SUPPLY VOLTAGE GENERATOR +5V 11 V+ 8 1 (-5V) 10µF + 4 + 10µF 2 3 5 TC7135 V– TC7660 24 2002 Microchip Technology Inc. DS21460B-page 13 © TC7135 FIGURE 6-2: 4-1/2 DIGIT ADC WITH MULTIPLEXED COMMON ANODE LED DISPLAY +5V 20 19 18 17 12 D1 D2 D3 D4 D5 4 INT OUT 0.33µF 1µF 5 AZ IN POL 23 4.7kΩ b 1µF c 7 7 X7 5 RBI DM7447A 16 +5V 9–15 7 7 100kΩ 200kHz 100kΩ 6 BUFF OUT 22 F IN 10 TC7135 CREF- 7 CREF+ 8 16 B8 15 B4 14 B2 B1 13 V+ 11 V+ Blank MSD On Zero 6 D 2 C 1 B 7 A + Analog Input – +INPUT –INPUT 1µF 9 3 ANALOG COMMON REF V – IN 12 –5V 100kΩ MCP1525 1µF FIGURE 6-3: R2 RC OSCILLATOR CIRCUIT R1 C FO FIGURE 6-4: COMPARATOR CLOCK CIRCUITS +5V 16kΩ 56kΩ + 2 3 8 7 1 4 1kΩ Gates are 74C04 1. F O = 1 2C(0.41 RP + 0.7 R1) , RP = R1 R2 R1 + R2 16kΩ 0.22µF VOUT LM311 6 7 4 1 C1 0.1µF 30kΩ 390pF a. If R1 = R 2 = R 1, F≅ 0.55/RC b. If R2 >> R 1, F ≅ 0.45/R1C c. If R2