TC9402

TC9400/9401/9402 Voltage-to-Frequency/Frequency-to-Voltage Converters Features VOLTAGE-TO-FREQUENCY • Choice of Linearity - TC9401: 0.01% - TC9400: 0.05% - TC9402: 0.25% • DC to 100kHz (F/V) or 1Hz to 100kHz (V/F) • Low Power Dissipation: 27mW (Typ.) • Single/Dual Supply Operation - +8V to +15V or ±4V to ±7.5V • Gain Temperature Stability: ±25 ppm/°C (Typ.) • Programmable Scale Factor General Description The TC9400/TC9401/TC9402 are low cost voltage-tofrequency (V/F) converters, utilizing low power CMOS technology. The converters accept a variable analog input signal and generate an output pulse train, whose frequency is linearly proportional to the input voltage. The devices can also be used as highly accurate frequency-to-voltage (F/V) converters, accepting virtually any input frequency waveform and providing a linearly proportional voltage output. A complete V/F or F/V system only requires the addition of two capacitors, three resistors, and reference voltage. FREQUENCY-TO-VOLTAGE • Operation: DC to 100kHz • Choice of Linearity - TC9401: 0.02% - TC9400: 0.05% - TC9402: 0.25% • Programmable Scale Factor Package Type 14-Pin Plastic DIP/CERDIP IBIAS 1 ZERO ADJ 2 IIN 3 VSS 4 VREF OUT 5 GND 6 VREF 7 14 VDD 13 NC Applications • • • • • • • µP Data Acquisition 13-bit Analog-to-Digital Converters Analog Data Transmission and Recording Phase Locked Loops Frequency Meters/Tachometer Motor Control FM Demodulation TC9400 TC9401 TC9402 12 AMPLIFIER OUT THRESHOLD 11 DETECTOR 10 FREQ/2 OUT 9 OUTPUT COMMON 8 PULSE FREQ OUT 14-Pin SOIC IBIAS ZERO ADJ 1 2 3 4 5 6 7 14 13 VDD NC AMPLIFIER OUT THRESHOLD DETECTOR FREQ/2 OUT OUTPUT COMMON PULSE FREQ OUT Device Selection Table Part Number TC9400COD TC9400CPD TC9400EJD TC9401CPD TC9401EJD TC9402CPD TC9402EJD Linearity (V/F) 0.05% 0.05% 0.05% 0.01% 0.01% 0.25% 0.25% Package 14-Pin SOIC (Narrow) 14-Pin PDIP 14-Pin CerDIP 14-Pin PDIP 14-Pin CerDIP 14-Pin PDIP 14-Pin CerDIP Temperature Range 0°C to +70°C 0°C to +70°C -40°C to +85°C 0°C to +70°C -40°C to +85°C 0°C to +70°C °C to +85°C IIN VSS VREF OUT GND VREF TC9400 TC9401 TC9402 12 11 10 9 8 NC = No Internal Connection 2002 Microchip Technology Inc. DS21483B-page 1 © TC9400/9401/9402 Functional Block Diagram Integrator Capacitor Input Voltage RIN IIN Integrator Op Amp Threshold Detector One Shot Pulse Output Reference Capacitor ÷2 Pulse/2 Output TC9400 IREF Reference Voltage © DS21483B-page 2 2002 Microchip Technology Inc. TC9400/9401/9402 1.0 ELECTRICAL CHARACTERISTICS *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Absolute Maximum Ratings* VDD – VSS ........................................................... +18V IIN ........................................................................ 10mA VOUTMAX – VOUT Common...................................... 23V VREF – VSS ..........................................................-1.5V Storage Temperature Range .............. -65°C to +150°C Operating Temperature Range: C Device ........................................... 0°C to +70°C E Device......................................... -40°C to +85°C Package Dissipation (TA ≤ 70°C): 8-Pin CerDIP .............................................. 800mW 8-Pin Plastic DIP ........................................ 730mW 8-Pin SOIC ................................................. 470mW TC940X ELECTRICAL SPECIFICATIONS Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Min Typ Max Min Typ Max Min Typ Max Units Test Conditions Voltage-to-Frequency Accuracy Linearity 10kHz — TC9400 0.01 0.05 — TC9401 0.004 0.01 — TC9402 0.05 0.25 % Output Deviation from Full Scale Straight Line Between Normalized Zero and Full Scale Input % Output Deviation from Full Scale Straight Line Between Normalized Zero Reading and Full Scale Input ppm/°C Variation in Gain A due Full Scale to Temperature Change % of Nominal mV Variation from Ideal Accuracy Correction at Zero Adjust for Zero Output when Input is Zero Variation in Zero Offset Due to Temperature Change Linearity 100kHz — 0.1 0.25 — 0.04 0.08 — 0.25 0.5 Gain Temperature Drift (Note 1) Gain Variance Zero Offset (Note 2) Zero Temperature Drift (Note 1) Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: — — — ±25 ±10 ±10 ±40 — ±50 — — — ±25 ±10 ±10 ±40 — ±50 — — — ±50 ±10 ±20 ±100 — ±100 — ±25 ±50 — ±25 ±50 — ±50 ±100 µV/°C Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10mA. IOUT = 10µ A. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10Hz to 100kHz; not tested. 5µ sec minimum positive pulse width and 0.5µsec minimum negative pulse width. tR = tF = 20nsec. RL ≥ 2kΩ, tested @ 10kΩ. Full temperature range, VIN = -0.1V. 2002 Microchip Technology Inc. DS21483B-page 3 © TC9400/9401/9402 TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Analog Input IIN Full Scale — 10 — — 10 — — 10 — µA Full Scale Analog Input Current to achieve Specified Accuracy Over Range Current Settling Time to 0.1% Full Scale Min Typ Max Min Typ Max Min Typ Max Units Test Conditions IIN Over Range Response Time Digital Section VSAT @ IOL = 10mA VOUTMAX – VOUT Common (Note 4) Pulse Frequency Output Width — — — 2 TC9400 50 — — — — 2 TC9401 50 — — — — 2 TC9402 50 — µA Cycle — — 0.2 — 0.4 18 — — 0.2 — 0.4 18 — — 0.2 — 0.4 18 V V Logic "0" Output Voltage (Note 3) Voltage Range Between Output and Common — 3 — — 3 — — 3 — µsec Frequency-to-Voltage Supply Current IDD Quiescent (Note 5) ISS Quiescent (Note 5) VDD Supply VSS Supply Reference Voltage VREF – VSS Accuracy Non-Linearity (Note 10) — 0.02 0.05 — 0.01 0.02 — 0.05 0.25 % Deviation from ideal Full Scale Transfer Function as a Percentage Full Scale Voltage Hz Frequency Range for Specified Non-Linearity -2.5 — — -2.5 — — -2.5 — — V Range of Voltage Reference Input — 1.5 6 — 1.5 6 — 3 10 mA Current Required from Positive Supply during Operation Current Required from Negative Supply during Operation Operating Range of Positive Supply Operating Range of Negative Supply — -1.5 -6 — -1.5 -6 — -3 -10 mA 4 -4 — — 7.5 -7.5 4 -4 — — 7.5 -7.5 4 -4 — — 7.5 -7.5 V V Input Frequency Range (Notes 7 and 8) Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: 10 — 100k 10 — 100k 10 — 100k Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10mA. IOUT = 10µ A. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10Hz to 100kHz; not tested. 5µ sec minimum positive pulse width and 0.5µsec minimum negative pulse width. tR = tF = 20nsec. RL ≥ 2kΩ, tested @ 10kΩ. Full temperature range, VIN = -0.1V. © DS21483B-page 4 2002 Microchip Technology Inc. TC9400/9401/9402 TC940X ELECTRICAL SPECIFICATIONS (CONTINUED) Electrical Characteristics: VDD = +5V, VSS = -5V, VGND = 0V, VREF = -5V, RBIAS = 100kΩ, Full Scale = 10kHz, unless otherwise specified. TA = +25°C, unless temperature range is specified (-40°C to +85°C for E device, 0°C to +70°C for C device). Parameter Frequency Input Positive Excursion 0.4 — VDD 0.4 — VDD 0.4 — VDD V Voltage Required to Turn Threshold Detector On Voltage Required to Turn Threshold Detector Off Time between Threshold Crossings Time Between Threshold Crossings Min Typ Max Min Typ Max Min Typ Max Units Test Conditions Negative Excursion -0.4 -2 -0.4 — -2 -0.4 — -2 V Minimum Positive Pulse Width (Note 8) Minimum Negative Pulse Width (Note 8) Input Impedance Analog Outputs Output Voltage (Note 9) Output Loading Supply Current IDD Quiescent (Note 10) ISS Quiescent (Note 10) VDD Supply VSS Supply Reference Voltage VREF – VSS Note 1: 2: 3: 4: 5: 6: 7: 8: 9: 10: — 5 — — 5 — — 5 — µsec — 0.5 — — 0.5 — — 0.5 — µsec — 10 TC9400 — — 10 TC9401 — — TC9402 10 MΩ — VDD – 1 — — VDD – 1 — — VDD – 1 — V Voltage Range of Op Amp Output for Specified Non-Linearity Resistive Loading at Output of Op Amp 2 — TC9400 — 2 — TC9401 — 2 — TC9402 — kΩ — 1.5 6 — 1.5 6 — 3 10 mA Current Required from Positive Supply During Operation Current Required from Negative Supply During Operation Operating Range of Positive Supply Operating Range of Negative Supply — -1.5 -6 -1.5 -6 — -3 -10 mA 4 -4 — — 7.5 -7.5 4 -4 — — 7.5 -7.5 4 -4 — — 7.5 -7.5 V V -2.5 — — -2.5 — — -2.5 — — V Range of Voltage Reference Input Full temperature range; not tested. IIN = 0. Full temperature range, IOUT = 10mA. IOUT = 10µ A. Threshold Detect = 5V, Amp Out = 0V, full temperature range. 10Hz to 100kHz; not tested. 5µ sec minimum positive pulse width and 0.5µsec minimum negative pulse width. tR = tF = 20nsec. RL ≥ 2kΩ, tested @ 10kΩ. Full temperature range, VIN = -0.1V. 2002 Microchip Technology Inc. DS21483B-page 5 © TC9400/9401/9402 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: PIN FUNCTION TABLE Symbol IBIAS ZERO ADJ IIN VSS VREF OUT GND VREF PULSE FREQ OUT OUTPUT COMMON FREQ/2 OUT THRESHOLD DETECTOR NC VDD Description This pin sets bias current in the TC9400. Connect to VSS through a 100kΩ resistor. Low frequency adjustment input. Input current connection for the V/F converter. Negative power supply voltage connection, typically -5V. Reference capacitor connection. Analog ground. Voltage reference input, typically -5V. Frequency output. This open drain output will pulse LOW each time the Freq. Threshold Detector limit is reached. The pulse rate is proportional to input voltage. Source connection for the open drain output FETs. This open drain output is a square wave at one-half the frequency of the pulse output (Pin 8). Output transitions of this pin occur on the rising edge of Pin 8. Input to the Threshold Detector. This pin is the frequency input during F/V operation. Pin No. 14-Pin PDIP/CERDIP 14-Pin SOIC (Narrow) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 AMPLIFIER OUT Output of the integrator amplifier. No internal connection. Positive power supply connection, typically +5V. © DS21483B-page 6 2002 Microchip Technology Inc. TC9400/9401/9402 3.0 3.1 DETAILED DESCRIPTION Voltage-to-Frequency (V/F) Circuit Description The TC9400 V/F converter operates on the principal of charge balancing. The operation of the TC9400 is easily understood by referring to Figure 3-1. The input voltage (VIN) is converted to a current (IIN) by the input resistor. This current is then converted to a charge on the integrating capacitor and shows up as a linearly decreasing voltage at the output of the Op Amp. The lower limit of the output swing is set by the threshold detector, which causes the reference voltage to be applied to the reference capacitor for a time period long enough to charge the capacitor to the reference voltage. This action reduces the charge on the integrating capacitor by a fixed amount (q = CREF x VREF), causing the Op Amp output to step up a finite amount. At the end of the charging period, CREF is shorted out. This dissipates the charge stored on the reference capacitor, so that when the output again crosses zero, the system is ready to recycle. In this manner, the continued discharging of the integrating capacitor by the input is balanced out by fixed charges from the reference voltage. As the input voltage is increased, the number of reference pulses required to maintain balance increases, which causes the output frequency to also increase. Since each charge increment is fixed, the increase in frequency with voltage is linear. In addition, the accuracy of the output pulse width does not directly affect the linearity of the V/F. The pulse must simply be long enough for full charge transfer to take place. The TC9400 contains a "self-start" circuit to ensure the V/F converter always operates properly when power is first applied. In the event that, during power-on, the Op Amp output is below the threshold and CREF is already charged, a positive voltage step will not occur. The Op Amp output will continue to decrease until it crosses the -3.0V threshold of the "self-start" comparator. When this happens, an internal resistor is connected to the Op Amp input, which forces the output to go positive until the TC9400 is in its Normal Operating mode. The TC9400 utilizes low power CMOS processing for low input bias and offset currents, with very low power dissipation. The open drain N-channel output FETs provide high voltage and high current sink capability. FIGURE 3-1: 10Hz TO 10kHz V/F CONVERTER +5V 14 VDD Threshold 11 Detect 3µsec Delay Threshold Detector FOUT/2 10 SelfStart -3V 12 AMP OUT 5 VREF OUT CINT 820pF CREF 180pF 3 IIN 510kΩ Zero Adjust 2 20kΩ 12pF 60pF ÷2 Output Common 9 RL 10kΩ FOUT 8 RL 10kΩ +5V +5V INPUT VIN 0V –10V RIN 1MΩ +5V TC9400 TC9401 TC9402 – Op Amp 50kΩ -5V Offset Adjust + IBIAS VSS 4 VREF 7 Reference Voltage (Typically -5V) -5V GND 6 10kΩ 1 RBIAS 100kΩ 2002 Microchip Technology Inc. DS21483B-page 7 © TC9400/9401/9402 3.2 Voltage-to-Time Measurements 4.0 4.1 PIN FUNCTIONS Threshold Detector Input The TC9400 output can be measured in the time domain as well as the frequency domain. Some microcomputers, for example, have extensive timing capability, but limited counter capability. Also, the response time of a time domain measurement is only the period between two output pulses, while the frequency measurement must accumulate pulses during the entire counter time-base period. Time measurements can be made from either the TC9400's PULSE FREQ OUT output, or from the FREQ/2 OUT output. The FREQ/2 OUT output changes state on the rising edge of PULSE FREQ OUT, so FREQ/2 OUT is a symmetrical square wave at one-half the pulse output frequency. Timing measurements can, therefore, be made between successive PULSE FREQ OUT pulses, or while FREQ/2 OUT is high (or low). In the V/F mode, this input is connected to the AMPLIFIER OUT output (Pin 12) and triggers a 3µsec pulse when the input voltage passes through its threshold. In the F/V mode, the input frequency is applied to this input. The nominal threshold of the detector is half way between the power supplies, or (VDD + VSS)/2 ±400mV. The TC9400's charge balancing V/F technique is not dependent on a precision comparator threshold, because the threshold only sets the lower limit of the Op Amp output. The Op Amp's peak-to-peak output swing, which determines the frequency, is only influenced by external capacitors and by V REF. 4.2 Pulse Freq Out This output is an open drain N-channel FET, which provides a pulse waveform whose frequency is proportional to the input voltage. This output requires a pullup resistor and interfaces directly with MOS, CMOS, and TTL logic (see Figure 4-1). FIGURE 4-1: OUTPUT WAVEFORMS 3µsec Typ. FOUT FOUT/2 1/f CREF CINT VREF Amp Out 0V Notes: 1. To adjust FMIN, set VIN = 10mV and adjust the 50kΩ offset for 10Hz output. 2. To adjust FMAX, set VIN = 10V and adjust RIN or VREF for 10kHz output. 3. To increase FOUTMAX to 100kHz, change CREF to 2pF and CINT to 75pF. 4. For high performance applications, use high stability components for RIN, CREF, VREF (metal film resistors and glass capacitors). Also, separate output ground (Pin 9) from input ground (Pin 6). © DS21483B-page 8 2002 Microchip Technology Inc. TC9400/9401/9402 4.3 Freq/2 Out 4.8 IIN This output is an open drain N-channel FET, which provides a square wave one-half the frequency of the pulse frequency output. The FREQ/2 OUT output will change state on the rising edge of PULSE FREQ OUT. This output requires a pull-up resistor and interfaces directly with MOS, CMOS, and TTL logic. The inverting input of the operational amplifier and the summing junction when connected in the V/F mode. An input current of 10µA is specified, but an over range current up to 50µA can be used without detrimental effect to the circuit operation. IIN connects the summing junction of an operational amplifier. Voltage sources cannot be attached directly, but must be buffered by external resistors. 4.4 Output Common The sources of both the FREQ/2 OUT and the PULSE FREQ OUT are connected to this pin. An output level swing from the drain voltage to ground, or to the V SS supply, may be obtained by connecting this pin to the appropriate point. 4.9 VREF A reference voltage from either a precision source, or the VSS supply is applied to this pin. Accuracy of the TC9400 is dependent on the voltage regulation and temperature characteristics of the reference circuitry. Since the TC9400 is a charge balancing V/F converter, the reference current will be equal to the input current. For this reason, the DC impedance of the reference voltage source must be kept low enough to prevent linearity errors. For linearity of 0.01%, a reference impedance of 200W or less is recommended. A 0.1µF bypass capacitor should be connected from VREF to ground. 4.5 R BIAS An external resistor, connected to V SS, sets the bias point for the TC9400. Specifications for the TC9400 are based on RBIAS = 100kΩ ±10%, unless otherwise noted. Increasing the maximum frequency of the TC9400 beyond 100kHz is limited by the pulse width of the pulse output (typically 3µsec). Reducing RBIAS will decrease the pulse width and increase the maximum operating frequency, but linearity errors will also increase. RBIAS can be reduced to 20kΩ, which will typically produce a maximum full scale frequency of 500kHz. 4.10 VREF Out 4.6 Amplifier Out This pin is the output stage of the operational amplifier. During V/F operation, a negative going ramp signal is available at this pin. In the F/V mode, a voltage proportional to the frequency input is generated. The charging current for CREF is supplied through this pin. When the Op Amp output reaches the threshold level, this pin is internally connected to the reference voltage and a charge, equal to VREF x CREF, is removed from the integrator capacitor. After about 3µsec, this pin is internally connected to the summing junction of the Op Amp to discharge CREF. Break-before-make switching ensures that the reference voltage is not directly applied to the summing junction. 4.7 Zero Adjust This pin is the non-inverting input of the operational amplifier. The low frequency set point is determined by adjusting the voltage at this pin. 2002 Microchip Technology Inc. DS21483B-page 9 © TC9400/9401/9402 5.0 VOLTAGE-TO-FREQUENCY (V/F) CONVERTER DESIGN INFORMATION Input/Output Relationships CREF (pF) +12pF FIGURE 5-1: 500 400 300 RECOMMENDED CREF VS. VREF VDD = +5V VSS = -5V RIN = 1MΩ VIN = +10V TA = +25°C 10kHz 5.1 The output frequency (FOUT) is related to the analog input voltage (VIN) by the transfer equation: EQUATION 5-1: Frequency Out = VIN 1 ,x (VREF)(VREF) RIN 200 100 100kHz 5.2 5.2.1 External Component Selection R IN 5.2.4 0 -1 -2 -3 -4 VREF (V) -5 -6 -7 The value of this component is chosen to give a full scale input current of approximately 10µA: VDD, VSS EQUATION 5-2: RIN ≅ VIN FULLSCALE 10µA Power supplies of ±5V are recommended. For high accuracy requirements, 0.05% line and load regulation and 0.1µF disc decoupling capacitors, located near the pins, are recommended. 5.3 Adjustment Procedure EQUATION 5-3: RIN ≅ 10V = 1MΩ 10µA Figure 3-1 shows a circuit for trimming the zero location. Full scale may be trimmed by adjusting RIN, VREF, or CREF. Recommended procedure for a 10kHz full scale frequency is as follows: 1. 2. Set VIN to 10mV and trim the zero adjust circuit to obtain a 10Hz output frequency. Set VIN to 10V and trim either RIN, VREF, or CREF to obtain a 10kHz output frequency. Note that the value is an approximation and the exact relationship is defined by the transfer equation. In practice, the value of RIN typically would be trimmed to obtain full scale frequency at VIN full scale (see Section 5.3, Adjustment Procedure). Metal film resistors with 1% tolerance or better are recommended for high accuracy applications because of their thermal stability and low noise generation. If adjustments are performed in this order, there should be no interaction and they should not have to be repeated. 5.4 5.2.2 C INT Improved Single Supply V/F Converter Operation The exact value is not critical but is related to CREF by the relationship: 3CREF ≤ CINT ≤ 10CREF Improved stability and linearity are obtained when CINT ≤ 4CREF. Low leakage types are recommended, although mica and ceramic devices can be used in applications where their temperature limits are not exceeded. Locate as close as possible to Pins 12 and 13. 5.2.3 C REF The exact value is not critical and may be used to trim the full scale frequency (see Section 7.1, Input/Output Relationships). Glass film or air trimmer capacitors are recommended because of their stability and low leakage. Locate as close as possible to Pins 5 and 3 (see Figure 5-1). A TC9400, which operates from a single 12 to 15V variable power source, is shown in Figure 5-2. This circuit uses two Zener diodes to set stable biasing levels for the TC9400. The Zener diodes also provide the reference voltage, so the output impedance and temperature coefficient of the Zeners will directly affect power supply rejection and temperature performance. Full scale adjustment is accomplished by trimming the input current. Trimming the reference voltage is not recommended for high accuracy applications unless an Op Amp is used as a buffer, because the TC9400 requires a low impedance reference (see Section 4.9, VREF pin description, for more information). The circuit of Figure 5-2 will directly interface with CMOS logic operating at 12V to 15V. TTL or 5V CMOS logic can be accommodated by connecting the output pull-up resistors to the +5V supply. An optoisolator can also be used if an isolated output is required; also, see Figure 5-3. © DS21483B-page 10 2002 Microchip Technology Inc. TC9400/9401/9402 FIGURE 5-2: VOLTAGE TO FREQUENCY +12 to +15V 1.2k 1µF R1 910k R3 Gain R4 100k CINT 14 VDD 11 Threshold Detect 12 Amp Out CREF 5 C REF D2 5.1VZ 10k 10k TC9400 3 IIN 2 Zero Adjust FOUT 8 10 Output Frequency 100k R2 910k R5 91k D1 5.1VZ 6 GND 0.1µ 7V REF 1I BIAS FOUT/2 Output 9 Common Input Voltage (0 to 10V) Rp Offset 20k Analog Ground Component Selection CREF CINT F/S FREQ. 2200pF 4700pF 1kHz 180pF 470pF 10kHz 27pF 75pF 100kHz 100k VSS 4 Digital Ground FIGURE 5-3: FIXED VOLTAGE - SINGLE SUPPLY OPERATION V+ = 8V to 15V (Fixed) R2 0.9 R1 Gain Adjust V2 5V 8.2 kΩ 2 kΩ Offset Adjust RIN 1MΩ VIN 0V–10V IIN 100kΩ 0.2 R1 820 pF 0.01 µF 2 6 14 8 10kΩ FOUT 10kΩ 10 FOUT/2 TC9400 7 VREF 0.01 11 µF 12 5 180 pF 3 IIN 1 4 9 V+ 10V 12V 15V R1 1MΩ 1.4MΩ 2MΩ R2 10kΩ 14kΩ 20kΩ FOUT = IIN 1 (V2 – V7) (CREF) + (V+ – V2) (0.9R1 + 0.2R1) IIN = (VIN – V2) RIN 2002 Microchip Technology Inc. DS21483B-page 11 © TC9400/9401/9402 6.0 FREQUENCY-TO-VOLTAGE (F/V) CIRCUIT DESCRIPTION CINT can be increased to lower the ripple. Values of 1µF to 100µF are perfectly acceptable for low frequencies. When the TC9400 is used in the Single Supply mode, VREF is defined as the voltage difference between Pin 7 and Pin 2. When used as an F/V converter, the TC9400 generates an output voltage linearly proportional to the input frequency waveform. Each zero crossing at the threshold detector's input causes a precise amount of charge (q = CREF ∞ VREF) to be dispensed into the Op Amp's summing junction. This charge, in turn, flows through the feedback resistor, generating voltage pulses at the output of the Op Amp. A capacitor (C INT) across R INT averages these pulses into a DC voltage, which is linearly proportional to the input frequency. 7.2 Input Voltage Levels 7.0 7.1 F/V CONVERTER DESIGN INFORMATION Input/Output Relationships The input frequency is applied to the Threshold Detector input (Pin 11). As discussed in the V/F circuit section of this data sheet, the threshold of Pin 11 is approximately (VDD + VSS)/2 ±400mV. Pin 11's input voltage range extends from VDD to about 2.5V below the threshold. If the voltage on Pin 11 goes more than 2.5 volts below the threshold, the V/F mode start-up comparator will turn on and corrupt the output voltage. The Threshold Detector input has about 200mV of hysteresis. In ±5V applications, the input voltage levels for the TC9400 are ±400mV, minimum. If the frequency source being measured is unipolar, such as TTL or CMOS operating from a +5V source, then an AC coupled level shifter should be used. One such circuit is shown in Figure 7-1(a). The level shifter circuit in Figure 7-1(b) can be used in single supply F/V applications. The resistor divider ensures that the input threshold will track the supply voltages. The diode clamp prevents the input from going far enough in the negative direction to turn on the start-up comparator. The diode's forward voltage decreases by 2.1mV/°C, so for high ambient temperature operation, two diodes in series are recommended; also, see Figure 7-2. The output voltage is related to the input frequency (FIN) by the transfer equation: EQUATION 7-1: VOUT = [V REF C REF RINT] FIN The response time to a change in FIN is equal to (RINT CINT). The amount of ripple on VOUT is inversely proportional to CINT and the input frequency. FIGURE 7-1: FREQUENCY INPUT LEVEL SHIFTER +8V to +5V +5V 14 VDD 10k 14 VDD TC9400 Frequency Input +5V 0V GND 6 VSS 4 -5V 33k 0.01µF 11 IN914 1.0M DET Frequency Input +5V 0V 0.1µF 10k 33k 0.01µF IN914 11 1.0M TC9400 DET VSS 4 (a) ±5V Supply (b) Single Supply © DS21483B-page 12 2002 Microchip Technology Inc. TC9400/9401/9402 FIGURE 7-2: F/V SINGLE SUPPLY F/V CONVERTER V+ = 10V to 15V 14 10k 6 GND 6.2V .01µF 10k VREF OUT 5 2 Zero Adjust V+ Offset Adjust Frequency Input 33k 0.01µF 1.0k 11 DET GND IN914 1.0M IBIAS VREF VSS 7 4 47pF IIN 3 1M Amp Out 12 6 VOUT .001µF VDD TC9400 500k 100k 0.1µF 1.0k 100k Note: The output is referenced to Pin 6, which is at 6.2V (Vz). For frequency meter applications, a 1mA meter with a series scaling resistor can be placed across Pins 6 and 12. 7.3 Input Buffer FIGURE 7-3: 0.5µsec Min Input F/V DIGITAL OUTPUTS 5.0µsec Min FOUT and FOUT/2 are not used in the F/V mode. However, these outputs may be useful for some applications, such as a buffer to feed additional circuitry. Then, FOUT will follow the input frequency waveform, except that FOUT will go high 3µsec after FIN goes high; FOUT/2 will be square wave with a frequency of one-half FOUT. If these outputs are not used, Pins 8, 9 and 10 should be connected to ground (see Figure 7-3 and Figure 7-4). FOUT Delay = 3µsec FOUT/2 2002 Microchip Technology Inc. DS21483B-page 13 © TC9400/9401/9402 FIGURE 7-4: DC - 10kHz CONVERTER +5V V+ 14 VDD * 42 FOUT/2 10 V+ Output Common 9 * * 3µsec Delay Threshold Detector VREF OUT FOUT 8 *Optional/If Buffer is Needed See Figure 7-1: "Frequency Input Level Shifter" Threshold Detect 11 TC9400A TC9401A TC9402A FIN 5 CREF 56pF RINT 1MΩ CINT 1000pF VOUT 12pF Offset Adjust +5V 2kΩ 100kΩ 2.2kΩ 2 Zero Adjust IBIAS 1 10kΩ -5V VREF (Typically -5V) VSS 4 VREF 7 – Op Amp + 60pF IIN 3 Amp Out 12 GND 6 7.4 Output Filtering FIGURE 7-5: VREF OUT 5 RIPPLE FILTER The output of the TC9400 has a sawtooth ripple superimposed on a DC level. The ripple will be rejected if the TC9400 output is converted to a digital value by an integrating analog-to-digital converter, such as the TC7107 or TC7109. The ripple can also be reduced by increasing the value of the integrating capacitor, although this will reduce the response time of the F/V converter. The sawtooth ripple on the output of an F/V can be eliminated without affecting the F/V's response time by using the circuit in Figure 7-5. The circuit is a capacitance multiplier, where the output coupling capacitor is multiplied by the AC gain of the Op Amp. A moderately fast Op Amp, such as the TL071, should be used. 47pF TC9400 IIN 3 1M .001µF 200 AMP OUT 12 .01µF 1M GND 6 2 3 1M – + 7 6 +5 © DS21483B-page 14 2002 Microchip Technology Inc. + 0.1µF VOUT TL071 4 -5 TC9400/9401/9402 8.0 F/V POWER-ON RESET In F/V mode, the TC9400 output voltage will occasionally be at its maximum value when power is first applied. This condition remains until the first pulse is applied to FIN. In most frequency measurement applications, this is not a problem because proper operation begins as soon as the frequency input is applied. In some cases, however, the TC9400 output must be zero at power-on without a frequency input. In such cases, a capacitor connected from Pin 11 to VDD will usually be sufficient to pulse the TC9400 and provide a Power-on Reset (see Figure 8-1 (a) and (b)). Where predictable power-on operation is critical, a more complicated circuit, such as Figure 8-1 (b), may be required. FIGURE 8-1: POWER-ON OPERATION/RESET (a) VDD VDD 14 1000pF 3 11 Threshold Detector 100kΩ 4 A VSS 8 FIN 16 VCC CLRA CD4538 Q 6 To TC9400 5 B R 2 1 C (b) FIN 1kΩ TC9400 1µF 2002 Microchip Technology Inc. DS21483B-page 15 © TC9400/9401/9402 9.0 9.1 9.2 PACKAGE INFORMATION Package Marking Information Taping Form Package marking data is not available at this time. Component Taping Orientation for 14-Pin SOIC (Narrow) Devices User Direction of Feed PIN 1 W P Standard Reel Component Orientation for TR Suffix Device Carrier Tape, Reel Size, and Number of Components Per Reel Package Carrier Width (W) Pitch (P) Part Per Full Reel Reel Size 14-Pin SOIC (N) 12 mm 8 mm 2500 13 in 9.3 Package Dimensions 14-Pin CDIP (Narrow) PIN 1 .300 (7.62) .230 (5.84) .098 (2.49) MAX. .030 (0.76) MIN. .780 (19.81) .740 (18.80) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .320 (8.13) .290 (7.37) .200 (5.08) .160 (4.06) .200 (5.08) .125 (3.18) .150 (3.81) MIN. 3° MIN. .110 (2.79) .090 (2.29) .065 (1.65) .045 (1.14) .020 (0.51) .016 (0.41) .400 (10.16) .320 (8.13) Dimensions: inches (mm) © DS21483B-page 16 2002 Microchip Technology Inc. TC9400/9401/9402 9.3 Package Dimensions (Continued) 14-Pin PDIP (Narrow) PIN 1 .260 (6.60) .240 (6.10) .770 (19.56) .745 (18.92) .200 (5.08) .140 (3.56) .150 (3.81) .115 (2.92) .310 (7.87) .290 (7.37) .040 (1.02) .020 (0.51) .015 (0.38) .008 (0.20) .400 (10.16) .310 (7.87) 3° MIN. .110 (2.79) .090 (2.29) .070 (1.78) .045 (1.14) .022 (0.56) .015 (0.38) Dimensions: inches (mm) 14-Pin SOIC (Narrow) PIN 1 .157 (3.99) .244 (6.20) .150 (3.81) .228 (5.79) .050 (1.27) TYP. .344 (8.74) .337 (8.56) .069 (1.75) .053 (1.35) .010 (0.25) .004 (0.10) 8° MAX. .050 (1.27) .016 (0.40) .010 (0.25) .007 (0.18) .018 (0.46) .014 (0.36) Dimensions: inches (mm) 2002 Microchip Technology Inc. DS21483B-page 17 © TC9400/9401/9402 SALES AND SUPPORT Data Sheets Products supported by a preliminary Data Sheet may have an errata sheet describing minor operational differences and recommended workarounds. To determine if an errata sheet exists for a particular device, please contact one of the following: 1. 2. 3. Your local Microchip sales office The Microchip Corporate Literature Center U.S. FAX: (480) 792-7277 The Microchip Worldwide Site (www.microchip.com) Please specify which device, revision of silicon and Data Sheet (include Literature #) you are using. New Customer Notification System Register on our web site (www.microchip.com/cn) to receive the most current information on our products. © DS21483B-page 18 2002 Microchip Technology Inc. TC9400/9401/9402 Information contained in this publication regarding device applications and the like is intended through suggestion only and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. No representation or warranty is given and no liability is assumed by Microchip Technology Incorporated with respect to the accuracy or use of such information, or infringement of patents or other intellectual property rights arising from such use or otherwise. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, FilterLab, KEELOQ, microID, MPLAB, PIC, PICmicro, PICMASTER, PICSTART, PRO MATE, SEEVAL and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. dsPIC, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, microPort, Migratable Memory, MPASM, MPLIB, MPLINK, MPSIM, MXDEV, PICC, PICDEM, PICDEM.net, rfPIC, Select Mode and Total Endurance are trademarks of Microchip Technology Incorporated in the U.S.A. Serialized Quick Turn Programming (SQTP) is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. © 2002, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. 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