M29W128GL70N6F

128Mb 3V Embedded Parallel NOR Flash Features Parallel NOR Flash Embedded Memory M29W128GH, M29W128GL Features • VPP/WP# pin protection – Protects first or last block regardless of block protection settings • Software protection – Volatile protection – Nonvolatile protection – Password protection • Extended memory block – 128-word (256-byte) memory block for permanent, secure identification • Common flash interface – 64-bit security code • Low power consumption: Standby and automatic mode • Minimum 100,00 PROGRAM/ERASE cycles per block • RoHS compliant packages – 56-pin TSOP (N) 14mm x 20mm – 64-ball TBGA (ZA) 10mm x 13mm – 64-ball FBGA (ZS) 11mm x 13mm • Electronic signature – Manufacturer code: 0020h – M29W128GH uniform, last block protected by VPP/WP#: 227Eh + 2221h + 2201h – M29W128GL uniform, first block protected by VPP/WP#: 227Eh + 2221h + 2200h • Automotive device grade temperature – –40°C to +125°C (automotive grade certified) • Supply voltage – VCC = 2.7–3.6V (program, erase, read) – VCCQ = 1.65–3.6V (I/O buffers) – VPPH = 12V for fast program (optional) • Asynchronous random/page read – Page size: 8 words or 16 bytes – Page access: 25, 30ns – Random access: 60ns1, 70, 80ns • Fast program commands: 32-word (64-byte) write buffer • Enhanced buffered program commands: 256-word • Program time – 16µs per byte/word TYP – Chip program time: 5s with V PPH and 8s without VPPH • Memory organization – Uniform blocks: 128 main blocks, 128-Kbytes or 64-Kwords each • Program/erase controller – Embedded byte/word program algorithms • Program/erase suspend and resume capability – Read from any block during a PROGRAM SUSPEND operation – Read or program another block during an ERASE SUSPEND operation • Unlock bypass, block erase, chip erase, write to buffer, enhanced buffer program commands – Fast buffered/batch programming – Fast block/chip erase PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN Note: 1 1. The 60ns device is available upon customer request. Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 128Mb 3V Embedded Parallel NOR Flash Features Part Numbering Information Available with extended memory block prelocked by Micron. Devices are shipped from the factory with memory content bits erased to 1. For available options, such as packages or high/low protection, or for further information, contact your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification comparison by device type is available at www.micron.com/products. Contact the factory for devices not found. Table 1: Part Number Information Part Number Category Device type Category Details Notes M29 Operating voltage W = VCC = 2.7– 3.6V Device function 128GH = 128Mb (x8/x16) page, uniform block Flash memory, highest block protected by VPP/WP# 128GL = 128Mb (x8/x16) page, uniform block Flash memory, lowest block protected by VPP/WP# Speed Package 70 = 70ns 1 60 = 60ns 1, 2 7A = 70ns 1, 3 N = 56-pin TSOP, 14mm x 20mm ZA = 64-ball TBGA, 10mm x 13mm, 1mm pitch ZS = 64-ball Fortified BGA, 11mm x 13mm, 1mm pitch Temperature range 1 = 0 to 70°C 6 = –40°C to +85°C (IT) 3 = –40°C to +125°C (IT) Shipping options E = RoHS-compliant package, standard packing F = RoHS-compliant package, tape and reel packing Notes: 1. 80ns if VCCQ = 1.65V to VCC. 2. The 60ns device is available upon customer request. 3. Automotive qualified, available only with option 6. Qualified and characterized according to AEC Q100 and Q003 or equivalent; advanced screening according to AEC Q001 and Q002 or equivalent. PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Features Contents General Description ......................................................................................................................................... 7 Signal Assignments ........................................................................................................................................... 8 Signal Descriptions ......................................................................................................................................... 10 Memory Organization .................................................................................................................................... 11 Uniform Block Memory Map – 128Mb Density ............................................................................................. 11 Bus Operations ............................................................................................................................................... 12 Read .......................................................................................................................................................... 12 Write .......................................................................................................................................................... 12 Standby and Automatic Standby ................................................................................................................. 12 Output Disable ........................................................................................................................................... 13 Reset .......................................................................................................................................................... 13 Status Register ................................................................................................................................................ 14 Lock Register .................................................................................................................................................. 19 Standard Command Definitions – Address-Data Cycles .................................................................................... 22 READ Operations ........................................................................................................................................... 24 READ/RESET Command ............................................................................................................................ 24 READ CFI Command .................................................................................................................................. 24 AUTO SELECT Operations .............................................................................................................................. 25 AUTO SELECT Command ........................................................................................................................... 25 Bypass Operations .......................................................................................................................................... 28 UNLOCK BYPASS Command ...................................................................................................................... 28 UNLOCK BYPASS RESET Command ............................................................................................................ 28 Program Operations ....................................................................................................................................... 29 PROGRAM Command ................................................................................................................................ 29 UNLOCK BYPASS PROGRAM Command ..................................................................................................... 29 WRITE TO BUFFER PROGRAM Command .................................................................................................. 29 UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 32 WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 32 BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 32 PROGRAM SUSPEND Command ................................................................................................................ 32 PROGRAM RESUME Command .................................................................................................................. 33 ENHANCED BUFFERED PROGRAM Command ........................................................................................... 33 UNLOCK BYPASS ENHANCED BUFFERED PROGRAM Command ............................................................... 34 ENHANCED BUFFERED PROGRAM CONFIRM Command .......................................................................... 34 Erase Operations ............................................................................................................................................ 37 CHIP ERASE Command .............................................................................................................................. 37 UNLOCK BYPASS CHIP ERASE Command ................................................................................................... 37 BLOCK ERASE Command ........................................................................................................................... 37 UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 38 ERASE SUSPEND Command ....................................................................................................................... 38 ERASE RESUME Command ........................................................................................................................ 39 Block Protection Command Definitions – Address-Data Cycles ........................................................................ 40 Protection Operations .................................................................................................................................... 43 LOCK REGISTER Commands ...................................................................................................................... 43 PASSWORD PROTECTION Commands ....................................................................................................... 43 NONVOLATILE PROTECTION Commands .................................................................................................. 43 NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 45 VOLATILE PROTECTION Commands .......................................................................................................... 45 EXTENDED MEMORY BLOCK Commands .................................................................................................. 45 EXIT PROTECTION Command .................................................................................................................... 46 PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Features Device Protection ........................................................................................................................................... Hardware Protection .................................................................................................................................. Software Protection .................................................................................................................................... Volatile Protection Mode ............................................................................................................................. Nonvolatile Protection Mode ...................................................................................................................... Password Protection Mode .......................................................................................................................... Common Flash Interface ................................................................................................................................ Power-Up and Reset Characteristics ................................................................................................................ Absolute Ratings and Operating Conditions ..................................................................................................... DC Characteristics .......................................................................................................................................... Read AC Characteristics .................................................................................................................................. Write AC Characteristics ................................................................................................................................. Accelerated Program, Data Polling/Toggle AC Characteristics ........................................................................... Program/Erase Characteristics ........................................................................................................................ Package Dimensions ....................................................................................................................................... Revision History ............................................................................................................................................. Rev. B – 05/15 ............................................................................................................................................. Rev. A – 07/13 ............................................................................................................................................. PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 4 47 47 47 48 48 49 50 54 57 59 61 64 71 73 74 77 77 77 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Features List of Figures Figure 1: 128 Logic Diagram ............................................................................................................................ 7 Figure 2: 56-Pin TSOP (Top View) .................................................................................................................... 8 Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA ............................................................................................. 9 Figure 4: Data Polling Flowchart .................................................................................................................... 16 Figure 5: Toggle Bit Flowchart ........................................................................................................................ 17 Figure 6: Status Register Polling Flowchart ..................................................................................................... 18 Figure 7: Lock Register Program Flowchart ..................................................................................................... 20 Figure 8: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 31 Figure 9: ENHANCED BUFFERED PROGRAM Flowchart ................................................................................ 35 Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 44 Figure 11: Software Protection Scheme .......................................................................................................... 49 Figure 12: Power-Up Timing .......................................................................................................................... 54 Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 55 Figure 14: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 56 Figure 15: AC Measurement Load Circuit ....................................................................................................... 58 Figure 16: AC Measurement I/O Waveform ..................................................................................................... 58 Figure 17: Random Read AC Timing (8-Bit Mode) ........................................................................................... 62 Figure 18: Random Read AC Timing (16-Bit Mode) ......................................................................................... 62 Figure 19: BYTE Transition AC Timing ............................................................................................................ 63 Figure 20: Page Read AC Timing (16-Bit Mode) ............................................................................................... 63 Figure 21: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 65 Figure 22: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 66 Figure 23: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 68 Figure 24: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 69 Figure 25: Chip/Block Erase AC Timing (8-Bit Mode) ...................................................................................... 70 Figure 26: Accelerated Program AC Timing ..................................................................................................... 71 Figure 27: Data Polling AC Timing .................................................................................................................. 72 Figure 28: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 72 Figure 29: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 74 Figure 30: 64-Ball TBGA – 10mm x 13mm ....................................................................................................... 75 Figure 31: 64-Ball FBGA – 11mm x 13mm ....................................................................................................... 76 PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Features List of Tables Table 1: Part Number Information ................................................................................................................... 2 Table 2: Signal Descriptions ........................................................................................................................... 10 Table 3: x8 and x16 Blocks[127:0] ................................................................................................................... 11 Table 4: Bus Operations ................................................................................................................................. 12 Table 5: Status Register Bit Definitions ........................................................................................................... 14 Table 6: Operations and Corresponding Bit Settings ........................................................................................ 15 Table 7: Lock Register Bit Definitions ............................................................................................................. 19 Table 8: Block Protection Status ..................................................................................................................... 19 Table 9: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ............................................. 22 Table 10: Read Electronic Signature ............................................................................................................... 25 Table 11: Block Protection ............................................................................................................................. 27 Table 12: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 40 Table 13: Extended Memory Block Address and Data ...................................................................................... 45 Table 14: V PP/WP# Functions ......................................................................................................................... 47 Table 15: Query Structure Overview ............................................................................................................... 50 Table 16: CFI Query Identification String ........................................................................................................ 50 Table 17: CFI Query System Interface Information .......................................................................................... 51 Table 18: Device Geometry Definition ............................................................................................................ 51 Table 19: Primary Algorithm-Specific Extended Query Table ........................................................................... 52 Table 20: Security Code Area .......................................................................................................................... 53 Table 21: Power-Up Wait Timing Specifications .............................................................................................. 54 Table 22: Reset AC Characteristics .................................................................................................................. 55 Table 23: Absolute Maximum/Minimum Ratings ............................................................................................ 57 Table 24: Operating and AC Measurment Conditions ...................................................................................... 57 Table 25: Input/Output Capacitance .............................................................................................................. 58 Table 26: DC Current Characteristics .............................................................................................................. 59 Table 27: DC Voltage Characteristics .............................................................................................................. 60 Table 28: Read AC Characteristics .................................................................................................................. 61 Table 29: WE#-Controlled Write AC Characteristics ......................................................................................... 64 Table 30: CE#-Controlled Write AC Characteristics ......................................................................................... 67 Table 31: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 71 Table 32: Program/Erase Characteristics ........................................................................................................ 73 PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash General Description General Description The M29W is an asynchronous, uniform block, parallel NOR Flash memory device manufactured on 90nm single-level cell (SLC) technology. READ, ERASE, and PROGRAM operations are performed using a single low-voltage supply. Upon power-up, the device defaults to read array mode. The main memory array is divided into uniform blocks that can be erased independently so that valid data can be preserved while old data is purged. PROGRAM and ERASE commands are written to the command interface of the memory. An on-chip program/ erase controller simplifies the process of programming or erasing the memory by taking care of all special operations required to update the memory contents. The end of a PROGRAM or ERASE operation can be detected and any error condition can be identified. The command set required to control the device is consistent with JEDEC standards. CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic. The M29W supports asynchronous random read and page read from all blocks of the array. It features a write to buffer program capability that improves throughput by programming a buffer of 32 words in one command sequence. Also, in x16 mode, the enhanced buffered program capability improves throughput by programming 256 words in one command sequence. The device V PP/WP# signal enables faster programming. The device contains a 128-word (x16) and 256-byte (x8) extended memory block. The user can program this additional space and then protect it to permanently secure the contents. The device also features different levels of hardware and software protection to secure blocks from unwanted modification. Figure 1: 128 Logic Diagram VCC VCCQ VPP/WP# 15 A[22:0] DQ[14:0] DQ15/A-1 WE# CE# OE# RY/BY# RST# BYTE# VSS PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Signal Assignments Signal Assignments Figure 2: 56-Pin TSOP (Top View) RFU A22 A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RST# A21 VPP/WP# RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 RFU RFU Notes: PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 RFU RFU A16 BYTE# VSS DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 OE# VSS CE# A0 RFU VCCQ 1. A22 = A[MAX]. 2. A-1 is the least significant address bit in x8 mode. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Signal Assignments Figure 3: 64-Ball Fortified BGA and 64-Ball TBGA 1 2 RFU A3 3 4 5 6 7 8 8 7 6 A9 A13 RFU RFU A13 A9 5 4 3 2 1 A3 RFU A A A7 RY/BY# WE# WE# RY/BY# A7 B B RFU A4 A17 VPP/WP# RST# A8 A12 A22 A22 A12 A8 RST# VPP/WP# A17 A4 RFU RFU A2 A6 A18 A10 A14 RFU RFU A14 A10 A21 A2 RFU C C A21 A18 A6 D D RFU A1 A5 A20 A19 A11 A15 VCCQ VCCQ A15 A11 A19 A20 A5 A1 RFU RFU A0 D0 D2 D5 D7 A16 VSS VSS A16 D7 D5 D2 D0 A0 RFU E E F F VCCQ CE# D8 D10 D12 D14 BYTE# RFU RFU BYTE# D14 D12 D10 D8 CE# VCCQ RFU OE# D9 D11 VCC D13 D15/A-1 RFU RFU D15/A-1 D13 VCC D11 D9 OE# RFU G G H H RFU VSS D1 D3 D4 D6 VSS RFU RFU Top view – ball side down Notes: PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN VSS D6 D4 D3 D1 VSS RFU Bottom view – ball side up 1. A[22] = A[MAX]. 2. A-1 is the least significant address bit in x8 mode. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Signal Descriptions Signal Descriptions The signal description table below is a comprehensive list of signals for this device family. All signals listed may not be supported on this device. See Signal Assignments for information specific to this device. Table 2: Signal Descriptions Name Type Description A[MAX:0] Input Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the command interface of the program/erase controller. CE# Input Chip enable: Activates the device, enabling READ and WRITE operations to be performed. When CE# is HIGH, the device goes to standby and data outputs are at HIGH-Z. OE# Input Output enable: Controls the bus READ operation. WE# Input Write enable: Controls the bus WRITE operation of the command interface. VPP/WP# Input VPP/Write Protect: Provides WRITE PROTECT function and VPPH function. These functions protect the lowest or highest block and enable the device to enter unlock bypass mode, respectively. (Refer to Hardware Protection and Bypass Operations for details.) BYTE# Input Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is LOW, the device is in x8 mode; when HIGH, the device is in x16 mode. RST# Input Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details. DQ[7:0] I/O Data I/O: Outputs the data stored at the selected address during a READ operation. During WRITE operations, they represent the commands sent to the command interface of the internal state machine. DQ[14:8] I/O Data I/O: Outputs the data stored at the selected address during a READ operation when BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE operations, these bits are not used. When reading the status register, these bits should be ignored. DQ15/A-1 I/O Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves as the least significant bit of the address. Except where stated explicitly otherwise, DQ15 = data I/O (x16 mode); A-1 = address input (x8 mode). RY/BY# Output Ready busy: Open-drain output that can be used to identify when the device is performing a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW, and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, READ and WRITE operations cannot begin until RY/BY# goes High-Z (see RESET AC Specifications for more details). The use of an open-drain output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value will then indicate that one ( or more) of the devices is (are) busy. A 10K Ohm or bigger resistor is recommended as pull-up resistor to achieve 0.1V VOL. PDF: 09005aef84daa141 m29w_128mb.pdf - Rev. B 5/15 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 128Mb 3V Embedded Parallel NOR Flash Memory Organization Table 2: Signal Descriptions (Continued) Name Type VCC Supply Description Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations. The command interface is disabled when VCC