M29W320ET
M29W320EB
32 Mbit (4Mbx8 or 2Mbx16, Uniform Parameter Blocks, Boot Block)
3V supply Flash memory
Features
Supply voltage
– VCC = 2.7V to 3.6V for Program, Erase and
Read
– VPP =12V for Fast Program (optional)
Access times: 70, 90ns
Programming time
– 10μs per byte/word typical
– Double word/ Quadruple byte Program
TSOP48 (N)
12 x 20 mm
Memory Blocks
– Memory Array: 63 Main Blocks
– 8 Parameter Blocks (Top or Bottom
Location)
FBGA
TFBGA48 (ZE)
6 x 8 mm
BGA
FBGA64 (ZS)
11 x 13 mm
Erase Suspend and Resume modes
– Read and Program another Block during
Erase Suspend
Unlock Bypass Program command
– Faster Production/Batch Programming
VPP/WP pin for fast Program and Write Protect
Temporary Block Unprotection mode
Common Flash Interface
– 64 bit Security code
Extended memory Block
– Extra block used as security block or to
store additional information
Low power consumption
– Standby and Automatic Standby
100,000 Program/Erase cycles per block
Electronic signature
– Manufacturer code: 0020h
– Top Device code M29W320ET: 2256h
– Bottom Device code M29W320EB: 2257h
RoHS® packages available
May 2009
Rev 9
1/65
www.numonyx.com
1
Contents
M29W320ET, M29W320EB
Contents
1
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2
Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3
4
2/65
2.1
Address Inputs (A0-A20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2
Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.3
Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4
Data Input/Output or Address Input (DQ15A–1) . . . . . . . . . . . . . . . . . . . 14
2.5
Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6
Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7
Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8
VPP/Write Protect (VPP/WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9
Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.10
Ready/Busy Output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.11
Byte/word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.12
VCC Supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.13
VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5
Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6
Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.1
Electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.6.2
Block Protect and Chip Unprotect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1
Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2
Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3
Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
4.4
Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
M29W320ET, M29W320EB
4.5
5
Contents
Fast Program commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.1
Quadruple byte Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.5.2
Double word Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.6
Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.7
Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.8
Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.9
Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.10
Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.11
Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.12
Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.13
Enter Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.14
Exit Extended Block command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
4.15
Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . . 26
Status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.1
Data Polling bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.2
Toggle bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3
Error bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.4
Erase Timer bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.5
Alternative Toggle bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
7
DC and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
8
Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
9
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Appendix A Block Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Appendix C Extended memory Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.1
Factory Locked Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
9.2
Customer Lockable Extended Block . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
3/65
Contents
M29W320ET, M29W320EB
Appendix D Block Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
D.1
Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
D.2
In-system technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
4/65
M29W320ET, M29W320EB
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Commands, 8-bit mode, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 29
Status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Read ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Write ac characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write ac characteristics, Chip Enable controlled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Toggle and alternative Toggle bits ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Reset/Block Temporary Unprotect ac characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, package mechanical data . . . . . . . 43
TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, package mechanical data. . . . . . . . . . . 44
FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data . . . 45
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Top Boot Block Addresses, M29W320ET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Bottom Boot Block Addresses, M29W320EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Primary Algorithm-specific extended Query table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Security code area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Extended Block Address and data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Programmer technique Bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64
5/65
List of figures
M29W320ET, M29W320EB
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
6/65
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
TFBGA48 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
FBGA64 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Block Addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
AC measurement Load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Read mode ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Write ac waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Write ac waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Toggle and alternative Toggle bits mechanism, Chip Enable controlled . . . . . . . . . . . . . . 41
Toggle and alternative Toggle bits mechanism, Output Enable controlled. . . . . . . . . . . . . 41
Reset/Block Temporary Unprotect ac waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Accelerated Program Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
TSOP48 Lead Plastic Thin Small Outline, 12x20 mm package outline, top view. . . . . . . . 43
TFBGA48 6x8mm-6x8 Ball Array, 0.8mm Pitch, package outline, bottom view . . . . . . . . . 44
FBGA64 11 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline, bottom view . 45
Programmer Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
In-system Equipment Group Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
In-system Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
M29W320ET, M29W320EB
1
Description
Description
The M29W320E is a 32 Mbit (4Mb x8 or 2Mb x16) non-volatile memory that can be read,
erased and reprogrammed. These operations can be performed using a single low voltage
(2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode.
The device features an asymmetrical block architecture. The M29W320E has an array of 8
parameter and 63 main blocks. M29W320ET locates the Parameter Blocks at the top of the
memory address space while the M29W320EB locates the Parameter Blocks starting from
the bottom.
M29W320E has an extra 32 Kword (x16 mode) or 64 Kbyte (x8 mode) block, the Extended
Block, that can be accessed using a dedicated command. The Extended Block can be
protected and so is useful for storing security information. However the protection is
irreversible, once protected the protection cannot be undone.
Each block can be erased independently so it is possible to preserve valid data while old
data is erased. The blocks can be protected to prevent accidental Program or Erase
commands from modifying the memory. Program and Erase commands are written to the
Command interface of the memory. An on-chip Program/Erase Controller simplifies the
process of programming or erasing the memory by taking care of all of the special
operations that are required to update the memory contents. The end of a program or erase
operation can be detected and any error conditions identified. The command set required to
control the memory is consistent with JEDEC standards.
Chip Enable, Output Enable and Write Enable signals control the bus operation of the
memory. They allow simple connection to most microprocessors, often without additional
logic.
The memory is offered in TSOP48 (12x20mm), and TFBGA48 (6x8mm, 0.8mm pitch)
packages. In order to meet environmental requirements, Numonyx offers the M29W320E in
RoHS packages, which are are Lead-free. The category of second Level Interconnect is
marked on the package and on the inner box label, in compliance with JEDEC Standard
JESD97. The maximum ratings related to soldering conditions are also marked on the inner
box label.
The memory is supplied with all the bits erased (set to ’1’).
7/65
Description
M29W320ET, M29W320EB
Figure 1.
Logic diagram
VCC VPP/WP
21
15
A0-A20
DQ0-DQ14
DQ15A–1
W
E
M29W320ET
M29W320EB
G
BYTE
RB
RP
VSS
AI09346
Table 1.
8/65
Signal names
A0-A20
Address Inputs
DQ0-DQ7
Data Inputs/Outputs
DQ8-DQ14
Data Inputs/Outputs
DQ15A–1
Data Input/Output or Address Input
E
Chip Enable
G
Output Enable
W
Write Enable
RP
Reset/Block Temporary Unprotect
RB
Ready/Busy Output
BYTE
Byte/word Organization Select
VCC
Supply voltage
VPP /WP
VPP/Write Protect
VSS
Ground
NC
Not Connected Internally
M29W320ET, M29W320EB
Figure 2.
Description
TSOP connections
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
W
RP
NC
VPP/WP
RB
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
48
M29W320ET
M29W320EB
12
13
37
36
24
25
A16
BYTE
VSS
DQ15A–1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
G
VSS
E
A0
AI09347
9/65
Description
Figure 3.
M29W320ET, M29W320EB
TFBGA48 connections (top view through package)
1
2
3
4
5
6
A
A3
A7
RB
W
A9
A13
B
A4
A17
VPP/WP
RP
A8
A12
C
A2
A6
A18
NC
A10
A14
D
A1
A5
A20
A19
A11
A15
E
A0
DQ0
DQ2
DQ5
DQ7
A16
F
E
DQ8
DQ10
DQ12
DQ14
BYTE
G
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
H
VSS
DQ1
DQ3
DQ4
DQ6
VSS
AI08084
10/65
M29W320ET, M29W320EB
Figure 4.
Description
FBGA64 connections (top view through package)
7
8
A9
A13
NC
RP
A8
A12
NC
A18
NC
A10
A14
NC
A5
A20
A19
A11
A15
VCC
A0
DQ0
DQ2
DQ5
DQ7
A16
VSS
VCC
E
DQ8
DQ10
DQ12
DQ14
BYTE
NC
NC
G
DQ9
DQ11
VCC
DQ13
DQ15
A–1
NC
NC
VSS
DQ1
DQ3
DQ4
DQ6
VSS
NC
1
2
3
4
5
A
NC
A3
A7
RB
W
B
NC
A4
A17
VPP/ WP
C
NC
A2
A6
D
NC
A1
E
NC
F
G
H
6
AI12719_bis
11/65
Description
Figure 5.
M29W320ET, M29W320EB
Block Addresses (x8)
Top Boot Block (x8)
Address lines A20-A0, DQ15A-1
000000h
00FFFFh
Bottom Boot Block (x8)
Address lines A20-A0, DQ15A-1
000000h
64 KByte or
32 KWord
001FFFh
8 KByte or
4 KWord
Total of 8
Parameter
Blocks (1)
2F0000h
2FFFFFh
300000h
30FFFFh
3E0000h
3EFFFFh
3F0000h
3F1FFFh
64 KByte or
32 KWord
00E000h
Total of 63
Main Blocks
64 KByte or
32 KWord
00FFFFh
010000h
01FFFFh
0F0000h
64 KByte or
32 KWord
0FFFFFh
100000h
8 KByte or
4 KWord
10FFFFh
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 63
Main Blocks
64 KByte or
32 KWord
Total of 8
Parameter
Blocks (1)
3FE000h
3FFFFFh
8 KByte or
4 KWord
3F0000h
3FFFFFh
64 KByte or
32 KWord
Note 1. Used as Extended Block Addresses in Extended Block mode.
1. See also Appendix A: Block Addresses, Table 21 and Table 22 for a full listing of the Block Addresses.
12/65
AI09348
M29W320ET, M29W320EB
Figure 6.
Description
Block Addresses (x16)
Top Boot Block (x16)
Address lines A20-A0
000000h
007FFFh
Bottom Boot Block (x16)
Address lines A20-A0
000000h
64 KByte or
32 KWord
000FFFh
8 KByte or
4 KWord
Total of 8
Parameter
Blocks (1)
178000h
17FFFFh
180000h
187FFFh
1F0000h
1F7FFFh
1F8000h
1F8FFFh
64 KByte or
32 KWord
64 KByte or
32 KWord
007000h
Total of 63
Main Blocks
007FFFh
008000h
00FFFFh
078000h
64 KByte or
32 KWord
07FFFFh
080000h
8 KByte or
4 KWord
087FFFh
8 KByte or
4 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
64 KByte or
32 KWord
Total of 63
Main Blocks
Total of 8
Parameter
Blocks (1)
1FF000h
1FFFFFh
8 KByte or
4 KWord
1F8000h
1FFFFFh
64 KByte or
32 KWord
Note 1. Used as Extended Block Addresses in Extended Block mode.
AI09349
1. See also Appendix A: Block Addresses, Table 21 and Table 22 for a full listing of the Block Addresses.
13/65
Signal descriptions
2
M29W320ET, M29W320EB
Signal descriptions
See Figure 1: Logic diagram, and Table 1: Signal names, for a brief overview of the signals
connected to this device.
2.1
Address Inputs (A0-A20)
The Address Inputs select the cells in the memory array to access during Bus Read
operations. During Bus Write operations they control the commands sent to the Command
interface of the Program/Erase Controller.
2.2
Data Inputs/Outputs (DQ0-DQ7)
The Data I/O outputs the data stored at the selected address during a Bus Read operation.
During Bus Write operations they represent the commands sent to the Command interface
of the Program/Erase Controller.
2.3
Data Inputs/Outputs (DQ8-DQ14)
The Data I/O outputs the data stored at the selected address during a Bus Read operation
when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high
impedance. During Bus Write operations the Command Register does not use these bits.
When reading the Status register these bits should be ignored.
2.4
Data Input/Output or Address Input (DQ15A–1)
When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14).
When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the
LSB of the addressed word, DQ15A–1 High will select the MSB. Throughout the text
consider references to the Data Input/Output to include this pin when BYTE is High and
references to the Address Inputs to include this pin when BYTE is Low except when stated
explicitly otherwise.
2.5
Chip Enable (E)
The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to
be performed. When Chip Enable is High, VIH, all other pins are ignored.
2.6
Output Enable (G)
The Output Enable, G, controls the Bus Read operation of the memory.
14/65
M29W320ET, M29W320EB
2.7
Signal descriptions
Write Enable (W)
The Write Enable, W, controls the Bus Write operation of the memory’s Command interface.
2.8
VPP/Write Protect (VPP/WP)
The VPP/Write Protect pin provides two functions. The VPP function allows the memory to
use an external high voltage power supply to reduce the time required for Program
operations. This is achieved by bypassing the unlock cycles and/or using the Double word
or Quadruple byte Program commands.
The Write Protect function provides a hardware method of protecting the two outermost boot
blocks. When VPP/Write Protect is Low, VIL, the memory protects the two outermost boot
blocks; Program and Erase operations in these blocks are ignored while VPP/Write Protect
is Low, even when RP is at VID.
When VPP/Write Protect is High, VIH, the memory reverts to the previous protection status
of the two outermost boot blocks. Program and Erase operations can now modify the data
in these blocks unless the blocks are protected using Block Protection.
When VPP/Write Protect is raised to VPP the memory automatically enters the Unlock
Bypass mode. When VPP/Write Protect returns to VIH or VIL normal operation resumes.
During Unlock Bypass Program operations the memory draws IPP from the pin to supply the
programming circuits. See the description of the Unlock Bypass command in the Command
interface section. The transitions from VIH to VPP and from VPP to VIH must be slower than
tVHVPP, see Figure 17
Never raise VPP/Write Protect to VPP from any mode except Read mode, otherwise the
memory may be left in an indeterminate state.
The VPP/Write Protect pin must not be left floating or unconnected or the device may
become unreliable. A 0.1μF capacitor should be connected between the VPP/Write Protect
pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB
track widths must be sufficient to carry the currents required during Unlock Bypass Program,
IPP.
2.9
Reset/Block Temporary Unprotect (RP)
The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the
memory or to temporarily unprotect all Blocks that have been protected.
Note that if VPP/WP is at VIL, then the two outermost boot blocks will remain protected even
if RP is at VID.
A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at
least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be
ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last.
See the Ready/Busy Output section, Table 16 and Figure 16: Reset/Block Temporary
Unprotect ac waveforms, for more details.
Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program
and Erase operations on all blocks will be possible. The transition from VIH to VID must be
slower than tPHPHH.
15/65
Signal descriptions
2.10
M29W320ET, M29W320EB
Ready/Busy Output (RB)
The Ready/Busy pin is an open-drain output that can be used to identify when the device is
performing a Program or Erase operation. During Program or Erase operations Ready/Busy
is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and
Erase Suspend mode.
After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy
becomes high-impedance. See Table 16 and Figure 16: Reset/Block Temporary Unprotect
ac waveforms.
The use of an open-drain output allows the Ready/Busy pins from several memories to be
connected to a single pull-up resistor. A Low will then indicate that one, or more, of the
memories is busy.
2.11
Byte/word Organization Select (BYTE)
The byte/word Organization Select pin is used to switch between the x8 and x16 Bus modes
of the memory. When byte/word Organization Select is Low, VIL, the memory is in x8 mode,
when it is High, VIH, the memory is in x16 mode.
2.12
VCC Supply voltage
VCC provides the power supply for all operations (Read, Program and Erase).
The Command interface is disabled when the VCC Supply voltage is less than the Lockout
voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data
during power up, power down and power surges. If the Program/Erase Controller is
programming or erasing during this time then the operation aborts and the memory contents
being altered will be invalid.
A 0.1μF capacitor should be connected between the VCC Supply voltage pin and the VSS
Ground pin to decouple the current surges from the power supply. The PCB track widths
must be sufficient to carry the currents required during Program and Erase operations, ICC3.
2.13
VSS Ground
VSS is the reference for all voltage measurements. The device features two VSS pins which
must be both connected to the system ground.
16/65
M29W320ET, M29W320EB
3
Bus operations
Bus operations
There are five standard bus operations that control the device. These are Bus Read, Bus
Write, Output Disable, Standby and Automatic Standby.
See Table 2 and Table 3, Bus operations, for a summary. Typically glitches of less than 5ns
on Chip Enable or Write Enable are ignored by the memory and do not affect bus
operations.
3.1
Bus Read
Bus Read operations read from the memory cells, or specific registers in the Command
interface. A valid Bus Read operation involves setting the desired address on the Address
Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write
Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 11: Read mode
ac waveforms, and Table 12: Read ac characteristics, for details of when the output
becomes valid.
3.2
Bus Write
Bus Write operations write to the Command interface. A valid Bus Write operation begins by
setting the desired address on the Address Inputs. The Address Inputs are latched by the
Command interface on the falling edge of Chip Enable or Write Enable, whichever occurs
last. The Data Inputs/Outputs are latched by the Command interface on the rising edge of
Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH,
during the whole Bus Write operation. See Figure 12 and Figure 13, Write ac waveforms,
and Table 13 and Table 14, Write ac characteristics, for details of the timing requirements.
3.3
Output Disable
The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH .
3.4
Standby
When Chip Enable is High, VIH, the memory enters Standby mode and the Data
Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply current to
the Standby Supply current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the
Standby current level see Table 11: DC characteristics.
During program or erase operations the memory will continue to use the Program/Erase
Supply current, ICC3, for Program or Erase operations until the operation completes.
17/65
Bus operations
3.5
M29W320ET, M29W320EB
Automatic Standby
If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 300ns or
more the memory enters Automatic Standby where the internal Supply current is reduced to
the Standby Supply current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read
operation is in progress.
3.6
Special bus operations
Additional bus operations can be performed to read the Electronic signature and also to
apply and remove Block Protection. These bus operations are intended for use by
programming equipment and are not usually used in applications. They require VID to be
applied to some pins.
3.6.1
Electronic signature
The memory has two codes, the manufacturer code and the device code, that can be read
to identify the memory. These codes can be read by applying the signals listed in Table 2
and Table 3, Bus operations.
3.6.2
Block Protect and Chip Unprotect
Groups of blocks can be protected against accidental Program or Erase. The Protection
groups are shown in Appendix A: Block Addresses, Table 21 and Table 22, Block
Addresses. The whole chip can be unprotected to allow the data inside the blocks to be
changed.
The VPP/Write Protect pin can be used to protect the two outermost boot blocks. When
VPP /Write Protect is at VIL the two outermost boot blocks are protected and remain
protected regardless of the Block Protection Status or the Reset/Block Temporary
Unprotect pin status.
Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
18/65
M29W320ET, M29W320EB
Table 2.
Bus operations
Bus operations, BYTE = VIL(1)
Data Inputs/Outputs
Operation
E
G
Address Inputs
DQ15A–1, A0-A20
W
DQ14DQ8
DQ7-DQ0
Bus Read
VIL
VIL
VIH
Cell Address
Hi-Z
Data Output
Bus Write
VIL
VIH
VIL
Command Address
Hi-Z
Data Input
X
VIH
VIH
X
Hi-Z
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Hi-Z
Read Manufacturer
code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID ,
Others VIL or VIH
Hi-Z
20h
Read Device code
VIL
VIL
VIH
A0 = VIH, A1 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z
56h (M29W320ET)
57h (M29W320EB)
Extended memory
Block Verify code
VIL
VIL
VIH
A0 = VIH, A1 = VIH, A6 = VIL,
A9 = VID, Others VIL or VIH
Hi-Z
81h (factory locked)
01h (factory unlocked)
Output Disable
1. X = VIL or VIH .
19/65
Bus operations
Table 3.
M29W320ET, M29W320EB
Bus operations, BYTE = VIH(1)
Operation
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
E
G
W
Bus Read
VIL
VIL
VIH
Cell Address
Bus Write
VIL
VIH
VIL
Command Address
X
VIH
VIH
X
Hi-Z
Standby
VIH
X
X
X
Hi-Z
Read Manufacturer
code
VIL
VIL
VIH
A0 = VIL, A1 = VIL, A9 = VID,
Others VIL or VIH
0020h
Read Device code
VIL
VIL
VIH
A0 = VIH, A1 = VIL, A9 = VID ,
Others VIL or VIH
2256h (M29W320ET)
2257h (M29W320EB)
Extended memory
Block Verify code
VIL
VIL
VIH
A0 = VIH, A1 = VIH, A6 = VIL ,
A9 = VID, Others VIL or VIH
81h (factory locked)
01h (factory unlocked)
Output Disable
1. X = VIL or VIH .
20/65
Data Output
Data Input
M29W320ET, M29W320EB
4
Command interface
Command interface
All Bus Write operations to the memory are interpreted by the Command interface.
Commands consist of one or more sequential Bus Write operations. Failure to observe a
valid sequence of Bus Write operations will result in the memory returning to Read mode.
The long command sequences are imposed to maximize data security.
The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being
used, for a summary of the commands.
4.1
Read/Reset command
The Read/Reset command returns the memory to its Read mode. It also resets the errors in
the Status register. Either one or three Bus Write operations can be used to issue the
Read/Reset command.
The Read/Reset command can be issued, between Bus Write cycles before the start of a
program or erase operation, to return the device to read mode. If the Read/Reset command
is issued during the time-out of a Block erase operation then the memory will take up to
10μs to abort. During the abort period no valid data can be read from the memory. The
Read/Reset command will not abort an Erase operation when issued while in Erase
Suspend.
4.2
Auto Select command
The Auto Select command is used to read the Manufacturer code, the Device code, the
Block Protection Status and the Extended memory Block Verify code. Three consecutive
Bus Write operations are required to issue the Auto Select command. The memory remains
in Auto Select mode until a Read/Reset or CFI Query command is issued.
In Auto Select mode the Manufacturer code can be read using a Bus Read operation with
A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH.
The Device code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The
other address bits may be set to either VIL or VIH.
The Block Protection Status of each block can be read using a Bus Read operation with A0
= VIL, A1 = VIH and A12-A20 specifying the block address. The other address bits may be
set to either VIL or VIH. If the addressed block is protected then 01h is output on Data
Inputs/Outputs DQ0-DQ7, otherwise 00h is output.
21/65
Command interface
4.3
M29W320ET, M29W320EB
Read CFI Query command
The Read CFI Query Command is used to read data from the Common Flash Interface
(CFI) memory Area. This command is valid when the device is in the Read Array mode, or
when the device is in Auto Select mode.
One Bus Write cycle is required to issue the Read CFI Query Command. Once the
command is issued subsequent Bus Read operations read from the Common Flash
Interface memory Area.
The Read/Reset command must be issued to return the device to the previous mode (the
Read Array mode or Auto Select mode). A second Read/Reset command would be needed
if the device is to be put in the Read Array mode from Auto Select mode.
See Appendix B: Common Flash Interface (CFI), Table 23, Table 24, Table 25, Table 26,
Table 27 and Table 28 for details on the information contained in the Common Flash
Interface (CFI) memory area.
4.4
Program command
The Program command can be used to program a value to one address in the memory
array at a time. The command requires four Bus Write operations, the final write operation
latches the address and data, and starts the Program/Erase Controller.
If the address falls in a protected block then the Program command is ignored, the data
remains unchanged. The Status register is never read and no error condition is given.
During the program operation the memory will ignore all commands. It is not possible to
issue any command to abort or pause the operation. After programming has started, Bus
Read operations output the Status register content. See Section 5: Status register for more
details. Typical program times are given in Table 6
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase
Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’.
22/65
M29W320ET, M29W320EB
4.5
Command interface
Fast Program commands
There are two Fast Program commands available to improve the programming throughput,
by writing several adjacent words or bytes in parallel. The Quadruple byte Program
command is available for x8 operations, while the Double word Program command is
available for x16 operations.
Fast Program commands should not be attempted when VPP/WP is not at VPP. Care must
be taken because applying a 12V VPP voltage to the VPP/WP pin will temporarily unprotect
any protected block.
After programming has started, Bus Read operations output the Status register content.
After the program operation has completed the memory will return to the Read mode, unless
an error has occurred. When an error occurs Bus Read operations will continue to output
the Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
Note that the Fast Program commands cannot change a bit set at ’0’ back to ’1’. One of the
Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’
to ’1’.
Typical Program times are given in Table 6: Program, Erase times and Program, Erase
Endurance cycles
4.5.1
Quadruple byte Program command
The Quadruple byte Program command is used to write a page of four adjacent bytes in
parallel. The four bytes must differ only for addresses A0, DQ15A-1. Five bus write cycles
are necessary to issue the Quadruple byte Program command.
4.5.2
1.
2.
The first bus cycle sets up the Quadruple byte Program command.
The second bus cycle latches the Address and the Data of the first byte to be written.
3.
The third bus cycle latches the Address and the Data of the second byte to be written.
4.
The fourth bus cycle latches the Address and the Data of the third byte to be written.
5.
The fifth bus cycle latches the Address and the Data of the fourth byte to be written and
starts the Program/Erase Controller.
Double word Program command
The Double word Program command is used to write a page of two adjacent words in
parallel. The two words must differ only for the address A0.
Three bus write cycles are necessary to issue the Double word Program command.
1.
The first bus cycle sets up the Double word Program command.
2.
The second bus cycle latches the Address and the Data of the first word to be written.
3.
The third bus cycle latches the Address and the Data of the second word to be written
and starts the Program/Erase Controller.
23/65
Command interface
4.6
M29W320ET, M29W320EB
Unlock Bypass command
The Unlock Bypass command is used in conjunction with the Unlock Bypass Program
command to program the memory faster than with the standard program commands. When
the cycle time to the device is long, considerable time saving can be made by using these
commands. Three Bus Write operations are required to issue the Unlock Bypass command.
Once the Unlock Bypass command has been issued the memory enters Unlock Bypass
mode. The Unlock Bypass Program command can then be issued to program addresses or
the Unlock Bypass Reset command can be issued to return to Read mode. In Unlock
Bypass mode the memory can be read as if in Read mode.
When VPP is applied to the VPP/Write Protect pin the memory automatically enters the
Unlock Bypass mode and the Unlock Bypass Program command can be issued
immediately. Care must be taken because applying a 12V VPP voltage to the VPP/WP pin
will temporarily unprotect any protected block.
4.7
Unlock Bypass Program command
The Unlock Bypass Program command can be used to program one address in the memory
array at a time. The command requires two Bus Write operations, the final write operation
latches the address and data, and starts the Program/Erase Controller.
The Program operation using the Unlock Bypass Program command behaves identically to
the Program operation using the Program command. The operation cannot be aborted, a
Bus Read operation outputs the Status register. See the Program command for details on
the behavior.
4.8
Unlock Bypass Reset command
The Unlock Bypass Reset command can be used to return to Read/Reset mode from
Unlock Bypass mode. Two Bus Write operations are required to issue the Unlock Bypass
Reset command. Read/Reset command does not exit from Unlock Bypass mode.
4.9
Chip Erase command
The Chip Erase command can be used to erase the entire chip. Six Bus Write operations
are required to issue the Chip Erase Command and start the Program/Erase Controller.
If any blocks are protected then these are ignored and all the other blocks are erased. If all
of the blocks are protected the Chip Erase operation appears to start but will terminate
within about 100μs, leaving the data unchanged. No error condition is given when protected
blocks are ignored.
During the erase operation the memory will ignore all commands, including the Erase
Suspend command. It is not possible to issue any command to abort the operation. Typical
chip erase times are given in Table 6. All Bus Read operations during the Chip Erase
operation will output the Status register on the Data Inputs/Outputs. See the section on the
Status register for more details.
After the Chip Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs the memory will continue to output the
24/65
M29W320ET, M29W320EB
Command interface
Status register. A Read/Reset command must be issued to reset the error condition and
return to Read mode.
The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All
previous data is lost.
4.10
Block Erase command
The Block Erase command can be used to erase a list of one or more blocks. It sets all of
the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is
lost.
Six Bus Write operations are required to select the first block in the list. Each additional
block in the list can be selected by repeating the sixth Bus Write operation using the address
of the additional block. The Block Erase operation starts the Program/Erase Controller after
a time-out period of 50μs after the last Bus Write operation. Once the Program/Erase
Controller starts it is not possible to select any more blocks. Each additional block must
therefore be selected within 50μs of the last block. The 50μs timer restarts when an
additional block is selected. After the sixth Bus Write operation a Bus Read operation will
output the Status register. See the Status register section for details on how to identify if the
Program/Erase Controller has started the Block Erase operation.
If any selected blocks are protected then these are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected the Block Erase operation appears to
start but will terminate within about 100μs, leaving the data unchanged. No error condition is
given when protected blocks are ignored.
During the Block Erase operation the memory will ignore all commands except the Erase
Suspend command and the Read/Reset command which is only accepted during the 50μs
time-out period. Typical block erase times are given in Table 6.
After the Erase operation has started all Bus Read operations will output the Status register
on the Data Inputs/Outputs. See the section on the Status register for more details.
After the Block Erase operation has completed the memory will return to the Read mode,
unless an error has occurred. When an error occurs Bus Read operations will continue to
output the Status register. A Read/Reset command must be issued to reset the error
condition and return to Read mode.
4.11
Erase Suspend command
The Erase Suspend Command may be used to temporarily suspend a Block Erase
operation and return the memory to Read mode. The command requires one Bus Write
operation.
The Program/Erase Controller will suspend within the Erase Suspend Latency time of the
Erase Suspend Command being issued. Once the Program/Erase Controller has stopped
the memory will be set to Read mode and the Erase will be suspended. If the Erase
Suspend command is issued during the period when the memory is waiting for an additional
block (before the Program/Erase Controller starts) then the Erase is suspended immediately
and will start immediately when the Erase Resume Command is issued. It is not possible to
select any further blocks to erase after the Erase Resume.
25/65
Command interface
M29W320ET, M29W320EB
During Erase Suspend it is possible to Read and Program cells in blocks that are not being
erased; both Read and Program operations behave as normal on these blocks. If any
attempt is made to program in a protected block or in the suspended block then the Program
command is ignored and the data remains unchanged. The Status register is not read and
no error condition is given. Reading from blocks that are being erased will output the Status
register.
It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands
during an Erase Suspend. The Read/Reset command must be issued to return the device to
Read Array mode before the Resume command will be accepted.
During Erase Suspend a Bus Read operation to the Extended Block will output the
Extended Block data.
4.12
Erase Resume command
The Erase Resume command must be used to restart the Program/Erase Controller after an
Erase Suspend. The device must be in Read Array mode before the Resume command will
be accepted. An erase can be suspended and resumed more than once.
4.13
Enter Extended Block command
The M29W320E has an extra 64Kbyte block (Extended Block) that can only be accessed
using the Enter Extended Block command. Three Bus write cycles are required to issue the
Extended Block command. Once the command has been issued the device enters
Extended Block mode where all Bus Read or Program operations to the Boot Block
addresses access the Extended Block. The Extended Block (with the same address as the
boot block) cannot be erased, and can be treated as one-time programmable (OTP)
memory. In Extended Block mode the Boot Blocks are not accessible.
To exit from the Extended Block mode the Exit Extended Block command must be issued.
The Extended Block can be protected, however once protected the protection cannot be
undone.
4.14
Exit Extended Block command
The Exit Extended Block command is used to exit from the Extended Block mode and return
the device to Read mode. Four Bus Write operations are required to issue the command.
4.15
Block Protect and Chip Unprotect commands
Groups of blocks can be protected against accidental Program or Erase. The Protection
groups are shown in Appendix A: Block Addresses, Table 21 and Table 22, Block
Addresses. The whole chip can be unprotected to allow the data inside the blocks to be
changed.
Block Protect and Chip Unprotect operations are described in Appendix D: Block Protection.
26/65
M29W320ET, M29W320EB
Table 4.
Command interface
Commands, 16-bit mode, BYTE = VIH(1)(2)
Command
Length
Bus Write operations
1st
2nd
3rd
Addr Data Addr Data
Addr
4th
6th
Data Addr Data Addr Data Addr Data
1
X
F0
3
555
AA
2AA
55
X
F0
Auto Select
3
555
AA
2AA
55
(BA)
555
90
Program
4
555
AA
2AA
55
555
A0
Double word Program
3
555
50
PA0
PD0
PA1
PD1
Unlock Bypass
3
555
AA
2AA
55
555
20
Unlock Bypass
Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
555
AA
2AA
55
555
Block Erase
6+
555
AA
2AA
55
Erase Suspend
1
BA
B0
Erase Resume
1
BA
30
Read CFI Query
1
55
98
Enter Extended Block
3
555
AA
2AA
Exit Extended Block
4
555
AA
2AA
Read/Reset
5th
PA
PD
80
555
AA
2AA
55
555
10
555
80
555
AA
2AA
55
BA
30
55
555
88
55
555
90
X
00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
27/65
Command interface
Table 5.
M29W320ET, M29W320EB
Commands, 8-bit mode, BYTE = VIL(1)(2)
Command
Length
Bus Write operations
1st
2nd
Add
Data
1
X
F0
3
AAA
Auto Select
3
Program
3rd
4th
Add
Data
Add
Data
AA
555
55
X
F0
AAA
AA
555
55
(BA)
AAA
90
4
AAA
AA
555
55
AAA
Quadruple byte Program
5
AAA
55
PA0
PD0
Unlock Bypass
3
AAA
AA
555
55
Unlock Bypass Program
2
X
A0
PA
PD
Unlock Bypass Reset
2
X
90
X
00
Chip Erase
6
AAA
AA
555
Block Erase
6+ AAA
AA
Erase Suspend
1
BA
B0
Erase Resume
1
BA
30
Read CFI Query
1
AA
98
Enter Extended Block
3
AAA
Exit Extended Block
4
AAA
Read/Reset
5th
6th
Add
Data
Add Data Add Data
A0
PA
PD
PA1
PD1
PA2
PD2
PA3
PD3
AAA
20
55
AAA
80
AAA
AA
555
55
AAA
10
555
55
AAA
80
AAA
AA
555
55
BA
30
AA
555
55
AAA
88
AA
555
55
AAA
90
X
00
1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in
hexadecimal.
2. The Command interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A20, DQ8-DQ14 and DQ15
are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH.
28/65
M29W320ET, M29W320EB
Table 6.
Command interface
Program, Erase times and Program, Erase Endurance cycles
Parameter
Min
Chip Erase
Block Erase (64 Kbytes)
Typ(1)(2)
Max(2)
Unit
40
200(3)
s
0.8
6(3)
s
(4)
Erase Suspend Latency time
50
μs
10
200(4)
μs
10
200
(3)
μs
40
200
(3)
s
Chip Program (word by word)
20
100(3)
s
Chip Program (Quadruple byte or Double word)
10
100(3)
s
Program (byte or word)
Double word Program (byte or word)
Chip Program (byte by byte)
Program/Erase Cycles (per Block)
Data Retention
100,000
cycles
20
years
1. Typical values measured at room temperature and nominal voltages.
2. Sampled, but not 100% tested.
3. Maximum value measured at worst case conditions for both temperature and V CC after 100,00 program/erase cycles.
4. Maximum value measured at worst case conditions for both temperature and V CC .
29/65
Status register
5
M29W320ET, M29W320EB
Status register
The M29W320E has one Status register. It provides information on the current or previous
Program or Erase operations. The various bits convey information and errors on the
operation. Bus Read operations from any address, always read the Status register during
Program and Erase operations. It is also read during Erase Suspend when an address
within a block being erased is accessed.
The bits in the Status register are summarized in Table 7: Status register bits.
5.1
Data Polling bit (DQ7)
The Data Polling bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Data
Polling bit is output on DQ7 when the Status register is read.
During Program operations the Data Polling bit outputs the complement of the bit being
programmed to DQ7. After successful completion of the Program operation the memory
returns to Read mode and Bus Read operations from the address just programmed output
DQ7, not its complement.
During Erase operations the Data Polling bit outputs ’0’, the complement of the erased state
of DQ7. After successful completion of the Erase operation the memory returns to Read
mode.
In Erase Suspend mode the Data Polling bit will output a ’1’ during a Bus Read operation
within a block being erased. The Data Polling bit will change from a ’0’ to a ’1’ when the
Program/Erase Controller has suspended the Erase operation.
Figure 7: Data Polling flowchart, gives an example of how to use the Data Polling bit. A Valid
Address is the address being programmed or an address within the block being erased.
5.2
Toggle bit (DQ6)
The Toggle bit can be used to identify whether the Program/Erase Controller has
successfully completed its operation or if it has responded to an Erase Suspend. The Toggle
bit is output on DQ6 when the Status register is read.
During Program and Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’, etc., with
successive Bus Read operations at any address. After successful completion of the
operation the memory returns to Read mode.
During Erase Suspend mode the Toggle bit will output when addressing a cell within a block
being erased. The Toggle bit will stop toggling when the Program/Erase Controller has
suspended the Erase operation.
Figure 8: Toggle flowchart, gives an example of how to use the Data Toggle bit. Figure 14
and Figure 15 describe Toggle bit timing waveform.
30/65
M29W320ET, M29W320EB
5.3
Status register
Error bit (DQ5)
The Error bit can be used to identify errors detected by the Program/Erase Controller. The
Error bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the
correct data to the memory. If the Error bit is set a Read/Reset command must be issued
before other commands are issued. The Error bit is output on DQ5 when the Status register
is read.
Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to
do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’.
One of the Erase commands must be used to set all the bits in a block or in the whole
memory from ’0’ to ’1’.
5.4
Erase Timer bit (DQ3)
The Erase Timer bit can be used to identify the start of Program/Erase Controller operation
during a Block Erase command. Once the Program/Erase Controller starts erasing the
Erase Timer bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer bit
is set to ’0’ and additional blocks to be erased may be written to the Command interface.
The Erase Timer bit is output on DQ3 when the Status register is read.
5.5
Alternative Toggle bit (DQ2)
The alternative Toggle bit can be used to monitor the Program/Erase controller during Erase
operations. The alternative Toggle bit is output on DQ2 when the Status register is read.
During Chip Erase and Block Erase operations the Toggle bit changes from ’0’ to ’1’ to ’0’,
etc., with successive Bus Read operations from addresses within the blocks being erased.
A protected block is treated the same as a block not being erased. Once the operation
completes the memory returns to Read mode.
During Erase Suspend the alternative Toggle bit changes from ’0’ to ’1’ to ’0’, etc. with
successive Bus Read operations from addresses within the blocks being erased. Bus Read
operations to addresses within blocks not being erased will output the memory cell data as if
in Read mode.
After an Erase operation that causes the Error bit to be set the alternative Toggle bit can be
used to identify which block or blocks have caused the error. The alternative Toggle bit
changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses
within blocks that have not erased correctly. The alternative Toggle bit does not change if
the addressed block has erased correctly.
31/65
Status register
M29W320ET, M29W320EB
Table 7.
Status register bits(1)
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
RB
Program
Any Address
DQ7
Toggle
0
–
–
0
Program during
Erase Suspend
Any Address
DQ7
Toggle
0
–
–
0
Program Error
Any Address
DQ7
Toggle
1
–
–
Hi-Z
Chip Erase
Any Address
0
Toggle
0
1
Toggle
0
Erasing Block
0
Toggle
0
0
Toggle
0
Non-Erasing Block
0
Toggle
0
0
No
Toggle
0
Erasing Block
0
Toggle
0
1
Toggle
0
Non-Erasing Block
0
Toggle
0
1
No
Toggle
0
Erasing Block
1
No
Toggle
0
–
Toggle
Hi-Z
Block Erase before
timeout
Block Erase
Erase Suspend
Non-Erasing Block
Erase Error
Hi-Z
Good Block
Address
0
Toggle
1
1
No
Toggle
Hi-Z
Faulty Block
Address
0
Toggle
1
1
Toggle
Hi-Z
1. Unspecified data bits should be ignored.
32/65
Data read as normal
M29W320ET, M29W320EB
Figure 7.
Status register
Data Polling flowchart
START
READ DQ5 & DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
NO
DQ5
=1
YES
READ DQ7
at VALID ADDRESS
DQ7
=
DATA
YES
NO
FAIL
PASS
AI90194
33/65
Status register
Figure 8.
M29W320ET, M29W320EB
Toggle flowchart
START
READ DQ6
ADDRESS = BA
READ
DQ5 & DQ6
ADDRESS = BA
DQ6
=
TOGGLE
NO
YES
NO
DQ5
=1
YES
READ DQ6
TWICE
ADDRESS = BA
DQ6
=
TOGGLE
NO
YES
FAIL
PASS
AI08929b
1. BA = Address of Block being Programmed or Erased.
34/65
M29W320ET, M29W320EB
6
Maximum rating
Maximum rating
Stressing the device above the rating listed in the absolute maximum ratings table may
cause permanent damage to the device. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability. These are stress ratings only and
operation of the device at these or any other conditions above those indicated in the
Operating sections of this specification is not implied. Refer also to the Numonyx SURE
Program and other relevant quality documents.
Table 8.
Absolute maximum ratings
Symbol
Parameter
Min
Max
Unit
TBIAS
Temperature under Bias
–50
125
°C
TSTG
Storage Temperature
–65
150
°C
–0.6
VCC +0.6
V
(1)(2)
VIO
Input or Output voltage
VCC
Supply voltage
–0.6
4
V
VID
Identification voltage
–0.6
13.5
V
Program voltage
–0.6
13.5
V
VPP(3)
1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions.
2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions.
3. VPP must not remain at 12V for more than a total of 80hrs.
35/65
DC and ac parameters
7
M29W320ET, M29W320EB
DC and ac parameters
This section summarizes the operating measurement conditions, and the dc and ac
characteristics of the device. The parameters in the dc and ac characteristics tables that
follow, are derived from tests performed under the measurement conditions summarized in
Table 9: Operating and ac measurement conditions. Designers should check that the
operating conditions in their circuit match the operating conditions when relying on the
quoted parameters.
Table 9.
Operating and ac measurement conditions
M29W320ET, M29W320EB
Parameter
70
90
Min
Max
Min
Max
VCC Supply voltage
2.7
3.6
2.7
3.6
V
Ambient operating temperature
–40
85
–40
85
°C
Load capacitance (CL)
30
Input Rise and Fall times
10
V
VCC /2
VCC/2
V
VCC
VCC/2
0V
AI05557
Figure 10. AC measurement Load circuit
VCC
VCC
25kΩ
DEVICE
UNDER
TEST
CL
0.1µF
ns
0 to VCC
AC measurement I/O waveform
VPP
pF
0 to VCC
Input and Output Timing Ref. voltages
Figure 9.
30
10
Input Pulse voltages
25kΩ
0.1µF
CL includes JIG capacitance
AI05558
36/65
Unit
M29W320ET, M29W320EB
Device capacitance(1)
Table 10.
Symbol
CIN
COUT
DC and ac parameters
Parameter
Input capacitance
Output capacitance
Test condition
Min
Max
Unit
VIN = 0V
6
pF
VOUT = 0V
12
pF
1. Sampled only, not 100% tested.
Table 11.
Symbol
DC characteristics
Parameter
Test condition
Min
Max
Unit
0V ≤ VIN ≤ VCC
±1
μA
ILI
Input Leakage current
ILO
Output Leakage current
0V ≤ VOUT ≤ VCC
±1
μA
Supply current (Read)
E = VIL, G = VIH,
f = 6MHz
10
mA
ICC2
Supply current (Standby)
E = VCC ±0.2V,
RP = VCC ±0.2V
100
μA
ICC3
Supply current
(Program/Erase)
VPP/WP =
VIL or VIH
20
mA
VPP/WP =
VPP
20
mA
ICC1(1)
(2)(1)
Program/Erase
Controller
active
VIL
Input Low voltage
–0.5
0.8
V
VIH
Input High voltage
0.7V CC
VCC +0.3
V
VPP
Voltage for VPP/WP
Program Acceleration
VCC = 2.7V ±10%
11.5
12.5
V
IPP
Current for VPP/WP
Program Acceleration
VCC = 2.7V ±10%
15
mA
VOL
Output Low voltage
IOL = 1.8mA
0.45
V
VOH
Output High voltage
IOH = –100μA
VID
Identification voltage
11.5
12.5
V
Program/Erase Lockout
Supply voltage
1.8
2.3
V
VLKO
VCC –0.4
V
1. In Dual operations the Supply current will be the sum of ICC1(read) and ICC3 (program/erase).
2. Sampled only, not 100% tested.
37/65
DC and ac parameters
Figure 11.
M29W320ET, M29W320EB
Read mode ac waveforms
tAVAV
A0-A20/
A–1
VALID
tAVQV
tAXQX
E
tELQV
tEHQX
tELQX
tEHQZ
G
tGLQX
tGHQX
tGLQV
tGHQZ
DQ0-DQ7/
DQ8-DQ15
VALID
tBHQV
BYTE
tELBL/tELBH
tBLQZ
AI05559
Table 12.
Read ac characteristics
M29W320ET, M29W320EB
Symbol
Alt
Parameter
Test Condition
Unit
70
90
tAVAV
tRC
Address Valid to Next Address Valid
E = VIL,
G = VIL
Min
70
90
ns
tAVQV
tACC
Address Valid to Output Valid
E = VIL,
G = VIL
Max
70
90
ns
tELQX(1)
tLZ
Chip Enable Low to Output Transition
G = VIL
Min
0
0
ns
tELQV
tCE
Chip Enable Low to Output Valid
G = VIL
Max
70
90
ns
tGLQX(1)
tOLZ
Output Enable Low to Output
Transition
E = VIL
Min
0
0
ns
tGLQV
tOE
Output Enable Low to Output Valid
E = VIL
Max
30
35
ns
tEHQZ(1)
tHZ
Chip Enable High to Output Hi-Z
G = VIL
Max
25
30
ns
tGHQZ(1)
tDF
Output Enable High to Output Hi-Z
E = VIL
Max
25
30
ns
tEHQX
tGHQX
tAXQX
tOH
Chip Enable, Output Enable or
Address Transition to Output
Transition
Min
0
0
ns
tELBL
tELBH
tELFL
Chip Enable to BYTE Low or High
tELFH
Max
5
5
ns
tBLQZ
tFLQZ BYTE Low to Output Hi-Z
Max
25
30
ns
tBHQV
tFHQV BYTE High to Output Valid
Max
30
40
ns
1. Sampled only, not 100% tested.
38/65
M29W320ET, M29W320EB
DC and ac parameters
Figure 12. Write ac waveforms, Write Enable controlled
tAVAV
A0-A20/
A–1
VALID
tWLAX
tAVWL
tWHEH
E
tELWL
tWHGL
G
tGHWL
tWLWH
W
tWHWL
tDVWH
DQ0-DQ7/
DQ8-DQ15
tWHDX
VALID
VCC
tVCHEL
RB
tWHRL
AI05560
Table 13.
Write ac characteristics, Write Enable controlled
M29W320ET, M29W320EB
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tELWL
tCS
Chip Enable Low to Write Enable Low
Min
0
0
ns
tWLWH
tWP
Write Enable Low to Write Enable High
Min
45
50
ns
tDVWH
tDS
Input Valid to Write Enable High
Min
45
50
ns
tWHDX
tDH
Write Enable High to Input Transition
Min
0
0
ns
tWHEH
tCH
Write Enable High to Chip Enable High
Min
0
0
ns
tWHWL
tWPH
Write Enable High to Write Enable Low
Min
30
30
ns
tAVWL
tAS
Address Valid to Write Enable Low
Min
0
0
ns
tWLAX
tAH
Write Enable Low to Address Transition
Min
45
50
ns
Output Enable High to Write Enable Low
Min
0
0
ns
tGHWL
tWHGL
tOEH
Write Enable High to Output Enable Low
Min
0
0
ns
tWHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHEL
tVCS
VCC High to Chip Enable Low
Min
50
50
μs
1. Sampled only, not 100% tested.
39/65
DC and ac parameters
M29W320ET, M29W320EB
Figure 13. Write ac waveforms, Chip Enable controlled
tAVAV
A0-A20/
A–1
VALID
tELAX
tAVEL
tEHWH
W
tWLEL
tEHGL
G
tGHEL
tELEH
E
tEHEL
tDVEH
DQ0-DQ7/
DQ8-DQ15
tEHDX
VALID
VCC
tVCHWL
RB
tEHRL
AI05561
Table 14.
Write ac characteristics, Chip Enable controlled
M29W320ET, M29W320EB
Symbol
Alt
Parameter
Unit
70
90
tAVAV
tWC
Address Valid to Next Address Valid
Min
70
90
ns
tWLEL
tWS
Write Enable Low to Chip Enable Low
Min
0
0
ns
tELEH
tCP
Chip Enable Low to Chip Enable High
Min
45
50
ns
tDVEH
tDS
Input Valid to Chip Enable High
Min
45
50
ns
tEHDX
tDH
Chip Enable High to Input Transition
Min
0
0
ns
tEHWH
tWH
Chip Enable High to Write Enable High
Min
0
0
ns
tEHEL
tCPH
Chip Enable High to Chip Enable Low
Min
30
30
ns
tAVEL
tAS
Address Valid to Chip Enable Low
Min
0
0
ns
tELAX
tAH
Chip Enable Low to Address Transition
Min
45
50
ns
Output Enable High Chip Enable Low
Min
0
0
ns
tGHEL
tEHGL
tOEH
Chip Enable High to Output Enable Low
Min
0
0
ns
tEHRL(1)
tBUSY
Program/Erase Valid to RB Low
Max
30
35
ns
tVCHWL
tVCS
VCC High to Write Enable Low
Min
50
50
μs
1. Sampled only, not 100% tested.
40/65
M29W320ET, M29W320EB
DC and ac parameters
Figure 14. Toggle and alternative Toggle bits mechanism, Chip Enable controlled
A0-A20
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
tAXEL
E
G
Data
DQ2(1)/DQ6(2)
tELQV
tELQV
Alternative Toggle/
Toggle Bit
Alternative Toggle/
Toggle Bit
Data
AI09350
1. The Toggle bit is output on DQ6.
2. The alternative Toggle bit is output on DQ2.
Figure 15. Toggle and alternative Toggle bits mechanism, Output Enable controlled
A0-A20
VALID ADDRESS
VALID ADDRESS
VALID ADDRESS
tAXGL
G
E
DQ2(1)/DQ6(2)
Data
tGLQV
tGLQV
Alternative Toggle/
Toggle Bit
Alternative Toggle/
Toggle Bit
Data
AI09351
1. The Toggle bit is output on DQ6.
2. The alternative Toggle bit is output on DQ2.
Table 15.
Symbol
Toggle and alternative Toggle bits ac characteristics(1)
Alt
M29W320ET,
M29W320EB
Parameter
70
90
Unit
tAXEL
Address Transition to Chip Enable Low
Min
10
10
ns
tAXGL
Address Transition to Output Enable Low
Min
10
10
ns
1. tELQV and tGLQV values are presented in Table 12: Read ac characteristics.
41/65
DC and ac parameters
M29W320ET, M29W320EB
Figure 16. Reset/Block Temporary Unprotect ac waveforms
W, E, G
tPHWL, tPHEL, tPHGL
RB
tRHWL, tRHEL, tRHGL
tPLPX
RP
tPHPHH
tPLYH
AI02931B
Table 16.
Symbol
Reset/Block Temporary Unprotect ac characteristics
Alt
M29W320ET,
M29W320EB
Parameter
70
90
Unit
tPHWL(1)
tPHEL
tPHGL(1)
tRH
RP High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
50
50
ns
tRHWL(1)
tRHEL(1)
tRHGL(1)
tRB
RB High to Write Enable Low, Chip Enable
Low, Output Enable Low
Min
0
0
ns
tPLPX
tRP
RP Pulse Width
Min
500
500
ns
tPLYH
tREADY
RP Low to Read mode
Max
50
50
μs
tPHPHH(1)
tVIDR
RP Rise time to VID
Min
500
500
ns
VPP Rise and Fall time
Min
250
250
ns
tVHVPP(1)
1. Sampled only, not 100% tested.
Figure 17. Accelerated Program Timing waveforms
VPP
VPP/WP
VIL or VIH
tVHVPP
tVHVPP
AI05563
42/65
M29W320ET, M29W320EB
8
Package mechanical
Package mechanical
Figure 18. TSOP48 Lead Plastic Thin Small Outline, 12x20 mm package outline, top view
1
48
e
D1
B
24
L1
25
A2
E1
E
A
A1
DIE
α
L
C
CP
TSOP-G
1. Drawing not to scale.
Table 17.
TSOP48 Lead Plastic Thin Small Outline, 12x20 mm, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
Max
0.0472
A1
0.100
0.050
0.150
0.0039
0.0020
0.0059
A2
1.000
0.950
1.050
0.0394
0.0374
0.0413
B
0.220
0.170
0.270
0.0087
0.0067
0.0106
0.100
0.210
0.0039
0.0083
C
CP
0.080
0.0031
D1
12.000
11.900
12.100
0.4724
0.4685
0.4764
E
20.000
19.800
20.200
0.7874
0.7795
0.7953
E1
18.400
18.300
18.500
0.7244
0.7205
0.7283
e
0.500
–
–
0.0197
–
–
L
0.600
0.500
0.700
0.0236
0.0197
0.0276
L1
0.800
α
3
0
5
0.0315
0
5
3
43/65
Package mechanical
M29W320ET, M29W320EB
Figure 19. TFBGA48 6x8mm-6x8 Ball Array, 0.8mm Pitch, package outline, bottom view
D
D1
FD
FE
SD
SE
E
E1
BALL "A1"
ddd
e
e
b
A
A2
A1
BGA-Z32
1. Drawing not to scale.
Table 18.
TFBGA48 6x8mm - 6x8 Ball Array, 0.8mm Pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
A
Max
Typ
Min
1.200
A1
0.0472
0.260
A2
0.0102
0.900
b
Max
0.350
0.450
0.0354
0.0138
0.0177
D
6.000
5.900
6.100
0.2362
0.2323
0.2402
D1
4.000
–
–
0.1575
–
–
ddd
0.100
0.0039
E
8.000
7.900
8.100
0.3150
0.3110
0.3189
E1
5.600
–
–
0.2205
–
–
e
0.800
–
–
0.0315
–
–
FD
1.000
–
–
0.0394
–
–
FE
1.200
–
–
0.0472
–
–
SD
0.400
–
–
0.0157
–
–
SE
0.400
–
–
0.0157
–
–
44/65
M29W320ET, M29W320EB
Package mechanical
Figure 20. FBGA64 11 x 13 mm - 8 x 8 active ball array, 1 mm pitch, package outline, bottom view
D
D1
FD
FE
E
SD
SE
E1
ddd
BALL "A1"
A
e
b
A2
A1
BGA-Z23
1. Drawing is not to scale.
Table 19.
FBGA64 11 x 13 mm—8 x 8 active ball array, 1 mm pitch, package mechanical data
millimeters
inches
Symbol
Typ
Min
Max
Typ
Min
Max
A
—
—
1.40
—
—
0.055
A1
0.48
0.43
0.53
0.018
0.016
A2
0.80
—
—
0.031
—
—
b
—
0.55
0.65
—
0.021
0.025
D
11.00
10.90
11.10
0.433
0.429
0.437
D1
7.00
—
—
0.275
—
—
ddd
—
—
0.15
—
—
0.0059
e
1.00
—
—
0.039
—
—
E
13.0
12.90
13.10
0.511
0.507
0.515
E1
7.00
—
—
0.275
—
—
FD
2.00
—
—
0.078
—
—
FE
3.00
—
—
0.118
—
—
SD
0.50
—
—
0.0196
—
—
SE
0.50
—
—
0.0196
—
—
45/65
Part numbering
9
M29W320ET, M29W320EB
Part numbering
Table 20.
Ordering information scheme
Example:
M29W320EB
70
N
1
T
Device type
M29
Operating voltage
W = VCC = 2.7 to 3.6V
Device function
320E = 32 Mbit (x8/x16), Uniform Parameter Blocks,
Boot Block
Array matrix
T = Top Boot
B = Bottom Boot
Speed
70 = 70 ns
90 = 90 ns
Package
N = TSOP48: 12 x 20 mm
ZE = TFBGA48: 6 x 8mm, 0.8mm pitch
ZS = FBGA64: 11 x 13 mm, 1 mm pitch
Temperature range
1 = 0 to 70 °C
6 = –40 to 85 °C
Option
Blank = standard packing
T = Tape & Reel packing
E = RoHS package, standard packing
F = RoHS package, Tape & Reel packing
Note:
This product is also available with the Extended Block factory locked. For further details and
ordering information contact your nearest Numonyx sales office.
Devices are shipped from the factory with the memory content bits erased to ’1’.
For a list of available options (Speed, Package, etc.) or for further information on any aspect
of this device, please contact the Numonyx Sales Office nearest to you.
46/65
M29W320ET, M29W320EB
Appendix A
Block Addresses
Table 21.
Block
Block Addresses
Top Boot Block Addresses, M29W320ET
Block size
(Kbytes/Kwords)
Protection Block
group
(x8)
(x16)
000000h–00FFFFh
000000h–07FFFh
010000h–01FFFFh
008000h–0FFFFh
020000h–02FFFFh
010000h–17FFFh
0
64/32
1
64/32
2
64/32
3
64/32
030000h–03FFFFh
018000h–01FFFFh
4
64/32
040000h–04FFFFh
020000h–027FFFh
5
64/32
050000h–05FFFFh
028000h–02FFFFh
6
64/32
060000h–06FFFFh
030000h–037FFFh
7
64/32
070000h–07FFFFh
038000h–03FFFFh
8
64/32
080000h–08FFFFh
040000h–047FFFh
9
64/32
090000h–09FFFFh
048000h–04FFFFh
10
64/32
0A0000h–0AFFFFh
050000h–057FFFh
11
64/32
0B0000h–0BFFFFh
058000h–05FFFFh
12
64/32
0C0000h–0CFFFFh
060000h–067FFFh
13
64/32
0D0000h–0DFFFFh
068000h–06FFFFh
14
64/32
0E0000h–0EFFFFh
070000h–077FFFh
15
64/32
0F0000h–0FFFFFh
078000h–07FFFFh
16
64/32
100000h–10FFFFh
080000h–087FFFh
17
64/32
110000h–11FFFFh
088000h–08FFFFh
18
64/32
120000h–12FFFFh
090000h–097FFFh
19
64/32
130000h–13FFFFh
098000h–09FFFFh
20
64/32
140000h–14FFFFh
0A0000h–0A7FFFh
21
64/32
150000h–15FFFFh
0A8000h–0AFFFFh
22
64/32
160000h–16FFFFh
0B0000h–0B7FFFh
23
64/32
170000h–17FFFFh
0B8000h–0BFFFFh
24
64/32
180000h–18FFFFh
0C0000h–0C7FFFh
25
64/32
190000h–19FFFFh
0C8000h–0CFFFFh
26
64/32
1A0000h–1AFFFFh
0D0000h–0D7FFFh
27
64/32
1B0000h–1BFFFFh
0D8000h–0DFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
47/65
Block Addresses
M29W320ET, M29W320EB
Table 21.
Block
48/65
Top Boot Block Addresses, M29W320ET (continued)
Block size
(Kbytes/Kwords)
Protection Block
group
(x8)
(x16)
1C0000h–1CFFFFh
0E0000h–0E7FFFh
1D0000h–1DFFFFh
0E8000h–0EFFFFh
1E0000h–1EFFFFh
0F0000h–0F7FFFh
28
64/32
29
64/32
30
64/32
31
64/32
1F0000h–1FFFFFh
0F8000h–0FFFFFh
32
64/32
200000h–20FFFFh
100000h–107FFFh
33
64/32
210000h–21FFFFh
108000h–10FFFFh
34
64/32
220000h–22FFFFh
110000h–117FFFh
35
64/32
230000h–23FFFFh
118000h–11FFFFh
36
64/32
240000h–24FFFFh
120000h–127FFFh
37
64/32
250000h–25FFFFh
128000h–12FFFFh
38
64/32
260000h–26FFFFh
130000h–137FFFh
39
64/32
270000h–27FFFFh
138000h–13FFFFh
40
64/32
280000h–28FFFFh
140000h–147FFFh
41
64/32
290000h–29FFFFh
148000h–14FFFFh
42
64/32
2A0000h–2AFFFFh
150000h–157FFFh
43
64/32
2B0000h–2BFFFFh
158000h–15FFFFh
44
64/32
2C0000h–2CFFFFh
160000h–167FFFh
45
64/32
2D0000h–2DFFFFh
168000h–16FFFFh
46
64/32
2E0000h–2EFFFFh
170000h–177FFFh
47
64/32
2F0000h–2FFFFFh
178000h–17FFFFh
48
64/32
300000h–30FFFFh
180000h–187FFFh
49
64/32
310000h–31FFFFh
188000h–18FFFFh
50
64/32
320000h–32FFFFh
190000h–197FFFh
51
64/32
330000h–33FFFFh
198000h–19FFFFh
52
64/32
340000h–34FFFFh
1A0000h–1A7FFFh
53
64/32
350000h–35FFFFh
1A8000h–1AFFFFh
54
64/32
360000h–36FFFFh
1B0000h–1B7FFFh
55
64/32
370000h–37FFFFh
1B8000h–1BFFFFh
56
64/32
380000h–38FFFFh
1C0000h–1C7FFFh
57
64/32
390000h–39FFFFh
1C8000h–1CFFFFh
58
64/32
3A0000h–3AFFFFh
1D0000h–1D7FFFh
59
64/32
3B0000h–3BFFFFh
1D8000h–1DFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
M29W320ET, M29W320EB
Table 21.
Block
Block Addresses
Top Boot Block Addresses, M29W320ET (continued)
Block size
(Kbytes/Kwords)
Protection Block
group
(x8)
(x16)
3C0000h–3CFFFFh
1E0000h–1E7FFFh
3D0000h–3DFFFFh
1E8000h–1EFFFFh
3E0000h–3EFFFFh
1F0000h–1F7FFFh
60
64/32
61
64/32
62
64/32
63
8/4
Protection group
3F0000h–3F1FFFh(1)
1F8000h–1F8FFFh(1)
64
8/4
Protection group
3F2000h–3F3FFFh(1)
1F9000h–1F9FFFh(1)
65
8/4
Protection group
3F4000h–3F5FFFh(1)
1FA000h–1FAFFFh(1)
66
8/4
Protection group
3F6000h–3F7FFFh(1)
1FB000h–1FBFFFh(1)
67
8/4
Protection group
3F8000h–3F9FFFh(1)
1FC000h–1FCFFFh(1)
68
8/4
Protection group
3FA000h–3FBFFFh(1)
1FD000h–1FDFFFh(1)
69
8/4
Protection group
3FC000h–3FDFFFh(1)
1FE000h–1FEFFFh(1)
70
8/4
Protection group
3FE000h–3FFFFFh(1)
1FF000h–1FFFFFh(1)
Protection group
1. Used as the Extended Block Addresses in Extended Block mode.
Table 22.
Bottom Boot Block Addresses, M29W320EB
Block
Block size
(Kbytes/Kwords)
Protection Block
group
(x8)
(x16)
0
8/4
Protection group
000000h-001FFFh(1)
000000h–000FFFh(1)
1
8/4
Protection group
002000h-003FFFh(1)
001000h–001FFFh(1)
2
8/4
Protection group
004000h-005FFFh(1)
002000h–002FFFh(1)
3
8/4
Protection group
006000h-007FFFh(1)
003000h–003FFFh(1)
4
8/4
Protection group
008000h-009FFFh(1)
004000h–004FFFh(1)
5
8/4
Protection group
00A000h-00BFFFh(1)
005000h–005FFFh(1)
6
8/4
Protection group
00C000h-00DFFFh(1)
006000h–006FFFh(1)
7
8/4
Protection group
00E000h-00FFFFh (1)
007000h–007FFFh(1)
8
64/32
010000h-01FFFFh
008000h–00FFFFh
9
64/32
020000h-02FFFFh
010000h–017FFFh
10
64/32
030000h-03FFFFh
018000h–01FFFFh
11
64/32
040000h-04FFFFh
020000h–027FFFh
12
64/32
050000h-05FFFFh
028000h–02FFFFh
13
64/32
060000h-06FFFFh
030000h–037FFFh
14
64/32
070000h-07FFFFh
038000h–03FFFFh
15
64/32
080000h-08FFFFh
040000h–047FFFh
16
64/32
090000h-09FFFFh
048000h–04FFFFh
17
64/32
0A0000h-0AFFFFh
050000h–057FFFh
18
64/32
0B0000h-0BFFFFh
058000h–05FFFFh
Protection group
Protection group
Protection group
49/65
Block Addresses
M29W320ET, M29W320EB
Table 22.
50/65
Bottom Boot Block Addresses, M29W320EB (continued)
Block
Block size
(Kbytes/Kwords)
19
64/32
20
64/32
21
64/32
22
Protection Block
group
(x8)
(x16)
0C0000h-0CFFFFh
060000h–067FFFh
0D0000h-0DFFFFh
068000h–06FFFFh
0E0000h-0EFFFFh
070000h–077FFFh
64/32
0F0000h-0FFFFFh
078000h–07FFFFh
23
64/32
100000h-10FFFFh
080000h–087FFFh
24
64/32
110000h-11FFFFh
088000h–08FFFFh
25
64/32
120000h-12FFFFh
090000h–097FFFh
26
64/32
130000h-13FFFFh
098000h–09FFFFh
27
64/32
140000h-14FFFFh
0A0000h–0A7FFFh
28
64/32
150000h-15FFFFh
0A8000h–0AFFFFh
29
64/32
160000h-16FFFFh
0B0000h–0B7FFFh
30
64/32
170000h-17FFFFh
0B8000h–0BFFFFh
31
64/32
180000h-18FFFFh
0C0000h–0C7FFFh
32
64/32
190000h-19FFFFh
0C8000h–0CFFFFh
33
64/32
1A0000h-1AFFFFh
0D0000h–0D7FFFh
34
64/32
1B0000h-1BFFFFh
0D8000h–0DFFFFh
35
64/32
1C0000h-1CFFFFh
0E0000h–0E7FFFh
36
64/32
1D0000h-1DFFFFh
0E8000h–0EFFFFh
37
64/32
1E0000h-1EFFFFh
0F0000h–0F7FFFh
38
64/32
1F0000h-1FFFFFh
0F8000h–0FFFFFh
39
64/32
200000h-20FFFFh
100000h–107FFFh
40
64/32
210000h-21FFFFh
108000h–10FFFFh
41
64/32
220000h-22FFFFh
110000h–117FFFh
42
64/32
230000h-23FFFFh
118000h–11FFFFh
43
64/32
240000h-24FFFFh
120000h–127FFFh
44
64/32
250000h-25FFFFh
128000h–12FFFFh
45
64/32
260000h-26FFFFh
130000h–137FFFh
46
64/32
270000h-27FFFFh
138000h–13FFFFh
47
64/32
280000h-28FFFFh
140000h–147FFFh
48
64/32
290000h-29FFFFh
148000h–14FFFFh
49
64/32
2A0000h-2AFFFFh
150000h–157FFFh
50
64/32
2B0000h-2BFFFFh
158000h–15FFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
Protection group
M29W320ET, M29W320EB
Table 22.
Block Addresses
Bottom Boot Block Addresses, M29W320EB (continued)
Block
Block size
(Kbytes/Kwords)
51
64/32
52
64/32
53
64/32
54
Protection Block
group
(x8)
(x16)
2C0000h-2CFFFFh
160000h–167FFFh
2D0000h-2DFFFFh
168000h–16FFFFh
2E0000h-2EFFFFh
170000h–177FFFh
64/32
2F0000h-2FFFFFh
178000h–17FFFFh
55
64/32
300000h-30FFFFh
180000h–187FFFh
56
64/32
310000h-31FFFFh
188000h–18FFFFh
57
64/32
320000h-32FFFFh
190000h–197FFFh
58
64/32
330000h-33FFFFh
198000h–19FFFFh
59
64/32
340000h-34FFFFh
1A0000h–1A7FFFh
60
64/32
350000h-35FFFFh
1A8000h–1AFFFFh
61
64/32
360000h-36FFFFh
1B0000h–1B7FFFh
62
64/32
370000h-37FFFFh
1B8000h–1BFFFFh
63
64/32
380000h-38FFFFh
1C0000h–1C7FFFh
64
64/32
390000h-39FFFFh
1C8000h–1CFFFFh
65
64/32
3A0000h-3AFFFFh
1D0000h–1D7FFFh
66
64/32
3B0000h-3BFFFFh
1D8000h–1DFFFFh
67
64/32
3C0000h-3CFFFFh
1E0000h–1E7FFFh
68
64/32
3D0000h-3DFFFFh
1E8000h–1EFFFFh
69
64/32
3E0000h-3EFFFFh
1F0000h–1F7FFFh
70
64/32
3F0000h-3FFFFFh
1F8000h–1FFFFFh
Protection group
Protection group
Protection group
Protection group
Protection group
1. Used as the Extended Block Addresses in Extended Block mode.
51/65
Common Flash Interface (CFI)
Appendix B
M29W320ET, M29W320EB
Common Flash Interface (CFI)
The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from
the Flash memory device. It allows a system software to query the device to determine various electrical
and timing parameters, density information and functions supported by the memory. The system can
interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI
Query Command is issued the device enters CFI Query mode and the data structure is read from the
memory. Table 23, Table 24, Table 25, Table 26, Table 27 and Table 28 show the addresses used to
retrieve the data.
The CFI data structure also contains a security area where a 64 bit unique security number is written
(see Table 28: Security code area). This area can be accessed only in Read mode by the final user. It is
impossible to change the security number after it has been written by Numonyx.
Query Structure Overview(1)
Table 23.
Address
Sub-section name
Description
x16
x8
10h
20h
CFI Query Identification String
Command set ID and algorithm data offset
1Bh
36h
System Interface Information
Device timing & voltage information
27h
4Eh
Device Geometry Definition
Flash device layout
40h
80h
Primary Algorithm-specific extended
Query table
Additional information specific to the Primary
Algorithm (optional)
61h
C2h
Security code area
64 bit unique device number
1. Query data are always presented on the lowest order data outputs.
CFI Query Identification String(1)
Table 24.
Address
Data
x16
x8
10h
20h
0051h
11h
22h
0052h
12h
24h
0059h
13h
26h
0002h
14h
28h
0000h
15h
2Ah
0040h
16h
2Ch
0000h
17h
2Eh
0000h
18h
30h
0000h
19h
32h
0000h
1Ah
34h
0000h
Description
“Q”
Query unique ASCII string "QRY"
"R"
"Y"
Primary Algorithm Command Set and Control Interface ID code 16 bit
ID code defining a specific algorithm
Address for Primary Algorithm extended query table (see Table 27)
AMD
Compatible
P = 40h
Alternate Vendor Command Set and Control Interface ID code second
vendor - specified algorithm supported
NA
Address for Alternate Algorithm extended Query table
NA
1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’.
52/65
Value
M29W320ET, M29W320EB
Table 25.
Common Flash Interface (CFI)
CFI Query System Interface Information
Address
Data
x16
x8
1Bh
36h
Description
Value
0027h
VCC Logic Supply Minimum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
2.7V
3.6V
1Ch
38h
0036h
VCC Logic Supply Maximum Program/Erase voltage
bit 7 to 4BCD value in volts
bit 3 to 0BCD value in 100 mV
1Dh
3Ah
00B5h
VPP [Programming] Supply Minimum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
11.5V
1Eh
3Ch
00C5h
VPP [Programming] Supply Maximum Program/Erase voltage
bit 7 to 4HEX value in volts
bit 3 to 0BCD value in 100 mV
12.5V
1Fh
3Eh
0004h
Typical timeout per single byte/word program = 2n μs
16μs
20h
21h
40h
42h
0000h
000Ah
n
Typical timeout for minimum size write buffer program = 2 μs
n
Typical timeout per individual block erase = 2 ms
n
22h
44h
0000h
Typical timeout for full Chip Erase = 2 ms
23h
46h
0004h
Maximum timeout for byte/word program = 2n times typical
24h
25h
26h
48h
4Ah
4Ch
0000h
0003h
0000h
Maximum timeout for write buffer program =
1s
NA
2n
256 μs
times typical
NA
n
8s
Maximum timeout per individual block erase = 2 times typical
n
NA
Maximum timeout for Chip Erase = 2 times typical
NA
53/65
Common Flash Interface (CFI)
Table 26.
M29W320ET, M29W320EB
Device Geometry Definition(1)
Address
Data
Description
Value
x16
x8
27h
4Eh
0016h
Device Size = 2n in number of bytes
4 Mbyte
28h
29h
50h
52h
0002h
0000h
Flash Device Interface code description
x8, x16
Async.
2Ah
2Bh
54h
56h
0000h
0000h
Maximum number of bytes in multi-byte program or page = 2n
NA
2Ch
58h
0002h
Number of Erase Block regions. It specifies the number of
regions containing contiguous Erase Blocks of the same size.
2
2Dh
2Eh
5Ah
5Ch
0007h
0000h
Region 1 information
Number of Erase Blocks of identical size = 0007h+1
8
2Fh
30h
5Eh
60h
0020h
0000h
Region 1 information
Block size in Region 1 = 0020h * 256 byte
31h
32h
62h
64h
003Eh
0000h
Region 2 information
Number of Erase Blocks of identical size = 003Eh+1
33h
34h
66h
68h
0000h
0001h
Region 2 information
Block size in region 2 = 0100h * 256 byte
8Kbyte
63
64Kbyte
1. For the M29W320EB, Region 1 corresponds to addresses 000000h to 007FFFh and Region 2 to addresses 008000h to
1FFFFFh. For the M29W320ET, Region 1 corresponds to addresses 1F8000h to 1FFFFFh and Region 2 to addresses
000000h to 1F7FFFh.
Table 27.
Primary Algorithm-specific extended Query table
Address
Data
Description
Value
x16
x8
40h
80h
0050h
41h
82h
0052h
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
44h
88h
0031h
Minor version number, ASCII
"1"
Yes
"P"
Primary Algorithm extended Query table unique ASCII string “PRI”
"R"
"I"
45h
8Ah
0000h
Address Sensitive Unlock (bits 1 to 0)
00 = required, 01= not required
Silicon Revision Number (bits 7 to 2)
46h
8Ch
0002h
Erase Suspend
00 = not supported, 01 = Read only, 02 = Read and Write
2
47h
8Eh
0001h
Block Protection
00 = not supported, x = number of blocks in per group
1
48h
90h
0001h
Temporary Block Unprotect
00 = not supported, 01 = supported
Yes
49h
92h
0004h
Block Protect /Unprotect
04 = M29W320E
04
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M29W320ET, M29W320EB
Table 27.
Common Flash Interface (CFI)
Primary Algorithm-specific extended Query table (continued)
Address
Data
Description
Value
x16
x8
4Ah
94h
0000h
Simultaneous operations, 00 = not supported
No
4Bh
96h
0000h
Burst mode, 00 = not supported, 01 = supported
No
4Ch
98h
0000h
Page mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word
No
11.5V
12.5V
4Dh
9Ah
00B5h
VPP Supply Minimum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
4Eh
9Ch
00C5h
VPP Supply Maximum Program/Erase voltage
bit 7 to 4 HEX value in volts
bit 3 to 0 BCD value in 100 mV
4Fh
9Eh
0002h
0003h
Top/Bottom Boot Block Flag
02h = Bottom Boot device, 03h = Top Boot device
Table 28.
–
Security code area
Address
Data
x16
x8
61h
C3h, C2h
XXXX
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
Description
64 bit: unique device number
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Extended memory Block
Appendix C
M29W320ET, M29W320EB
Extended memory Block
The M29W320E has an extra block, the Extended Block, that can be accessed using a
dedicated command.
This Extended Block is 32 Kwords in x16 mode and 64 Kbytes in x8 mode. It is used as a
security block (to provide a permanent security identification number) or to store additional
information.
The Extended Block is either Factory Locked or Customer Lockable, its status is indicated
by bit DQ7. This bit is permanently set to either ‘1’ or ‘0’ at the factory and cannot be
changed. When set to ‘1’, it indicates that the device is factory locked and the Extended
Block is protected. When set to ‘0’, it indicates that the device is customer lockable and the
Extended Block is unprotected. Bit DQ7 being permanently locked to either ‘1’ or ‘0’ is
another security feature which ensures that a customer lockable device cannot be used
instead of a factory locked one.
Bit DQ7 is the most significant bit in the Extended Block Verify code and a specific
procedure must be followed to read it. See “Extended memory Block Verify code” in Table 2
and Section Table 3. on page 20, Table 2: Bus operations, BYTE = VIL and Table 3: Bus
operations, BYTE = VIH , respectively, for details of how to read bit DQ7.
The Extended Block can only be accessed when the device is in Extended Block mode. For
details of how the Extended Block mode is entered and exited, refer to Section 4.13: Enter
Extended Block command and Section 4.14: Exit Extended Block command, and to Table 4
and Table 5, Table 4: Commands, 16-bit mode, BYTE = VIH and Table 5: Commands, 8-bit
mode, BYTE = VIL, respectively.
9.1
Factory Locked Extended Block
In devices where the Extended Block is factory locked, the Security Identification Number is
written to the Extended Block address space (see Table 29: Extended Block Address and
data) in the factory. The DQ7 bit is set to ‘1’ and the Extended Block cannot be unprotected.
9.2
Customer Lockable Extended Block
A device where the Extended Block is customer lockable is delivered with the DQ7 bit set to
‘0’ and the Extended Block unprotected. It is up to the customer to program and protect the
Extended Block but care must be taken because the protection of the Extended Block is not
reversible.
There are two ways of protecting the Extended Block:
56/65
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the In-system technique with RP either at VIH or at VID (refer to Appendix D:
Block Protection, Section D.2: In-system technique and to the corresponding
flowcharts, Figure 23 and Figure 24, for a detailed explanation of the technique).
Issue the Enter Extended Block command to place the device in Extended Block mode,
then use the Programmer technique (refer to Appendix D: Block Protection,
Section D.1: Programmer technique and to the corresponding flowcharts, Figure 21
and Figure 22, for a detailed explanation of the technique).
M29W320ET, M29W320EB
Extended memory Block
Once the Extended Block is programmed and protected, the Exit Extended Block command must be
issued to exit the Extended Block mode and return the device to Read mode.
Table 29.
Extended Block Address and data
Address(1)
Data
Device
M29W320ET
M29W320EB
x8
x16
Factory Locked
3F0000h-3F000Fh
1F8000h-1F8007h
Security identification
number
3F0010h-3FFFFFh
1F8008h-1FFFFFh
Unavailable
000000h-00000Fh
000000h-000007h
Security identification
number
000010h-00FFFFh
000008h-007FFFh
Unavailable
Customer Lockable
Determined by
customer
Determined by
customer
1. See Table 21 and Table 22, Top and Bottom Boot Block Addresses.
57/65
Block Protection
Appendix D
M29W320ET, M29W320EB
Block Protection
Block protection can be used to prevent any operation from modifying the data stored in the
memory. The blocks are protected in groups, refer to Appendix A: Block Addresses,
Table 21 and Table 22. for details of the Protection groups. Once protected, Program and
Erase operations within the protected group fail to change the data.
There are three techniques that can be used to control Block Protection, these are the
Programmer technique, the In-system technique and Temporary Unprotection. Temporary
Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is
described in the Signal Descriptions section.
D.1
Programmer technique
The Programmer technique uses high (VID) voltage levels on some of the bus pins. These
cannot be achieved using a standard microprocessor bus, therefore the technique is
recommended only for use in programming equipment.
To protect a group of blocks follow the flowchart in Figure 21, Programmer Equipment Block
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all groups can be unprotected at the same time. To unprotect the chip follow Figure 22:
Programmer Equipment Chip Unprotect flowchart. Table 30: Programmer technique Bus
operations, BYTE = VIH or VIL, gives a summary of each operation.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not abort the procedure before
reaching the end. Chip Unprotect can take several seconds and a user message should be
provided to show that the operation is progressing.
D.2
In-system technique
The In-system technique requires a high voltage level on the Reset/Blocks Temporary
Unprotect pin, RP(1). This can be achieved without violating the maximum ratings of the
components on the microprocessor bus, therefore this technique is suitable for use after the
memory has been fitted to the system.
To protect a group of blocks follow the flowchart in Figure 23: In-system Equipment Group
Protect flowchart. To unprotect the whole chip it is necessary to protect all of the groups first,
then all the groups can be unprotected at the same time. To unprotect the chip follow
Figure 24: In-system Equipment Chip Unprotect flowchart.
The timing on these flowcharts is critical. Care should be taken to ensure that, where a
pause is specified, it is followed as closely as possible. Do not allow the microprocessor to
service interrupts that will upset the timing and do not abort the procedure before reaching
the end. Chip Unprotect can take several seconds and a user message should be provided
to show that the operation is progressing.
Note:
58/65
RP can be either at VIH or at VID when using the In-system technique to protect the
Extended Block.
M29W320ET, M29W320EB
Table 30.
Block Protection
Programmer technique Bus operations, BYTE = VIH or VIL
E
G
W
Address Inputs
A0-A20
Data Inputs/Outputs
DQ15A–1, DQ14-DQ0
Block (group)
Protect(1)
VIL
VID
VIL Pulse
A9 = VID, A12-A20 Block Address
others = X
X
Chip Unprotect
VID
VID
VIL Pulse
A9 = VID, A12 = VIH, A15 = VIH
others = X
X
Block (group)
Protection Verify
VIL
VIL
VIH
A0 = VIL , A1 = VIH, A6 = VIL,
A9 = VID, A12-A20 Block Address
others = X
Pass = XX01h
Retry = XX00h
Block (group)
Unprotection Verify
VIL
VIL
VIH
A0 = VIL , A1 = VIH, A6 = VIH,
A9 = VID, A12-A20 Block Address
others = X
Retry = XX01h
Pass = XX00h
Operation
1. Block Protection groups are shown in Appendix A: Block Addresses, Table 21 and Table 22.
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Block Protection
M29W320ET, M29W320EB
Figure 21. Programmer Equipment Group Protect flowchart
START
Set-up
ADDRESS = GROUP ADDRESS
W = VIH
n=0
G, A9 = VID,
E = VIL
Protect
Wait 4µs
W = VIL
Wait 100µs
W = VIH
E, G = VIH,
A0, A6 = VIL,
A1 = VIH
E = VIL
Verify
Wait 4µs
G = VIL
Wait 60ns
Read DATA
DATA
NO
=
01h
YES
A9 = VIH
E, G = VIH
++n
= 25
NO
End
YES
PASS
A9 = VIH
E, G = VIH
FAIL
1. Block Protection groups are shown in Appendix A: Block Addresses, Table 21 and Table 22.
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AI05574
M29W320ET, M29W320EB
Block Protection
Figure 22. Programmer Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
A6, A12, A15 = VIH(1)
E, G, A9 = VID
Unprotect
Wait 4µs
W = VIL
Wait 10ms
W = VIH
E, G = VIH
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1, A6 = VIH
E = VIL
Wait 4µs
G = VIL
INCREMENT
CURRENT GROUP
Verify
Wait 60ns
Read DATA
NO
End
NO
++n
= 1000
DATA
=
00h
YES
LAST
GROUP
YES
YES
A9 = VIH
E, G = VIH
A9 = VIH
E, G = VIH
FAIL
PASS
NO
AI05575
1. Block Protection groups are shown in Appendix A: Block Addresses, Table 21 and Table 22.
61/65
Block Protection
M29W320ET, M29W320EB
Figure 23. In-system Equipment Group Protect flowchart
Set-up
START
n=0
RP = VID
Protect
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
WRITE 60h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 100µs
Verify
WRITE 40h
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
Wait 4µs
READ DATA
ADDRESS = GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIL
DATA
NO
=
01h
YES
End
RP = VIH
ISSUE READ/RESET
COMMAND
PASS
++n
= 25
NO
YES
RP = VIH
ISSUE READ/RESET
COMMAND
FAIL
AI05576
1. Block Protection groups are shown in Appendix A: Block Addresses, Table 21 and Table 22.
2. RP can be either at VIH or at VID when using the In-system technique to protect the Extended Block.
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M29W320ET, M29W320EB
Block Protection
Figure 24. In-system Equipment Chip Unprotect flowchart
START
Set-up
PROTECT ALL GROUPS
n=0
CURRENT GROUP = 0
RP = VID
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Unprotect
WRITE 60h
ANY ADDRESS WITH
A0 = VIL, A1 = VIH, A6 = VIH
Wait 10ms
Verify
WRITE 40h
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
Wait 4µs
INCREMENT
CURRENT GROUP
READ DATA
ADDRESS = CURRENT GROUP ADDRESS
A0 = VIL, A1 = VIH, A6 = VIH
NO
End
NO
++n
= 1000
DATA
=
00h
YES
LAST
GROUP
YES
NO
YES
RP = VIH
RP = VIH
ISSUE READ/RESET
COMMAND
ISSUE READ/RESET
COMMAND
FAIL
PASS
AI05577
1. Block Protection groups are shown in Appendix A: Block Addresses, Table 21 and Table 22.
63/65
Revision history
M29W320ET, M29W320EB
Revision history
Table 31.
Document revision history
Date
Version
15-Apr-2004
1.0
First Issue.
18-Nov-2004
2.0
Protection group for Blocks 0 to 3 and and Blocks 67 to 70 modifed in
Table 21: Top Boot Block Addresses, M29W320ET and Table 22:
Bottom Boot Block Addresses, M29W320EB, respectively.
TFBGA48 Commercial code changed from ZA to ZE.
14-Mar-2005
3.0
RB updated in Table 7: Status register bits.
Section 4.5: Fast Program commands restructured and updated.
Section 4.6: Unlock Bypass command updated.
28-Mar-2006
4.0
Datasheet title modified.
RoHS text added.
16-Jan-2007
5
Changed DQ7 to DQ7 for ‘Program’, ‘Program during Erase Suspend’,
and ‘Program Error’ in Table 7: Status register bits.
26-Mar-2008
6
Applied Numonyx branding.
5-March 2009
7
Added FBGA (ZS) package information.
12-March-2009
8
Added FBGA64 8x8 ballout.
9
Specified top and bottom boot data for addresses 4Fh and 9Eh in Table
27.: Primary Algorithm-specific extended Query table;
Corrected a CFI field (address 44h in x16 mode) in Table 27.: Primary
Algorithm-specific extended Query table.
Parts with the new programmed values are available from week 13
2009
1-April-2009
64/65
Changes
M29W320ET, M29W320EB
Please Read Carefully:
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