512Mb: 3V Embedded Parallel NOR Flash
Features
Parallel NOR Flash Embedded Memory
M29W512GH70N3E, M29W512GH7AN6E
Features
• VPP/WP# pin protection
– Protects first and last block regardless of block
protection settings
• Software protection
– Volatile protection
– Nonvolatile protection
– Password protection
• Two extended memory blocks
– 2 x 256 bytes (2 x 128 words) memory block for
permanent, secure identification
– Programmed or locked at the factory or by the
customer
• Common flash interface
– 64-bit security code
• Low power consumption: Standby and automatic
modes
• JESD47H-compliant
– 100,000 minimum PROGRAM/ERASE cycles per
block
– Data retention: 20 years (TYP)
• 65nm single-level cell (SLC) process technology
• TSOP package
• Green packages available
– RoHS-compliant
– Halogen-free
• Automotive device temperature (automotive grade
certified):
–40°C to +125°C (automotive grade 3)
–40°C to +85°C (automotive grade 6)
• Stacked device (two 256Mb die)
• Supply voltage
– VCC = 2.7–3.6V (program, erase, read)
– VCCQ = 1.65–3.6V (I/O buffers)
– VPPH = 12V for fast program (optional)
• Asynchronous random/page read
– Page size: 8 words or 16 bytes
– Page access: 25ns, 30ns
– Random access: 80ns, 90ns
• Commands sensitive to MSB A24 (die selection)
• Fast program commands: 32-word (64-byte) write
buffer
• Enhanced buffered program commands: 256-word
• Program time
– 16µs per byte/word TYP
– Single die program time: 10s with V PPH, 16s without V PPH
• Memory organization
– Uniform blocks: 512 main blocks (2 x 256),
128KB or 64KW each
• Program/erase controller
– Embedded byte/word program algorithms
• Program/erase suspend and resume capability
– Read from any block during a PROGRAM
SUSPEND operation
– Read or program another block during an ERASE
SUSPEND operation
• Unlock bypass, block erase, die erase, write to buffer
and program
– Fast buffered/batch programming
– Fast block/die erase
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2012 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.
512Mb: 3V Embedded Parallel NOR Flash
Features
Part Numbering Information
This device is available with extended memory block prelocked by Micron. Devices are shipped from the factory
with memory content bits erased to 1. For available options, such as packages, or for further information, contact
your Micron sales representative. Part numbers can be verified at www.micron.com. Feature and specification
comparison by device type is available at www.micron.com/products. Contact the factory for devices not found.
Table 1: Part Number Information
Part Number
Category
Category Details
Device Type
M29W
Notes
Operating Voltage
W = VCC = 2.7 to 3.6V
Device function
512GH = 512Mb (x8/x16) page, uniform block Flash memory, outermost blocks protected
by VPP/WP#
Speed
7A = 80ns
1, 2
70 = 80ns
1
Package
N = 56-pin TSOP, 14mm x 20mm, lead-free, halogen-free, RoHS-compliant
Temperature Range
3 = –40°C to +125°C
6 = –40°C to +85°C
Shipping Options
E = RoHS-compliant package, standard packing
F = RoHS-compliant package, tape and reel packing
Notes:
1. 90ns if VCCQ = 1.65V to VCC.
2. Automotive qualified, available only with option 6. Qualified and characterized according to AEC Q100 and
Q003 or equivalent; advanced screening according to AEC Q001 and Q002 or equivalent.
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512Mb: 3V Embedded Parallel NOR Flash
Features
Contents
Important Notes and Warnings ......................................................................................................................... 7
General Description ......................................................................................................................................... 7
Signal Assignments ......................................................................................................................................... 10
Signal Descriptions ......................................................................................................................................... 11
Memory Organization .................................................................................................................................... 12
Memory Configuration ............................................................................................................................... 12
Memory Map – 512Mb Density ................................................................................................................... 12
Bus Operations ............................................................................................................................................... 14
Read .......................................................................................................................................................... 14
Write .......................................................................................................................................................... 14
Standby and Automatic Standby ................................................................................................................. 14
Output Disable ........................................................................................................................................... 15
Reset .......................................................................................................................................................... 15
Registers ........................................................................................................................................................ 16
Status Register ............................................................................................................................................ 16
Lock Register .............................................................................................................................................. 20
Standard Command Definitions – Address-Data Cycles .................................................................................... 24
READ and AUTO SELECT Operations .............................................................................................................. 27
READ/RESET Command ............................................................................................................................ 27
READ CFI Command .................................................................................................................................. 27
AUTO SELECT Command ........................................................................................................................... 27
BYPASS Operations ......................................................................................................................................... 29
UNLOCK BYPASS Command ...................................................................................................................... 29
UNLOCK BYPASS RESET Command ............................................................................................................ 30
PROGRAM Operations .................................................................................................................................... 30
PROGRAM Command ................................................................................................................................ 30
UNLOCK BYPASS PROGRAM Command ..................................................................................................... 31
WRITE TO BUFFER PROGRAM Command .................................................................................................. 31
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command ....................................................................... 34
WRITE TO BUFFER PROGRAM CONFIRM Command .................................................................................. 34
BUFFERED PROGRAM ABORT AND RESET Command ................................................................................ 34
PROGRAM SUSPEND Command ................................................................................................................ 34
PROGRAM RESUME Command .................................................................................................................. 35
ENTER/EXIT ENHANCED BUFFERED PROGRAM Commands ..................................................................... 35
ENHANCED BUFFERED PROGRAM Command ........................................................................................... 35
ENHANCED BUFFERED PROGRAM ABORT AND RESET Command ............................................................ 38
ERASE Operations .......................................................................................................................................... 38
DIE ERASE Command ................................................................................................................................ 38
UNLOCK BYPASS DIE ERASE Command ..................................................................................................... 39
BLOCK ERASE Command ........................................................................................................................... 39
UNLOCK BYPASS BLOCK ERASE Command ................................................................................................ 39
ERASE SUSPEND Command ....................................................................................................................... 40
ERASE RESUME Command ........................................................................................................................ 41
Block Protection Command Definitions – Address-Data Cycles ........................................................................ 42
PROTECTION Operations ............................................................................................................................... 45
LOCK REGISTER Commands ...................................................................................................................... 45
PASSWORD PROTECTION Commands ....................................................................................................... 45
NONVOLATILE PROTECTION Commands .................................................................................................. 46
NONVOLATILE PROTECTION BIT LOCK BIT Commands ............................................................................ 48
VOLATILE PROTECTION Commands .......................................................................................................... 48
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512Mb: 3V Embedded Parallel NOR Flash
Features
EXTENDED MEMORY BLOCK Commands ..................................................................................................
EXIT PROTECTION Command ....................................................................................................................
Device Protection ...........................................................................................................................................
Hardware Protection ..................................................................................................................................
Software Protection ....................................................................................................................................
Volatile Protection Mode .............................................................................................................................
Nonvolatile Protection Mode ......................................................................................................................
Password Protection Mode ..........................................................................................................................
Common Flash Interface ................................................................................................................................
Power-Up and Reset Characteristics ................................................................................................................
Absolute Ratings and Operating Conditions .....................................................................................................
DC Characteristics ..........................................................................................................................................
Read AC Characteristics ..................................................................................................................................
Write AC Characteristics .................................................................................................................................
Accelerated Program, Data Polling/Toggle AC Characteristics ...........................................................................
Program/Erase Characteristics ........................................................................................................................
Package Dimensions .......................................................................................................................................
Revision History .............................................................................................................................................
Rev. F – 5/18 ...............................................................................................................................................
Rev. E – 9/15 ...............................................................................................................................................
Rev. D – 6/15 ..............................................................................................................................................
Rev. C – 6/14 ...............................................................................................................................................
Rev. B – 2/14 ...............................................................................................................................................
Rev. A – 4/13 ...............................................................................................................................................
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512Mb: 3V Embedded Parallel NOR Flash
Features
List of Figures
Figure 1: Logic Diagram ................................................................................................................................... 8
Figure 2: Configuration Diagram ...................................................................................................................... 9
Figure 3: 56-Pin TSOP (Top View) .................................................................................................................. 10
Figure 4: Data Polling Flowchart .................................................................................................................... 18
Figure 5: Toggle Bit Flowchart ........................................................................................................................ 19
Figure 6: Status Register Polling Flowchart ..................................................................................................... 20
Figure 7: Lock Register Program Flowchart ..................................................................................................... 23
Figure 8: WRITE TO BUFFER PROGRAM Flowchart ........................................................................................ 33
Figure 9: ENHANCED BUFFERED PROGRAM Flowchart ................................................................................ 37
Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm ...................................................................... 47
Figure 11: Software Protection Scheme – Single Die ........................................................................................ 53
Figure 12: Power-Up Timing .......................................................................................................................... 58
Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress ...................................................... 59
Figure 14: Reset AC Timing During PROGRAM/ERASE Operation .................................................................... 60
Figure 15: AC Measurement Load Circuit ....................................................................................................... 62
Figure 16: AC Measurement I/O Waveform ..................................................................................................... 62
Figure 17: Random Read AC Timing (8-Bit Mode) ........................................................................................... 66
Figure 18: Random Read AC Timing (16-Bit Mode) ......................................................................................... 66
Figure 19: Page Read AC Timing (16-Bit Mode) ............................................................................................... 67
Figure 20: WE#-Controlled Program AC Timing (8-Bit Mode) .......................................................................... 69
Figure 21: WE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 70
Figure 22: CE#-Controlled Program AC Timing (8-Bit Mode) ........................................................................... 72
Figure 23: CE#-Controlled Program AC Timing (16-Bit Mode) ......................................................................... 73
Figure 24: Die/Block Erase AC Timing (8-Bit Mode) ........................................................................................ 74
Figure 25: Accelerated Program AC Timing ..................................................................................................... 75
Figure 26: Data Polling AC Timing .................................................................................................................. 76
Figure 27: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode) .......................................................... 76
Figure 28: 56-Pin TSOP – 14mm x 20mm ........................................................................................................ 78
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512Mb: 3V Embedded Parallel NOR Flash
Features
List of Tables
Table 1: Part Number Information ................................................................................................................... 2
Table 2: Signal Descriptions ........................................................................................................................... 11
Table 3: 512Mb, Blocks[511:256] – Upper Die .................................................................................................. 12
Table 4: 512Mb, Blocks[255:0] – Lower Die ...................................................................................................... 13
Table 5: Bus Operations ................................................................................................................................. 14
Table 6: Status Register Bit Definitions ........................................................................................................... 16
Table 7: Operations and Corresponding Bit Settings ........................................................................................ 17
Table 8: Lock Register Bit Definitions ............................................................................................................. 21
Table 9: Block Protection Status ..................................................................................................................... 21
Table 10: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ........................................... 24
Table 11: Read Electronic Signature ............................................................................................................... 28
Table 12: Block Protection ............................................................................................................................. 28
Table 13: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit ................................ 42
Table 14: Extended Memory Blocks and Data ................................................................................................. 48
Table 15: V PP/WP# Functions ......................................................................................................................... 50
Table 16: Query Structure Overview ............................................................................................................... 53
Table 17: CFI Query Identification String ........................................................................................................ 54
Table 18: CFI Query System Interface Information .......................................................................................... 54
Table 19: Device Geometry Definition ............................................................................................................ 55
Table 20: Primary Algorithm-Specific Extended Query Table ........................................................................... 55
Table 21: Security Code Area .......................................................................................................................... 57
Table 22: Power-Up Wait Timing Specifications .............................................................................................. 58
Table 23: Reset AC Specifications ................................................................................................................... 59
Table 24: Absolute Maximum/Minimum Ratings ............................................................................................ 61
Table 25: Operating Conditions ...................................................................................................................... 61
Table 26: Input/Output Capacitance .............................................................................................................. 62
Table 27: DC Current Characteristics .............................................................................................................. 63
Table 28: DC Voltage Characteristics .............................................................................................................. 64
Table 29: Read AC Characteristics .................................................................................................................. 65
Table 30: WE#-Controlled Write AC Characteristics ......................................................................................... 68
Table 31: CE#-Controlled Write AC Characteristics ......................................................................................... 71
Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics .............................................. 75
Table 33: Program/Erase Characteristics ........................................................................................................ 77
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512Mb: 3V Embedded Parallel NOR Flash
Important Notes and Warnings
Important Notes and Warnings
Micron Technology, Inc. ("Micron") reserves the right to make changes to information published in this document,
including without limitation specifications and product descriptions. This document supersedes and replaces all
information supplied prior to the publication hereof. You may not rely on any information set forth in this document if you obtain the product described herein from any unauthorized distributor or other source not authorized
by Micron.
Automotive Applications. Products are not designed or intended for use in automotive applications unless specifically designated by Micron as automotive-grade by their respective data sheets. Distributor and customer/distributor shall assume the sole risk and liability for and shall indemnify and hold Micron harmless against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, death, or property damage resulting directly or indirectly from any use of nonautomotive-grade products in automotive applications. Customer/distributor shall ensure that the terms and conditions of sale between customer/distributor and any customer of distributor/customer (1) state that Micron
products are not designed or intended for use in automotive applications unless specifically designated by Micron
as automotive-grade by their respective data sheets and (2) require such customer of distributor/customer to indemnify and hold Micron harmless against all claims, costs, damages, and expenses and reasonable attorneys'
fees arising out of, directly or indirectly, any claim of product liability, personal injury, death, or property damage
resulting from any use of non-automotive-grade products in automotive applications.
Critical Applications. Products are not authorized for use in applications in which failure of the Micron component could result, directly or indirectly in death, personal injury, or severe property or environmental damage
("Critical Applications"). Customer must protect against death, personal injury, and severe property and environmental damage by incorporating safety design measures into customer's applications to ensure that failure of the
Micron component will not result in such harms. Should customer or distributor purchase, use, or sell any Micron
component for any critical application, customer and distributor shall indemnify and hold harmless Micron and
its subsidiaries, subcontractors, and affiliates and the directors, officers, and employees of each against all claims,
costs, damages, and expenses and reasonable attorneys' fees arising out of, directly or indirectly, any claim of
product liability, personal injury, or death arising in any way out of such critical application, whether or not Micron or its subsidiaries, subcontractors, or affiliates were negligent in the design, manufacture, or warning of the
Micron product.
Customer Responsibility. Customers are responsible for the design, manufacture, and operation of their systems,
applications, and products using Micron products. ALL SEMICONDUCTOR PRODUCTS HAVE INHERENT FAILURE RATES AND LIMITED USEFUL LIVES. IT IS THE CUSTOMER'S SOLE RESPONSIBILITY TO DETERMINE
WHETHER THE MICRON PRODUCT IS SUITABLE AND FIT FOR THE CUSTOMER'S SYSTEM, APPLICATION, OR
PRODUCT. Customers must ensure that adequate design, manufacturing, and operating safeguards are included
in customer's applications and products to eliminate the risk that personal injury, death, or severe property or environmental damages will result from failure of any semiconductor component.
Limited Warranty. In no event shall Micron be liable for any indirect, incidental, punitive, special or consequential
damages (including without limitation lost profits, lost savings, business interruption, costs related to the removal
or replacement of any products or rework charges) whether or not such damages are based on tort, warranty,
breach of contract or other legal theory, unless explicitly stated in a written agreement executed by Micron's duly
authorized representative.
General Description
The M29W512GH is an asynchronous, uniform block, parallel NOR Flash memory device manufactured with 65nm single-level cell (SLC) technology. It is a 512Mb stacked
device that contains two 256Mb die. READ, ERASE, and PROGRAM operations are per-
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512Mb: 3V Embedded Parallel NOR Flash
General Description
formed using a single low-voltage supply. Upon power-up, the device defaults to read
array mode. Only one die at a time can be selected and erased/programmed.
The main memory array is divided into uniform blocks that can be erased independently so that valid data is preserved, while old data is purged. PROGRAM and ERASE commands are written to the memory command interface. An on-chip program/erase controller simplifies the process of programming or erasing the memory by managing all
special operations required to update the memory contents. The end of a PROGRAM or
ERASE operation can be detected and any error condition can be identified. The command set required to control the device is JEDEC-compliant.
CE#, OE#, and WE# control the bus operation of the device and enable a simple connection to most microprocessors, often without additional logic.
The device supports asynchronous random read and page read from all blocks of the
array. It features a write-to-buffer program capability that improves throughput by programming a buffer of 32 words in one command sequence. Also, in x16 mode, the enhanced buffered program capability improves throughput by programming 256 words
in one command sequence. The V PP/WP# signal enables faster programming.
The device contains two extended memory blocks, each of which has 128 words (x16) or
256 bytes (x8). The user can program these additional spaces, and then protect them to
permanently secure the contents. The device also features different levels of hardware
and software protection to secure blocks from unwanted modification.
Figure 1: Logic Diagram
VCC
VCCQ
VPP/WP#
15
A[24:0]
DQ[14:0]
DQ15/A-1
WE#
CE#
RY/BY#
OE#
RST#
BYTE#
VSS
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512Mb: 3V Embedded Parallel NOR Flash
General Description
Figure 2: Configuration Diagram
VPP/WP#
CE#
OE#
Upper die
(256Mb)
VCCQ
WE#
VSS
RST#
BYTE#
Lower die
(256Mb)
A[24:0]
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VCC
DQ[14:0]
DQ15/A-1
RY/BY#
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512Mb: 3V Embedded Parallel NOR Flash
Signal Assignments
Signal Assignments
Figure 3: 56-Pin TSOP (Top View)
A23
A22
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RST#
A21
VPP/WP#
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
RFU
RFU
Notes:
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49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
A24
RFU
A16
BYTE#
VSS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
VCC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
VSS
CE#
A0
RFU
VCCQ
1. A24 = A[MAX].
2. A-1 is the least significant address bit in x8 mode.
10
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512Mb: 3V Embedded Parallel NOR Flash
Signal Descriptions
Signal Descriptions
The signal description table below is a comprehensive list of signals for this device.
Table 2: Signal Descriptions
Name
Type
Description
A[MAX:0]
Input
Address: Selects the cells in the array to access during READ operations. During WRITE operations, they control the commands sent to the command interface of the program/erase controller.
CE#
Input
Chip enable: Activates the device, enabling READ and WRITE operations to be performed.
When CE# is HIGH, the device enters standby mode, and data outputs are at HIGH-Z.
OE#
Input
Output enable: Controls the bus READ operation.
WE#
Input
Write enable: Controls the bus WRITE operation of the command interface.
VPP/WP#
Input
VPP/Write Protect: Provides the WRITE PROTECT function and VPPH function. These functions
protect both the lowest and highest block and enable the device to enter unlock bypass
mode, respectively. (Refer to Hardware Protection and Bypass Operations for details.)
BYTE#
Input
Byte/word organization select: Switches between x8 and x16 bus modes. When BYTE# is
LOW, the device is in x8 mode; when HIGH, the device is in x16 mode.
RST#
Input
Reset: Applies a hardware reset to the device, which is achieved by holding RST# LOW for at
least tPLPX. After RST# goes HIGH, the device is ready for READ and WRITE operations (after
tPHEL or tRHEL, whichever occurs last). See RESET AC Specifications for more details.
DQ[7:0]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation. During
WRITE operations, they represent the commands sent to the command interface of the internal state machine.
DQ[14:8]
I/O
Data I/O: Outputs the data stored at the selected address during a READ operation when
BYTE# is HIGH. When BYTE# is LOW, these pins are not used and are High-Z. During WRITE
operations, these bits are not used. When reading the status register, these bits should be
ignored.
DQ15/A-1
I/O
Data I/O or address input: When the device operates in x16 bus mode, this pin behaves as
data I/O, together with DQ[14:8]. When the device operates in x8 bus mode, this pin behaves
as the least significant bit of the address. Except where stated otherwise, DQ15 = data I/O
(x16 mode); A-1 = address input (x8 mode).
RY/BY#
Output
Ready busy: Open-drain output that can be used to identify when the device is performing
a PROGRAM or ERASE operation. During PROGRAM or ERASE operations, RY/BY# is LOW,
and is High-Z during read mode, auto select mode, and erase suspend mode. After a hardware reset, READ and WRITE operations cannot start until RY/BY# goes High-Z (see RESET AC
Specifications for more details).
The use of an open-drain output enables the RY/BY# pins from several devices to be connected to a single pull-up resistor to VCCQ. A low value then indicates that one (or more) of the
devices is (are) busy. A resistor ≥10kΩ is recommended as a pull-up resistor to achieve 0.1V
VOL.
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512Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 2: Signal Descriptions (Continued)
Name
Type
VCC
Supply
Supply voltage: Provides the power supply for READ, PROGRAM, and ERASE operations.
The command interface is disabled when VCC ≤ VLKO. This prevents WRITE operations from accidentally damaging the data during power-up, power-down, and power surges. If the program/erase controller is programming or erasing during this time, then the operation aborts
and the contents being altered are invalid.
A 0.1μF capacitor should be connected between VCC and VSS to decouple the current surges
from the power supply. The PCB track widths must be sufficient to carry the currents required
during PROGRAM and ERASE operations (see DC Characteristics).
Description
VCCQ
Supply
I/O supply voltage: Provides the power supply to the I/O pins and enables all outputs to be
powered independently from VCC.
VSS
Supply
Ground: All VSS pins must be connected to the system ground.
RFU
–
Reserved for future use: RFUs should be not connected.
Memory Organization
Memory Configuration
The main memory array is divided into 128KB or 64KW uniform blocks.
Memory Map – 512Mb Density
Table 3: 512Mb, Blocks[511:256] – Upper Die
Address Range (x8)
Block
Block
Size
Start
511
128KB
3FE 0000h
⋮
⋮
383
2FE 0000h
Address Range (x16)
End
Block
Size
Start
End
3FF FFFFh
64KW
1FF 0000h
1FF FFFFh
⋮
⋮
⋮
2FF FFFFh
17F 0000h
17F FFFFh
⋮
⋮
⋮
⋮
⋮
319
27E 0000h
27F FFFFh
13F 0000h
13F FFFFh
⋮
⋮
⋮
⋮
⋮
256
200 0000h
201 FFFFh
100 0000h
100 FFFFh
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512Mb: 3V Embedded Parallel NOR Flash
Memory Organization
Table 4: 512Mb, Blocks[255:0] – Lower Die
Address Range (x8)
Address Range (x16)
Block
Block
Size
Start
End
Block
Size
Start
End
255
128KB
1FE 0000h
1FF FFFFh
64KW
0FF 0000h
0FF FFFFh
⋮
⋮
⋮
⋮
⋮
127
0FE 0000h
0FF FFFFh
07F 0000h
07F FFFFh
⋮
⋮
⋮
⋮
⋮
63
07E 0000h
07F FFFFh
03F 0000h
03F FFFFh
⋮
⋮
⋮
⋮
⋮
0
000 0000h
001 FFFFh
000 0000h
000 FFFFh
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512Mb: 3V Embedded Parallel NOR Flash
Bus Operations
Bus Operations
Table 5: Bus Operations
Notes 1 and 2 apply to entire table
8-Bit Mode
Operation
READ
CE# OE# WE# RST# VPP/WP#
L
L
H
16-Bit Mode
A[MAX:0],
DQ15/A-1
DQ[14:8]
DQ[7:0]
A[MAX:0]
DQ15/A-1,
DQ[14:0]
Cell address
High-Z
Data output
Cell address
Data output
input4
Command
address
Data input4
H
X
Command
address
High-Z
WRITE
L
H
L
H
X3
STANDBY
H
X
X
H
X
X
High-Z
High-Z
X
High-Z
OUTPUT
DISABLE
L
H
H
H
X
X
High-Z
High-Z
X
High-Z
RESET
X
X
X
L
X
X
High-Z
High-Z
X
High-Z
Notes:
Data
1. Typical glitches of less than 3ns on CE#, WE#, and RST# are ignored by the device and do
not affect bus operations.
2. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
3. If WP# is LOW, then both the highest and the lowest block remains protected.
4. Data input is required when issuing a command sequence or when performing data
polling or block protection.
Read
Bus READ operations read from the memory cells, registers, or Common Flash Interface
(CFI) space. To accelerate the READ operation, the memory array can be read in page
mode where data is internally read and stored in a page buffer.
Page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus
mode and A[2:0] plus DQ15/A-1 in x8 bus mode. The extended memory blocks and CFI
area do not support page read mode.
A valid bus READ operation involves setting the desired address on the address inputs,
taking CE# and OE# LOW, and holding WE# HIGH. The data I/Os will output the value.
(See AC Characteristics for details about when the output becomes valid.)
Write
Bus WRITE operations write to the command interface. A valid bus WRITE operation
begins by setting the desired address on the address inputs. The address inputs are
latched by the command interface on the falling edge of CE# or WE#, whichever occurs
last. The data I/Os are latched by the command interface on the rising edge of CE# or
WE#, whichever occurs first. OE# must remain HIGH during the entire bus WRITE operation. (See AC Characteristics for timing requirement details.)
Standby and Automatic Standby
Driving CE# HIGH in read mode causes the device to enter standby mode, and data
I/Os to be High-Z. To reduce the supply current to the standby supply current (I CC2),
CE# must be held within V CC ±0.3V. (See DC Characteristics.)
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512Mb: 3V Embedded Parallel NOR Flash
Bus Operations
During PROGRAM or ERASE operations, the device continues to use the program/erase
supply current (ICC3) until the operation completes.
Automatic standby allows the memory to achieve low power consumption during read
mode. After a READ operation, if CMOS levels (VCC ± 0.3 V) are used to drive the bus
and the bus is inactive for tAVQV + 30ns or more, the memory enters automatic standby
mode, where the internal supply current is reduced to the standby supply current, ICC2
(see DC Characteristics). The data inputs/outputs still output data if a READ operation
is in progress. Depending on the load circuits connected to the data bus, V CCQ can have
null power consumption when the memory enters automatic standby mode.
Output Disable
Data I/Os are High-Z when OE# is HIGH.
Reset
During reset mode, the device is deselected and the outputs are High-Z. The device is in
reset mode when RST# is LOW. Power consumption is reduced to the standby level, independent of CE#, OE#, or WE# inputs.
CCMTD-1725822587-9451
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15
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Registers
Status Register
The device has two status registers: one for each die. Each operation initiated in one die
must be terminated before attempting to start a new operation in the other die. During
PROGRAM or ERASE operations in one die, the related status register should be monitored by asserting A[24].
Table 6: Status Register Bit Definitions
Notes 1 and 7 apply to entire table
Bit
Name
Settings
Description
Notes
DQ7
Data polling 0 or 1, depending on
bit
operations
Monitors whether the program/erase controller has success
fully completed its operation, or has responded to an ERASE
SUSPEND operation.
2, 3, 4
DQ6
Toggle bit
Toggles: 0 to 1, 1 to 0,
and so on
Monitors whether the program/erase controller has successfully completed its operations, or has responded to an ERASE
SUSPEND operation. During a PROGRAM/ERASE operation,
DQ6 toggles from 0 to 1, 1 to 0, and so on, with each successive READ operation from any address.
3, 4, 5
DQ5
Error bit
0 = Success
1 = Failure
Identifies errors detected by the program/erase controller. DQ5
is set to 1 when a PROGRAM, BLOCK ERASE, or DIE ERASE operation fails to write the correct data to the memory.
4, 6
DQ3
Erase timer
bit
0 = Erase not in progress
1 = Erase in progress
Identifies the start of program/erase controller operation during a BLOCK ERASE command. Before the program/erase controller starts, this bit is set to 0, and additional blocks to be
erased can be written to the command interface.
4
DQ2
Alternative
toggle bit
Toggles: 0 to 1, 1 to 0,
and so on
Monitors the program/erase controller during ERASE operations. During DIE ERASE, BLOCK ERASE, and ERASE SUSPEND
operations, DQ2 toggles from 0 to 1, 1 to 0, and so on, with
each successive READ operation from addresses within the
blocks being erased.
DQ1
Buffered
program
abort bit
1 = Abort
Indicates a BUFFER PROGRAM operation abort. The BUFFERED
PROGRAM ABORT and RESET command must be issued to return the device to read mode (see WRITE TO BUFFER PROGRAM command).
Notes:
CCMTD-1725822587-9451
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3, 4
1. The status register can be read during PROGRAM, ERASE, or ERASE SUSPEND operations;
the READ operation outputs data on DQ[7:0].
2. For a PROGRAM operation in progress, DQ7 outputs the complement of the bit being
programmed. For a READ operation from the address previously programmed successfully, DQ7 outputs existing DQ7 data. For a READ operation from addresses with blocks
to be erased while an ERASE SUSPEND operation is in progress, DQ7 outputs 0; upon
successful completion of the ERASE SUSPEND operation, DQ7 outputs 1. For an ERASE
operation in progress, DQ7 outputs 0; upon either operation's successful completion,
DQ7 outputs 1.
3. After successful completion of a PROGRAM or ERASE operation, the device returns to
read mode.
16
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512Mb: 3V Embedded Parallel NOR Flash
Registers
4. During erase suspend mode, READ operations to addresses within blocks not being
erased output memory array data as if in read mode. A protected block is treated the
same as a block not being erased. See Toggle Flowchart for more information.
5. During erase suspend mode, DQ6 toggles when addressing a cell within a block being
erased. The toggling stops when the program/erase controller has suspended the ERASE
operation. See Toggle Flowchart for more information.
6. When DQ5 is set to 1, a READ/RESET command must be issued before any subsequent
command.
7. The status register must be addressed in the die under modification, with A24 asserted
accordingly.
Table 7: Operations and Corresponding Bit Settings
Note 1 and 3 apply to entire table
Operation
Address
DQ7
DQ6
DQ5
DQ3
DQ2
DQ1
RY/BY#
Notes
PROGRAM
Any address
DQ7#
Toggle
0
–
No toggle
0
0
2
PROGRAM during
ERASE SUSPEND
Any address
DQ7#
Toggle
0
–
–
–
0
ENHANCED
BUFFERED
PROGRAM
Any address
–
Toggle
0
–
–
–
0
BUFFERED
PROGRAM ABORT
Any address
DQ7#
Toggle
0
–
–
1
0
PROGRAM error
Any address
DQ7#
Toggle
1
–
–
–
High-Z
DIE ERASE
Any address
0
Toggle
0
1
Toggle
–
0
BLOCK ERASE
before time-out
Erasing block
0
Toggle
0
0
Toggle
–
0
Non-erasing block
0
Toggle
0
0
No toggle
–
0
BLOCK ERASE
ERASE SUSPEND
Erasing block
0
Toggle
0
1
Toggle
–
0
Non-erasing block
0
Toggle
0
1
No toggle
–
0
Erasing block
1
No toggle
0
–
Toggle
–
High-Z
Outputs memory array data as if in read mode
–
High-Z
Good block
address
0
Toggle
1
1
No toggle
–
High-Z
Faulty block
address
0
Toggle
1
1
Toggle
–
High-Z
Non-erasing block
BLOCK ERASE
error
Notes:
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2
1. Unspecified data bits should be ignored.
2. DQ7# for buffer program is related to the last address location loaded.
3. The status register must be addressed in the die under modification with A24 asserted
accordingly.
17
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 4: Data Polling Flowchart
Start
Read DQ7, DQ5, and DQ1
at valid address1
Yes
DQ7 = Data
No
No
DQ1 = 13
No
DQ5 = 12
Yes
Yes
Read DQ7 at valid address
DQ7 = Data
Yes
No
Failure 4
Notes:
CCMTD-1725822587-9451
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Success
1. Valid address is the address being programmed or an address within the block being
erased.
2. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO
BUFFER PROGRAM ABORT operation.
18
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 5: Toggle Bit Flowchart
Start
Read DQ6 at valid address
Read DQ6, DQ5, and DQ1
at valid address
DQ6 = Toggle
Yes
No
DQ1 = 1
No
No
DQ5 = 1
Yes
Yes
Read DQ6 (twice) at valid address
DQ6 = Toggle
No
Yes
Failure1
Note:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
Success
1. Failure results: DQ5 = 1 indicates an operation error; DQ1 = 1 indicates a WRITE TO
BUFFER PROGRAM ABORT operation.
19
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 6: Status Register Polling Flowchart
Start
Read 1
DQ7 = Valid data
Yes
Read 2
Read 3
PROGRAM operation
Yes
Read 3 correct data?
Yes
No
No
No
DQ5 = 1
Yes
PROGRAM operation
failure
Read 2
No
DQ6 = Toggling
Yes
Read2.DQ6 = Read3.DQ6
Read 3
Device error
No
DQ6 = Toggling
Yes
Read1.DQ6 = Read2.DQ6
DQ2 = Toggling
Timeout failure
Read2.DQ2 = Read3.DQ2
No
No
Yes
DQ1 = 1
Erase/suspend mode
No
ERASE operation
complete
Device busy: Repolling
WRITE TO BUFFER
PROGRAM
Yes
Yes
PROGRAM operation
complete
WRITE TO BUFFER
PROGRAM
abort
No
Device busy: Repolling
Lock Register
The device has two lock registers: one for each die. Micron recommends programming
both of the lock registers with the same contents in order to have the same protection
scheme for both the upper and lower die.
CCMTD-1725822587-9451
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Table 8: Lock Register Bit Definitions
Note 1 applies to entire table
Bit Name
Settings
Description
Notes
DQ2 Password
0 = Password protection
protection
mode enabled
mode lock bit 1 = Password protection
mode disabled (default)
Places the device permanently in password protection mode.
2
DQ1 Nonvolatile
0 = Nonvolatile protection
protection
mode enabled with passmode lock bit word protection mode
permanently disabled
1 = Nonvolatile protection
mode enabled (default)
Places the device in nonvolatile protection mode with password protection mode permanently disabled. When shipped
from the factory, the device will operate in nonvolatile protection mode, and the memory blocks are unprotected.
2
DQ0 Extended
0 = Protected
memory
1 = Unprotected (default)
block
protection bit
If the device is shipped with the extended memory block unlocked, the block can be protected by setting this bit to 0. The
extended memory block protection status can be read in auto
select mode by issuing an AUTO SELECT command.
Notes:
1. The lock register is a 16-bit, one-time programmable register. DQ[15:3] are reserved and
are set to a default value of 1.
2. The password protection mode lock bit and nonvolatile protection mode lock bit cannot
both be programmed to 0. Any attempt to program one bit while the other bit is being
programmed causes the operation to abort, and the device returns to read mode. The
device is shipped from the factory with the default setting.
Table 9: Block Protection Status
Nonvolatile
Nonvolatile
Volatile
Protection Bit Protection Protection
Lock Bit1
Bit2
Bit3
Block
Protection
Status
Block Protection Status
1
1
1
00h
Block unprotected; nonvolatile protection bit changeable.
1
1
0
01h
Block protected by volatile protection bit; nonvolatile protection bit changeable.
1
0
1
01h
Block protected by nonvolatile protection bit; nonvolatile
protection bit changeable.
1
0
0
01h
Block protected by nonvolatile protection bit and volatile
protection bit; nonvolatile protection bit changeable.
0
1
1
00h
Block unprotected; nonvolatile protection bit unchangeable.
0
1
0
01h
Block protected by volatile protection bit; nonvolatile protection bit unchangeable.
0
0
1
01h
Block protected by nonvolatile protection bit; nonvolatile
protection bit unchangeable.
0
0
0
01h
Block protected by nonvolatile protection bit and volatile
protection bit; nonvolatile protection bit unchangeable.
Notes:
CCMTD-1725822587-9451
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1. Nonvolatile protection bit lock bit: when set to 1, all nonvolatile protection bits are unlocked; when set to 0, all nonvolatile protection bits are locked.
21
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512Mb: 3V Embedded Parallel NOR Flash
Registers
2. Block nonvolatile protection bit: when set to 1, the block is unprotected; when set to 0,
the block is protected.
3. Block volatile protection bit: when set to 1, the block is unprotected; when set to 0, the
block is protected.
CCMTD-1725822587-9451
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512Mb: 3V Embedded Parallel NOR Flash
Registers
Figure 7: Lock Register Program Flowchart
Start
Enter LOCK REGISTER command set
Address/data (unlock) cycle 1
Address/data (unlock) cycle 2
Address/data cycle 3
PROGRAM LOCK REGISTER
Address/data cycle 1
Address/data cycle 2
Polling algorithm
Yes
Done?
No
DQ5 = 1
No
Yes
Success:
EXIT PROTECTION command set
(Returns to device read mode)
Address/data cycle 1
Address/data cycle 2
Notes:
CCMTD-1725822587-9451
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Failure:
READ/RESET
(Returns device to read mode)
1. Each lock register bit can be programmed only once.
2. See the Block Protection Command Definitions table for address-data cycle details.
23
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512Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
Standard Command Definitions – Address-Data Cycles
A command sequence must be issued to the selected die; that is, the command sequence is address-sensitive to MSB A24. Only one die at a time can be selected and
read, erased, programmed, or protected.
Table 10: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Note 1 applies to entire table
Address and Data Cycles
Command and
Code/Subcode
Bus
Size
1st
A
2nd
D
3rd
4th
A
D
A
D
555
55
X
F0
2AA
55
X
F0
555
55
AAA
90
A
5th
D
A
6th
D
A
D
Notes
READ and AUTO SELECT Operations
READ/RESET (F0h)
x8
x16
READ CFI (98h)
AUTO SELECT (90h)
X
F0
AAA
AA
X
F0
555
AA
x8
AA
98
x16
55
x8
AAA
x16
555
x8
AAA
x16
555
x8
X
90
X
00
x8
AAA
AA
555
55
x16
555
x8
X
A0
PA
PD
AAA
AA
555
55
BAd
25
BAd
N
PA
PD
555
55
AAA
F0
AA
2AA
555
Note Note
2
2
2, 3, 4
BYPASS Operations
UNLOCK BYPASS (20h)
UNLOCK BYPASS
RESET (90h/00h)
AA
555
55
2AA
AAA
20
555
x16
PROGRAM Operations
PROGRAM (A0h)
UNLOCK BYPASS
PROGRAM (A0h)
WRITE TO BUFFER
PROGRAM (25h)
UNLOCK BYPASS
WRITE TO BUFFER
PROGRAM (25h)
WRITE TO BUFFER
PROGRAM CONFIRM
(29h)
BUFFERED PROGRAM
ABORT and RESET (F0h)
ENTER ENHANCED
BUFFERED
PROGRAM (38h)
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2AA
AAA
A0
PA
PD
555
5
x16
x8
x16
555
x8
BAd
25
BAd
29
x8
AAA
AA
x16
555
BAd
N
PA
PD
6, 7, 8
2AA
5
x16
x8
x16
2AA
555
x8
x16
NA
555
AA
2AA
55
555
24
38
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512Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
Table 10: Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Note 1 applies to entire table
Address and Data Cycles
Command and
Code/Subcode
Bus
Size
ENHANCED
BUFFERED
PROGRAM (33h)
1st
2nd
3rd
4th
A
D
A
D
A
D
BAd
33
BAd
(00)
Data
BAd
(01)
Data
x8
x16
EXIT ENHANCED
BUFFERED
PROGRAM (90h)
ENHANCED
BUFFERED
PROGRAM ABORT (F0h)
PROGRAM SUSPEND
(B0h)
D
A
6th
D
A
D
NA
x8
x16
A
5th
Notes
9
NA
X
90
X
00
x8
NA
x16
555
AA
2AA
55
555
F0
x8
X
B0
X
30
x8
AAA
AA
555
55
AAA
80
x16
555
x8
X
80
X
10
AA
555
55
x16
PROGRAM RESUME
(30h)
x8
x16
ERASE Operations
DIE ERASE (80/10h)
2AA
UNLOCK BYPASS
DIE ERASE (80/10h)
x16
BLOCK ERASE (80/30h)
x8
AAA
x16
555
x8
X
80
X
B0
X
30
UNLOCK BYPASS
BLOCK ERASE (80/30h)
x16
ERASE SUSPEND (B0h)
x8
555
2AA
BAd
AAA
AA
555
555
55
2AA
AAA
10
555
5
AAA
555
30
80
AAA
555
AA
555
55
BAd
30
10
2AA
5
x16
ERASE RESUME (30h)
x8
x16
Notes:
CCMTD-1725822587-9451
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1. A = Address; D = Data; X = "Don't Care;" BAd = Any address in the block; N = Number of
bytes to be programmed; PA = Program address; PD = Program data; Gray shading = Not
applicable. All values in the table are hexadecimal. Some commands require both a command code and a sub code. A command sequence must be issued according to the selected die asserting A24.
2. These cells represent read cycles (versus write cycles for the others).
3. AUTO SELECT enables the device to read the manufacturer code, device code, block protection status, and extended memory block protection indicator.
4. AUTO SELECT addresses and data are specified in the Read Electronic Signature table
and the Extended Memory Block Protection table.
5. For any UNLOCK BYPASS ERASE/PROGRAM command, the first two UNLOCK cycles are
unnecessary.
25
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512Mb: 3V Embedded Parallel NOR Flash
Standard Command Definitions – Address-Data Cycles
6. BAd must be the same as the address loaded during the WRITE TO BUFFER PROGRAM
third and fourth cycles.
7. WRITE TO BUFFER PROGRAM operation: Maximum cycles = 68 (x8) and 36 (x16). UNLOCK BYPASS WRITE TO BUFFER PROGRAM operation: Maximum cycles = 66 (x8), 34
(x16). WRITE TO BUFFER PROGRAM operation: N + 1 = bytes to be programmed; maximum buffer size = 64 bytes (x8) and 32 words (x16).
8. For x8, A[MAX:5] address pins should remain unchanged while A[4:0] and A-1 pins are
used to select a byte within the N + 1 byte page. For x16, A[MAX:5] address pins should
remain unchanged, while A[4:0] pins are used to select a word within the N + 1 word
page.
9. The following is content for address-data cycles 256 through 258: BAd (FE) - Data; BAd
(FF) - Data; BAd (00) - 29.
10. BLOCK ERASE address cycles can extend beyond six address-data cycles, depending on
the number of blocks to be erased.
CCMTD-1725822587-9451
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512Mb: 3V Embedded Parallel NOR Flash
READ and AUTO SELECT Operations
READ and AUTO SELECT Operations
READ/RESET Command
The READ/RESET (F0h) command returns the device to read mode and resets the errors
in the status register. One or three bus WRITE operations can be used to issue the
READ/RESET command.
To return the device to read mode, this command can be issued between bus WRITE
cycles before the start of a PROGRAM or ERASE operation. If the READ/RESET command is issued during the timeout of a BLOCK ERASE operation, the device requires up
to 10μs to abort, during which time no valid data can be read.
This command will not abort an ERASE operation while in erase suspend mode, nor will
it abort a PROGRAM operation while in program suspend mode.
READ CFI Command
The READ CFI (98h) command puts the device in read CFI mode and is only valid when
the device is in read array or auto select mode. One bus WRITE cycle is required to issue
the command.
Once in read CFI mode, bus READ operations will output data from the CFI memory
area (Refer to Common Flash Interface for details). A READ/RESET command must be
issued to return the device to the previous mode (read array or auto select ). A second
READ/RESET command is required to put the device in read array mode from auto select mode.
AUTO SELECT Command
At power-up or after a hardware reset, the device is in read mode. It can then be put in
auto select mode by issuing an AUTO SELECT (90h) command or by applying V ID to A9.
Auto select mode enables the following device information to be read:
• Electronic signature, which includes manufacturer and device code information (see
the Read Electronic Signature table).
• Block protection, which includes the block protection status and extended memory
block protection indicator (see the Block Protection table).
Electronic signature or block protection information is read by executing a READ operation with control signals and addresses set, as shown in the Read Electronic Signature
table or the Block Protection table, respectively.
Auto select mode can be used by the programming equipment to automatically match a
device with the application code to be programmed.
Three consecutive bus WRITE operations are required to issue an AUTO SELECT command. The device remains in auto select mode until a READ/RESET or READ CFI command is issued.
The device cannot enter auto select mode when a PROGRAM or ERASE operation is in
progress (RY/BY# LOW). However, auto select mode can be entered if the PROGRAM or
ERASE operation has been suspended by issuing a PROGRAM SUSPEND or ERASE SUSPEND command.
To enter auto select mode by applying V ID to A9, see the Read Electronic Signature table
and the Block Protection table. A24 must be asserted according to the selected die.
CCMTD-1725822587-9451
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512Mb: 3V Embedded Parallel NOR Flash
READ and AUTO SELECT Operations
Auto select mode is exited by performing a reset. The device returns to read mode unless it entered auto select mode after an ERASE SUSPEND or PROGRAM SUSPEND
command, in which case it returns to erase or program suspend mode.
Table 11: Read Electronic Signature
Note 1 applies to entire table
Read Cycle
Manufacturer
Code
Device Code 1
Device Code 3
Device Code 3
CE#
L
L
L
L
OE#
L
L
L
L
WE#
H
H
H
H
X
X
X
X
A9
VID
VID
VID
VID
A8
X
X
X
X
Signal
Notes
Address Input, 8-Bit and 16-Bit
A[MAX:10]
A[7:5]
L
L
L
L
A4
X
X
X
X
A[3:1]
L
L
H
H
A0
L
H
L
H
X
X
X
X
DQ[14:8]
X
X
X
X
DQ[7:0]
20h
7Eh
23h
01h
0020h
227Eh
2223h
2201h
2
Address Input, 8-Bit Only
DQ[15]/A-1
Data Input/Output, 8-Bit Only
Data Input/Output, 16-Bit Only
DQ[15]/A-1, and DQ[14:0]
Notes:
1. H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
2. When using the AUTO SELECT command to enter auto select mode, applying VID to A9 is
not required. A9 can be either VIL or VIH.
Table 12: Block Protection
Note 1 applies to entire table
Read Cycle
Extended Memory
Block Verify Indicator
Block Protection
Status Indicator
CE#
L
L
OE#
L
L
WE#
H
H
H/L
Block base address
Signal
Notes
Address Input, 8-Bit and 16-Bit
A24
A[23:16]
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512Mb: 3V Embedded Parallel NOR Flash
BYPASS Operations
Table 12: Block Protection (Continued)
Note 1 applies to entire table
Read Cycle
Signal
A[15:10]
Extended Memory
Block Verify Indicator
Block Protection
Status Indicator
X
X
A9
VID
VID
A8
X
X
A[7:5]
L
L
A4
X
X
Notes
2
A[3:2]
L
L
A1
H
H
A0
H
L
X
X
DQ[14:8]
X
X
DQ[7:0]
99h (A24 = H)/89h (A24 = L)
01h
3, 5
19h (A24 = H)/09h (A24 = L)
00h
4, 6
0099h (A24 = H)/
0089h (A24 = L)
0001h
3, 5
0019h (A24 = H)/
0009h (A24 = L)
0000h
4, 6
Address Input, 8-Bit Only
DQ[15]/A-1
Data Input/Output, 8-Bit Only
Data Input/Output, 16-Bit Only
DQ[15]/A-1 and DQ[14:0]
Notes:
1. Read cycle output to DQ7 = Extended memory block protection indicator; BPS = Block
protection status; H = Logic level HIGH (VIH); L = Logic level LOW (VIL); X = HIGH or LOW.
2. When using the AUTO SELECT command to enter auto select mode, applying VID to A9 is
not required. A9 can be either VIL or VIH.
3. Extended memory blocks are Micron-prelocked (permanent).
4. Extended memory blocks are customer-lockable.
5. Block protection status = protected: 01h (in x8 mode) is output on DQ[7:0].
6. Block protection status = unprotected: 00h (in x8 mode) is output on DQ[7:0].
BYPASS Operations
UNLOCK BYPASS Command
The UNLOCK BYPASS (20h) command is used to place the device in unlock bypass
mode. Three bus WRITE operations are required to issue the UNLOCK BYPASS command.
When the device enters unlock bypass mode, the two initial UNLOCK cycles required
for a standard PROGRAM or ERASE operation are not needed, thus enabling faster total
program or erase time.
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PROGRAM Operations
The UNLOCK BYPASS command is used in conjunction with the UNLOCK BYPASS
PROGRAM or UNLOCK BYPASS ERASE commands to program or erase the device faster
than with standard PROGRAM or ERASE commands. When the cycle time to the device
is long, considerable time can be saved by using these commands. When in unlock bypass mode, only the following commands are valid:
• The UNLOCK BYPASS PROGRAM command can be issued to program addresses
within the device.
• The UNLOCK BYPASS BLOCK ERASE command can then be issued to erase one or
more memory blocks.
• The UNLOCK BYPASS DIE ERASE command can be issued to erase the whole memory array.
• The UNLOCK BYPASS WRITE TO BUFFER PROGRAM and UNLOCK BYPASS ENHANCED WRITE TO BUFFER PROGRAM commands can be issued to speed up the
programming operation.
• The UNLOCK BYPASS RESET command can be issued to return the device to read
mode.
In unlock bypass mode, the device can be read as if in read mode.
In addition to the UNLOCK BYPASS command, when V PP/WP# is raised to V PPH, the device automatically enters unlock bypass mode. When V PP/WP# returns to V IH or V IL, the
device is no longer in unlock bypass mode and normal operation resumes. The transitions from V IH to V PPH and from V PPH to V IH must be slower than tVHVPP (see Accelerated Program, Data Polling/Toggle AC Characteristics).
Note: Micron recommends the user enter and exit unlock bypass mode using the ENTER UNLOCK BYPASS and UNLOCK BYPASS RESET commands rather than raising
VPP/WP# to V PPH. V PP/WP# should never be raised to V PPH from any mode except read
mode; otherwise, the device may be left in an indeterminate state.
UNLOCK BYPASS RESET Command
The UNLOCK BYPASS RESET (90/00h) command is used to return to the read/reset
mode from the unlock bypass mode. Two bus WRITE operations are required to issue
the UNLOCK BYPASS RESET command. The READ/RESET command does not exit
from the unlock bypass mode.
PROGRAM Operations
PROGRAM Command
The PROGRAM (A0h) command can be used to program a value to one address in the
memory array. The command requires four bus WRITE operations, and the final WRITE
operation latches the address and data in the internal state machine and starts the program/erase controller. After programming has started, bus READ operations output the
status register contents.
Programming can be suspended and then resumed by issuing a PROGRAM SUSPEND
command and a PROGRAM RESUME command, respectively.
If the address falls in a protected block, the PROGRAM command is ignored, and the
data remains unchanged. The status register is not read, and no error condition is given.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
After the PROGRAM operation has completed, the device returns to read mode, unless
an error has occurred. If an error occurs, bus READ operations to the device continue to
output the status register. A READ/RESET command must be issued to reset the error
condition and return the device to read mode.
The PROGRAM command cannot change a bit from 0 to 1; an attempt to do so is
masked during a PROGRAM operation. Instead, an ERASE command must be used to
set all bits in one memory block or in the entire memory from 0 to 1.
The PROGRAM operation is aborted by performing a reset or by powering-down the device. In this case, data integrity cannot be ensured, and it is recommended that the
words or bytes that were aborted be reprogrammed.
UNLOCK BYPASS PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS PROGRAM (A0h)
command can be used to program one address in the memory array. The command requires two bus WRITE operations instead of four required by a standard PROGRAM
command; the final WRITE operation latches the address and data and starts the program/erase controller (The standard PROGRAM command requires four bus WRITE operations). A PROGRAM operation that uses the UNLOCK BYPASS PROGRAM command
behaves the same way as a PROGRAM operation that uses the PROGRAM command.
The operation cannot be aborted. A bus READ operation to the memory outputs the
status register.
WRITE TO BUFFER PROGRAM Command
The WRITE TO BUFFER PROGRAM (25h) command uses the 32-word program buffer to
speed up programming. A maximum of 32 words can be loaded into the program buffer.
The WRITE TO BUFFER PROGRAM command dramatically reduces system programming time compared to the standard unbuffered PROGRAM command.
When issuing a WRITE TO BUFFER PROGRAM command, V PP/WP# can be held either
HIGH or raised to V PPH. It can also be held LOW if the block is not the lowest or highest
block. The following successive steps are required to issue the WRITE TO BUFFER PROGRAM command:
First, two UNLOCK cycles are issued. Next, a third bus WRITE cycle sets up the WRITE
TO BUFFER PROGRAM command. The setup code can be addressed to any location
within the targeted block. Then, a fourth bus WRITE cycle sets up the number of words/
bytes to be programmed. The value of n is written to the same block address, where n +
1 is the number of words/bytes to be programmed. The value of n + 1 must not exceed
the size of the program buffer, or the operation will abort. A fifth cycle loads the first
address and data to be programmed. Last, n bus WRITE cycles load the address and data for each word/byte into the program buffer. Addresses must lie within the range of
start address + 1 to start address + (n - 1).
Optimum programming performance and lower power usage are achieved by aligning
the starting address at the beginning of a 32-word boundary. Any buffer size smaller
than 32 words is allowed within a 32-word boundary, while all addresses used in the operation must lie within the 32-word boundary. In addition, any crossing boundary buffer program will result in a program abort.
To program the contents of the program buffer, this command must be followed by a
WRITE TO BUFFER PROGRAM CONFIRM command.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
If an address is written several times during a WRITE TO BUFFER PROGRAM operation,
the address/data counter will be decremented at each data load operation, and the data
is programmed to the last word loaded into the buffer.
Invalid address combinations or an incorrect sequence of bus WRITE cycles will abort
the WRITE TO BUFFER PROGRAM command.
Satus register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
The WRITE TO BUFFER PROGRAM command should not be used to change a bit from
0 to 1; an attempt to do so is masked during the operation. Rather than using the WRITE
TO BUFFER PROGRAM command, the ERASE command should be used to set memory
bits from 0 to 1.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
Figure 8: WRITE TO BUFFER PROGRAM Flowchart
Start
WRITE TO BUFFER
command,
block address
WRITE TO BUFFER
confirm, block address
Write n,1
block address
Read data polling
register (DQ1, DQ5,
DQ7) at last loaded
address
First three cycles of the
WRITE TO BUFFER
PROGRAM command
Write buffer data,
start address
DQ7 = Data
X=n
No
No
DQ1 = 1
Yes
X=0
Yes
No
Abort
WRITE TO BUFFER
Yes
No
DQ5 = 1
Yes
Check data polling
register (DQ5, DQ7)
at last loaded address
Write to a different
block address
No
Write next data,3
program address pair
Yes
WRITE TO BUFFER
and PROGRAM
aborted2
DQ7 = Data4
Yes
No
Fail or
abort5
X=X-1
Notes:
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1. n + 1 is the number of addresses to be programmed.
2. The BUFFERED PROGRAM ABORT and RESET command must be issued to return the device to read mode.
3. When the block address is specified, any address in the selected block address space is
acceptable. However, when loading the program buffer address with data, all addresses
must fall within the selected program buffer page.
4. DQ7 must be checked because DQ5 and DQ7 may change simultaneously.
5. If this flowchart location is reached because DQ5 = 1, then the WRITE TO BUFFER PROGRAM command failed. If this flowchart location is reached because DQ1 = 1, then the
WRITE TO BUFFER PROGRAM command aborted. In both cases, the appropriate RESET
command must be issued to return the device to read mode: A RESET command if the
operation failed; a WRITE TO BUFFER PROGRAM ABORT AND RESET command if the operation aborted.
6. See the Standard Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit table for
details about the WRITE TO BUFFER PROGRAM command sequence.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
UNLOCK BYPASS WRITE TO BUFFER PROGRAM Command
When the device is in unlock bypass mode, the UNLOCK BYPASS WRITE TO BUFFER
(25h) command can be used to program the device in fast program mode. The command requires two bus WRITE operations fewer than the standard WRITE TO BUFFER
PROGRAM command.
The UNLOCK BYPASS WRITE TO BUFFER PROGRAM command behaves the same way
as the WRITE TO BUFFER PROGRAM command: the operation cannot be aborted, and
a bus READ operation to the memory outputs the status register.
The WRITE TO BUFFER PROGRAM CONFIRM command is used to confirm an UNLOCK BYPASS WRITE TO BUFFER PROGRAM command and to program the n +
1words/bytes loaded in the program buffer by this command.
WRITE TO BUFFER PROGRAM CONFIRM Command
The WRITE TO BUFFER PROGRAM CONFIRM (29h) command is used to confirm a
WRITE TO BUFFER PROGRAM command and to program the n + 1 words/bytes loaded
in the program buffer by this command.
BUFFERED PROGRAM ABORT AND RESET Command
A BUFFERED PROGRAM ABORT AND RESET (F0h) command must be issued to reset
the device to read mode when the BUFFER PROGRAM operation is aborted. The buffer
programming sequence can be aborted the following ways:
• Load a value that is greater than the page buffer size while programming the number
of locations to be programmed in the WRITE TO BUFFER PROGRAM command.
• Write to an address in a different block than the one specified during the WRITE TO
BUFFER PROGRAM command.
• Write an address/data pair to a different write buffer page than the one selected by
the starting address during the program buffer data loading stage of the operation.
• Write data other than the WRITE TO BUFFER PROGRAM CONFIRM command after
the specified number of data load cycles.
The abort condition is indicated by DQ1 = 1, DQ7 = DQ7# (for the last address location
loaded), DQ6 = toggle, and DQ5 = 0 (all of which are status register bits). A BUFFERED
PROGRAM ABORT AND RESET command sequence must be written to reset the device
for the next operation.
Note: The full three-cycle BUFFERED PROGRAM ABORT AND RESET command sequence is required when using buffer programming features in unlock bypass mode.
PROGRAM SUSPEND Command
The PROGRAM SUSPEND (B0h) command can be used to interrupt a program operation so that data can be read from any block. When the PROGRAM SUSPEND command
is issued during a PROGRAM operation, the device suspends the operation within the
program suspend latency time and updates the status register bits.
After the PROGRAM operation has been suspended, data can be read from any address.
However, data is invalid when read from an address where a PROGRAM operation has
been suspended.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
The PROGRAM SUSPEND command may also be issued during a PROGRAM operation
while an erase is suspended. In this case, data can be read from any address not in erase
suspend or program suspend mode. To read from the extended memory block area
(one-time programmable area), the ENTER/EXIT EXTENDED MEMORY BLOCK command sequences must be issued.
The system may also issue the AUTO SELECT command sequence when the device is in
program suspend mode. The system can read as many auto select codes as required.
When the device exits auto select mode, the device reverts to program suspend mode
and is ready for another valid operation.
The PROGRAM SUSPEND operation is aborted by performing a device reset or powerdown. In this case, data integrity cannot be ensured, and the words or bytes that were
aborted should be reprogrammed.
PROGRAM RESUME Command
The PROGRAM RESUME (30h) command must be issued to exit program suspend
mode and resume a PROGRAM operation. The controller can use DQ7 or DQ6 status
bits to determine the status of the PROGRAM operation. After a PROGRAM RESUME
command is issued, subsequent PROGRAM RESUME commands are ignored. Another
PROGRAM SUSPEND command can be issued after the device has resumed programming.
ENTER/EXIT ENHANCED BUFFERED PROGRAM Commands
The ENTER and EXIT ENHANCED BUFFERED PROGRAM commands are available only
in x16 mode. When the ENTER ENHANCED BUFFERED PROGRAM (38h) command is
issued, the device accepts only these commands, which can be executed multiple times.
To ensure successful completion of the ENTER ENHANCED BUFFERED PROGRAM
command, users should monitor the toggle bit. The EXIT ENHANCED BUFFERED PROGRAM (90h) command returns the device to read mode; two bus WRITE operations are
required to issue the command.
ENHANCED BUFFERED PROGRAM Command
The ENHANCED BUFFERED PROGRAM (33h) command uses a 256-word write buffer
to speed up programming. Each write buffer has the same addresses A[24:8]. This command dramatically reduces system programming time as compared to both the standard unbuffered PROGRAM command and the WRITE TO BUFFER command.
When issuing the ENHANCED BUFFERED PROGRAM command, the V PP/WP pin can
be held HIGH or raised to V PPH (see Program/Erase Characteristics). The following successive steps are required to issue the WRITE TO BUFFER PROGRAM command:
First, the ENTER ENHANCED BUFFERED PROGRAM command issued. Next, one bus
WRITE cycle sets up the ENHANCED BUFFERED PROGRAM command. The setup code
can be addressed to any location within the targeted block. Then, a second bus WRITE
cycle loads the first address and data to be programmed. There are a total of 256 address
and data loading cycles. When the 256 words are loaded to the buffer, a third WRITE cycle programs the contents of the buffer. Last, when the command completes, the EXIT
ENHANCED BUFFERED PROGRAM command is issued.
Address/data cycles must be loaded in ascending address order, from A[7:0] = 00000000
to A[7:0] = 11111111, until all 256 words are loaded. Invalid address combinations, or
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
the incorrect sequence of bus WRITE cycles, will abort the WRITE TO BUFFER PROGRAM command.
Status register bits DQ1, DQ5, DQ6, and DQ7 can be used to monitor the device status
during a WRITE TO BUFFER PROGRAM operation.
An external 12V supply can be used to improve programming efficiency.
When reprogramming data in a portion of memory already programmed (changing
programmed data from 0 to 1), operation failure can be detected by a logical OR between the previous value and the current value.
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512Mb: 3V Embedded Parallel NOR Flash
PROGRAM Operations
Figure 9: ENHANCED BUFFERED PROGRAM Flowchart
Start
ENHANCED BUFFERED
PROGRAM command,
block address
ENHANCED
BUFFERED PROGRAM
command set
First cycle of the
ENHANCED BUFFERED PROGRAM
command
Write buffer data,
start address (00),
X=255
Read DQ6 at
valid address
Read
DQ5 and DQ6
at valid address
Yes
X=0
No
DQ6 =
Abort WRITE
TO BUFFER
No
Yes
Write to a different
block address
toggle
No
Yes
No
ENHANCED BUFFERED
PROGRAM aborted (1)
Write next data, (2)
program address pair
DQ5 =1
Yes
Write next data, (2)
program address pair
Read DQ6
twice
at valid address
X = X-1
No
DQ6 =
toggle
ENHANCED BUFFERED
PROGRAM confirm,
block address
Yes
Fail
258th WRITE cycle of the
ENHANCED BUFFERED PROGRAM
command
Read status register
(DQ1, DQ5, DQ7) at
last loaded address
DQ7 = Data
No
DQ1 = 1
Yes
No
No
DQ5 = 1
Yes
Yes
Check status register
(DQ5, DQ7) at
last loaded address
New
Program?
Yes
No
DQ7 = Data
(3)
No
Fail or Abort(4)
Notes:
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Yes
Exit ENHANCED
BUFFERED PROGRAM
command set
End
1. The ENHANCED BUFFERED PROGRAM ABORT AND RESET command must be issued to
return the device to read mode.
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512Mb: 3V Embedded Parallel NOR Flash
ERASE Operations
2. When the block address is specified, all addresses in the selected block address space
must be issued starting from 00h. Furthermore, when loading the write buffer address
with data, data program addresses must be consecutive.
3. DQ7 must be checked since DQ5 and DQ7 may change simultaneously.
4. If this flowchart location is reached because DQ5 = 1, then the ENHANCED WRITE TO
BUFFER PROGRAM command failed. If this flowchart location is reached because DQ1 =
1, then the ENHANCED WRITE TO BUFFER PROGRAM command aborted. In both cases,
the appropriate RESET command must be issued to return the device to read mode: A
RESET command if the operation failed; an ENHANCED WRITE TO BUFFER PROGRAM
ABORT AND RESET command if the operation aborted.
ENHANCED BUFFERED PROGRAM ABORT AND RESET Command
The ENHANCED BUFFERED PROGRAM ABORT AND RESET command must be issued
to reset the device to read mode when the ENHANCED BUFFERED PROGRAM operation is aborted. The buffer programming sequence can be aborted the following ways:
• Write to an address in a different block than the one specified during the buffer load.
• Write an address/data pair to a different write buffer page than the one selected by
the starting address during the program buffer data loading stage of the operation.
• Write data other than the WRITE TO BUFFER PROGRAM CONFIRM command after
the 256 data load cycles.
• Load a value that is greater than or less than the 256 buffer size.
• Load address/data pairs in an incorrect sequence.
The abort condition is indicated by DQ1 = 1, DQ6 = toggle, and DQ5 = 0 (all of which are
status register bits).
ERASE Operations
Note: A full device ERASE cannot be performed, but a DIE ERASE command can be executed on each 256Mb die.
DIE ERASE Command
The DIE ERASE (80/10h) command erases a single 256Mb die. Six bus WRITE operations are required to issue the command and start the program/erase controller.
Protected blocks are not erased. If all of the blocks in a die are protected, the DIE ERASE
operation appears to start, but will terminate within approximately100μs, leaving the
data unchanged. No error is reported when protected blocks are not erased.
During the DIE ERASE operation, the device ignores all other commands, including
ERASE SUSPEND. The operation cannot be aborted. All bus READ operations performed during a DIE ERASE operation output the status register on the data I/Os. See
the Status Register for more details.
After the DIE ERASE operation completes, the device returns to read mode, unless an
error has occurred. If an error occurs, the device continues to output the status register.
A READ/RESET command must be issued to reset the error condition and return to
read mode.
The DIE ERASE command sets all of the bits in unprotected blocks of the device to 1. All
previous data is lost.
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512Mb: 3V Embedded Parallel NOR Flash
ERASE Operations
The operation is aborted by performing a reset or by powering-down the device. In this
case, data integrity cannot be ensured, and the entire die should erased again.
To erase the whole 512Mb array, two DIE ERASE operations are required: the first one
for die 0, and the second one for die 1. No parallel ERASE is allowed. The second DIE
ERASE operation must be issued after the completion of the first one.
UNLOCK BYPASS DIE ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS DIE ERASE (80/10h)
command can be used to erase all of the memory blocks in a die at one time. The command requires only two bus WRITE operations, instead of six, using the standard DIE
ERASE command; the final bus WRITE operation starts the program/erase controller.
The UNLOCK BYPASS DIE ERASE command behaves the same way as the DIE ERASE
command; the operation cannot be aborted, and a bus READ operation to the memory
outputs the status register.
BLOCK ERASE Command
The BLOCK ERASE (80/30h) command erases a list of one or more blocks belonging to
the same die. It sets all of the bits in the unprotected selected blocks to 1. All previous
data in the selected blocks is lost.
Six bus WRITE operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth bus WRITE operation using the
address of the additional block. After the command sequence is written, a block erase
timeout occurs. During the timeout period, additional block addresses and BLOCK
ERASE commands can be written. After the program/erase controller has started, it is
not possible to select any more blocks. Each additional block must therefore be selected
within the timeout period of the last block. The timeout timer restarts when an additional block is selected. After the sixth bus WRITE operation, a bus READ operation outputs the status register. See the WE#-Controlled Program waveforms for details on how
to identify whether the program/erase controller has started the BLOCK ERASE operation.
After the BLOCK ERASE operation completes, the device returns to read mode, unless
an error has occurred. If an error occurs, bus READ operations will continue to output
the status register. A READ/RESET command must be issued to reset the error condition and return to read mode.
If any selected blocks are protected, they are ignored and all the other selected blocks
are erased. If all of the selected blocks are protected, the BLOCK ERASE operation appears to start, but will terminate within approximately 100μs, leaving the data unchanged. No error condition is reported when protected blocks are not erased.
During the BLOCK ERASE operation, the device ignores all commands except the
ERASE SUSPEND command and the READ/RESET command, which is accepted only
during the timeout period. The operation is aborted by performing a reset or poweringdown the device. In this case, data integrity cannot be ensured, and the aborted blocks
should be erased again.
UNLOCK BYPASS BLOCK ERASE Command
When the device is in unlock bypass mode, the UNLOCK BYPASS BLOCK ERASE
(80/30h) command can be used to erase one or more memory blocks belonging to the
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512Mb: 3V Embedded Parallel NOR Flash
ERASE Operations
same die at a time. The command requires two bus WRITE operations, instead of six,
using the standard BLOCK ERASE command. The final bus WRITE operation latches the
address of the block and starts the program/erase controller.
To erase multiple blocks (after the first two bus WRITE operations have selected the first
block in the list), each additional block in the list can be selected by repeating the second bus WRITE operation using the address of the additional block.
The UNLOCK BYPASS BLOCK ERASE command behaves the same way as the BLOCK
ERASE command; the operation cannot be aborted, and a bus READ operation to the
memory outputs the status register. See the BLOCK ERASE Command for details.
ERASE SUSPEND Command
The ERASE SUSPEND (B0h) command temporarily suspends a BLOCK ERASE operation. One bus WRITE operation is required to issue the command. The block address is
"Don't Care."
The program/erase controller suspends the ERASE operation within the erase suspend
latency time of the ERASE SUSPEND command being issued. However, when the
ERASE SUSPEND command is written during the block erase timeout, the device immediately terminates the timeout period and suspends the ERASE operation. After the
program/erase controller has stopped, the device operates in read mode, and the
ERASE is suspended.
During an ERASE SUSPEND operation, it is possible to read and execute PROGRAM operations or WRITE TO BUFFER PROGRAM operations in blocks that are not suspended.
Both READ operations and PROGRAM operations behave normally on those blocks.
Reading from blocks that are suspended will output the status register. If any attempt is
made to program in a protected block or in the suspended block, the PROGRAM command is ignored, and the data remains unchanged. In this case, the status register is not
read, and no error condition is reported.
It is also possible to issue AUTO SELECT and UNLOCK BYPASS commands during an
ERASE SUSPEND operation. The READ/RESET command must be issued to return the
device to read array mode before the RESUME command will be accepted.
During an ERASE SUSPEND operation, a bus READ operation to the extended memory
block will output the extended memory block data. After the device enters extended
memory block mode, the EXIT EXTENDED MEMORY BLOCK command must be issued
before the ERASE operation can be resumed.
An ERASE SUSPEND command is ignored if it is written during a DIE ERASE operation.
If the ERASE SUSPEND operation is aborted by performing a device reset or powerdown, data integrity cannot be ensured, and the suspended blocks should be erased
again.
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512Mb: 3V Embedded Parallel NOR Flash
ERASE Operations
ERASE RESUME Command
The ERASE RESUME (30h) command restarts the program/erase controller after an
ERASE SUSPEND operation.
The device must be in read array mode before the RESUME command will be accepted.
An erase can be suspended and resumed more than once.
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512Mb: 3V Embedded Parallel NOR Flash
Block Protection Command Definitions – Address-Data Cycles
Block Protection Command Definitions – Address-Data Cycles
A command sequence must be issued according to the selected die; that is, a command
sequence is address-sensitive to MSB A24. Only one die at a time can be selected and
read, erased, programmed, or protected.
Table 13: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit
Notes 1 and 2 apply to entire table
Address and Data Cycles
Command and
Code/Subcode
Bus
Size
1st
2nd
3rd
4th
A
D
A
D
A
D
x8
AAA
AA
555
55
AAA
40
x16
555
AA
2AA
55
555
x8
X
A0
X
Data
X
Data
A
nth
D
…
A
D
Notes
LOCK REGISTER Commands
ENTER LOCK REGISTER
COMMAND SET (40h)
PROGRAM LOCK REGISTER
(A0h)
x16
READ LOCK REGISTER
x8
3
5
4, 5, 6
x16
PASSWORD PROTECTION Commands
ENTER PASSWORD
PROTECTION COMMAND
SET (60h)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
x8
X
A0
00
PWD0
x16
00
x8
00
PROGRAM PASSWORD
(A0h)
x16
READ PASSWORD
x8
UNLOCK PASSWORD
(25h/03)
60
3
PWAn PWDn
7
01
PWD1
02
PWD2
03
PWD3 …
PWD0
01
PWD1
02
PWD2
03
PWD3
25
00
03
00
PWD0
01
PWD1 …
C0
07
00
PWD7 4, 6, 8,
9
29
8, 10
x16
NONVOLATILE PROTECTION Commands
ENTER NONVOLATILE
PROTECTION COMMAND
SET (C0h)
PROGRAM NONVOLATILE
PROTECTION BIT (A0h)
READ NONVOLATILE
PROTECTION BIT STATUS
CLEAR ALL NONVOLATILE
PROTECTION BITS (80/30h)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
x8
X
A0
BAd
00
BAd
READ(0)
X
80
3
x16
x8
4, 6,
11
x16
x8
00
30
12
x16
NONVOLATILE PROTECTION BIT LOCK BIT Commands
ENTER NONVOLATILE
PROTECTION BIT LOCK BIT
COMMAND SET (50h)
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AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
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512Mb: 3V Embedded Parallel NOR Flash
Block Protection Command Definitions – Address-Data Cycles
Table 13: Block Protection Command Definitions – Address-Data Cycles, 8-Bit and 16-Bit (Continued)
Notes 1 and 2 apply to entire table
Address and Data Cycles
1st
2nd
3rd
Command and
Code/Subcode
Bus
Size
A
D
A
D
PROGRAM NONVOLATILE
PROTECTION BIT LOCK BIT
(A0h)
x8
X
A0
X
00
x16
X
READ(0)
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
x8
X
A0
BAd
00
BAd
READ(0)
X
A0
BAd
01
AAA
AA
555
55
x16
555
AA
2AA
55
555
x8
AAA
AA
555
55
AAA
x16
555
AA
2AA
55
555
X
90
X
00
READ NONVOLATILE
PROTECTION BIT LOCK BIT
STATUS
x8
A
4th
D
A
nth
D
…
A
D
Notes
11
4, 6,
11
x16
VOLATILE PROTECTION Commands
ENTER VOLATILE
PROTECTION COMMAND
SET (E0h)
PROGRAM VOLATILE
PROTECTION BIT (A0h)
E0
3
x16
READ VOLATILE
PROTECTION BIT STATUS
x8
x16
CLEAR VOLATILE
PROTECTION BIT (A0h)
x16
x8
4, 6,
11
EXTENDED MEMORY BLOCK Commands
ENTER EXTENDED
MEMORY BLOCK (88h)
EXIT EXTENDED
MEMORY BLOCK (90/00h)
x8
AAA
88
90
3
X
00
EXIT PROTECTION Commands
EXIT PROTECTION
COMMAND SET (90/00h)
Notes:
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x8
3
x16
1. Key: A = Address; D = Data; X = "Don’t Care;" BAd = Any address in the block; PWDn =
Password bytes 0 to 7; PWAn = Password address, n = 0 to 7; Gray = Not applicable. All
values in the table are hexadecimal.
2. DQ[15:8] are "Don’t Care" during UNLOCK and COMMAND cycles. A[MAX:16] are
"Don’t Care" during UNLOCK and COMMAND cycles, unless an address is required.
3. The ENTER command sequence must be issued prior to any operation. It disables READ
and WRITE operations from and to block 0. READ and WRITE operations from and to
any other block are allowed. Also, when an ENTER COMMAND SET command is issued,
an EXIT PROTECTION COMMAND SET command must be issued to return the device to
READ mode.
4. READ REGISTER/PASSWORD commands have no command code; CE# and OE# are driven
LOW and data is read according to a specified address.
5. Data = Lock register content.
6. All address cycles shown for this command are READ cycles.
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Block Protection Command Definitions – Address-Data Cycles
7. Only one portion of the password can be programmed or read by each PROGRAM PASSWORD command.
8. Each portion of the password can be entered or read in any order as long as the entire
64-bit password is entered or read.
9. For the x8 READ PASSWORD command, the nth (and final) address cycle equals the 8th
address cycle. From the 5th to the 8th address cycle, the values for each address and data pair continue the pattern shown in the table as follows: For x8, address and data = 04
and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
10. For the x8 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
11th address cycle. From the 5th to the 10th address cycle, the values for each address
and data pair continue the pattern shown in the table as follows: Address and data = 02
and PWD2; 03 and PWD3; 04 and PWD4; 05 and PWD5; 06 and PWD6; 07 and PWD7.
For the x16 UNLOCK PASSWORD command, the nth (and final) address cycle equals the
7th address cycle. For the 5th and 6th address cycles, the values for the address and data
pair continue the pattern shown in the table as follows: Address and data = 02 and
PWD2; 03 and PWD3.
11. Both nonvolatile and volatile protection bit settings are as follows: Protected state = 00;
Unprotected state= 01.
12. The CLEAR ALL NONVOLATILE PROTECTION BITS command programs all nonvolatile protection bits before erasure. This prevents over-erasure of previously cleared nonvolatile
protection bits.
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512Mb: 3V Embedded Parallel NOR Flash
PROTECTION Operations
PROTECTION Operations
Blocks can be protected individually against accidental PROGRAM, ERASE, or READ operations In both 8-bit and 16-bit configurations. The block protection scheme is shown
in the Software Protection Scheme figure.
Memory block and extended memory block protection is configured through the lock
register (see Lock Register).
Each die has its own block protection scheme and its own lock register. When setting
the block protection scheme, the same scheme must be used for both the upper die and
the lower die.
LOCK REGISTER Commands
After the ENTER LOCK REGISTER COMMAND SET (40h) command has been issued, all
bus READ or PROGRAM operations can be issued to the lock register.
The PROGRAM LOCK REGISTER (A0h) command allows the lock register to be configured. The programmed data can then be checked with a READ LOCK REGISTER command by driving CE# and OE# LOW with the appropriate address data on the address
bus.
PASSWORD PROTECTION Commands
After the ENTER PASSWORD PROTECTION COMMAND SET (60h) command has been
issued, the commands related to password protection mode can be issued to the device.
The PROGRAM PASSWORD (A0h) command is used to program the 64-bit password
used in the password protection mode. To program the 64-bit password, the complete
command sequence must be entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1 in 8-bit mode, or four times at four consecutive addresses
selected by A[1:0] in 16-bit mode. By default, all password bits are set to 1. The password
can be checked by issuing a READ PASSWORD command.
Important Note: To use the password protection feature on the this device, the same 64bit password must be programmed to both the upper die and the lower die.
The READ PASSWORD command is used to verify the password used in password protection mode. To verify the 64-bit password, the complete command sequence must be
entered eight times at eight consecutive addresses selected by A[1:0] plus DQ15/A-1 in
8-bit mode, or four times at four consecutive addresses selected by A[1:0] in 16-bit
mode. If the password mode lock bit is programmed and the user attempts to read the
password, the device will output FFh onto the I/O data bus.
The UNLOCK PASSWORD (25/03h) command is used to clear the nonvolatile protection bit lock bit, allowing the nonvolatile protection bits to be modified. The UNLOCK
PASSWORD command must be issued, along with the correct password, and requires a
1μs delay between successive UNLOCK PASSWORD commands in order to prevent discovery of the password by trying all possible 64-bit combinations. If this delay does not
occur, the latest command will be ignored. Approximately 1μs is required for unlocking
the device after the valid 64-bit password has been provided.
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512Mb: 3V Embedded Parallel NOR Flash
PROTECTION Operations
NONVOLATILE PROTECTION Commands
After the ENTER NONVOLATILE PROTECTION COMMAND SET (C0h) command has
been issued, the commands related to nonvolatile protection mode can be issued to the
device.
A block can be protected from being programmed or erased by issuing a PROGRAM
NONVOLATILE PROTECTION BIT (A0h) command, along with the block address. This
command sets the nonvolatile protection bit to 0 for a given block.
The status of a nonvolatile protection bit for a given block or group of blocks can be
read by issuing a READ NONVOLATILE MODIFY PROTECTION BIT command, along
with the block address.
The nonvolatile protection bits of a single die are erased simultaneously by issuing a
CLEAR ALL NONVOLATILE PROTECTION BITS (80/30h) command. No specific block
address is required. If the nonvolatile protection bit lock bit is set to 0, the command
fails.
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512Mb: 3V Embedded Parallel NOR Flash
PROTECTION Operations
Figure 10: Program/Erase Nonvolatile Protection Bit Algorithm
Start
ENTER NONVOLATILE
PROTECTION
command set
PROGRAM NONVOLATILE
PROTECTION BIT
Addr = BAd
Read byte twice
Addr = BAd
DQ6 = Toggle
No
Yes
No
DQ5 = 1
Wait 500µs
Yes
Read byte twice
Addr = BAd
DQ6 = Toggle
No
Read byte twice
Addr = BAd
Yes
No
DQ0 =
1 (erase)
0 (program)
Yes
Fail
Reset
Pass
EXIT PROTECTION
command set
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512Mb: 3V Embedded Parallel NOR Flash
PROTECTION Operations
NONVOLATILE PROTECTION BIT LOCK BIT Commands
After the ENTER NONVOLATILE PROTECTION BIT LOCK BIT COMMAND SET (50h)
command has been issued, the commands that allow the nonvolatile protection bit lock
bit to be set can be issued to the device.
The PROGRAM NONVOLATILE PROTECTION BIT LOCK BIT (A0h) command is used to
set the nonvolatile protection bit lock bit to 0, thus locking the nonvolatile protection
bits and preventing them from being modified.
The READ NONVOLATILE PROTECTION BIT LOCK BIT STATUS command is used to
read the status of the nonvolatile protection bit lock bit.
The nonvolatile protection bit lock bit (NVPB lock bit) is a global volatile bit for all
blocks in a die. There are two NVPB lock bits: one per die.
VOLATILE PROTECTION Commands
After the ENTER VOLATILE PROTECTION COMMAND SET (E0h) command has been
issued, commands related to the volatile protection mode can be issued to the device.
The PROGRAM VOLATILE PROTECTION BIT (A0h) command individually sets a volatile protection bit to 0 for a given block. If the nonvolatile protection bit is set for the
same block, the block is locked regardless of the value of the volatile protection bit. (See
the Block Protection Status table.)
The status of a volatile protection bit for a given block can be read by issuing a READ
VOLATILE PROTECTION BIT STATUS command, along with the block address.
The CLEAR VOLATILE PROTECTION BIT (A0h) command individually clears (sets to 1)
the volatile protection bit for a given block. If the nonvolatile protection bit is set for the
same block, the block is locked regardless of the value of the volatile protection bit. (See
the Block Protection Status table.)
EXTENDED MEMORY BLOCK Commands
The device has two extra 128-word extended memory blocks that can be accessed only
by the ENTER EXTENDED MEMORY BLOCK (88h) command. Each extended memory
block is 128 words (x16) or 256 bytes (x8). It is used as a security block to provide a permanent 128-bit security identification number or to store additional information. The
device can be shipped with the extended memory blocks prelocked permanently by Micron, including the 128-bit security identification number. Or, the device can be shipped with the extended memory blocks unlocked, enabling customers to permanently
program and lock them. (See Lock Register, the AUTO SELECT command, and the Block
Protection table.)
Table 14: Extended Memory Blocks and Data
Address
Data
Die
x8
x16
Micron Prelocked
Customer Lockable
Lower Die
0000000-00000FFh
0000000h-000007Fh
Secure ID number
Determined by customer
Upper Die
2000000-20000FFh
1000000h-100007Fh
Data
Determined by customer
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512Mb: 3V Embedded Parallel NOR Flash
PROTECTION Operations
After the ENTER EXTENDED MEMORY BLOCK command has been issued, the device
enters the extended memory block mode. All bus READ or PROGRAM operations are
conducted on the extended memory blocks, and the extended memory blocks are addressed using the addresses occupied by block 0 and block 256 in the other operating
modes (see the Memory Map table).
In extended memory block mode, ERASE, DIE ERASE, ERASE SUSPEND, and ERASE
RESUME commands are not allowed. The extended memory blocks cannot be erased,
and each bit of the extended memory blocks can only be programmed once.
The extended memory blocks are protected from further modification by programming
lock register bit 0. Once invoked, this protection cannot be undone.
The device remains in extended memory block mode until the EXIT EXTENDED MEMORY BLOCK (90/00h) command is issued, which returns the device to read mode, or
until power is removed from the device. After a power-up sequence or hardware reset,
the device reverts to reading memory blocks in the main array.
EXIT PROTECTION Command
The EXIT PROTECTION COMMAND SET (90/00h) command is used to exit the lock
register, password protection, nonvolatile protection, volatile protection, and nonvolatile protection bit lock bit command set modes, and return the device to read mode.
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512Mb: 3V Embedded Parallel NOR Flash
Device Protection
Device Protection
Hardware Protection
The V PP/WP# function provides a hardware method of protecting the highest and the
lowest blocks (block 511 and block 0). When V PP/WP# is LOW, PROGRAM and ERASE
operations on these blocks are ignored to provide protection. When V PP/WP# is HIGH,
the device reverts to the previous protection status for the highest and the lowest
blocks. PROGRAM and ERASE operations can modify the data in these blocks unless the
blocks are protected using block protection.
When V PP/WP# is increased to V PPH, the device automatically enters the unlock bypass
mode, and command execution time is faster. This must never be done from any mode
except read mode; otherwise the device might be left in an indeterminate state.
A 0.1μF capacitor should be connected between the V PP/WP# pin and the V SS ground
pin to decouple current surges from the power supply. The PCB track widths must be
sufficient to carry the currents required during unlock bypass program.
When V PP/WP# returns to HIGH or LOW, normal operation resumes. When operations
execute in unlock bypass mode, the device draws IPP from the pin to supply the programming circuits. Transitions from HIGH to V PPH and from V PPH to LOW must be slower than tVHVPP.
Note: Micron highly recommends driving V PP/WP# HIGH or LOW. If a system needs to
float the V PP/WP# pin without a pull-up or pull-down resistor and without a capacitor,
then an internal pull-up resistor is enabled.
Table 15: VPP/WP# Functions
VPP/WP# Settings
Function
VIL
Highest and lowest blocks are protected (block 511 and block 0).
VIH
Highest and lowest blocks are unprotected unless software protection is activated.
VPPH
Unlock bypass mode supplies the current necessary to speed up PROGRAM execution time.
Software Protection
The following software protection modes are available:
• Volatile protection
• Nonvolatile protection
• Password protection
The device is shipped with all blocks unprotected. On first use, the device defaults to
the nonvolatile protection mode, but can be activated in either the nonvolatile protection or password protection mode.
The desired protection mode is activated by setting either the nonvolatile protection
mode lock bit or the password protection mode lock bit of the lock register for each die
(see the Lock Register). Both bits are one-time-programmable and nonvolatile; therefore, after the protection mode has been activated, it cannot be changed and the device
is set permanently to operate in the selected protection mode. It is recommended that
the desired software protection mode be activated when first programming the device.
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512Mb: 3V Embedded Parallel NOR Flash
Device Protection
Each die has its own block protection scheme and its own lock register. When setting
the protection scheme, the same protection scheme must be selected for both the upper die and the lower die.
For the lowest and highest blocks, a higher level of block protection can be achieved by
locking the blocks using nonvolatile protection mode and holding V PP /WP# LOW.
Blocks with volatile protection and nonvolatile protection can coexist within the memory array. If the user attempts to program or erase a protected block, the device ignores
the command and returns to read mode.
The block protection status can be read by performing a read electronic signature or by
issuing an AUTO SELECT command (see the Block Protection table).
Refer to the Block Protection Status table and the Software Protection Scheme figure for
details on the block protection scheme. Refer to Protection Operations for a description
of the command sets.
Volatile Protection Mode
Volatile protection enables the software application to protect blocks against inadvertent change, and can be disabled when changes are needed. Volatile protection bits are
unique for each block, and can be individually modified. Volatile protection bits control
the protection scheme only for unprotected blocks whose nonvolatile protection bits
are set to 1. Issuing a PROGRAM VOLATILE PROTECTION BIT command or a CLEAR
VOLATILE PROTECTION BIT command sets to 0, or clears to 1, the volatile protection
bits and places the associated blocks in the protected (0) or unprotected (1) state, respectively. The volatile protection bit can be set or cleared as often as needed.
When the device is first shipped, or after a power-up or hardware reset, the volatile protection bits default to 1 (unprotected).
Nonvolatile Protection Mode
A nonvolatile protection bit is assigned to each block. Each of these bits can be set for
protection individually by issuing a PROGRAM NONVOLATILE PROTECTION BIT command. Also, each die has one global volatile bit called the nonvolatile protection bit lock
bit; it can be set to protect all nonvolatile protection bits of a die at once. This global bit
must be set to 0 only after all nonvolatile protection bits are configured to the desired
settings. When set to 0, the nonvolatile protection bit lock bit prevents changes to the
state of the nonvolatile protection bits. When cleared to 1, the nonvolatile protection
bits can be set and cleared using the PROGRAM NONVOLATILE PROTECTION BIT and
CLEAR ALL NONVOLATILE PROTECTION BITS commands, respectively.
No software command unlocks the nonvolatile protection bit lock bit, unless the device
is in password protection mode; in nonvolatile protection mode, the nonvolatile protection bit lock bit can be cleared only by taking the device through a hardware reset or
power-up sequence.
Nonvolatile protection bits of a die cannot be cleared individually; they must be cleared
all at once using a CLEAR ALL NONVOLATILE PROTECTION BITS command. They will
remain set through a hardware reset or a power-down/power-up sequence.
If one of the nonvolatile protection bits needs to be cleared (unprotected), additional
steps are required: First, the nonvolatile protection bit lock bit must be cleared to 1, using either a power-cycle or hardware reset. Then, the nonvolatile protection bits can be
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512Mb: 3V Embedded Parallel NOR Flash
Device Protection
changed to reflect the desired settings. Finally, the nonvolatile protection bit lock bit
must be set to 0 to lock the nonvolatile protection bits. The device will then operate normally.
To achieve the best protection, the PROGRAM NONVOLATILE PROTECTION LOCK BIT
command should be executed early in the boot code, and the boot code should be protected by holding V PP/WP# LOW.
Nonvolatile protection bits and volatile protection bits have the same function when
VPP/WP# is HIGH or when V PP/WP# is at the voltage for program acceleration (VPPH ).
Password Protection Mode
Important Note: There is no means to verify the password after password protection
mode is enabled. If the password is lost after enabling password protection mode, there
is no way to clear the nonvolatile protection bit lock bit.
Password protection mode provides a higher level of security than the nonvolatile protection mode by requiring a 64-bit password to unlock the nonvolatile protection bit
lock bit. In addition to this password requirement, the nonvolatile protection bit lock
bit is set to 0 after power-up and reset to maintain the device in password protection
mode.
Executing the UNLOCK PASSWORD command by entering the correct password clears
the nonvolatile protection bit lock bit, enabling the block nonvolatile protection bits to
be modified. If the password provided is incorrect, the nonvolatile protection bit lock
bit remains locked, and the state of the nonvolatile protection bits cannot be modified.
To place the device in password protection mode, the following two steps are required:
First, before activating the password protection mode, a 64-bit password must be set
and the setting must be verified. Password verification is allowed only before the password protection mode is activated. Next, password protection mode is activated by programming the password protection mode lock bit to 0. This operation is irreversible. After the bit is programmed, it cannot be erased, the device remains permanently in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. In addition, all commands to the address where the password is stored are
disabled.
Note: To use the password protection feature on this device, the same 64-bit password
must be programmed to both the upper die and the lower die.
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512Mb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Figure 11: Software Protection Scheme – Single Die
Volatile protection bit
1 = unprotected
0 = protected
(Default setting depends on the product order option)
Volatile
protection
Nonvolatile protection bit
1 = unprotected (default)
0 = protected
Nonvolatile
protection
Nonvolatile protection bit lock bit (volatile)
Array block
1 = unlocked (default, after power-up or hardware reset)
0 = locked
Nonvolatile protection
mode
Notes:
Password protection
mode
1. Volatile protection bits are programmed and cleared individually. Nonvolatile protection
bits are programmed individually and cleared collectively.
2. Once programmed to 0, the nonvolatile protection bit lock bit can be reset to 1 only by
taking the device through a power-up or hardware reset.
Common Flash Interface
The Common Flash Interface (CFI) is a JEDEC-approved, standardized data structure
that can be read from a Flash memory device. It allows a system's software to query the
device to determine various electrical and timing parameters, density information, and
functions supported by the memory. The system can interface easily with the device,
enabling the software to upgrade itself when necessary.
When the READ CFI command is issued, the device enters CFI query mode and the data
structure is read from CFI space. The following tables show the addresses (A-1, A[7:0])
used to retrieve the data. The query data is always presented on the lowest order data
outputs (DQ[7:0]), and the other data outputs (DQ[15:8]) are set to 0.
Table 16: Query Structure Overview
Note 1 applies to the entire table
Address
x16
x8
Subsection Name
Description
10h
20h
CFI query identification string
Command set ID and algorithm data offset
1Bh
36h
System interface information
Device timing and voltage information
27h
4Eh
Device geometry definition
Flash device layout
40h
80h
Primary algorithm-specific extended query table
Additional information specific to the primary algorithm (optional)
61h
C2h
Security code area
64-bit unique device number
Note:
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1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
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512Mb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 17: CFI Query Identification String
Note 1 applies to the entire table
Address
x16
x8
Data
Description
Value
10h
20h
0051h
Query unique ASCII string "QRY"
11h
22h
0052h
"R"
12h
24h
0059h
"Y"
13h
14h
26h
28h
0002h
0000h
Primary algorithm command set and control interface ID code 16-bit ID code defining a specific algorithm
15h
16h
2Ah
2Ch
0040h
0000h
Address for primary algorithm extended query table (see Primary AlgorithmSpecific Extended Query Table)
P = 40h
17h
18h
2Eh
30h
0000h
0000h
Alternate vendor command set and control interface ID code second vendorspecified algorithm supported
–
19h
1Ah
32h
34h
0000h
0000h
Address for alternate algorithm extended query table
–
Note:
1. Query data are always presented on the lowest order data outputs (DQ[7:0]). DQ[15:8]
are set to 0.
"Q"
–
Table 18: CFI Query System Interface Information
Address
x16
x8
Data
Description
1Bh
36h
0027h
VCC logic supply minimum program/erase voltage
Bits[7:4] BCD value in volts
Bits[3:0] BCD value in 100mV
2.7V
1Ch
38h
0036h
VCC logic supply maximum program/erase voltage
Bits[7:4] BCD value in volts
Bits[3:0] BCD value in 100mV
3.6V
1Dh
3Ah
00B5h
VPPH (programming) supply minimum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
11.5V
1Eh
3Ch
00C5h
VPPH (programming) supply maximum program/erase voltage
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
12.5V
1Fh
3Eh
0004h
Typical timeout for single byte/word program = 2nμs
16µs
20h
40h
0004h
Value
Typical timeout for maximum size buffer program =
21h
42h
0009h
Typical timeout per individual block erase =
22h
44h
0000h
Typical timeout for full chip erase = 2nms
23h
24h
25h
46h
48h
4Ah
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0004h
0004h
0003h
2nms
Maximum timeout for buffer program =
2n
0.5s
times typical
times typical
Maximum timeout per individual block erase =
54
16µs
–
Maximum timeout for byte/word program =
2n
2nμs
2n
Notes
times typical
1
200µs
200µs
2.3s
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512Mb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 18: CFI Query System Interface Information (Continued)
Address
x16
x8
26h
4Ch
Data
Description
0000h
Note:
Maximum timeout for chip erase =
2n
times typical
Value
Notes
–
1
1. M29W512GH does not support the CHIP ERASE command; however, the same functionality for erasing 256Mb is available through the DIE ERASE command.
Table 19: Device Geometry Definition
Address
x16
x8
Data
Description
Value
2n
27h
4Eh
001Ah
Device size =
in number of bytes
64MB
28h
29h
50h
52h
0002h
0000h
Flash device interface code description
2Ah
2Bh
54h
56h
0006h
0000h
Maximum number of bytes in multi-byte program or page =
2n
64
2Ch
58h
0001h
Number of erase block regions. It specifies the number of regions containing contiguous erase blocks of the same size.
1
2Dh
2Eh
5Ah
5Ch
00FFh
0001h
Erase block region 1 information
Number of identical-size erase blocks = 01FFh + 1
2Fh
30h
5Eh
60h
0000h
0002h
Erase block region 1 information
Block size in region 1 = 0200h × 256 bytes
31h
32h
33h
34h
62h
64h
66h
68h
0000h
0000h
0000h
0000h
Erase block region 2 information
0
35h
36h
37h
38h
6Ah
6Ch
6Eh
70h
0000h
0000h
0000h
0000h
Erase block region 3 information
0
39h
3Ah
3Bh
3Ch
72h
74h
76h
78h
0000h
0000h
0000h
0000h
Erase block region 4 information
0
x8, x16
asynchronous
512
128KB
Table 20: Primary Algorithm-Specific Extended Query Table
Address
x16
x8
Data
Description
40h
80h
0050h
41h
82h
0052h
Primary algorithm extended query table unique ASCII string
“PRI”
"R"
42h
84h
0049h
43h
86h
0031h
Major version number, ASCII
"1"
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Value
"P"
"I"
55
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512Mb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 20: Primary Algorithm-Specific Extended Query Table (Continued)
Address
x16
x8
Data
Description
44h
88h
0033h
Minor version number, ASCII
45h
8Ah
0010h
Address sensitive unlock (bits[1:0]):
00 = Required
01 = Not required
Silicon revision number (bits[7:2])
46h
8Ch
0002h
Erase suspend:
00 = Not supported
01 = Read only
02 = Read and write
2
47h
8Eh
0001h
Block protection:
00 = Not supported
x = Number of blocks per group
1
48h
90h
0000h
Temporary block unprotect:
00 = Not supported
01 = Supported
00
49h
92h
0008h
Block protect/unprotect
8
4Ah
94h
0000h
Simultaneous operations:
Not supported
–
4Bh
96h
0000h
Burst mode:
00 = Not supported
01 = Supported
00
4Ch
98h
0002h
Page mode:
00 = Not supported
02 = 8-word page
02
4Dh
9Ah
00B5h
VPPH supply minimum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
11.5V
4Eh
9Ch
00C5h
VPPH supply maximum program/erase voltage:
Bits[7:4] hex value in volts
Bits[3:0] BCD value in 100mV
12.5V
4Fh
9Eh
00xxh
Top/bottom boot block flag:
xx = 07h: M29W512GH, first and last blocks protected by
VPP/WP#
50h
A0h
0001h
Program suspend:
00 = Not supported
01 = Supported
CCMTD-1725822587-9451
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Value
"3"
Yes
65nm
Uniform + VPP/WP#
protecting the highest
and lowest blocks
01
56
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512Mb: 3V Embedded Parallel NOR Flash
Common Flash Interface
Table 21: Security Code Area
Address
x16
x8
Data
Description
61h
C3h, C2h
XXXX
64-bit unique device number
62h
C5h, C4h
XXXX
63h
C7h, C6h
XXXX
64h
C9h, C8h
XXXX
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512Mb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Power-Up and Reset Characteristics
Table 22: Power-Up Wait Timing Specifications
Note 1 applies to the entire table
Symbol
Parameter
VCC HIGH to CE# LOW
VCCQ HIGH to CE# LOW
VCC HIGH to WE# LOW
VCCQ HIGH to WE# LOW
Notes:
Legacy
JEDEC
Min
Unit
Notes
tVCH
tVCHEL
70
µs
2, 3
–
tVCQHEL
70
µs
2, 3
–
tVCHWL
500
µs
–
tVCQHWL
500
µs
1. Specifications apply to 80ns and 90ns devices, unless otherwise noted.
2. VCC and VCCQ ramps must be synchronized during power-up.
3. If RST# is not stable for tVCS or tVIOS, the device will not allow any READ or WRITE operations, and a hardware reset is required.
Figure 12: Power-Up Timing
tVCHEL
VCC
VCCQ
tVCQHEL
CE#
WE#
tVCHWL
tVCQHWL
RST#
tRH
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512Mb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Table 23: Reset AC Specifications
Note 1 applies to the entire table
Symbol
Condition/Parameter
Legacy
JEDEC
Min
Max
Unit
Notes
RST# LOW to read mode during program or erase
tREADY
tPLRH
–
100
µs
2
RST# pulse width
tRP
tPLPH
20
–
µs
RST# HIGH to CE# LOW, OE# LOW
tRH
tPHEL,
55
–
ns
20
–
µs
55
–
µs
0
–
ns
2
tPHGL,
tPHWL
tRPD
RST# LOW to standby mode during read mode
–
RST# LOW to standby mode during program or erase
tRB
RY/BY# HIGH to CE# LOW, OE# LOW
tRHEL,
2
tRHGL,
tRHWL
Notes:
1. Specifications apply to 80ns and 90ns devices, unless otherwise noted.
2. Sampled only; not 100% tested.
Figure 13: Reset AC Timing – No PROGRAM/ERASE Operation in Progress
RY/BY#
CE#, OE#, WE#
tRH
RST#
tRP
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512Mb: 3V Embedded Parallel NOR Flash
Power-Up and Reset Characteristics
Figure 14: Reset AC Timing During PROGRAM/ERASE Operation
tREADY
RY/BY#
tRB
CE#, OE#, WE#
tRH
RST#
tRP
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512Mb: 3V Embedded Parallel NOR Flash
Absolute Ratings and Operating Conditions
Absolute Ratings and Operating Conditions
Stresses greater than those listed may cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 24: Absolute Maximum/Minimum Ratings
Parameter
Symbol
Min
Max
Unit
Temperature under bias
TBIAS
–50
125
°C
Storage temperature
TSTG
–65
150
°C
Input/output voltage
VIO
–0.6
VCC + 0.6
V
Supply voltage
VCC
–0.6
4
V
Input/output supply voltage
VCCQ
–0.6
4
V
VID
–0.6
13.5
V
VPPH
–0.6
13.5
V
Identification voltage
Program voltage
Notes:
Notes
1, 2
3
1. During signal transitions, minimum voltage may undershoot to −2V for periods less than
20ns.
2. During signal transitions, maximum voltage may overshoot to VCC + 2V for periods less
than 20ns.
3. VPPH must not remain at 12V for more than 80 hours cumulative.
Table 25: Operating Conditions
Note 1 applies to the entire table.
Parameter
Symbol
Min
Max
Unit
Supply voltage
VCC
2.7
3.6
V
Input/output supply voltage (VCCQ ≤ VCC)
VCCQ
1.65
3.6
V
Ambient operating temperature (range 3)
TA
–40
125
°C
Ambient operating temperature (range 6)
TA
–40
85
°C
Load capacitance
CL
Input rise and fall times
–
Input pulse voltages
–
0 to VCCQ
V
Input and output timing reference voltages
–
VCCQ/2
V
Notes:
CCMTD-1725822587-9451
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30
–
Notes
2
pF
10
ns
1. Specifications apply to 80ns and 90ns devices, unless otherwise noted.
2. For the 90ns device, input/output supply voltage (VCCQ ≤ VCC) = 1.65V (MIN) and 3.6V
(MAX). For the 80ns devices, input/output supply voltage (VCCQ ≤ VCC) = 2.7V (MIN) and
3.6V (MAX).
61
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512Mb: 3V Embedded Parallel NOR Flash
Absolute Ratings and Operating Conditions
Figure 15: AC Measurement Load Circuit
VCCQ
VCC
VPP
25kΩ
Device
under
test
CL
0.1µF
25kΩ
0.1µF
Note:
1. CL includes jig capacitance.
Figure 16: AC Measurement I/O Waveform
VCCQ
VCCQ/2
0V
Table 26: Input/Output Capacitance
Parameter
Input capacitance (256Mb/256Mb)
Output capacitance
Note:
CCMTD-1725822587-9451
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Symbol
Test Condition
Min
Max
Unit
CIN
VIN = 0V
–
16
pF
COUT
VOUT = 0V
–
12
pF
1. Sampled only, not 100% tested.
62
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512Mb: 3V Embedded Parallel NOR Flash
DC Characteristics
DC Characteristics
Table 27: DC Current Characteristics
Parameter
Input leakage current
Symbol
Conditions
Min
Typ
Max
Unit
Notes
ILI
0V ≤ VIN ≤ VCC
–
–
±1
µA
1
Output leakage current
ILO
0V ≤ VOUT ≤ VCC
–
–
±1
µA
VCC read
current
ICC1
CE# = VIL, OE# = VIH,
f = 6 MHz
–
–
10
mA
CE# = VIL, OE# = VIH,
f = 10 MHz
–
–
1
mA
CE# = VCCQ ±0.2V,
RST# = VCCQ ±0.2V
–
–
400
µA
VPP/WP# = VIL
or VIH
–
–
20
mA
VPP/WP# =
VPPH
–
–
15
mA
5
µA
Random read
Page read
VCC standby
current
Grade 3
ICC2
Grade 6
VCC program/erase current
VPP current
ICC3
Program/
erase
controller
active
200
IPP1
VPP/WP# ≤ VCC
–
1
–
1
5
µA
Reset
IPP2
RST# = VSS ±0.2V
–
1
5
µA
PROGRAM operation
ongoing
IPP3
VPP/WP# = 12V ±5%
–
1
10
mA
VPP/WP# = VCC
–
1
5
µA
ERASE operation
ongoing
IPP4
Read
Standby
Notes:
CCMTD-1725822587-9451
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VPP/WP# = 12V ±5%
–
3
10
mA
VPP/WP# = VCC
–
1
5
µA
2
1. The maximum input leakage current is ±5µA on the VPP/WP# pin.
2. Sampled only; not 100% tested.
63
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512Mb: 3V Embedded Parallel NOR Flash
DC Characteristics
Table 28: DC Voltage Characteristics
Parameter
Input LOW voltage
Symbol
Conditions
Min
Typ
Max
Unit
VIL
VCC ≥ 2.7V
–0.5
–
0.3VCCQ
V
Input HIGH voltage
VIH
VCC ≥ 2.7V
0.7VCCQ
–
VCCQ + 0.4
V
Output LOW voltage
VOL
IOL = 100µA,
VCC = VCC,min,
VCCQ = VCCQ,min
–
–
0.15VCCQ
V
Output HIGH voltage
VOH
IOH = 100µA,
VCC = VCC,min,
VCCQ = VCCQ,min
0.85VCCQ
–
–
V
Identification voltage
VID
–
11.5
–
12.5
V
Voltage for VPP/WP# program
acceleration
VPPH
–
11.5
–
12.5
V
Program/erase lockout supply
voltage
VLKO
–
1.8
–
2.5
V
Note:
CCMTD-1725822587-9451
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Notes
1
1. Sampled only; not 100% tested.
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512Mb: 3V Embedded Parallel NOR Flash
Read AC Characteristics
Read AC Characteristics
Table 29: Read AC Characteristics
Symbol
80ns
VCCQ = VCC
Parameter
90ns
VCCQ = 1.65V
to VCC
Legacy
JEDEC
Condition
Min
Max
Min
Max
Unit
Address valid to next address
valid
tRC
tAVAV
CE# = VIL,
OE# = VIL
80
–
90
–
ns
Address valid to output valid
tACC
tAVQV
CE# = VIL,
OE# = VIL
–
80
–
90
ns
Address valid to output valid
(page)
tPAGE
tAVQV1
CE# = VIL,
OE# = VIL
–
25
–
30
ns
CE# LOW to output transition
tLZ
tELQX
OE# = VIL
0
–
0
–
ns
tE
tELQV
OE# = VIL
–
80
–
90
ns
tOLZ
tGLQX
CE# = VIL
0
–
0
–
ns
OE# LOW to output valid
tOE
tGLQV
CE# = VIL
–
25
–
30
ns
CE# HIGH to output High-Z
tHZ
tEHQZ
OE# = VIL
–
25
–
30
ns
1
OE# HIGH to output High-Z
tDF
tGHQZ
CE# = VIL
–
25
–
30
ns
1
CE#, OE#, or address transition
to output transition
tOH
tEHQX,
–
0
–
0
–
ns
CE# LOW to output valid
OE# LOW to output transition
Notes
1
1
tGHQX,
tAXQX
tEHQV
CE# to BYTE# LOW
tELFL
tELBL
–
–
5
–
5
ns
CE# to BYTE# HIGH
tELFH
tELBH
–
–
5
–
5
ns
tELQZ
BYTE# LOW to output High-Z
tFLQZ
tBLQZ
–
–
25
–
30
ns
BYTE# HIGH to output valid
tFHQV
tBHQV
–
–
30
–
30
ns
Note:
CCMTD-1725822587-9451
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1. Sampled only; not 100% tested.
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512Mb: 3V Embedded Parallel NOR Flash
Read AC Characteristics
Figure 17: Random Read AC Timing (8-Bit Mode)
tRC
A[MAX:0]/A-1
Valid
tACC
tOH
CE#
tCE
tOH
tLZ
tHZ
OE#
tOLZ
tOH
tOE
tDF
DQ[7:0]
Valid
BYTE#
tELFL
Note:
1. BYTE# = VIL
Figure 18: Random Read AC Timing (16-Bit Mode)
tRC
A[MAX:0]
Valid
tACC
tOH
CE#
tE
tOH
tLZ
tHZ
OE#
tOLZ
tOH
tOE
tDF
DQ[14:0]
DQ15A-1
Valid
BYTE#
tELFH
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512Mb: 3V Embedded Parallel NOR Flash
Read AC Characteristics
Figure 19: Page Read AC Timing (16-Bit Mode)
A[MAX:3]
A[2:0]
Valid
Valid
Valid
Valid
Valid
Valid
Valid
Valid
tACC
CE#
tE
tOH
tHZ
OE#
tPAGE
tOE
tOH
tDF
DQ[15:0]
DQ15A-1
Valid
Note:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
Valid
Valid
Valid
Valid
Valid
Valid
1. Page size is 8 words (16 bytes) and is addressed by address inputs A[2:0] in x16 bus mode
and A[2:0] plus DQ15/A-1 in x8 bus mode.
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Write AC Characteristics
Table 30: WE#-Controlled Write AC Characteristics
Parameter
80ns
VCCQ = VCC
Symbol
90ns
VCCQ = 1.65V to
VCC
Unit
Legacy
JEDEC
Min
Max
Min
Max
tWC
tAVAV
80
–
90
–
ns
CE# LOW to WE# LOW
tCS
tELWL
0
–
0
–
ns
WE# LOW to WE# HIGH
tWP
tWLWH
35
–
35
–
ns
Input valid to WE# HIGH
tDS
tDVWH
45
–
45
–
ns
WE# HIGH to input transition
tDH
tWHDX
0
–
0
–
ns
WE# HIGH to CE# HIGH
tCH
tWHEH
0
–
0
–
ns
WE# HIGH to WE# LOW
tWPH
tWHWL
30
–
30
–
ns
Address valid to WE# LOW
tAS
tAVWL
0
–
0
–
ns
WE# LOW to address transition
tAH
tWLAX
45
–
45
–
ns
OE# HIGH to WE# LOW
–
tGHWL
0
–
0
–
ns
WE# HIGH to OE# LOW
tOEH
tWHGL
0
–
0
–
ns
Program/erase valid to RY/BY#
LOW
tBUSY
tWHRL
–
30
–
30
ns
tVCS
tVCHEL
50
–
50
–
µs
Address valid to next address valid
VCC HIGH to CE# LOW
Notes:
CCMTD-1725822587-9451
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Notes
1
2
1. The user's write timing must comply with this specification. Any violation of this write
timing specification may result in permanent damage to the NOR Flash device.
2. Sampled only; not 100% tested.
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Figure 20: WE#-Controlled Program AC Timing (8-Bit Mode)
3rd Cycle
4th Cycle
Data Polling
tWC
A[MAX:0]/A-1
READ Cycle
tWC
AAAh
PA
PA
tAH
tAS
tCH
tCS
tCE
CE#
tOE
tGHWL
OE#
tWPH
tWP
WE#
tWHWH1
tDS
DQ[7:0]
A0h
PD
DQ7#
tDF
DOUT
tOH
DOUT
tDH
Notes:
CCMTD-1725822587-9451
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1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit and by a
READ operation that outputs the data (DOUT) programmed by the previous PROGRAM
command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Figure 21: WE#-Controlled Program AC Timing (16-Bit Mode)
3rd Cycle
4th Cycle
Data Polling
READ Cycle
tWC
tWC
A[MAX:0]
555h
PA
PA
tAS
tAH
tCH
tCS
tE
CE#
tGHWL
tOE
OE#
tWP
tWPH
WE#
tWHWH1
tDS
DQ[14:0]/A-1
AOh
PD
DQ7#
tDF
DOUT
tOH
DOUT
tDH
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit and by a
READ operation that outputs the data (DOUT) programmed by the previous PROGRAM
command.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
70
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Table 31: CE#-Controlled Write AC Characteristics
Parameter
80ns
VCCQ = VCC
Symbol
90ns
VCCQ = 1.65V to
VCC
Unit
Legacy
JEDEC
Min
Max
Min
Max
Address valid to next address valid
tWC
tAVAV
80
–
90
–
ns
WE# LOW to CE# LOW
tWS
tWLEL
0
–
0
–
ns
CE# LOW to CE# HIGH
tCP
tELEH
35
–
35
–
ns
Input valid to CE# HIGH
tDS
tDVEH
45
–
45
–
ns
CE# HIGH to input transition
tDH
tEHDX
0
–
0
–
ns
CE# HIGH to WE# HIGH
tWH
tEHWH
0
–
0
–
ns
CE# HIGH to CE# LOW
tCPH
tEHEL
30
–
30
–
ns
Address valid to CE# LOW
tAS
tAVEL
0
–
0
–
ns
CE# LOW to address transition
tAH
tELAX
45
–
45
–
ns
–
tGHEL
0
–
0
–
ns
OE# HIGH to CE# LOW
Note:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
Notes
1
1. The user's write timing must comply with this specification. Any violation of this write
timing specification may result in permanent damage to the NOR Flash device.
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Figure 22: CE#-Controlled Program AC Timing (8-Bit Mode)
3rd Cycle
4th Cycle
Data Polling
AAAh
PA
PA
tWC
A[MAX:0]/A-1
tAS
tAH
tWH
tWS
WE#
tGHEL
OE#
tCP
tCPH
CE#
tWHWH1
tDS
DQ[7:0]
A0h
PD
DQ7#
DOUT
tDH
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
72
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Figure 23: CE#-Controlled Program AC Timing (16-Bit Mode)
3rd Cycle
4th Cycle
Data Polling
555h
PA
PA
tWC
A[MAX:0]
tAH
tAS
tWH
tWS
WE#
tGHEL
OE#
tCPH
tCP
CE#
tWHWH1
tDS
DQ[14:0]/A-1
AOh
PD
DQ7#
DOUT
tDH
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. Only the third and fourth cycles of the PROGRAM command are represented. The PROGRAM command is followed by checking of the status register data polling bit.
2. PA is the address of the memory location to be programmed. PD is the data to be programmed.
3. DQ7 is the complement of the data bit being programmed to DQ7 (See Data Polling Bit
[DQ7]).
4. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
73
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512Mb: 3V Embedded Parallel NOR Flash
Write AC Characteristics
Figure 24: Die/Block Erase AC Timing (8-Bit Mode)
tWC
A[MAX:0]/
A–1
AAAh
555h
tAS
AAAh
AAAh
AAAh
BAh1
555h
tAH
tCH
tCS
CE#
tGHWL
OE#
tWP
tWPH
WE#
tDS
DQ[7:0]
AAh
55h
80h
AAh
55h
10h/
30h
tDH
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. For a DIE ERASE command, the address is AAAh, and the data is 10h; for a BLOCK ERASE
command, the address is BAd, and the data is 30h.
2. BAd is the block address.
3. See the following tables for timing details: Read AC Characteristics, WE#-Controlled
Write AC Characteristics, and CE#-Controlled Write AC Characteristics.
74
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512Mb: 3V Embedded Parallel NOR Flash
Accelerated Program, Data Polling/Toggle AC Characteristics
Accelerated Program, Data Polling/Toggle AC Characteristics
Table 32: Accelerated Program and Data Polling/Data Toggle AC Characteristics
Note 1 and 2 apply to the entire table.
Symbol
Parameter
Legacy
JEDEC
Min
Max
Unit
–
tVHVPP
250
–
ns
Address setup time to OE# LOW during toggle bit polling
tASO
tAXGL
10
–
ns
Address hold time from OE# during toggle bit polling
tAHT
tGHAX, tEHAX
10
–
ns
CE# HIGH during toggle bit polling
tEPH
tEHEL2
10
–
ns
Output hold time during data and toggle bit polling
tOEH
tWHGL2,
20
–
ns
Program/erase valid to RY/BY# LOW
tBUSY
–
30
ns
VPP/WP# rising or falling time
tGHGL2
Notes:
tWHRL
1. Specifications apply to 80ns and 90ns devices, unless otherwise noted.
2. Sampled only; not 100% tested.
Figure 25: Accelerated Program AC Timing
VPP/WP#
VPPH
VIL or VIH
tVHVPP
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
75
tVHVPP
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512Mb: 3V Embedded Parallel NOR Flash
Accelerated Program, Data Polling/Toggle AC Characteristics
Figure 26: Data Polling AC Timing
tCE
tCH
tHZ/tDF
CE#
tOPH
tOE
OE#
tOEH
WE#
DQ7
Data
DQ7#
DQ7#
Valid DQ7
Data
DQ[6:0]
Data
Output flag
Output flag
Valid
DQ[6:0] Data
tBUSY
RY/BY#
Notes:
1. DQ7 returns a valid data bit when the PROGRAM or ERASE command has completed.
2. See the following tables for timing details: Read AC Characteristics, Accelerated Program and Data Polling/Data Toggle AC Characteristics.
Figure 27: Toggle/Alternative Toggle Bit Polling AC Timing (8-Bit Mode)
A[MAX:0]/
A–1
tAHT
tASO
CE#
tOEH
tASO
tAHT
WE#
tOPH
tEPH
tOPH
OE#
tDH
DQ6/DQ2
tCE
tOE
Data
Toggle
Toggle
Toggle
Stop
toggling
Output
Valid
tBUSY
RY/BY#
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. DQ6 stops toggling when the PROGRAM or ERASE command has completed. DQ2 stops
toggling when the DIE ERASE or BLOCK ERASE command has completed.
2. See the following tables for timing details: Read AC Characteristics, Accelerated Program and Data Polling/Data Toggle AC Characteristics.
76
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512Mb: 3V Embedded Parallel NOR Flash
Program/Erase Characteristics
Program/Erase Characteristics
Table 33: Program/Erase Characteristics
Notes 1, 2, and 7 apply to the entire table
Parameter
Min
Typ
Max
–
145
–
125
Block erase (128KB)
–
Erase suspend latency time
–
Die erase
Die erase
VPP/WP# =
VPPH
Block erase timeout
Byte program
Word program
Notes
400
s
3, 4
400
s
4
0.5
2
s
4, 5
25
45
µs
50
–
–
µs
–
16
200
µs
4
VPP/WP# =
VPPH
–
50
200
µs
4
VPP/WP# =
VIH
–
70
200
µs
4
Single-byte program
Write to buffer program
(64 bytes at a time)
Unit
Single-word program
–
16
200
µs
4
VPP/WP# =
VPPH
–
50
200
µs
4
VPP/WP# =
VIH
–
70
200
µs
4
Die program (byte by byte)
–
540
800
s
4
Die program (word by word)
–
270
400
s
4
Die program (write to buffer program)
–
25
200
s
4, 6
Die program (write to buffer program with VPP/WP# = VPPH)
–
13
50
s
4, 6
Die program (enhanced buffered program)
–
15
60
s
6
Die program (enhanced buffered program with VPP/WP# = VPPH)
–
10
40
s
6
Program suspend latency time
–
5
15
µs
100,000
–
–
cycles
20
–
–
years
Write to buffer program
(32 words at a time)
PROGRAM/ERASE cycles (per block)
Data retention
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. Typical values measured at room temperature and nominal voltages, and for devices not
cycled.
2. Typical and maximum values are sampled; not 100% tested.
3. Time needed to program the whole array at 0 is included.
4. Maximum value measured at worst case conditions for both temperature and VCC after
100,000 PROGRAM/ERASE cycles.
5. Block erase polling cycle time (see Data polling AC Timing figure).
6. Intrinsic program timing, that means without the time required to execute the bus
cycles to load the PROGRAM commands.
7. Values are referenced to each single die of the device.
77
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512Mb: 3V Embedded Parallel NOR Flash
Package Dimensions
Package Dimensions
Figure 28: 56-Pin TSOP – 14mm x 20mm
1.1 ±0.1
Pin A1 ID
1
56
0.5 TYP
56X 0.22 ±0.05
28
14 ±0.1
29
18.4 ±0.1
56X 0.1 ±0.05
20 ±0.2
Plating material composition: Ni/Pd/Au.
Plastic package material: epoxy novolac.
Package width and length include mold flash.
0.1 A
0.15 ±0.05
See Detail A
0.25 gage plane
Seating plane
(0.1 ±0.05)
A
0.6 ±0.1
Detail A
Notes:
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
1. All dimensions are in millimeters.
2. For the lead width value of 0.22 ±0.05, there is also a legacy value of 0.15 ±0.05.
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512Mb: 3V Embedded Parallel NOR Flash
Revision History
Revision History
Rev. F – 5/18
• Added Important Notes and Warnings section for further clarification aligning to industry standards
Rev. E – 9/15
• Updated Package Dimensions
Rev. D – 6/15
• Preliminary to production
Rev. C – 6/14
• Changed tPLRH from 55 to 100 in the Reset AC Specifications table
Rev. B – 2/14
• Added information for automotive grade 3 device
• Updated tables: Part Number Information, Power-Up Wait Timing Specifications, Operating Conditions, DC Current Characteristics, Read AC Characteristics, WE#-Controlled Write AC Characteristics, and Accelerated Program and Data Polling/Data Toggle AC Characteristics
• Updated figure: Power-Up Timing
Rev. A – 4/13
• Initial release
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000
www.micron.com/products/support Sales inquiries: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
CCMTD-1725822587-9451
m29w_512mb.pdf - Rev. F 5/18 EN
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