M58LR256KT70ZQ5E

M58LR128KT M58LR128KB M58LR256KT M58LR256KB 128 or 256 Mbit (x16, multiple bank, multilevel interface, burst) 1.8 V supply flash memories Features „ Supply voltage – VDD = 1.7 V to 2.0 V for program, erase and read – VDDQ = 1.7 V to 2.0 V for I/O buffers – VPP = 9 V for fast program FBGA „ Synchronous/asynchronous read – Synchronous burst read mode: 54 MHz, 66 MHz – Asynchronous page read mode – Random access: 70 ns, 85 ns VFBGA56 (ZB) 7.7 x 9 mm VFBGA79 (ZC) 9 x 11 mm TFBGA88 (ZQ) 8 x 10 mm „ Synchronous burst read suspend „ Programming time – 2.5 μs typical word program time using Buffer Enhanced Factory Program command „ Memory organization – Multiple bank memory array: 8 Mbit banks for the M58LR128KT/B 16 Mbit banks for the M58LR256KT/B – Parameter blocks (top or bottom location) „ Dual operations – Program/erase in one bank while read in others – No delay between read and write operations „ Block locking – All blocks locked at power-up – Any combination of blocks can be locked with zero latency – WP for block lock-down – Absolute write protection with VPP = VSS October 2008 „ Security – 64 bit unique device number – 2112 bit user programmable OTP cells „ Common flash interface (CFI) „ 100,000 program/erase cycles per block „ Electronic signature – Manufacturer code: 20h – Top device codes: M58LR128KT: 88C4h M58LR256KT: 880Dh – Bottom device codes M58LR128KB: 88C5h M58LR256KB: 880Eh „ The M58LR128KT/B is available in the ECOPACK-compliant VFBGA56 package. „ The M58LR256KT/B is available in the ECOPACK-compliant VFBGA79 and TFBGA88 packages. Rev 6 1/120 www.numonyx.com 1 Contents M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 3 4 2/120 2.1 Address inputs (A0-Amax) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.2 Data inputs/outputs (DQ0-DQ15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.3 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.4 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.5 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.6 Write Protect (WP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.7 Reset (RP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.8 Latch Enable (L) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.9 Clock (K) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10 Wait (WAIT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.11 VDD supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.12 VDDQ supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.13 VPP program supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.14 VSS ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.15 VSSQ ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.1 Bus read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.2 Bus write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.3 Address Latch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.4 Output disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3.5 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.6 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.1 Read Array command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.2 Read Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.3 Read Electronic Signature command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.4 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 5 6 Contents 4.5 Clear Status Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.6 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.7 Blank Check command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 4.8 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.9 Buffer Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 4.10 Buffer Enhanced Factory Program command . . . . . . . . . . . . . . . . . . . . . 29 4.10.1 Setup phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10.2 Program and verify phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4.10.3 Exit phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.11 Program/Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 4.12 Program/Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.13 Protection Register Program command . . . . . . . . . . . . . . . . . . . . . . . . . . 32 4.14 Set Configuration Register command . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.15 Block Lock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 4.16 Block Unlock command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 4.17 Block Lock-Down command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.1 Program/Erase Controller status bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . 39 5.2 Erase suspend status bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.3 Erase/blank check status bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.4 Program status bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.5 VPP status bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.6 Program suspend status bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.7 Block protection status bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 5.8 Bank write/multiple word program status bit (SR0) . . . . . . . . . . . . . . . . . 41 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.1 Read select bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.2 X latency bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 6.3 Wait polarity bit (CR10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.4 Data output configuration bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.5 Wait configuration bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 6.6 Burst type bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 3/120 Contents 7 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 6.7 Valid Clock edge bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.8 Wrap burst bit (CR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 6.9 Burst length bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Read modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.1 Asynchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.2 Synchronous burst read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.2.1 7.3 Synchronous burst read suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Single synchronous read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 8 Dual operations and multiple bank architecture . . . . . . . . . . . . . . . . . 54 9 Block locking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.1 Reading block lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.2 Locked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.3 Unlocked state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 9.4 Lock-down state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 9.5 Locking operations during erase suspend . . . . . . . . . . . . . . . . . . . . . . . . 57 10 Program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 59 11 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 12 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 13 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 14 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Appendix A Block address tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Appendix B Common Flash interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 Appendix C Flowcharts and pseudocodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Appendix D Command interface state tables. . . . . . . . . . . . . . . . . . . . . . . . . . . 110 4/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 15 Contents Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 5/120 List of tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. Table 29. Table 30. Table 31. Table 32. Table 33. Table 34. Table 35. Table 36. Table 37. Table 38. Table 39. Table 40. Table 41. Table 42. Table 43. Table 44. Table 45. Table 46. Table 47. Table 48. 6/120 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 M58LR128KT/B bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M58LR256KT/B bank architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Command codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Standard commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Factory commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Electronic signature codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Protection Register locks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Status Register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 X latency settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Burst type definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Dual operations allowed in other banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Dual operations allowed in same bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Dual operation limitations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Lock status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Program/erase times and endurance cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 DC characteristics - currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 DC characteristics - voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Asynchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 Synchronous read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Reset and power-up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 VFBGA56 7.7 x 9 mm - 8 x 7 ball array, 0.75 mm pitch, package mechanical data. . . . . . 79 TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data . . . . . . 80 VFBGA79 9x11mm - 0.75 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . 81 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 M58LR128KT - Parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 M58LR128KT - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 M58LR128KT - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 M58LR256KT - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 M58LR256KT - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 M58LR256KT - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 M58LR128KB - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 M58LR128KB - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 M58LR128KB - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 M58LR256KB - parameter bank block addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 M58LR256KB - main bank base addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 M58LR256KB - block addresses in main banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 CFI query identification string . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 CFI query system interface information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 Device geometry definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 49. Table 50. Table 51. Table 52. Table 53. Table 54. Table 55. Table 56. Table 57. Table 58. Table 59. List of tables Primary algorithm-specific extended query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 Protection Register information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Burst read information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Bank and erase block region information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Bank and erase block region 1 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Bank and erase block region 2 information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 Command interface states - modify table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 Command interface states - modify table, next output state . . . . . . . . . . . . . . . . . . . . . . 113 Command interface states - lock table, next state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115 Command interface states - lock table, next output state . . . . . . . . . . . . . . . . . . . . . . . . 117 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 7/120 List of figures M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. 8/120 Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 VFBGA56 package connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . 13 TFBGA88 connections (top view through package) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 M58LR128KT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 M58LR256KT/B memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Protection Register memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 X latency and data output configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Wait configuration example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 AC measurement load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Asynchronous random access read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Asynchronous page read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Synchronous burst read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Single synchronous read AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Synchronous burst read suspend AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Clock input AC waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Reset and power-up AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 VFBGA56 7.7 x 9 mm - 8 x 7 active ball array, 0.75 mm pitch, bottom view package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, bottom view package outline . . . . 79 Drawing is not to scale.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 VFBGA79 9x11mm - 0.75 pitch -package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 Blank check flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Buffer program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Program suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . 104 Block erase flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 Erase suspend and resume flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Locking operations flowchart and pseudocode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Protection Register program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . . . . . 108 Buffer enhanced factory program flowchart and pseudocode . . . . . . . . . . . . . . . . . . . . . 109 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 1 Description Description The M58LR128KT/B and M58LR256KT/B are 128 Mbit (8 Mbit x16) and 256 Mbit (16 Mbit x 16) non-volatile Flash memories, respectively. They can be erased electrically at block level and programmed in-system on a word-by-word basis using a 1.7 V to 2.0 V VDD supply for the circuitry and a 1.7 V to 2.0 V VDDQ supply for the input/output pins. An optional 9 V VPP power supply is provided to accelerate factory programming. The devices feature an asymmetrical block architecture: z The M58LR128KT/B have an array of 131 blocks, and are divided into 8 Mbit banks. There are 15 banks each containing 8 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 7 main blocks of 64 Kwords. z The M58LR256KT/B have an array of 259 blocks, and are divided into 16 Mbit banks. There are 15 banks each containing 16 main blocks of 64 Kwords, and one parameter bank containing 4 parameter blocks of 16 Kwords and 15 main blocks of 64 Kwords. The multiple bank architecture allows dual operations. While programming or erasing in one bank, read operations are possible in other banks. Only one bank at a time is allowed to be in program or erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory map is shown in Figure 4. The parameter blocks are located at the top of the memory address space for the M58LR128KT and M58LR256KT, and at the bottom for the M58LR128KB and M58LR256KB. Each block can be erased separately. Erase can be suspended to perform a program or read operation in any other block, and then resumed. Program can be suspended to read data at any memory location except for the one being programmed, and then resumed. Each block can be programmed and erased over 100 000 cycles using the supply voltage VDD. There is a buffer enhanced factory programming command available to speed up programming. Program and erase commands are written to the command interface of the memory. An internal Program/Erase Controller manages the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst read mode, data is output on each clock cycle at frequencies of up to 66 MHz. The synchronous burst read operation can be suspended and resumed. The device features an automatic standby mode. When the bus is inactive during asynchronous read operations, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When VPP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at power-up. 9/120 Description M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB The device includes 17 Protection Registers and 2 Protection Register locks, one for the first Protection Register and the other for the 16 one-time-programmable (OTP) Protection Registers of 128 bits each. The first Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by Numonyx, and a 64 bit segment OTP by the user. The user programmable segment can be permanently protected. Figure 6, shows the Protection Register memory map. The M58LR128KT/B is offered in a VFBGA56 7.7 x 9 mm, 0.75 mm package, and the M58LR256KT/B is offered in a VFBGA79 9 x 11mm, 0.75 mm package and TFGBA88 8 x 10mm, 0.8 mm package. All devices are supplied with all the bits erased (set to ’1’). 10/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 1. Description Logic diagram VDD VDDQ VPP 16 A0-Amax(1) DQ0-DQ15 W E G RP WAIT M58LR128KT M58LR128KB M58LR256KT M58LR256KB WP L K VSS VSSQ AI14011 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 11/120 Description M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 1. Signal names Signal name Function A0-Amax(1) Address inputs Inputs DQ0-DQ15 Data input/outputs, command inputs I/O E Chip Enable Input G Output Enable Input W Write Enable Input RP Reset Input WP Write Protect Input K Clock Input L Latch Enable Input WAIT Wait Output VDD Supply voltage VDDQ Supply voltage for input/output buffers VPP Optional supply voltage for fast program & erase VSS Ground VSSQ Ground input/output supply 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 12/120 Direction M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 2. Description VFBGA56 package connections (top view through package) 1 2 3 4 5 6 7 8 A A11 A8 VSS VDD VPP A18 A6 A4 B A12 A9 A20 K RP A17 A5 A3 C A13 A10 A21 L W A19 A7 A2 D A15 A14 WAIT A16 DQ12 WP A22 A1 E VDDQ DQ15 DQ6 DQ4 DQ2 DQ1 E A0 F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 G G DQ7 VSSQ DQ5 VDD DQ3 VDDQ DQ8 VSSQ AI09814 1. This package is available only for the M58LR128KT/B devices. 13/120 Description Figure 3. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB TFBGA88 connections (top view through package) 1 2 3 4 5 A DU DU B A4 A18 A19 VSS VDD C A5 NC A23 VSS D A3 A17 NC E A2 A7 F A1 G 6 7 8 DU DU NC A21 A11 NC K A22 A12 VPP NC NC A9 A13 NC WP L A20 A10 A15 A6 NC RP W A8 A14 A16 A0 DQ8 DQ2 DQ10 DQ5 DQ13 WAIT NC H NC DQ0 DQ1 DQ3 DQ12 DQ14 DQ7 NC J NC G DQ9 DQ11 DQ4 DQ6 DQ15 VDDQ K E NC NC NC NC NC VDDQ NC L VSS VSS VDDQ VDD VSS VSS VSS VSS M DU DU DU DU AI08497 14/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 1: Description 7x9 Active-Ball Matrix for 256-Mbit Density in VF BGA Package 9 10 11 12 13 13 12 A18 A6 A4 RFU DU DU DU DU RFU RST# A17 A5 A3 RFU DU DU DU DU ADV# WE# A19 A7 A2 WAIT A16 D12 WP# A22 D15 D6 D4 D2 D1 1 2 3 4 5 6 7 DU DU A11 A8 VSS VCC VPP DU DU A12 A9 A20 CLK A13 A10 A21 A15 A14 VCCQ 8 11 10 9 8 7 6 5 4 3 2 1 A4 A6 A18 VPP VCC VSS A8 A11 DU DU RFU A3 A5 A17 RST# CLK A20 A9 A12 DU DU RFU A25 A2 A7 A19 WE# ADV# A21 A10 A13 A1 RFU A24 A1 A22 WP# D12 A16 WAIT A14 A15 CE# A0 A23 A23 A0 CE# D1 D2 D4 D6 D15 VCCQ D9 D10 D11 D13 D14 VSS DU DU D3 VCC D5 VSSQ D7 DU DU A A B B C C D D E E F F DU DU VSS D14 D13 D11 D10 D9 D0 OE# RFU DU DU DU DU RFU OE# D0 DU DU D7 VSSQ D5 VCC D3 VCCQ D8 VSSQ RFU DU DU DU DU RFU VSSQ D8 G G Ball Side Down - Top View VCCQ Bottom View - Ball Side Up 15/120 Description Table 2. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB M58LR128KT/B bank architecture Parameter Bank 8 Mbits 4 blocks of 16 Kwords 7 blocks of 64 Kwords Bank 1 8 Mbits - 8 blocks of 64 Kwords Bank 2 8 Mbits - 8 blocks of 64 Kwords Bank 3 8 Mbits - 8 blocks of 64 Kwords ---- Main blocks ---- Parameter blocks ---- Bank size ---- Number Bank 14 8 Mbits - 8 blocks of 64 Kwords Bank 15 8 Mbits - 8 blocks of 64 Kwords Figure 4. M58LR128KT/B memory map M58LR128KB - Bottom Boot Block Address lines A0-A22 M58LR128KT - Top Boot Block Address lines A0-A22 000000h 00FFFFh 64 Kword 070000h 07FFFFh 64 Kword Bank 15 600000h 60FFFFh 8 Main Blocks Parameter Bank 7E0000h 7EFFFFh 7F0000h 7F3FFFh 7FC000h 7FFFFFh 4 Parameter Blocks 16 Kword 64 Kword 7 Main Blocks 64 Kword 64 Kword 8 Main Blocks 64 Kword 64 Kword 8 Main Blocks Bank 2 170000h 17FFFFh 180000h 18FFFFh 64 Kword Bank 1 770000h 77FFFFh 780000h 78FFFFh 0F0000h 0FFFFFh 100000h 10FFFFh 64 Kword 8 Main Blocks 16 Kword Bank 1 64 Kword 8 Main Blocks 00C000h 00FFFFh 010000h 01FFFFh 070000h 07FFFFh 080000h 08FFFFh 64 Kword Bank 2 6F0000h 6FFFFFh 700000h 70FFFFh Parameter Bank 64 Kword Bank 3 670000h 67FFFFh 680000h 68FFFFh 000000h 003FFFh 8 Main Blocks 64 Kword 64 Kword 8 Main Blocks Bank 3 64 Kword 1F0000h 1FFFFFh 64 Kword 780000h 78FFFFh 64 Kword 7F0000h 7FFFFFh 64 Kword 64 Kword 7 Main Blocks 64 Kword 16 Kword 4 Parameter Blocks Bank 15 16 Kword 8 Main Blocks AI14012 16/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 3. Description M58LR256KT/B bank architecture Parameter bank 16 Mbits 4 blocks of 16 Kwords 15 blocks of 64 Kwords Bank 1 16 Mbits - 16 blocks of 64 Kwords Bank 2 16 Mbits - 16 blocks of 64 Kwords Bank 3 16 Mbits - 16 blocks of 64 Kwords ---- Main blocks ---- Parameter blocks ---- Bank size ---- Number Bank 14 16 Mbits - 16 blocks of 64 Kwords Bank 15 16 Mbits - 16 blocks of 64 Kwords Figure 5. M58LR256KT/B memory map M58LR256KB - Bottom Boot Block Address lines A23-A0 M58LR256KT - Top Boot Block Address lines A23-A0 000000h 00FFFFh 64 Kword 0F0000h 0FFFFFh 64 Kword Bank 15 C00000h C0FFFFh 16 Main Blocks EF0000h EFFFFFh F00000h F0FFFFh Parameter Bank FE0000h FEFFFFh FF0000h FF3FFFh FFC000h FFFFFFh 1F0000h 1FFFFFh 200000h 20FFFFh 2F0000h 2FFFFFh 300000h 30FFFFh 64 Kword 16 Main Blocks 4 Parameter Blocks 16 Kword 64 Kword 15 Main Blocks 64 Kword 64 Kword 16 Main Blocks 64 Kword 64 Kword 16 Main Blocks Bank 2 64 Kword Bank 1 16 Kword Bank 1 64 Kword 16 Main Blocks 00C000h 00FFFFh 010000h 01FFFFh 0F0000h 0FFFFFh 100000h 10FFFFh 64 Kword Bank 2 DF0000h DFFFFFh E00000h E0FFFFh Parameter Bank 64 Kword Bank 3 CF0000h CFFFFFh D00000h D0FFFFh 000000h 003FFFh 16 Main Blocks 64 Kword 64 Kword 16 Main Blocks Bank 3 64 Kword 3F0000h 3FFFFFh 64 Kword F00000h F0FFFFh 64 Kword FF0000h FFFFFFh 64 Kword 64 Kword 15 Main Blocks 64 Kword 16 Kword 4 Parameter Blocks 16 Kword 16 Main Blocks Bank 15 AI14013 17/120 Signal descriptions 2 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Signal descriptions See Figure 1: Logic diagram and Table 1: Signal names for a brief overview of the signals connected to this device. 2.1 Address inputs (A0-Amax) Amax is the highest order address input. It is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. The address inputs select the cells in the memory array to access during bus read operations. During bus write operations they control the commands sent to the command interface of the Program/Erase Controller. 2.2 Data inputs/outputs (DQ0-DQ15) The data I/O output the data stored at the selected address during a bus read operation or input a command or the data to be programmed during a bus write operation. 2.3 Chip Enable (E) The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the standby level. 2.4 Output Enable (G) The Output Enable input controls data outputs during the bus read operation of the memory. 2.5 Write Enable (W) The Write Enable input controls the bus write operation of the memory’s command interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable, whichever occurs first. 2.6 Write Protect (WP) Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the lock-down is enabled and the protection status of the lockeddown blocks cannot be changed. When Write Protect is at VIH, the lock-down is disabled and the locked-down blocks can be locked or unlocked. (refer to Table 17: Lock status). 18/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 2.7 Signal descriptions Reset (RP) The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset supply current IDD2. Refer to Table 22: DC characteristics - currents for the value of IDD2. After Reset all blocks are in the locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, and a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. 2.8 Latch Enable (L) Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at VIL and it is inhibited when Latch Enable is at VIH. 2.9 Clock (K) The Clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is ignored during asynchronous read and in write operations. 2.10 Wait (WAIT) Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH, Output Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. 2.11 VDD supply voltage VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (read, program and erase). 2.12 VDDQ supply voltage VDDQ provides the power supply to the I/O pins and enables all outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. 19/120 Signal descriptions 2.13 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB VPP program supply voltage VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If VPP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK provides absolute protection against program or erase, while VPP in the VPP1 range enables these functions (see Tables 22 and 23, DC characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase. A change in its value after the operation has started does not have any effect and program or erase operations continue. If VPP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the program/erase algorithm is completed. 2.14 VSS ground VSS ground is the reference for the core supply. It must be connected to the system ground. 2.15 VSSQ ground VSSQ ground is the reference for the input/output circuitry driven by VDDQ. VSSQ must be connected to VSS Note: 20/120 Each device in a system should have VDD, VDDQ and VPP decoupled with a 0.1 µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the package). See Figure 10: AC measurement load circuit. The PCB track widths should be sufficient to carry the required VPP program and erase currents. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 3 Bus operations Bus operations There are six standard bus operations that control the device. These are bus read, bus write, address latch, output disable, standby and reset. See Table 4: Bus operations for a summary. Typically glitches of less than 5 ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus write operations. 3.1 Bus read Bus read operations are used to output the contents of the memory array, the electronic signature, the Status Register and the Common Flash interface. Both Chip Enable and Output Enable must be at VIL to perform a read operation. The Chip Enable input should be used to enable the device, and Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see command interface section). See Figures 11, 12 and 13 read AC waveforms, and Tables 24 and 25 read AC characteristics for details of when the output becomes valid. 3.2 Bus write Bus write operations write commands to the memory or latch input data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, input data and addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses must be latched prior to the write operation by toggling Latch Enable (when Chip Enable is at VIL). The Latch Enable must be tied to VIH during the bus write operation. See Figures 17 and 18, write AC waveforms, and Tables 26 and 27, write AC characteristics for details of the timing requirements. 3.3 Address Latch Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at VIL during address latch operations. The addresses are latched on the rising edge of Latch Enable. 3.4 Output disable The outputs are high impedance when the Output Enable is at VIH. 21/120 Bus operations 3.5 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Standby Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in standby when Chip Enable and Reset are at VIH. The power consumption is reduced to the standby level IDD3 and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters standby mode when finished. 3.6 Reset During reset mode the memory is deselected and the outputs are high impedance. The memory is in reset mode when Reset is at VIL. The power consumption is reduced to the reset level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a program or erase, this operation is aborted and the memory content is no longer valid. Table 4. Bus operations(1) Operation Bus read WAIT(2) E G W L RP VIL VIL VIH VIL(3) VIH Data output (3) VIH Data input Data output or Hi-Z(4) Bus write VIL VIH VIL Address latch VIL X VIH VIL VIH Output disable VIL VIH VIH X VIH Hi-Z Hi-Z Standby VIH X X X VIH Hi-Z Hi-Z X X X X VIL Hi-Z Hi-Z Reset VIL 1. X = ‘don't care’ 2. WAIT signal polarity is configured using the Set Configuration Register command. 3. L can be tied to VIH if the valid address has been previously latched. 4. Depends on G. 22/120 DQ15-DQ0 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 4 Command interface Command interface All bus write operations to the memory are interpreted by the command interface. Commands consist of one or more sequential bus write operations. An internal Program/Erase Controller manages all timings and verifies the correct execution of the program and erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The command interface is reset to read mode when power is first applied, when exiting from Reset or whenever VDD is lower than VLKO. Command sequences must be followed exactly. Any invalid combination of commands are ignored. Refer to Table 5: Command codes, Table 6: Standard commands, Table 7: Factory commands and Appendix D: Command interface state tables for a summary of the command interface. Table 5. Command codes Hex Code Command 01h Block Lock Confirm 03h Set Configuration Register Confirm 10h Alternative Program Setup 20h Block Erase Setup 2Fh Block Lock-Down Confirm 40h Program Setup 50h Clear Status Register 60h Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup 70h Read Status Register 80h Buffer Enhanced Factory Program Setup 90h Read Electronic Signature 98h Read CFI Query B0h Program/Erase Suspend BCh Blank Check Setup C0h Protection Register Program CBh Blank Check Confirm D0h Program/Erase Resume, Block Erase Confirm, Block Unlock Confirm, Buffer Program or Buffer Enhanced Factory Program Confirm E8h Buffer Program FFh Read Array 23/120 Command interface 4.1 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Read Array command The Read Array command returns the addressed bank to read array mode. One bus write cycle is required to issue the Read Array command. Once a bank is in read array mode, subsequent read operations outputs the data from the memory array. A Read Array command can be issued to any banks while programming or erasing in another bank. If the Read Array command is issued to a bank currently executing a program or erase operation, the bank returns to read array mode but the program or erase operation continues, however the data output from the bank is not guaranteed until the program or erase operation has finished. The read modes of other banks are not affected. 4.2 Read Status Register command The device contains a Status Register that monitors program or erase operations. The Read Status Register command reads the contents of the Status Register for the addressed bank. One bus write cycle is required to issue the Read Status Register command. Once a bank is in read Status Register mode, subsequent read operations output the contents of the Status Register. The Status Register data is latched on the falling edge of the Chip Enable or Output Enable signals. Either Chip Enable or Output Enable must be toggled to update the Status Register data. The Read Status Register command can be issued at any time, even during program or erase operations. The Read Status Register command only changes the read mode of the addressed bank. The read modes of other banks are not affected. only asynchronous read and single synchronous read operations should be used to read the Status Register. A Read Array command is required to return the bank to read array mode. See Table 10 for the description of the Status Register bits. 24/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 4.3 Command interface Read Electronic Signature command The Read Electronic Signature command reads the manufacturer and device codes, the lock status of the addressed bank, the Protection Register, and the Configuration Register. One bus write cycle is required to issue the Read Electronic Signature command. Once a bank is in read electronic signature mode, subsequent read operations in the same bank output the manufacturer code, the device code, the lock status of the addressed bank, the Protection Register, or the Configuration Register (see Table 9). The Read Electronic Signature command can be issued at any time, even during program or erase operations, except during Protection Register Program operations. Dual operations between the parameter bank and the electronic signature location are not allowed (see Table 16: Dual operation limitations for details). If a Read Electronic Signature command is issued to a bank that is executing a program or erase operation, the bank goes into read electronic signature mode. Subsequent bus read cycles output the electronic signature data and the Program/Erase Controller continue to program or erase in the background. The Read Electronic Signature command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read the electronic signature. A Read Array command is required to return the bank to read array mode. 4.4 Read CFI Query command The Read CFI Query command reads data from the common Flash interface (CFI). One bus write cycle is required to issue the Read CFI Query command. Once a bank is in read CFI query mode, subsequent bus read operations in the same bank read from the common Flash interface. The Read CFI Query command can be issued at any time, even during program or erase operations. If a Read CFI Query command is issued to a bank that is executing a program or erase operation the bank gos into read CFI query mode. Subsequent bus read cycles output the CFI data and the Program/Erase Controller continues to program or erase in the background. The Read CFI Query command only changes the read mode of the addressed bank. The read modes of other banks are not affected. Only asynchronous read and single synchronous read operations should be used to read from the CFI. A Read Array command is required to return the bank to read array mode. Dual operations between the parameter bank and the CFI memory space are not allowed (see Table 16: Dual operation limitations for details). See Appendix B: Common Flash interface and Tables 45, 46, 47, 48, 49, 50, 51, 52, 53 and 54 for details on the information contained in the common Flash interface memory area. 25/120 Command interface 4.5 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Clear Status Register command The Clear Status Register command resets (set to ‘0’) all error bits (SR1, 3, 4 and 5) in the Status Register. One bus write cycle is required to issue the Clear Status Register command. The Clear Status Register command does not affect the read mode of the bank. The error bits in the Status Register do not automatically return to ‘0’ when a new command is issued. The error bits in the Status Register should be cleared before attempting a new program or erase command. 4.6 Block Erase command The Block Erase command erases a block. It sets all the bits within the selected block to ’1’. All previous data in the block is lost. If the block is protected then the erase operation aborts, the data in the block does not change and the Status Register outputs the error. Two bus write cycles are required to issue the command. z The first bus cycle sets up the Block Erase command. z The second latches the block address and starts the Program/Erase Controller. If the second bus cycle is not the Block Erase Confirm code, Status Register bits SR4 and SR5 are set and the command is aborted. Once the command is issued the bank enters Read Status Register mode and any read operation within the addressed bank outputs the contents of the Status Register. A Read Array command is required to return the bank to read array mode. During block erase operations the bank containing the block being erased only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. The block erase operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the block erase operation is aborted, the block must be erased again. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being erased. Typical erase times are given in Table 18: Program/erase times and endurance cycles. See Appendix C, Figure 28: Block erase flowchart and pseudocode for a suggested flowchart for using the Block Erase command. 26/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 4.7 Command interface Blank Check command The Blank Check command checks whether a main array block has been completely erased. Only one block at a time can be checked. To use the Blank Check command VPP must be equal to VPPH. If VPP is not equal to VPPH, the device ignores the command and no error is shown in the Status Register. Two bus cycles are required to issue the Blank Check command: z The first bus cycle writes the Blank Check command (BCh) to any address in the block to be checked. z The second bus cycle writes the Blank Check Confirm command (CBh) to any address in the block to be checked and starts the blank check operation. If the second bus cycle is not Blank Check Confirm, Status Register bits SR4 and SR5 are set to '1' and the command aborts. Once the command is issued, the addressed bank automatically enters the Status Register mode and further reads within the bank output the Status Register contents. The only operation permitted during blank check is Read Status Register. Dual operations are not supported while a blank check operation is in progress. Blank check operations cannot be suspended and are not allowed while the device is in program/erase suspend. The SR7 Status Register bit indicates the status of the blank check operation in progress. SR7 = '0' means that the Blank Check operation is still ongoing, and SR7 = '1' means that the operation is complete. The SR5 Status Register bit goes High (SR5 = '1') to indicate that the blank check operation has failed. At the end of the operation the bank remains in the read Status Register mode until another command is written to the command interface. See Appendix C, Figure 25: Blank check flowchart and pseudocode for a suggested flowchart for using the Blank Check command. Typical blank check times are given in Table 18: Program/erase times and endurance cycles. 27/120 Command interface 4.8 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Program command The Program command programs a single word to the memory array. If the block being programmed is protected, then the program operation aborts, the data in the block does not change and the Status Register outputs the error. Two bus write cycles are required to issue the Program command: z The first bus cycle sets up the Program command. z The second latches the address and data to be programmed and starts the Program/Erase Controller. Once the programming has started, read operations in the bank being programmed output the Status Register content. During a program operation, the bank containing the word being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. A Read Array command is required to return the bank to read array mode. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. Typical program times are given in Table 18: Program/erase times and endurance cycles. The program operation aborts if Reset, RP, goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the word must be reprogrammed. See Appendix C, Figure 24: Program flowchart and pseudocode for the flowchart for using the Program command. 4.9 Buffer Program command The Buffer Program Command uses the device’s 32-word write buffer to speed up programming. Up to 32 words can be loaded into the write buffer. The Buffer Program command dramatically reduces in-system programming time compared to the standard nonbuffered Program command. Four successive steps are required to issue the Buffer Program command: 1. The first bus write cycle sets up the Buffer Program command. The setup code can be addressed to any location within the targeted block. After the first bus write cycle, read operations in the bank output the contents of the Status Register. Status Register bit SR7 should be read to check that the buffer is available (SR7 = 1). If the buffer is not available (SR7 = 0), re-issue the Buffer Program command to update the Status Register contents. 2. 28/120 The second bus write cycle sets up the number of words to be programmed. Value n is written to the same block address, where n+1 is the number of words to be programmed. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface 3. Use n+1 bus write cycles to load the address and data for each word into the write buffer. Addresses must lie within the range from the start address to the start address + n, where the start address is the location of the first data to be programmed. Optimum performance is obtained when the start address corresponds to a 32 word boundary. 4. The final bus write cycle confirms the Buffer Program command and starts the program operation. All the addresses used in the Buffer Program operation must lie within the same block. Invalid address combinations or failing to follow the correct sequence of bus write cycles sets an error in the Status Register and aborts the operation without affecting the data in the memory array. If the Status Register bits SR4 and SR5 are set to '1', the Buffer Program command is not accepted. Clear the Status Register before re-issuing the command. If the block being programmed is protected an error sets in the Status Register and the operation aborts without affecting the data in the memory array. During Buffer Program operations the bank being programmed only accepts the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend commands; all other commands are ignored. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed in banks not being programmed. See Appendix C, Figure 26: Buffer program flowchart and pseudocode for a suggested flowchart on using the Buffer Program command. 4.10 Buffer Enhanced Factory Program command The Buffer Enhanced Factory Program command has been specially developed to speed up programming in manufacturing environments where the programming time is critical. It is used to program one or more write buffer(s) of 32 words to a block. Once the device enters Buffer Enhanced Factory Program mode, the write buffer can be reloaded any number of times as long as the address remains within the same block. Only one block can be programmed at a time. If the block being programmed is protected, then the Program operation aborts the data in the block does not change, and the Status Register outputs the error. The use of the Buffer Enhanced Factory Program command requires the following operating conditions: z VPP must be set to VPPH z VDD must be within operating range z Ambient temperature TA must be 30°C ± 10°C z The targeted block must be unlocked z The start address must be aligned with the start of a 32 word buffer boundary z The address must remain the start address throughout programming. Dual operations are not supported during the Buffer Enhanced Factory Program operation and the command cannot be suspended. 29/120 Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB The Buffer Enhanced Factory Program Command consists of three phases: the setup phase, the program and verify phase, and the exit phase, Please refer to Table 7: Factory commands for detailed information. 4.10.1 Setup phase The Buffer Enhanced Factory Program command requires two bus write cycles to initiate the command: z The first bus write cycle sets up the Buffer Enhanced Factory Program command. z The second bus write cycle confirms the command. After the confirm command is issued, read operations output the contents of the Status Register. The Read Status Register command must not be issued or it is interpreted as data to program. The Status Register P/EC bit SR7 should be read to check that the P/EC is ready to proceed to the next phase. If an error is detected, SR4 goes high (set to ‘1’) and the Buffer Enhanced Factory Program operation is terminated. See Section 5: Status Register for details on the error. 4.10.2 Program and verify phase The program and verify phase requires 32 cycles to program the 32 words to the write buffer. The data is stored sequentially, starting at the first address of the write buffer, until the write buffer is full (32 words). To program less than 32 words, the remaining words should be programmed with FFFFh. Three successive steps are required to issue and execute the program and verify phase of the command: 1. Use one bus write operation to latch the start address and the first word to be programmed. The Status Register bank write status bit SR0 should be read to check that the P/EC is ready for the next word. 2. Each subsequent word to be programmed is latched with a new bus write operation. The address must remain the start address as the P/EC increments the address location. If any address is given that is not in the same block as the start address, the program and verify phase terminates. Status Register bit SR0 should be read between each bus write cycle to check that the P/EC is ready for the next word. 3. Once the write buffer is full, the data is programmed sequentially to the memory array. After the program operation the device automatically verifies the data and reprograms if necessary. The program and verify phase can be repeated, without re-issuing the command, to program additional 32 word locations as long as the address remains in the same block. 4. Finally, after all words, or the entire block have been programmed, write one bus write operation to any address outside the block containing the start address, to terminate program and verify phase. Status Register bit SR0 must be checked to determine whether the program operation is finished. The Status Register may be checked for errors at any time but it must be checked after the entire block has been programmed. 30/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 4.10.3 Command interface Exit phase Status Register P/EC bit SR7 set to ‘1’ indicates that the device has exited the buffer enhanced factory program operation and returned to read Status Register mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See Section 5: Status Register for more details. For optimum performance the Buffer Enhanced Factory Program command should be limited to a maximum of 100 program/erase cycles per block. If this limit is exceeded the internal algorithm continues to work properly but some degradation in performance is possible. Typical program times are given in Table 18. See Appendix C, Figure 32: Buffer enhanced factory program flowchart and pseudocode for a suggested flowchart on using the Buffer Enhanced Factory Program command. 4.11 Program/Erase Suspend command The Program/Erase Suspend command pauses a program or block erase operation. The command can be addressed to any bank. The Program/Erase Resume command is required to restart the suspended operation. One bus write cycle is required to issue the Program/Erase Suspend command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register are set to ‘1’. The following commands are accepted during Program/Erase Suspend: – Program/Erase Resume – Read Array (data from erase-suspended block or program-suspended word is not valid) – Read Status Register – Read Electronic Signature – Read CFI Query – Clear Status Register Additionally, if the suspended operation was a block erase then the following commands are also accepted: – Set Configuration Register – Program (except in erase-suspended block) – Buffer Program (except in erase suspended blocks) – Block Lock – Block Lock-Down – Block Unlock. During an erase suspend the block being erased can be protected by issuing the Block Lock or Block Lock-Down commands. When the Program/Erase Resume command is issued the operation completes. It is possible to accumulate multiple suspend operations. For example,it is possible to suspend an erase operation, start a program operation, suspend the program operation, and then read the array. 31/120 Command interface M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB If a Program command is issued during a block erase suspend, the erase operation cannot be resumed until the program operation has completed. The Program/Erase Suspend command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode, the bank remains in that mode and outputs the corresponding data. Refer to Section 8: Dual operations and multiple bank architecture for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/erase is aborted if Reset, RP, goes to VIL. See Appendix C, Figure 27: Program suspend and resume flowchart and pseudocode, and Figure 29: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Suspend command. 4.12 Program/Erase Resume command The Program/Erase Resume command restarts the program or erase operation suspended by the Program/Erase Suspend command. One bus write cycle is required to issue the command. The command can be issued to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in read Status Register, read electronic signature or read CFI query mode the bank remains in that mode and outputs the corresponding data. If a program command is issued during a block erase suspend, then the erase cannot be resumed until the program operation has completed. See Appendix C, Figure 27: Program suspend and resume flowchart and pseudocode, and Figure 29: Erase suspend and resume flowchart and pseudocode for flowcharts for using the Program/Erase Resume command. 4.13 Protection Register Program command The Protection Register Program command programs the user OTP segments of the Protection Register and the two Protection Register locks. The device features 16 OTP segments of 128 bits and one OTP segment of 64 bits, as shown in Figure 6: Protection Register memory map. The segments are programmed one word at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two bus write cycles are required to issue the Protection Register Program command. z The first bus cycle sets up the Protection Register Program command. z The second latches the address and data to be programmed to the Protection Register and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the program operation has started. Attempting to program a previously protected Protection Register results in a Status Register error. 32/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface The Protection Register Program cannot be suspended. Dual operations between the parameter bank and the Protection Register memory space are not allowed (see Table 16: Dual operation limitations for details) The two Protection Register locks protect the OTP segments from further modification. The protection of the OTP segments is not reversible. Refer to Figure 6: Protection Register memory map and Table 9: Protection Register locks for details on the lock bits. See Appendix C, Figure 31: Protection Register program flowchart and pseudocode for a flowchart for using the Protection Register Program command. 4.14 Set Configuration Register command The Set Configuration Register command writes a new value to the Configuration Register. Two bus write cycles are required to issue the Set Configuration Register comman: z The first cycle sets up the Set Configuration Register command and the address corresponding to the Configuration Register content. z The second cycle writes the Configuration Register data and the confirm command. The Configuration Register data must be written as an address during the bus write cycles, that is A0 = CR0, A1 = CR1, …, A15 = CR15. Addresses A16-Amax are ignored. Read operations output the array content after the Set Configuration Register command is issued. The Read Electronic Signature command is required to read the updated contents of the Configuration Register. 4.15 Block Lock command The Block Lock command locks a block and prevent program or erase operations from changing the data in it. All blocks are locked after power-up or reset. Two bus write cycles are required to issue the Block Lock command: z The first bus cycle sets up the Block Lock command. z The second bus write cycle latches the block address and locks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the lock status after issuing a Block Lock command. Once set, the block lock bits remain set even after a hardware reset or power-down/powerup. They are cleared by a Block Unlock command. Refer to Section 9: Block locking for a detailed explanation. See Appendix C, Figure 30: Locking operations flowchart and pseudocode for a flowchart for using the Lock command. 33/120 Command interface 4.16 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Block Unlock command The Block Unlock command unlocks a block, allowing the block to be programmed or erased. Two bus write cycles are required to issue the Block Unlock command: z The first bus cycle sets up the Block Unlock command. z The second bus write cycle latches the block address and unlocks the block. The lock status can be monitored for each block using the Read Electronic Signature command. Table 17 shows the protection status after issuing a Block Unlock command. Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 30: Locking operations flowchart and pseudocode for a flowchart for using the Block Unlock command. 4.17 Block Lock-Down command The Block Lock-Down command is used to lock down a locked or unlocked block. A locked-down block cannot be programmed or erased. The lock status of a locked-down block cannot be changed when WP is low, VIL. When WP is high, VIH, the lock-down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two bus write cycles are required to issue the Block Lock-Down command: z The first bus cycle sets up the Block Lock-Down command. z The second bus write cycle latches the block address and locks down the block. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table 17 shows the lock status after issuing a Block Lock-Down command. Refer to Section 9: Block locking for a detailed explanation and Appendix C, Figure 30: Locking operations flowchart and pseudocode for a flowchart for using the Lock-Down command. 34/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Command interface Standard commands(1) Table 6. Commands Cycles Bus operations 1st cycle 2nd cycle Op. Add Data Op. Add Data Read Array 1+ Write BKA FFh Read WA RD Read Status Register 1+ Write BKA 70h Read BKA(2) SRD Read BKA (2) ESD Read BKA(2) QD Read Electronic Signature 1+ Write BKA 90h Read CFI Query 1+ Write BKA 98h Clear Status Register 1 Write X 50h Block Erase 2 Write BKA or BA(3) 20h Write BA D0h Program 2 Write BKA or WA(3) 40h or 10h Write WA PD Write BA E8h Write BA n Write PA1 PD1 Write PA2 PD2 Write PAn+1 PDn+1 Write X D0h Buffer Program(4) n+4 Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h Protection Register Program 2 Write PRA C0h Write PRA PRD Set Configuration Register 2 Write CRD 60h Write CRD 03h Block Lock 2 Write BKA or BA(3) 60h Write BA 01h Block Unlock 2 Write BKA or BA(3) 60h Write BA D0h Block Lock-Down 2 Write BKA or BA(3) 60h Write BA 2Fh 1. X = Don't Care, WA = Word Address in targeted bank, RD =Read Data, SRD =Status Register Data, ESD = Electronic Signature Data, QD =Query Data, BA =Block Address, BKA = Bank Address, PD = Program Data, PRA = Protection Register Address, PRD = Protection Register Data, CRD = Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 8. 3. Any address within the bank can be used. 4. n+1 is the number of words to be programmed. 35/120 Command interface Table 7. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Factory commands Command Cycles Bus write operations(1) Phase Blank Check Setup 1st 2nd 3rd Add Data Add Data Add Data 2 BA BCh BA CBh 2 BKA or WA(2) 80h WA1 D0h WA1 PD1 WA1 PD2 WA1 PD3 NOT BA1(4) X Buffer Enhanced Program/ ≥32 Factory verify(3) Program Exit 1 Final -1 Add Final Data Add Data WA1 PD31 WA1 PD32 1. WA = Word Address in targeted bank, BKA = Bank Address, PD =Program Data, BA = Block Address, X = ‘don’t care’. 2. Any address within the bank can be used. 3. The program/verify phase can be executed any number of times as long as the data is to be programmed to the same block. 4. WA1 is the start address, NOT BA1 = Not Block Address of WA1. Table 8. Electronic signature codes Code Manufacturer code Address (h) Bank address + 00 0020 Top Bank address + 01 88C4 (M58LR128KT) 880D (M58LR256KT) Bottom Bank address + 01 88C5 (M58LR128KB) 880E (M58LR256KB) Device code Locked Block protection Unlocked Locked and locked-down 0001 Block address + 02 Unlocked and locked-down Configuration Register Protection Register PR0 lock Numonyx factory default OTP area permanently locked 0000 0003 0002 Bank address + 05 CR(1) 0002 Bank address + 80 0000 Bank address + 81 Bank address + 84 Unique device number Bank address + 85 Bank address + 88 OTP Area Protection Register PR1 through PR16 Lock Bank address + 89 PRLD(1) Protection Registers PR1-PR16 Bank address + 8A Bank address + 109 OTP area Protection Register PR0 1. CR = Configuration Register, PRLD = Protection Register Lock Data. 36/120 Data (h) M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 6. Command interface Protection Register memory map PROTECTION REGISTERS 109h PR16 User Programmable OTP 102h 91h PR1 User Programmable OTP 8Ah Protection Register Lock 89h 88h 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 PR0 User Programmable OTP 85h 84h Unique device number 81h 80h Protection Register Lock 1 0 AI07563 37/120 Command interface Table 9. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Protection Register locks Lock Description Number Lock 1 Address 80h Bits Bit 0 Preprogrammed to protect unique device number, address 81h to 84h in PR0 Bit 1 Protects 64 bits of OTP segment, address 85h to 88h in PR0 Bits 2 to 15 Reserved 38/120 Bit 1 Protects 128 bits of OTP segment PR2 Bit 2 Protects 128 bits of OTP segment PR3 ---- 89h Protects 128 bits of OTP segment PR1 ---- Lock 2 Bit 0 Bit 13 Protects 128 bits of OTP segment PR14 Bit 14 Protects 128 bits of OTP segment PR15 Bit 15 Protects 128 bits of OTP segment PR16 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 5 Status Register Status Register The Status Register provides information on the current or previous program or erase operations. Issue a Read Status Register command to read the contents of the Status Register (refer to Section 4.2: Read Status Register command for more details). To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single Asynchronous or single synchronous reads. Bus read operations from any address within the bank always read the Status Register during program and erase operations if no Read Array command has been issued. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. The bits in the Status Register are summarized in Table 10: Status Register bits. Refer to Table 10 in conjunction with the following text descriptions. 5.1 Program/Erase Controller status bit (SR7) The Program/Erase Controller status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller status bit is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. 5.2 Erase suspend status bit (SR6) The erase suspend status bit indicates that an erase operation has been suspended in the addressed block. When the erase suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The erase suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). SR6 is set within the erase suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued the erase suspend status bit returns Low. 39/120 Status Register 5.3 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Erase/blank check status bit (SR5) The erase/blank check status bit identifies if there was an error during a block erase operation. When the erase/blank check status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block and still failed to verify that it has erased correctly. The erase/blank check status bit should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). The erase/blank check status bit is also used to indicate whether an error occurred during the blank check operation. If the data at one or more locations in the block where the Blank Check command has been issued is different from FFFFh, SR5 is set to '1'. Once set High, the erase/blank check status bit must be set Low by a Clear Status Register command or a hardware reset before a new erase command is issued, otherwise the new command appears to fail. 5.4 Program status bit (SR4) The program status bit identifies if there was an error during a program operation. It should be read once the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the program status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the word and still failed to verify that it has programmed correctly. Attempting to program a '1' to an already programmed bit while VPP = VPPH also sets the program status bit High. If VPP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown. Once set High, the program status bit must be set Low by a Clear Status Register command or a hardware reset before a new program command is issued, otherwise the new command appears to fail. 5.5 VPP status bit (SR3) The VPP status bit identifies an invalid voltage on the VPP pin during program and erase operations. The VPP pin is only sampled at the beginning of a program or erase operation. Program and erase operations are not guaranteed if VPP becomes invalid during an operation When the VPP status bit is Low (set to ‘0’), the voltage on the VPP pin was sampled at a valid voltage. When the VPP status bit is High (set to ‘1’), the VPP pin has a voltage that is below the VPP lockout voltage, VPPLK, the memory is protected and program and erase operations cannot be performed. Once set High, the VPP status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail. 40/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 5.6 Status Register Program suspend status bit (SR2) The program suspend status bit indicates that a program operation has been suspended in the addressed block. The program suspend status bit should only be considered valid when the Program/Erase Controller status bit is High (Program/Erase Controller inactive). When the program suspend status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. SR2 is set within the program suspend latency time of the Program/Erase Suspend command being issued, therefore, the memory may still complete the operation rather than entering the suspend mode. When a Program/Erase Resume command is issued the program suspend status bit returns Low. 5.7 Block protection status bit (SR1) The block protection status bit identifies if a program or block erase operation has tried to modify the contents of a locked or locked-down block. When the block protection status bit is High (set to ‘1’), a program or erase operation has been attempted on a locked or locked-down block Once set High, the block protection status bit must be set Low by a Clear Status Register command or a hardware reset before a new program or erase command is issued, otherwise the new command appears to fail. 5.8 Bank write/multiple word program status bit (SR0) The bank write status bit indicates whether the addressed bank is programming or erasing. In buffer enhanced factory program mode the multiple word program bit shows if the device is ready to accept a new word to be programmed to the memory array. The bank write status bit should only be considered valid when the Program/Erase Controller status bit SR7 is Low (set to ‘0’). When both the Program/Erase Controller status bit and the bank write status bit are Low (set to ‘0’), the addressed bank is executing a program or erase operation. When the Program/Erase Controller status bit is Low (set to ‘0’) and the bank write status bit is High (set to ‘1’), a program or erase operation is being executed in a bank other than the one being addressed. In buffer enhanced factory program mode if multiple word program status bit is Low (set to ‘0’), the device is ready for the next word. If the multiple word program status bit is High (set to ‘1’) the device is not ready for the next word. For further details on how to use the Status Register, see the Flowcharts and Pseudocodes provided in Appendix C. 41/120 Status Register M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 10. Bit Status Register bits Name SR7 P/EC status Type Status SR6 Erase suspend status Status SR5 Erase/blank check status Error SR4 Program status Error SR3 VPP status Error SR2 Program suspend status Status SR1 Block protection status Error Logic level(1) Definition '1' Ready '0' Busy '1' Erase suspended '0' Erase In progress or completed '1' Erase/blank check error '0' Erase/blank check success '1' Program error '0' Program success '1' VPP invalid, abort '0' VPP OK '1' Program suspended '0' Program in progress or completed '1' Program/erase on protected block, abort '0' No operation to protected blocks SR7 = ‘1’ Not allowed '1' Bank write status Status SR7 = ‘0’ Program or erase operation in a bank other than the addressed bank SR7 = ‘1’ No program or erase operation in the device SR7 = ‘0’ Program or erase operation in addressed bank '0' SR0 SR7 = ‘1’ Not allowed Multiple word program status (buffer enhanced factory program mode) '1' Status 1. Logic level '1' is High, '0' is Low. 42/120 The device is not ready for the next SR7 = ‘0’ buffer loading or is going to exit the BEFP mode SR7 = ‘1’ The device has exited the BEFP mode SR7 = ‘0’ The device is ready for the next buffer loading '0' M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 6 Configuration Register Configuration Register The Configuration Register configures the type of bus access that the memory performs. Refer to Section 7: Read modes for details on read operations. The Configuration Register is set through the command interface using the Set Configuration Register command. After a reset or power-up the device is configured for asynchronous read (CR15 = 1). The Configuration Register bits are described in Table 12 They specify the selection of the burst length, burst type, burst X latency and the read operation. Refer to Figures 7 and 8 for examples of synchronous burst configurations. 6.1 Read select bit (CR15) The read select bit, CR15, switches between asynchronous and synchronous read operations. When the read select bit is set to ’1’, read operations are asynchronous, and when the read select bit is set to ’0’, read operations are synchronous. Synchronous burst read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the read select bit is set to ’1’ for asynchronous access. 6.2 X latency bits (CR13-CR11) The X latency bits are used during synchronous read operations to set the number of clock cycles between the address being latched and the first data becoming available. Refer to Figure 7: X latency and data output configuration example. For correct operation the X latency bits can only assume the values in Table 12: Configuration Register. Table 11 shows how to set the X latency parameter, taking into account the speed class of the device and the frequency used to read the Flash memory in synchronous mode. Table 11. X latency settings fmax tKmin X latency min 30 MHz 33 ns 3 40 MHz 25 ns 4 54 MHz 19 ns 5 66 MHz 15 ns 5 43/120 Configuration Register 6.3 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Wait polarity bit (CR10) The wait polarity bit is used to set the polarity of the Wait signal used in synchronous burst read mode. During synchronous burst read mode the Wait signal indicates whether the data output are valid or a WAIT state must be inserted. When the wait polarity bit is set to ‘0’ the Wait signal is active Low. When the wait polarity bit is set to ‘1’ the Wait signal is active High. 6.4 Data output configuration bit (CR9) The data output configuration bit configures the output to remain valid for either one or two clock cycles during synchronous mode. When the data output configuration bit is ’0’ the output data is valid for one clock cycle, and when the data output configuration bit is ’1’ the output data is valid for two clock cycles. The data output configuration bit must be configured using the following condition: z tK > tKQV + tQVK_CPU where z tK is the clock period z tQVK_CPU is the data setup time required by the system CPU z tKQV is the clock to data valid time. If this condition is not satisfied, the data output configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 7: X latency and data output configuration example. 6.5 Wait configuration bit (CR8) The wait configuration bit is used to control the timing of the Wait output pin, WAIT, in synchronous burst read mode. When WAIT is asserted, data is not valid and when WAIT is de-asserted, data is valid. When the wait configuration bit is Low (set to ’0’) the Wait output pin is asserted during the WAIT state. When the wait configuration bit is High (set to ’1’), the Wait output pin is asserted one data cycle before the WAIT state. 6.6 Burst type bit (CR7) The burst type bit determines the sequence of addresses read during synchronous burst reads. The burst type bit is High (set to ’1’), as the memory outputs from sequential addresses only. See Table 13: Burst type definition for the sequence of addresses output from a given starting address in sequential mode. 44/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 6.7 Configuration Register Valid Clock edge bit (CR6) The valid Clock edge bit, CR6, configures the active edge of the Clock, K, during synchronous read operations. When the valid Clock edge bit is Low (set to ’0’) the falling edge of the Clock is the active edge. When the valid Clock edge bit is High (set to ’1’) the rising edge of the Clock is the active edge. 6.8 Wrap burst bit (CR3) The wrap burst bit, CR3, selects between wrap and no wrap. Synchronous burst reads can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). When the Wrap Burst bit is Low (set to ‘0’) the burst read wraps. When it is High (set to ‘1’) the burst read does not wrap. 6.9 Burst length bits (CR2-CR0) The burst length bits sets the number of words to be output during a synchronous burst read operation as result of a single address latch cycle. They can be set for 4 words, 8 words, 16 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode, in 4, 8 or 16 words no-wrap, depending on the starting address, the device asserts the WAIT signal to indicate that a delay is necessary before the data is output. If the starting address is shifted by 1, 2 or 3 positions from the four-word boundary, WAIT is asserted for 1, 2 or 3 clock cycles, respectively. When the burst sequence crosses the first 16-word boundary this indicates that the device needs an internal delay to read the successive words in the array. WAITis asserted only once during a continuous burst access. See also Table 13: Burst type definition. CR14, CR5 and CR4 are reserved for future use. 45/120 Configuration Register Table 12. Bit M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Configuration Register Description CR15 Read select CR14 Reserved CR13-CR11 X latency Value Description 0 Synchronous read 1 Asynchronous Read (default at power-on) 010 2 clock latency(1) 011 3 clock latency 100 4 clock latency 101 5 clock latency 110 6 clock latency 111 7 clock latency (default) Other configurations reserved CR10 Wait polarity CR9 Data output configuration CR8 Wait configuration CR7 Burst type CR6 Valid Clock edge CR5-CR4 CR3 CR2-CR0 0 WAIT is active Low 1 WAIT is active High (default) 0 Data held for one clock cycle 1 Data held for two clock cycles (default)(1) 0 WAIT is active during WAIT state 1 WAIT is active one data cycle before WAIT state(1) (default) 0 Reserved 1 Sequential (default) 0 Falling Clock edge 1 Rising Clock edge (default) 0 Wrap 1 No wrap (default) 001 4 words 010 8 words 011 16 words 111 Continuous (default) Reserved Wrap burst Burst Length 1. The combination X latency=2, data held for two clock cycles and Wait active one data cycle before the WAIT state is not supported. 46/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Wrap Mode Table 13. Start addr Configuration Register Burst type definition Sequential Continuous burst 4 words 8 words 16 words 0 0-1-2-3 0-1-2-3-4-5-67 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 0-1-2-3-4-5-6... 1 1-2-3-0 1-2-3-4-5-6-70 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-0 1-2-3-4-5-6-7-...15-WAIT-16-1718... 2 2-3-0-1 2-3-4-5-6-7-01 2-3-4-5-6-7-8-9-10-1112-13-14-15-0-1 2-3-4-5-6-7...15-WAIT-WAIT16-17-18... 3 3-0-1-2 3-4-5-6-7-0-1- 3-4-5-6-7-8-9-10-11-122 13-14-15-0-1-2 7-4-5-6 7-0-1-2-3-4-56 3-4-5-6-7...15-WAIT-WAITWAIT-16-17-18... ... 7 7-8-9-10-11-12-13-1415-0-1-2-3-4-5-6 7-8-9-10-11-12-13-14-15-WAITWAIT-WAIT-16-17... ... 12 12-13-14-15-16-17-18... 13 13-14-15-WAIT-16-17-18... 14 14-15-WAIT-WAIT-16-17-18.... 15 15-WAIT-WAIT-WAIT-16-1718... 47/120 Configuration Register Mode Table 13. Start addr M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Burst type definition (continued) Sequential Continuous burst 4 words 8 words 16 words 0 0-1-2-3 0-1-2-3-4-5-67 0-1-2-3-4-5-6-7-8-9-1011-12-13-14-15 1 1-2-3-4 1-2-3-4-5-6-78 1-2-3-4-5-6-7-8-9-1011-12-13-14-15-WAIT16 2 2-3-4-5 2-3-4-5-6-7-89... 2-3-4-5-6-7-8-9-10-1112-13-14-15-WAITWAIT-16-17 3 3-4-5-6 3-4-5-6-7-8-910 3-4-5-6-7-8-9-10-11-1213-14-15-WAIT-WAITWAIT-16-17-18 7-8-9-10 7-8-9-10-1112-13-14 7-8-9-10-11-12-13-1415-WAIT-WAIT-WAIT16-17-18-19-20-21-22 12 12-13-1415 12-13-14-1516-17-18-19 12-13-14-15-16-17-1819-20-21-22-23-24-2526-27 13 13-14-15WAIT-16 13-14-15WAIT-16-1718-19-20 13-14-15-WAIT-16-1718-19-20-21-22-23-2425-26-27-28 14 14-15WAITWAIT-1617 14-15-WAITWAIT-16-1718-19-20-21 14-15-WAIT-WAIT-1617-18-19-20-21-22-2324-25-26-27-28-29 15 15-WAITWAITWAIT-1617-18 15-WAITWAIT-WAIT16-17-18-1920-21-22 15-WAIT-WAIT-WAIT16-17-18-19-20-21-2223-24-25-26-27-28-2930 No-wrap ... 48/120 7 ... Same as for wrap (wrap /no wrap has no effect on continuous burst) M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 7. Configuration Register X latency and data output configuration example X-latency 1st cycle 2nd cycle 3rd cycle 4th cycle K E L Amax-A0(1) VALID ADDRESS tQVK_CPU tK tKQV DQ15-DQ0 VALID DATA VALID DATA Ai14014 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 2. The settings shown are X latency = 4, data output held for one clock cycle. 49/120 Configuration Register Figure 8. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Wait configuration example E K L Amax-A0(1) DQ15-DQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' AI14015 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 50/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 7 Read modes Read modes Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is asynchronous If the data output is synchronized with clock, the read operation is synchronous. The read mode and format of the data output are determined by the Configuration Register. (see Section 6: Configuration Register for details). All banks support both asynchronous and synchronous read operations. 7.1 Asynchronous read mode In asynchronous read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, common Flash interface or electronic signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for asynchronous operations. Asynchronous read operations can be performed in two different ways, Asynchronous random access read and asynchronous page read. Only asynchronous page read takes full advantage of the internal page storage so different timings are applied. In asynchronous read mode a page of data is internally read and stored in a page buffer. The page has a size of 4 words and is addressed by address inputs A0 and A1. The first read operation within the page has a longer access time (tAVQV, random access time), subsequent reads within the same page have much shorter access times (tAVQV1, page access time). If the page changes then the normal, longer timings apply again. The device features an automatic standby mode. During asynchronous read operations, after a bus inactivity of 150 ns, the device automatically switches to automatic standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In asynchronous read mode, the WAIT signal is always deasserted. See Table 24: Asynchronous read AC characteristics, Figure 11: Asynchronous random access read AC waveforms and Figure 12: Asynchronous page read AC waveforms for details. 51/120 Read modes 7.2 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Synchronous burst read mode In synchronous burst read mode the data is output in bursts synchronized with the clock. It is possible to perform burst reads across bank boundaries. Synchronous burst read mode can only be used to read the memory array. For other read operations, such as read Status Register, read CFI , and read electronic signature, single synchronous read or asynchronous random access read must be used. In synchronous burst read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence starts at the first clock edge (rising or falling depending on valid Clock edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and data is output on each data cycle after a delay which depends on the X latency bits CR13-CR11 of the Configuration Register. The number of words to be output during a synchronous burst read operation can be configured as 4 words, 8 words, 16 words or continuous (burst length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (data output configuration bit CR9). The order of the data output can be modified through the wrap burst bit in the Configuration Register. The burst sequence is sequential and can be confined inside the 4, 8 or 16 word boundary (wrap) or overcome the boundary (no wrap). The WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay depends on the starting address of the burst sequence and on the burst configuration. WAIT is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid. In continuous burst read mode a WAIT state occurs when crossing the first 16 word boundary. If the starting address is aligned to the burst length (4, 8 or 16 words) the wrapped configuration has no impact on the output sequence. The WAIT signal can be configured to be active Low or active High by setting CR10 in the Configuration Register. See Table 25: Synchronous read AC characteristics and Figure 13: Synchronous burst read AC waveforms for details. 52/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 7.2.1 Read modes Synchronous burst read suspend A synchronous burst read operation can be suspended, freeing the data bus for other higher priority devices. It can be suspended during the initial access latency time (before data is output) or after the device has output data. When the synchronous burst read operation is suspended, internal array sensing continues and any previously latched internal data is retained. A burst sequence can be suspended and resumed as often as required as long as the operating conditions of the device are met. A synchronous burst read operation is suspended when Chip Enable, E, is Low and the current address has been latched (on a Latch Enable rising edge or on a valid clock edge). The Clock signal is then halted at VIH or at VIL, and Output Enable, G, goes High. When Output Enable, G, becomes Low again and the Clock signal restarts, the synchronous burst read operation is resumed exactly where it stopped. WAIT reverts to high-impedance when Chip Enable, E, or Output Enable, G, goes High. See Table 25: Synchronous read AC characteristics and Figure 15: Synchronous burst read suspend AC waveforms for details. 7.3 Single synchronous read mode Single synchronous read operations are similar to synchronous burst read operations except that the memory outputs the same data to the end of the operation. Synchronous single reads are used to read the electronic signature, Status Register, CFI, block protection status, Configuration Register Status or the Protection Register. When the addressed bank is in read CFI, read Status Register or read electronic signature mode, the WAIT signal is asserted during the X latency, the WAIT state and at the end of a 4, 8 and 16 word burst. It is only de-asserted when output data are valid. See Table 25: Synchronous read AC characteristics and Figure 14: Single synchronous read AC waveforms for details. 53/120 Dual operations and multiple bank architecture 8 M58LR128KT, M58LR128KB, M58LR256KT, Dual operations and multiple bank architecture The multiple bank architecture of the M58LRxxxKT/B gives greater flexibility for software developers to split the code and data spaces within the memory array. The dual operations feature simplifies the software management of the device by allowing code to be executed from one bank while another bank is being programmed or erased. The dual operations feature means that while programming or erasing in one bank, read operations are possible in another bank with zero latency (only one bank at a time is allowed to be in program or erase mode). If a read operation is required in a bank, which is programming or erasing, the program or erase operation can be suspended. In addition, if the suspended operation is erase then a program command can be issued to another block. This means the device can have one block in erase suspend mode, one programming, and other banks in read mode. Bus read operations are allowed in another bank between setup and confirm cycles of program or erase operations. By using a combination of these features, read operations are possible at any moment in the M58LRxxxKT/B device. Dual operations between the parameter bank and either of the CFI, the OTP or the electronic signature memory space are not allowed. Table 16 shows which dual operations are allowed or not between the CFI, the OTP, the electronic signature locations and the memory array. Tables 14 and 15 show the dual operations possible in other banks and in the same bank. Table 14. Dual operations allowed in other banks Commands allowed in another bank Status of bank 54/120 Read Array Read Read Read Status CFI Electronic Register Query Signature Program, Buffer Program Block Erase Program Program /Erase /Erase Suspend Resume Idle Yes Yes Yes Yes Yes Yes Yes Yes Programming Yes Yes Yes Yes – – Yes – Erasing Yes Yes Yes Yes – – Yes – Program suspended Yes Yes Yes Yes – – – Yes Erase suspended Yes Yes Yes Yes Yes – – Yes M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 15. Dual operations and multiple bank ar- Dual operations allowed in same bank Commands allowed in same bank Status of bank Idle Read Array Read Read Read Status CFI Electronic Register Query Signature Program, Buffer Program Block Erase Program Program /Erase /Erase Suspend Resume Yes Yes Yes Yes Yes Yes Yes Yes – (1) Yes Yes Yes – – Yes – Erasing – (1) Yes Yes Yes – – Yes – Program suspended Yes Yes Yes Yes – – – Yes Erase suspended Yes(2 Yes Yes Yes Yes(1) – – Yes Programming (2) ) 1. The Read Array command is accepted but the data output is not guaranteed until the program or erase has completed. 2. Not allowed in the block that is being erased or in the word that is being programmed. Table 16. Dual operation limitations Commands allowed Read main blocks Current Status Programming/erasing parameter blocks Located in parameter bank Programming/ erasing main Not located in blocks parameter bank Programming OTP Read CFI / OTP / Electronic Signature Read Parameter Blocks No Located in parameter bank Not located in parameter bank No No Yes Yes No No Yes Yes Yes Yes In different bank only No No No No 55/120 Block locking 9 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Block locking The M58LRxxxKT/B features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. z Lock/unlock - this first level allows software only control of block locking. z Lock-down - this second level requires hardware interaction before locking can be changed. z VPP ≤ VPPLK - the third level offers complete hardware protection against program and erase on all blocks. The protection status of each block can be set to locked, unlocked, and locked-down. Table 17, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 30 shows a flowchart for the locking operations. 9.1 Reading block lock status The lock status of every block can be read in read electronic signature mode of the device. To enter this mode issue the Read Electronic Signature command. Subsequent reads at the address specified in Table 8 output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the block lock/unlock status and is set by the Lock command and cleared by the Unlock command. DQ0 is automatically set when entering lock-down. DQ1 indicates the lock-down status and is set by the LockDown command. DQ1 cannot be cleared by software, except a hardware reset or powerdown. The following sections explain the operation of the locking system. 9.2 Locked state The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from program or erase operations. Any program or erase operations attempted on a locked block will return an error in the Status Register. The status of a locked block can be changed to unlocked or locked-down using the appropriate software commands. An unlocked block can be locked by issuing the Lock command. 9.3 Unlocked state Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the locked state after a hardware reset or when the device is powereddown. The status of an unlocked block can be changed to locked or locked-down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. 56/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 9.4 Block locking Lock-down state Blocks that are locked-down (state (0,1,x))are protected from program and erase operations (as for locked blocks) but their protection status cannot be changed using software commands alone. A locked or unlocked block can be locked down by issuing the LockDown command. Locked-down blocks revert to the locked state when the device is reset or powered-down. The lock-down function is dependent on the Write Protect, WP, input pin. When WP=0 (VIL), the blocks in the lock-down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (VIH) the lock-down function is disabled (1,1,x) and locked-down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. When the lock-down function is disabled (WP=1) blocks can be locked (1,1,1) and unlocked (1,1,0) as desired. When WP=0 blocks that were previously locked-down return to the lockdown state (0,1,x) regardless of any changes that were made while WP=1. Device reset or power-down resets all blocks, including those in lock-down, to the locked state. 9.5 Locking operations during erase suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the Status Register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status is changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked down during an erase suspend of the same block, the locking status bits is changed immediately, but when the erase is resumed, the erase operation completes. Locking operations cannot be performed during a program suspend. 57/120 Block locking M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 17. Lock status Current protection status(1) Next protection status(1) (WP, DQ1, DQ0) (WP, DQ1, DQ0) Current state Program/erase allowed After Block Lock command After Block Unlock command After Block Lock-Down command After WP transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 no 0,0,1 0,0,0 0,1,1 1,0,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0(3) (2) 1,0,1 (2) 0,0,1 0,1,1 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with DQ1 = VIH and DQ0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 58/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 10 Program and erase times and endur- Program and erase times and endurance cycles The program and erase times and the number of program/ erase cycles per block are shown in Table 18. Exact erase times may change depending on the memory array condition. The best case is when all the bits in the block are at ‘0’ (pre-programmed). The worst case is when all the bits in the block are at ‘1’ (not preprogrammed). Usually, the system overhead is negligible with respect to the erase time. In the M58LRxxxKT/B the maximum number of program/erase cycles depends on the VPP voltage supply used. Table 18. Program/erase times and endurance cycles(1) (2) Typ Typical after 100kW/E cycles Max Unit 0.6 1 2.5 s Preprogrammed 1.2 3 4 s Not preprogrammed 1.5 4 s Word program 12 180 μs Buffer program 12 180 μs Buffer (32 words) (buffer program) 384 μs Main block (64 Kword) 768 ms Program 20 25 μs Erase 20 25 μs Parameter Condition Min Parameter block (16 Kword) VPP = VDD Erase Main block (64 Kword) Single Word Program(3) Suspend latency Program/erase cycles (per block) Main blocks 100 000 cycles Parameter blocks 100 000 cycles 59/120 Program and erase times and endurance cycles Program/erase times and endurance cycles(1) (2) (continued) Table 18. Parameter Condition Unit 0.6 2.5 s 1 4 s Word program 10 170 μs Buffer enhanced factory program(4) 2.5 μs Buffer program 80 μs 80 μs Buffer program 160 ms Buffer enhanced factory program 160 ms Buffer program 1.28 s Buffer enhanced factory program 1.28 s Main block (64 Kword) Single word (3) Program Buffer (32 words) Buffer enhanced factory program Main block (64 Kwords) Bank (8 Mbits) Program/erase cycles (per block) Blank Check Min Typ Typical after 100kW/E cycles Max Parameter block (16 Kword) Erase VPP = VPPH M58LR128KT, M58LR128KB, M58LR256KT, Main blocks 1000 cycles Parameter blocks 2500 cycles Main blocks 16 ms Parameter blocks 4 ms 1. TA = –30 to 85 °C; VDD = 1.7 V to 2 V; VDDQ = 1.7 V to 2 V. 2. Values are liable to change with the external system-level overhead (command sequence and Status Register polling execution). 3. Excludes the time needed to execute the command sequence. 4. This is an average value on the entire device. 60/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB 11 Maximum ratings Maximum ratings Stressing the device above the rating listed in the Table 19: Absolute maximum ratings may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to Absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the Numonyx SURE program and other relevant quality documents. Table 19. Absolute maximum ratings Value Symbol Parameter Unit Min Max Ambient operating temperature –30 85 °C TBIAS Temperature under bias –30 85 °C TSTG Storage temperature –65 125 °C VIO Input or output voltage –0.5 VDDQ + 0.6 V VDD Supply voltage –0.2 2.5 V Input/output supply voltage –0.2 2.5 V Program voltage –0.2 10 V Output short circuit current 100 mA Time for VPP at VPPH 100 hours TA VDDQ VPP IO tVPPH 61/120 DC and AC parameters 12 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters This section summarizes the operating measurement conditions and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables in this section are derived from tests performed under the measurement conditions summarized in Table 20: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 20. Operating and AC measurement conditions M58LRxxxKT/B Parameter 70 ns 85 ns Min Max Min Max VDD supply voltage 1.7 2.0 1.7 2.0 V VDDQ supply voltage 1.7 2.0 1.7 2.0 V VPP supply voltage (factory environment) 8.5 9.5 8.5 9.5 V VPP supply voltage (application environment) –0.4 VDDQ+0.4 –0.4 VDDQ+0.4 V Ambient operating temperature –30 85 –30 85 °C Load capacitance (CL) 30 Input rise and fall times Input and output timing ref. voltages Figure 9. 30 5 Input pulse voltages pF 5 ns 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 V AC measurement I/O waveform VDDQ VDDQ/2 0V AI06161 62/120 Unit M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 10. AC measurement load circuit VDDQ VDDQ VDD 16.7kΩ DEVICE UNDER TEST CL 0.1µF 16.7kΩ 0.1µF CL includes JIG capacitance Table 21. Symbol CIN COUT AI06162 Capacitance(1) Parameter Input capacitance Output capacitance Test condition Min Max Unit VIN = 0 V 6 8 pF VOUT = 0 V 8 12 pF 1. Sampled only, not 100% tested. 63/120 DC and AC parameters Table 22. Symbol M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC characteristics - currents Parameter ILI Input leakage current ILO Output leakage current Test condition Supply current Asynchronous read (f = 5 MHz) Supply current Synchronous read (f = 54 MHz) IDD1 Supply current Synchronous read (f = 66 MHz) 128 Mbit IDD2 Supply current (reset) IDD3 Supply current (standby) IDD4 Supply current (automatic standby) 256 Mbit 128 Mbit 256 Mbit Supply current (program) IDD5(1) Supply current (erase) IDD6(1),(2) IDD7(1) Supply current (dual operations) Supply current program/erase suspended (standby) 128 Mbit 256 Mbit VPP supply current (program) IPP1(1) VPP supply current (erase) 64/120 Typ Max Unit 0 V ≤ VIN ≤ VDDQ ±1 μA 0 V ≤ VOUT ≤ VDDQ ±1 μA E = VIL, G = VIH 13 15 mA 4 word 18 20 mA 8 word 20 22 mA 16 word 25 27 mA Continuous 28 30 mA 4 word 20 22 mA 8 word 22 24 mA 16 word 27 29 mA Continuous 30 32 mA 22 70 70 110 E = VDD ± 0.2 V K=VSS 22 70 70 110 E = VIL, G = VIH 22 50 μA VPP = VPPH 10 30 mA VPP = VDD 20 35 mA VPP = VPPH 10 30 mA VPP = VDD 20 35 mA Program/erase in one bank, asynchronous read in another bank 33 50 mA Program/erase in one bank, synchronous read (continuous f = 66 MHz) in another bank 50 67 mA 22 70 70 110 VPP = VPPH 2 5 mA VPP = VDD 0.2 5 μA VPP = VPPH 2 5 mA VPP = VDD 0.2 5 μA RP = VSS ± 0.2 V E = VDD ± 0.2 V K=VSS μA μA μA M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 22. Symbol DC and AC parameters DC characteristics - currents Parameter Test condition Typ Max Unit IPP2 VPP supply current (read) VPP ≤ VDD 0.2 5 μA IPP3(1) VPP supply current (standby) VPP ≤ VDD 0.2 5 μA 1. Sampled only, not 100% tested. 2. VDD dual operation current is the sum of read and program or erase currents. Table 23. Symbol DC characteristics - voltages Parameter Test condition Min Typ Max Unit VIL Input Low voltage 0 0.4 V VIH Input High voltage VDDQ –0.4 VDDQ + 0.4 V VOL Output Low voltage IOL = 100 μA 0.1 V VOH Output High voltage IOH = –100 μA VDDQ –0.1 VPP1 VPP Program voltage-logic Program, erase 1.3 1.8 3.3 V VPPH VPP Program voltage factory Program, erase 8.5 9.0 9.5 V VPPLK Program or erase lockout 0.4 V VLKO VDD lock voltage 1 V V 65/120 66/120 Hi-Z Hi-Z tELLH tLLLH tAVLH tGLTV tELQX tELTV tGLQV tLHAX tGLQX tELQV tLLQV tAVQV VALID tEHQZ tEHQX tEHTZ tGHQZ tGHQX tAXQX VALID VALID tGHTZ Notes: 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 2. Latch Enable, L, can be kept Low (also at board level) when the Latch Enable function is not required or supported. 3. Write Enable, W, is High, WAIT is active Low. WAIT(3) DQ0-DQ15 G E L(2) A0-Amax(1) tAVAV AI14016 DC and AC parameters M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 11. Asynchronous random access read AC waveforms Hi-Z tELTV tELQX tGLQV tGLQX tELQV tLLQV Valid Address Latch tELLH tLLLH tAVLH VALID ADDRESS tAVAV Enabled Outputs tLHGL tLHAX VALID DATA VALID DATA VALID ADDRESS Valid Data VALID DATA tAVQV1 VALID ADDRESS VALID ADDRESS Notes: 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 2. WAIT is active Low. DQ0-DQ15 WAIT (2) G E L A0-A1 A2-Amax(1) VALID DATA VALID ADDRESS AI14017 Standby M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 12. Asynchronous page read AC waveforms 67/120 DC and AC parameters Table 24. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Asynchronous read AC characteristics M58LRxxxKT/B Symbol Alt Read Timings Unit 70 85 tAVAV tRC Address Valid to Next Address Valid Min 70 85 ns tAVQV tACC Address Valid to Output Valid (Random) Max 70 85 ns tAVQV1 tPAGE Address Valid to Output Valid (page) Max 20 25 ns tAXQX(1) tOH Address Transition to Output Transition Min 0 0 ns Chip Enable Low to Wait Valid Max 11 14 ns tELTV tELQV(2) tCE Chip Enable Low to Output Valid Max 70 85 ns tELQX(1) tLZ Chip Enable Low to Output Transition Min 0 0 ns Chip Enable High to Wait Hi-Z Max 11 14 ns tEHTZ tEHQX(1) tOH Chip Enable High to Output Transition Min 2 2 ns (1) tHZ Chip Enable High to Output Hi-Z Max 14 14 ns tGLQV(2) tOE Output Enable Low to Output Valid Max 20 20 ns tGLQX(1) tOLZ Output Enable Low to Output Transition Min 0 0 ns Output Enable Low to Wait Valid Max 14 14 ns tEHQZ tGLTV (1) tOH Output Enable High to Output Transition Min 2 2 ns tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 14 14 ns Output Enable High to Wait Hi-Z Max 14 14 ns tGHQX tGHTZ Latch Timings Parameter tAVLH tAVADVH Address Valid to Latch Enable High Min 7 7 ns tELLH tELADVH Chip Enable Low to Latch Enable High Min 10 10 ns tLHAX tADVHAX Latch Enable High to Address Transition Min 7 7 ns Min 7 7 ns Max 70 85 ns tLLLH tLLQV tADVLADVH Latch Enable Pulse Width tADVLQV Latch Enable Low to Output Valid (Random) 1. Sampled only, not 100% tested. 2. G may be delayed by up to tELQV - tGLQV after the falling edge of E without increasing tELQV. 68/120 Hi-Z tLLLH Address Latch tELTV tKHAX tAVKH tLLKH tAVLH VALID ADDRESS X Latency tGLTV tGLQX Note 2 Note 1 VALID Valid Data Flow tKHTV tKHQV VALID Note 2 tKHTX tKHQX VALID Boundary Crossing Note 2 NOT VALID Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. 4. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge of K is the rising one. 5. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. WAIT G E K(4) L tELKH Hi-Z A0-Amax(5) DQ0-DQ15 Data Valid tGHQZ tGHQX AI14018 Standby tEHTZ tEHQZ tEHQX tEHEL VALID M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 13. Synchronous burst read AC waveforms 69/120 DC and AC parameters M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 14. Single synchronous read AC waveforms A0-Amax(1) VALID ADDRESS tAVKH L tLLKH K(2) tELKH tKHQV tELQV E tGLQV tGLQX G tELQX DQ0-DQ15 Hi-Z VALID tGLTV WAIT(3) tGHTZ tKHTV Hi-Z Ai14019 1. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. 2. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. 3. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 70/120 tELKH tLLLH tELTV tKHAX tAVKH tLLKH tAVLH VALID ADDRESS tGLTV tGLQV tGLQX Note 1 tKHQV VALID VALID tGHTZ tGHQZ Note 3 VALID VALID tGHQX tEHEL tEHQZ tEHQX Notes 1. The number of clock cycles to be inserted depends on the X latency set in the Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. The CLOCK signal can be held high or low 4. Address latched and data output on the rising clock edge. Either the rising or the falling edge of the clock signal, K, can be configured as the active edge. Here, the active edge is the rising one. 5. Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. WAIT(2) G E K(4) L Hi-Z Hi-Z A0-Amax(5) DQ0-DQ15 AI14020 tEHTZ M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 15. Synchronous burst read suspend AC waveforms 71/120 DC and AC parameters M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 16. Clock input AC waveform tKHKL tKHKH tf tr tKLKH AI06981 Table 25. Synchronous read AC characteristics(1) (2) M58LRxxxKT/B Clock Specifications Synchronous Read Timings Symbol Alt Parameter Unit 85 tAVKH tAVCLKH Address Valid to Clock High Min 7 7 ns tELKH tELCLKH Chip Enable Low to Clock High Min 7 7 ns tELTV Chip Enable Low to Wait Valid Max 14 14 ns tEHEL Chip Enable Pulse Width (subsequent synchronous reads) Min 14 14 ns tEHTZ Chip Enable High to Wait Hi-Z Max 14 14 ns tKHAX tCLKHAX Clock High to Address Transition Min 7 7 ns tKHQV tKHTV tCLKHQV Clock High to Output Valid Clock High to WAIT Valid Max 11 14 ns tKHQX tKHTX tCLKHQX Clock High to Output Transition Clock High to WAIT Transition Min 3 3 ns tLLKH tADVLCLKH Latch Enable Low to Clock High Min 7 7 ns tKHKH tCLK 18.5 ns Clock Period (f = 54 MHz) Clock Period (f = 66 MHz) Min 15 ns tKHKL tKLKH Clock High to Clock Low Clock Low to Clock High Min 4.5 4.5 ns tf tr Clock Fall or Rise Time Max 3 3 ns 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 24: Asynchronous read AC characteristics. 72/120 70 tWHDX CONFIRM COMMAND OR DATA INPUT tVPHWH tWHVPL tWHWPL tELKV tWHEL tWHGL tWHAV tWHAX CMD or DATA VALID ADDRESS tAVWH tWPHWH tWHWL tWHEH tWHLL tWLWH tLHAX COMMAND tLLLH SET-UP COMMAND tDVWH tGHWL tELWL tELLH tAVLH BANK ADDRESS Note: Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. K VPP WP DQ0-DQ15 W G E L A0-Amax(1) tAVAV Ai14021 tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV VALID ADDRESS PROGRAM OR ERASE M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 17. Write AC waveforms, Write Enable controlled 73/120 DC and AC parameters M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Write AC characteristics, Write Enable controlled(1) Table 26. M58LRxxxKT/B Symbol Alt tAVAV 70 85 ns tAVLH Address Valid to Latch Enable High Min 7 7 ns tAVWH(2) Address Valid to Write Enable High Min 45 45 ns Data Valid to Write Enable High Min 45 45 ns Chip Enable Low to Latch Enable High Min 10 10 ns Chip Enable Low to Write Enable Low Min 0 0 ns tELQV Chip Enable Low to Output Valid Min 70 85 ns tELKV Chip Enable Low to Clock Valid Min 7 7 ns tGHWL Output Enable High to Write Enable Low Min 17 17 ns tLHAX Latch Enable High to Address Transition Min 7 7 ns tLLLH Latch Enable Pulse Width Min 7 7 ns Write Enable High to Address Valid Min 0 0 ns tELWL Write Enable Controlled Timings 85 Min tDS tELLH tCS tWHAV(2) tWHAX(2) tAH Write Enable High to Address Transition Min 0 0 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns Write Enable High to Chip Enable Low Min 25 25 ns tWHGL Write Enable High to Output Enable Low Min 0 0 ns tWHLL(3) Write Enable High to Latch Enable Low Min 25 25 ns tWHWL tWPH Write Enable High to Write Enable Low Min 25 25 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns tQVVPL Output (Status Register) Valid to VPP Low Min 0 0 ns tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 0 ns VPP High to Write Enable High Min 200 200 ns tWHVPL Write Enable High to VPP Low Min 200 200 ns tWHWPL Write Enable High to Write Protect Low Min 200 200 ns tWPHWH Write Protect High to Write Enable High Min 200 200 ns tWHEL Protection Timings Unit 70 Address Valid to Next Address Valid tDVWH tWC Parameter (3) tVPHWH tVPS 1. Sampled only, not 100% tested. 2. Meaningful only if L is always kept low. 3. tWHEL and tWHLLhave this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL and tWHLL is 0 ns. 74/120 tGHEL tELEH tLHAX COMMAND SET-UP COMMAND tDVEH tLLLH tELLH tWLEL tAVLH BANK ADDRESS tEHDX tEHEL tEHWH CMD or DATA tEHAX CONFIRM COMMAND OR DATA INPUT tVPHEH tWPHEH tAVEH VALID ADDRESS Note: Amax is equal to A22 in the M58LR128KT/B and, to A23 in the M58LR256KT/B. K VPP WP DQ0-DQ15 E G W L A0-Amax(1) tAVAV tEHVPL tEHWPL tELKV tWHEL tEHGL tQVVPL Ai14022 tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV VALID ADDRESS PROGRAM OR ERASE M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 18. Write AC waveforms, Chip Enable controlled 75/120 DC and AC parameters M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Write AC characteristics, Chip Enable controlled(1) Table 27. M58LRxxxKT/B Symbol Alt Chip Enable Controlled Timings tAVAV Unit 70 85 Address Valid to Next Address Valid Min 70 85 ns tAVEH Address Valid to Chip Enable High Min 45 45 ns tAVLH Address Valid to Latch Enable High Min 7 7 ns tDVEH tDS Data Valid to Chip Enable High Min 45 45 ns tEHAX tAH Chip Enable High to Address Transition Min 0 0 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 25 25 ns Chip Enable High to Output Enable Low Min 0 0 ns Chip Enable High to Write Enable High Min 0 0 ns Chip Enable Low to Clock Valid Min 7 7 ns Chip Enable Low to Chip Enable High Min 45 45 ns tELLH Chip Enable Low to Latch Enable High Min 10 10 ns tELQV Chip Enable Low to Output Valid Min 70 85 ns tGHEL Output Enable High to Chip Enable Low Min 17 17 ns tLHAX Latch Enable High to Address Transition Min 7 7 ns tLLLH Latch Enable Pulse Width Min 7 7 ns Write Enable High to Chip Enable Low Min 25 25 ns Write Enable Low to Chip Enable Low Min 0 0 ns tEHVPL Chip Enable High to VPP Low Min 200 200 ns tEHWPL Chip Enable High to Write Protect Low Min 200 200 ns tQVVPL Output (Status Register) Valid to VPP Low Min 0 0 ns tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 0 ns VPP High to Chip Enable High Min 200 200 ns Write Protect High to Chip Enable High Min 200 200 ns tEHGL tEHWH tCH tELKV tELEH tWHEL tCP (2) tWLEL Protection Timings tWC Parameter tVPHEH tWPHEH tCS tVPS 1. Sampled only, not 100% tested. 2. tWHEL has this value when reading in the targeted bank or when reading following a Set Configuration Register command. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing any command and to delay the first read to any address after issuing a Set Configuration Register command. If the first read after the command is a Read Array operation in a different bank and no changes to the Configuration Register have been issued, tWHEL is 0ns. 76/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB DC and AC parameters Figure 19. Reset and power-up AC waveforms tPHWL tPHEL tPHGL tPHLL W, E, G, L tPLWL tPLEL tPLGL tPLLL RP tVDHPH tPLPH VDD, VDDQ Power-Up Reset AI06976 Table 28. Symbol Reset and power-up AC characteristics Parameter tPLWL tPLEL tPLGL tPLLL Reset Low to Write Enable Low Reset Low to Chip Enable Low, Reset Low to Output Enable Low, Reset Low to Latch Enable Low tPHWL tPHEL tPHGL tPHLL tPLPH(1),(2) tVDHPH(3) Test condition M58LRxxxKT/B Unit During program Min 25 μs During erase Min 25 μs Other conditions Min 80 ns Reset High to Write Enable Low Reset High to Chip Enable Low Reset High to Output Enable Low Reset High to Latch Enable Low Min 30 ns RP pulse width Min 50 ns Supply voltages High to Reset High Min 300 μs 1. The device Reset is possible but not guaranteed if tPLPH < 50 ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP to allow proper CPU initialization during power-up or Reset. 77/120 Package mechanical 13 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Package mechanical To meet environmental requirements, Numonyx offers the M58LR128KT/B in ECOPACK® packages. These packages have a lead-free, second-level interconnect. The category of second-level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an Numonyx trademark. Figure 20. VFBGA56 7.7 x 9 mm - 8 x 7 active ball array, 0.75 mm pitch, bottom view package outline D D1 FD FE E SD E1 ddd BALL "A1" e e b A A2 A1 BGA-Z38 1. Drawing is not to scale. 78/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 29. Package mechanical VFBGA56 7.7 x 9 mm - 8 x 7 ball array, 0.75 mm pitch, package mechanical data Millimeters Inches Symbol Typ Min Max A Typ Min Max 1.000 A1 0.0394 0.200 0.0079 A2 0.660 0.0260 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 7.700 7.600 7.800 0.3031 0.2992 0.3071 D1 5.250 – – 0.2067 – – ddd 0.080 0.0031 e 0.750 – – 0.0295 – – E 9.000 8.900 9.100 0.3543 0.3504 0.3583 E1 4.500 – – 0.1772 – – FD 1.225 – – 0.0482 – – FE 2.250 – – 0.0886 – – SD 0.375 – – 0.0148 – – Figure 21. TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, bottom view package outline D D1 e SE E E2 E1 b BALL "A1" ddd FE FE1 FD SD A2 A A1 BGA-Z42 Figure 22. Drawing is not to scale. 79/120 Package mechanical M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 30. TFBGA88 8 x 10 mm - 8 x 10 ball array, 0.8 mm pitch, package mechanical data Millimeters Inches Symbol Typ Min A Typ Min 1.200 A1 Max 0.0472 0.200 0.0079 A2 0.850 0.0335 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 8.000 7.900 8.100 0.3150 0.3110 0.3189 D1 5.600 0.2205 ddd 80/120 Max 0.100 9.900 E 10.000 E1 7.200 0.2835 E2 8.800 0.3465 e 0.800 FD 1.200 0.0472 FE 1.400 0.0551 FE1 0.600 0.0236 SD 0.400 0.0157 SE 0.400 0.0157 - 10.100 0.0039 - 0.3937 0.0315 0.3898 0.3976 - - M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Package mechanical Figure 23. VFBGA79 9x11mm - 0.75 pitch -package outline (1) S1 A1 Index Mark A1 Index Mark D 1 2 3 4 5 6 7 8 9 10 11 12 13 A B C D 13 12 11 10 9 8 7 E E F G 6 5 4 3 2 1 S2 A B C D E F G b Top View - Ball Side Down e Bottom View - Ball Side Up A1 A2 A Seating Y Plane Side View 1. Drawing not to scale Table 31. VFBGA79 9x11mm - 0.75 mm pitch, package mechanical data Millimeters Inches Symbol Min Typ A A1 Max Min Typ 1.000 0.150 A2 Max 0.0394 0.0059 0.665 0.0262 b 0.325 0.375 0.425 0.0128 0.0148 0.0167 D 10.900 11.000 11.100 0.4291 0.4331 0.4370 E 8.900 9.000 9.100 0.3504 0.3543 0.3583 e 0.750 0.0295 N 79 79 Y 0.100 0.0039 S1 0.900 1.000 1.100 0.0354 0.0394 0.0433 S2 2.150 2.250 2.350 0.0846 0.0886 0.0925 81/120 Part numbering 14 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Part numbering Table 32. Ordering information scheme Example: M58LR128KT 70 ZB 5 E Device type M58 Architecture L = multilevel, multiple bank, burst mode Operating voltage R = VDD = 1.7 V to 2.0 V, VDDQ = 1.7 V to 2.0 V Density 128 = 128 Mbit (x16) 256 = 256 Mbit (x16) Technology K = 65 nm technology Parameter location T = top boot B = bottom boot Speed 70 = 70 ns 85 = 85 ns Package ZB = VFBGA56, 7.7 x 9 mm, 0.75 mm pitch(1) ZC = VFBGA79, 9 x 11 mm, 0.75 mm pitch ZQ = TFBGA88, 8 x 10mm, 0.8 mm pitch Temperature range 5 = –30 to 85 °C Packing option E = ECOPACK® package, standard packing F = ECOPACK® package, tape and reel packing 1. The M58LR128KT/B are available in the ZB package, while the M58LR256KT/B are available M58LR256KT/B are available in the ZC and ZQ package. Devices are shipped from the factory with the memory content bits erased to ’1’. 82/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Part numbering For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact the Numonyx sales office nearest to you. 83/120 Block address tables Appendix A M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Block address tables The following set of equations can be used to calculate a complete set of block addresses for the M58LRxxxKT/B using the information contained in Tables 36 to 44. To calculate the block base address from the block number: First it is necessary to calculate the bank number and the block number offset. This can be achieved using the following formulas: Bank_Number = (Block_Number − 3) / 8 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 8), If Bank_Number= 0, the block base address can be directly read from Tables 36 and 42 (parameter bank block addresses) in the address range column, in the row that corresponds to the given block number. Otherwise: Block_Base_Address = Bank_Base_Address + Block_Base_Address_Offset To calculate the bank number and the block number from the block base address: If the address is in the range of the parameter bank, the Bank Number is 0 and the Block Number can be directly read from Tables 36 and 42 (parameter bank Block Addresses), in the Block Number column, in the row that corresponds to the address given. Otherwise, the Block Number can be calculated using the formulas below: For the top configuration (M58LR256KT and M58LR128KT): Block_Number = ((NOT address) / 216) + 3 For the bottom configuration (M58LR256KB and M58LR128KB): Block_Number = (address / 216) + 3 For both configurations the Bank Number and the Block Number Offset can be calculated using the following formulas: Bank_Number = (Block_Number − 3) / 8 Block_Number_Offset = Block_Number − 3 − (Bank_Number x 8) 84/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 33. Block address tables M58LR128KT - Parameter bank block addresses Block number Size (Kwords) Address range 0 16 7FC000-7FFFFF 1 16 7F8000-7FBFFF 2 16 7F4000-7F7FFF 3 16 7F0000-7F3FFF 4 64 7E0000-7EFFFF 5 64 7D0000-7DFFFF 6 64 7C0000-7CFFFF 7 64 7B0000-7BFFFF 8 64 7A0000-7AFFFF 9 64 790000-79FFFF 10 64 780000-78FFFF Table 34. M58LR128KT - main bank base addresses Bank number(1) Block numbers Bank base address 1 11-18 70 0000 2 19-26 68 0000 3 27-34 60 0000 4 35-42 58 0000 5 43-50 50 0000 6 51-58 48 0000 7 59-66 40 0000 8 67-74 38 0000 9 75-82 30 0000 10 83-90 28 0000 11 91-98 20 0000 12 99-106 18 0000 13 107-114 10 0000 14 115-122 08 0000 15 123-130 00 0000 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). 85/120 Block address tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 35. M58LR128KT - block addresses in main banks Block number offset Block base address offset 0 07 0000 1 06 0000 2 05 0000 3 04 0000 4 03 0000 5 02 0000 6 01 0000 7 00 0000 Table 36. 86/120 M58LR256KT - parameter bank block addresses Block number Size (Kwords) Address range 0 16 FFC000-FFFFFF 1 16 FF8000-FFBFFF 2 16 FF4000-FF7FFF 3 16 FF0000-FF3FFF 4 64 FE0000-FEFFFF 5 64 FD0000-FDFFFF 6 64 FC0000-FCFFFF 7 64 FB0000-FBFFFF 8 64 FA0000-FAFFFF 9 64 F90000-F9FFFF 10 64 F80000-F8FFFF 11 64 F70000-F7FFFF 12 64 F60000-F6FFFF 13 64 F50000-F5FFFF 14 64 F40000-F4FFFF 15 64 F30000-F3FFFF 16 64 F20000-F2FFFF 17 64 F10000-F1FFFF 18 64 F00000-F0FFFF M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 37. Block address tables M58LR256KT - main bank base addresses Bank number(1) Block numbers Bank base address 1 19-34 E00000 2 35-50 D00000 3 51-66 C00000 4 67-82 B00000 5 83-98 A00000 6 99-114 900000 7 115-130 800000 8 131-146 700000 9 147-162 600000 10 163-178 500000 11 179-194 400000 12 195-210 300000 13 211-226 200000 14 227-242 100000 15 243-258 000000 1. There are two Bank Regions: Bank Region 1 contains all the banks that are made up of main blocks only; Bank Region 2 contains the banks that are made up of the parameter and main blocks (parameter bank). Table 38. M58LR256KT - block addresses in main banks Block number offset Block base address offset 0 0F0000 1 0E0000 2 0D0000 3 0C0000 4 0B0000 5 0A0000 6 090000 7 080000 8 070000 9 060000 10 050000 11 040000 12 030000 13 020000 14 010000 15 000000 87/120 Block address tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 39. M58LR128KB - parameter bank block addresses Block number Size (Kwords) Address range 10 64 070000-07FFFF 9 64 060000-06FFFF 8 64 050000-05FFFF 7 64 040000-04FFFF 6 64 030000-03FFFF 5 64 020000-02FFFF 4 64 010000-01FFFF 3 16 00C000-00FFFF 2 16 008000-00BFFF 1 16 004000-007FFF 0 16 000000-003FFF Table 40. M58LR128KB - main bank base addresses Bank number(1) Block numbers Bank base address 15 123-130 78 0000 14 115-122 70 0000 13 107-114 68 0000 12 99-106 60 0000 11 91-98 58 0000 10 83-90 50 0000 9 75-82 48 0000 8 67-74 40 0000 7 59-66 38 0000 6 51-58 30 0000 5 43-50 28 0000 4 35-42 20 0000 3 27-34 18 0000 2 19-26 10 0000 1 11-18 08 0000 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). 88/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 41. Block address tables M58LR128KB - block addresses in main banks Block number offset Block base address offset 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000 Table 42. M58LR256KB - parameter bank block addresses Block number Size (Kwords) Address range 18 64 0F0000-0FFFFF 17 64 0E0000-0EFFFF 16 64 0D0000-0DFFFF 15 64 0C0000-0CFFFF 14 64 0B0000-0BFFFF 13 64 0A0000-0AFFFF 12 64 090000-09FFFF 11 64 080000-08FFFF 10 64 070000-07FFFF 9 64 060000-06FFFF 8 64 050000-05FFFF 7 64 040000-04FFFF 6 64 030000-03FFFF 5 64 020000-02FFFF 4 64 010000-01FFFF 3 16 00C000-00FFFF 2 16 008000-00BFFF 1 16 004000-007FFF 0 16 000000-003FFF 89/120 Block address tables M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 43. M58LR256KB - main bank base addresses Bank number Block numbers Bank base address 15 243-258 F00000 14 227-242 E00000 13 211-226 D00000 12 195-210 C00000 11 179-194 B00000 10 163-178 A00000 9 147-162 900000 8 131-146 800000 7 115-130 700000 6 99-114 600000 5 83-98 500000 4 67-82 400000 3 51-66 300000 2 35-50 200000 1 19-34 100000 1. There are two Bank Regions: Bank Region 2 contains all the banks that are made up of main blocks only; Bank Region 1 contains the banks that are made up of the parameter and main blocks (parameter bank). Table 44. 90/120 M58LR256KB - block addresses in main banks Block number offset Block base address offset 15 0F0000 14 0E0000 13 0D0000 12 0C0000 11 0B0000 10 0A0000 9 090000 8 080000 7 070000 6 060000 5 050000 4 040000 3 030000 2 020000 1 010000 0 000000 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Appendix B Common Flash interface Common Flash interface The common Flash interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the read CFI Query command is issued the device enters CFI query mode and the data structure is read from the memory. Tables 45, 46, 47, 48, 49, 50, 51, 52, 53 and 54 show the addresses used to retrieve the data. The query data is always presented on the lowest order data outputs (DQ0-DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Figure 6: Protection Register memory map). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by Numonyx. Issue a Read Array command to return to read mode. Table 45. Query structure overview Offset Sub-section name Description 000h Reserved Reserved for algorithm-specific information 010h CFI query identification string Command set ID and algorithm data offset 01Bh System interface information Device timing and voltage information 027h Device geometry definition Flash device layout P Primary algorithm-specific extended query table Additional information specific to the primary algorithm (optional) A Alternate algorithm-specific extended query table Additional information specific to the alternate algorithm (optional) Security code area Lock Protection Register Unique device number and User programmable OTP 080h 1. The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 46, 47, 48 and 49. Query data is always presented on the lowest order data outputs. 91/120 Common Flash interface Table 46. 92/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB CFI query identification string Offset Sub-section Name 000h 0020h 001h 88C4h 88C5h 880Dh 880Eh 002h-00Fh Reserved 010h 0051h 011h 0052h 012h 0059h 013h 0001h 014h 0000h 015h offset = P = 000Ah 016h 0001h 017h 0000h 018h 0000h 019h value = A = 0000h 01Ah 0000h Description Value Manufacturer code Device code Numonyx M58LR128KT M58LR128KB M58LR256KT M58LR256KB Top Bottom Top Bottom Reserved "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 49) p = 10Ah Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA Address for Alternate Algorithm extended Query table NA M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 47. Common Flash interface CFI query system interface information Offset Data 01Bh 0017h VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1.7V 01Ch 0020h VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 2V 01Dh 0085h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 8.5V 01Eh 0095h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 9.5V 01Fh 0004h Typical time-out per single byte/word program = 2n μs 16μs 020h 0009h Description Value n Typical time-out for Buffer Program = 2 μs 512μs 021h 000Ah Typical time-out per individual block erase = 022h 0000h Typical time-out for full chip erase = 2n ms 023h 024h 0004h 0004h 2n ms NA n Maximum time-out for word program = 2 times typical Maximum time-out for Buffer Program = 2n 1s 256μs times typical 8192μs n 025h 0002h Maximum time-out per individual block erase = 2 times typical 4s 026h 0000h Maximum time-out for chip erase = 2n times typical NA 93/120 Common Flash interface Table 48. Offset 027h TOP DEVICES Data 0018h Description M58LR128KT/B device size = 2n in number of bytes n Value 16 Mbytes M58LR256KT/B device size = 2 in number of bytes 028h 029h 0001h 0000h Flash Device Interface Code description 02Ah 02Bh 0006h 0000h Maximum number of bytes in multi-byte program or page = 2n 02Ch 0002h Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions 007Eh 0000h M58LR128KT/B Erase Block Region 1 Information Number of identical-size erase blocks = 007Eh+1 127 00FEh 0000h M58LR256KT/B Erase Block Region 1 Information Number of identical-size erase blocks = 00FEh+1 255 02Fh 030h 0000h 0002h Erase Block Region 1 Information Block size in Region 1 = 0200h * 256 byte 031h 032h 0003h 0000h Erase Block Region 2 Information Number of identical-size erase blocks = 0003h+1 033h 034h 0080h 0000h Erase Block Region 2 Information Block size in Region 2 = 0080h * 256 byte 035h 038h BOTTOM DEVICES Device geometry definition 0019h 02Dh 02Eh Reserved Reserved for future erase block region information 32 Mbytes x16 Async. 64 bytes 2 128 Kbyte 4 32 Kbyte NA 02Dh 02Eh 0003h 0000h Erase Block Region 1 Information Number of identical-size erase block = 0003h+1 02Fh 030h 0080h 0000h Erase Block Region 1 Information Block size in Region 1 = 0080h * 256 bytes 007Eh 0000h M58LR128KT/B Erase Block Region 2 Information Number of identical-size erase block = 007Eh+1 127 00FEh 0000h M58LR256KT/B Erase Block Region 2 Information Number of identical-size erase block = 00FEh+1 255 0000h 0002h Erase Block Region 2 Information Block size in Region 2 = 0200h * 256 bytes 031h 032h 033h 034h 035h 038h 94/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Reserved Reserved for future erase block region information 4 32 Kbytes 128 Kbytes NA M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 49. Common Flash interface Primary algorithm-specific extended query table Offset Data (P)h = 10Ah 0050h 0052h Description Value "P" Primary Algorithm extended Query table unique ASCII string “PRI” 0049h "R" "I" (P+3)h =10Dh 0031h Major version number, ASCII "1" (P+4)h = 10Eh 0033h Minor version number, ASCII "3" (P+5)h = 10Fh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. 0003h (P+7)h = 111h (P+8)h = 112h 0000h 0000h bit 0 Chip Erase supported(1 = Yes, 0 = No) bit 1 Erase Suspend supported(1 = Yes, 0 = No) bit 2 Program Suspend supported(1 = Yes, 0 = No) bit 3 Legacy Lock/Unlock supported(1 = Yes, 0 = No) bit 4 Queued Erase supported(1 = Yes, 0 = No) bit 5 Instant individual block locking supported(1 = Yes, 0 = No) bit 6 Protection bits supported(1 = Yes, 0 = No) bit 7 Page mode read supported(1 = Yes, 0 = No) bit 8 Synchronous read supported(1 = Yes, 0 = No) bit 9 Simultaneous operation supported(1 = Yes, 0 = No) bit 10 to 31 Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Supported Functions after Suspend Read Array, Read Status Register and CFI Query (P+9)h = 113h 0001h (P+A)h = 114h 0003h (P+B)h = 115h 0000h bit 0 Program supported after Erase Suspend (1 = Yes, 0 = No) bit 7 to 1 Reserved; undefined bits are ‘0’ Yes Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’ Yes Yes 95/120 Common Flash interface Table 49. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Primary algorithm-specific extended query table Offset Data Description Value VDD Logic Supply Optimum Program/Erase voltage (highest performance) (P+C)h = 116h 0018h 1.8V bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV VPP Supply Optimum Program/Erase voltage (P+D)h = 117h Table 50. bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 mV Offset Data (P+E)h = 118h 0002h (P+F)h = 119h (P+12)h = 11Ch 0080h Protection Field 1: Protection Description 0000h Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address 0003h Bits 16-23 2n bytes in factory pre-programmed region 0003h Bits 24-31 2n bytes in user programmable region (P+13)h = 11Dh 0089h (P+ 11)h = 11Bh (P+14)h = 11Eh 0000h (P+15)h = 11Fh 0000h (P+16)h = 120h 0000h (P+17)h = 121h 0000h (P+18)h = 122h 0000h (P+19)h = 123h 0000h (P+1A)h = 124h 0010h (P+1B)h = 125h 0000h (P+1C)h = 126h 0004h Table 51. 9V Protection Register information (P+10)h = 11Ah Description Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. Value 2 80h 00h 8 bytes 8 bytes 89h Protection Register 2: Protection Description Bits 0-31 protection register address Bits 32-39 n number of factory programmed regions (lower byte) Bits 40-47 n number of factory programmed regions (upper byte) Bits 48-55 2n bytes in factory programmable region Bits 56-63 n number of user programmable regions (lower byte) Bits 64-71 n number of user programmable regions (upper byte) Bits 72-79 2n bytes in user programmable region 00h 00h 00h 0 0 0 16 0 16 Burst read information Offset 96/120 0090h Data Description (P+1D)h = 127h Page-mode read capability bits 0-7 n’ such that 2n HEX value represents the number of 0003h read-page bytes. See offset 0028h for device word width to determine page-mode data output width. (P+1E)h = 128h 0004h Number of synchronous mode read configuration fields that follow. Value 8 bytes 4 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 51. Common Flash interface Burst read information Offset Data Description Value (P+1F)h = 129h Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 n’ such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear 0001h bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 0028h for word width to determine the burst data output width. 4 (P+20)h = 12Ah 0002h Synchronous mode read capability configuration 2 8 (P-21)h = 12Bh (P+22)h = 12Ch 0003h Synchronous mode read capability configuration 3 0007h Synchronous mode read capability configuration 4 16 Table 52. Cont. Bank and erase block region information(1) (2) Flash memory (top) Flash memory (bottom) Description Offset Data Offset Data (P+23)h = 12Dh 02h (P+23)h = 12Dh 02h Number of Bank Regions within the device 1. The variable P is a pointer that is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 34, Table 37, Table 40 and Table 43. Table 53. Bank and erase block region 1 information Flash memory (top) Flash memory (bottom) Description Offset(1) Data Offset(1) Data (P+24)h = 12Eh 0Fh (P+24)h = 12Eh 01h (P+25)h = 12Fh 00h (P+25)h = 12Fh 00h (P+26)h = 130h (P+27)h = 131h 11h 00h (P+26)h = 130h (P+27)h = 131h Number of identical banks within Bank Region 1 11h Number of program or erase operations allowed in Bank Region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 97/120 Common Flash interface Table 53. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Bank and erase block region 1 information (continued) Flash memory (top) Offset(1) (P+28)h = 132h (P+29)h = 133h (P+2A)h = 134h Data Flash memory (bottom) Offset(1) 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+29)h = 133h 02h Types of erase block regions in Bank Region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region(2) 07h(3) (P+2A)h = 134h 0Fh(4) 03h 00h 01h (P+28)h = 132h (P+2B)h = 135h 00h (P+2B)h = 135h 00h (P+2C)h = 136h 00h (P+2C)h = 136h 80h (P+2D)h = 137h 02h (P+2D)h = 137h 00h (P+2E)h = 138h 64h (P+2E)h = 138h 64h (P+2F)h = 139h 00h (P+2F)h = 139h 00h (P+30)h = 13Ah (P+31)h = 13Bh 01h 03h (P+30)h = 13Ah (P+31)h = 13Bh (P+32)h = 13Ch 98/120 Description Data Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n x 256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 1) Minimum block erase cycles x 1000 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 03h Bank Region 1 (Erase Block Type 1): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted(5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 06h(3) Bank Region 1 Erase Block Type 2 Information 0Eh(4) (P+33)h = 13Dh 00h (P+34)h = 13Eh 00h (P+35)h = 13Fh 02h (P+36)h = 140h 64h (P+37)h = 141h 00h Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n x 256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles x 1000 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 53. Common Flash interface Bank and erase block region 1 information (continued) Flash memory (top) Offset(1) Data Flash memory (bottom) Offset(1) (P+38)h = 142h (P+39)h = 143h Description Data 01h Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 03h Bank Region 1 (Erase Block Type 2): Page mode and Synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 1. The variable P is a pointer that is defined at CFI offset 015h. 2. Bank Regions. There are two Bank Regions, see Table 34, Table 37, Table 40 and Table 43. 3. Applies to M58LR128KT/B only. 4. Applies to M58LR256KT/B only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. Table 54. Bank and erase block region 2 information Flash memory (top) Flash memory (bottom) Description Offset(1) Data Offset(1) Data (P+32)h = 13Ch 01h (P+3A)h = 144h 0Fh (P+33)h = 13Dh 00h (P+3B)h = 145h 00h (P+34)h = 13Eh (P+35)h = 13Fh (P+36)h = 140h 11h 00h 00h (P+3C)h = 146h (P+3D)h = 147h (P+3E)h = 148h Number of identical banks within Bank Region 2 11h Number of program or erase operations allowed in Bank Region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 99/120 Common Flash interface Table 54. M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Bank and erase block region 2 information (continued) Flash memory (top) Offset(1) (P+37)h = 141h (P+38)h = 142h 02h Offset(1) (P+3F)h = 149h 06h(3) (P+40)h = 14Ah 0Eh(4) Description Data 01h 00h (P+41)h = 14Bh (P+3A)h = 144h 00h (P+42)h = 14Ch (P+3B)h = 145h 02h (P+43)h = 14Dh (P+3C)h = 146h 64h (P+44)h = 14Eh 64h (P+3D)h = 147h 00h (P+45)h = 14Fh 00h 01h (P+3F)h = 149h 03h (P+40)h = 14Ah 03h (P+41)h = 14Bh 00h (P+42)h = 14Ch 80h (P+43)h = 14Dh 00h (P+44)h = 14Eh 64h (P+45)h = 14Fh 00h (P+46)h = 150h 01h (P+46)h = 150h (P+47)h = 151h Types of erase block regions in Bank Region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) 07h(3) Bank Region 2 Erase Block Type 1 Information 0Fh(4) Bits 0-15: n+1 = number of identical-sized 00h erase blocks 00h Bits 16-31: n x 256 = number of bytes in erase block region 02h (P+39)h = 143h (P+3E)h = 148h 100/120 Data Flash memory (bottom) Bank Region 2 (Erase Block Type 1) Minimum block erase cycles x 1000 01h Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 03h Bank Region 2 (Erase Block Type 1):Page mode and Synchronous mode capabilities (defined in Table 51) Bit 0: Page-mode reads permitted(5) Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n x 256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 2) Minimum block erase cycles x 1000 Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Table 54. Common Flash interface Bank and erase block region 2 information (continued) Flash memory (top) Offset(1) (P+47)h = 151h Data Flash memory (bottom) Offset(1) Description Data Bank Region 2 (Erase Block Type 2): Page mode and Synchronous mode capabilities (defined in Table 51) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved 03h (P+48)h = 152h (P+48)h = 152h Feature Space definitions (P+49)h = 153h (P+43)h = 153h Reserved 1. The variable P is a pointer which is defined at CFI offset 015h. 2. Bank Regions. There are two bank regions, see Table 34, Table 37, Table 40 and Table 43. 3. Applies to M58LR128KT/B only. 4. Applies to M58LR256KT/B only. 5. Although the device supports Page Read mode, this is not described in the datasheet as its use is not advantageous in a multiplexed device. 101/120 Flowcharts and pseudocodes Appendix C M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Flowcharts and pseudocodes Figure 24. Program flowchart and pseudocode Start program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ Write 40h or 10h (3) writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ Read Status Register (3) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES SR4 = 0 YES SR1 = 0 if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06170b 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 102/120 M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Flowcharts and pseudocodes Figure 25. Blank check flowchart and pseudocode Start blank_check_command (blockToCheck) { writeToFlash (blockToCheck, 0xBC); Write Block Address & BCh writeToFlash (blockToCheck, 0xCB); /* Memory enters read status state after the Blank Check Command */ Write Block Address & CBh do { status_register = readFlash (blockToCheck); /* see note (1) */ /* E or G must be toggled */ Read Status Register (1) } while (status_register.SR7==0); SR7 = 1 NO YES SR4 = 1 SR5 = 1 SR5 = 0 YES NO Command Sequence Error (2) if (status_register.SR4==1) && (status_register.SR5==1) /* command sequence error */ error_handler () ; Blank Check Error (2) if (status_register.SR5==1) /* Blank Check error */ error_handler () ; End } ai10520c 1. Any address within the bank can equally be used. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 103/120 Flowcharts and pseudocodes M58LR128KT, M58LR128KB, M58LR256KT, M58LR256KB Figure 26. Buffer program flowchart and pseudocode Start Buffer Program E8h Command, Start Address status_register=readFlash (Start_Address); Read Status Register SR7 = 1 Buffer_Program_command (Start_Address, n, buffer_Program[] ) /* buffer_Program [] is an array structure used to store the address and data to be programmed to the Flash memory (the address must be within the segment Start Address and Start Address+n) */ { do {writeToFlash (Start_Address, 0xE8) ; NO } while (status_register.SR7==0); YES writeToFlash (Start_Address, n); Write n(1), Start Address Write Buffer Data, Start Address writeToFlash (buffer_Program[0].address, buffer_Program[0].data); /*buffer_Program[0].address is the start address*/ X=0 X=n x = 0; YES while (x