M58WR064EB70ZB6

M58WR064ET M58WR064EB 64 Mbit (4Mb x 16, Multiple Bank, Burst) 1.8V Supply Flash Memory FEATURES SUMMARY ■ SUPPLY VOLTAGE Figure 1. Package – VDD = 1.65V to 2.2V for Program, Erase and Read – VDDQ = 1.65V to 3.3V for I/O Buffers – VPP = 12V for fast Program (optional) ■ SYNCHRONOUS / ASYNCHRONOUS READ – Synchronous Burst Read mode: 54MHz FBGA – Asynchronous/ Synchronous Page Read mode – Random Access: 70, 80, 100 ns ■ PROGRAMMING TIME – 8µs by Word typical for Fast Factory Program VFBGA56 (ZB) 7.7 x 9 mm – Double/Quadruple Word Program option – Enhanced Factory Program options ■ MEMORY BLOCKS – Multiple Bank Memory Array: 4 Mbit Banks – Parameter Blocks (Top or Bottom location) ■ ELECTRONIC SIGNATURE – Manufacturer Code: 20h – Program Erase in one Bank while Read in others – Top Device Code, M58WR064ET: 8810h – No delay between Read and Write operations ■ ■ DUAL OPERATIONS – Bottom Device Code, M58WR064EB: 8811h BLOCK LOCKING – All blocks locked at Power up – Any combination of blocks can be locked – WP for Block Lock-Down ■ SECURITY – 128 bit user programmable OTP cells – 64 bit unique device number – One parameter block permanently lockable ■ COMMON FLASH INTERFACE (CFI) ■ 100,000 PROGRAM/ERASE CYCLES per BLOCK February 2003 1/82 M58WR064ET, M58WR064EB TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Table 1. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 3. VFBGA Connections (Top view through package). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Table 2. Bank Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Figure 4. Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 SIGNAL DESCRIPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Address Inputs (A0-A21). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Data Input/Output (DQ0-DQ15). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chip Enable (E). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Output Enable (G). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Enable (W). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Write Protect (WP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset (RP). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Latch Enable (L). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Clock (K).. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Wait (WAIT). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDD Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VDDQ Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VPP Program Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSS Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 VSSQ Ground. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 BUS OPERATIONS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Bus Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Address Latch.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Output Disable. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Standby. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Table 3. Bus Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 COMMAND INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Table 4. Command Codes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 COMMAND INTERFACE - STANDARD COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Array Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read Electronic Signature Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Read CFI Query Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Clear Status Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Block Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program/Erase Suspend Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Program/Erase Resume Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2/82 M58WR064ET, M58WR064EB Protection Register Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Set Configuration Register Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Unlock Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Block Lock-Down Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Table 5. Standard Commands. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Table 6. Electronic Signature Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Figure 5. Security Block and Protection Register Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 COMMAND INTERFACE - FACTORY PROGRAM COMMANDS . . . . . . . . . . . . . . . . . . . . . . . . . 18 Bank Erase Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Double Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Quadruple Word Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Program Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Quadruple Enhanced Factory Program Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Setup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Load Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Program and Verify Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Exit Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Table 7. Factory Program Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 STATUS REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program/Erase Controller Status Bit (SR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Suspend Status Bit (SR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Erase Status Bit (SR5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Status Bit (SR4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 VPP Status Bit (SR3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Program Suspend Status Bit (SR2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Block Protection Status Bit (SR1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Bank Write/Multiple Word Program Status Bit (SR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Table 8. Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 CONFIGURATION REGISTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Read Select Bit (CR15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 X-Latency Bits (CR13-CR11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wait Polarity Bit (CR10). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Data Output Configuration Bit (CR9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wait Configuration Bit (CR8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Burst Type Bit (CR7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Valid Clock Edge Bit (CR6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Wrap Burst Bit (CR3). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Burst length Bits (CR2-CR0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Table 9. Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 3/82 M58WR064ET, M58WR064EB Table 10. Burst Type Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 6. X-Latency and Data Output Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Figure 7. Wait Configuration Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 READ MODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Asynchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Synchronous Burst Read Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Single Synchronous Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 11. Dual Operations Allowed In Other Banks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Table 12. Dual Operations Allowed In Same Bank . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 BLOCK LOCKING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reading a Block’s Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Locked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Unlocked State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Lock-Down State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Locking Operations During Erase Suspend . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Table 13. Lock Status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Table 14. Program, Erase Times and Program, Erase Endurance Cycles . . . . . . . . . . . . . . . . . . . 34 MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Table 15. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 16. Operating and AC Measurement Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 8. AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Figure 9. AC Measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 17. Capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Table 18. DC Characteristics - Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Table 19. DC Characteristics - Voltages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Figure 10. Asynchronous Random Access Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . 39 Figure 11. Asynchronous Page Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Table 20. Asynchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Figure 12. Synchronous Burst Read AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Figure 13. Single Synchronous Read AC Waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Figure 14. Clock input AC Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Table 21. Synchronous Read AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Figure 15. Write AC Waveforms, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Table 22. Write AC Characteristics, Write Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Figure 16. Write AC Waveforms, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Table 23. Write AC Characteristics, Chip Enable Controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Figure 17. Reset and Power-up AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Table 24. Reset and Power-up AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 4/82 M58WR064ET, M58WR064EB PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Figure 18. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline. . . 50 Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data . . . . . . 50 Figure 19. VFBGA56 Daisy Chain - Package Connections (Top view through package) . . . . . . . . 51 Figure 20. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) . . . . 52 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 26. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Table 27. Daisy Chain Ordering Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 APPENDIX A. BLOCK ADDRESS TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 28. Top Boot Block Addresses, M58WR064ET. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Table 29. Bottom Boot Block Addresses, M58WR064EB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 APPENDIX B. COMMON FLASH INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 30. Query Structure Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 31. CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Table 32. CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 33. Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Table 34. Primary Algorithm-Specific Extended Query Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Table 35. Protection Register Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 36. Burst Read Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 37. Bank and Erase Block Region Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Table 38. Bank and Erase Block Region 1 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 Table 39. Bank and Erase Block Region 2 Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 APPENDIX C. FLOWCHARTS AND PSEUDO CODES. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 21. Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Figure 22. Double Word Program Flowchart and Pseudo code . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Figure 23. Quadruple Word Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . 67 Figure 24. Program Suspend & Resume Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . 68 Figure 25. Block Erase Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code. . . . . . . . . . . . . . . . . . . . . . . . 70 Figure 27. Locking Operations Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Figure 28. Protection Register Program Flowchart and Pseudo Code . . . . . . . . . . . . . . . . . . . . . . 72 Figure 29. Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Figure 30. Quadruple Enhanced Factory Program Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Quadruple Enhanced Factory Program Pseudo Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 APPENDIX D. COMMAND INTERFACE STATE TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 40. Command Interface States Table 41. Command Interface States Table 42. Command Interface States Table 43. Command Interface States - Modify Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . 77 - Modify Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . 78 - Lock Table, Next State . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 - Lock Table, Next Output . . . . . . . . . . . . . . . . . . . . . . . . . . 80 REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 44. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 5/82 M58WR064ET, M58WR064EB SUMMARY DESCRIPTION The M58WR064E is a 64 Mbit (4Mbit x16) non-volatile Flash memory that may be erased electrically at block level and programmed in-system on a Word-by-Word basis using a 1.65V to 2.2V V DD supply for the circuitry and a 1.65V to 3.3V VDDQ supply for the Input/Output pins. An optional 12V VPP power supply is provided to speed up customer programming. The device features an asymmetrical block architecture. M58WR064E has an array of 135 blocks, and is divided into 4 Mbit banks. There are 15 banks each containing 8 main blocks of 32 KWords, and one parameter bank containing 8 parameter blocks of 4 KWords and 7 main blocks of 32 KWords. The Multiple Bank Architecture allows Dual Operations, while programming or erasing in one bank, Read operations are possible in other banks. Only one bank at a time is allowed to be in Program or Erase mode. It is possible to perform burst reads that cross bank boundaries. The bank architecture is summarized in Table 2, and the memory maps are shown in Figure 4. The Parameter Blocks are located at the top of the memory address space for the M58WR064ET, and at the bottom for the M58WR064EB. Each block can be erased separately. Erase can be suspended, in order to perform program in any other block, and then resumed. Program can be suspended to read data in any other block and then resumed. Each block can be programmed and erased over 100,000 cycles using the supply voltage V DD. There are two Enhanced Factory programming commands available to speed up programming. Program and Erase commands are written to the Command Interface of the memory. An internal Program/Erase Controller takes care of the timings necessary for program and erase operations. The end of a program or erase operation can be detected and any error conditions identified in the Status Register. The command set required to 6/82 control the memory is consistent with JEDEC standards. The device supports synchronous burst read and asynchronous read from all blocks of the memory array; at power-up the device is configured for asynchronous read. In synchronous burst mode, data is output on each clock cycle at frequencies of up to 54MHz. The device features an Automatic Standby mode. When the bus is inactive during Asynchronous Read operations, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value IDD4 and the outputs are still driven. The M58WR064E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency, enabling instant code and data protection. All blocks have three levels of protection. They can be locked and locked-down individually preventing any accidental programming or erasure. There is an additional hardware protection against program and erase. When V PP ≤ VPPLK all blocks are protected against program or erase. All blocks are locked at PowerUp. The device includes a Protection Register and a Security Block to increase the protection of a system’s design. The Protection Register is divided into two segments: a 64 bit segment containing a unique device number written by ST, and a 128 bit segment One-Time-Programmable (OTP) by the user. The user programmable segment can be permanently protected. The Security Block, parameter block 0, can be permanently protected by the user. Figure 5, shows the Security Block and Protection Register Memory Map. The memory is offered in a VFBGA56, 7.7 x 9 mm 0.75 mm ball pitch package and is supplied with all the bits erased (set to ’1’). M58WR064ET, M58WR064EB Figure 2. Logic Diagram Table 1. Signal Names A0-A21 Address Inputs DQ0-DQ15 Data Input/Outputs, Command Inputs E Chip Enable G Output Enable W Write Enable RP Reset WP Write Protect K Clock L Latch Enable WAIT Wait VDD Supply Voltage VDDQ Supply Voltage for Input/Output Buffers VPP Optional Supply Voltage for Fast Program & Erase VSS Ground VSSQ Ground Input/Output Supply NC Not Connected Internally VDD VDDQ VPP 22 16 A0-A21 DQ0-DQ15 W WAIT E G M58WR064ET M58WR064EB RP WP L K VSS VSSQ AI05587 7/82 M58WR064ET, M58WR064EB Figure 3. VFBGA Connections (Top view through package) 1 2 3 4 5 6 7 8 A A11 A8 VSS VDD VPP A18 A6 A4 B A12 A9 A20 K RP A17 A5 A3 C A13 A10 A21 L W A19 A7 A2 D A15 A14 WAIT A16 DQ12 WP NC A1 E VDDQ DQ15 DQ6 DQ4 DQ2 DQ1 E A0 F VSS DQ14 DQ13 DQ11 DQ10 DQ9 DQ0 G G DQ7 VSSQ DQ5 VDD DQ3 VDDQ DQ8 VSSQ AI06189 Table 2. Bank Architecture 8/82 Parameter Bank 4 Mbits 8 blocks of 4 KWords 7 blocks of 32 KWords Bank 1 4 Mbits - 8 blocks of 32 KWords Bank 2 4 Mbits - 8 blocks of 32 KWords Bank 3 4 Mbits - 8 blocks of 32 KWords ---- Main Blocks ---- Parameter Blocks ---- Bank Size ---- Number Bank 14 4 Mbits - 8 blocks of 32 KWords Bank 15 4 Mbits - 8 blocks of 32 KWords M58WR064ET, M58WR064EB Figure 4. Memory Map M58WR064ET - Top Boot Block Address lines A21-A0 000000h 007FFFh 32 KWord 038000h 03FFFFh 32 KWord 8 Main Blocks Parameter Bank 3F0000h 3F7FFFh 3F8000h 3F8FFFh 3FF000h 3FFFFFh 8 Parameter Blocks 4KWord 32 KWord 7 Main Blocks 32 KWord 32 KWord 8 Main Blocks 32 KWord 32 KWord 8 Main Blocks Bank 2 0B8000h 0BFFFFh 0C0000h 0C7FFFh 32 KWord Bank 1 3B8000h 3BFFFFh 3C0000h 3C7FFFh 078000h 07FFFFh 080000h 087FFFh 32 KWord 8 Main Blocks 4 KWord Bank 1 32 KWord 8 Main Blocks 007000h 007FFFh 008000h 00FFFFh 038000h 03FFFFh 040000h 047FFFh 32 KWord Bank 2 378000h 37FFFFh 380000h 387FFFh Parameter Bank 32 KWord Bank 3 338000h 33FFFFh 340000h 347FFFh 000000h 000FFFh 8 Main Blocks Bank 15 300000h 307FFFh M58WR064EB - Bottom Boot Block Address lines A21-A0 32 KWord 32 KWord 8 Main Blocks Bank 3 32 KWord 0F8000h 0FFFFFh 32 KWord 3C0000h 3C7FFFh 32 KWord 3F8000h 3FFFFFh 32 KWord 32 KWord 7 Main Blocks 32 KWord 4 KWord 8 Parameter Blocks 4 KWord 8 Main Blocks Bank 15 AI06971b 9/82 M58WR064ET, M58WR064EB SIGNAL DESCRIPTIONS See Figure 2 Logic Diagram and Table 1,Signal Names, for a brief overview of the signals connected to this device. Address Inputs (A0-A21). The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. Data Input/Output (DQ0-DQ15). The Data I/O outputs the data stored at the selected address during a Bus Read operation or inputs a command or the data to be programmed during a Bus Write operation. Chip Enable (E). The Chip Enable input activates the memory control logic, input buffers, decoders and sense amplifiers. When Chip Enable is at VILand Reset is at VIH the device is in active mode. When Chip Enable is at VIH the memory is deselected, the outputs are high impedance and the power consumption is reduced to the stand-by level. Output Enable (G). The Output Enable controls data outputs during the Bus Read operation of the memory. Write Enable (W). The Write Enable controls the Bus Write operation of the memory’s Command Interface. The data and address inputs are latched on the rising edge of Chip Enable or Write Enable whichever occurs first. Write Protect (WP). Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is at VIL, the LockDown is enabled and the protection status of the Locked-Down blocks cannot be changed. When Write Protect is at VIH, the Lock-Down is disabled and the Locked-Down blocks can be locked or unlocked. (refer to Table 13, Lock Status). Reset (RP). The Reset input provides a hardware reset of the memory. When Reset is at VIL, the memory is in reset mode: the outputs are high impedance and the current consumption is reduced to the Reset Supply Current IDD2. Refer to Table 2, DC Characteristics - Currents for the value of I DD2. After Reset all blocks are in the Locked state and the Configuration Register is reset. When Reset is at VIH, the device is in normal operation. Exiting reset mode the device enters asynchronous read mode, but a negative transition of Chip Enable or Latch Enable is required to ensure valid data outputs. The Reset pin can be interfaced with 3V logic without any additional circuitry. It can be tied to VRPH (refer to Table 19, DC Characteristics). Latch Enable (L). Latch Enable latches the address bits on its rising edge. The address latch is transparent when Latch Enable is at 10/82 V IL and it is inhibited when Latch Enable is at V IH . Latch Enable can be kept Low (also at board level) when the Latch Enable function is not required or supported. Clock (K). The clock input synchronizes the memory to the microcontroller during synchronous read operations; the address is latched on a Clock edge (rising or falling, according to the configuration settings) when Latch Enable is at VIL. Clock is don't care during asynchronous read and in write operations. Wait (WAIT). Wait is an output signal used during synchronous read to indicate whether the data on the output bus are valid. This output is high impedance when Chip Enable is at VIH or Reset is at VIL. It can be configured to be active during the wait cycle or one clock cycle in advance. The WAIT signal is not gated by Output Enable. VDD Supply Voltage . VDD provides the power supply to the internal core of the memory device. It is the main power supply for all operations (Read, Program and Erase). VDDQ Supply Voltage. VDDQ provides the power supply to the I/O pins and enables all Outputs to be powered independently from VDD. VDDQ can be tied to VDD or can use a separate supply. VPP Program Supply Voltage. VPP is both a control input and a power supply pin. The two functions are selected by the voltage range applied to the pin. If V PP is kept in a low voltage range (0V to VDDQ) VPP is seen as a control input. In this case a voltage lower than VPPLK gives an absolute protection against program or erase, while V PP > VPP1 enables these functions (see Tables 18 and 19, DC Characteristics for the relevant values). VPP is only sampled at the beginning of a program or erase; a change in its value after the operation has started does not have any effect and program or erase operations continue. If V PP is in the range of VPPH it acts as a power supply pin. In this condition VPP must be stable until the Program/Erase algorithm is completed. VSS Ground. VSS ground is the reference for the core supply. It must be connected to the system ground. VSSQ Ground. VSSQ ground is the reference for the input/output circuitry driven by V DDQ. VSSQ must be connected to V SS Note: Each device in a system should have VDD, VDDQ and V PP decoupled with a 0.1µF ceramic capacitor close to the pin (high frequency, inherently low inductance capacitors should be as close as possible to the pack- M58WR064ET, M58WR064EB age). See Figure 9, AC Measurement Load Circuit. The PCB trace widths should be sufficient BUS OPERATIONS There are six standard bus operations that control the device. These are Bus Read, Bus Write, Address Latch, Output Disable, Standby and Reset. See Table 3, Bus Operations, for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect Bus Write operations. Bus Read. Bus Read operations are used to output the contents of the Memory Array, the Electronic Signature, the Status Register and the Common Flash Interface. Both Chip Enable and Output Enable must be at V IL in order to perform a read operation. The Chip Enable input should be used to enable the device. Output Enable should be used to gate data onto the output. The data read depends on the previous command written to the memory (see Command Interface section). See Figures 10, 11, 12 and 13 Read AC Waveforms, and Tables 20 and 21 Read AC Characteristics, for details of when the output becomes valid. Bus Write. Bus Write operations write Commands to the memory or latch Input Data to be programmed. A bus write operation is initiated when Chip Enable and Write Enable are at VIL with Output Enable at VIH. Commands, Input Data and Addresses are latched on the rising edge of Write Enable or Chip Enable, whichever occurs first. The addresses can also be latched prior to the write operation by toggling Latch Enable. In this case to carry the required V PP program and erase currents. the Latch Enable should be tied to VIH during the bus write operation. See Figures 15 and 16, Write AC Waveforms, and Tables 22 and 23, Write AC Characteristics, for details of the timing requirements. Address Latch. Address latch operations input valid addresses. Both Chip enable and Latch Enable must be at V IL during address latch operations. The addresses are latched on the rising edge of Latch Enable. Output Disable. The outputs are high impedance when the Output Enable is at VIH. Standby. Standby disables most of the internal circuitry allowing a substantial reduction of the current consumption. The memory is in stand-by when Chip Enable and Reset are at VIH. The power consumption is reduced to the stand-by level and the outputs are set to high impedance, independently from the Output Enable or Write Enable inputs. If Chip Enable switches to VIH during a program or erase operation, the device enters Standby mode when finished. Reset. During Reset mode the memory is deselected and the outputs are high impedance. The memory is in Reset mode when Reset is at VIL. The power consumption is reduced to the Standby level, independently from the Chip Enable, Output Enable or Write Enable inputs. If Reset is pulled to VSS during a Program or Erase, this operation is aborted and the memory content is no longer valid. Table 3. Bus Operations Operation WAIT(4) E G W L RP Bus Read VIL VIL VIH VIL(2) VIH Data Output Bus Write VIL VIH VIL VIL(2) VIH Data Input Address Latch VIL X VIH VIL VIH Data Output or Hi-Z (3) Output Disable VIL VIH VIH X VIH Hi-Z Standby VIH X X X VIH Hi-Z Hi-Z X X X X VIL Hi-Z Hi-Z Reset Note: 1. 2. 3. 4. DQ15-DQ0 X = Don’t care. L can be tied to VIH if the valid address has been previously latched. Depends on G. WAIT signal polarity is configured using the Set Configuration Register command. 11/82 M58WR064ET, M58WR064EB COMMAND INTERFACE All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. An internal Program/Erase Controller handles all timings and verifies the correct execution of the Program and Erase commands. The Program/Erase Controller provides a Status Register whose output may be read at any time to monitor the progress or the result of the operation. The Command Interface is reset to read mode when power is first applied, when exiting from Reset or whenever V DD is lower than VLKO . Command sequences must be followed exactly. Any invalid combination of commands will be ignored. Refer to Table 4, Command Codes and Appendix D, Tables 40, 41, 42 and 43, Command Interface States - Modify and Lock Tables, for a summary of the Command Interface. The Command Interface is split into two types of commands: Standard commands and Factory Program commands. The following sections explain in detail how to perform each command. 12/82 Table 4. Command Codes Hex Code Command 01h Block Lock Confirm 03h Set Configuration Register Confirm 10h Alternative Program Setup 20h Block Erase Setup 2Fh Block Lock-Down Confirm 30h Enhanced Factory Program Setup 35h Double Word Program Setup 40h Program Setup 50h Clear Status Register 56h Quadruple Word Program Setup 60h Block Lock Setup, Block Unlock Setup, Block Lock Down Setup and Set Configuration Register Setup 70h Read Status Register 75h Quadruple Enhanced Factory Program Setup 80h Bank Erase Setup 90h Read Electronic Signature 98h Read CFI Query B0h Program/Erase Suspend C0h Protection Register Program D0h Program/Erase Resume, Block Erase Confirm, Bank Erase Confirm, Block Unlock Confirm or Enhanced Factory Program Confirm FFh Read Array M58WR064ET, M58WR064EB COMMAND INTERFACE - STANDARD COMMANDS The following commands are the basic commands Read CFI Query Command used to read, write to and configure the device. The Read CFI Query command is used to read Refer to Table 5, Standard Commands, in condata from the Common Flash Interface (CFI). The junction with the following text descriptions. Read CFI Query Command consists of one Bus Read Array Command Write cycle, to an address within one of the banks. Once the command is issued subsequent Bus The Read Array command returns the addressed Read operations in the same bank read from the bank to Read Array mode. One Bus Write cycle is Common Flash Interface. required to issue the Read Array command and return the addressed bank to Read Array mode. If a Read CFI Query command is issued in a bank Subsequent read operations will read the adthat is executing a Program or Erase operation the dressed location and output the data. A Read Arbank will go into Read CFI Query mode, subseray command can be issued in one bank while quent Bus Read cycles will output the CFI data programming or erasing in another bank. However and the Program/Erase controller will continue to if a Read Array command is issued to a bank curProgram or Erase in the background. This mode rently executing a Program or Erase operation the supports asynchronous or single synchronous command will be executed but the output data is reads only, it does not support page mode or synnot guaranteed. chronous burst reads. Read Status Register Command The status of the other banks is not affected by the command (see Table 11). After issuing a Read The Status Register indicates when a Program or CFI Query command, a Read Array command Erase operation is complete and the success or should be issued to the addressed bank to return failure of operation itself. Issue a Read Status the bank to Read Array mode. Register command to read the Status Register content. The Read Status Register command can See Appendix C, Common Flash Interface, Tables be issued at any time, even during Program or 30, 31, 32, 33, 34, 36, 37, 38 and 39 for details on Erase operations. the information contained in the Common Flash Interface memory area. The following read operations output the content of the Status Register of the addressed bank. The Clear Status Register Command Status Register is latched on the falling edge of E The Clear Status Register command can be used or G signals, and can be read until E or G returns to reset (set to ‘0’) error bits 1, 3, 4 and 5 in the Stato V IH. Either E or G must be toggled to update the tus Register. One bus write cycle is required to islatched data. See Table 8 for the description of the sue the Clear Status Register command. The Status Register Bits. This mode supports asynClear Status Register command does not change chronous or single synchronous reads only. the Read mode of the bank. Read Electronic Signature Command The error bits in the Status Register do not autoThe Read Electronic Signature command reads matically return to ‘0’ when a new command is isthe Manufacturer and Device Codes, the Block sued. The error bits in the Status Register should Locking Status, the Protection Register, and the be cleared before attempting a new Program or Configuration Register. Erase command. The Read Electronic Signature command consists Block Erase Command of one write cycle to an address within one of the The Block Erase command can be used to erase banks. A subsequent Read operation in the same a block. It sets all the bits within the selected block bank will output the Manufacturer Code, the Deto ’1’. All previous data in the block is lost. If the vice Code, the protection Status of the blocks in block is protected then the Erase operation will the targeted bank, the Protection Register, or the abort, the data in the block will not be changed and Configuration Register (see Table 6). the Status Register will output the error. The Block If a Read Electronic Signature command is issued Erase command can be issued at any moment, rein a bank that is executing a Program or Erase opgardless of whether the block has been proeration the bank will go into Read Electronic Siggrammed or not. nature mode, subsequent Bus Read cycles will Two Bus Write cycles are required to issue the output the Electronic Signature data and the Procommand. gram/Erase controller will continue to program or ■ The first bus cycle sets up the Erase command. erase in the background. This mode supports ■ The second latches the block address in the asynchronous or single synchronous reads only, it internal state machine and starts the Program/ does not support page mode or synchronous burst Erase Controller. reads. 13/82 M58WR064ET, M58WR064EB If the second bus cycle is not Write Erase Confirm (D0h), Status Register bits 4 and 5 are set and the command aborts. Erase aborts if Reset turns to VIL. As data integrity cannot be guaranteed when the Erase operation is aborted, the block must be erased again. Once the command is issued the device outputs the Status Register data when any address within the bank is read. At the end of the operation the bank will remain in Read Status Register mode until a Read Array, Read CFI Query or Read Electronic Signature command is issued. During Erase operations the bank containing the block being erased will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command, all other commands will be ignored. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being erased. Typical Erase times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 25, Block Erase Flowchart and Pseudo Code, for a suggested flowchart for using the Block Erase command. Program Command The memory array can be programmed word-byword. Only one Word in one bank can be programmed at any one time. Two bus write cycles are required to issue the Program Command. ■ The first bus cycle sets up the Program command. ■ The second latches the Address and the Data to be written and starts the Program/Erase Controller. After programming has started, read operations in the bank being programmed output the Status Register content. During Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature, Read CFI Query and the Program/Erase Suspend command. Refer to Dual Operations section for detailed information about simultaneous operations allowed in banks not being programmed. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory location must be reprogrammed. See Appendix C, Figure 21, Program Flowchart and Pseudo Code, for the flowchart for using the Program command. 14/82 Program/Erase Suspend Command The Program/Erase Suspend command is used to pause a Program or Block Erase operation. A Bank Erase operation cannot be suspended. One bus write cycle is required to issue the Program/Erase command. Once the Program/Erase Controller has paused bits SR7, SR6 and/ or SR2 of the Status Register will be set to ‘1’. The command can be addressed to any bank. During Program/Erase Suspend the Command Interface will accept the Program/Erase Resume, Read Array (cannot read the erase-suspended block or the program-suspended Word), Read Status Register, Read Electronic Signature and Read CFI Query commands. Additionally, if the suspend operation was Erase then the Clear status Register, Program, Block Lock, Block LockDown or Block Unlock commands will also be accepted. The block being erased may be protected by issuing the Block Lock, Block Lock-Down or Protection Register Program commands. Only the blocks not being erased may be read or programmed correctly. When the Program/Erase Resume command is issued the operation will complete. Refer to the Dual Operations section for detailed information about simultaneous operations allowed during Program/Erase Suspend. During a Program/Erase Suspend, the device can be placed in standby mode by taking Chip Enable to VIH. Program/Erase is aborted if Reset turns to VIL. See Appendix C, Figure 24, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/ Erase Suspend command. Program/Erase Resume Command The Program/Erase Resume command can be used to restart the Program/Erase Controller after a Program/Erase Suspend command has paused it. One Bus Write cycle is required to issue the command. The command can be written to any address. The Program/Erase Resume command does not change the read mode of the banks. If the suspended bank was in Read Status Register, Read Electronic signature or Read CFI Query mode the bank remains in that mode and outputs the corresponding data. If the bank was in Read Array mode subsequent read operations will output invalid data. If a Program command is issued during a Block Erase Suspend, then the erase cannot be resumed until the programming operation has completed. It is possible to accumulate suspend operations. For example: suspend an erase operation, start a programming operation, suspend the M58WR064ET, M58WR064EB programming operation then read the array. See Appendix C, Figure 24, Program Suspend & Resume Flowchart and Pseudo Code, and Figure 26, Erase Suspend & Resume Flowchart and Pseudo Code for flowcharts for using the Program/Erase Resume command. Protection Register Program Command The Protection Register Program command is used to Program the 128 bit user One-Time-Programmable (OTP) segment of the Protection Register and the Protection Register Lock. The segment is programmed 16 bits at a time. When shipped all bits in the segment are set to ‘1’. The user can only program the bits to ‘0’. Two write cycles are required to issue the Protection Register Program command. ■ The first bus cycle sets up the Protection Register Program command. ■ The second latches the Address and the Data to be written to the Protection Register and starts the Program/Erase Controller. Read operations output the Status Register content after the programming has started. The segment can be protected by programming bit 1 of the Protection Lock Register. Bit 1 of the Protection Lock Register also protects bit 2 of the Protection Lock Register. Programming bit 2 of the Protection Lock Register will result in a permanent protection of Parameter Block #0 (see Figure 5, Security Block and Protection Register Memory Map). Attempting to program a previously protected Protection Register will result in a Status Register error. The protection of the Protection Register and/or the Security Block is not reversible. The Protection Register Program cannot be suspended. See Appendix C, Figure 28, Protection Register Program Flowchart and Pseudo Code, for a flowchart for using the Protection Register Program command. Set Configuration Register Command The Set Configuration Register command is used to write a new value to the Burst Configuration Control Register which defines the burst length, type, X latency, Synchronous/Asynchronous Read mode and the valid Clock edge configuration. Two Bus Write cycles are required to issue the Set Configuration Register command. ■ The first cycle writes the setup command and the address corresponding to the Configuration Register content. ■ The second cycle writes the Configuration Register data and the confirm command. The Read mode of the banks is not modified when the Set Configuration Register command is issued. The value for the Configuration Register is always presented on A0-A15. CR0 is on A0, CR1 on A1, etc.; the other address bits are ignored. Block Lock Command The Block Lock command is used to lock a block and prevent Program or Erase operations from changing the data in it. All blocks are locked at power-up or reset. Two Bus Write cycles are required to issue the Block Lock command. ■ The first bus cycle sets up the Block Lock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table. 13 shows the Lock Status after issuing a Block Lock command. The Block Lock bits are volatile, once set they remain set until a hardware reset or power-down/ power-up. They are cleared by a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation. See Appendix C, Figure 27, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock command. Block Unlock Command The Block Unlock command is used to unlock a block, allowing the block to be programmed or erased. Two Bus Write cycles are required to issue the Block Unlock command. ■ The first bus cycle sets up the Block Unlock command. ■ The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Table 13 shows the protection status after issuing a Block Unlock command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 27, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Unlock command. Block Lock-Down Command A locked or unlocked block can be locked-down by issuing the Block Lock-Down command. A lockeddown block cannot be programmed or erased, or have its protection status changed when WP is low, VIL. When WP is high, VIH, the Lock-Down function is disabled and the locked blocks can be individually unlocked by the Block Unlock command. Two Bus Write cycles are required to issue the Block Lock-Down command. ■ The first bus cycle sets up the Block Lock command. 15/82 M58WR064ET, M58WR064EB The second Bus Write cycle latches the block address. The lock status can be monitored for each block using the Read Electronic Signature command. Locked-Down blocks revert to the locked (and not locked-down) state when the device is reset on power-down. Table. 13 shows the Lock Status after issuing a Block Lock-Down command. Refer to the section, Block Locking, for a detailed explanation and Appendix C, Figure 27, Locking Operations Flowchart and Pseudo Code, for a flowchart for using the Lock-Down command. ■ Commands Cycles Table 5. Standard Commands Bus Operations 1st Cycle 2nd Cycle Op. Add Data Op. Add Data Read Array 1+ Write BKA FFh Read WA RD Read Status Register 1+ Write BKA 70h Read BKA(2) SRD Read Electronic Signature 1+ Write BKA 90h Read BKA(2) ESD Read CFI Query 1+ Write BKA 98h Read BKA(2) QD Clear Status Register 1 Write BKA 50h Block Erase 2 Write BKA or BA(3) 20h Write BA D0h Program 2 Write BKA or WA(3) 40h or 10h Write WA PD Program/Erase Suspend 1 Write X B0h Program/Erase Resume 1 Write X D0h Protection Register Program 2 Write PRA C0h Write PRA PRD Set Configuration Register 2 Write CRD 60h Write CRD 03h Block Lock 2 Write BKA or BA(3) 60h Write BA 01h Block Unlock 2 Write BKA or BA(3) 60h Write BA D0h Block Lock-Down 2 Write BKA or BA(3) 60h Write BA 2Fh Note: 1. X = Don’t Care, WA=Word Address in targeted bank, RD=Read Data, SRD=Status Register Data, ESD=Electronic Signature Data, QD=Query Data, BA=Block Address, BKA= Bank Address, PD=Program Data, PRA=Protection Register Address, PRD=Protection Register Data, CRD=Configuration Register Data. 2. Must be same bank as in the first cycle. The signature addresses are listed in Table 6. 3. Any address within the bank can be used. 16/82 M58WR064ET, M58WR064EB Table 6. Electronic Signature Codes Code Address (h) Data (h) Bank Address + 00 0020 Top Bank Address + 01 8810 Bottom Bank Address + 01 8811 Manufacturer Code Device Code Lock 0001 Unlocked 0000 Block Protection Block Address + 02 Locked and Locked-Down 0003 Unlocked and Locked-Down 0002 Reserved Bank Address + 03 Reserved Configuration Register Bank Address + 05 CR ST Factory Default 0006 Security Block Permanently Locked Protection Register Lock 0002 Bank Address + 80 OTP Area Permanently Locked Security Block and OTP Area Permanently Locked 0004 0000 Bank Address + 81 Bank Address + 84 Unique Device Number Bank Address + 85 Bank Address + 8C OTP Area Protection Register Note: CR=Configuration Register. Figure 5. Security Block and Protection Register Memory Map PROTECTION REGISTER 8Ch SECURITY BLOCK User Programmable OTP 85h 84h Parameter Block # 0 Unique device number 81h 80h Protection Register Lock 2 1 0 AI06181 17/82 M58WR064ET, M58WR064EB COMMAND INTERFACE - FACTORY PROGRAM COMMANDS Dual operations are not supported during Bank The Factory Program commands are used to Erase operations and the command cannot be speed up programming. They require V PP to be at suspended. VPPH except for the Bank Erase command which also operates at VPP = VDD. Refer to Table 7, FacTypical Erase times are given in Table 14, Protory Program Commands, in conjunction with the gram, Erase Times and Program/Erase Endurfollowing text descriptions. ance Cycles. The use of Factory Program commands requires Double Word Program Command certain operating conditions. The Double Word Program command improves ■ VPP must be set to VPPH (except for Bank Erase the programming throughput by writing a page of command), two adjacent words in parallel. The two words ■ VDD must be within operating range, must differ only for the address A0. ■ Ambient temperature, TA must be 25°C ± 5°C, Three bus write cycles are necessary to issue the Double Word Program command. ■ The targeted block must be unlocked. ■ The first bus cycle sets up the Double Word Bank Erase Command Program Command. The Bank Erase command can be used to erase a ■ The second bus cycle latches the Address and bank. It sets all the bits within the selected bank to the Data of the first word to be written. ’1’. All previous data in the bank is lost. The Bank ■ The third bus cycle latches the Address and the Erase command will ignore any protected blocks Data of the second word to be written and starts within the bank. If all blocks in the bank are prothe Program/Erase Controller. tected then the Bank Erase operation will abort and the data in the bank will not be changed. The Read operations in the bank being programmed Status Register will not output any error. output the Status Register content after the programming has started. Bank Erase operations can be performed at both VPP = VPPH and V PP = VDD. During Double Word Program operations the bank Two Bus Write cycles are required to issue the being programmed will only accept the Read Arcommand. ray, Read Status Register, Read Electronic Signature and Read CFI Query command, all other ■ The first bus cycle sets up the Bank Erase commands will be ignored. Dual operations are command. not supported during Double Word Program oper■ The second latches the bank address in the ations and the command cannot be suspended. internal state machine and starts the Program/ Typical Program times are given in Table 14, ProErase Controller. gram, Erase Times and Program/Erase EndurIf the second bus cycle is not Write Bank Erase ance Cycles. Confirm (D0h), Status Register bits SR4 and SR5 Programming aborts if Reset goes to VIL. As data are set and the command aborts. Erase aborts if integrity cannot be guaranteed when the program Reset turns to VIL. As data integrity cannot be operation is aborted, the memory locations must guaranteed when the Erase operation is aborted, be reprogrammed. the bank must be erased again. See Appendix C, Figure 22, Double Word ProOnce the command is issued the device outputs gram Flowchart and Pseudo Code, for the flowthe Status Register data when any address within chart for using the Double Word Program the bank is read. At the end of the operation the command. bank will remain in Read Status Register mode unQuadruple Word Program Command til a Read Array, Read CFI Query or Read Electronic Signature command is issued. The Quadruple Word Program command improves the programming throughput by writing a During Bank Erase operations the bank being page of four adjacent words in parallel. The four erased will only accept the Read Array, Read Stawords must differ only for the addresses A0 and tus Register, Read Electronic Signature and Read A1. CFI Query command, all other commands will be ignored. Five bus write cycles are necessary to issue the Quadruple Word Program command. For optimum performance, Bank Erase com■ The first bus cycle sets up the Double Word mands should be limited to a maximum of 100 ProProgram Command. gram/Erase cycles per Block. After 100 Program/ Erase cycles the internal algorithm will still operate ■ The second bus cycle latches the Address and properly but some degradation in performance the Data of the first word to be written. may occur. 18/82 M58WR064ET, M58WR064EB The third bus cycle latches the Address and the Data of the second word to be written. ■ The fourth bus cycle latches the Address and the Data of the third word to be written. ■ The fifth bus cycle latches the Address and the Data of the fourth word to be written and starts the Program/Erase Controller. Read operations to the bank being programmed output the Status Register content after the programming has started. Programming aborts if Reset goes to VIL. As data integrity cannot be guaranteed when the program operation is aborted, the memory locations must be reprogrammed. During Quadruple Word Program operations the bank being programmed will only accept the Read Array, Read Status Register, Read Electronic Signature and Read CFI Query command, all other commands will be ignored. Dual operations are not supported during Quadruple Word Program operations and the command cannot be suspended. Typical Program times are given in Table 14, Program, Erase Times and Program/Erase Endurance Cycles. See Appendix C, Figure 23, Quadruple Word Program Flowchart and Pseudo Code, for the flowchart for using the Quadruple Word Program command. Enhanced Factory Program Command The Enhanced Factory Program command can be used to program large streams of data within any one block. It greatly reduces the total programming time when a large number of Words are written to a block at any one time. Dual operations are not supported during the Enhanced Factory Program operation and the command cannot be suspended. For optimum performance the Enhanced Factory Program commands should be limited to a maximum of 10 program/erase cycles per block. If this limit is exceeded the internal algorithm will continue to work properly but some degradation in performance is possible. Typical Program times are given in Table 14. The Enhanced Factory Program command has four phases: the Setup Phase, the Program Phase to program the data to the memory, the Verify Phase to check that the data has been correctly programmed and reprogram if necessary and the Exit Phase. Refer to Table 7, Enhanced Factory Program Command and Figure 29, Enhanced Factory Program Flowchart. Setup Phase. The Enhanced Factory Program command requires two Bus Write operations to initiate the command. ■ The first bus cycle sets up the Enhanced Factory Program command. ■ The second bus cycle confirms the command. The Status Register P/E.C. Bit 7 should be read to check that the P/E.C. is ready. After the confirm command is issued, read operations output the Status Register data. The read Status Register command must not be issued as it will be interpreted as data to program. Program Phase. The Program Phase requires n+1 cycles, where n is the number of Words (refer to Table 7, Enhanced Factory Program Command and Figure 29, Enhanced Factory Program Flowchart). Three successive steps are required to issue and execute the Program Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word to be programmed. The Status Register Bank Write Status bit SR0 should be read to check that the P/E.C. is ready for the next Word. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address can either remain the Start Address, in which case the P/E.C. increments the address location or the address can be incremented in which case the P/E.C. jumps to the new address. If any address that is not in the same block as the Start Address is given with data FFFFh, the Program Phase terminates and the Verify Phase begins. The Status Register bit SR0 should be read between each Bus Write cycle to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the programming phase. If the data is not FFFFh, the command is ignored. The memory is now set to enter the Verify Phase. Verify Phase. The Verify Phase is similar to the Program Phase in that all Words must be resent to the memory for them to be checked against the programmed data. The Program/Erase Controller checks the stream of data with the data that was programmed in the Program Phase and reprograms the memory location if necessary. Three successive steps are required to execute the Verify Phase of the command. 1. Use one Bus Write operation to latch the Start Address and the first Word, to be verified. The Status Register bit SR0 should be read to check that the Program/Erase Controller is ready for the next Word. ■ 19/82 M58WR064ET, M58WR064EB 2. Each subsequent Word to be verified is latched with a new Bus Write operation. The Words must be written in the same order as in the Program Phase. The address can remain the Start Address or be incremented. If any address that is not in the same block as the Start Address is given with data FFFFh, the Verify Phase terminates. Status Register bit SR0 should be read to check that the P/E.C. is ready for the next Word. 3. Finally, after all Words have been verified, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Verify Phase. If the Verify Phase is successfully completed the memory remains in Read Status Register mode. If the Program/Erase Controller fails to reprogram a given location, the error will be signaled in the Status Register. Exit Phase. Status Register P/E.C. bit SR7 set to ‘1’ indicates that the device has returned to Read mode. A full Status Register check should be done to ensure that the block has been successfully programmed. See the section on the Status Register for more details. Quadruple Enhanced Factory Program Command The Quadruple Enhanced Factory Program command can be used to program one or more pages of four adjacent Words in parallel. The four Words must differ only for the addresses A0 and A1. Dual operations are not supported during Quadruple Enhanced Factory Program operations and the command cannot be suspended. The Quadruple Enhanced Factory Program command has four phases: the Setup Phase, the Load Phase where the data is loaded into the buffer, the combined Program and Verify Phase where the loaded data is programmed to the memory and then automatically checked and reprogrammed if necessary and the Exit Phase. Unlike the Enhanced Factory Program it is not necessary to resubmit the data for the Verify Phase. The Load Phase and the Program and Verify Phase can be repeated to program any number of pages within the block. Setup Phase. The Quadruple Enhanced Factory Program command requires one Bus Write operation to initiate the load phase. After the setup command is issued, read operations output the Status Register data. The Read Status Register command must not be issued as it will be interpreted as data to program. Load Phase. The Load Phase requires 4 cycles to load the data (refer to Table 7, Factory Program Commands and Figure 30, Quadruple Enhanced Factory Program Flowchart). Once the first Word 20/82 of each Page is written it is impossible to exit the Load phase until all four Words have been written. Two successive steps are required to issue and execute the Load Phase of the Quadruple Enhanced Factory Program command. 1. Use one Bus Write operation to latch the Start Address and the first Word of the first Page to be programmed. For subsequent Pages the first Word address can remain the Start Address (in which case the next Page is programmed) or can be any address in the same block. If any address with data FFFFh is given that is not in the same block as the Start Address, the device enters the Exit Phase. For the first Load Phase Status Register bit SR7 should be read after the first Word has been issued to check that the command has been accepted (bit SR7 set to ‘0’). This check is not required for subsequent Load Phases. 2. Each subsequent Word to be programmed is latched with a new Bus Write operation. The address is only checked for the first Word of each Page as the order of the Words to be programmed is fixed. The memory is now set to enter the Program and Verify Phase. Program and Verify Phase. In the Program and Verify Phase the four Words that were loaded in the Load Phase are programmed in the memory array and then verified by the Program/Erase Controller. If any errors are found the Program/Erase Controller reprograms the location. During this phase the Status Register shows that the Program/Erase Controller is busy, Status Register bit SR7 set to ‘0’, and that the device is not waiting for new data, Status Register bit SR0 set to ‘1’. When Status Register bit SR0 is set to ‘0’ the Program and Verify phase has terminated. Once the Verify Phase has successfully completed subsequent pages in the same block can be loaded and programmed. The device returns to the beginning of the Load Phase by issuing one Bus Write operation to latch the Address and the first of the four new Words to be programmed. Exit Phase. Finally, after all the pages have been programmed, write one Bus Write operation with data FFFFh to any address outside the block containing the Start Address, to terminate the Load and Program and Verify Phases. Status Register bit SR7 set to ‘1’ and bit SR0 set to ‘0’ indicate that the Quadruple Enhanced Factory Program command has terminated. A full Status Register check should be done to ensure that the block has been sucessfully programmed. See the section on the Status Register for more details. If the Program and Verify Phase has successfully completed the memory returns to Read mode. If M58WR064ET, M58WR064EB the P/E.C. fails to program and reprogram a given location, the error will be signaled in the Status Register. Table 7. Factory Program Commands Phase Cycles Command Bus Write Operations 1st 2nd 3rd Add Data Add Data Final -1 Add Data Final Add Data Add Data WA3 PD3 WA4 PD4 Bank Erase 2 BKA 80h BKA D0h Double Word Program(4) 3 BKA or WA1(8) 35h WA1 PD1 WA2 PD2 Quadruple Word Program(5) 5 BKA or WA1(8) 56h WA1 PD1 WA2 PD2 2+ n+1 BKA or WA1(8) 30h BA or WA1(9) D0h WA1(2) PD1 WAn(3) PAn NOT FFFFh WA1(2) n+1 WA1(2) PD1 WA2(3) PD2 WA3(3) PD3 WAn(3) PAn NOT FFFFh WA1(2) 5 BKA or WA1(8) 75h WA1(2) PD1 WA2(7) PD2 WA3(7) PD3 WA4(7) Enhanced Setup, Program Factory (6) Program Verify, Exit Setup, first Load First Program & Quadruple Verify Enhanced Subsequent Factory Program Loads (5,6) Automatic 4 WA1i (2) PD1i Subsequent Program & Verify Exit PD4 WA2i (7) PD2i WA3i (7) PD3i WA4i (7) PD4i Automatic 1 NOT WA1 FFFFh (2) Note: 1. 2. 3. 4. 5. 6. WA=Word Address in targeted bank, BKA= Bank Address, PD=Program Data, BA=Block Address. WA1 is the Start Address. NOT WA1 is any address that is not in the same block as WA1. Address can remain Starting Address WA1 or be incremented. Word Addresses 1 and 2 must be consecutive Addresses differing only for A0. Word Addresses 1,2,3 and 4 must be consecutive Addresses differing only for A0 and A1. A Bus Read must be done between each Write cycle where the data is programmed or verified to read the Status Register and check that the memory is ready to accept the next data. n = number of Words, i = number of Pages to be programmed. 7. Address is only checked for the first Word of each Page as the order to program the Words in each page is fixed so subsequent Words in each Page can be written to any address. 8. Any address within the bank can be used. 9. Any address within the block can be used. 21/82 M58WR064ET, M58WR064EB STATUS REGISTER The Status Register provides information on the current or previous Program or Erase operations. Issue a Read Status Register command to read the contents of the Status Register, refer to Read Status Register Command section for more details. To output the contents, the Status Register is latched and updated on the falling edge of the Chip Enable or Output Enable signals and can be read until Chip Enable or Output Enable returns to VIH. The Status Register can only be read using single asynchronous or single synchronous reads. Bus Read operations from any address within the bank, always read the Status Register during Program and Erase operations. The various bits convey information about the status and any errors of the operation. Bits SR7, SR6, SR2 and SR0 give information on the status of the device and are set and reset by the device. Bits SR5, SR4, SR3 and SR1 give information on errors, they are set by the device but must be reset by issuing a Clear Status Register command or a hardware reset. If an error bit is set to ‘1’ the Status Register should be reset before issuing another command. SR7 to SR1 refer to the status of the device while SR0 refers to the status of the addressed bank. The bits in the Status Register are summarized in Table 8, Status Register Bits. Refer to Table 8 in conjunction with the following text descriptions. Program/Erase Controller Status Bit (SR7). The Program/Erase Controller Status bit indicates whether the Program/Erase Controller is active or inactive in any bank. When the Program/Erase Controller Status bit is Low (set to ‘0’), the Program/Erase Controller is active; when the bit is High (set to ‘1’), the Program/Erase Controller is inactive, and the device is ready to process a new command. The Program/Erase Controller Status is Low immediately after a Program/Erase Suspend command is issued until the Program/Erase Controller pauses. After the Program/Erase Controller pauses the bit is High. During Program, Erase, operations the Program/ Erase Controller Status bit can be polled to find the end of the operation. Other bits in the Status Register should not be tested until the Program/Erase Controller completes the operation and the bit is High. After the Program/Erase Controller completes its operation the Erase Status, Program Status, VPP Status and Block Lock Status bits should be tested for errors. Erase Suspend Status Bit (SR6). The Erase Suspend Status bit indicates that an Erase operation has been suspended or is going to be sus- 22/82 pended in the addressed block. When the Erase Suspend Status bit is High (set to ‘1’), a Program/ Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Erase Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR7 is set within the Erase Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Erase Suspend Status bit returns Low. Erase Status Bit (SR5). The Erase Status bit can be used to identify if the memory has failed to verify that the block or bank has erased correctly. When the Erase Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the block or bank and still failed to verify that it has erased correctly. The Erase Status bit should be read once the Program/ Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Erase Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Status Bit (SR4). The Program Status bit is used to identify a Program failure or an attempt to program a ‘1’ to an already programmed bit when V PP = VPPH. When the Program Status bit is High (set to ‘1’), the Program/Erase Controller has applied the maximum number of pulses to the byte and still failed to verify that it has programmed correctly. After an attempt to program a '1' to an already programmed bit, the Program Status bit SR4 only goes High (set to '1') if V PP = VPPH (if V PP is different from VPPH, SR4 remains Low (set to '0') and the attempt is not shown). The Program Status bit should be read once the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). Once set High, the Program Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. VPP Status Bit (SR3). The V PP Status bit can be used to identify an invalid voltage on the VPP pin during Program and Erase operations. The VPP pin is only sampled at the beginning of a Program M58WR064ET, M58WR064EB or Erase operation. Indeterminate results can occur if V PP becomes invalid during an operation. When the VPP Status bit is Low (set to ‘0’), the voltage on the V PP pin was sampled at a valid voltage; when the V PP Status bit is High (set to ‘1’), the VPP pin has a voltage that is below the V PP Lockout Voltage, VPPLK, the memory is protected and Program and Erase operations cannot be performed. Once set High, the V PP Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new Program or Erase command is issued, otherwise the new command will appear to fail. Program Suspend Status Bit (SR2). The Program Suspend Status bit indicates that a Program operation has been suspended in the addressed block. When the Program Suspend Status bit is High (set to ‘1’), a Program/Erase Suspend command has been issued and the memory is waiting for a Program/Erase Resume command. The Program Suspend Status should only be considered valid when the Program/Erase Controller Status bit is High (Program/Erase Controller inactive). SR2 is set within the Program Suspend Latency time of the Program/Erase Suspend command being issued therefore the memory may still complete the operation rather than entering the Suspend mode. When a Program/Erase Resume command is issued the Program Suspend Status bit returns Low. Block Protection Status Bit (SR1). The Block Protection Status bit can be used to identify if a Program or Block Erase operation has tried to modify the contents of a locked block. When the Block Protection Status bit is High (set to ‘1’), a Program or Erase operation has been attempted on a locked block. Once set High, the Block Protection Status bit can only be reset Low by a Clear Status Register command or a hardware reset. If set High it should be reset before a new command is issued, otherwise the new command will appear to fail. Bank Write/Multiple Word Program Status Bit (SR0). The Bank Write Status bit indicates whether the addressed bank is programming or erasing. In Enhanced Factory Program mode the Multiple Word Program bit shows if a Word has finished programming or verifying depending on the phase. The Bank Write Status bit should only be considered valid when the Program/Erase Controller Status SR7 is Low (set to ‘0’). When both the Program/Erase Controller Status bit and the Bank Write Status bit are Low (set to ‘0’), the addressed bank is executing a Program or Erase operation. When the Program/Erase Controller Status bit is Low (set to ‘0’) and the Bank Write Status bit is High (set to ‘1’), a Program or Erase operation is being executed in a bank other than the one being addressed. In Enhanced Factory Program mode if Multiple Word Program Status bit is Low (set to ‘0’), the device is ready for the next Word, if the Multiple Word Program Status bit is High (set to ‘1’) the device is not ready for the next Word. Note: Refer to Appendix C, Flowcharts and Pseudo Codes, for using the Status Register. 23/82 M58WR064ET, M58WR064EB Table 8. Status Register Bits Bit SR7 SR6 SR5 SR4 SR3 SR2 SR1 Name P/E.C. Status Erase Suspend Status Erase Status Program Status VPP Status Type Logic Level Definition ’1’ Ready ’0’ Busy ’1’ Erase Suspended ’0’ Erase In progress or Completed ’1’ Erase Error ’0’ Erase Success ’1’ Program Error ’0’ Program Success ’1’ VPP Invalid, Abort ’0’ VPP OK ’1’ Program Suspended ’0’ Program In Progress or Completed ’1’ Program/Erase on protected Block, Abort ’0’ No operation to protected blocks Status Status Error Error Error Program Suspend Status Status Block Protection Status Error SR7 = ‘0’ Program or erase operation in addressed bank ’0’ SR7 = ‘1’ No Program or erase operation in the device Bank Write Status Status SR7 = ‘0’ '1' Program or erase operation in a bank other than the addressed bank SR7 = ‘1’ Not Allowed SR0 SR7 = ‘0’ Multiple Word Program Status (Enhanced Factory Program mode) the device is NOT ready for the next word '1' SR7 = ‘1’ Not Allowed Status SR7 = ‘0’ the device is ready for the next Word '0' SR7 = ‘1’ the device is exiting from EFP Note: Logic level ’1’ is High, ’0’ is Low. 24/82 M58WR064ET, M58WR064EB CONFIGURATION REGISTER The Configuration Register is used to configure the type of bus access that the memory will perform. Refer to Read Modes section for details on read operations. The Configuration Register is set through the Command Interface. After a Reset or Power-Up the device is configured for asynchronous page read (CR15 = 1). The Configuration Register bits are described in Table 9. They specify the selection of the burst length, burst type, burst X latency and the Read operation. Refer to Figures 6 and 7 for examples of synchronous burst configurations. Read Select Bit (CR15) The Read Select bit, CR15, is used to switch between asynchronous and synchronous Bus Read operations. When the Read Select bit is set to ’1’, read operations are asynchronous; when the Read Select bit is set to ’0’, read operations are synchronous. Synchronous Burst Read is supported in both parameter and main blocks and can be performed across banks. On reset or power-up the Read Select bit is set to’1’ for asynchronous access. X-Latency Bits (CR13-CR11) The X-Latency bits are used during Synchronous Read operations to set the number of clock cycles between the address being latched and the first data becoming available. For correct operation the X-Latency bits can only assume the values in Table 9, Configuration Register. The correspondence between X-Latency settings and the maximum sustainable frequency must be calculated taking into account some system parameters. Two conditions must be satisfied: 1. Depending on whether tAVK_CPU or t DELAY is supplied either one of the following two equations must be satisfied: (n + 1) t K ≥ tACC - tAVK_CPU + tQVK_CPU (n + 2) tK ≥ tACC + tDELAY + tQVK_CPU 2. and also tK > tKQV + tQVK_CPU where n is the chosen X-Latency configuration code tK is the clock period tAVK_CPU is clock to address valid, L Low, or E Low, whichever occurs last tDELAY is address valid, L Low, or E Low to clock, whichever occurs last tQVK_CPU is the data setup time required by the system CPU, tKQV is the clock to data valid time tACC is the random access time of the device. Refer to Figure 6, X-Latency and Data Output Configuration Example. Wait Polarity Bit (CR10) In synchronous burst mode the Wait signal indicates whether the output data are valid or a WAIT state must be inserted. The Wait Polarity bit is used to set the polarity of the Wait signal. When the Wait Polarity bit is set to ‘0’ the Wait signal is active Low. When the Wait Polarity bit is set to ‘1’ the Wait signal is active High (default). Data Output Configuration Bit (CR9) The Data Output Configuration bit determines whether the output remains valid for one or two clock cycles. When the Data Output Configuration Bit is ’0’ the output data is valid for one clock cycle, when the Data Output Configuration Bit is ’1’ the output data is valid for two clock cycles. The Data Output Configuration depends on the condition: ■ tK > tKQV + tQVK_CPU where t K is the clock period, tQVK_CPU is the data setup time required by the system CPU and tKQV is the clock to data valid time. If this condition is not satisfied, the Data Output Configuration bit should be set to ‘1’ (two clock cycles). Refer to Figure 6, X-Latency and Data Output Configuration Example. Wait Configuration Bit (CR8) In burst mode the Wait bit controls the timing of the Wait output pin, WAIT. When WAIT is asserted, Data is Not Valid and when WAIT is deasserted, Data is Valid. When the Wait bit is ’0’ the Wait output pin is asserted during the wait state. When the Wait bit is ’1’ (default) the Wait output pin is asserted one clock cycle before the wait state. Burst Type Bit (CR7) The Burst Type bit is used to configure the sequence of addresses read as sequential or interleaved. When the Burst Type bit is ’0’ the memory outputs from interleaved addresses; when the Burst Type bit is ’1’ (default) the memory outputs from sequential addresses. See Tables 10, Burst Type Definition, for the sequence of addresses output from a given starting address in each mode. Valid Clock Edge Bit (CR6) The Valid Clock Edge bit, CR6, is used to configure the active edge of the Clock, K, during Synchronous Burst Read operations. When the Valid Clock Edge bit is ’0’ the falling edge of the Clock is the active edge; when the Valid Clock Edge bit is ’1’ the rising edge of the Clock is active. Wrap Burst Bit (CR3) The burst reads can be confined inside the 4 or 8 Word boundary (wrap) or overcome the boundary 25/82 M58WR064ET, M58WR064EB (no wrap). The Wrap Burst bit is used to select between wrap and no wrap. When the Wrap Burst bit is set to ‘0’ the burst read wraps; when it is set to ‘1’ the burst read does not wrap. Burst length Bits (CR2-CR0) The Burst Length bits set the number of Words to be output during a Synchronous Burst Read operation as result of a single address latch cycle. They can be set for 4 words, 8 words or continuous burst, where all the words are read sequentially. In continuous burst mode the burst sequence can cross bank boundaries. In continuous burst mode or in 4, 8 words no-wrap, depending on the starting address, the device as- 26/82 serts the WAIT output to indicate that a delay is necessary before the data is output. If the starting address is aligned to a 4 word boundary no wait states are needed and the WAIT output is not asserted. If the starting address is shifted by 1,2 or 3 positions from the four word boundary, WAIT will be asserted for 1, 2 or 3 clock cycles when the burst sequence crosses the first 64 word boundary, to indicate that the device needs an internal delay to read the successive words in the array. WAIT will be asserted only once during a continuous burst access. See also Table 10, Burst Type Definition. CR14, CR5 and CR4 are reserved for future use. M58WR064ET, M58WR064EB Table 9. Configuration Register Bit CR15 Description Value 0 Synchronous Read 1 Asynchronous Read (Default at power-on) Read Select CR14 CR13-CR11 Description Reserved 010 2 clock latency 011 3 clock latency 100 4 clock latency 101 5 clock latency 111 Reserved (default) X-Latency Other configurations reserved CR10 CR9 CR8 CR7 CR6 0 WAIT is active Low 1 WAIT is active high (default) 0 Data held for one clock cycle 1 Data held for two clock cycles (default) 0 WAIT is active during wait state 1 WAIT is active one data cycle before wait state (default) 0 Interleaved 1 Sequential (default) 0 Falling Clock edge 1 Rising Clock edge (default) Wait Polarity Data Output Configuration Wait Configuration Burst Type Valid Clock Edge CR5-CR4 CR3 CR2-CR0 Reserved 0 Wrap 1 No Wrap (default) 001 4 words 010 8 words 111 Continuous (CR7 must be set to ‘1’) (default) Wrap Burst Burst Length 27/82 M58WR064ET, M58WR064EB Mode Table 10. Burst Type Definition Start Address 4 Words 8 Words Continuous Burst Sequential Interleaved Sequential Interleaved 0 0-1-2-3 0-1-2-3 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6-7 0-1-2-3-4-5-6... 1 1-2-3-0 1-0-3-2 1-2-3-4-5-6-7-0 1-0-3-2-5-4-7-6 1-2-3-4-5-6-7... 2 2-3-0-1 2-3-0-1 2-3-4-5-6-7-0-1 2-3-0-1-6-7-4-5 2-3-4-5-6-7-8... 3 3-0-1-2 3-2-1-0 3-4-5-6-7-0-1-2 3-2-1-0-7-6-5-4 3-4-5-6-7-8-9... 7-4-5-6 7-6-5-4 7-0-1-2-3-4-5-6 7-6-5-4-3-2-1-0 7-8-9-10-11-12-13... Wrap ... 7 ... 60 60-61-62-63-64-65-66... 61 61-62-63-WAIT-64-65-66... 62 62-63-WAIT-WAIT-64-65-66... 63 63-WAIT-WAIT-WAIT-64-6566... Sequential Interleaved Sequential 0 0-1-2-3 0-1-2-3-4-5-6-7 1 1-2-3-4 1-2-3-4-5-6-7-8 2 2-3-4-5 2-3-4-5-6-7-8-9... 3 3-4-5-6 3-4-5-6-7-8-9-10 7-8-9-10 7-8-9-10-11-12-13-14 60 60-61-62-63 60-61-62-63-64-65-6667 61 61-62-63-WAIT-64 61-62-63-WAIT-64-6566-67-68 62 62-63-WAIT-WAIT64-65 62-63-WAIT-WAIT-6465-66-67-68-69 63 63-WAIT-WAITWAIT-64-65-66 63-WAIT-WAIT-WAIT64-65-66-67-68-69-70 Interleaved No-wrap ... 28/82 7 ... Same as for Wrap (Wrap /No Wrap has no effect on Continuous Burst ) M58WR064ET, M58WR064EB Figure 6. X-Latency and Data Output Configuration Example X-latency 1st cycle 2nd cycle 3rd cycle 4th cycle K E L A21-A0 tDELAY VALID ADDRESS tAVK_CPU tQVK_CPU tK tKQV tACC tQVK_CPU DQ15-DQ0 VALID DATA VALID DATA Note. Settings shown: X-latency = 4, Data Output held for one clock cycle AI06182 Figure 7. Wait Configuration Example E K L A21-A0 DQ15-DQ0 VALID ADDRESS VALID DATA VALID DATA NOT VALID VALID DATA WAIT CR8 = '0' CR10 = '0' WAIT CR8 = '1' CR10 = '0' WAIT CR8 = '0' CR10 = '1' WAIT CR8 = '1' CR10 = '1' AI06972 29/82 M58WR064ET, M58WR064EB READ MODES Read operations can be performed in two different ways depending on the settings in the Configuration Register. If the clock signal is ‘don’t care’ for the data output, the read operation is Asynchronous; if the data output is synchronized with clock, the read operation is Synchronous. The Read mode and data output format are determined by the Configuration Register. (See Configuration Register section for details). All banks supports both asynchronous and synchronous read operations. The Multiple Bank architecture allows read operations in one bank, while write operations are being executed in another (see Tables 11 and 12). Asynchronous Read Mode In Asynchronous Read operations the clock signal is ‘don’t care’. The device outputs the data corresponding to the address latched, that is the memory array, Status Register, Common Flash Interface or Electronic Signature depending on the command issued. CR15 in the Configuration Register must be set to ‘1’ for Asynchronous operations. In Asynchronous Read mode a Page of data is internally read and stored in a Page Buffer. The Page has a size of 4 Words and is addressed by A0 and A1 address inputs. The address inputs A0 and A1 are not gated by Latch Enable in Asynchronous Read mode. The first read operation within the Page has a longer access time (Tacc, Random access time), subsequent reads within the same Page have much shorter access times. If the Page changes then the normal, longer timings apply again. Asynchronous Read operations can be performed in two different ways, Asynchronous Random Access Read and Asynchronous Page Read. Only Asynchronous Page Read takes full advantage of the internal page storage so different timings are applied. During Asynchronous Read operations, after a bus inactivity of 150ns, the device automatically switches to the Automatic Standby mode. In this condition the power consumption is reduced to the standby value and the outputs are still driven. In Asynchronous Read mode, the WAIT signal is always asserted. See Table 20, Asynchronous Read AC Characteristics, Figure 10, Asynchronous Random Access Read AC Waveform and Figure 11, Asynchronous Page Read AC Waveform for details. Synchronous Burst Read Mode In Synchronous Burst Read mode the data is output in bursts synchronized with the clock. It is pos- 30/82 sible to perform burst reads across bank boundaries. Synchronous Burst Read mode can only be used to read the memory array. For other read operations, such as Read Status Register, Read CFI and Read Electronic Signature, Single Synchronous Read or Asynchronous Random Access Read must be used. In Synchronous Burst Read mode the flow of the data output depends on parameters that are configured in the Configuration Register. A burst sequence is started at the first clock edge (rising or falling depending on Valid Clock Edge bit CR6 in the Configuration Register) after the falling edge of Latch Enable or Chip Enable, whichever occurs last. Addresses are internally incremented and after a delay of 2 to 5 clock cycles (X latency bits CR13-CR11) the corresponding data are output on each clock cycle. The number of Words to be output during a Synchronous Burst Read operation can be configured as 4 or 8 Words or Continuous (Burst Length bits CR2-CR0). The data can be configured to remain valid for one or two clock cycles (Data Output Configuration bit CR9). The order of the data output can be modified through the Burst Type and the Wrap Burst bits in the Configuration Register. The burst sequence may be configured to be sequential or interleaved (CR7). The burst reads can be confined inside the 4 or 8 Word boundary (Wrap) or overcome the boundary (No Wrap). If the starting address is aligned to the Burst Length (4 or 8 Words), the wrapped configuration has no impact on the output sequence. Interleaved mode is not allowed in Continuous Burst Read mode or with No Wrap sequences. A WAIT signal may be asserted to indicate to the system that an output delay will occur. This delay will depend on the starting address of the burst sequence; the worst case delay will occur when the sequence is crossing a 64 word boundary and the starting address was at the end of a four word boundary. WAIT is asserted during X latency, the Wait state and at the end of 4- and 8-Word burst. It is only deasserted when output data are valid. In Continuous Burst Read mode a Wait state will occur when crossing the first 64 Word boundary. If the burst starting address is aligned to a 4 Word Page, the Wait state will not occur. The WAIT signal can be configured to be active Low or active High (default) by setting CR10 in the Configuration Register. The WAIT signal is meaningful only in Synchronous Burst Read mode, in M58WR064ET, M58WR064EB other modes, WAIT is always asserted (except for Read Array mode). See Table 21, Synchronous Read AC Characteristics and Figure 12, Synchronous Burst Read AC Waveform for details. Single Synchronous Read Mode Single Synchronous Read operations are similar to Synchronous Burst Read operations except that only the first data output after the X latency is valid. Synchronous Single Reads are used to read the Electronic Signature, Status Register, CFI, Block Protection Status, Configuration Register Status or Protection Register. When the addressed bank is in Read CFI, Read Status Register or Read Electronic Signature mode, the WAIT signal is always asserted. See Table 21, Synchronous Read AC Characteristics and Figure 13, Single Synchronous Read AC Waveform for details. DUAL OPERATIONS AND MULTIPLE BANK ARCHITECTURE The Multiple Bank Architecture of the the Program or Erase operation can be suspendM58WR064E provides flexibility for software deed. Also if the suspended operation was Erase velopers by allowing code and data to be split with then a Program command can be issued to anoth4Mbit granularity. The Dual Operations feature er block, so the device can have one block in simplifies the software management of the device Erase Suspend mode, one programming and othand allows code to be executed from one bank er banks in Read mode. Bus Read operations are while another bank is being programmed or allowed in another bank between setup and conerased. firm cycles of program or erase operations. The combination of these features means that read opThe Dual operations feature means that while proerations are possible at any moment. gramming or erasing in one bank, Read operations are possible in another bank with zero Tables 11 and 12 show the dual operations possilatency (only one bank at a time is allowed to be in ble in other banks and in the same bank. For a Program or Erase mode). If a Read operation is recomplete list of possible commands refer to Apquired in a bank which is programming or erasing, pendix D, Command Interface State Tables. Table 11. Dual Operations Allowed In Other Banks Commands allowed in another bank Read Array Read Status Register Read CFI Query Idle Yes Yes Yes Yes Yes Yes Yes Yes Programming Yes Yes Yes Yes – – Yes – Erasing Yes Yes Yes Yes – – Yes – Program Suspended Yes Yes Yes Yes – – – Yes Erase Suspended Yes Yes Yes Yes Yes – – Yes Block Erase Program/ Erase Suspend Program/ Erase Resume Status of bank Read Electronic Program Signature Block Erase Program/ Program/ Erase Erase Suspend Resume Table 12. Dual Operations Allowed In Same Bank Commands allowed in same bank Status of bank Read Array Read Read Read Status Electronic Program CFI Query Register Signature Idle Yes Yes Yes Yes Yes Yes Yes Yes Programming –(2) Yes Yes Yes – – Yes – Erasing –(2) Yes Yes Yes – – Yes – Program Suspended Yes(1) Yes Yes Yes – – – Yes Erase Suspended Yes(1) Yes Yes Yes Yes(1) – – Yes Note: 1. Not allowed in the Block or Word that is being erased or programmed. 2. The Read Array command is accepted but the data output is not guaranteed until the Program or Erase has completed. 31/82 M58WR064ET, M58WR064EB BLOCK LOCKING The M58WR064E features an instant, individual block locking scheme that allows any block to be locked or unlocked with no latency. This locking scheme has three levels of protection. ■ Lock/Unlock - this first level allows softwareonly control of block locking. ■ ■ Lock-Down - this second level requires hardware interaction before locking can be changed. VPP ≤ VPPLK - the third level offers a complete hardware protection against program and erase on all blocks. The protection status of each block can be set to Locked, Unlocked, and Lock-Down. Table 13, defines all of the possible protection states (WP, DQ1, DQ0), and Appendix C, Figure 27, shows a flowchart for the locking operations. Reading a Block’s Lock Status The lock status of every block can be read in the Read Electronic Signature mode of the device. To enter this mode write 90h to the device. Subsequent reads at the address specified in Table 6, will output the protection status of that block. The lock status is represented by DQ0 and DQ1. DQ0 indicates the Block Lock/Unlock status and is set by the Lock command and cleared by the Unlock command. It is also automatically set when entering Lock-Down. DQ1 indicates the Lock-Down status and is set by the Lock-Down command. It cannot be cleared by software, only by a hardware reset or power-down. The following sections explain the operation of the locking system. Locked State The default status of all blocks on power-up or after a hardware reset is Locked (states (0,0,1) or (1,0,1)). Locked blocks are fully protected from any program or erase. Any program or erase operations attempted on a locked block will return an error in the Status Register. The Status of a Locked block can be changed to Unlocked or Lock-Down using the appropriate software commands. An Unlocked block can be Locked by issuing the Lock command. Unlocked State Unlocked blocks (states (0,0,0), (1,0,0) (1,1,0)), can be programmed or erased. All unlocked blocks return to the Locked state after a hardware reset or when the device is powered-down. The status of an unlocked block can be changed to 32/82 Locked or Locked-Down using the appropriate software commands. A locked block can be unlocked by issuing the Unlock command. Lock-Down State Blocks that are Locked-Down (state (0,1,x))are protected from program and erase operations (as for Locked blocks) but their protection status cannot be changed using software commands alone. A Locked or Unlocked block can be Locked-Down by issuing the Lock-Down command. LockedDown blocks revert to the Locked state when the device is reset or powered-down. The Lock-Down function is dependent on the WP input pin. When WP=0 (VIL), the blocks in the Lock-Down state (0,1,x) are protected from program, erase and protection status changes. When WP=1 (V IH) the Lock-Down function is disabled (1,1,x) and Locked-Down blocks can be individually unlocked to the (1,1,0) state by issuing the software command, where they can be erased and programmed. These blocks can then be re-locked (1,1,1) and unlocked (1,1,0) as desired while WP remains high. When WP is low , blocks that were previously Locked-Down return to the Lock-Down state (0,1,x) regardless of any changes made while WP was high. Device reset or power-down resets all blocks , including those in Lock-Down, to the Locked state. Locking Operations During Erase Suspend Changes to block lock status can be performed during an erase suspend by using the standard locking command sequences to unlock, lock or lock-down a block. This is useful in the case when another block needs to be updated while an erase operation is in progress. To change block locking during an erase operation, first write the Erase Suspend command, then check the status register until it indicates that the erase operation has been suspended. Next write the desired Lock command sequence to a block and the lock status will be changed. After completing any desired lock, read, or program operations, resume the erase operation with the Erase Resume command. If a block is locked or locked-down during an erase suspend of the same block, the locking status bits will be changed immediately, but when the erase is resumed, the erase operation will complete. Locking operations cannot be performed during a program suspend. Refer to Appendix , Command Interface State Table, for detailed information on which commands are valid during erase suspend. M58WR064ET, M58WR064EB Table 13. Lock Status Current Protection Status(1) (WP, DQ1, DQ0) Next Protection Status(1) (WP, DQ1, DQ0) Current State Program/Erase Allowed After Block Lock Command After Block Unlock Command After Block Lock-Down Command After WP transition 1,0,0 yes 1,0,1 1,0,0 1,1,1 0,0,0 1,0,1(2) no 1,0,1 1,0,0 1,1,1 0,0,1 1,1,0 yes 1,1,1 1,1,0 1,1,1 0,1,1 1,1,1 no 1,1,1 1,1,0 1,1,1 0,1,1 0,0,0 yes 0,0,1 0,0,0 0,1,1 1,0,0 0,0,1(2) no 0,0,1 0,0,0 0,1,1 1,0,1 0,1,1 no 0,1,1 0,1,1 0,1,1 1,1,1 or 1,1,0 (3) Note: 1. The lock status is defined by the write protect pin and by DQ1 (‘1’ for a locked-down block) and DQ0 (‘1’ for a locked block) as read in the Read Electronic Signature command with A1 = VIH and A0 = VIL. 2. All blocks are locked at power-up, so the default configuration is 001 or 101 according to WP status. 3. A WP transition to VIH on a locked block will restore the previous DQ0 value, giving a 111 or 110. 33/82 M58WR064ET, M58WR064EB PROGRAM AND ERASE TIMES AND ENDURANCE CYCLES The Program and Erase times and the number of of Program/ Erase cycles depends on the voltage Program/ Erase cycles per block are shown in Tasupply used. ble 14. In the M58WR064E the maximum number Table 14. Program, Erase Times and Program, Erase Endurance Cycles Typ Typical after 100k W/E Cycles Max Unit 0.3 1 2.5 s Preprogrammed 0.8 3 4 s Not Preprogrammed 1.1 4 s Parameter Condition Min Parameter Block (4 KWord) Erase(2) Main Block (32 KWord) Erase Preprogrammed 3 s 4.5 s Parameter Block (4 KWord) Program(3) 40 ms Main Block (32 KWord) Program(3) 300 ms Word Program (3) 10 Program Suspend Latency Erase Suspend Latency Bank (4Mbit) Erase VPP = VDD Not Preprogrammed 10 100 µs 5 10 µs 5 20 µs Main Blocks 100,000 cycles Parameter Blocks 100,000 cycles Program/Erase Cycles (per Block) Parameter Block (4 KWord) Erase 0.3 2.5 s Main Block (32 KWord) Erase 0.9 4 s Bank (4Mbit) Erase 3.5 s t.b.a.(4) s 510 ms VPP = VPPH Bank (4Mbit) Program (Quad-Enhanced Factory Program)(5) 4Mbit Program Quadruple Word(5) Word/ Double Word/ Quadruple Word Program(3, 5) 8 Parameter Block (4 KWord) Program(3) Quadruple Word(5) 8 ms Word 32 ms Quadruple Word(5) 64 ms Word 256 ms Main Block (32 KWord) Program(3) 100 µs Main Blocks 1000 cycles Parameter Blocks 2500 cycles Program/Erase Cycles (per Block) Note: 1. 2. 3. 4. 5. 34/82 TA = –40 to 85°C; VDD = 1.65V to 2.2V; VDDQ = 1.65V to 3.3V. The difference between Preprogrammed and not preprogrammed is not significant (‹30ms). Excludes the time needed to execute the command sequence. t.b.a. = to be announced Measurements performed at 25°C. TA = 25°C ±5°C for Quadruple Word, Double Word and Quadruple Enhanced Factory Program. M58WR064ET, M58WR064EB MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- plied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 15. Absolute Maximum Ratings Value Symbol Min Max Unit Ambient Operating Temperature –40 85 °C TBIAS Temperature Under Bias –40 125 °C TSTG Storage Temperature –65 155 °C VIO Input or Output Voltage –0.5 VDDQ+0.6 V VDD Supply Voltage –0.2 2.45 V Input/Output Supply Voltage –0.2 3.6 V Program Voltage –0.2 14 V Output Short Circuit Current 100 mA Time for VPP at VPPH 100 hours TA VDDQ VPP IO tVPPH Parameter 35/82 M58WR064ET, M58WR064EB DC AND AC PARAMETERS This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 16, Operating and AC Measurement Conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 16. Operating and AC Measurement Conditions M58WR064ET, M58WR064EB 70 80 100 Parameter Units Min Max Min Max Min Max VDD Supply Voltage 1.7 2.2 1.65 2.2 1.65 2.2 V VDDQ Supply Voltage 1.7 3.3 1.65 3.3 1.65 3.3 V VPP Supply Voltage (Factory environment) 11.4 12.6 11.4 12.6 11.4 12.6 V VPP Supply Voltage (Application environment) -0.4 VDDQ +0.4 -0.4 VDDQ +0.4 -0.4 VDDQ +0.4 V Ambient Operating Temperature – 40 85 – 40 85 – 40 85 °C Load Capacitance (CL) 30 30 Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 30 pF 5 5 5 ns 0 to VDDQ 0 to VDDQ 0 to VDDQ V VDDQ/2 VDDQ/2 VDDQ/2 V Figure 8. AC Measurement I/O Waveform Figure 9. AC Measurement Load Circuit VDDQ VDDQ VDDQ VDDQ/2 VDD 0V 16.7kΩ AI06161 DEVICE UNDER TEST CL 0.1µF 16.7kΩ 0.1µF CL includes JIG capacitance AI06162 Table 17. Capacitance Symbol CIN COUT Parameter Input Capacitance Output Capacitance Note: Sampled only, not 100% tested. 36/82 Test Condition Min Max Unit VIN = 0V 6 8 pF VOUT = 0V 8 12 pF M58WR064ET, M58WR064EB Table 18. DC Characteristics - Currents Symbol Parameter Test Condition ILI Input Leakage Current ILO Output Leakage Current Supply Current Asynchronous Read (f=6MHz) IDD1 Supply Current Synchronous Read (f=40MHz) Supply Current Synchronous Read (f=54MHz) Min Typ Max Unit 0V ≤ VIN ≤ VDDQ ±1 µA 0V ≤ VOUT ≤ VDDQ ±1 µA E = VIL, G = VIH 3 6 mA 4 Word 6 13 mA 8 Word 8 14 mA Continuous 6 10 mA 4 Word 7 16 mA 8 Word 10 18 mA Continuous 13 25 mA RP = VSS ± 0.2V 10 50 µA IDD2 Supply Current (Reset) IDD3 Supply Current (Standby) E = VDD ± 0.2V 10 50 µA IDD4 Supply Current (Automatic Standby) E = VIL, G = VIH 10 50 µA VPP = VPPH 8 15 mA VPP = VDD 10 20 mA VPP = VPPH 8 15 mA VPP = VDD 10 20 mA Program/Erase in one Bank, Asynchronous Read in another Bank 13 26 mA Program/Erase in one Bank, Synchronous Read in another Bank 16 30 mA E = VDD ± 0.2V 10 50 µA VPP = VPPH 2 5 mA VPP = VDD 0.2 5 µA VPP = VPPH 2 5 mA VPP = VDD 0.2 5 µA VPP Supply Current (Read) VPP ≤ VDD 0.2 5 µA VPP Supply Current (Standby) VPP ≤ VDD 0.2 5 µA Supply Current (Program) IDD5 (1) Supply Current (Erase) Supply Current IDD6 (1,2) (Dual Operations) IDD7(1) Supply Current Program/ Erase Suspended (Standby) VPP Supply Current (Program) IPP1(1) VPP Supply Current (Erase) IPP2 IPP3(1) Note: 1. Sampled only, not 100% tested. 2. VDD Dual Operation current is the sum of read and program or erase currents. 37/82 M58WR064ET, M58WR064EB Table 19. DC Characteristics - Voltages Symbol Parameter Test Condition Min Typ Max Unit VIL Input Low Voltage –0.5 0.4 V VIH Input High Voltage VDDQ –0.4 VDDQ + 0.4 V VOL Output Low Voltage IOL = 100µA 0.1 V VOH Output High Voltage IOH = –100µA VDDQ –0.1 VPP1 VPP Program Voltage-Logic Program, Erase 1 1.8 1.95 V VPPH VPP Program Voltage Factory Program, Erase 11.4 12 12.6 V VPPLK Program or Erase Lockout 0.9 V VLKO VDD Lock Voltage VRPH RP pin Extended High Voltage 38/82 V 1 V 3.3 V Hi-Z Hi-Z tELLH tLLLH tAVLH tAVQV tELTV tELQX tELQV tLLQV VALID Valid Address Latch Note. Write Enable, W, is High, WAIT is active Low. DQ0-DQ15 WAIT G E L A0-A21 tGLQV Outputs Enabled tGLQX tLHGL tLHAX tAVAV Data Valid VALID tAXQX tEHTZ tGHQZ tGHQX tEHQX tEHQZ Standby VALID AI06163b M58WR064ET, M58WR064EB Figure 10. Asynchronous Random Access Read AC Waveforms 39/82 40/82 Hi-Z Note 1. WAIT is active Low. DQ0-DQ15 WAIT (1) G E L A0-A1 A2-A21 tELTV tELQX tGLQV tGLQX tELQV Valid Address Latch tELLH tLLQV tLLLH tAVLH VALID ADDRESS tAVAV Enabled Outputs tLHGL tLHAX VALID DATA VALID DATA VALID ADDRESS Valid Data VALID DATA tAVQV1 VALID ADDRESS VALID ADDRESS VALID DATA VALID ADDRESS Standby AI06164b M58WR064ET, M58WR064EB Figure 11. Asynchronous Page Read AC Waveforms M58WR064ET, M58WR064EB Table 20. Asynchronous Read AC Characteristics VDDQ = 1.65V-2.2V Symbol Alt Read Timings Unit 70 80 100 70 80 100 tAVAV tRC Address Valid to Next Address Valid Min 70 80 100 70 80 100 ns tAVQV tACC Address Valid to Output Valid (Random) Max 70 80 100 70 80 100 ns tAVQV1 tPAGE Address Valid to Output Valid (Page) Max 20 25 25 25 25 25 ns tAXQX (1) tOH Address Transition to Output Transition Min 0 0 0 0 0 0 ns Chip Enable Low to Wait Valid Max 14 14 18 20 22 22 ns tELTV Latch Timings VDDQ = 2.2V-3.3V Parameter tELQV (2) tCE Chip Enable Low to Output Valid Max 70 80 100 70 80 100 ns tELQX (1) tLZ Chip Enable Low to Output Transition Min 0 0 0 0 0 0 ns Chip Enable High to Wait Hi-Z Max 17 17 20 25 25 25 ns tEHTZ tEHQX (1) tOH Chip Enable High to Output Transition Min 0 0 0 0 0 0 ns tEHQZ (1) tHZ Chip Enable High to Output Hi-Z Max 17 17 20 20 20 20 ns tGLQV (2) tOE Output Enable Low to Output Valid Max 20 25 25 30 30 30 ns tGLQX (1) tOLZ Output Enable Low to Output Transition Min 0 0 0 0 0 0 ns tGHQX(1) tOH Output Enable High to Output Transition Min 0 0 0 0 0 0 ns tGHQZ(1) tDF Output Enable High to Output Hi-Z Max 17 17 20 17 17 20 ns Min 9 9 10 10 10 12 ns tAVLH tAVADVH Address Valid to Latch Enable High tELLH tELADVH Chip Enable Low to Latch Enable High Min 10 10 10 10 10 12 ns tLHAX tADVHAX Latch Enable High to Address Transition Min 9 9 10 9 9 10 ns tLLLH tADVLAD Latch Enable Pulse Width Min 9 9 10 10 10 12 ns tLLQV tADVLQV Latch Enable Low to Output Valid (Random) Max 70 80 100 70 80 100 ns tLHGL tADVHGL Latch Enable High to Output Enable Low Min 0 0 0 0 0 0 ns VH Note: 1. Sampled only, not 100% tested. 2. G may be delayed by up to t ELQV - tGLQV after the falling edge of E without increasing tELQV . 41/82 42/82 Hi-Z tELKH Hi-Z tLLLH Address Latch tELTV tKHAX tAVKH tLLKH tAVLH VALID ADDRESS X Latency tGLQX Note 2 Note 1 VALID Valid Data Flow tKHTV tKHQV tKHQV VALID Note 2 tKHTX tKHQX tKHQX VALID Boundary Crossing Note 2 tKHTV tKHTX tKHQV tKHQX NOT VALID Data AI06980c Standby tEHTZ tGHQZ tGHQX tEHQZ tEHQX tEHEL VALID Valid Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal can be configured to be active during wait state or one cycle before. WAIT signal is active Low. 3. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge. Here the active edge of K is the rising one. WAIT G E K(3) L A0-A21 DQ0-DQ15 M58WR064ET, M58WR064EB Figure 12. Synchronous Burst Read AC Waveforms Hi-Z tELKH Hi-Z tLLLH tELTV tKHAX tAVKH tLLKH tAVLH VALID ADDRESS tGLQV tGLQX Note 1 Note 3 tKHTV tKHQV VALID NOT VALID NOT VALID NOT VALID tGHQZ tGHQX tEHEL tEHQZ AI06973c tEHTZ NOT VALID tEHQX NOT VALID Note 1. The number of clock cycles to be inserted depends on the X latency set in the Burst Configuration Register. 2. The WAIT signal is configured to be active during wait state. WAIT signal is active Low. 3. WAIT is always asserted when addressed bank is in Read CFI, Read SR or Read electronic signature mode. WAIT signals valid data if the addressed bank is in Read Array mode. 4. Address latched and data output on the rising clock edge. Either the falling or the rising edge of the clock signal, K, can be configured as the active edge. Here the active edge of K is the rising one. WAIT(2) G E K(4) L A0-A21 DQ0-DQ15 M58WR064ET, M58WR064EB Figure 13. Single Synchronous Read AC Waveforms 43/82 M58WR064ET, M58WR064EB Figure 14. Clock input AC Waveform tKHKL tKHKH tf tr tKLKH AI06981 Table 21. Synchronous Read AC Characteristics Synchronous Read Timings Symbol Alt Parameter VDDQ = 2.2V-3.3V 70 80 100 70 80 100 Unit tAVKH tAVCLKH Address Valid to Clock High Min 7 7 7 9 9 10 ns tELKH tELCLKH Chip Enable Low to Clock High Min 7 7 7 9 9 10 ns tELTV Chip Enable Low to Wait Valid Max 14 14 18 20 22 22 ns tEHEL Chip Enable Pulse Width (subsequent synchronous reads) Min 14 14 14 20 20 20 ns tEHTZ Chip Enable High to Wait Hi-Z Max 14 14 20 25 25 25 ns tKHAX tCLKHAX Clock High to Address Transition Min 9 9 10 10 10 10 ns tKHQV tKHTV tCLKHQV Clock High to Output Valid Clock High to WAIT Valid Max 14 14 18 20 22 22 ns tKHQX tKHTX tCLKHQX Clock High to Output Transition Clock High to WAIT Transition Min 4 4 4 5 5 5 ns tLLKH tADVLCLK Latch Enable Low to Clock High Min 7 7 7 10 10 10 ns - - - 30 30 ns - - - ns H Clock Period (f=33MHz) Clock Specifications VDDQ = 1.65V-2.2V tKHKH tCLK Clock Period (f=40MHz) Min Clock Period (f=54MHz) 25 18.5 18.5 tKHKL tKLKH Clock High to Clock Low Clock Low to Clock High Min 4.5 4.5 5 9.5 9.5 9.5 ns tf tr Clock Fall or Rise Time Max 3 3 3 3 5 5 ns Note: 1. Sampled only, not 100% tested. 2. For other timings please refer to Table 20, Asynchronous Read AC Characteristics. 44/82 25 K VPP WP DQ0-DQ15 W G E L A0-A21 tWHDX CONFIRM COMMAND OR DATA INPUT tVPHWH tWHQV tELKV tWHVPL tWHWPL tWHEL tWHGL tWHAV tWHAX CMD or DATA VALID ADDRESS tAVWH tWPHWH tWHWL tWHEH tWHLL tWLWH tLHAX COMMAND tLLLH SET-UP COMMAND tDVWH tGHWL tELWL tELLH tAVLH BANK ADDRESS tAVAV tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV VALID ADDRESS PROGRAM OR ERASE AI06974 M58WR064ET, M58WR064EB Figure 15. Write AC Waveforms, Write Enable Controlled 45/82 M58WR064ET, M58WR064EB Table 22. Write AC Characteristics, Write Enable Controlled M58WR064E Symbol tAVAV Alt tWC tAVLH 80 100 Address Valid to Next Address Valid Min 70 80 100 ns Address Valid to Latch Enable High Min 9 9 10 ns tWC Address Valid to Write Enable High Min 45 50 50 ns tDVWH tDS Data Valid to Write Enable High Min 45 50 50 ns Chip Enable Low to Latch Enable High Min 10 10 10 ns Chip Enable Low to Write Enable Low Min 0 0 0 ns tELQV Chip Enable Low to Output Valid Min 70 80 100 ns tELKV Chip Enable High to Clock Valid Min 9 9 9 ns tGHWL Output Enable High to Write Enable Low Min 17 17 20 ns tLHAX Latch Enable High to Address Transition Min 9 9 10 ns tLLLH Latch Enable Pulse Width Min 9 9 10 ns Write Enable High to Address Valid Min 0 0 0 ns tELWL Write Enable Controlled Timings Unit 70 tAVWH(3) tELLH tCS tWHAV(3) tWHAX(3) tAH Write Enable High to Address Transition Min 0 0 0 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 0 ns Write Enable High to Chip Enable Low Min 25 25 25 ns tWHGL Write Enable High to Output Enable Low Min 0 0 0 ns tWHLL Write Enable High to Latch Enable Low Min 0 0 0 ns Write Enable High to Write Enable Low Min 25 25 25 ns Write Enable High to Output Valid Min 95 105 125 ns Write Enable Low to Write Enable High Min 45 50 50 ns tQVVPL Output (Status Register) Valid to VPP Low Min 0 0 0 ns tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 0 0 ns VPP High to Write Enable High Min 200 200 200 ns tWHVPL Write Enable High to VPP Low Min 200 200 200 ns tWHWPL Write Enable High to Write Protect Low Min 200 200 200 ns tWPHWH Write Protect High to Write Enable High Min 200 200 200 ns tWHEL(2) tWHWL tWPH tWHQV tWLWH Protection Timings Parameter tVPHWH tWP tVPS Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 3. Meaningful only if L is always kept low. 46/82 K VPP WP DQ0-DQ15 E G W L A0-A21 tELEH tLHAX COMMAND tELLH tLLLH SET-UP COMMAND tDVEH tGHEL tWLEL tAVLH BANK ADDRESS tEHDX tEHEL tEHWH CMD or DATA tEHAX CONFIRM COMMAND OR DATA INPUT tVPHEH tWPHEH tAVEH VALID ADDRESS tAVAV tELKV tEHVPL tEHWPL tWHQV tWHEL tEHGL tQVVPL tQVWPL STATUS REGISTER STATUS REGISTER READ 1st POLLING tELQV VALID ADDRESS PROGRAM OR ERASE AI06975 M58WR064ET, M58WR064EB Figure 16. Write AC Waveforms, Chip Enable Controlled 47/82 M58WR064ET, M58WR064EB Table 23. Write AC Characteristics, Chip Enable Controlled M58WR064E Symbol Alt Chip Enable Controlled Timings Unit 70 80 100 tAVAV tWC Address Valid to Next Address Valid Min 70 80 100 ns tAVEH tWC Address Valid to Chip Enable High Min 45 50 50 ns Address Valid to Latch Enable High Min 9 9 10 ns tAVLH tDVEH tDS Data Valid to Write Enable High Min 45 50 50 ns tEHAX tAH Chip Enable High to Address Transition Min 0 0 0 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 0 ns tEHEL tWPH Chip Enable High to Chip Enable Low Min 25 25 25 ns Chip Enable High to Output Enable Low Min 0 0 0 ns Chip Enable High to Write Enable High Min 0 0 0 ns Chip Enable Low to Clock Valid Min 9 9 9 ns Chip Enable Low to Chip Enable High Min 45 50 50 ns tELLH Chip Enable Low to Latch Enable High Min 10 10 10 ns tELQV Chip Enable Low to Output Valid Min 70 80 100 ns tGHEL Output Enable High to Chip Enable Low Min 17 17 20 ns tLHAX Latch Enable High to Address Transition Min 9 9 10 ns tLLLH Latch Enable Pulse Width Min 9 9 10 ns Write Enable High to Chip Enable Low Min 25 25 25 ns Write Enable High to Output Valid Min 95 105 125 ns Write Enable Low to Chip Enable Low Min 0 0 0 ns tEHVPL Chip Enable High to VPP Low Min 200 200 200 ns tEHWPL Chip Enable High to Write Protect Low Min 200 200 200 ns tQVVPL Output (Status Register) Valid to VPP Low Min 0 0 0 ns tQVWPL Output (Status Register) Valid to Write Protect Low Min 0 0 0 ns VPP High to Chip Enable High Min 200 200 200 ns Write Protect High to Chip Enable High Min 200 200 200 ns tEHGL tEHWH tCH tELKV tELEH tWP tWHEL(2) tWHQV tWLEL Protection Timings Parameter tVPHEH tWPHEH tCS tVPS Note: 1. Sampled only, not 100% tested. 2. tWHEL has the values shown when reading in the targeted bank. System designers should take this into account and may insert a software No-Op instruction to delay the first read in the same bank after issuing a command. If it is a Read Array operation in a different bank tWHEL is 0ns. 48/82 M58WR064ET, M58WR064EB Figure 17. Reset and Power-up AC Waveforms tPHWL tPHEL tPHGL tPHLL W, E, G, L tPLWL tPLEL tPLGL tPLLL RP tVDHPH tPLPH VDD, VDDQ Power-Up Reset AI06976 Table 24. Reset and Power-up AC Characteristics Symbol Parameter tPLWL tPLEL tPLGL tPLLL Reset Low to Write Enable Low, Chip Enable Low, Output Enable Low, Latch Enable Low tPHWL tPHEL tPHGL tPHLL Test Condition 70 80 100 Unit During Program Min 10 10 10 µs During Erase Min 20 20 20 µs Other Conditions Min 80 80 80 ns Reset High to Write Enable Low Chip Enable Low Output Enable Low Latch Enable Low Min 30 30 30 ns tPLPH (1,2) RP Pulse Width Min 50 50 50 ns tVDHPH (3) Supply Voltages High to Reset High Min 50 50 50 µs Note: 1. The device Reset is possible but not guaranteed if tPLPH < 50ns. 2. Sampled only, not 100% tested. 3. It is important to assert RP in order to allow proper CPU initialization during Power-Up or Reset. 49/82 M58WR064ET, M58WR064EB PACKAGE MECHANICAL Figure 18. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Bottom View Package Outline D D1 FD FE E SD E1 ddd BALL "A1" e e b A A2 A1 BGA-Z38 Note: Drawing is not to scale. Table 25. VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data millimeters inches Symbol Typ Min A Max Typ Min 1.000 A1 Max 0.0394 0.200 0.0079 A2 0.660 0.0260 b 0.350 0.300 0.400 0.0138 0.0118 0.0157 D 7.700 7.600 7.800 0.3031 0.2992 0.3071 D1 5.250 – – 0.2067 – – ddd 0.080 0.0031 e 0.750 – – 0.0295 – – E 9.000 8.900 9.100 0.3543 0.3504 0.3583 E1 4.500 – – 0.1772 – – FD 1.225 – – 0.0482 – – FE 2.250 – – 0.0886 – – SD 0.375 – – 0.0148 – – 50/82 M58WR064ET, M58WR064EB Figure 19. VFBGA56 Daisy Chain - Package Connections (Top view through package) 1 2 3 4 5 6 7 8 A B C D E F G AI07731 51/82 M58WR064ET, M58WR064EB Figure 20. VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) 1 2 3 4 5 6 7 8 START POINT A B C D E F G END POINT AI07755 52/82 M58WR064ET, M58WR064EB PART NUMBERING Table 26. Ordering Information Scheme Example: M58WR064ET 70 ZB M58WR064E -ZB T 6 T Device Type M58 Architecture W = Multiple Bank, Burst Mode Operating Voltage R = VDD = 1.65V to 2.2V, VDDQ = 1.65V to 3.3V Device Function 064ET = 64 Mbit (x16), Top Boot 064EB = 64 Mbit (x16), Bottom Boot Speed 70 = 70ns 80 = 80ns 10 = 100ns Package ZB = VFBGA56: 7.7 x 9 mm, 0.75mm pitch Temperature Range 6 = –40 to 85°C Option T = Tape & Reel packing Table 27. Daisy Chain Ordering Scheme Example: Device Type M58WR064E Daisy Chain ZB = VFBGA56: 7.7x9 mm, 0.75 mm pitch Option T = Tape & Reel Packing Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc....) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 53/82 M58WR064ET, M58WR064EB APPENDIX A. BLOCK ADDRESS TABLES Table 28. Top Boot Block Addresses, M58WR064ET 4 3FF000-3FFFFF 1 4 3FE000-3FEFFF 2 4 3FD000-3FDFFF 3 4 3FC000-3FCFFF 3FA000-3FAFFF 6 4 3F9000-3F9FFF 7 4 3F8000-3F8FFF 8 32 3F0000-3F7FFF 9 32 3E8000-3EFFFF 10 32 3E0000-3E7FFF 11 32 3D8000-3DFFFF 12 32 3D0000-3D7FFF 13 32 3C8000-3CFFFF 14 32 3C0000-3C7FFF 15 32 3B8000-3BFFFF 16 32 3B0000-3B7FFF 17 32 3A8000-3AFFFF Bank 5 4 32 2F8000-2FFFFF 40 32 2F0000-2F7FFF 41 32 2E8000-2EFFFF 42 32 2E0000-2E7FFF 43 32 2D8000-2DFFFF 44 32 2D0000-2D7FFF 45 32 2C8000-2CFFFF 46 32 2C0000-2C7FFF 47 32 2B8000-2BFFFF 48 32 2B0000-2B7FFF 49 32 2A8000-2AFFFF 50 32 2A0000-2A7FFF 51 32 298000-29FFFF 52 32 290000-297FFF 53 32 288000-28FFFF 54 32 280000-287FFF 55 32 278000-27FFFF 56 32 270000-277FFF 57 32 268000-26FFFF 58 32 260000-267FFF 59 32 258000-25FFFF 32 250000-257FFF 248000-24FFFF 18 32 3A0000-3A7FFF 60 19 32 398000-39FFFF 61 32 62 32 240000-247FFF 63 32 238000-23FFFF 64 32 230000-237FFF 65 32 228000-22FFFF 66 32 220000-227FFF 67 32 218000-21FFFF 68 32 210000-217FFF 69 32 208000-20FFFF 70 32 200000-207FFF 71 32 1F8000-1FFFFF 72 32 1F0000-1F7FFF 73 32 1E8000-1EFFFF 74 32 1E0000-1E7FFF 75 32 1D8000-1DFFFF 32 1D0000-1D7FFF 32 390000-397FFF 21 32 388000-38FFFF 22 32 380000-387FFF 23 32 378000-37FFFF 24 32 370000-377FFF 25 32 368000-36FFFF 26 32 360000-367FFF 27 32 358000-35FFFF 28 32 350000-357FFF 29 32 348000-34FFFF 30 32 340000-347FFF 31 32 338000-33FFFF 32 32 330000-337FFF 33 32 328000-32FFFF Bank 7 Parameter Bank Bank 1 Bank 2 3FB000-3FBFFF 5 20 Bank 3 4 Bank 4 0 4 54/82 Address Range Bank 6 # Bank 8 Bank Size (KWord) 39 34 32 320000-327FFF 76 35 32 318000-31FFFF 77 32 1C8000-1CFFFF 78 32 1C0000-1C7FFF 36 32 310000-317FFF 37 32 308000-30FFFF 38 32 300000-307FFF Bank 12 32 1B8000-1BFFFF 111 32 80 32 1B0000-1B7FFF 112 32 0B0000-0B7FFF 81 32 1A8000-1AFFFF 113 32 0A8000-0AFFFF 82 32 1A0000-1A7FFF 114 32 0A0000-0A7FFF 83 32 198000-19FFFF 115 32 098000-09FFFF 84 32 190000-197FFF 116 32 090000-097FFF 85 32 188000-18FFFF 117 32 088000-08FFFF 86 32 180000-187FFF 118 32 080000-087FFF 87 32 178000-17FFFF 119 32 078000-07FFFF 88 32 170000-177FFF 120 32 070000-077FFF 89 32 168000-16FFFF 121 32 068000-06FFFF 90 32 160000-167FFF 122 32 060000-067FFF 91 32 158000-15FFFF 123 32 058000-05FFFF 92 32 150000-157FFF 124 32 050000-057FFF 93 32 148000-14FFFF 125 32 048000-04FFFF 94 32 140000-147FFF 126 32 040000-047FFF 95 32 138000-13FFFF 127 32 038000-03FFFF 96 32 130000-137FFF 128 32 030000-037FFF 97 32 128000-12FFFF 129 32 028000-02FFFF 98 32 120000-127FFF 130 32 020000-027FFF 99 32 118000-11FFFF 131 32 018000-01FFFF 100 32 110000-117FFF 132 32 010000-017FFF 101 32 108000-10FFFF 133 32 008000-00FFFF 102 32 100000-107FFF 134 32 000000-007FFF 103 32 0F8000-0FFFFF 104 32 0F0000-0F7FFF 105 32 0E8000-0EFFFF 106 32 0E0000-0E7FFF 107 32 0D8000-0DFFFF 108 32 0D0000-0D7FFF 109 32 0C8000-0CFFFF 110 32 0C0000-0C7FFF Bank 14 Bank 13 79 Bank 15 Bank 11 Bank 10 Bank 9 M58WR064ET, M58WR064EB 0B8000-0BFFFF Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks. 55/82 M58WR064ET, M58WR064EB # Size (KWord) Address Range 134 32 3F8000-3FFFFF 133 32 3F0000-3F7FFF 132 32 3E8000-3EFFFF 2B8000-2BFFFF 2B0000-2B7FFF 92 32 2A8000-2AFFFF 91 32 2A0000-2A7FFF 90 32 298000-29FFFF 89 32 290000-297FFF 32 288000-28FFFF 130 32 3D8000-3DFFFF 87 32 280000-287FFF 86 32 278000-27FFFF 85 32 270000-277FFF 84 32 268000-26FFFF 83 32 260000-267FFF 82 32 258000-25FFFF 32 250000-257FFF 129 32 3D0000-3D7FFF 128 32 3C8000-3CFFFF 127 32 3C0000-3C7FFF 126 32 3B8000-3BFFFF 125 32 3B0000-3B7FFF Bank 9 3E0000-3E7FFF 124 32 3A8000-3AFFFF 81 123 32 3A0000-3A7FFF 80 32 248000-24FFFF 79 32 240000-247FFF 78 32 238000-23FFFF 77 32 230000-237FFF 76 32 228000-22FFFF 75 32 220000-227FFF 74 32 218000-21FFFF 73 32 210000-217FFF 72 32 208000-20FFFF 71 32 200000-207FFF 70 32 1F8000-1FFFFF 69 32 1F0000-1F7FFF 68 32 1E8000-1EFFFF 67 32 1E0000-1E7FFF 66 32 1D8000-1DFFFF 65 32 1D0000-1D7FFF 122 32 398000-39FFFF 121 32 390000-397FFF 388000-38FFFF 119 32 380000-387FFF 118 32 378000-37FFFF 117 32 370000-377FFF 116 32 368000-36FFFF 115 32 360000-367FFF 114 32 358000-35FFFF 113 32 350000-357FFF 112 32 348000-34FFFF 111 32 340000-347FFF 110 32 338000-33FFFF 109 32 330000-337FFF Bank 8 32 Bank 7 Bank 13 Bank 12 32 32 108 32 328000-32FFFF 107 32 320000-327FFF 64 32 1C8000-1CFFFF 63 32 1C0000-1C7FFF 62 32 1B8000-1BFFFF 61 32 1B0000-1B7FFF 60 32 1A8000-1AFFFF 59 32 1A0000-1A7FFF 58 32 198000-19FFFF 106 32 318000-31FFFF 105 32 310000-317FFF 104 Bank 11 32 93 131 120 56/82 94 88 32 308000-30FFFF 103 32 300000-307FFF 102 32 2F8000-2FFFFF Bank 6 Bank 14 Bank 15 Bank Bank 10 Table 29. Bottom Boot Block Addresses, M58WR064EB 101 32 2F0000-2F7FFF 100 32 2E8000-2EFFFF 57 32 190000-197FFF 56 32 188000-18FFFF 55 32 180000-187FFF 99 32 2E0000-2E7FFF 98 32 2D8000-2DFFFF 97 32 2D0000-2D7FFF 96 32 2C8000-2CFFFF 95 32 2C0000-2C7FFF Bank 2 Bank 3 32 178000-17FFFF 22 32 53 32 170000-177FFF 21 32 070000-077FFF 52 32 168000-16FFFF 20 32 068000-06FFFF 51 32 160000-167FFF 19 32 060000-067FFF 50 32 158000-15FFFF 18 32 058000-05FFFF 49 32 150000-157FFF 17 32 050000-057FFF 48 32 148000-14FFFF 16 32 048000-04FFFF 47 32 140000-147FFF 15 32 040000-047FFF 46 32 138000-13FFFF 14 32 038000-03FFFF 45 32 130000-137FFF 13 32 030000-037FFF 44 32 128000-12FFFF 12 32 028000-02FFFF 43 32 120000-127FFF 11 32 020000-027FFF 42 32 118000-11FFFF 10 32 018000-01FFFF 41 32 110000-117FFF 9 32 010000-017FFF 40 32 108000-10FFFF 8 32 008000-00FFFF 39 32 100000-107FFF 7 4 007000-007FFF 38 32 0F8000-0FFFFF 6 4 006000-006FFF 37 32 0F0000-0F7FFF 5 4 005000-005FFF 36 32 0E8000-0EFFFF 4 4 004000-004FFF 35 32 0E0000-0E7FFF 3 4 003000-003FFF 34 32 0D8000-0DFFFF 2 4 002000-002FFF 33 32 0D0000-0D7FFF 1 4 001000-001FFF 32 32 0C8000-0CFFFF 0 4 000000-000FFF 31 32 0C0000-0C7FFF 30 32 0B8000-0BFFFF 29 32 0B0000-0B7FFF 28 32 0A8000-0AFFFF 27 32 0A0000-0A7FFF 26 32 098000-09FFFF 25 32 090000-097FFF 24 32 088000-08FFFF 23 32 080000-087FFF Bank 1 54 Parameter Bank Bank 4 Bank 5 M58WR064ET, M58WR064EB 078000-07FFFF Note: There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks. 57/82 M58WR064ET, M58WR064EB APPENDIX B. COMMON FLASH INTERFACE The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the Read CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Tables 30, 31, 32, 33, 34, 36 and 1 show the addresses used to retrieve the data. The Query data is always presented on the lowest order data outputs (DQ0DQ7), the other outputs (DQ8-DQ15) are set to 0. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 1, Security Code area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read Array command to return to Read mode. Table 30. Query Structure Overview Offset 00h Sub-section Name Description Reserved Reserved for algorithm-specific information 10h CFI Query Identification String Command set ID and algorithm data offset 1Bh System Interface Information Device timing & voltage information 27h Device Geometry Definition Flash device layout P Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) A Alternate Algorithm-specific Extended Query table Additional information specific to the Alternate Algorithm (optional) Security Code Area Lock Protection Register Unique device Number and User Programmable OTP 80h Note: The Flash memory display the CFI data structure when CFI Query command is issued. In this table are listed the main sub-sections detailed in Tables 31, 32, 33, 34, 36 and 1. Query data is always presented on the lowest order data outputs. Table 31. CFI Query Identification String Offset Sub-section Name 00h 0020h Manufacturer Code Description 01h 8810h 8811h Device Code 02h reserved ST Top Bottom Reserved 03h reserved Reserved 04h-0Fh reserved Reserved 10h 0051h 11h 0052h 12h 0059h 13h 0003h 14h 0000h 15h offset = P = 0039h 16h 0000h 17h 0000h 18h 0000h 19h value = A = 0000h 1Ah 0000h 58/82 Value "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm Address for Primary Algorithm extended Query table (see Table 33) p = 39h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA Address for Alternate Algorithm extended Query table NA M58WR064ET, M58WR064EB Table 32. CFI Query System Interface Information Offset Data Description Value 1Bh 0017h VDD Logic Supply Minimum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 1.7V 1Ch 0022h VDD Logic Supply Maximum Program/Erase or Write voltage bit 7 to 4 BCD value in volts bit 3 to 0 BCD value in 100 millivolts 2.2V 1Dh 0017h VPP [Programming] Supply Minimum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 1.7V 1Eh 00C0h VPP [Programming] Supply Maximum Program/Erase voltage bit 7 to 4 HEX value in volts bit 3 to 0 BCD value in 100 millivolts 12V 1Fh 0004h Typical time-out per single byte/word program = 2n µs 16µs 20h 0003h Typical time-out for quadruple word program = 2n µs 8µs 21h 000Ah Typical time-out per individual block erase = 2n ms 1s 22h 0000h Typical time-out for full chip erase = 2n ms NA 23h 0003h Maximum time-out for word program = 2n times typical 128µs 24h 0004h Maximum time-out for quadruple word = 2n times typical 128µs 25h 0002h Maximum time-out per individual block erase = 2n times typical 4s 26h 0000h Maximum time-out for chip erase = 2n times typical NA Table 33. Device Geometry Definition Data 27h 0017h Device Size = 2n in number of bytes 28h 29h 0001h 0000h Flash Device Interface Code description x16 Async. 2Ah 2Bh 0003h 0000h Maximum number of bytes in multi-byte program or page = 2n 8 Byte 2Ch 0002h Number of identical sized erase block regions within the device bit 7 to 0 = x = number of Erase Block Regions 2Dh 2Eh 007Eh 0000h Region 1 Information Number of identical-size erase blocks = 007Eh+1 2Fh 30h 0000h 0001h Region 1 Information Block size in Region 1 = 0100h * 256 byte 31h 32h 0007h 0000h Region 2 Information Number of identical-size erase blocks = 0007h+1 33h 34h 0020h 0000h Region 2 Information Block size in Region 2 = 0020h * 256 byte 35h 38h Reserved M58WR064ET Offset Word Mode Description Reserved for future erase block region information Value 8 MByte 2 127 64 KByte 8 8 KByte NA 59/82 M58WR064ET, M58WR064EB M58WR064EB Offset Word Mode Data Description 2Dh 2Eh 0007h 0000h Region 1 Information Number of identical-size erase block = 0007h+1 2Fh 30h 0020h 0000h Region 1 Information Block size in Region 1 = 0020h * 256 byte 31h 32h 007Eh 0000h Region 2 Information Number of identical-size erase block = 007Eh+1 33h 34h 0000h 0001h Region 2 Information Block size in Region 2 = 0100h * 256 byte 35h 38h Reserved Reserved for future erase block region information Value 8 8 KByte 127 64 KByte NA Table 34. Primary Algorithm-Specific Extended Query Table Offset Data (P)h = 39h 0050h 0052h Description Value "P" Primary Algorithm extended Query table unique ASCII string “PRI” 0049h "R" "I" (P+3)h = 3Ch 0031h Major version number, ASCII "1" (P+4)h = 3Dh 0030h Minor version number, ASCII "0" (P+5)h = 3Eh 00E6h Extended Query table contents for Primary Algorithm. Address (P+5)h contains less significant byte. 0003h (P+7)h = 40h 0000h (P+8)h = 41h 0000h (P+9)h = 42h 0001h bit bit bit bit bit bit bit bit bit bit bit 0 1 2 3 4 5 6 7 8 9 10 to 31 Chip Erase supported (1 = Yes, 0 = No) Erase Suspend supported (1 = Yes, 0 = No) Program Suspend supported (1 = Yes, 0 = No) Legacy Lock/Unlock supported (1 = Yes, 0 = No) Queued Erase supported (1 = Yes, 0 = No) Instant individual block locking supported (1 = Yes, 0 = No) Protection bits supported (1 = Yes, 0 = No) Page mode read supported (1 = Yes, 0 = No) Synchronous read supported (1 = Yes, 0 = No) Simultaneous operation supported (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’. If bit 31 is ’1’ then another 31 bit field of optional features follows at the end of the bit-30 field. No Yes Yes No No Yes Yes Yes Yes Yes Supported Functions after Suspend Read Array, Read Status Register and CFI Query Yes bit 0 bit 7 to 1 (P+A)h = 43h 0003h (P+B)h = 44h 0000h Program supported after Erase Suspend (1 = Yes, 0 = No) Reserved; undefined bits are ‘0’ Block Protect Status Defines which bits in the Block Status Register section of the Query are implemented. bit 0 Block protect Status Register Lock/Unlock bit active (1 = Yes, 0 = No) bit 1 Block Lock Status Register Lock-Down bit active (1 = Yes, 0 = No) bit 15 to 2 Reserved for future use; undefined bits are ‘0’ 60/82 Yes Yes M58WR064ET, M58WR064EB Offset Data Description Value VDD Logic Supply Optimum Program/Erase voltage (highest performance) (P+C)h = 45h 0018h 1.8V bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV VPP Supply Optimum Program/Erase voltage (P+D)h = 46h 00C0h 12V bit 7 to 4HEX value in volts bit 3 to 0BCD value in 100 mV Table 35. Protection Register Information Offset Data Description Value (P+E)h = 47h 0001h Number of protection register fields in JEDEC ID space. 0000h indicates that 256 fields are available. 1 (P+F)h = 48h 0080h (P+10)h = 49h 0000h (P+11)h = 4Ah 0003h (P+12)h= 4Bh 0004h Protection Field 1: Protection Description Bits 0-7 Lower byte of protection register address Bits 8-15 Upper byte of protection register address Bits 16-23 2n bytes in factory pre-programmed region Bits 24-31 2n bytes in user programmable region 0080h 8 Bytes 16 Bytes Table 36. Burst Read Information Offset Data Description Value (P+13)h = 4Ch 0003h Page-mode read capability bits 0-7 ’n’ such that 2n HEX value represents the number of readpage bytes. See offset 28h for device word width to determine page-mode data output width. (P+14)h = 4Dh 0003h Number of synchronous mode read configuration fields that follow. 3 (P+15)h = 4Eh 0001h Synchronous mode read capability configuration 1 bit 3-7 Reserved bit 0-2 ’n’ such that 2n+1 HEX value represents the maximum number of continuous synchronous reads when the device is configured for its maximum word width. A value of 07h indicates that the device is capable of continuous linear bursts that will output data until the internal burst counter reaches the end of the device’s burstable address space. This field’s 3-bit value can be written directly to the read configuration register bit 0-2 if the device is configured for its maximum word width. See offset 28h for word width to determine the burst data output width. 4 (P+16)h = 4Fh 0002h Synchronous mode read capability configuration 2 8 (P+17)h = 50h 0007h Synchronous mode read capability configuration 3 Cont. 8 Bytes Table 37. Bank and Erase Block Region Information M58WR064ET (top) M58WR064EB (bottom) Description Offset Data Offset Data (P+18)h =51h 02h (P+18)h =51h 02h Number of Bank Regions within the device Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. 61/82 M58WR064ET, M58WR064EB Table 38. Bank and Erase Block Region 1 Information M58WR064ET (top) M58WR064EB (bottom) Description Offset Data Offset Data (P+19)h =52h 0Fh (P+19)h =52h 01h (P+1A)h =53h 00h (P+1A)h =53h 00h (P+1B)h =54h 11h (P+1B)h =54h 11h Number of program or erase operations allowed in region 1: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+1C)h =55h 00h (P+1C)h =55h 00h Number of program or erase operations allowed in other banks while a bank in same region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 1 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) (P+1D)h =56h 00h (P+1D)h =56h (P+1E)h =57h 01h (P+1E)h =57h 02h (P+1F)h =58h 07h (P+1F)h =58h 07h (P+20)h =59h 00h (P+20)h =59h 00h (P+21)h =5Ah 00h (P+21)h =5Ah 20h (P+22)h =5Bh 01h (P+22)h =5Bh 00h (P+23)h =5Ch 64h (P+23)h =5Ch 64h (P+24)h =5Dh 00h (P+24)h =5Dh 00h (P+25)h =5Eh (P+26)h =5Fh 01h 03h Bank Region 1 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 1) Minimum block erase cycles × 1000 01h Bank Region 1 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 5Eh 01 5Eh 01 (P+26)h =5Fh 03h Bank Region 1 (Erase Block Type 1): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+27)h =60h 06h (P+28)h =61h 00h (P+29)h =62h 00h (P+2A)h =63h 01h (P+2B)h =64h 64h (P+2C)h =65h 00h (P+25)h =5Eh (P+2D)h =66h 62/82 Number of identical banks within Bank Region 1 01h Bank Region 1 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region Bank Region 1 (Erase Block Type 2) Minimum block erase cycles × 1000 Bank Regions 1 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved M58WR064ET, M58WR064EB M58WR064ET (top) M58WR064EB (bottom) Description Offset Data Offset (P+2E)h =67h Data 03h Bank Region 1 (Erase Block Type 2): Page mode and synchronous mode capabilities Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, 1 contains all the banks that are made up of main blocks only, 2 contains the banks that are made up of the parameter and main blocks. Table 39. Bank and Erase Block Region 2 Information M58WR064ET (top) M58WR064EB (bottom) Description Offset Data Offset Data (P+27)h =60h 01h (P+2F)h =68h 0Fh (P+28)h =61h 00h (P+30)h =69h 00h Number of identical banks within bank region 2 (P+29)h =62h 11h (P+31)h =6Ah 11h Number of program or erase operations allowed in bank region 2: Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations (P+2A)h =63h 00h (P+32)h =6Bh 00h Number of program or erase operations allowed in other banks while a bank in this region is programming Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations 00h Number of program or erase operations allowed in other banks while a bank in this region is erasing Bits 0-3: Number of simultaneous program operations Bits 4-7: Number of simultaneous erase operations Types of erase block regions in region 2 n = number of erase block regions with contiguous same-size erase blocks. Symmetrically blocked banks have one blocking region.(2) (P+2B)h =64h 00h (P+33)h =6Ch (P+2C)h =65h 02h (P+34)h =6Dh 01h (P+2D)h =66h 06h (P+35)h =6Eh 07h (P+2E)h =67h 00h (P+36)h =6Fh 00h (P+2F)h =68h 00h (P+37)h =70h 00h (P+30)h =69h 01h (P+38)h =71h 01h (P+31)h =6Ah 64h (P+39)h =72h 64h (P+32)h =6Bh 00h (P+3A)h =73h 00h (P+33)h =6Ch 01h (P+3B)h =74h 01h Bank Region 2 Erase Block Type 1 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 1) Minimum block erase cycles × 1000 Bank Region 2 (Erase Block Type 1): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 63/82 M58WR064ET, M58WR064EB M58WR064ET (top) M58WR064EB (bottom) Description Offset Data (P+34)h =6Dh 03h (P+35)h =6Eh 07h (P+36)h =6Fh 00h (P+37)h =70h 20h (P+38)h =71h 00h (P+39)h =72h 64h (P+3A)h =73h 00h (P+3B)h =74h (P+3C)h =75h Offset (P+3C)h =75h Data 03h Bank Region 2 (Erase Block Type 1): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved Bank Region 2 Erase Block Type 2 Information Bits 0-15: n+1 = number of identical-sized erase blocks Bits 16-31: n×256 = number of bytes in erase block region Bank Region 2 (Erase Block Type 2) Minimum block erase cycles × 1000 01h Bank Region 2 (Erase Block Type 2): BIts per cell, internal ECC Bits 0-3: bits per cell in erase region Bit 4: reserved for “internal ECC used” BIts 5-7: reserved 03h Bank Region 2 (Erase Block Type 2): Page mode and synchronous mode capabilities (defined in table 10) Bit 0: Page-mode reads permitted Bit 1: Synchronous reads permitted Bit 2: Synchronous writes permitted Bits 3-7: reserved (P+3D)h =76h (P+3D)h =76h Feature Space definitions (P+3E)h =77h (P+3E)h =77h Reserved Note: 1. The variable P is a pointer which is defined at CFI offset 15h. 2. Bank Regions. There are two Bank Regions, Region 1 contains all the banks that are made up of main blocks only, Region 2 contains the banks that are made up of the parameter and main blocks. 64/82 M58WR064ET, M58WR064EB APPENDIX C. FLOWCHARTS AND PSEUDO CODES Figure 21. Program Flowchart and Pseudo Code Start program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0x40); /*writeToFlash (addressToProgram, 0x10);*/ /*see note (3)*/ Write 40h or 10h (3) writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (addressToProgram); "see note (3)"; /* E or G must be toggled*/ Read Status Register (3) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES SR4 = 0 YES SR1 = 0 if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06170c Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 65/82 M58WR064ET, M58WR064EB Figure 22. Double Word Program Flowchart and Pseudo code Start Write 35h double_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2) { writeToFlash (addressToProgram1, 0x35); /*see note (4)*/ writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ /*Memory enters read status state after the Program command*/ Write Address 1 & Data 1 (3, 4) Write Address 2 & Data 2 (3) do { status_register=readFlash (addressToProgram) ; "see note (4)" /* E or G must be toggled*/ Read Status Register (4) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; YES SR4 = 0 YES SR1 = 0 NO Program to Protected Block Error (1, 2) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06171b Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 and Address 2 must be consecutive addresses differing only for bit A0. 4. Any address within the bank can equally be used. 66/82 M58WR064ET, M58WR064EB Figure 23. Quadruple Word Program Flowchart and Pseudo Code Start quadruple_word_program_command (addressToProgram1, dataToProgram1, addressToProgram2, dataToProgram2, addressToProgram3, dataToProgram3, addressToProgram4, dataToProgram4) { writeToFlash (addressToProgram1, 0x56); /*see note (4) */ Write 56h Write Address 1 & Data 1 (3, 4) writeToFlash (addressToProgram1, dataToProgram1) ; /*see note (3) */ Write Address 2 & Data 2 (3) writeToFlash (addressToProgram2, dataToProgram2) ; /*see note (3) */ writeToFlash (addressToProgram3, dataToProgram3) ; /*see note (3) */ Write Address 3 & Data 3 (3) writeToFlash (addressToProgram4, dataToProgram4) ; /*see note (3) */ Write Address 4 & Data 4 (3) /*Memory enters read status state after the Program command*/ do { status_register=readFlash (addressToProgram) ; /"see note (4) "/ /* E or G must be toggled*/ Read Status Register (4) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; YES SR4 = 0 YES SR1 = 0 NO Program to Protected Block Error (1, 2) if (status_register.SR==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06977b Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase operations. 3. Address 1 to Address 4 must be consecutive addresses differing only for bits A0 and A1. 4. Any address within the bank can equally be used. 67/82 M58WR064ET, M58WR064EB Figure 24. Program Suspend & Resume Flowchart and Pseudo Code Start program_suspend_command ( ) { writeToFlash (any_address, 0xB0) ; Write B0h writeToFlash (bank_address, 0x70) ; /* read status register to check if program has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Read Status Register SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR2 = 1 NO Program Complete YES Write FFh } Read data from another address Write D0h if (status_register.SR2==0) /*program completed */ { writeToFlash (bank_address, 0xFF) ; read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ else { writeToFlash (bank_address, 0xFF) ; read_data ( ); /*read data from another address*/ writeToFlash (any_address, 0xD0) ; /*write 0xD0 to resume program*/ } Write FFh } Program Continues Read Data AI06173 68/82 M58WR064ET, M58WR064EB Figure 25. Block Erase Flowchart and Pseudo Code Start erase_command ( blockToErase ) { writeToFlash (blockToErase, 0x20) ; /*see note (2) */ Write 20h (2) writeToFlash (blockToErase, 0xD0) ; /* only A12-A20 are significannt */ /* Memory enters read status state after the Erase Command */ Write Block Address & D0h do { status_register=readFlash (blockToErase) ; /* see note (2) */ /* E or G must be toggled*/ Read Status Register (2) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1) YES Command Sequence Error (1) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; YES SR4, SR5 = 1 if ( (status_register.SR4==1) && (status_register.SR5==1) ) /* command sequence error */ error_handler ( ) ; NO SR5 = 0 NO Erase Error (1) if ( (status_register.SR5==1) ) /* erase error */ error_handler ( ) ; YES SR1 = 0 NO Erase to Protected Block Error (1) if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06174b Note: 1. If an error is found, the Status Register must be cleared before further Program/Erase operations. 2. Any address within the bank can be used also. 69/82 M58WR064ET, M58WR064EB Figure 26. Erase Suspend & Resume Flowchart and Pseudo Code Start erase_suspend_command ( ) { writeToFlash (bank_address, 0xB0) ; Write B0h writeToFlash (bank_address, 0x70) ; /* read status register to check if erase has already completed */ Write 70h do { status_register=readFlash (bank_address) ; /* E or G must be toggled*/ Read Status Register SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR6 = 1 NO Erase Complete if (status_register.SR6==0) /*erase completed */ { writeToFlash (bank_address, 0xFF) ; YES read_data ( ) ; /*read data from another block*/ /*The device returns to Read Array (as if program/erase suspend was not issued).*/ Write FFh Read data from another block or Program/Protection Program or Block Protect/Unprotect/Lock } else Write D0h Write FFh Erase Continues Read Data { writeToFlash (bank_address, 0xFF) ; read_program_data ( ); /*read or program data from another address*/ writeToFlash (bank_address, 0xD0) ; /*write 0xD0 to resume erase*/ } } AI06175 70/82 M58WR064ET, M58WR064EB Figure 27. Locking Operations Flowchart and Pseudo Code Start locking_operation_command (address, lock_operation) { writeToFlash (address, 0x60) ; /*configuration setup*/ /* see note (1) */ Write 60h (1) if (lock_operation==LOCK) /*to protect the block*/ writeToFlash (address, 0x01) ; else if (lock_operation==UNLOCK) /*to unprotect the block*/ writeToFlash (address, 0xD0) ; else if (lock_operation==LOCK-DOWN) /*to lock the block*/ writeToFlash (address, 0x2F) ; Write 01h, D0h or 2Fh writeToFlash (address, 0x90) ; /*see note (1) */ Write 90h (1) Read Block Lock States Locking change confirmed? if (readFlash (address) ! = locking_state_expected) error_handler () ; /*Check the locking state (see Read Block Signature table )*/ NO YES writeToFlash (address, 0xFF) ; /*Reset to Read Array mode*/ /*see note (1) */ Write FFh (1) } End AI06176b Note: 1. Any address within the bank can equally be used. 71/82 M58WR064ET, M58WR064EB Figure 28. Protection Register Program Flowchart and Pseudo Code Start protection_register_program_command (addressToProgram, dataToProgram) {: writeToFlash (addressToProgram, 0xC0) ; /*see note (3) */ Write C0h (3) writeToFlash (addressToProgram, dataToProgram) ; /*Memory enters read status state after the Program Command*/ Write Address & Data do { status_register=readFlash (addressToProgram) ; /* see note (3) */ /* E or G must be toggled*/ Read Status Register (3) SR7 = 1 NO } while (status_register.SR7== 0) ; YES SR3 = 0 NO VPP Invalid Error (1, 2) if (status_register.SR3==1) /*VPP invalid error */ error_handler ( ) ; NO Program Error (1, 2) if (status_register.SR4==1) /*program error */ error_handler ( ) ; NO Program to Protected Block Error (1, 2) YES SR4 = 0 YES SR1 = 0 if (status_register.SR1==1) /*program to protect block error */ error_handler ( ) ; YES End } AI06177b Note: 1. Status check of SR1 (Protected Block), SR3 (VPP Invalid) and SR4 (Program Error) can be made after each program operation or after a sequence. 2. If an error is found, the Status Register must be cleared before further Program/Erase Controller operations. 3. Any address within the bank can equally be used. 72/82 M58WR064ET, M58WR064EB Figure 29. Enhanced Factory Program Flowchart SETUP PHASE VERIFY PHASE Start Write PD1 Address WA1(1) Write 30h Address WA1 Write D0h Address WA1 Read Status Register Read Status Register SR0 = 0? NO Check SR4, SR3 and SR1 for program, VPP and Lock Errors SR7 = 0? Exit PROGRAM PHASE YES Write PD2 Address WA2(1) YES SR0 = 0? NO NO YES Read Status Register Write PD1 Address WA1 SR0 = 0? Read Status Register NO YES NO SR0 = 0? Write PDn Address WAn(1) YES Write PD2 Address WA2(1) Read Status Register Read Status Register SR0 = 0? NO YES SR0 = 0? NO Write FFFFh Address =/ Block WA1 YES EXIT PHASE Write PDn Address WAn(1) Read Status Register Read Status Register SR7 = 1? NO YES SR0 = 0? NO Check Status Register for Errors YES Write FFFFh Address =/ Block WA1 End AI06160 Note: 1. Address can remain Starting Address WA1 or be incremented. 73/82 M58WR064ET, M58WR064EB Enhanced Factory Program Pseudo Code efp_command(addressFlow,dataFlow,n) /* n is the number of data to be programmed */ { /* setup phase */ writeToFlash(addressFlow[0],0x30); writeToFlash(addressFlow[0],0xD0); status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } else{ /*Program Phase*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1) /*Ready for first data*/ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* Verify Phase */ for (i=0; i++; i< n){ writeToFlash(addressFlow[i],dataFlow[i]); /* status register polling*/ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ } while (status_register.SR0==1); /* Ready for a new data */ } writeToFlash(another_block_address,FFFFh); /* exit program phase */ /* Exit Phase */ /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR4==1) /*program failure error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } 74/82 M58WR064ET, M58WR064EB Figure 30. Quadruple Enhanced Factory Program Flowchart SETUP PHASE LOAD PHASE Start Write 75h Address WA1 FIRST LOAD PHASE Write PD1 Address WA1 Read Status Register Write PD1 Address WA1(1) Write PD2 Address WA2(2) Write PD3 Address WA3(2) NO SR7 = 0? YES Write PD4 Address WA4(2) EXIT PHASE Check SR4, SR3 and SR1 for program, VPP and Lock Errors PROGRAM AND VERIFY PHASE Read Status Register Write FFFFh Address = / Block WA1 Exit NO SR0 = 0? YES Check SR4 for Programming Errors End Last Page? NO YES Note 1. Address can remain Starting Address WA1 (in which case the next Page is programmed) or can be any address in the same block. 2.The address is only checked for the first Word of each Page as the order to program the Words is fixed so subsequent Words in each Page can be written to any address. AI06178b 75/82 M58WR064ET, M58WR064EB Quadruple Enhanced Factory Program Pseudo Code quad_efp_command(addressFlow,dataFlow,n) /* n is the number of pages to be programmed.*/ { /* Setup phase */ writeToFlash(addressFlow[0],0x75); for (i=0; i++; i< n){ /*Data Load Phase*/ /*First Data*/ writeToFlash(addressFlow[i],dataFlow[i,0]); /*at the first data of the first page, Quad-EFP may be aborted*/ if (First_Page) { status_register=readFlash(any_address); if (status_register.SR7==1){ /*EFP aborted for an error*/ if (status_register.SR4==1) /*program error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR1==1) /*program to protect block error*/ error_handler(); } } /*2nd data*/ writeToFlash(addressFlow[i],dataFlow[i,1]); /*3rd data*/ writeToFlash(addressFlow[i],dataFlow[i,2]); /*4th data*/ writeToFlash(addressFlow[i],dataFlow[i,3]); /* Program&Verify Phase */ do{ status_register=readFlash(any_address); /* E or G must be toggled*/ }while (status_register.SR0==1) } /* Exit Phase */ writeToFlash(another_block_address,FFFFh); /* status register polling */ do{ status_register=readFlash(any_address); /* E or G must be toggled */ } while (status_register.SR7==0); if (status_register.SR1==1) /*program to protected block error*/ error_handler(); if (status_register.SR3==1) /*VPP invalid error*/ error_handler(); if (status_register.SR4==1) /*program failure error*/ error_handler(); } } 76/82 M58WR064ET, M58WR064EB APPENDIX D. COMMAND INTERFACE STATE TABLES Table 40. Command Interface States - Modify Table, Next State Current CI State Ready Lock/CR Setup Setup OTP Busy Setup Program Next CI State After Command Input Erase Confirm Block P/E Read Program Program Clear Electronic Erase, Quad- Resume, Program/ Read WP DWP, Read EFP status signature, Bank Block Erase Status EFP setup QWP Setup Erase Array(2) (3,4) Unlock Suspend Register Register Read CFI Setup Setup (5) Setup (3,4) confirm, Query (3,4) EFP Confirm Program Program Quad-EFP Ready Erase Setup EFP Setup Ready Setup Setup Setup Ready (Lock Error) Ready Ready (Lock Error) OTP Busy Program Busy Busy Suspend Program Suspended Setup Ready (error) Busy Erase Suspended Program in Erase Suspend Busy Suspend Lock/CR Setup in Erase Suspend Setup EFP Quad EFP Program Busy Program Suspended Ready (error) Erase Suspended Erase Suspended Setup Program in Erase Suspend Program Busy Erase Busy Erase Busy Erase Suspend Program Suspended Program Busy Erase Busy Erase Busy Erase Suspended Program in Erase Suspend Busy Program in Erase Suspend Suspended Program in Erase Suspend Busy Program in Erase Suspend Suspended Erase Suspend (Lock Error) Ready (error) Program in Erase Suspend Busy Erase Suspend EFP Busy Busy EFP Busy (6) Verify EFP Verify (6) Setup Quad EFP Busy (6) Busy Quad EFP Busy(6) Program in Erase Suspend Busy Program in Erase Suspend Suspended Erase Suspend (Lock Error) Ready (error) Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’.EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 77/82 M58WR064ET, M58WR064EB Table 41. Command Interface States - Modify Table, Next Output Current CI State Read Array(2) Program DWP, QWP Setup (3,4) Block Erase, Bank Erase Setup (3,4) Next Output State After Command Input (6) Erase Confirm P/E Resume, Program/ QuadRead EFP Block EFP Erase Status Setup Unlock Setup Suspend Register confirm, EFP Confirm Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend Clear status Register (5) Read Electronic signature, Read CFI Query Status Register Status Register OTP Busy Array Status Register Output Unchanged Status Register Output Unchanged Status Register Ready Program Busy Erase Busy Program/Erase Program in Erase Suspend Busy Program in Erase Suspend Suspended Array Status Register Output Unchanged Status Register Output Unchanged Electronic Signature/ CFI Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, DWP = Double Word Program, QWP = Quadruple Word Program, P/E. C. = Program/Erase Controller. 2. At Power-Up, all banks are in Read Array mode. A Read Array command issued to a busy bank, results in undetermined data output. 3. The two cycle command should be issued to the same bank address. 4. If the P/E.C. is active, both cycles are ignored. 5. The Clear Status Register command clears the Status Register error bits except when the P/E.C. is busy or suspended. 6. The output state shows the type of data that appears at the outputs if the bank address is the same as the command address. A bank can be placed in Read Array, Read Status Register, Read Electronic Signature or Read CFI Query mode, depending on the command issued. Each bank remains in its last output state until a new command is issued. The next state does not depend on the bank’s output state. 78/82 M58WR064ET, M58WR064EB Table 42. Command Interface States - Lock Table, Next State Next CI State After Command Input Current CI State Ready Lock/CR Setup OTP Program Lock/CR Setup(4) OTP Setup Lock/CR Setup OTP Setup (4) Ready (Lock error) Ready EFP Exit, Quad EFP Exit (3) Illegal Command (5) P/E. C. Operation Completed N/A Ready (Lock error) N/A N/A OTP Busy Busy Ready Setup Program Busy N/A Busy Program Busy Ready Suspend Program Suspended N/A Setup Ready (error) N/A Busy Erase Busy Ready Suspend Lock/CR Setup in Erase Suspend Erase Suspended Setup N/A Program in Erase Suspend Busy N/A Busy Program in Erase Suspend Busy Erase Suspended Suspend Program in Erase Suspend Suspended N/A Lock/CR Setup in Erase Suspend Erase Suspend (Lock error) Erase Suspend Setup EFP Set CR Confirm Ready Setup Erase Program in Erase Suspend Block Lock-Down Confirm Block Lock Confirm Erase Suspend (Lock error) Ready (error) N/A N/A Busy EFP Busy (2) EFP Verify EFP Busy(2) N/A Verify EFP Verify (2) Ready EFP Verify(2) Ready Setup QuadEFP Busy Quad EFP Busy Quad EFP Busy (2) (2) N/A Ready Quad EFP Busy(2) Ready Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP are allowed only when Status Register bit SR0 is set to ‘0’. EFP and Quad EFP are busy if Block Address is first EFP Address. Any other commands are treated as data. 3. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 4. If the P/E.C. is active, both cycles are ignored. 5. Illegal commands are those not defined in the command set. 79/82 M58WR064ET, M58WR064EB Table 43. Command Interface States - Lock Table, Next Output Current CI State Program Setup Erase Setup OTP Setup Program in Erase Suspend EFP Setup EFP Busy EFP Verify Quad EFP Setup Quad EFP Busy Lock/CR Setup Lock/CR Setup in Erase Suspend Lock/CR Setup(3) OTP Setup (3) Next Output State After Command Input Block EFP Exit, Block Lock Set CR Lock-Down Quad EFP Confirm Confirm Confirm Exit (2) Illegal Command (4) Output Unchanged Status Register Status Register P/E. C. Operation Completed Array Status Register Output Unchanged OTP Busy Status Register Output Unchanged Array Output Unchanged Output Unchanged Ready Program Busy EraseBusy Program/Erase Program in Erase Suspend Busy Program in Erase Suspend Suspended Status Register Output Unchanged Array Output Unchanged Output Unchanged Note: 1. CI = Command Interface, CR = Configuration Register, EFP = Enhanced Factory Program, Quad EFP = Quadruple Enhanced Factory Program, P/E. C. = Program/Erase Controller. 2. EFP and Quad EFP exit when Block Address is different from first Block Address and data is FFFFh. 3. If the P/E.C. is active, both cycles are ignored. 4. Illegal commands are those not defined in the command set. 80/82 M58WR064ET, M58WR064EB REVISION HISTORY Table 44. Document Revision History Date Version 08-Apr-2002 -01 First Issue -02 Part number modified, Synchronous Burst Frequency modified, description of the Automatic Standby mode added. Hexadecimal Code for Quadruple Word Program Setup modified. Double/Quadruple Word Program command descriptions modified. Description of the Verify Phase in the Enhanced Factory Program command and the Exit Phase in the Quadruple Enhanced Factory Program command modified. Parameters in Tables 6, 7, 8, 18, 20, 21, 22, 23, 24, 33, 39, 40, 41 and 43 modified and/or specified. Figures 4, 7, 12, 13, 15, 16, 17 and 23 modified. Figure 14 added. 2.1 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 02 equals 2.0). Revision history moved to end of document. Bank numbering modified; Figures 21, 22, 23, 24, 27, 28 and 29 modified. 1st Cycle Addresses modified in Table 5 and note to Figure 13, modified. “Read Status Register Command”, “Program/Erase Suspend Command”, “Set Configuration Register Command”, “Double Word Program Command”, “Quadruple Word Program Command”, “Enhanced Factory Program Command”, “Quadruple Enhanced Factory Program Command”, “Erase Status Bit (SR5)”, “Wait Configuration Bit (CR8)”, “Asynchronous Read Mode”, “Synchronous Burst Read Mode” and “Single Synchronous Read Mode” paragraphs clarified. Default values added to Table 9; Figure 19, VFBGA56 Daisy Chain - Package Connections (Top view through package), Figure 20, VFBGA56 Daisy Chain - PCB Connection Proposal (Top view through package) and Table 27, Daisy Chain Ordering Scheme added. Notes added to Figures 12, 21, 22, 23, 24, 27, and 28 and Table 14. 85ns Speed Class removed, 80ns Speed Class added. 70ns Speed Class characterized (certain timings modified). 3.0 Document promoted from Product Preview to full Datasheet status. Automatic Standby mode explained under Asynchronous Read Mode. Minor text changes in Clear Status Register Command, Quadruple Enhanced Factory Program Command and Synchronous Burst Read Mode. Bank Erase Command moved from the Standard to the Factory Program Commands. Number of Bank Erase cycles limited to 100. Erase replaced by Block Erase in Tables 11 and 12, Dual Operations Allowed in Other Banks and the Same Bank, respectively. Overbar removed from WAIT signal in all AC Waveform Figures. Latch Enable waveform modified in Figure 11, Asynchronous Page Read AC Waveforms. VDDQ range split into two in Tables 20 and 21, Asynchronous and Synchronous Read AC Characteristics: for VDDQ = 1.65V to 2.2V, tAVKH and tELKH in Table 20, and tLLKH in Table 21, were changed; for VDDQ = 2.2V to 3.3V, tAVQV1, tELTV, tEHTZ, tEHQZ, tGLQV, tAVLH, tLLH in Table 20 and all the timings in Table 21 were modified. Values corrected in Table 25, VFBGA56 - 7.7x9mm, 8x7 ball array, 0.75mm pitch, Package Mechanical Data. Data reserved at addresses 35h and 38h in Table 33, Device Geometry Definition. Data corrected at address offset (P+37)h = 70h in Table 39, Bank and Erase Block Region 2 Information. Quotes removed from Figure 21, Program Flowchart and Pseudo Code. 20-Jun-2002 21-Oct-2002 19-Feb-2003 Revision Details 81/82 M58WR064ET, M58WR064EB Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. 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