MT16LSDT3264AG-133G3

128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM SYNCHRONOUS DRAM MODULE MT8LSDT1664A – 128MB MT16LSDT3264A – 256MB For the latest data sheet, please refer to the Micron® Web site: www.micron.com/products/modules Features Figure 1: 168-Pin DIMM (MO-161) • 168-pin, dual in-line memory module (DIMM) • PC100- and PC133-compliant • Utilizes 125 MHz and 133 MHz SDRAM components • Unbuffered • 128MB (16 Meg x 64) and 256MB (32 Meg x 64) • Single +3.3V power supply • Fully synchronous; all signals registered on positive edge of system clock • Internal pipelined operation; column address can be changed every clock cycle • Internal SDRAM banks for hiding row access/ precharge • Programmable burst lengths: 1, 2, 4, 8, or full page • Auto Precharge, includes CONCURRENT AUTO PRECHARGE and Auto Refresh Modes • Self Refresh Mode: 64ms, 4,096-cycle refresh (15.625µs refresh interval) • LVTTL-compatible inputs and outputs • Serial Presence-Detect (SPD) • Gold edge contacts Table 1: Standard 1.375in. (34.93mm) Low Profile 1.125in. (28.58mm) Y1 • Frequency/CAS Latency 133 MHz/CL = 2 133 MHz/CL = 3 100 MHz/CL = 2 • PCB Standard 1.375in. (34.93mm) Low-Profile 1.125in. (28.58mm)1 Timing Parameters CL = CAS (READ) latency ACCESS TIME MODULE CLOCK MARKING FREQUENCY CL = 2 CL = 3 -13E -133 -10E Table 2: 133 MHz 133 MHz 100 MHz 5.4ns – 9ns – 5.4ns 7.5ns SETUP TIME HOLD TIME 1.5 1.5 2ns 0.8 0.8 1ns Marking Options NOTE: -13E -133 -10E 1. Contact Micron for product availability. Address Table Refresh Count Device Banks Device Configuration Row Addressing Column Addressing Module Ranks PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 128MB 256MB 4K 4 (BA0, BA1) 128Mb (16 Meg x 8) 4K (A0–A11) 1K (A0–A9) 1 (S0#, S2#) 4K 4 (BA0, BA1) 128Mb (16 Meg x 8) 4K (A0–A11) 1K (A0–A9) 2 (S0#, S2#; S1#, S3#) 1 ©2003, 2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. Table 3: Part Numbers PART NUMBER MT8LSDT1664AG-13E_ MT8LSDT1664AY-13E_ MT8LSDT1664AG-133_ MT8LSDT1664AY-133_ MT8LSDT1664AG-10E_ MT8LSDT1664AY-10E_ MT16LSDT3264AG-13E_ MT16LSDT3264AY-13E_ MT16LSDT3264AG-133_ MT16LSDT3264AY-133_ MT16LSDT3264AG-10E_ MT16LSDT3264AY-10E_ MODULE DENSITY CONFIGURATION SYSTEM BUS SPEED 128MB 128MB 128MB 128MB 128MB 128MB 256MB 256MB 256MB 256MB 256MB 256MB 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 16 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 32 Meg x 64 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz 133 MHz 133 MHz 133 MHz 133 MHz 100 MHz 100 MHz NOTE: The designators for component and PCB revision are the last two characters of each part number Consult factory for current revision codes. Example: MT16LSDT3264AG-133B1. SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 4: Pin Assignment (168-Pin DIMM Front) Table 5: PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 NC 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 NC VSS NC NC VDD WE# DQMB0 DQMB1 S0# NC VSS A0 A2 A4 A6 A8 A10 BA1 VDD VDD CKO 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 VSS NC S2# DQMB2 DQMB3 NC VDD NC NC NC NC VSS DQ16 DQ17 DQ18 DQ19 VDD DQ20 NC NC CKE1 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Pin Assignment (168-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS CK2 NC WP SDA SCL VDD Figure 2: 168-Pin DIMM Pin Locations Front View U10 U2 U1 U3 U4 U6 U7 U8 PIN 41 PIN 1 U9 PIN 84 Back View (Populated only for 256MB module) U11 U12 U13 U14 U16 PIN 125 PIN 168 Indicates a VDD pin U17 U18 U19 PIN 85 Indicates a VSS pin 3 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Functional Block Diagram – 128MB S0# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ DQ U1 DQ DQ DQ DQ DQ DQ DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ U2 DQ DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB5 DQM CS# DQ U3 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ U4 DQ DQ DQ DQ DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ U7 DQ DQ DQ DQ DQ DQ DQ DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQM CS# DQ U9 DQ DQ DQ DQ DQ DQ DQ RAS# RAS#: SDRAMs CAS# CAS#: SDRAMs CKE0 CKE0: SDRAMs WE# A0-A11 U1 U2 U3 U4 CK0 A0-A11: SDRAMs BA0: SDRAMs BA1 BA1: SDRAMs SCL WP DQM CS# DQ U8 DQ DQ DQ DQ DQ DQ DQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 WE#: SDRAMs BA0 DQM CS# DQ U6 DQ DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 CK2 3.3pF SPD U10 A0 A1 U6 U7 U8 U9 A2 SDA CK1, CK3 10pF VDD SDRAMs VSS SDRAMs SA0 SA1 SA2 NOTE: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide. 4 Standard modules use the following SDRAM devices: MT48LC16M8A2TG Lead-free modules use the following SDRAM devices: MT48LC16M8A2P ©2003, 2004 Micron Technology, Inc. All rights reserved. S0# S1# DQMB0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQMB4 DQM CS# DQ U1 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U19 DQ DQ DQ DQ DQ DQ DQM CS# DQ U3 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U17 DQ DQ DQ DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQMB1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM CS# DQ U2 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U18 DQ DQ DQ DQ DQ DQ DQM CS# DQ U4 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U16 DQ DQ DQ DQ DQ DQ DQM CS# DQ U6 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U14 DQ DQ DQ DQ DQ DQ DQM CS# DQ U8 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U12 DQ DQ DQ DQ DQ DQ DQMB5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 S2# S3# DQMB2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQMB6 DQM CS# DQ U7 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U13 DQ DQ DQ DQ DQ DQ DQM CS# DQ U9 DQ DQ DQ DQ DQ DQ DQ DQM CS# DQ DQ U11 DQ DQ DQ DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQMB3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DQMB7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VDD 10K CKE1 CKE0 CKE: SDRAMs U1-U4; U6-U9 CAS# CAS#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 RAS# RAS#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 WE# WE#: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 A0-A11 CK0 U1 U2 U3 U4 CK1 U16 U17 U18 U19 CK2 U6 U7 U8 U9 CK3 U11 U12 U13 U14 CKE: SDRAMs U11-U14; U16-U19 A0-A11: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 BA0 BA0: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 BA1 BA1: SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 VDD SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 VSS SDRAMs U1-U4; U6-U9; U11-U14; U16-U19 3.3pF SCL WP 3.3pF SPD U10 A0 A1 A2 SDA SA0 SA1 SA2 NOTE: 1. All resistor values are 10Ω unless otherwise specified. 2. Per industry standard, Micron modules utilize various component speed grades, as referenced in the module part numbering guide at www.micron.com/numberguide. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 5 Standard modules use the following SDRAM devices: MT48LC16M8A2TG Lead-free modules use the following SDRAM devices: MT48LC16M8A2P Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information 27, 115, 111 RAS#, CAS#, WE# CK0–CK3 Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input 63, 128 CKE0, CKE1 Input 30, 45, 114, 129 S0#–S3# Input 28–29, 46–47, 112– DQMB0– 113, 130–131 DQMB7 Input Clock: CK is driven by the system clock. All SDRAM input signals are sampled on the positive edge of CK. CK also increments the internal burst counter and controls the output registers. Clock Enable: CKE0 activate (HIGH) and deactivate (LOW) the CK signal. Deactivating the clock provides PRECHARGE POWER-DOWN and SELF REFRESH operation (all device banks idle), ACTIVE POWER-DOWN (row ACTIVE in any device bank) or CLOCK SUSPEND operation (burst access in progress). CKE is synchronous except after the device enters power-down and self refresh modes, where CKE becomes asynchronous until after exiting the same mode. The input buffers, including CK, are disabled during power-down and self refresh modes, providing low standby power. Chip Select: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input/Output Mask: DQMB is an input mask signal for write accesses and an output enable signal for read accesses. Input data is masked when DQMB is sampled HIGH during a WRITE cycle. The output buffers are placed in a High-Z state (two-clock latency) when DQMB is sampled HIGH during a READ cycle. Bank Address: BA0 and BA1 define to which device bank the ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to once device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Presence-Detect Address Inputs: These pins are used to configure the presencedetect device. Data I/O: Data bus. 42, 79, 125, 163 39, 122 BA0, BA1 Input 33, 34, 35, 36, 37, 38, 117, 118, 119, 120, 121, 123 A0–A11 Input 83 SCL Input 165–167 SA0–SA2 Input 2–5, 7–11, 13–17, 19–20, 55–58, 60, 65–67, 69–72, 74– 77, 86–89, 91–95, 97–101, 103–104, 139–142, 144, 149–151, 153–156, 158–161 82 DQ0– DQ63 Input/ Output SDA Input/ Output 6, 18, 26, 40, 41, 49, 59, 73, 84, 90, 102, 110, 124, 133, 143, 157, 168 VDD Supply PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN Serial Presence-Detect Data: SDA is a bidirectional pin used to transfer addresses and data into and data out of the presence-detect portion of the module. Power Supply: +3.3V ±0.3V. 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Pin numbers may not correlate with symbols; refer to Pin Assignment tables on page 3 for more information 1, 12, 23, 32, 43, 54, 64, 68, 78, 85, 96, 107, 116, 127, 138, 148, 152, 162 21, 22, 24, 25, 31, 44, 48, 50–53, 61, 62, 80, 81, 105, 106, 108, 109, 126, 132, 134–137, 145–147, 164 VSS Supply NC – PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN Ground. Not Connected: These pins are not connected on this module. 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. General Description Serial Presence-Detect Operation SDRAM modules incorporate serial presence-detect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. signals CK). Read and write accesses to the SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select the device bank, A0–A11 select the device row). The address bits registered coincident with the READ or WRITE command are used to select the starting column location for the burst access. The modules provide for programmable READ or WRITE burst lengths of 1, 2, 4, or 8 locations, or the full page, with a burst terminate option. An AUTO PRECHARGE function may be enabled to provide a selftimed row precharge that is initiated at the end of the burst sequence. SDRAM modules use an internal pipelined architecture to achieve high-speed operation. This architecture is compatible with the 2n rule of prefetch architectures, but it also allows the column address to be changed on every clock cycle to achieve a highspeed, fully random access. Precharging one device bank while accessing one of the other three device banks will hide the precharge cycles and provide seamless, high-speed, random-access operation. SDRAM modules are designed to operate in 3.3V, low-power memory systems. An auto refresh mode is provided, along with a power-saving, power-down mode. All inputs and outputs are LVTTL-compatible. SDRAM modules offer substantial advances in DRAM operating performance, including the ability to synchronously burst data at a high data rate with automatic column-address generation, the ability to interleave between internal banks in order to hide precharge time and the capability to randomly change column addresses on each clock cycle during a burst access. For more information regarding SDRAM operation, refer to the 128Mb SDRAM component data sheets. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN Initialization DD and VDDQ (simultaneously) and the clock is stable (stable clock is defined as a signal cycling within timing constraints specified for the clock pin), the SDRAM requires a 100µs delay prior to issuing any command other than a COMMAND INHIBIT or NOP. Starting at some point during this 100µs period and continuing at least through the end of this period, Command Inhibit or NOP commands should be applied. Once the 100µs delay has been satisfied with at least one Command Inhibit or NOP command having been applied, a PRECHARGE command should be applied. All device banks must then be precharged, thereby placing the device in the all banks idle state. Once in the idle state, two AUTO refresh cycles must be performed. After the AUTO refresh cycles are complete, the SDRAM is ready for mode register programming. Because the mode register will power up in an unknown state, it should be loaded prior to applying any operational command. Mode Register Definition 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM A11 A10 11 10 A9 9 Reserved* WB A8 8 A6 A7 6 7 Op Mode A5 5 A4 A3 4 CAS Latency 3 1 2 BT A1 A2 Address Bus A0 0 Mode Register (Mx) Burst Length Burst Length *Should program M11, M10 = “0, 0” to ensure compatibility with future devices. Burst Length M2 M1 M0 in conjunction with the BURST TERMINATE command to generate arbitrary burst lengths. Reserved states should not be used, as unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached, as shown in the Burst Definition Table. The block is uniquely selected by A1– A9 when the burst length is set to two; by A2–A9 when the burst length is set to four; and by A3–A9 when the burst length is set to eight. The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. Full-page bursts wrap within the page if the boundary is reached, as shown in the Table 7. 0 0 1 1 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Full Page Reserved Burst Type 0 Sequential 1 Interleaved M6 M5 M4 9 M3 = 1 0 M3 Burst Type M3 = 0 CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 3 1 0 0 Reserved 1 0 1 Reserved 1 1 0 Reserved 1 1 1 Reserved M8 M7 M6-M0 Operating Mode 0 0 Defined Standard Operation - - - M9 Write Burst Mode 0 Programmed Burst Length 1 Single Location Access All other states reserved ©2003, 2004 Micron Technology, Inc. All rights reserved. Table 7: Burst Definition CAS Latency Diagram ORDER OF ACCESSES WITHIN A BURST ADDRESS BURST LENGTH STARTING COLUMN TYPE = SEQUENTIAL T0 T1 T2 T3 READ NOP NOP CLK TYPE = INTERLEAVED COMMAND tLZ A0 tOH DOUT DQ tAC CAS Latency = 2 A1 A0 T0 T1 T2 T3 T4 READ NOP NOP NOP CLK COMMAND A2 A1 A0 tLZ tOH DOUT DQ tAC CAS Latency = 3 DON’T CARE UNDEFINED Not Supported CAS Latency …Cn - 1, Cn… NOTE: 1. For full-page accesses: y = 1,024. 2. For a burst length of two, A1–A9 select the block-oftwo burst; A0 selects the starting column within the block. 3. For a burst length of four,A2–A9 select the block-offour burst; A0–A1 select the starting column within the block. 4. For a burst length of eight, A3–A9 select the block-ofeight burst; A0–A2 select the starting column within the block. 5. For a full-page burst, the full row is selected and A0–A9 select the starting column. 6. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 7. For a burst length of one, A0–A9 select the unique column to be accessed, and mode register bit M3 is ignored. Operating Mode 10 ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM CLOCK FREQUENCY (MHZ) Write Burst Mode CAS LATENCY = 2 ≤ ≤ ≤ PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 11 CAS LATENCY = 3 ≤ ≤ ≤ Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Table 9: SDRAM Commands and DQMB Operation Truth Table NAME (FUNCTION) CS# NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO refresh or Self Refresh (Enter self refresh mode) LOAD MODE REGISTER Write Enable/Output Enable L L L L L L L L – RAS# CAS# WE# DQMB X H L H H H L L L – X H H L L H H L L – X H H H L L L H L – X X X L/H8 L/H8 X X X X L ADDR DQ X X X X Bank/Row X Bank/Col X Bank/Col Valid X Active Code X X X Op-code X – Active NOTES 1 2 2 3 4, 5 6 7 NOTE: 1. A0–A11provide device row address, and BA0, BA1 determine which device bank is made active. 2. A0–A9 provide device column address; A10 HIGH enables the auto precharge feature (nonpersistent), while A10 LOW disables the auto precharge feature; BA0, BA1 determine which device bank is being read from or written to. 3. A10 LOW: BA0, BA1 determine which device bank is being precharged. A10 HIGH: all device banks are precharged and BA0, BA1 are “Don’t Care.” 4. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 5. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 6. A0–A11 define the op-code written to the mode register. 7. Activates or deactivates the DQs during WRITEs (zero-clock delay) and READs (two-clock delay). PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Absolute Maximum Ratings Operating Temperature TOPR (Commercial - ambient) . . . . . .0°C to +65°C Storage Temperature (plastic) . . . . . . . . -55°C to +150°C SS . . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Voltage on Inputs, NC or I/O Pins Relative to VSS . . . . . . . . . . . . . . . . . . . . . . . . -1V to +4.6V Table 10: DC Electrical Characteristics and Operating Conditions – 128MB PARAMETER/CONDITION SYMBOL MIN MAX UNITS NOTES 2 -0.3 VDD + 0.3 0.8 V V 22 22 40 20 5 5 µA µA µA µA 33 IOZ -40 -20 -5 -5 VOH VOL 2.4 – – 0.4 V V VDD, VDDQ VIH VIL 3 2 -0.3 -80 3.6 VDD + 0.3 0.8 80 V V V µA IOZ -20 -10 -10 20 10 10 µA µA µA VOH VOL 2.4 – – 0.4 V V IH INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) VIL Command and Address Inputs, CKE CK, S# DQMB DQ II 33 Notes: 1, 5, 6; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs INPUT LEAKAGE CURRENT: Any input 0V ≤ VIN ≤ VDD (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT: DQ pins are disabled; 0V ≤ VOUT ≤ VDDQ OUTPUT LEVELS: Output High Voltage (IOUT = -4mA) Output Low Voltage (IOUT = 4mA) PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN Command and Address Inputs, CKE CK, S# DQMB DQ 13 II 22 22 33 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. DD Specifications and Conditions – 128MB MAX PARAMETER/CONDITION = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) AUTO REFRESH CURRENT tRFC = 15.625µs CKE = HIGH; CS# = HIGH SELF REFRESH CURRENT: CKE £ 0.2V SYMBOL -13E -133 -10E UNITS NOTES IDD1 1,280 1,200 1,120 mA IDD2 16 16 16 mA 3, 18, 19, 30 30 IDD3 400 400 320 mA 3, 12, 19, 30 IDD4 1,320 1,280 1,200 mA IDD5 IDD6 IDD7 2,640 24 16 2,480 24 16 2,160 24 16 mA mA mA 3, 18, 19, 30 3, 12, 18, 19, 30, 31 tRC 4 Notes: 1, 5, 6, 11, 13; notes appear on page 18; VDD, VDDQ = +3.3V ±0.3V; SDRAM components only OPERATING CURRENT: Active Mode; Burst = 2; READ or WRITE; tRC = tRC (MIN) STANDBY CURRENT: Power-Down Mode; All device banks idle; CKE = LOW STANDBY CURRENT: Active Mode; CKE = HIGH; CS# = HIGH; All device banks active after tRCD met; No accesses in progress OPERATING CURRENT: Burst Mode; Continuous burst; READ or WRITE; All device banks active tRFC = tRFC (MIN) AUTO REFRESH CURRENT tRFC = 15.625µs CS# = HIGH; CKE = HIGH SELF REFRESH CURRENT: CKE ≤ 0.2V IDD1a 1,296 1,216 1,136 mA IDD2b 32 32 32 mA IDD3a 416 416 336 mA 3, 12, 19, 30 IDD4a 1,336 1,216 1,136 mA IDD5b IDD6b IDD7b 5,280 48 32 4,960 48 32 4,320 48 32 mA mA mA 3, 18, 19, 30 3, 12, 18, 19, 30, 31 3, 18, 19, 30 30 4 a - Value calculated as one module rank in this operating condition, and all otherranks in Power-Down Mode. b - Value calculated reflects all module ranks in this operating condition. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Input Capacitance: Command and Address Input Capacitance: CK Input Capacitance: S# Input Capacitance: CKE Input Capacitance: DQMB Input/Output Capacitance: DQ CI1 CI2 CI3 CI4 CI5 CIO 20 13.3 10 20 2.5 4 30.4 17.3 15.2 30.4 3.8 6 pF pF pF pF pF pF Input Capacitance: Command and Address Input Capacitance: CK Input Capacitance: S# Input Capacitance: CKE Input Capacitance: DQMB Input/Output Capacitance: DQ CI1 CI2 CI3 CI4 CI5 CIO 40 13.3 10 20 5 8 60.8 17.3 15.2 30.4 7.6 12 pF pF pF pF pF pF PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Notes: 5–9, 11, 32; notes appear on page 18; module AC timing parameters comply with PC100 and PC133 design specs, based on component parameters Access time from CLK (pos. edge) Address hold time Address setup time CLK high-level width CLK low-level width Clock cycle time CL = 3 CL = 2 CL = 3 CL = 2 CKE hold time CKE setup time CS#, RAS#, CAS#, WE#, DQM hold time CS#, RAS#, CAS#, WE#, DQM setup time Data-in hold time Data-in setup time Data-out high-impedance time CL = 3 CL = 2 Data-out low-impedance time Data-out hold time (load) Data-out hold time (no load) ACTIVE to PRECHARGE command ACTIVE to ACTIVE command period ACTIVE to READ or WRITE delay Refresh period (8,192 rows) AUTO REFRESH period PRECHARGE command period ACTIVE bank a to ACTIVE bank b command Transition time Write recovery time Exit self refresh to ACTIVE command PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN t AC(3) AC(2) t AH t AS tCH t CL tCK(3) tCK(2) tCKH tCKS tCMH tCMS tDH tDS tHZ(3) tHZ(2) tLZ tOH tOHN tRAS tRC tRCD tREF tRFC tRP tRRD 5.4 5.4 t tT t WR tXSR 0.8 1.5 2.5 2.5 7 7.5 0.8 1.5 0.8 1.5 0.8 1.5 5.4 6 0.8 1.5 2.5 2.5 7.5 10 0.8 1.5 0.8 1.5 0.8 1.5 5.4 5.4 1 3 1.8 37 60 15 120,000 1 2 3 3 8 10 1 2 1 2 1 2 5.4 6 1 3 1.8 44 66 20 64 66 15 14 120,000 1.2 16 6 6 1 3 1.8 50 70 20 64 66 20 15 0.3 1 CLK + 7ns 14 67 6 6 0.3 1 CLK + 7.5ns 15 75 120,000 64 70 20 20 1.2 0.3 1 CLK + 7ns 15 80 1.2 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms ns ns ns 27 ns ns 7 24 ns ns 25 20 23 23 10 10 28 . Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. (Notes: 5, 6, 7, 8, 9, 11, 32; notes appear following parameter tables) READ/WRITE command to READ/WRITE command CKE to clock disable or power-down entry mode CKE to clock enable or power-down exit setup mode DQM to input data delay DQM to data mask during WRITEs DQM to data high-impedance during READs WRITE command to input data delay Data-in to ACTIVE command Data-in to precharge command Last data-in to burst stop command Last data-in to new READ/WRITE command Last data-in to precharge command LOAD MODE REGISTER command to ACTIVE or REFRESH command Data-out to high-impedance from CL = 3 precharge command CL = 2 PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN t CCD tCKED tPED t DQD tDQM t DQZ tDWD t DAL tDPL tBDL t CDL tRDL tMRD 1 1 1 0 0 2 0 4 2 1 1 2 2 1 1 1 0 0 2 0 5 2 1 1 2 2 1 1 1 0 0 2 0 4 2 1 1 2 2 t tROH(3) 3 2 3 2 3 2 tCK tROH(2) 17 CK tCK t CK CK tCK t CK tCK t CK tCK tCK t CK tCK tCK t tCK 17 14 14 17 17 17 17 15, 21 16, 21 17 17 16, 21 26 17 17 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. 1. All voltages referenced to Vss. 2. This parameter is sampled. VDD, VDDQ = +3.3V; f = 1 MHz, TA = 25°C; pin under test biased at 1.4V. 3. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time and the outputs open. 4. Enables on-chip refresh and address counters. 5. The minimum specifications are used only to indicate cycle time at which proper operation over the full temperature range is ensured (0°C ≤ TA ≤ +70°C). 6. An initial pause of 100µs is required after powerup, followed by two AUTO Refresh commands, before proper device operation is ensured. (VDD and VDDQ must be powered up simultaneously. Vss and VssQ must be at same potential.) The two AUTO Refresh command wake-ups should be repeated any time the tREF refresh requirement is exceeded. 7. AC characteristics assume tT = 1ns. 8. In addition to meeting the transition rate specification, the clock and CKE must transit between VIH and VIL (or between VIL and VIH) in a monotonic manner. 9. Outputs measured at 1.5V with equivalent load: Q 50pF 10. tHZ defines the time at which the output achieves the open circuit condition; it is not a reference to VOH or VOL. The last valid data element will meet t OH before going High-Z. 11. AC timing and Idd tests have VIL = 0V and VIH = 3V, with timing referenced to 1.5V crossover point. If the input transition time is longer than 1 ns, then the timing is referenced at VIL (MAX) and VIH (MIN) and no longer at the 1.5V crossover point. 12. Other input signals are allowed to transition no more than once every two clocks and are otherwise at valid VIH or VIL levels. 13. IDD specifications are tested after the device is properly initialized. 14. Timing actually specified by tCKS; clock(s) specified as a reference only at minimum cycle rate. 15. Timing actually specified by tWR plus tRP; clock(s) specified as a reference only at minimum cycle rate. 16. Timing actually specified by tWR. 17. Required clocks are specified by JEDEC functionality and are not dependent on any timing parameter. 18. The IDD current will increase or decrease proportionally according to the amount of frequency alteration for the test condition. 19. Address transitions average one transition every two clocks. 20. CLK must be toggled a minimum of two times during this period. 21. Based on tCK = 10ns for -10E, and tCK = 7.5ns for 133 and -13E. 22. VIH overshoot: VIH (MAX) = VDDQ + 2V for a pulse width ≤ 3ns, and the pulse width cannot be greater than one third of the cycle rate. VIL undershoot: VIL (MIN) = -2V for a pulse width ≤ 3ns. 23. The clock frequency must remain constant (stable clock is defined as a signal cycling within timing constraints specified for the clock pin) during access or precharge states (READ, WRITE, including tWR, and PRECHARGE commands). CKE may be used to reduce the data rate. 24. Auto precharge mode only. The precharge timing budget (tRP) begins 7ns for -13E; 7.5ns for -133 and 7ns for -10E after the first clock delay, after the last WRITE is executed. May not exceed limit set for precharge mode. 25. Precharge mode only. 26. JEDEC and PC100 specify three clocks. 27. tAC for -133/-13E at CL = 3 with no load is 4.6ns and is guaranteed by design. 28. Parameter guaranteed by design. 29. For -10E, CL= 2 and tCK = 10ns; for -133, CL = 3 and tCK = 7.5ns; for -13E, CL = 2 and tCK = 7.5ns. 30. CKE is HIGH during refresh command period t RFC (MIN) else CKE is LOW. The Idd6 limit is actually a nominal value and does not result in a fail value. 31. The value of tRAS used in -13E speed grade module SPDs is calculated from tRC - tRP = 45ns. 32. Refer to device data sheet for timing waveforms. 33. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 7, Data Validity, and Figure 8, Definition of Start and Stop). SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 7: Data Validity Figure 8: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 9: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge 128MB (x64, SR), 256MB (x64, DR) 168-PIN SDRAM UDIMM Table 18: EEPROM Device Select Code DEVICE TYPE IDENTIFIER SELECT CODE b7 b6 b5 b4 CHIP ENABLE b3 b2 RW b1 b0 Table 19: EEPROM Operating Modes MODE RW BIT WC BYTES INITIAL SEQUENCE ≥ ≤ Figure 10: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t AA t DH t BUF SDA OUT UNDEFINED All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V VDDSPD Vih VIL VOL ILI ILO ISB ICC SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = VDD or VSS POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz 2.3 3.6 VDDSPD × 0.7 VDDSPD + 0.5 -1 VDDSPD × 0.3 – 0.4 – 10 – 10 – 30 – 2 V V V V µA µA µA mA All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V tAA SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time tBUF tDH 0.2 1.3 200 tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT tSU:STA tSU:STO t WRC 0.9 100 0.6 0.6 10 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” 0 1 2 3 4 5 6 7 8 9 Number of Bytes Used by Micron Total Number of SPD Memory Bytes Memory Type Number of Row Addresses Number of Column Addresses Number of Module Ranks Module Data Width Module Data Width (Continued) Module Voltage Interface Levels 10 SDRAM Access From Clock, tAC, (CAS Latency = 3) Module Configuration Type Refresh Rate/type SDRAM Width (Primary SDRAM) Error-Checking SDRAM Data Width 11 12 13 14 15 16 17 18 19 20 21 22 23 SDRAM Cycle Time, tCK, (CAS Latency = 3) Minimum Clock Delay, tCCD Burst Lengths Supported Number of Banks on SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK, (CAS Latency = 2) 128 256 SDRAM 12 10 1 or 2 64 0 LVTTL 7 (-13E) 7.5 (-133) 8 (-10E) 5.4 (-13E/-133) 6 (-10E) 80 08 04 0C 0A 01 40 00 01 70 75 80 54 60 80 08 04 0C 0A 02 40 00 01 70 75 80 54 60 NONPARITY 15.625µs/SELF 8 NONE 1 00 80 08 00 01 00 80 08 00 01 1, 2, 4, 8, PAGE 4 2, 3 0 0 UNBUFFERED 0E 7.5 (13E) 10 (-133/-10E) 54 (-13E) 6 (-133/-10E) 8F 04 06 01 01 00 0E 75 A0 54 60 8F 04 06 01 01 00 0E 75 A0 54 60 24 SDRAM Access From Clock, tAC, (CAS Latency = 2) 25 SDRAM Cycle Time, tCK ,(CAS Latency = 1) 00 00 26 SDRAM Access From Clock, tAC, (CAS Latency = 1) 00 00 27 Minimum Row Precharge Time, tRP 28 Minimum Row Active to Row Active, tRRD 29 Minimum RAS# to CAS# Delay, tRCD 30 Minimum RAS# Pulse Width, tRAS (See note 1) 31 32 Module Rank Density 0F 14 0E 0F 14 0F 14 2D 2C 32 20 15 20 0F 14 0E 0F 14 0F 14 2D 2C 32 20 15 20 Command Address Setup, tAS PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 15 (-13E) 20 (-133/-10E) 14 (-13E) 15 (-133) 20 (-10E) 15 (-13E) 20 (-133/-10E) 45 (-13E) 44 (-133) 50 (-10E) 128MB 1.5 (-13E/-133) 2 (-10E) 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW” 33 Command Address Hold, tAH 34 Data Signal Input Setup, tDS 35 Data Signal Input Hold, tDH 0.8 (-13E/-133) 1 (-10E) 1.5 (-13E/-133) 2 (-10E) 0.8 (-13E/-133) 1 (-10E) 36–40 Reserved Bytes 41 Device Minimum Active/Auto-Refresh Time, tRC 60ns (-13E) 66ns (-133) 70ns (-10E) 42–61 Reserved Bytes 62 SPD Revision 63 Checksum For Bytes 0-62 64 65-71 72 73–90 91 92 93 94 95–98 99–125 126 127 Manufacturer's JEDEC ID Code Manufacturer's JEDEC Code (Cont.) Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continuted) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-Specific Data (RSVD) System Frequency REV.2.0 (-13E) (-133) (-10E) MICRON 00–12 0 100 MHz (-13E/-133, -10E) Year of Manufacture in BCD 08 10 15 20 08 10 00 3C 42 46 00 02 94 E0 2C 2C FF 00–0C Variable Data Variable Data 00 Variable Data Variable Data Variable Data 08 10 15 20 08 10 00 3C 42 46 00 12 95 E1 2D 2C FF 00–0C Variable Data Variable Data 00 Variable Data Variable Data Variable Data 64 64 AF FF NOTE: 1. The value of tRAS used for the -13E module is calculated from tRC - tRP. Actual device spec. vaule is 37ns. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Figure 11: 168-Pin DIMM Dimensions – 128MB STANDARD PCB FRONT VIEW 0.125 (3.18) MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U2 U1 U4 U3 U7 U6 U8 U9 0.118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) 0.700 (17.78) TYP U10 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.054 (1.37) 0.046 (1.17) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP PIN 84 (PIN 168 ON BACKSIDE) PIN 1 (PIN 85 ON BACKSIDE) 4.550 (115.57) LOW PROFILE PCB 0.125 (3.18) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (2X) U10 U1 U2 U4 U3 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00)R (2X) 2.625 (66.68) 0.039 (1.00) TYP PIN 1 (PIN 85 ON BACKSIDE) 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 (PIN 168 ON BACKSIDE) 4.550 (115.57) NOTE: MAX All dimensions in inches (millimeters); MIN or typical where noted. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. STANDARD PCB 0.157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) FRONT VIEW 0.079 (2.00) R (2X) U4 U3 U2 U1 U7 U6 U8 U9 0.118 (3.00) (2X) 1.380 (35.05) 1.370 (34.80) 0.700 (17.78) TYP U10 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.039 (1.00)R (2X) 2.625 (66.68) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U12 U11 U14 U13 U17 U16 U18 U19 PIN 168 PIN 85 0.157 (3.99) MAX LOW PROFILE PCB 5.256 (133.50) 5.244 (133.20) FRONT VIEW 0.079 (2.00) R (2X) U10 U1 U4 U3 U2 U6 U7 U8 U9 1.131 (28.73) 0.700 (17.78) 1.119 (28.42) TYP 0.118 (3.00) (2X) 0.118 (3.00) TYP 0.250 (6.35) TYP 0.118 (3.00) TYP 1.661 (42.18) 0.128 (3.25) (2X) 0.118 (3.00) 0.039 (1.00)R (2X) 2.625 (66.68) 0.039 (1.00) TYP 0.050 (1.27) TYP 0.054 (1.37) 0.046 (1.17) PIN 84 PIN 1 4.550 (115.57) BACK VIEW U12 U11 U13 U14 U16 U17 PIN 168 U18 U19 PIN 85 NOTE: MAX All dimensions in inches (millimeters); MIN or typical where noted. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 25 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved. Released (No Mark): ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. PDF: 09005aef8137b07b/Source: 09005aef8137b02d SD8_16C16_32x64AG.fm - Rev. E 12/10 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2003, 2004 Micron Technology, Inc. All rights reserved.