MT18KBZS1G72PKIZ-1G4E1

8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Features 1.35V DDR3L SDRAM ULP Mini-RDIMM MT18KBZS1G72PKZ – 8GB Features Figure 1: 244-Pin ULP Mini-RDIMM • DDR3L functionality and operations supported as defined in the component data sheet • 244-pin, ultra low profile (17.9mm), 82mm, miniregistered dual in-line memory module (ULP MiniRDIMM) • Fast data transfer rates: PC3-12800, PC3-10600, PC3-8500, or PC3-6400 • 8GB (1 Gig x 72) • VDD = 1.35V (1.283–1.45V) • VDD = 1.5V (1.425–1.575V) • Backward compatible to V DD = 1.5V ±0.075V • Supports ECC error detection and correction • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Dual rank, using 8Gb TwinDie ™ devices • On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM • 8 internal device banks • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Full module heat spreader • Selectable BC4 or BL8 on-the-fly (OTF) • Gold edge contacts • Halogen-free • Fly-by topology • Terminated control, command, and address bus Module height: 17.9mm (0.705in) Options Marking • Operating temperature – Commercial (0°C ≤ T A ≤ +70°C) – Industrial (–40°C ≤ T A ≤ +85°C)1 • Package – 244-pin Mini-RDIMM (halogen-free) • Frequency/CAS latency – 1.25ns @ CL = 11 (DDR3-1600) – 1.5ns @ CL = 9 (DDR3-1333) – 1.87ns @ CL = 7 (DDR3-1066) Note: None I Z -1G6 -1G4 -1G1 1. Contact Micron for industrial temperature module offerings. Table 1: Key Timing Parameters Data Rate (MT/s) Speed Grade Industry Nomenclature -1G6 PC3-12800 1600 -1G4 PC3-10600 -1G1 PC3-8500 -1G0 -80B tRP tRC CL = 9 CL = 8 CL = 7 CL = 6 CL = 5 (ns) (ns) (ns) 1333 1333 1066 1066 800 667 13.125 13.125 48.125 – 1333 1333 1066 1066 800 667 13.125 13.125 49.125 – – – 1066 1066 800 667 13.125 13.125 50.625 PC3-8500 – – – 1066 – 800 667 15 15 52.5 PC3-6400 – – – – – 800 667 15 15 52.5 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN CL = 11 CL = 10 tRCD Products and specifications discussed herein are subject to change by Micron without notice. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Features Table 2: Addressing Parameter 4GB Refresh count 8K Row address 64K A[15:0] Device bank address 8 BA[2:0] Device configuration 8Gb TwinDie (1 Gig x 8) Column address 1K A[9:0] Module rank address 2 S#[1:0] Table 3: Part Numbers and Timing Parameters – 8GB Modules Base device: MT41K1G8,1 8Gb 1.35V TwinDie DDR3L SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18KBZS1G72PK(I)Z-1G6__ 8GB 1 Gig x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11 MT18KBZS1G72PK(I)Z-1G4__ 8GB 1 Gig x 72 10.6 GB/s 1.5ns/1333 MT/s 9-9-9 MT18KBZS1G72PK(I)Z-1G1__ 8GB 1 Gig x 72 8.5 GB/s 1.87ns/1066 MT/s 7-7-7 Notes: 1. The data sheet for the base device can be found on Micron’s Web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18KBZS1G72PKZ-1G4E1. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Pin Assignments Pin Assignments Table 4: Pin Assignments 244-Pin DDR3 Mini-RDIMM Front 244-Pin DDR3 Mini-RDIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol 1 VTT 31 DQ24 61 VDD 92 DQ40 123 VTT 153 DQ29 183 A3 214 DQ45 2 VREFDQ 32 DQ25 62 A2 93 DQ41 124 VSS 154 VSS 184 A1 215 VSS 3 VSS 33 VSS 63 VDD 94 VSS 125 DQ4 155 DM3/ TDQS12 185 VDD 216 DM5/ TDQS14 4 DQ0 34 DQS3# 64 NC 95 DQS5# 126 DQ5 156 NF/ TDQS12# 186 CK0 217 NF/ TDQS14# 5 DQ1 35 DQS3 65 NC 96 DQS5 127 VSS 157 VSS 187 CK0# 218 VSS 6 VSS 36 VSS 66 VDD 97 VSS 128 DM0/ TDQS9 158 DQ30 188 VDD 219 DQ46 7 DQS0# 37 DQ26 67 VREFCA 98 DQ42 129 NF/ TDQS9# 159 DQ31 189 VDD 220 DQ47 8 DQS0 38 DQ27 68 VDD 99 DQ43 130 VSS 160 VSS 190 EVENT# 221 VSS 9 VSS 39 VSS 69 Par_In 100 VSS 131 DQ6 161 CB4 191 A0 222 DQ52 10 DQ2 40 CB0 70 VDD 101 DQ48 132 DQ7 162 CB5 192 VDD 223 DQ53 11 DQ3 41 CB1 71 A10 102 DQ49 133 VSS 163 VSS 193 BA1 224 VSS 12 VSS 42 VSS 72 BA0 103 VSS 134 DQ12 164 DM8/ TDQS17 194 VDD 225 DM6/ TDQS15 13 DQ8 43 DQS8# 73 VDD 104 DQS6# 135 DQ13 165 NF/ TDQS17# 195 RAS# 226 NF/ TDQS15# 14 DQ9 44 DQS8 74 WE# 105 DQS6 136 VSS 166 VSS 196 CS0# 227 VSS 15 VSS 45 VSS 75 CAS# 106 VSS 137 DM1/ TDQS10 167 CB6 197 VDD 228 DQ54 16 DQS1# 46 CB2 76 VDD 107 DQ50 138 NF/ TDQS10# 168 CB7 198 ODT0 229 DQ55 17 DQS1 47 CB3 77 S1# 108 DQ51 139 VSS 169 VSS 199 A13 230 VSS 18 VSS 48 VSS 78 ODT1 109 VSS 140 DQ14 170 NC 200 VDD 231 DQ60 19 DQ10 49 NC 79 VDD 110 DQ56 141 DQ15 171 NC 201 NC 232 DQ61 20 DQ11 50 RESET# 80 NC 111 DQ57 142 VSS 172 CKE1 202 NC 233 VSS 21 VSS 51 CKE0 81 NC 112 VSS 143 DQ20 173 VDD 203 VSS 234 DM7/ TDQS16 22 DQ16 52 VDD 82 VSS 113 DQS7# 144 DQ21 174 A15 204 DQ36 235 NF/ TDQS16# 23 DQ17 53 BA2 83 DQ32 114 DQS7 145 VSS 175 A14 205 DQ37 236 VSS 24 VSS 54 Err_Out# 84 DQ33 115 VSS 146 DM2/ TDQS11 176 VDD 206 VSS 237 DQ62 25 DQS2# 55 VDD 85 VSS 116 DQ58 147 NF/ TDQS11# 177 A12 207 DM4/ TDQS13 238 DQ63 26 DQS2 56 A11 86 DQS4# 117 DQ59 148 VSS 178 A9 208 NF/ TDQS13# 239 VSS 27 VSS 57 A7 87 DQS4 118 VSS 149 DQ22 179 VDD 209 VSS 240 VDDSPD 28 DQ18 58 VDD 88 VSS 119 SA0 150 DQ23 180 A8 210 DQ38 241 SA1 29 DQ19 59 A5 89 DQ34 120 SCL 151 VSS 181 A6 211 DQ39 242 SDA 30 VSS 60 A4 90 DQ35 121 SA2 152 DQ28 182 VDD 212 VSS 243 VSS 91 VSS 122 VTT 213 DQ44 244 VTT PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 5: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments Table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus. SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus. CBx I/O Check bits: Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQSx# I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type SDA I/O Description Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus. TDQSx, TDQSx# Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function. Err_Out# Output Parity error output: Parity error found on the command and address bus. (open drain) EVENT# Output Temperature event:The EVENT# pin is asserted by the temperature sensor when criti(open drain) cal temperature thresholds have been exceeded. VDD Supply Power supply: 1.5V ±0.075V. The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. VREFCA Supply Reference voltage: Control, command, and address VDD/2. VREFDQ Supply Reference voltage: DQ, DM VDD/2. VSS Supply Ground. VTT Supply Termination voltage: Used for control, command, and address VDD/2. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM DQ Map DQ Map Table 6: Component-to-Module DQ Map Component Reference Number Component DQ U1 U3 U5 U8 PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 6 131 U2 0 13 135 1 1 5 1 10 19 2 7 132 2 15 141 3 5 126 3 12 134 4 2 10 4 11 20 5 4 125 5 8 13 6 3 11 6 14 140 7 0 4 7 9 14 0 28 152 0 34 89 1 26 37 1 37 205 2 30 158 2 39 211 3 29 153 3 33 84 4 27 38 4 35 90 5 24 31 5 36 204 6 31 159 6 38 210 7 25 32 7 32 83 0 51 108 0 56 110 1 49 102 1 62 237 2 54 228 2 57 111 3 53 223 3 58 116 4 50 107 4 61 232 5 48 101 5 59 117 6 55 229 6 60 231 7 52 222 7 63 238 0 41 93 0 CB2 46 1 42 98 1 CB1 41 2 40 92 2 CB3 47 3 46 219 3 CB0 40 4 44 213 4 CB4 161 5 43 99 5 CB7 168 6 45 214 6 CB5 162 7 47 220 7 CB6 167 U4 U7 U10 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM DQ Map Table 6: Component-to-Module DQ Map (Continued) Component Reference Number Component DQ Module DQ Module Pin Number U11 0 18 28 1 17 23 2 19 29 3 16 22 4 20 143 5 22 149 6 21 144 7 23 150 PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN Component Reference Number 7 Component DQ Module DQ Module Pin Number Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram RS1# RS0# DQS0 DQS0# DM0/TDQS9 NF/TDQS9# DQS4 DQS4# DM4/TDQS13 NF/TDQS13# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ U1 U1b NU/ CS# DQS DQS# TDQS# U21 U1t ZQ DQS1 DQS1# DM1/TDQS10 NF/TDQS10# VSS DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ U2 U2b DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ U20 U2t ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ U3 U11b DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ U19 U11t ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ U4 U3b DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ ZQ NU/ CS# DQS DQS# TDQS# ZQ NU/ CS# DQS DQS# TDQS# U9 U8b DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# TDQS# CK0 CK0# DQ DQ DQ DQ DQ DQ DQ DQ ZQ CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 VSS DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ ZQ NU/ CS# DQS DQS# TDQS# DM/ TDQS U5 U10b DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# TDQS# U10 U5b DDR3 SDRAM DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ NU/ CS# DQS DQS# TDQS# U11 U7b DM/ TDQS DQ DQ DQ DQ DQ DQ DQ DQ SPD EEPROM/ Temperature sensor EVT A0 SDA A1 A2 SA0 SA1 SA2 EVENT# U13 U5t Rank0: U1b–U5b, U7b, U8b, U10b, U11b Rank1: U1t–U5t, U7t, U8t, U10t, U11t Clock, command, control, and address line terminations NU/ CS# DQS DQS# TDQS# RCKE[1:0], RA[15:0], RS#[1:0], RRAS#, RCAS#, RWE#, RODT[1:0], RBA[2:0] U12 U7t ZQ VSS CK CK# DDR3 SDRAM VTT DDR3 SDRAM VDD SPD EEPROM/ Temperature sensor DDR3 SDRAM Control, command and address termination VTT ZQ U9 SCL NU/ CS# DQS DQS# TDQS# ZQ VDD U17 U10t DDR3 SDRAM CK# ZQ VDDSPD NU/ CS# DQS DQS# TDQS# CK P L L RESET# VSS DM/ TDQS RS0#: Rank0 RS1#: Rank1 RBA[2:0] DDR3 SDRAM RA[15:0]: DDR3 SDRAM RRAS#: DDR3 SDRAM RCAS#: DDR3 SDRAM RWE#: DDR3 SDRAM RCKE0: Rank0 RCKE1: Rank1 RODT0: Rank0 RODT1: Rank1 Err_Out# a n d U14 U8t VSS DQS8 DQS8# DM8/TDQS17 NF/TDQS17# R E G iI S T E R S0# S1# BA[2:0] A[15:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 Par_In U15 U4t DQS7 DQS7# DM7/TDQS16 NF/TDQS16# DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 VSS U18 U3t DQ DQ DQ DQ DQ DQ DQ DQ VSS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 VSS VSS U8 U4b DM/ TDQS DQS6 DQS6# DM6/TDQS15 NF/TDQS15# NU/ CS# DQS DQS# TDQS# DQS3 DQS3# DM3/TDQS12 NF/TDQS12# NU/ CS# DQS DQS# TDQS# VSS DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 VSS VSS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 VSS DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQS5 DQS5# DM5/TDQS14 NF/TDQS14# NU/ CS# DQS DQS# TDQS# DQS2 DQS2# DM2/TDQS11 NF/TDQS11# U6 DM/ TDQS DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 VSS VREFCA DDR3 SDRAM VREFDQ DDR3 SDRAM VSS DDR3 SDRAM VSS Note: PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM General Description General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3. Registering Clock Driver Operation Registered DDR3 SDRAM modules use a registering clock driver device consisting of a register and a phase-lock loop (PLL). The device complies with the JEDEC standard "Definition of the SSTE32882 Registering Clock Driver with Parity and Quad Chip Selects for DDR3 RDIMM Applications." The register section of the registering clock driver latches command and address input signals on the rising clock edge. The PLL section of the registering clock driver receives and redrives the differential clock signals (CK, CK#) to the DDR3 SDRAM devices. The register(s) and PLL reduce clock, control, command, and address signals loading by isolating DRAM from the system controller. Parity Operations The registering clock driver includes an even parity function for checking parity. The memory controller accepts a parity bit at the Par_In input and compares it with the data received on A[15:0], BA[2:0], RAS#, CAS#, and WE#. Valid parity is defined as an even number of ones (1s) across the address and command inputs (A[15:0], BA[2:0], RAS#, CAS#, and WE#) combined with Par_In. Parity errors are flagged on Err_Out#. Address and command parity is checked during all DRAM operations and during control word WRITE operations to the registering clock driver. For SDRAM operations, the address is still propagated to the SDRAM even when there is a parity error. When writing to the internal control words of the registering clock driver, the write will be ignored if parity is not valid. For this reason, systems must connect the Par_In pins on the DIMM and provide correct parity when writing to the registering clock driver control word configuration registers. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The temperature from the integrated thermal sensor is monitored and converts into a digital word via the I2C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect." PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 7: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS –0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V Table 8: Operating Conditions Symbol Parameter VDD VDD supply voltage IVTT Termination reference current from VTT VTT Termination reference voltage (DC) – command/address bus II IOZ IVREF TA TC Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) Output leakage current; 0V ≤ VOUT ≤ VDD; DQ and ODT are disabled; ODT is HIGH Min Nom Max Units 1.283 1.35 1.45 V 1.425 1.5 1.575 V –600 – 600 mA 0.5 × VDD 0.51 × VDD + 20mV V 2 Address inputs, RAS#, CAS#, WE#, S#, CKE, ODT, BA, CK, CK# – – – µA 6 DM –4 0 4 DQ, DQS, DQS# –10 0 10 µA –18 0 18 µA 0 – 70 °C 3, 4 –40 – 85 0 – 95 °C 3, 4, 5 –40 – 95 Commercial Industrial DDR3 SDRAM component Commercial case operating temperature Industrial Notes: PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 1 0.49 × VDD 20mV VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) Module ambient operating temperature Notes 1. Module is backward-compatible with 1.5V operation. Refer to device specification for details and operation guidance. 2. VTT termination voltage in excess of the stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins. 3. TA and TC are simultaneous requirements. 4. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s Web site. 5. The refresh rate is required to double when 85°C < TC ≤ 95°C. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Electrical Specifications 6. Inputs are terminated to VDD/2. Input current is dependent on terminating resistance selected in register. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available on Micron’s web site. Module speed grades correlate with component speed grades, as shown below. Table 9: Module and Component Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -2G1 -093 -1G9 -107 -1G6 -125 -1G4 -15E -1G1 -187E -1G0 -187 -80C -25E -80B -25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM ICDD Specifications ICDD Specifications Table 10: DDR3L ICDD Specifications and Conditions – 8GB (Die Revision E) Values are for the MT41K1G8 DDR3L SDRAM only and are computed from values specified in the 8Gb 1.35V TwinDie component data sheet Parameter Symbol 1600 1333 1066 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE ICDD0 702 630 603 mA Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE ICDD1 801 765 738 mA Precharge power-down current: Slow exit ICDD2P0 324 324 324 mA Precharge power-down current: Fast exit ICDD2P1 450 414 396 mA Precharge quiet standby current ICDD2Q 450 414 405 mA Precharge standby current ICDD2N 450 423 414 mA Precharge standby ODT current ICDD2NT 513 477 450 mA Active power-down current ICDD3P 504 477 450 mA Active standby current ICDD3N 504 477 450 mA Burst read operating current ICDD4R 1620 1467 1314 mA Burst write operating current ICDD4W 1332 1197 1062 mA Refresh current ICDD5B 2277 2214 2178 mA Self refresh temperature current: MAX TC = 85°C ICDD6 360 360 360 mA ICDD6ET 450 450 450 mA All banks interleaved read current ICDD7 2187 1917 1647 mA Reset current ICDD8 360 360 360 mA Self refresh temperature current (SRT-enabled): MAX TC = 95°C PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Registering Clock Driver Specifications Registering Clock Driver Specifications Table 11: Registering Clock Driver Electrical Characteristics SSTE32882 devices or equivalent; Note 1 applies to entire table Parameter Symbol Pins Min Nom DC supply voltage VDD – Max Units Notes 1.283 1.35 1.45 V 1.425 1.5 1.575 V DC reference voltage VREF – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V DC termination voltage VTT – 0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV V AC high-level input voltage VIH(AC) Control, command, address VREF + 175mV – VDD + 400mV V AC low-level input voltage VIL(AC) Control, command, address –0.4 – VREF - 175mV V DC high-level input voltage VIH(DC) Control, command, address VREF + 100mV – VDD + 0.4 V DC low-level input voltage VIL(DC) Control, command, address –0.4 – VREF - 100mV V High-level input voltage VIH(CMOS) RESET#, MIRROR 0.65 × VDD – VDD V Low-level input voltage VIL(CMOS) RESET#, MIRROR 0 – 0.35 × VDD V Differential input crosspoint voltage range VIX(AC) CK, CK#, FBIN, FBIN# 0.5 × VDD - 175mV 0.5 × VDD 0.5 × VDD + 175mV V Differential input voltage VID(AC) CK, CK# 350 – VDD + TBD mV High-level output current IOH Err_Out# – – TBD mA Low-level output current IOL Err_Out# TBD – TBD mA Notes: PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 2 1. Timing and switching specifications for the register listed are critical for proper operation of the DDR3 SDRAM RDIMMs. These are meant to be a subset of the parameters for the specific device used on the module. 2. The register is backward-compatible with 1.5V operation. Refer to device specification for details and operation guidance. 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD. Table 12: Temperature Sensor with SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3.0 3.6 V Supply current: VDD = 3.3V IDD – 2.0 mA Input high voltage: Logic 1; SCL, SDA VIH VDDSPD x 0.7 VDDSPD + 1 V Input low voltage: Logic 0; SCL, SDA VIL –0.5 VDDSPD x 0.3 V Output low voltage: IOUT = 2.1mA VOL – 0.4 V Input current IIN –5.0 5.0 µA Temperature sensing range – –40 125 °C Temperature sensor accuracy (class B) – –1.0 1.0 °C Supply voltage Table 13: Temperature Sensor and SPD EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units tBUF 4.7 – µs SDA fall time tF 20 300 ns SDA rise time tR – 1000 ns tHD:DAT 200 900 ns Time bus must be free before a new transition can start Data hold time Start condition hold time tH:STA 4.0 – µs Clock HIGH period tHIGH 4.0 50 µs Clock LOW period tLOW 4.7 – µs tSCL 10 100 kHz Data setup time tSU:DAT 250 – ns Start condition setup time tSU:STA 4.7 – µs Stop condition setup time tSU:STO 4.0 – µs SCL clock frequency PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Temperature Sensor with Serial Presence-Detect EEPROM EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor’s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved. 8GB (x72, ECC, DR) 244-Pin DDR3L ULP Mini-RDIMM Module Dimensions Module Dimensions Figure 3: 244-Pin DDR3 ULP Mini-RDIMM Front view 3.80 (0.15) MAX 82.15 (3.234) 81.85 (3.222) 1.0 (0.039) R X2 U1 U2 U3 1.8 (0.071) D X2 U4 U6 U5 10.0 (0.394) TYP 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP Pin 1 1.1 (0.043) 0.9 (0.035) 0.5 (0.02) R 0.6 (0.024) 0.45 (0.018) TYP TYP 43.9 (1.73) TYP 17.91 (0.705) 17.89 (0.704) Pin 122 78.0 (3.071) TYP Back view 45° X4 U7 U8 U9 U10 U11 3.3 (0.13) TYP 3.6 (0.142) TYP Pin 244 33.6 (1.323) TYP 3.2 (0.126) TYP Pin 123 38.4 (1.512) TYP With heat spreader attached 5.94 (0.234) TYP U1 U7 Notes: U2 U8 U3 U9 U4 U6 U10 U11 U5 6.94 (0.273) TYP 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 www.micron.com/productsupport Customer Comment Line: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. TwinDie is a trademark of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef84d5d3b7 kbzs18c1gx72pkz.pdf - Rev. E 5/13 EN 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2012 Micron Technology, Inc. All rights reserved.