2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Features
1.35V DDR3L SDRAM UDIMM
MT18KSF25672AZ – 2GB
MT18KSF51272AZ – 4GB
Features
Figure 1: 240-Pin UDIMM (MO-269 R/C E)
Module Height: 30.0mm (1.181 in.)
• DDR3L functionality and operations supported as
defined in the component data sheet
• 240-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC3-12800, PC3-10600,
PC3-8500, or PC3-6400
• 2GB (256 Meg x 72), 4GB (512 Meg x 72)
• VDD = 1.35V (1.235–1.45V)
• VDD = 1.5V (1.425–1.575V)
• Backward compatible to VDD = 1.5V ±0.075V
• VDDSPD = 3.0–3.6V
• Supports ECC error detection and correction
• Nominal and dynamic on-die termination (ODT) for
data, strobe, and mask signals
• Dual rank
• On-board I2C temperature sensor with integrated
serial presence-detect (SPD) EEPROM
• 8 internal device banks
• Fixed burst chop (BC) of 4 and burst length (BL) of 8
via the mode register set (MRS)
• Selectable BC4 or BL8 on-the-fly (OTF)
• Gold edge contacts
• Halogen-free
• Fly-by topology
• Terminated control, command, and address bus
Options
• Operating temperature
– Commercial (0°C ≤ TA ≤ +70°C)
• Package
– 240-pin DIMM (halogen-free)
• Frequency/CAS latency
– 1.25ns @ CL = 11 (DDR3-1600)
– 1.5ns @ CL = 9 (DDR3-1333)
– 1.87ns @ CL = 7 (DDR3-1066)
Marking
None
Z
-1G6
-1G4
-1G1
Table 1: Key Timing Parameters
Data Rate (MT/s)
Speed
Grade
Industry
Nomenclature
-1G6
PC3-12800
1600
-1G4
PC3-10600
–
-1G1
PC3-8500
-1G0
-80B
tRP
tRC
CL = 9
CL = 8
CL = 7
CL = 6
CL = 5
(ns)
(ns)
(ns)
1333
1333
1066
1066
800
667
13.125
13.125
48.125
1333
1333
1066
1066
800
667
13.125
13.125
49.125
–
–
–
1066
1066
800
667
13.125
13.125
50.625
PC3-8500
–
–
–
1066
–
800
667
15
15
52.5
PC3-6400
–
–
–
–
–
800
667
15
15
52.5
1
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
PDF: 09005aef83cd9e75
ksf18c256_512x72az.pdf – Rev. D 5/11 EN
CL = 11 CL = 10
tRCD
Products and specifications discussed herein are subject to change by Micron without notice.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Features
Table 2: Addressing
Parameter
Refresh count
Row address
2GB
4GB
8K
8K
16K A[13:0]
32K A[14:0]
Device bank address
8 BA[2:0]
8 BA[2:0]
Device configuration
1Gb (128 Meg x8)
2Gb (256 Meg x 8)
Column address
1K A[9:0]
1K A[9:0]
Module rank address
2 S#[1:0]
2 S#[1:0]
Table 3: Part Numbers and Timing Parameters – 2GB Modules
Base device: MT41K128M8,11.35V 1Gb DDR3L SDRAM
Module
Part Number2
Density
Configuration
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
MT18KSF25672AZ-1G6__
2GB
256 Meg x 72
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT18KSF25672AZ-1G4__
2GB
256 Meg x 72
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT18KSF25672AZ-1G1__
2GB
256 Meg x 72
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Module
Bandwidth
Memory Clock/
Data Rate
Clock Cycles
(CL-tRCD-tRP)
Table 4: Part Numbers and Timing Parameters – 4GB Modules
Base device: MT41K256M8,11.35V 2Gb DDR3L SDRAM
Module
Part Number2
Density
Configuration
MT18KSF51272AZ-1G6__
4GB
512 Meg x 72
12.8 GB/s
1.25ns/1600 MT/s
11-11-11
MT18KSF51272AZ-1G4__
4GB
512 Meg x 72
10.6 GB/s
1.5ns/1333 MT/s
9-9-9
MT18KSF51272AZ-1G1__
4GB
512 Meg x 72
8.5 GB/s
1.87ns/1066 MT/s
7-7-7
Notes:
1. The data sheet for the base device can be found on Micron’s Web site.
2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18KSF51272AZ-1G4M1.
PDF: 09005aef83cd9e75
ksf18c256_512x72az.pdf – Rev. D 5/11 EN
2
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Pin Assignments
Pin Assignments
Table 5: Pin Assignments
240-Pin DDR3 UDIMM Front
240-Pin DDR3 UDIMM Back
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
Pin
Symbol
1
VREFDQ
31
DQ25
61
A2
91
DQ41
121
VSS
151
VSS
181
A1
211
VSS
2
VSS
32
VSS
62
VDD
92
VSS
122
DQ4
152
DM3
182
VDD
212
DM5
3
DQ0
33
DQS3#
63
CK1
93
DQS5#
123
DQ5
153
NC
183
VDD
213
NC
4
DQ1
34
DQS3
64
CK1#
94
DQS5
124
VSS
154
VSS
184
CK0
214
VSS
5
VSS
35
VSS
65
VDD
95
VSS
125
DM0
155
DQ30
185
CK0#
215
DQ46
6
DQS0#
36
DQ26
66
VDD
96
DQ42
126
NC
156
DQ31
186
VDD
216
DQ47
7
DQS0
37
DQ27
67
VREFCA
97
DQ43
127
VSS
157
VSS
187
EVENT#
217
VSS
8
VSS
38
VSS
68
NC
98
VSS
128
DQ6
158
CB4
188
A0
218
DQ52
9
DQ2
39
CB0
69
VDD
99
DQ48
129
DQ7
159
CB5
189
VDD
219
DQ53
10
DQ3
40
CB1
70
A10
100
DQ49
130
VSS
160
VSS
190
BA1
220
VSS
11
VSS
41
VSS
71
BA0
101
VSS
131
DQ12
161
DM8
191
VDD
221
DM6
12
DQ8
42
DQS8#
72
VDD
102
DQS6#
132
DQ13
162
NC
192
RAS#
222
NC
13
DQ9
43
DQS8
73
WE#
103
DQS6
133
VSS
163
VSS
193
S0#
223
VSS
14
VSS
44
VSS
74
CAS#
104
VSS
134
DM1
164
CB6
194
VDD
224
DQ54
15
DQS1#
45
CB2
75
VDD
105
DQ50
135
NC
165
CB7
195
ODT0
225
DQ55
16
DQS1
46
CB3
76
S1#
106
DQ51
136
VSS
166
VSS
196
A13
226
VSS
17
VSS
47
VSS
77
ODT1
107
VSS
137
DQ14
167
NU
197
VDD
227
DQ60
18
DQ10
48
NC
78
VDD
108
DQ56
138
DQ15
168
RESET#
198
NC
228
DQ61
19
DQ11
49
NC
79
NC
109
DQ57
139
VSS
169
CKE1
199
VSS
229
VSS
20
VSS
50
CKE0
80
VSS
110
VSS
140
DQ20
170
VDD
200
DQ36
230
DM7
21
DQ16
51
VDD
81
DQ32
111
DQS7#
141
DQ21
171
NF
201
DQ37
231
NC
22
DQ17
52
BA2
82
DQ33
112
DQS7
142
VSS
172
A14
202
VSS
232
VSS
23
VSS
53
NC
83
VSS
113
VSS
143
DM2
173
VDD
203
DM4
233
DQ62
24
DQS2#
54
VDD
84
DQS4#
114
DQ58
144
NC
174
A12
204
NC
234
DQ63
25
DQS2
55
A11
85
DQS4
115
DQ59
145
VSS
175
A9
205
VSS
235
VSS
26
VSS
56
A7
86
VSS
116
VSS
146
DQ22
176
VDD
206
DQ38
236
VDDSPD
27
DQ18
57
VDD
87
DQ34
117
SA0
147
DQ23
177
A8
207
DQ39
237
SA1
28
DQ19
58
A5
88
DQ35
118
SCL
148
VSS
178
A6
208
VSS
238
SDA
29
VSS
59
A4
89
VSS
119
SA2
149
DQ28
179
VDD
209
DQ44
239
VSS
30
DQ24
60
VDD
90
DQ40
120
VTT
150
DQ29
180
A3
210
DQ45
240
VTT
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Pin Descriptions
Pin Descriptions
The pin description table below is a comprehensive list of all possible pins for all DDR3
modules. All pins listed may not be supported on this module. See Pin Assignments for
information specific to this module.
Table 6: Pin Descriptions
Symbol
Type
Description
Ax
Input
Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location
out of the memory array in the respective bank. A10 sampled during a PRECHARGE
command determines whether the PRECHARGE applies to one bank (A10 LOW, bank
selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code
during a LOAD MODE command. See the Pin Assignments Table for density-specific
addressing information.
BAx
Input
Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or
PRECHARGE command is being applied. BA define which mode register (MR0, MR1,
MR2, or MR3) is loaded during the LOAD MODE command.
CKx,
CKx#
Input
Clock: Differential clock inputs. All control, command, and address input signals are
sampled on the crossing of the positive edge of CK and the negative edge of CK#.
CKEx
Input
Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM.
DMx
Input
Data mask (x8 devices only): DM is an input mask signal for write data. Input data
is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the
DQ and DQS pins.
ODTx
Input
On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation,
ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input
will be ignored if disabled via the LOAD MODE command.
Par_In
Input
Parity input: Parity bit for Ax, RAS#, CAS#, and WE#.
RAS#, CAS#, WE#
Input
Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being
entered.
RESET#
Input
(LVCMOS)
Reset: RESET# is an active LOW asychronous input that is connected to each DRAM
and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed.
Sx#
Input
Chip select: Enables (registered LOW) and disables (registered HIGH) the command
decoder.
SAx
Input
Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus.
SCL
Input
Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus.
CBx
I/O
Check bits: Used for system error detection and correction.
DQx
I/O
Data input/output: Bidirectional data bus.
DQSx,
DQSx#
I/O
Data strobe: Differential data strobes. Output with read data; edge-aligned with
read data; input with write data; center-aligned with write data.
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© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Pin Descriptions
Table 6: Pin Descriptions (Continued)
Symbol
Type
SDA
I/O
TDQSx,
TDQSx#
Output
Description
Serial data: Used to transfer addresses and data into and out of the temperature sensor/
SPD EEPROM on the I2C bus.
Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD
MODE command to the extended mode register (EMR). When TDQS is enabled, DM is
disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are
no function.
Err_Out#
Output
Parity error output: Parity error found on the command and address bus.
(open drain)
EVENT#
Output
Temperature event:The EVENT# pin is asserted by the temperature sensor when crit(open drain) ical temperature thresholds have been exceeded.
VDD
Supply
Power supply: 1.35V(1.283-1.45V) backward-compatible to 1.5V(1.425-1.575V). The
component VDD and VDDQ are connected to the module VDD.
VDDSPD
Supply
Temperature sensor/SPD EEPROM power supply: 3.0–3.6V.
VREFCA
Supply
Reference voltage: Control, command, and address VDD/2.
VREFDQ
Supply
Reference voltage: DQ, DM VDD/2.
VSS
Supply
Ground.
VTT
Supply
Termination voltage: Used for control, command, and address VDD/2.
NC
–
No connect: These pins are not connected on the module.
NF
–
No function: These pins are connected within the module, but provide no functionality.
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ksf18c256_512x72az.pdf – Rev. D 5/11 EN
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© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
DQ Map
DQ Map
Table 7: Component-to-Module DQ Map
Component
Reference
Number
Component
DQ
U1
U3
U5
U7
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
2
9
U2
0
10
18
1
5
123
1
13
132
2
7
129
2
15
138
3
0
3
3
8
12
4
6
128
4
14
137
5
4
122
5
12
131
6
3
10
6
11
19
7
1
4
7
9
13
0
18
27
0
26
36
1
21
141
1
29
150
2
23
147
2
31
156
3
6
21
3
24
30
4
22
146
4
30
155
5
20
140
5
28
149
6
19
28
6
27
37
7
17
22
7
25
31
0
CB2
45
0
34
87
1
CB5
159
1
37
201
2
CB7
165
2
39
207
3
CB0
39
3
33
82
4
CB6
164
4
38
206
5
CB4
158
5
36
200
6
CB3
46
6
35
88
7
CB1
40
7
32
81
0
42
96
0
50
105
1
45
210
1
53
219
2
47
216
2
55
225
3
41
91
3
49
100
4
46
215
4
54
224
5
44
209
5
52
218
6
43
97
6
51
106
7
40
90
7
48
99
PDF: 09005aef83cd9e75
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U4
U6
U8
6
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
DQ Map
Table 7: Component-to-Module DQ Map (Continued)
Component
Reference
Number
Component
DQ
U9
U12
U14
U16
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
0
58
114
U11
0
61
228
1
61
228
1
58
114
2
63
234
2
57
109
3
57
109
3
63
234
4
62
233
4
56
108
5
60
227
5
59
115
6
59
115
6
60
227
7
56
108
7
62
233
0
53
219
0
45
210
1
50
105
1
42
96
2
49
100
2
41
91
3
55
225
3
47
216
4
48
99
4
40
90
5
51
106
5
43
97
6
52
218
6
44
209
7
54
224
7
46
215
0
37
201
0
CB5
159
1
34
87
1
CB2
45
2
33
82
2
CB0
39
3
39
207
3
CB7
165
4
32
81
4
CB1
40
5
35
88
5
CB3
46
6
36
200
6
CB4
158
7
38
206
7
CB6
164
0
29
150
0
21
141
1
26
36
1
18
27
2
24
30
2
16
21
3
31
156
3
23
147
4
25
31
4
17
22
5
27
37
5
19
28
6
28
149
6
20
140
7
30
155
7
22
146
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U13
U15
U17
7
Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
DQ Map
Table 7: Component-to-Module DQ Map (Continued)
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
Component
Reference
Number
Component
DQ
Module DQ
Module Pin
Number
U18
0
13
132
U19
0
5
123
1
10
18
1
2
9
2
8
12
2
0
3
3
15
138
3
7
129
4
9
13
4
1
4
5
11
19
5
3
10
6
12
131
6
4
122
7
14
137
7
6
128
PDF: 09005aef83cd9e75
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© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Functional Block Diagram
Functional Block Diagram
Figure 2: Functional Block Diagram
S1#
S0#
DQS0
DQS0#
DM0
DQS4
DQS4#
DM4
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
VSS
U1
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
VSS
U19
ZQ
DQS1
DQS1#
DM1
VSS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
VSS
U2
U3
U18
U17
ZQ
DM CS# DQS DQS#
U4
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
U16
U5
U15
CAS#
WE#
ODT0
ODT1
RESET#
BA[2:0]: DDR3 SDRAM
A[14/13:0]: DDR3 SDRAM
RAS#: DDR3 SDRAM
CAS#: DDR3 SDRAM
WE#: DDR3 SDRAM
CKE0: Rank 0
CKE1: Rank 1
ODT0: Rank 0
ODT1: Rank 1
RESET#: DDR3 SDRAM
Note:
PDF: 09005aef83cd9e75
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DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U9
U11
ZQ
VSS
Rank 0: U1–U9
Rank 1: U11–U19
SCL
U10
Temperature
sensor/
SPD EEPROM
EVT A0
CK0
CK0#
Rank 0
CK1
CK1#
Rank 1
SDA
A1 A2
SA0 SA1 SA2
EVENT#
ZQ
VSS
CKE0
CKE1
ZQ
VSS
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
VSS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U12
DQS7
DQS7#
DM7
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U8
VSS
CB0
CB1
CB2
CB3
CB4
CB5
CB6
CB7
VSS
BA[2:0]
A[14/13:0]
RAS#
ZQ
DM CS# DQS DQS#
DQS8
DQS8#
DM8
U13
VSS
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U7
DQS6
DQS6#
DM6
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
VSS
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DM CS# DQS DQS#
DQS3
DQS3#
DM3
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
U14
ZQ
DM CS# DQS DQS#
ZQ
DM CS# DQS DQS#
U6
VSS
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
VSS
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS5
DQS5#
DM5
DM CS# DQS DQS#
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQS2
DQS2#
DM2
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
VSS
DQ
DQ
DQ
DQ
DQ
DQ
DQ
DQ
ZQ
VDDSPD
VDD
Clock, control, command, and address line terminations:
Temperature sensor/SPD EEPROM
DDR3 SDRAM
VREFCA
CKE[1:0], A[14/13:0],
RAS#, CAS#, WE#,
Control, command, and address termination
ODT[1:0], BA[2:0],
S#[1:0]
DDR3 SDRAM
VREFDQ
DDR3 SDRAM
VSS
DDR3 SDRAM
VTT
CK
CK#
DDR3
SDRAM
VTT
DDR3
SDRAM
VDD
1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor
that is tied to ground. It is used for the calibration of the component’s ODT and output
driver.
9
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
General Description
General Description
DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is
essentially a 8n-prefetch architecture with an interface designed to transfer two data
words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM
module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the
internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK
and CK# to capture commands, addresses, and control signals. Differential clocks and
data strobes ensure exceptional noise immunity for these signals and provide precise
crossing points to capture input signals.
Fly-By Topology
DDR3 modules use faster clock speeds than earlier DDR technologies, making signal
quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock,
control, command, and address pin on each DRAM is connected to a single trace and
terminated (rather than a tree structure, where the termination is off the module near
the connector). Inherent to fly-by topology, the timing skew between the clock and DQS
signals can be easily accounted for by using the write-leveling feature of DDR3.
Temperature Sensor with Serial Presence-Detect EEPROM
Thermal Sensor Operations
The temperature from the integrated thermal sensor is monitored and converts into a
digital word via the I2C bus. System designers can use the user-programmable registers
to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1,
"Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor."
Serial Presence-Detect EEPROM Operation
DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a
256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM
Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use
by the customer. System READ/WRITE operations between the master (system logic)
and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL
(clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to VSS, permanently disabling hardware write protection. For further information refer to Micron
technical note TN-04-42, "Memory Module Serial Presence-Detect."
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Electrical Specifications
Electrical Specifications
Stresses greater than those listed may cause permanent damage to the module. This is a
stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to
absolute maximum rating conditions for extended periods may adversely affect reliability.
Table 8: Absolute Maximum Ratings
Symbol
Parameter
Min
Max
Units
VDD
VDD supply voltage relative to VSS
–0.4
1.975
V
VIN, VOUT
Voltage on any pin relative to VSS
–0.4
1.975
V
Table 9: Operating Conditions
Symbol
Parameter
Min
Nom
Max
VDD supply voltage
1.283
1.35
1.45
V
1.425
1.5
1.575
V
VREFCA(DC) Input reference voltage command/
address bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
VREFDQ(DC) I/O reference voltage DQ bus
0.49 × VDD
0.5 × VDD
0.51 × VDD
V
–600
–
600
mA
VDD
IVTT
Termination reference current from VTT
VTT
Termination reference voltage (DC) –
command/address bus
II
Input leakage current; Any
input 0V ≤ VIN ≤ VDD; VREF
input 0V ≤ VIN ≤ 0.95V
(All other pins not under
test = 0V)
0.49 × VDD - 20mV 0.5 × VDD 0.51 × VDD + 20mV
Address inputs, RAS#,
CAS#, WE#,
BA
–36
0
36
S#, CKE,
ODT, CK,
CK#
–18
0
18
DM
–4
0
4
Units Notes
V
1
2
µA
IOZ
Output leakage current; 0V DQ, DQS,
≤ VOUT ≤ VDDQ; DQ and ODT DQS#
are disabled; ODT is HIGH
–10
0
10
µA
IVREF
VREF supply leakage current; VREFDQ =
VDD/2 or VREFCA = VDD/2 (All other pins
not under test = 0V)
–18
0
18
µA
TA
Module ambient operating
temperature
Commercial
0
–
70
°C
3, 4
TC
DDR3 SDRAM component
Commercial
case operating temperature
0
–
95
°C
3, 4, 5
Notes:
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1. Module is backward-compatible with 1.5V operation. Refer to device specification for
details and operation guidance.
2. VTT termination voltage in excess of the stated limit will adversely affect the command
and address signals’ voltage margin and will reduce timing margins.
3. TA and TC are simultaneous requirements.
11
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Electrical Specifications
4. For further information, refer to technical note TN-00-08: ”Thermal Applications,”
available on Micron’s Web site.
5. The refresh rate is required to double when 85°C < TC ≤ 95°C.
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
DRAM Operating Conditions
DRAM Operating Conditions
Recommended AC operating conditions are given in the DDR3 component data sheets.
Component specifications are available on Micron’s Web site. Module speed grades correlate with component speed grades, as shown below.
Table 10: Module and Component Speed Grades
DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades
Module Speed Grade
Component Speed Grade
-1G9
-107
-1G6
-125
-1G4
-15E
-1G1
-187E
-1G0
-187
-80C
-25E
-80B
-25
Design Considerations
Simulations
Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length
matching, and decoupling. However, good signal integrity starts at the system level.
Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system.
Power
Operating voltages are specified at the DRAM, not at the edge connector of the module.
Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained.
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
IDD Specifications
IDD Specifications
Table 11: DDR3 IDD Specifications and Conditions – 2GB (Die Revision G)
Values are for the MT41K128M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 1Gb (128 Meg x
8) component data sheet
Parameter
Symbol
1600
1333
1066
Units
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
IDD01
783
738
693
mA
1
918
873
828
mA
2
216
216
216
mA
Precharge power-down current: Fast exit
IDD2P1
2
630
540
450
mA
Precharge quiet standby current
IDD2Q2
810
810
720
mA
2
810
810
720
mA
IDD2NT
2
603
558
558
mA
Active power-down current
IDD3P
2
630
630
540
mA
Active standby current
IDD3N2
810
810
720
mA
Burst read operating current
IDD4R1
1413
1278
1098
mA
Burst write operating current
IDD4W
1
1458
1323
1143
mA
Refresh current
IDD5B1
1683
1638
1593
mA
Self refresh temperature current: MAX TC = 85°C
IDD62
144
144
144
mA
Precharge power-down current: Slow exit
IDD1
IDD2P0
Precharge standby current
IDD2N
Precharge standby ODT current
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
2
IDD6ET
180
180
180
mA
1
2358
2313
1908
mA
2
252
252
252
mA
IDD7
Reset current
IDD8
Notes:
PDF: 09005aef83cd9e75
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1. One module rank in the active IDD; the other rank in IDD2P0 (slow exit).
2. All ranks in this IDD condition.
14
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© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
IDD Specifications
Table 12: DDR3 IDD Specifications and Conditions – 4GB (Die Revision M)
Values are for the MT41K256M8 DDR3L SDRAM only and are computed from values specified in the 1.35V 2Gb (256 Meg x
8) component data sheet
Parameter
Symbol
1600
1333
1066
Units
IDD01
Operating current 0: One bank ACTIVATE-to-PRECHARGE
Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE
1
603
558
mA
783
738
693
mA
IDD2P0
2
216
216
216
mA
Precharge power-down current: Fast exit
IDD2P1
2
594
504
414
mA
Precharge quiet standby current
IDD2Q2
594
504
414
mA
2
630
540
450
mA
2
Precharge power-down current: Slow exit
Precharge standby current
IDD1
648
IDD2N
Precharge standby ODT current
IDD2NT
468
423
378
mA
Active power-down current
IDD3P
2
846
756
666
mA
Active standby current
IDD3N2
936
846
756
mA
1
1368
1233
1098
mA
1
1233
1098
963
mA
1
Burst read operating current
IDD4R
Burst write operating current
IDD4W
Refresh current
IDD5B
1818
1773
1728
mA
Self refresh temperature current: MAX TC = 85°C
IDD62
216
216
216
mA
Self refresh temperature current (SRT-enabled): MAX TC = 95°C
All banks interleaved read current
IDD6ET
270
270
270
mA
1
2088
1953
1818
mA
2
252
252
252
mA
IDD7
Reset current
IDD8
Notes:
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2
1. One module rank in the active IDD; the other rank in IDD2P0 (slow exit).
2. All ranks in this IDD condition.
15
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© 2009 Micron Technology, Inc. All rights reserved.
2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
Temperature Sensor with Serial Presence-Detect EEPROM
The temperature sensor continuously monitors the module's temperature and can be
read back at any time over the I2C bus shared with the SPD EEPROM.
Serial Presence-Detect
For the latest SPD data, refer to Micron's SPD page: www.micron.com/SPD.
Table 13: Temperature Sensor with SPD EEPROM Operating Conditions
Parameter/Condition
Symbol
Min
Max
Units
VDDSPD
3.0
3.6
V
Supply current: VDD = 3.3V
IDD
–
2.0
mA
Input high voltage: Logic 1; SCL, SDA
VIH
1.45
VDDSPD + 1
V
Input low voltage: Logic 0; SCL, SDA
VIL
–
0.55
V
Output low voltage: IOUT = 2.1mA
VOL
–
0.4
V
Input current
IIN
–5.0
5.0
µA
Temperature sensing range
–
–40
125
°C
Temperature sensor accuracy (class B)
–
–1.0
1.0
°C
Supply voltage
Table 14: Temperature Sensor and EEPROM Serial Interface Timing
Parameter/Condition
Symbol
Min
Max
Units
tBUF
4.7
–
µs
SDA fall time
tF
20
300
ns
SDA rise time
tR
–
1000
ns
tHD:DAT
200
900
ns
Start condition hold time
tH:STA
4.0
–
µs
Clock HIGH period
tHIGH
4.0
50
µs
Clock LOW period
tLOW
4.7
–
µs
tSCL
10
100
kHz
Data setup time
tSU:DAT
250
–
ns
Start condition setup time
tSU:STA
4.7
–
µs
Stop condition setup time
tSU:STO
4.0
–
µs
Time bus must be free before a new transition can
start
Data hold time
SCL clock frequency
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Temperature Sensor with Serial Presence-Detect EEPROM
EVENT# Pin
The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD
EEPROM, EVENT# is a temperature sensor output used to flag critical events that can
be set up in the sensor’s configuration register.
EVENT# has three defined modes of operation: interrupt mode, compare mode, and
critical temperature mode. Event thresholds are programmed in the 0x01 register using
a hysteresis. The alarm window provides a comparison window, with upper and lower
limits set in the alarm upper boundary register and the alarm lower boundary register,
respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user.
The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user.
This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window.
The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by
the user and returns to the logic HIGH state only when the temperature falls below the
programmed thresholds.
Critical temperature mode triggers EVENT# only when the temperature has exceeded
the programmed critical trip point. When the critical trip point has been reached, the
temperature sensor goes into comparator mode, and the critical EVENT# cannot be
cleared through software.
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2GB, 4GB (x72, ECC, DR) 240-Pin 1.35V DDR3L UDIMM
Module Dimensions
Module Dimensions
Figure 3: 240-Pin DDR3 UDIMM
FRONT VIEW
4.0 (0.157)
MAX
133.50 (5.256)
133.20 (5.244)
0.9 (0.035) TYP
0.50 (0.02) R
(4X)
0.75 (0.03) R
(8X)
U1
U2
U3
U4
U5
2.50 (0.098) D
(2X)
U6
U7
U8
U9
30.50 (1.20)
23.3 (0.92) 29.85 (1.175)
TYP
17.3 (0.68)
TYP
U10
2.30 (0.091) TYP
0.76 (0.030) R
PIN 1
2.20 (0.087) TYP
1.0 (0.039)
TYP
1.45 (0.057) TYP
9.5 (0.374)
TYP
0.80 (0.031)
TYP
1.37 (0.054)
1.17 (0.046)
PIN 120
54.68 (2.15)
TYP
123.0 (4.84)
TYP
15.0 (0.59)
TYP
(4X)
1.0 (0.039) R (8X)
BACK VIEW
45°, 4X
5.1 (0.2) TYP
3.1 (0.122) 2X TYP
U11
U12
U13
U14
U15
U16
U17
U18
U19
3.0 (0.118) 4X TYP
3.05 (0.12) TYP
PIN 240
Notes:
PIN 121
5.0 (0.197) TYP
47.0 (1.85)
TYP
71.0 (2.79)
TYP
1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted.
2. The dimensional diagram is for reference only.
8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900
www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur.
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ksf18c256_512x72az.pdf – Rev. D 5/11 EN
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Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2009 Micron Technology, Inc. All rights reserved.