MT18KSF2G72HZ-1G6A2

16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Features 1.35V DDR3L SDRAM SODIMM MT18KSF2G72HZ – 16GB Features Figure 1: 204-Pin SODIMM (MO-268 R/C D1) • DDR3L functionality and operations supported as defined in the component data sheet • 204-pin, small outline dual in-line memory module (SODIMM) with ECC • Fast data transfer rates: PC3-14900, PC3-12800 • 16GB (2 Gig x 72) • VDD = 1.35V (1.283–1.45V) • VDD = 1.5V (1.425–1.575V) • Backward compatible to V DD = 1.5V ±0.075V • VDDSPD = 3.0–3.6V • Supports ECC error detection and correction • Nominal and dynamic on-die termination (ODT) for data, strobe, and mask signals • Dual-rank • On-board I2C temperature sensor with integrated serial presence-detect (SPD) EEPROM • Fixed burst chop (BC) of 4 and burst length (BL) of 8 via the mode register set (MRS) • Selectable BC4 or BL8 on-the-fly (OTF) • Gold edge contacts • Halogen-free • Fly-by topology • Terminated control, command, and address bus Module Height: 30mm (1.181in) Options Marking • Operating temperature – Commercial (0°C ≤ T A ≤ 70°C) • Package – 204-pin DIMM (halogen-free) • Frequency/CAS latency – 1.07ns @ CL = 13 (DDR3-1866) – 1.25ns @ CL = 11 (DDR3-1600) None Z -1G9 -1G6 Table 1: Key Timing Parameters Data Rate (MT/s) Speed Industry Grade Nomenclature CL = 13 CL = 11 CL = 10 CL = 9 CL = 8 CL = 7 CL = 6 tRCD tRP tRC CL = 5 (ns) (ns) (ns) -1G9 PC3-14900 1866 1600 1333 1333 1066 1066 800 667 13.125 13.125 47.125 -1G6 PC3-12800 – 1600 1333 1333 1066 1066 800 667 13.125 13.125 48.125 -1G4 PC3-10600 – – 1333 1333 1066 1066 800 667 13.125 13.125 49.125 -1G1 PC3-8500 – – – – 1066 1066 800 667 13.125 13.125 50.625 -1G0 PC3-8500 – – – – 1066 – 800 667 15 15 52.5 -80B PC3-6400 – – – – – – 800 667 15 15 52.5 PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Features Table 2: Addressing Parameter 16GB Refresh count 8K Row address 64K A[15:0] Device bank address 8 BA[2:0] Device configuration 8Gb (1 Gig x 8) Column address 2K A[11, 9:0] Module rank address 2 S#[1:0] Table 3: Part Numbers and Timing Parameters – 8GB Modules Base device: MT41K1G8,1 8Gb 1.35V DDR3L SDRAM Module Part Number2 Density Configuration Module Bandwidth Memory Clock/ Data Rate Clock Cycles (CL-tRCD-tRP) MT18KSF2G72HZ-1G9__ 16GB 2 Gig x 72 14.9 GB/s 1.07ns/1866MT/s 13-13-13 MT18KSF2G72HZ-1G6__ 16GB 2 Gig x 72 12.8 GB/s 1.25ns/1600 MT/s 11-11-11 Notes: 1. The data sheet for the base device can be found on Micron’s web site. 2. All part numbers end with a two-place code (not shown) that designates component and PCB revisions. Consult factory for current revision codes. Example: MT18KSF2G72HZ-1G9A2. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 2 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Pin Assignments Pin Assignments Table 4: Pin Assignments 204-Pin DDR3 SODIMM Front 204-Pin DDR3 SODIMM Back Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin Symbol Pin 1 VREFDQ 53 VSS 105 A1 157 DM5 2 VSS 54 DQ28 106 A2 158 Symbol VSS 3 VSS 55 DQ24 107 A0 159 DQ42 4 DQ4 56 DQ29 108 BA1 160 DQ46 5 DQ0 57 DQ25 109 VDD 161 DQ43 6 DQ5 58 VSS 110 VDD 162 DQ47 7 DQ1 59 DM3 111 CK0 163 VSS 8 VSS 60 DQS3# 112 CK1 164 VSS 9 VSS 61 VSS 113 CK0# 165 DQ48 10 DQS0# 62 DQS3 114 CK1# 166 DQ52 11 DM0 63 DQ26 115 VDD 167 DQ49 12 DQS0 64 VSS 116 VDD 168 DQ53 13 DQ2 65 DQ27 117 A10/AP 169 VSS 14 VSS 66 DQ30 118 NC 170 VSS 15 DQ3 67 VSS 119 BA0 171 DQS6# 16 DQ6 68 DQ31 120 NC 172 DM6 17 VSS 69 CB0 121 WE# 173 DQS6 18 DQ7 70 VSS 122 RAS# 174 DQ54 19 DQ8 71 CB1 123 VDD 175 VSS 20 VSS 72 CB4 124 VDD 176 DQ55 21 DQ9 73 VSS 125 CAS# 177 DQ50 22 DQ12 74 CB5 126 ODT0 178 VSS 23 VSS 75 DQS8# 127 S0# 179 DQ51 24 DQ13 76 DM8 128 ODT1 180 DQ60 25 DQS1# 77 DQS8 129 S1# 181 VSS 26 VSS 78 VSS 130 A13 182 DQ61 27 DQS1 79 VSS 131 VDD 183 DQ56 28 DM1 80 CB6 132 VDD 184 VSS 29 VSS 81 CB2 133 DQ32 185 DQ57 30 RESET# 82 CB7 134 DQ36 186 DQS7# 31 DQ10 83 CB3 135 DQ33 187 VSS 32 VSS 84 VREFCA 136 DQ37 188 DQS7 33 DQ11 85 VDD 137 VSS 189 DM7 34 DQ14 86 VDD 138 VSS 190 VSS 35 VSS 87 CKE0 139 DQS4# 191 DQ58 36 DQ15 88 A15 140 DM4 192 DQ62 37 DQ16 89 CKE1 141 DQS4 193 DQ59 38 VSS 90 A14 142 DQ38 194 DQ63 39 DQ17 91 BA2 143 VSS 195 VSS 40 DQ20 92 A9 144 DQ39 196 VSS 41 VSS 93 VDD 145 DQ34 197 SA0 42 DQ21 94 VDD 146 VSS 198 EVENT# 43 DQS2# 95 A12 147 DQ35 199 VDDSPD 44 DM2 96 A11 148 DQ44 200 SDA 45 DQS2 97 A8 149 VSS 201 SA1 46 VSS 98 A7 150 DQ45 202 SCL 47 VSS 99 A5 151 DQ40 203 VTT 48 DQ22 100 A6 152 VSS 204 VTT 49 DQ18 101 VDD 153 DQ41 – – 50 DQ23 102 VDD 154 DQS5# – – 51 DQ19 103 A3 155 VSS – – 52 VSS 104 A4 156 DQS5 – – PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Pin Descriptions Pin Descriptions The pin description table below is a comprehensive list of all possible pins for all DDR3 modules. All pins listed may not be supported on this module. See Pin Assignments for information specific to this module. Table 5: Pin Descriptions Symbol Type Description Ax Input Address inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/WRITE commands, to select one location out of the memory array in the respective bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one bank (A10 LOW, bank selected by BAx) or all banks (A10 HIGH). The address inputs also provide the op-code during a LOAD MODE command. See the Pin Assignments table for density-specific addressing information. BAx Input Bank address inputs: Define the device bank to which an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. BA define which mode register (MR0, MR1, MR2, or MR3) is loaded during the LOAD MODE command. CKx, CKx# Input Clock: Differential clock inputs. All control, command, and address input signals are sampled on the crossing of the positive edge of CK and the negative edge of CK#. CKEx Input Clock enable: Enables (registered HIGH) and disables (registered LOW) internal circuitry and clocks on the DRAM. DMx Input Data mask (x8 devices only): DM is an input mask signal for write data. Input data is masked when DM is sampled HIGH, along with that input data, during a write access. Although DM pins are input-only, DM loading is designed to match that of the DQ and DQS pins. ODTx Input On-die termination: Enables (registered HIGH) and disables (registered LOW) termination resistance internal to the DDR3 SDRAM. When enabled in normal operation, ODT is only applied to the following pins: DQ, DQS, DQS#, DM, and CB. The ODT input will be ignored if disabled via the LOAD MODE command. Par_In Input Parity input: Parity bit for Ax, RAS#, CAS#, and WE#. RAS#, CAS#, WE# Input Command inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. RESET# Input (LVCMOS) Reset: RESET# is an active LOW asychronous input that is connected to each DRAM and the registering clock driver. After RESET# goes HIGH, the DRAM must be reinitialized as though a normal power-up was executed. Sx# Input Chip select: Enables (registered LOW) and disables (registered HIGH) the command decoder. SAx Input Serial address inputs: Used to configure the temperature sensor/SPD EEPROM address range on the I2C bus. SCL Input Serial clock for temperature sensor/SPD EEPROM: Used to synchronize communication to and from the temperature sensor/SPD EEPROM on the I2C bus. CBx I/O Check bits: Used for system error detection and correction. DQx I/O Data input/output: Bidirectional data bus. DQSx, DQSx# I/O Data strobe: Differential data strobes. Output with read data; edge-aligned with read data; input with write data; center-aligned with write data. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Pin Descriptions Table 5: Pin Descriptions (Continued) Symbol Type SDA I/O Description Serial data: Used to transfer addresses and data into and out of the temperature sensor/SPD EEPROM on the I2C bus. TDQSx, TDQSx# Output Redundant data strobe (x8 devices only): TDQS is enabled/disabled via the LOAD MODE command to the extended mode register (EMR). When TDQS is enabled, DM is disabled and TDQS and TDQS# provide termination resistance; otherwise, TDQS# are no function. Err_Out# Output Parity error output: Parity error found on the command and address bus. (open drain) EVENT# Output Temperature event: The EVENT# pin is asserted by the temperature sensor when crit(open drain) ical temperature thresholds have been exceeded. VDD Supply Power supply: 1.35V (1.283–1.45V) backward-compatible to 1.5V (1.425–1.575V). The component VDD and VDDQ are connected to the module VDD. VDDSPD Supply Temperature sensor/SPD EEPROM power supply: 3.0–3.6V. VREFCA Supply Reference voltage: Control, command, and address VDD/2. VREFDQ Supply Reference voltage: DQ, DM VDD/2. VSS Supply Ground. VTT Supply Termination voltage: Used for control, command, and address VDD/2. NC – No connect: These pins are not connected on the module. NF – No function: These pins are connected within the module, but provide no functionality. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 5 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM DQ Map DQ Map Table 6: Component-to-Module DQ Map, Front Component Reference Number Component DQ U1 U3 U5 U7 PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 2 13 U2 0 23 50 1 0 5 1 21 42 2 3 15 2 19 51 3 5 6 3 20 40 4 7 18 4 22 48 5 4 4 5 16 37 6 6 16 6 18 49 7 1 7 7 17 39 0 CB2 81 0 42 159 1 CB1 71 1 45 150 2 CB3 83 2 46 160 3 CB4 72 3 40 151 4 CB6 80 4 43 161 5 CB0 69 5 44 148 6 CB7 82 6 47 162 7 CB5 74 7 41 153 0 59 193 0 14 34 1 57 185 1 9 21 2 62 192 2 11 33 3 56 183 3 8 19 4 58 191 4 10 31 5 61 182 5 13 24 6 63 194 6 15 36 7 60 180 7 12 22 0 29 56 0 38 142 1 26 63 1 33 135 2 28 54 2 35 147 3 31 68 3 37 136 4 25 57 4 39 144 5 27 65 5 32 133 6 24 55 6 34 145 7 30 66 7 36 134 U4 U6 U8 6 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM DQ Map Table 6: Component-to-Module DQ Map, Front (Continued) Component Reference Number Component DQ Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number U9 0 55 176 U10 0 57 185 1 53 168 1 59 193 2 54 174 2 56 183 3 52 166 3 62 192 4 51 179 4 60 180 5 48 165 5 63 194 6 50 177 6 61 182 7 49 167 7 58 191 Table 7: Component-to-Module DQ Map, Back Component Reference Number Component DQ U11 U13 PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 45 150 U12 0 CB1 71 1 42 159 1 CB2 81 2 40 151 2 CB4 72 3 46 160 3 CB3 83 4 41 153 4 CB5 74 5 47 162 5 CB7 82 6 44 148 6 CB0 69 7 43 161 7 CB6 80 0 21 42 0 0 5 1 23 50 1 2 13 2 20 40 2 5 6 3 19 51 3 3 15 4 17 39 4 1 7 5 18 49 5 6 16 6 16 37 6 4 4 7 22 48 7 7 18 U14 7 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM DQ Map Table 7: Component-to-Module DQ Map, Back (Continued) Component Reference Number Component DQ U16 U18 PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN Module DQ Module Pin Number Component Reference Number Component DQ Module DQ Module Pin Number 0 53 168 U17 0 33 135 1 55 176 1 38 142 2 52 166 2 37 136 3 54 174 3 35 147 4 49 167 4 36 134 5 50 177 5 34 145 6 48 165 6 32 133 7 51 179 7 39 144 0 26 63 0 9 21 1 29 56 1 14 34 2 31 68 2 8 19 3 28 54 3 11 33 4 30 66 4 12 22 5 24 55 5 15 36 6 27 65 6 13 24 7 25 57 7 10 31 U19 8 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Functional Block Diagram Functional Block Diagram Figure 2: Functional Block Diagram S1# S0# DQS0 DQS0# DM0 DQS4 DQS4# DM4 DM CS# DQS DQS# DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 Vss DQ DQ DQ DQ DQ DQ DQ DQ ZQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U1 DM CS# DQS DQS# DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 U14 Vss ZQ DQS1 DQS1# DM1 DM CS# DQS DQS# Vss DQ DQ DQ DQ DQ DQ DQ DQ ZQ U6 DM CS# DQS DQS# U19 Vss ZQ DM CS# DQS DQS# Vss DQ DQ DQ DQ DQ DQ DQ DQ ZQ U2 DM CS# DQS DQS# U13 Vss ZQ DM CS# DQS DQS# Vss DQ DQ DQ DQ DQ DQ DQ DQ ZQ U7 DM CS# DQS DQS# Vss ZQ DM CS# DQS DQS# Vss U10 U5 ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ Vss Rank 0: U1–U4, U6, U7, U10, U16, U17 Rank 1: U5, U8, U9, U11–U14, U18, U19 DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ U3 U12 U15 Temperature sensor/ SPD EEPROM SCL EVT A0 EVENT# ZQ BA[2:0]: DDR3 SDRAM A[15:0]: DDR3 SDRAM RAS#: DDR3 SDRAM CAS#: DDR3 SDRAM WE#: DDR3 SDRAM CKE0: Rank 0 CKE1: Rank 1 ODT0: Rank 0 ODT1: Rank 1 RESET#: DDR3 SDRAM Note: Vddspd Vdd Vtt CK0 CK0# Rank 0 CK1 CK1# Rank 1 SDA A1 A2 SA0 SA1 Vss PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ Vss CB0 CB1 CB2 CB3 CB4 CB5 CB6 CB7 BA[2:0] A[15:0] RAS# CAS# WE# CKE0 CKE1 ODT0 ODT1 RESET# U9 ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 U18 DQS8 DQS8# DM8 U16 Vss DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQS7 DQS7# DM7 Vss DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 U11 ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS3 DQS3# DM3 U4 Vss DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQS6 DQS6# DM6 Vss DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 U8 ZQ DQ DQ DQ DQ DQ DQ DQ DQ ZQ DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS2 DQS2# DM2 U17 Vss DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DM CS# DQS DQS# DQ DQ DQ DQ DQ DQ DQ DQ DQS5 DQS5# DM5 Vss DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQ DQ DQ DQ DQ DQ DQ DQ ZQ Vss Temperature sensor/ SPD EEPROM Clock, control, command, and address line terminations: DDR3 SDRAM CKE[1:0], A[15:0], RAS#, CAS#, WE#, ODT[1:0], BA[2:0], S#[1:0] Control, command, and address termination Vref CA DDR3 SDRAM Vref DQ DDR3 SDRAM Vss DDR3 SDRAM CK CK# DDR3 SDRAM VTT DDR3 SDRAM VDD 1. The ZQ ball on each DDR3 component is connected to an external 240Ω ±1% resistor that is tied to ground. It is used for the calibration of the component’s ODT and output driver. 9 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM General Description General Description DDR3 SDRAM modules are high-speed, CMOS dynamic random access memory modules that use internally configured 8-bank DDR3 SDRAM devices. DDR3 SDRAM modules use DDR architecture to achieve high-speed operation. DDR3 architecture is essentially an 8n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR3 SDRAM module effectively consists of a single 8n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and eight corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins. DDR3 modules use two sets of differential signals: DQS, DQS# to capture data and CK and CK# to capture commands, addresses, and control signals. Differential clocks and data strobes ensure exceptional noise immunity for these signals and provide precise crossing points to capture input signals. Fly-By Topology DDR3 modules use faster clock speeds than earlier DDR technologies, making signal quality more important than ever. For improved signal quality, the clock, control, command, and address buses have been routed in a fly-by topology, where each clock, control, command, and address pin on each DRAM is connected to a single trace and terminated (rather than a tree structure, where the termination is off the module near the connector). Inherent to fly-by topology, the timing skew between the clock and DQS signals can be easily accounted for by using the write-leveling feature of DDR3. Temperature Sensor with Serial Presence-Detect EEPROM Thermal Sensor Operations The temperature from the integrated thermal sensor is monitored and converts into a digital word via the I2C bus. System designers can use the user-programmable registers to create a custom temperature-sensing solution based on system requirements. Programming and configuration details comply with JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect EEPROM Operation DDR3 SDRAM modules incorporate serial presence-detect. The SPD data is stored in a 256-byte EEPROM. The first 128 bytes are programmed by Micron to comply with JEDEC standard JC-45, "Appendix X: Serial Presence Detect (SPD) for DDR3 SDRAM Modules." These bytes identify module-specific timing parameters, configuration information, and physical attributes. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device occur via a standard I2C bus using the DIMM’s SCL (clock) SDA (data), and SA (address) pins. Write protect (WP) is connected to V SS, permanently disabling hardware write protection. For further information refer to Micron technical note TN-04-42, "Memory Module Serial Presence-Detect." PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Electrical Specifications Electrical Specifications Stresses greater than those listed may cause permanent damage to the module. This is a stress rating only, and functional operation of the module at these or any other conditions outside those indicated in each device's data sheet is not implied. Exposure to absolute maximum rating conditions for extended periods may adversely affect reliability. Table 8: Absolute Maximum Ratings Symbol Parameter Min Max Units VDD VDD supply voltage relative to VSS –0.4 1.975 V VIN, VOUT Voltage on any pin relative to VSS –0.4 1.975 V Table 9: Operating Conditions Symbol VDD Parameter Min Nom Max Units Notes VDD supply voltage 1.283 1.35 1.45 V 1.425 1.5 1.575 V VREFCA(DC) Input reference voltage command/address bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V VREFDQ(DC) I/O reference voltage DQ bus 0.49 × VDD 0.5 × VDD 0.51 × VDD V –600 – 600 mA 0.49 × VDD 20mV 0.5 × VDD 0.51 × VDD + 20mV V Address inputs, RAS#, CAS#, WE#, BA –36 0 36 µA S#, CKE, ODT, CK, CK# –18 0 18 DM –4 0 4 DQ, DQS, DQS#, CB –10 0 10 µA –18 0 18 µA IVTT Termination reference current from VTT VTT Termination reference voltage (DC) – command/ address bus II IOZ IVREF Input leakage current; Any input 0V ≤ VIN ≤ VDD; VREF input 0V ≤ VIN ≤ 0.95V (All other pins not under test = 0V) Output leakage current; 0V ≤ VOUT ≤ VDD; DQ and ODT are disabled; ODT is HIGH VREF supply leakage current; VREFDQ = VDD/2 or VREFCA = VDD/2 (All other pins not under test = 0V) 1 2 TA Module ambient operating temperature 0 – 70 °C 3, 4 TC DDR3 SDRAM component case operating temperature 0 – 95 °C 3, 4, 5 Notes: PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 1. Module is backward-compatible with 1.5V operation. Refer to device specification for details and operation guidance. 2. VTT termination voltage in excess of the stated limit will adversely affect the command and address signals’ voltage margin and will reduce timing margins. 3. TA and TC are simultaneous requirements. 4. For further information, refer to technical note TN-00-08: “Thermal Applications,” available on Micron’s web site. 5. The refresh rate is required to double when 85°C < TC ≤ 95°C. 11 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM DRAM Operating Conditions DRAM Operating Conditions Recommended AC operating conditions are given in the DDR3 component data sheets. Component specifications are available at micron.com. Module speed grades correlate with component speed grades, as shown below. Table 10: Module and Component Speed Grades DDR3 components may exceed the listed module speed grades; module may not be available in all listed speed grades Module Speed Grade Component Speed Grade -2G1 -093 -1G9 -107 -1G6 -125 -1G4 -15E -1G1 -187E -1G0 -187 -80C -25E -80B -25 Design Considerations Simulations Micron memory modules are designed to optimize signal integrity through carefully designed terminations, controlled board impedances, routing topologies, trace length matching, and decoupling. However, good signal integrity starts at the system level. Micron encourages designers to simulate the signal characteristics of the system's memory bus to ensure adequate signal integrity of the entire memory system. Power Operating voltages are specified at the DRAM, not at the edge connector of the module. Designers must account for any system voltage drops at anticipated power levels to ensure the required supply voltage is maintained. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 12 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM IDD Specifications IDD Specifications Table 11: DDR3 IDD Specifications and Conditions – 16GB (Die Revision A) Values are for the MT41K1G8 DDR3L SDRAM only and are computed from values specified in the 8Gb 1.35V (1 Gig x 8) component data sheet Parameter Symbol 1866 1600 Units Operating current 0: One bank ACTIVATE-to-PRECHARGE Operating current 1: One bank ACTIVATE-to-READ-to-PRECHARGE IDD01 720 702 mA 1 828 801 mA 198 198 mA IDD1 2 Precharge power-down current: Slow exit IDD2P0 Precharge power-down current: Fast exit IDD2P1 2 288 252 mA Precharge quiet standby current IDD2Q2 648 612 mA 2 684 648 mA 1 477 459 mA Precharge standby current IDD2N Precharge standby ODT current IDD2NT Active power-down current IDD3P 2 684 648 mA Active standby current IDD3N2 954 918 mA Burst read operating current IDD4R1 1314 1224 mA 1 1314 1224 mA 1 Burst write operating current IDD4W Refresh current IDD5B 2349 2304 mA Self refresh temperature current: MAX TC = 85°C IDD62 432 432 mA Self refresh temperature current (SRT-enabled): MAX TC = 95°C All banks interleaved read current IDD6ET 612 612 mA 1 1899 1809 mA 2 234 234 mA IDD7 Reset current IDD8 Notes: PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 2 1. One module rank in the active IDD, the other rank in IDD2P0. 2. All ranks in this IDD condition. 13 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Temperature Sensor with Serial Presence-Detect EEPROM Temperature Sensor with Serial Presence-Detect EEPROM The temperature sensor continuously monitors the module's temperature and can be read back at any time over the I2C bus shared with the SPD EEPROM. Refer to JEDEC standard No. 21-C page 4.7-1, "Definition of the TSE2002av, Serial Presence Detect with Temperature Sensor." Serial Presence-Detect For the latest SPD data, refer to Micron's SPD page: micron.com/SPD. Table 12: Temperature Sensor with SPD EEPROM Operating Conditions Parameter/Condition Symbol Min Max Units VDDSPD 3.0 3.6 V Supply current: VDD = 3.3V IDD – 2.0 mA Input high voltage: Logic 1; SCL, SDA VIH VDDSPD x 0.7 VDDSPD + 1 V Input low voltage: Logic 0; SCL, SDA VIL –0.5 VDDSPD x 0.3 V Output low voltage: IOUT = 2.1mA VOL – 0.4 V Input current IIN –5.0 5.0 µA Temperature sensing range – –40 125 °C Temperature sensor accuracy (class B) – –1.0 1.0 °C Supply voltage Table 13: Temperature Sensor and SPD EEPROM Serial Interface Timing Parameter/Condition Symbol Min Max Units tBUF 4.7 – µs SDA fall time tF 20 300 ns SDA rise time tR – 1000 ns tHD:DAT 200 900 ns Time bus must be free before a new transition can start Data hold time Start condition hold time tH:STA 4.0 – µs Clock HIGH period tHIGH 4.0 50 µs Clock LOW period tLOW 4.7 – µs tSCL 10 100 kHz Data setup time tSU:DAT 250 – ns Start condition setup time tSU:STA 4.7 – µs Stop condition setup time tSU:STO 4.0 – µs SCL clock frequency PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Temperature Sensor with Serial Presence-Detect EEPROM EVENT# Pin The temperature sensor also adds the EVENT# pin (open-drain). Not used by the SPD EEPROM, EVENT# is a temperature sensor output used to flag critical events that can be set up in the sensor’s configuration register. EVENT# has three defined modes of operation: interrupt mode, compare mode, and critical temperature mode. Event thresholds are programmed in the 0x01 register using a hysteresis. The alarm window provides a comparison window, with upper and lower limits set in the alarm upper boundary register and the alarm lower boundary register, respectively. When the alarm window is enabled, EVENT# will trigger whenever the temperature is outside the MIN or MAX values set by the user. The interrupt mode enables software to reset EVENT# after a critical temperature threshold has been detected. Threshold points are set in the configuration register by the user. This mode triggers the critical temperature limit and both the MIN and MAX of the temperature window. The compare mode is similar to the interrupt mode, except EVENT# cannot be reset by the user and returns to the logic HIGH state only when the temperature falls below the programmed thresholds. Critical temperature mode triggers EVENT# only when the temperature has exceeded the programmed critical trip point. When the critical trip point has been reached, the temperature sensor goes into comparator mode, and the critical EVENT# cannot be cleared through software. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 15 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved. 16GB (x72, ECC, DR) 204-Pin DDR3L SODIMM Module Dimensions Module Dimensions Figure 3: 204-Pin DDR3 SODIMM Front view 3.8 (0.150) MAX 67.75 (2.667) 67.45 (2.656) 2.0 (0.079) R (2X) U1 1.8 (0.071) (2X) U2 U6 U3 U5 U4 U7 U9 U8 30.15 (1.187) 29.85 (1.175) 20.0 (0.787) TYP 6.0 (0.236) TYP 1.0 (0.039) TYP 2.0 (0.079) TYP Pin 1 0.45 (0.018) TYP Pin 203 63.6 (2.504) TYP 45° 4X 1.10 (0.043) 0.90 (0.035) 0.6 (0.024) TYP Back view U10 U16 U11 U17 U14 U13 U12 U19 U18 U15 4.0 (0.157) TYP 2.55 (0.10) TYP 3.0 (0.12) TYP Pin 204 39.0 (1.535) TYP Pin 2 21.0 (0.827) TYP 24.8 (0.976) TYP Notes: 1. All dimensions are in millimeters (inches); MAX/MIN or typical (TYP) where noted. 2. The dimensional diagram is for reference only. 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-4000 www.micron.com/products/support Sales inquiries: 800-932-4992 Micron and the Micron logo are trademarks of Micron Technology, Inc. All other trademarks are the property of their respective owners. This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. PDF: 09005aef861a851f ksf18c2gx72hz.pdf – Rev. B 4/15 EN 16 Micron Technology, Inc. reserves the right to change products or specifications without notice. © 2015 Micron Technology, Inc. All rights reserved.