MT18VDDF12872DY-40BF1

512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM DDR SDRAM REGISTERED DIMM MT18VDDF6472 – 512MB MT18VDDF12872 – 1GB For the latest data sheet, please refer to the Micron Web site: www.micron.com/products/modules Features Figure 1: 184-Pin DIMM (MO-206) • 184-pin, dual in-line memory module (DIMM) • Fast data transfer rates: PC1600, PC2100, or PC2700 • Utilizes 200 MT/s, 266 MT/s, and 333 MT/s DDR SDRAM components • Registered inputs with one-clock delay • Phase-lock loop (PLL) clock driver to reduce loading • Supports ECC error detection and correction • 512MB (64 Meg x 72) and 1GB (128 Meg x 72) • VDD = VDDQ = +2.5V • VDDSPD = +2.3V to +3.6V • 2.5V I/O (SSTL_2 compatible) • Commands entered on each positive CK edge • DQS edge-aligned with data for READs; centeraligned with data for WRITEs • Internal, pipelined double data rate (DDR) architecture; two data accesses per clock cycle • Bidirectional data strobe (DQS) transmitted/received with data—i.e., source-synchronous data capture • Differential clock inputs CK and CK# • Four internal device banks for concurrent operation • Programmable burst lengths: 2, 4, or 8 • Auto precharge option • Auto Refresh and Self Refresh modes • 7.8125µs maximum average periodic refresh interval • Serial Presence Detect (SPD) with EEPROM • Programmable READ CAS latency • Gold edge contacts Standard PCB 1.125in. (28.58mm) Alternate PCB 1.125in. (28.58mm) Very Low Profile 0.72in. (18.29mm) OPTIONS NOTE: Table 1: MARKING • Operating Temperature Range Commercial (0°C ≤ TA ≤ +70°C) • Package 184-pin DIMM (standard) 184-pin DIMM (lead-free)1 • Memory Clock, Speed, CAS Latency2 6ns (166MHz), 333 MT/s, CL = 2.5 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2 7.5ns (133 MHz), 266 MT/s, CL = 2.5 10ns (100 MHz), 200 MT/s, CL = 2 • PCB Low-Profile 1.125in. (28.58mm) Very Low Profile 0.72in. (18.29mm) none G Y -335 -2621 -26A1 -265 -2021 See page 2 note 1. Contact Micron for availability of products. 2. CL = CAS latency. Registered Mode will add one clock cycle to CL. Address Table 512MB 8K 8K (A0–A12) 4 (BA0, BA1) 256Mb (64 Meg x 4) 2K (A0–A9, A11) 1 (S0#) Refresh Count Row Addressing Device Bank Addressing Device Configuration Column Addressing Module Rank Addressing pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 1 1GB 8K 8K (A0–A12) 4 (BA0, BA1) 512Mb (128 Meg x 4) 4K (A0–A9, A11, A12) 1 (S0#) ©2004 Micron Technology, Inc. All rights reserved. PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 2: Part Numbers and Timing Parameters PART NUMBER MT18VDDF6472G-335__ MT18VDDF6472Y-335__ MT18VDDF6472G-262__ MT18VDDF6472Y-262__ MT18VDDF6472G-26A__ MT18VDDF6472Y-26A__ MT18VDDF6472G-265__ MT18VDDF6472Y-265__ MT18VDDF6472G-202__ MT18VDDF6472Y-202__ MT18VDDF12872G-335__ MT18VDDF12872Y-335__ MT18VDDF12872G-262__ MT18VDDF12872Y-262__ MT18VDDF12872G-26A__ MT18VDDF12872Y-26A__ MT18VDDF12872G-265__ MT18VDDF12872Y-265__ MT18VDDF12872G-202__ MT18VDDF12872Y-202__ MODULE DENSITY CONFIGURATION MODULE BANDWIDTH MEMORY CLOCK/ DATA RATE LATENCY (CL - tRCD - tRP) 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 512MB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 1GB 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 64 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 128 Meg x 72 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 2.7 GB/s 2.7 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 2.1 GB/s 1.6 GB/s 1.6 GB/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 6ns/333 MT/s 6ns/333 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 7.5ns/266 MT/s 10ns/200 MT/s 10ns/200 MT/s 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2.5-3-3 2.5-3-3 2-2-2 2-2-2 2-3-3 2-3-3 2.5-3-3 2.5-3-3 2-2-2 2-2-2 NOTE: All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for current revision codes. Example: MT18VDDF6472G-265B1. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 2 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 3: Table 4: Pin Assignment (184-Pin DIMM Front) Pin Assignment (184-Pin DIMM Back) PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 VREF DQ0 VSS DQ1 DQS0 DQ2 VDD DQ3 NC RESET# VSS DQ8 DQ9 DQS1 VDDQ NC NC VSS DQ10 DQ11 CKE0 VDDQ DQ16 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 DQ17 DQS2 VSS A9 DQ18 A7 VDDQ DQ19 A5 DQ24 VSS DQ25 DQS3 A4 VDD DQ26 DQ27 A2 VSS A1 CB0 CB1 VDD 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 DQS8 A0 CB2 VSS CB3 BA1 DQ32 VDDQ DQ33 DQS4 DQ34 VSS BA0 DQ35 DQ40 VDDQ WE# DQ41 CAS# VSS DQS5 DQ42 DQ43 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 VDD NC DQ48 DQ49 VSS NC NC VDDQ DQS6 DQ50 DQ51 VSS NC DQ56 DQ57 VDD DQS7 DQ58 DQ59 VSS NC SDA SCL VSS DQ4 DQ5 VDDQ DQS9 DQ6 DQ7 VSS NC NC NC VDDQ DQ12 DQ13 DQS10 VDD DQ14 DQ15 NC VDDQ NC DQ20 A12 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 VSS DQ21 A11 DQS11 VDD DQ22 A8 DQ23 VSS A6 DQ28 DQ29 VDDQ DQS12 A3 DQ30 VSS DQ31 CB4 CB5 VDDQ CK0 CK0# 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 VSS DQS17 A10 CB6 VDDQ CB7 VSS DQ36 DQ37 VDD DQS13 DQ38 DQ39 VSS DQ44 RAS# DQ45 VDDQ S0# NC DQS14 VSS DQ46 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 DQ47 NC VDDQ DQ52 DQ53 NC VDD DQS15 DQ54 DQ55 VDDQ NC DQ60 DQ61 VSS DQS16 DQ62 DQ63 VDDQ SA0 SA1 SA2 VDDSPD Figure 2: Pin Locations Low-Profile 1.125in. (28.58mm) Back View Front View U17 U6 U1 U2 U3 U4 U5 U8 U9 U10 U11 U12 U13 U14 U15 U18 U7 PIN 1 U19 U20 U21 U22 U16 PIN 92 PIN 53 PIN 52 PIN 184 PIN 93 PIN 144 PIN 145 Back View Front View U12 U6 U1 U2 U3 U4 U19 U8 U5 U9 U10 U11 U15 U16 U17 U18 U20 U21 U22 U23 U24 U7 PIN 52 PIN 1 PIN 92 PIN 53 PIN 145 PIN 184 PIN 93 PIN 144 Very Low-Profile 0.72in. (18.29mm) Front View U1 Back View U2 U3 U4 U5 U8 U6 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 U7 PIN 1 PIN 52 PIN 53 PIN 92 PIN 184 Indicates a VDD pin pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN PIN 145 PIN 144 PIN 93 Indicates a VSS pin 3 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. PIN NUMBERS SYMBOL TYPE 10 RESET# Input 63, 65, 154 WE#, CAS#, RAS# 137, 138 CK0, CK0# 21 CKE0 157 S0# 52, 59 BA0, BA1 27, 29, 32, 37, 41, 43, 48, 115, 118, 122, 125, 130, 141 A0–A12 5, 14, 25, 36, 47, 56, 67, 78, 86, 97, 107, 119, 129, 140, 149, 159, 169, 177 44, 45, 49, 51, 134, 135, 142, 144 DQS0–DQS17 pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN CB0–CB7 DESCRIPTION Asynchronously forces all registered ouputs LOW when RESET# is LOW. This signal can be used during power-up to ensure CKE is LOW and DQs are High-Z. Input Command Inputs: RAS#, CAS#, and WE# (along with S#) define the command being entered. Input Clock: CK, CK# are differential clock inputs. All address and control input signals are sampled on the crossing of the positive edge of CK,and negative edge of CK#. Output data (DQ and DQS) is referenced to the crossings of CK and CK#. Input Clock Enable: CKE HIGH activates and CKE LOW deactivates the internal clock, input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER-DOWN and SELF REFRESH operations (all device banks idle), or ACTIVE POWER-DOWN (row ACTIVE in any device bank). CKE is synchronous for POWER-DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous for SELF REFRESH exit and for disabling the outputs. CKE must be maintained HIGH throughout read and write accesses. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CK, CK# and CKE) are disabled during POWER-DOWN. Input buffers (excluding CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input but will detect an LVCMOS LOW level after VDD is applied and until CKE is first brought HIGH. After CKE is brought HIGH, it becomes an SSTL_2 input only. Input Chip Selects: S# enables (registered LOW) and disables (registered HIGH) the command decoder. All commands are masked when S# is registered HIGH. S# is considered part of the command code. Input Bank Address: BA0 and BA1 define to which device bank an ACTIVE, READ, WRITE, or PRECHARGE command is being applied. Input Address Inputs: Provide the row address for ACTIVE commands, and the column address and auto precharge bit (A10) for READ/ WRITE commands, to select one location out of the memory array in the respective device bank. A10 sampled during a PRECHARGE command determines whether the PRECHARGE applies to one device bank (A10 LOW, device bank selected by BA0, BA1) or all device banks (A10 HIGH). The address inputs also provide the op-code during a MODE REGISTER SET command. BA0 and BA1 define which mode register (mode register or extended mode register) is loaded during the LOAD MODE REGISTER command. Input/ Data Strobe: Output with READ data, input with WRITE data. Output DQS is edge-aligned with READ data, centered in WRITE data. Used to capture data. Input/ Check Bits. Output 4 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 5: Pin Descriptions Pin numbers may not correlate with symbols. Refer to Pin Assignment Tables for pin number and symbol information. PIN NUMBERS SYMBOL 2, 4, 6, 8, 12,13, 19, 20, 23, 24, 28, 31, 33, 35, 39, 40, 53, 55, 57, 60, 61, 64, 68, 69, 72, 73, 79, 80, 83, 84, 87, 88, 94, 95, 98, 99, 105, 106, 109, 110, 114, 117, 121, 123, 126, 127, 131, 133, 146, 147, 150, 151, 153, 155, 161, 162, 165, 166, 170, 171, 174, 175, 178, 179 92 DQ0–DQ63 181, 182, 183 SA0–SA2 91 SDA 1 15, 22, 30, 54, 62, 77, 96, 104, 112, 128, 136, 143, 156, 164, 172, 180 7, 38, 46, 70, 85, 108, 120, 148, 168 3, 11, 18, 26, 34, 42, 50, 58, 66, 74, 81, 89, 93, 100, 116, 124, 132, 139, 145, 152, 160, 176 184 9, 16, 17, 71, 75, 76, 82, 90, 101, 102, 103, 111, 113,158, 163, 167, 173 VREF VDDQ pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN SCL TYPE DESCRIPTION Input/ Data I/Os: Data bus. Output Input Serial Clock for Presence-Detect: SCL is used to synchronize the presence-detect data transfer to and from the module. Input Presence-Detect Address Inputs: These pins are used to configure the presence-detect device. Input/ Serial Presence-Detect Data: SDA is a bidirectional pin used to Output transfer addresses and data into and out of the presence-detect portion of the module. Supply SSTL_2 reference voltage. Supply DQ Power Supply: +2.5V ±0.2V. VDD Supply Power Supply: +2.5V ±0.2V. VSS Supply Ground. VDDSPD NC Supply Serial EEPROM positive power supply: +2.3V to +3.6V. — No Connect: These pins should be left unconnected. 5 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 3: Functional Block Diagram – Standard Low-Profile PCB VSS RS0# DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQS CS# DM DQ U1 DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQS CS# DM DQ U2 DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQS CS# DM DQ U3 DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQS CS# DM DQ U4 DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQS CS# DM DQ U8 DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQS CS# DM DQ U9 DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQS CS# DM DQ DQ U10 DQ DQ DQ56 DQ57 DQ58 DQ59 DQS CS# DM DQ DQ U11 DQ DQ DQS1 DQ4 DQ5 DQ6 DQ7 DQS CS# DM DQ DQ U22 DQ DQ DQ12 DQ13 DQ14 DQ15 DQS CS# DM DQ DQ U21 DQ DQ DQ20 DQ21 DQ22 DQ23 DQS CS# DM DQ DQ U20 DQ DQ DQ28 DQ29 DQ30 DQ31 DQS CS# DM DQ DQ U19 DQ DQ DQ36 DQ37 DQ38 DQ39 DQS CS# DM DQ DQ U15 DQ DQ DQ44 DQ45 DQ46 DQ47 DQS CS# DM DQ DQ U14 DQ DQ DQ52 DQ53 DQ54 DQ55 DQS CS# DM DQ DQ U13 DQ DQ DQ60 DQ61 DQ62 DQ63 DQS CS# DM DQ DQ U12 DQ DQ CB4 CB5 CB6 CB7 DQS CS# DM DQ DQ U18 DQ DQ DQS10 DQS2 DQS11 DQS3 DQS12 DQS4 DQS13 DQS5 DQS14 DQS6 DQS15 DQS7 DQS16 DQS8 DQS17 DQS CS# DM DQ U5 DQ DQ DQ CB0 CB1 CB2 CB3 U7, U16 PLL 120Ω S0?# BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# CK CK# R E G I S T E R S CK0 CK0# RS0#: DDR SDRAMs RBA0, RBA1: DDR SDRAMs VDD RA0-RA12: DDR SDRAMs RRAS#: DDR SDRAMs RCAS#: DDR SDRAMs RCKE0: DDR SDRAMs SERIAL PD RWE#: DDR SDRAMs SCL WP VDD RESET# U17 A0 A1 A2 SA0 SA1 SA2 NOTE: SDA VDDSPD VDDQ VDD VREF VSS SPD/EEPROM DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS Standard modules use the following DDR SDRAM devices: MT46V64M4FG (512MB); MT46V128M4FG (1GB) 1. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN U6 1KΩ DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 REGISTER X 2 Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) 6 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 4: Functional Block Diagram – Alternate Low-Profile PCB VSS RS0# DQS9 DQS0 DQ0 DQ1 DQ2 DQ3 DQS CS# DM DQ U1 DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQS CS# DM DQ U2 DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQS CS# DM DQ U3 DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQS CS# DM DQ U4 DQ DQ DQ DQS1 DQ4 DQ5 DQ6 DQ7 DQS CS# DM DQ DQ U24 DQ DQ DQ12 DQ13 DQ14 DQ15 DQS CS# DM DQ DQ U23 DQ DQ DQ20 DQ21 DQ22 DQ23 DQS CS# DM DQ DQ U22 DQ DQ DQ28 DQ29 DQ30 DQ31 DQS CS# DM DQ DQ U21 DQ DQ DQ36 DQ37 DQ38 DQ39 DQS CS# DM DQ DQ U18 DQ DQ DQ44 DQ45 DQ46 DQ47 DQS CS# DM DQ DQ U17 DQ DQ DQ52 DQ53 DQ54 DQ55 DQS CS# DM DQ DQ U16 DQ DQ DQ60 DQ61 DQ62 DQ63 DQS CS# DM DQ DQ U15 DQ DQ CB4 CB5 CB6 CB7 DQS CS# DM DQ DQ U20 DQ DQ DQS10 DQS2 DQS11 DQS3 DQS12 DQS4 DQS13 DQ32 DQ33 DQ34 DQ35 DQS CS# DM DQ U8 DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQS CS# DM DQ U9 DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQS CS# DM DQ DQ U10 DQ DQ DQ56 DQ57 DQ58 DQ59 DQS CS# DM DQ DQ U11 DQ DQ CB0 CB1 CB2 CB3 DQS CS# DM DQ U5 DQ DQ DQ DQS5 DQS14 DQS6 DQS15 DQS7 DQS16 DQS8 DQS17 U6, U19 PLL 120Ω S0?# BA0, BA1 A0-A12 RAS# CAS# CKE0 WE# CK CK# R E G I S T E R S CK0 CK0# RS0#: DDR SDRAMs VDD RA0-RA12: DDR SDRAMs RRAS#: DDR SDRAMs RCAS#: DDR SDRAMs RCKE0: DDR SDRAMs SERIAL PD RWE#: DDR SDRAMs SCL WP VDD RESET# U12 A0 A1 A2 SA0 SA1 SA2 NOTE: SDA VDDSPD VDDQ VDD VREF VSS SPD/EEPROM DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS Standard modules use the following DDR SDRAM devices: MT46V64M4FG (512MB); MT46V128M4FG (1GB) 1. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN U7 1KΩ RBA0, RBA1: DDR SDRAMs DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 DDR SDRAM X 2 REGISTER X 2 Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) 7 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 5: Functional Block Diagram – Very Low-Profile PCB VSS RS0# DQS0 DQS9 DQ0 DQ1 DQ2 DQ3 DQS CS# DM DQ U1 DQ DQ DQ DQ8 DQ9 DQ10 DQ11 DQS CS# DM DQ U2 DQ DQ DQ DQ16 DQ17 DQ18 DQ19 DQS CS# DM DQ U3 DQ DQ DQ DQ24 DQ25 DQ26 DQ27 DQS CS# DM DQ U4 DQ DQ DQ DQ32 DQ33 DQ34 DQ35 DQS CS# DM DQ U8 DQ DQ DQ DQ40 DQ41 DQ42 DQ43 DQS CS# DM DQ U9 DQ DQ DQ DQ48 DQ49 DQ50 DQ51 DQS CS# DM DQ DQ U10 DQ DQ DQ56 DQ57 DQ58 DQ59 DQS CS# DM DQ DQ U11 DQ DQ CB0 CB1 CB2 CB3 DQS CS# DM DQ U5 DQ DQ DQ DQ4 DQ5 DQ6 DQ7 DQS CS# DM DQ DQ U22 DQ DQ DQ12 DQ13 DQ14 DQ15 DQS CS# DM DQ DQ U21 DQ DQ DQ20 DQ21 DQ22 DQ23 DQS CS# DM DQ DQ U20 DQ DQ DQ28 DQ29 DQ30 DQ31 DQS CS# DM DQ DQ U19 DQ DQ DQ36 DQ37 DQ38 DQ39 DQS CS# DM DQ DQ U15 DQ DQ DQ44 DQ45 DQ46 DQ47 DQS CS# DM DQ DQ U14 DQ DQ DQ52 DQ53 DQ54 DQ55 DQS CS# DM DQ DQ U13 DQ DQ DQ60 DQ61 DQ62 DQ63 DQS CS# DM DQ DQ U12 DQ DQ CB4 CB5 CB6 CB7 DQS CS# DM DQ DQ U18 DQ DQ DQS10 DQS1 DQS2 DQS11 DQS12 DQS3 DQS13 DQS4 DQS14 DQS5 DQS6 DQS15 DQS16 DQS7 DQS8 DQS17 U6, U17 PLL 120 R E G I S T E R S RAS# CAS# CKE0 WE# A0-A12 BA0, BA1 S0# CK# CK CK0 CK0# RRAS#: DDR SDRAMs RCAS#: DDR SDRAMs VDD RCKE0: DDR SDRAMs RWE#: DDR SDRAMs 2 2 2 2 2 2 2 2 2 RA0-RA12: DDR SDRAMs RBA0, RBA1: DDR SDRAMs RS0#: DDR SDRAMs SERIAL PD U7 SCL WP VDD A0 RESET# A1 A2 SDA VDDSPD VDDQ VDD VREF VSS SPD/EEPROM DDR SDRAMS DDR SDRAMS DDR SDRAMS DDR SDRAMS SA0 SA1 SA2 NOTE: Standard modules use the following DDR SDRAM devices MT46V64M4FG (512MB); MT46V128M4FG (1GB) 1. All resistor values are 22Ω unless otherwise specified. 2. Per industry standard, Micron utilizes various component speed grades as referenced in the Module Part Numbering Guide at www.micron.com/numberguide. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN U16 1K DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X DDR SDRAM X REGISTER X 2 Lead-free modules use the following DDR SDRAM devices: MT46V64M4BG (512MB); MT46V128M4BG (1GB) 8 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM General Description An auto refresh mode is provided, along with a power-saving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All outputs are SSTL_2, Class II compatible. For more information regarding DDR SDRAM operation, refer to the 256Mb or 512Mb DDR SDRAM component data sheets. The MT18VDDF6472 and MT18VDDF12872 are high-speed CMOS, dynamic random-access, 512MB and 1GB memory modules organized in x72 (ECC) configuration. DDR SDRAM modules use internally configured quad-bank DDR SDRAM devices. DDR SDRAM modules use a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the DDR SDRAM module effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is an intermittent strobe transmitted by the DDR SDRAM device during READs and by the memory controller during WRITEs. DQS is edgealigned with data for READs and center-aligned with data for WRITEs. DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to DDR SDRAM modules are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the device bank and row to be accessed (BA0, BA1 select device bank; A0–A12 select device row). The address bits registered coincident with the READ or WRITE command are used to select the device bank and starting device column location for the burst access. DDR SDRAM modules provide for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. The pipelined, multibank architecture of DDR SDRAM modules allows for concurrent operation, thereby providing effective high bandwidth by hiding row precharge and activation time. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN PLL and Register Operation DDR SDRAM modules operate in registered mode, where the command/address input signals are latched in the registers on the rising clock edge and sent to the DDR SDRAM devices on the following rising clock edge (data access is delayed by one clock cycle). A phase-lock loop (PLL), on the module, receives and redrives the differential clock signals (CK, CK#) to the DDR SDRAM devices. The registers and PLL minimize system and clock loading. Serial Presence-Detect Operation DDR SDRAM modules incorporate serial presencedetect (SPD). The SPD function is implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains 256 bytes. The first 128 bytes can be programmed by Micron to identify the module type and various SDRAM organizations and timing parameters. The remaining 128 bytes of storage are available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to ground on the module, permanently disabling hardware write protect. Mode Register Definition The mode register is used to define the specific mode of operation of DDR SDRAM devices. This definition includes the selection of a burst length, a burst type, a CAS latency and an operating mode, as shown in the Mode Register Diagram. The mode register is programmed via the MODE REGISTER SET command (with BA0 = 0 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power (except for bit A8, which is self-clearing). Reprogramming the mode register will not alter the contents of the memory, provided it is performed correctly. The mode register must be loaded (reloaded) when all device banks are idle and no bursts are in progress, and the controller must wait the specified 9 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM The ordering of accesses within a burst is determined by the burst length, the burst type and the starting column address, as shown in Table 6, Burst Definition Table, on page 11. time before initiating the subsequent operation. Violating either of these requirements will result in unspecified operation. Mode register bits A0–A2 specify the burst length, A3 specifies the type of burst (sequential or interleaved), A4–A6 specify the CAS latency, and A7–A12 specify the operating mode. Figure 6: Mode Register Definition Diagram Burst Length BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Read and write accesses to DDR SDRAM devices are burst oriented, with the burst length being programmable, as shown in Figure 6, Mode Register Definition Diagram. The burst length determines the maximum number of column locations that can be accessed for a given READ or WRITE command. Burst lengths of 2, 4, or 8 locations are available for both the sequential and the interleaved burst types. Reserved states should not be used, because unknown operation or incompatibility with future versions may result. When a READ or WRITE command is issued, a block of columns equal to the burst length is effectively selected. All accesses for that burst take place within this block, meaning that the burst will wrap within the block if a boundary is reached. The block is uniquely selected by A1–Ai when the burst length is set to two, by A2–Ai when the burst length is set to four and by A3–Ai when the burst length is set to eight (where Ai is the most significant column address bit for a given configuration. See Note 5 of Table 6, Burst Definition Table, on page 11, for Ai values). The remaining (least significant) address bit(s) is (are) used to select the starting location within the block. The programmed burst length applies to both READ and WRITE bursts.. 14 13 12 11 10 9 8 Operating Mode 0* 0* 7 * M14 and M13 (BA1 and BA0) must be “0, 0” to select the base mode register (vs. the extended mode register). Mode Register (Mx) Burst Length M2 M1 M0 0 Reserved Reserved 0 0 1 2 2 0 1 0 4 4 0 1 1 8 8 1 0 0 Reserved Reserved 1 0 1 Reserved Reserved 1 1 0 Reserved Reserved 1 1 1 Reserved Reserved Burst Type 0 Sequential 1 Interleaved CAS Latency 0 0 0 Reserved 0 0 1 Reserved 0 1 0 2 0 1 1 Reserved 1 0 0 Reserved 1 0 1 Reserved 1 1 0 2.5 1 1 1 Reserved M12 M11 M10 M9 M8 M7 10 M3 = 1 0 M6 M5 M4 Accesses within a given burst may be programmed to be either sequential or interleaved; this is referred to as the burst type and is selected via bit M3. M3 = 0 0 M3 Burst Type pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 6 5 4 3 2 1 0 CAS Latency BT Burst Length Address Bus M6-M0 Operating Mode 0 0 0 0 0 0 Valid Normal Operation 0 0 0 0 1 0 Valid Normal Operation/Reset DLL - - - - - - - All other states reserved Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 6: Burst Definition Table STARTING COLUMN ADDRESS BURST LENGTH Figure 7: CAS Latency Diagram ORDER OF ACCESSES WITHIN A BURST CK# TYPE = TYPE = SEQUENTIAL INTERLEAVED COMMAND T0 T1 T2 READ NOP NOP T3 T3n CK A0 2 T2n NOP CL = 2 0 1 0-1 1-0 0-1 1-0 0-1-2-3 1-2-3-0 2-3-0-1 3-0-1-2 0-1-2-3 1-0-3-2 2-3-0-1 3-2-1-0 DQS DQ A1 A0 0 0 1 1 4 0 1 0 1 CK# T0 T1 T2 READ NOP NOP 8 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 T3 T3n CK COMMAND NOP CL = 2.5 A2 A1 A0 0 0 0 0 1 1 1 1 T2n 0-1-2-3-4-5-6-7 1-2-3-4-5-6-7-0 2-3-4-5-6-7-0-1 3-4-5-6-7-0-1-2 4-5-6-7-0-1-2-3 5-6-7-0-1-2-3-4 6-7-0-1-2-3-4-5 7-0-1-2-3-4-5-6 DQS 0-1-2-3-4-5-6-7 1-0-3-2-5-4-7-6 2-3-0-1-6-7-4-5 3-2-1-0-7-6-5-4 4-5-6-7-0-1-2-3 5-4-7-6-1-0-3-2 6-7-4-5-2-3-0-1 7-6-5-4-3-2-1-0 DQ Burst Length = 4 in the cases shown Shown with nominal tAC, tDQSCK, and tDQSQ TRANSITIONING DATA DON’T CARE Read Latency NOTE: The READ latency is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The latency can be set to 2 or 2.5 clocks, as shown in Figure 7, CAS Latency Diagram. If a READ command is registered at clock edge n, and the latency is m clocks, the data will be available nominally coincident with clock edge n + m. The CAS Latency Table indicates the operating frequencies at which each CAS latency setting can be used. Reserved states should not be used, because unknown operation or incompatibility with future versions may result. 1. For a burst length of two, A1–Ai select the two-dataelement block; A0 selects the first access within the block. 2. For a burst length of four, A2–Ai select the four-dataelement block; A0–A1 select the first access within the block. 3. For a burst length of eight, A3–Ai select the eight-dataelement block; A0–A2 select the first access within the block. 4. Whenever a boundary of the block is reached within a given sequence above, the following access wraps within the block. 5. i = 9, 11 (512MB) i = 9, 11, 12 (1GB) Table 7: Operating Mode CAS Latency (CL) Table The normal operating mode is selected by issuing a MODE REGISTER SET command with bits A7–A12 each set to zero, and bits A0–A6 set to the desired values. A DLL reset is initiated by issuing a MODE REGISTER SET command with bits A7 and A9–A12 each set to zero, bit A8 set to one, and bits A0–A6 set to the desired values. Although not required by the Micron device, JEDEC specifications recommend when a LOAD MODE REGISTER command is issued to reset ALLOWABLE OPERATING CLOCK FREQUENCY (MHz) SPEED CL = 2 CL = 2.5 -335 -262 -26A -265 -202 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 100 75 ≤ f ≤ 100 75 ≤ f ≤ 166 75 ≤ f ≤ 133 75 ≤ f ≤ 133 75 ≤ f ≤ 133 N/A pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 11 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM DLL Enable/Disable the DLL, it should always be followed by a LOAD MODE REGISTER command to select normal operating mode. All other combinations of values for A7–A12 are reserved for future use and/or test modes. Test modes and reserved states should not be used because unknown operation or incompatibility with future versions may result. The DLL must be enabled for normal operation. DLL enable is required during power-up initialization and upon returning to normal operation after having disabled the DLL for the purpose of debug or evaluation. (When the device exits self refresh mode, the DLL is enabled automatically.) Any time the DLL is enabled, a DLL Reset and 200 clock cycles with CKE HIGH must occur before a READ command can be issued. Extended Mode Register The extended mode register controls functions beyond those controlled by the mode register; these additional functions are DLL enable/disable and output drive strength. These functions are controlled via the bits shown in the Extended Mode Register Definition Diagram. The extended mode register is programmed via the LOAD MODE REGISTER command to the mode register (with BA0 = 1 and BA1 = 0) and will retain the stored information until it is programmed again or the device loses power. The enabling of the DLL should always be followed by a LOAD MODE REGISTER command to the mode register (BA0/BA1 both LOW) to reset the DLL. The extended mode register must be loaded when all device banks are idle and no bursts are in progress, and the controller must wait the specified time before initiating any subsequent operation. Violating either of these requirements could result in unspecified operation. Figure 8: Extended Mode Register Definition Diagram BA1 BA0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 14 13 12 11 10 9 8 7 6 5 Operating Mode 01 11 E12 E11 E10 E9 E8 E7 E6 E5 E4 E3 E22 4 3 2 1 0 Address Bus Extended Mode Register (Ex) DS DLL E0 DLL 0 Enable 1 Disable E1 Drive Strength 0 Normal E1, E0 Operating Mode 0 0 0 0 0 0 0 0 0 0 0 Valid Reserved – – – – – – – – – – – – Reserved NOTE: 1. BA1 and BA0 (E14 and E13) must be “0, 1” to select the Extended Mode Register (vs. the base Mode Register). 2. QFC# is not supported. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 12 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Commands Table 8, Commands Truth Table, and Table 9, DM Operation Truth Table, provide a general reference of available commands. For a more detailed description Table 8: of commands and operations, refer to the 256Mb or 512Mb DDR SDRAM component data sheet. Commands Truth Table CKE is HIGH for all commands shown except SELF REFRESH; all states and sequences not shown are illegal or reserved NAME (FUNCTION) CS# RAS# CAS# WE# ADDR NOTES H L L L L L L L L X H L H H H L L L X H H L L H H L L X H H H L L L H L X X Bank/Row Bank/Col Bank/Col X Code X Op-Code 1 1 2 3 3 4 5 6, 7 8 DESELECT (NOP) NO OPERATION (NOP) ACTIVE (Select bank and activate row) READ (Select bank and column, and start READ burst) WRITE (Select bank and column, and start WRITE burst) BURST TERMINATE PRECHARGE (Deactivate row in bank or banks) AUTO REFRESH or SELF REFRESH (Enter self refresh mode) LOAD MODE REGISTER NOTE: 1. DESELECT and NOP are functionally interchangeable. 2. BA0–BA1 provide device bank address and A0–A12 provide row address. 3. BA0–BA1 provide device bank address; A0–A9, A11 (512MB) or A0–A9, A11, A12 (1GB) provide column address; A10 HIGH enables the auto precharge feature (nonpersistent), and A10 LOW disables the auto precharge feature. 4. Applies only to read bursts with auto precharge disabled; this command is undefined (and should not be used) for READ bursts with auto precharge enabled and for WRITE bursts. 5. A10 LOW: BA0–BA1 determine which device bank is precharged. A10 HIGH: all device banks are precharged and BA0– BA1 are “Don’t Care.” 6. This command is AUTO REFRESH if CKE is HIGH, SELF REFRESH if CKE is LOW. 7. Internal refresh counter controls row addressing; all inputs and I/Os are “Don’t Care” except for CKE. 8. BA0–BA1 select either the mode register or the extended mode register (BA0 = 0, BA1 = 0 select the mode register; BA0 = 1, BA1 = 0 select extended mode register; other combinations of BA0-BA1 are reserved). A0–A12 provide the op-code to be written to the selected mode register. Table 9: DM Operation Truth Table Used to mask write data; provided coincident with the corresponding data NAME (FUNCTION) WRITE Enable WRITE Inhibit pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 13 DM DQS L H Valid X Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Absolute Maximum Ratings Stresses greater than those listed may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions above those indicated in the opera- tional sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Voltage on VDD Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VDDQ Supply Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on VREF and Inputs Relative to VSS . . . . . . . . . . . . . . . . . . . . -1V to +3.6V Voltage on I/O Pins Relative to VSS . . . . . . . . . . . . -0.5V to VDDQ +0.5V Operating Temperature TA (commercial - ambient) . . . . . . . .. 0°C to +70°C Storage Temperature (plastic) . . . . . . -55°C to +150°C Short Circuit Output Current. . . . . . . . . . . . . . . 50mA Table 10: DC Electrical Characteristics and Operating Conditions Notes: 1–5, 14; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage INPUT LEAKAGE CURRENT Any input 0V ≤ VIN ≤ VDD, VREF pin 0V ≤ VIN ≤ 1.35V (All other pins not under test = 0V) SYMBOL VDD VDDQ VREF VTT VIH(DC) VIL(DC) Command/ Address, RAS#, CAS#, WE#, S#, CKE CK, CK# DQ, DQS OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V ≤ VOUT ≤ VDDQ) OUTPUT LEVELS High Current (VOUT = VDDQ - 0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF, maximum VTT) MIN MAX UNITS NOTES V V V V V V 32, 36 32, 36, 39 6, 39 7, 39 25 25 µA 47 2.3 2.7 2.3 2.7 0.49 X VDDQ 0.51 X VDDQ VREF - 0.04 VREF + 0.04 VREF + 0.15 VDD + 0.3 -0.3 VREF - 0.15 -5 5 II IOZ -10 -5 10 5 µA 47 IOH IOL -16.8 16.8 – – mA mA 33, 34 Table 11: AC Input Operating Conditions Notes: 1–5, 14, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD, VDDQ = +2.5V ±0.2V PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage I/O Reference Voltage pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN SYMBOL MIN MAX UNITS NOTES VIH(AC) VIL(AC) VREF(AC) VREF + 0.310 – 0.49 X VDDQ – VREF - 0.310 0.51 X VDDQ V V V 12, 25, 35 12, 25, 35 6 14 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 12: IDD Specifications and Conditions – 512MB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION OPERATING CURRENT: One device bank; Active-Precharge; RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125µs SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands SYMBOL -335 -262 -26A/ -265/202 IDD0 2,250 2,250 2,160 mA 20, 43 IDD1 3,060 2,880 2,610 mA 20, 43 IDD2P 72 72 72 mA IDD2F 900 810 810 mA 21, 28, 45 46 IDD3P 540 450 450 mA IDD3N 1,080 900 900 mA 21, 28, 45 42 IDD4R 3,150 2,700 2,700 mA 20, 43 IDD4W 3,150 2,700 2,700 mA 20 IDD5 IDD5A IDD6 IDD7 4,590 108 72 7,380 4,230 108 72 6,300 4,230 108 72 6,300 mA mA mA mA 20, 45 24, 45 9 20, 44 UNITS NOTES t pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 15 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 13: IDD Specifications and Conditions – 1GB DDR SDRAM components only Notes: 1–5, 8, 10, 12, 48; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V MAX PARAMETER/CONDITION SYMBOL -335 -262 -26A/ -265/ -202 IDD0 2,340 2,340 2,070 mA 20, 43 IDD1 2,880 2,880 2,610 mA 20, 43 IDD2P 90 90 90 mA IDD2F 810 810 720 mA 21, 28, 45 46 IDD3P 630 630 540 mA IDD3N 900 900 810 mA 21, 28, 45 42 IDD4R 2,970 2,970 2,610 mA 20, 43 IDD4W 3,150 2,790 2,430 mA 20 IDD5 IDD5A IDD6 IDD7 5,220 180 90 7,290 5,220 180 90 7,200 5,040 180 90 6,300 mA mA mA mA 20, 45 24, 45 9 20, 44 OPERATING CURRENT: One device bank; Active-Precharge; t RC = tRC (MIN); tCK = tCK (MIN); DQ, DM and DQS inputs changing once per clock cyle; Address and control inputs changing once every two clock cycles OPERATING CURRENT: One device bank; Active -Read Precharge; Burst = 4; tRC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All device banks idle; Power-down mode; tCK = tCK (MIN); CKE = (LOW) IDLE STANDBY CURRENT: CS# = HIGH; All device banks idle; tCK = tCK MIN; CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One device bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One device bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One device bank active; Address and control inputs changing once per clock cycle; tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle tREFC = tRFC (MIN) AUTO REFRESH CURRENT tREFC = 7.8125µs SELF REFRESH CURRENT: CKE ≤ 0.2V OPERATING CURRENT: Four device bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tCK (MIN); Address and control inputs change only during Active READ, or WRITE commands pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 16 UNITS NOTES Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 14: Capacitance Note: 11; notes appear on pages 21–24 PARAMETER SYMBOL MIN MAX UNITS CI0 CI1 CI2 4 2.5 2 5 3.5 3 pF pF pF Input/Output Capacitance: DQ, DQS Input Capacitance: Command and Address, S#, CKE Input Capacitance: CK, CK# Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS PARAMETER -335 SYMBOL MIN MAX MIN MAX UNITS tAC -0.7 0.45 0.45 6 7.5 0.45 0.45 1.75 -0.60 0.35 0.35 +0.70 0.55 0.55 13 13 -0.75 0.45 0.45 7.5 7.5 0.45 0.45 1.75 -0.75 0.35 0.35 +0.75 0.55 0.55 13 13 ns tCK tCK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time tCH tCL tCK (2.5) CL = 2.5 tCK (2) CL = 2 tDH DQ and DM input hold time relative to DQS tDS DQ and DM input setup time relative to DQS tDIPW DQ and DM input pulse width (for each input) tDQSCK Access window of DQS from CK/CK# tDQSH DQS input high pulse width tDQSL DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access tDQSQ tDQSS Write command to first DQS latching transition tDSS DQS falling edge to CK rising - setup time tDSH DQS falling edge from CK rising - hold time tHP Half clock period tHZ Data-out high-impedance window from CK/CK# tLZ Data-out low-impedance window from CK/CK# tIH Address and control input hold time (fast slew rate) F t ISF Address and control input setup time (fast slew rate) tIH Address and control input hold time (slow slew rate) S tIS Address and control input setup time (slow slew rate) S tIPW Address and Control input pulse width (for each input) t MRD LOAD MODE REGISTER command cycle time t QH DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN -262 t QHS RAS tRAP tRC tRFC t RCD tRP t 17 +0.60 0.45 0.75 1.25 0.2 0.2 tCH, tCL +0.70 -0.70 0.75 0.75 0.80 0.80 2.2 12 t HP tQHS 0.55 42 70,000 15 60 75 15 15 +0.75 0.50 0.75 1.25 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 t HP tQHS 0.75 40 120,000 15 60 75 15 15 ns ns ns ns ns ns ns NOTES 26 26 40, 46 40, 46 23, 27 23, 27 27 22, 23 30 16, 37 16, 37 12 12 12 12 22, 23 31, 49 44 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 15: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-335, -262) (Continued) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS PARAMETER DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN -335 SYMBOL tRPRE t RPST RRD t WPRE t WPRES tWPST tWR tWTR na tREFC tREFI tVTD tXSNR tXSRD t 18 MIN MAX 0.9 1.1 0.4 0.6 12 0.25 0 0.4 0.6 15 1 t QH - tDQSQ 70.3 7.8 0 75 200 -262 MIN MAX 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 t QH - tDQSQ 70.3 7.8 0 75 200 UNITS NOTES tCK 38 38 t CK ns t CK ns tCK ns tCK ns µs µs ns ns tCK 18, 19 17 22 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS -26A/-265 PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time SYMBOL t AC tCH t CL = 2.5 CL = 2 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) Address and Control input pulse width (for each input) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN CL (2.5) t CK (2) t DH tDS tDIPW tDQSCK tDQSH tDQSL tDQSQ tDQSS tDSS tDSH tHP tHZ tLZ tIH F tIS F tIH S tIS S tIPW tMRD tQH tCK tQHS tRAS tRAP t RC tRFC tRCD tRP t RPRE RPST tRRD tWPRE tWPRES tWPST t WR tWTR na t 19 -202 MIN MAX MIN MAX -0.75 0.45 0.45 7.5 7.5/10 0.5 0.5 1.75 -0.75 0.35 0.35 +0.75 0.55 0.55 13 13 -0.8 0.45 0.45 8 10 0.6 0.6 2 -0.8 0.35 0.35 +0.8 0.55 0.55 13 13 +0.75 0.5 1.25 0.75 0.2 0.2 tCH, tCL +0.75 -0.75 0.90 0.90 1 1 2.2 15 tHP t QHS 0.75 40 120,000 20 65 75 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ +0.8 0.6 1.25 0.75 0.2 0.2 tCH, tCL +0.8 -0.8 1.1 1.1 1.1 1.1 2.2 16 tHP t QHS 1 40 120,000 20 70 80 20 20 0.9 1.1 0.4 0.6 15 0.25 0 0.4 0.6 15 1 tQH - tDQSQ UNITS NOTES ns tCK t CK ns ns ns ns ns ns tCK tCK ns tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns tCK ns tCK ns tCK ns 26 26 40, 46 40, 46 23, 27 23, 27 27 22, 23 30 16, 37 16, 37 12 12 12 12 22, 23 31, 49 44 38 38 18, 19 17 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 16: DDR SDRAM Component Electrical Characteristics and Recommended AC Operating Conditions (-26A, -265, -202) (Continued) Notes: 1–5, 12-15, 29, 49; notes appear on pages 21–24; 0°C ≤ TA ≤ +70°C; VDD = VDDQ = +2.5V ±0.2V AC CHARACTERISTICS PARAMETER REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to VDD Exit SELF REFRESH to non-READ command Exit SELF REFRESH to READ command pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN -26A/-265 SYMBOL MIN tREFC REFI VTD t XSNR t XSRD 20 MIN 70.3 7.8 t t MAX -202 0 75 200 0 80 200 MAX UNITS NOTES 70.3 7.8 µs µs ns ns t CK 21 21 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Notes 1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: 12. VTT Output (VOUT) 50Ω Reference Point 30pF 13. 14. 4. AC timing and IDD tests may use a VIL-to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (non-common mode) on VREF may not exceed ±2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed ±25mV for DC error and an additional ±25mV for AC noise. This measurement is to be taken at the nearest VREF by-pass capacitor. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. IDD is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2 for -262, -26A, and -202, CL = 2.5 for -335 and -265 with the outputs open. 9. Enables on-chip refresh and address counters. 10. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 11. This parameter is sampled. VDD = +2.5V ±0.2V, VDDQ = +2.5V ±0.2V, VREF = VSS, f = 100 MHz, TA = 25°C, VOUT (DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 15. 16. 17. 18. 19. 20. 21. 21 input is grouped with I/O pins, reflecting the fact that they are matched in loading. For slew rates less than 1 V/ns and greater than or equal to 0.5 V/ns. If slew rate is less than 0.5 V/ns, timing must be derated: tIS has an additional 50ps per each 100 mV/ns reduction in slew rate from 500 mV/ns, while tIH is unaffected. If slew rate exceeds 4.5 V/ns, functionality is uncertain. For 335, slew rates must be ≥ 0.5 V/ns. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE ≤ 0.3 x VDDQ is recognized as LOW. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. t HZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). The intent of the Don’t Care state after completion of the postamble is the DQS-driven signal should either be high, low, or high-Z and that any signal transition within the input switching region must follow valid input requirements. That is, if DQS transitions high (above VIHDC (MIN) then it must not transition low (below VIHDC) prior to tDQSH (MIN). This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. MIN (tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. The refresh period 64ms. This equates to an average refresh rate of 7.8125µs. However, an AUTO REFRESH command must be asserted at least Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM 22. 23. 24. 25. once every 70.3µs; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. The valid data window is derived by achieving other specifications: tHP (tCK/2), tDQSQ, and tQH (tQH = tHP - tQHS). The data valid window derates in direct porportion to the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55, beyond which functionality is uncertain. Figure 9, Derating Data Valid Window (tQH tDQSQ), shows duty cycles ranging between 50/50 and 45/55. Each byte lane has a corresponding DQS. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period (tRFC [MIN]) else CKE is LOW (i.e., during standby). To maintain a valid level, the transitioning edge of the input must: a. Sustain a constant slew rate from the current AC level through to the target AC level, VIL (AC) or VIH (AC). b. Reach at least the target AC level. c. After the AC target level is reached, continue to 26. 27. 28. 29. 30. 31. maintain at least the target DC level, VIL (DC) or VIH (DC). JEDEC specifies CK and CK# input slew rate must be ≥ 1V/ns (2V/ns differentially). DQ and DM input slew rates must not deviate from DQS by more than 10 percent. If the DQ/ DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. For -335, slew rates must be ≥ 0.5 V/ns. For 335, slew rates must be ≥ 0.5 V/ns. VDD must not vary more than 4 percent if CKE is not active while any bank is active. The clock is allowed up to ±150ps of jitter. Each timing parameter is allowed to vary by the same amount. t HP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK# inputs, collectively during bank active. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. Figure 9: Derating Data Valid Window (tQH - tDQSQ) 3.8 3.750 3.700 3.6 3.400 3.4 3.350 3.650 3.600 3.550 3.500 3.450 3.300 3.400 3.250 3.200 3.150 3.2 3.100 tCK -26A/-265 @ = 10ns -202 @ tCK = 10ns -26A/-265 @ tCK = 7.5ns N/A -202 @ tCK = 8ns N/A -335 @ tCK = 6ns ns 3.0 2.8 2.6 2.500 2.463 2.425 3.350 2.388 2.350 2.313 2.275 3.250 3.050 3.000 2.4 3.300 2.238 2.200 2.950 2.163 2.2 2.900 2.125 2.0 1.8 50/50 49.5/50.5 49/51 48.5/52.5 48/52 47.5/53.5 47/53 46.5/54.5 46/54 45.5/55.5 45/55 Clock Duty Cycle pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 22 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM 32. Any positive glitch must be less than 1/3 of the clock and not more than +400mV or 2.9V, whichever is less. Any negative glitch must be less than 1/3 of the clock cycle and not exceed either 300mV or 2.2V, whichever is more positive. 33. Normal Output Drive Curves: a. The full variation in driver pull-down current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 10. b. The variation in driver pull-down current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 10. c. The full variation in driver pull-up current from minimum to maximum process, temperature and voltage will lie within the outer bounding lines of the V-I curve of Figure 11. d. The variation in driver pull-up current within nominal limits of voltage and temperature is expected, but not guaranteed, to lie within the inner bounding lines of the V-I curve of Figure 11. e. The full variation in the ratio of the maximum to minimum pull-up and pull-down current should be between 0.71 and 1.4, for device drain-to-source voltages from 0.1V to 1.0V, and at the same voltage and temperature. f. The full variation in the ratio of the nominal pull-up to pull-down current should be unity ±10 percent, for device drain-to-source voltages from 0.1V to 1.0V. 34. The voltage levels used are derived from a minimum VDD level and the referenced test load. In practice, the voltage levels obtained from a prop- erly terminated bus will provide significantly different voltage values. VIH overshoot: VIH (MAX) = VDDQ + 1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL (MIN) = -1.5V for a pulse width ≤ 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VDD and VDDQ must track each other. tHZ (MAX) will prevail over tDQSCK (MAX) + tRPST (MAX) condition. tLZ (MIN) will prevail over tDQSCK (MIN) + tRPRE (MAX) condition. t RPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving (tRPST), or begins driving (tRPRE). During initialization, VDDQ, VTT, and VREF must be equal to or less than VDD + 0.3V. Alternatively, VTT may be 1.35V maximum during power up, even if VDD/VDDQ are 0V, provided a minimum of 42Ω of series resistance is used between the VTT supply and the input pin. The current Micron part operates below the slowest JEDEC operating frequency of 83 MHz. As such, future die may not reflect this option. For -335, -262, -26A and -265, IDD3N is specified to be 35mA per DDR SDRAM at 100 MHz. Random address changing and 50 percent of data changing at every transfer. Random address changing and 100 percent of data changing at every transfer. CKE must be active (high) during the entire time a refresh command is executed. That is, from the time the AUTO REFRESH command is registered, CKE must be active at each rising clock edge, until t REF later. 35. 36. 37. 38. 39. 40. 41. 42. 43. 44. Figure 10: Pull-Down Figure 11: Pull-Up 160 0 140 -20 um Maxim Maximum -40 120 IOUT (mA) 80 Nominal low 60 -80 -100 Nom inal low -120 -140 Minimum 40 Nominal high -60 high IOUT (mA) Nominal 100 Min imu m -160 20 -180 0 -200 0.0 0.5 1.0 1.5 2.0 0.0 2.5 pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 0.5 1.0 1.5 2.0 2.5 VDDQ - VOUT (V) VOUT (V) 23 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM 47. Leakage number reflects the worst case leakage possible through the module pin, not what each memory device contributes. 48. When an input signal is HIGH or LOW, it is defined as a steady state logic high or logic low. 49. The -335 speed grade will operate with tRAS (MIN) = 40ns and tRAS (MAX) = 120,000ns at any slower frequency. 45. IDD2N specifies the DQ, DQS, and DM to be driven to a valid high or low logic level. IDD2Q is similar to IDD2F except IDD2Q specifies the address and control inputs to remain stable. Although IDD2F, IDD2N, and IDD2Q are similar, IDD2F is “worst case.” 46. Whenever the operating frequency is altered, not including jitter, the DLL is required to be reset. This is followed by 200 clock cycles (before READ commands). pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 24 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Initialization Figure 12: Initialization Flow Diagram To ensure device operation the DRAM must be initialized as described below: 1. Simultaneously apply power to VDD and VDDQ. 2. Apply VREF and then VTT power. 3. Assert and hold CKE at a LVCMOS logic low. 4. Provide stable CLOCK signals. 5. Wait at least 200µs. 6. Bring CKE high and provide at least one NOP or DESELECT command. At this point the CKE input changes from a LVCMOS input to a SSTL2 input only and will remain a SSTL_2 input unless a power cycle occurs. 7. Perform a PRECHARGE ALL command. 8. Wait at least tRP time, during this time NOPs or DESELECT commands must be given. 9. Using the LMR command program the Extended Mode Register (E0 = 0 to enable the DLL and E1 = 0 for normal drive or E1 = 1 for reduced drive, E2 through En must be set to 0; where n = most significant bit). 10. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 11. Using the LMR command program the Mode Register to set operating parameters and to reset the DLL. Note at least 200 clock cycles are required between a DLL reset and any READ command. 12. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 13. Issue a PRECHARGE ALL command. 14. Wait at least tRP time, only NOPs or DESELECT commands are allowed. 15. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 16. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 17. Issue an AUTO REFRESH command (Note this may be moved prior to step 13). 18. Wait at least tRFC time, only NOPs or DESELECT commands are allowed. 19. Although not required by the Micron device, JEDEC requires a LMR command to clear the DLL bit (set M8 = 0). If a LMR command is issued the same operating parameters should be utilized as in step 11. 20. Wait at least tMRD time, only NOPs or DESELECT commands are allowed. 21. At this point the DRAM is ready for any valid command. Note 200 clock cycles are required between step 11 (DLL Reset) and any READ command. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN Step 25 1 VDD and VDDQ Ramp 2 Apply VREF and VTT 3 CKE must be LVCMOS Low 4 Apply stable CLOCKs 5 Wait at least 200us 6 Bring CKE High with a NOP command 7 PRECHARGE ALL 8 Assert NOP or DESELECT for tRP time 9 Configure Extended Mode Register 10 Assert NOP or DESELECT for tMRD time 11 Configure Load Mode Register and reset DLL 12 Assert NOP or DESELECT for tMRD time 13 PRECHARGE ALL 14 Assert NOP or DESELECT for tRP time 15 Issue AUTO REFRESH command 16 Assert NOP or DESELECT commands for tRFC 17 Issue AUTO REFRESH command 18 Assert NOP or DESELECT for tRFC time 19 Optional LMR command to clear DLL bit 20 Assert NOP or DESELECT for tMRD time 21 DRAM is ready for any valid command Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 17: PLL Clock Driver Timing Requirements and Switching Characteristics Note: 1 0°C ≤ TA ≤ +70°C VDD = 2.5V ± 0.2V PARAMETER SYMBOL MIN NOMINAL MAX UNITS NOTES CK 60 - 170 MHz 2, 3 DC 40 - 60 % STAB - - 100 ms JITCC -75 - 75 ps ∅ -50 0 50 ps - - 100 ps -75 - 75 ps 6 -100 - 100 ps 6 Operating Clock Frequency f Input Duty Cycle t Stabilization Time t Cycle to Cycle Jitter t Static Phase Offset t Output Clock Skew tSK O Period Jitter tJIT Half-Period Jitter t PER JITHPER Input Clock Slew Rate tLS 1.0 - 4 V/ns Output Clock Slew Rate tLS 1.0 - 2 V/ns I O 4 5 7 NOTE: 1. The timing and switching specifications for the PLL listed above are critical for proper operation of the DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this PLL is available in JEDEC Standard JESD82. 2. The PLL must be able to handle spread spectrum induced skew. 3. Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up. 5. Static Phase Offset does not include Jitter. 6. Period Jitter and Half-Period Jitter specifications are separate specifications that must be met independently of each other. 7. The Output Slew Rate is determined from the IBIS model: VDD CDCV857 VCK R=60 Ω R=60 Ω VDD/2 VCK GND pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 26 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 18: Register Timing Requirements and Switching Characteristics Note: 1 0°C ≤ TA ≤ +70°C VDD = 2.5V ± 0.2V REGISTER SSTL (bit pattern by JESD82-3 or JESD82-4) SYMBOL PARAMERTER fclock Clock Frequency tpd Clock to Output Time tPHL Reset to Output Time tw Pulse Duration tact tinact tsu th CONDITION MIN MAX UNITS - 200 MHz 30pF to GND and 50Ω to VTT 1.1 2.8 ns - 5 ns CK, CK# HIGH or LOW 2.5 - ns Differential Inputs Active Time - 22 ns 2 Differential Inputs Inactive Time Setup Time, Fast Slew Rate Setup Time, Slow Slew Rate Hold Time, Fast Slew Rate Hold Time, Slow Slew Rate - 22 ns 3 0.75 0.90 0.75 0.90 - ns ns ns ns 4, 6 5, 6 4, 6 5, 6 Data Before CK HIGH, CK# LOW Data After CK HIGH, CK# LOW NOTES NOTE: 1. The timing and switching specifications for the register listed above are critical for proper operation of DDR SDRAM Registered DIMMs. These are meant to be a subset of the parameters for the specific device used on the module. Detailed information for this register is available in JEDEC Standard JESD82. 2. Data inputs must be low a minimum time of tact max, after RESET# is taken HIGH. 3. Data and clock inputs must be held at valid levels (not floating) a minimum time of tinact max, after RESET# is taken LOW. 4. For data signal input slew rate ≥ 1 V/ns. 5. For data signal input slew rate ≥ 0.5 V/ns and < 1V/ns. 6. CK, CK# signals input slew rate ≥ 1V/ns. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 27 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 13: Component Case Temperature vs. Air Flow 100 Ambient Temperature = 25º C 90 Tmax- memory stress software Degrees Celsius 80 70 Tave- memory stress software 60 50 Tave- 3D gaming software 40 30 Minimum Air Flow 20 2.0 1.0 0.5 0.0 Air Flow (meters/sec) NOTE: 1. Micron Technology, Inc. recommends a minimum air flow of 1 meter/second (~197 LFM) across all modules. 2. The component case temperature measurements shown above were obtained experimentally. The typical system to be used for experimental purposes is a dual-processor 600 MHz work station, fully loaded, with four comparable registered memory modules. Case temperatures charted represent worst-case component locations on modules installed in the internal slots of the system. 3. Temperature versus air speed data is obtained by performing experiments with the system motherboard removed from its case and mounted in a Eiffel-type low air speed wind tunnel. Peripheral devices installed on the system motherboard for testing are the processor(s) and video card, all other peripheral devices are mounted outside of the wind tunnel test chamber. 4. The memory diagnostic software used for determining worst-case component temperatures is a memory diagnostic software application developed for internal use by Micron Technology, Inc. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 28 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM SPD Clock and Data Conventions SPD Acknowledge Data states on the SDA line can change only during SCL LOW. SDA state changes during SCL HIGH are reserved for indicating start and stop conditions (as shown in Figure 14, Data Validity, and Figure 15, Definition of Start and Stop). Acknowledge is a software convention used to indicate successful data transfers. The transmitting device, either master or slave, will release the bus after transmitting eight bits. During the ninth clock cycle, the receiver will pull the SDA line LOW to acknowledge that it received the eight bits of data (as shown in Figure 16, Acknowledge Response From Receiver). The SPD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a WRITE operation have been selected, the SPD device will respond with an acknowledge after the receipt of each subsequent eight-bit word. In the read mode the SPD device will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no stop condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return to standby power mode. SPD Start Condition All commands are preceded by the start condition, which is a HIGH-to-LOW transition of SDA when SCL is HIGH. The SPD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command until this condition has been met. SPD Stop Condition All communications are terminated by a stop condition, which is a LOW-to-HIGH transition of SDA when SCL is HIGH. The stop condition is also used to place the SPD device into standby power mode. Figure 14: Data Validity Figure 15: Definition of Start and Stop SCL SCL SDA SDA DATA STABLE DATA CHANGE DATA STABLE START BIT STOP BIT Figure 16: Acknowledge Response From Receiver SCL from Master 8 9 Data Output from Transmitter Data Output from Receiver Acknowledge pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 29 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 19: EEPROM Device Select Code The most significant bit (b7) is sent first DEVICE TYPE IDENTIFIER SELECT CODE Memory Area Select Code (two arrays) Protection Register Select Code CHIP ENABLE RW b7 b6 b5 b4 b3 b2 b1 b0 1 0 0 1 1 1 0 0 SA2 SA2 SA1 SA1 SA0 SA0 RW RW Table 20: EEPROM Operating Modes MODE Current Address Read Random Address Read Sequential Read Byte Write Page Write RW BIT WC BYTES 1 0 1 1 0 0 VIH or VIL VIH or VIL VIH or VIL VIH or VIL VIL VIL 1 1 1 ≥1 1 ≤ 16 INITIAL SEQUENCE START, Device Select, RW = ‘1’ START, Device Select, RW = ‘0’, Address reSTART, Device Select, RW = ‘1’ Similar to Current or Random Address Read START, Device Select, RW = ‘0’ START, Device Select, RW = ‘0’ Figure 17: SPD EEPROM Timing Diagram tF t HIGH tR t LOW SCL t SU:STA t HD:STA t SU:DAT t HD:DAT t SU:STO SDA IN t DH t AA t BUF SDA OUT UNDEFINED pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 30 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 21: Serial Presence-Detect EEPROM DC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SUPPLY VOLTAGE INPUT HIGH VOLTAGE: Logic 1; All inputs INPUT LOW VOLTAGE: Logic 0; All inputs OUTPUT LOW VOLTAGE: IOUT = 3mA INPUT LEAKAGE CURRENT: VIN = GND to VDD OUTPUT LEAKAGE CURRENT: VOUT = GND to VDD STANDBY CURRENT: SCL = SDA = VDD - 0.3V; All other inputs = GND or 3.3V ±10% POWER SUPPLY CURRENT: SCL clock frequency = 100 KHz SYMBOL MIN MAX UNITS VDDSPD VIH VIL VOL ILI ILO ISB 2.3 VDD x 0.7 -1 – – – – 3.6 VDD + 0.5 VDD x 0.3 0.4 10 10 30 V V V V µA µA µA ICC – 2 mA Table 22: Serial Presence-Detect EEPROM AC Operating Conditions All voltages referenced to VSS; VDDSPD = +2.3V to +3.6V PARAMETER/CONDITION SCL LOW to SDA data-out valid Time the bus must be free before a new transition can start Data-out hold time SDA and SCL fall time Data-in hold time Start condition hold time Clock HIGH period Noise suppression time constant at SCL, SDA inputs Clock LOW period SDA and SCL rise time SCL clock frequency Data-in setup time Start condition setup time Stop condition setup time WRITE cycle time SYMBOL MIN MAX UNITS NOTES tAA 0.2 1.3 200 0.9 µs µs ns ns µs µs µs ns µs µs KHz ns µs µs ms 1 tBUF tDH tF tHD:DAT tHD:STA tHIGH 300 0 0.6 0.6 tI tLOW 50 1.3 tR 0.3 400 fSCL tSU:DAT t SU:STA tSU:STO tWRC 100 0.6 0.6 10 2 2 3 4 NOTE: 1. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL = 1 and the falling or rising edge of SDA. 2. This parameter is sampled. 3. For a reSTART condition, or following a WRITE cycle. 4. The SPD EEPROM WRITE cycle time (tWRC) is the time from a valid stop condition of a write sequence to the end of the EEPROM internal erase/program cycle. During the WRITE cycle, the EEPROM bus interface circuit is disabled, SDA remains HIGH due to pull-up resistor, and the EEPROM does not respond to its slave address. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 31 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 23: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 34 BYTE DESCRIPTION 0 1 2 3 4 5 6 7 8 9 Number of SPD Bytes Used By Micron Total Number of Bytes In SPD Device Fundamental Memory Type Number of Row Addresses on Assembly Number of Column Addresses on Assembly Number of Physical Ranks on DIMM Module Data Width Module Data Width (Continued) Module Voltage Interface Levels SDRAM Cycle Time, tCK CAS Latency = 2.5 (See note 1) 10 SDRAM Access From Clock, tAC, CAS Latency = 2.5 11 12 13 14 15 Module Configuration Type Refresh Rate/type SDRAM Device Width (Primary DDR SDRAM) Error-checking DDR SDRAM Data Width Minimum Clock Delay, Back-to-Back Random Column Access Burst Lengths Supported Number of Banks on DDR SDRAM Device CAS Latencies Supported CS Latency WE Latency SDRAM Module Attributes SDRAM Device Attributes: General SDRAM Cycle Time, tCK, CAS Latency = 2 16 17 18 19 20 21 22 23 24 25 26 27 28 29 ENTRY (VERSION) MT18VDDF6472 MT18VDDF12872 128 256 DDR SDRAM 12 11, 12 1 72 0 SSTL 2.5V 6ns (-335) 7ns (-262/-26A) 7.5ns (-265) 8ns (-202) 0.7ns (-335) 0.75ns (-262/-26A/-265) 0.8ns (-202) ECC 7.8µs/SELF 4 4 1 clock 80 08 07 0D 0B 01 48 00 04 60 70 75 80 70 75 80 02 82 04 04 01 80 08 07 0D 0C 01 48 00 04 60 70 75 80 70 75 80 02 82 04 04 01 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50 0E 04 0C 01 02 26 C0 75 A0 70 75 80 00 00 48 3C 50 30 3C 48 3C 50 2, 4, 8 4 2, 2.5 0 1 Registered, PLL Fast/Concurrent AP 7.5ns (-335/-262/-26A) 10ns (-265/-202) tAC, CAS Latency = 2 0.7ns (-335) SDRAM Access From Clock, 0.75ns (-262/-26A/-265) 0.8ns (-202) N/A SDRAM Cycle Time, tCK, CAS Latency = 1.5 t N/A SDRAM Access From CK, AC, CAS Latency = 1.5 18ns (-335) Minimum Row Precharge Time, tRP 15ns (-262) 20ns (-26A/-265/-202) 12ns (-335) Minimum Row Active to Row Active, tRRD 15ns (-262/-26A/-265/-202) 18ns (-335) Minimum RAS# to CAS# Delay, tRCD 15ns (-262) 20ns (-26A/-265/-202) pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 32 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 23: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 34 BYTE DESCRIPTION tRAS, 30 Minimum RAS# Pulse Width, 31 32 Module Rank Density Address and Command Setup Time, tIS, (See note 4) 33 Address and Command Hold Time, tIH, (See note 4) 34 Data/Data Mask Input Setup Time, tDS 35 Data/Data Mask Input Hold Time, tDH (See note 3) 36-40 Reserved 41 Min Active Auto Refresh Time, tRC 42 Minimum Auto Refresh to Active/Auto Refresh Command Period, tRFC 43 SDRAM Device Max Cycle Time, tCKMAX 44 SDRAM Device Max DQS-DQ Skew Time, tDQSQ 45 SDRAM Device Max Read Data Hold Skew Factor, tQHS 46-61 47 48-61 62 63 Reserved DIMM Height Reserved SPD Revision Checksum for Bytes 0–62 64 65-71 72 73-90 91 92 Manufacturer’s JEDEC ID Code Manufacturer’s JEDEC IDCode Manufacturing Location Module Part Number (ASCII) PCB Identification Code Identification Code (Continued) pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN ENTRY (VERSION) MT18VDDF6472 MT18VDDF12872 42ns (-335) 45ns (-262/-26A/-265) 40ns (-202) 256MB, 512MB 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.8ns (-335) 1.0ns (-262/-26A/-265) 1.1ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 2A 2D 28 80 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 6E 0B 38 68 03 2C FF 01–0C Variable Data 01-09 00 2A 2D 28 01 80 A0 B0 80 A0 B0 45 50 60 45 50 60 00 3C 41 46 48 4B 50 30 34 28 32 3C 50 75 A0 00 01 00 10 F0 8D BA EA 85 2C FF 01–0C Variable Data 01-09 00 60ns (335/-262) 65ns (-26A/-265) 70ns (-202) 72ns (-335) 75ns (-262/-26A/-265) 80ns (-202) 12ns (-335) 13ns (-262/-26A/-265/-202) 0.45ns (-335) 0.5ns (-262/-26A/-265) 0.6ns (-202) 0.55ns (-335) 0.75ns (-262/-26A/-265) 1.0ns (-202) Low-profile Release 1.0 -335 -262 -26A -265 -202 MICRON (Continued) 01–12 1-9 0 33 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Table 23: Serial Presence-Detect Matrix “1”/“0”: Serial Data, “driven to HIGH”/“driven to LOW”; notes appear on page 34 BYTE 93 94 95-98 99-127 DESCRIPTION ENTRY (VERSION) Year of Manufacture in BCD Week of Manufacture in BCD Module Serial Number Manufacturer-specific Data (RSVD) MT18VDDF6472 MT18VDDF12872 Variable Data Variable Data Variable Data – Variable Data Variable Data Variable Data – NOTE: 1. Value for -26A tCK set to 7ns (0x70) for optimum BIOS compatibility. Actual device spec. vaule is 7.5ns. 2. The value of tRAS used for -26A/-265 modules is calculated from tRC - tRP. Actual device spec value is 40 ns. 3. The JEDEC SPD specification allows fast or slow slew rate values for these bytes. The worst-case (slow slew rate) value is represented here. Systems requiring the fast slew rate setup and hold values are supported, provided the faster minimum slew rate is met. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 34 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 18: 184-Pin DIMM Dimensions – Low-Profile PCB FRONT VIEW 0.157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U6 U1 U2 U3 U4 U5 U8 U9 U10 U11 1.131 (28.73) 1.119 (28.42) U7 0.700 (17.78) TYP. 0.098 (2.50) D (2X) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) 0.091 (2.30) TYP. 0.054 (1.37) 0.046 (1.17) 0.394 (10.00) TYP. 0.250 (6.35) TYP. 1.95 (49.53) PIN 92 4.750 (120.65) BACK VIEW U17 U12 U13 U14 U18 U15 U19 U20 U21 U22 U16 PIN 184 PIN 93 Figure 19: 184-Pin DIMM Dimensions – Alternate Low-Profile PCB FRONT VIEW 0.157 (3.99) MAX 5.256 (133.50) 5.244 (133.20) U12 0.079 (2.00) R (4X) U6 U1 U2 U3 U4 U8 U5 0.098 (2.50) D (2X) U9 U10 U11 1.131 (28.73) 1.119 (28.42) 0.700 (17.78) TYP. U7 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) 0.091 (2.30) TYP. 0.394 (10.00) TYP. 0.250 (6.35) TYP. 1.95 (49.53) 0.054 (1.37) 0.046 (1.17) PIN 92 4.750 (120.65) BACK VIEW U19 U15 U16 U17 U18 U20 U21 U22 PIN 184 U23 U24 PIN 93 NOTE: All dimensions are in inches (millimeters); pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN MAX or typical where noted. MIN 35 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved. 512MB, 1GB (x72, ECC, SR) 184-PIN DDR SDRAM RDIMM Figure 20: 184-Pin DIMM Dimensions – Very Low-Profile PCB 0.157 (3.99) MAX FRONT VIEW 5.256 (133.50) 5.244 (133.20) 0.079 (2.00) R (4X) U1 U2 U3 U4 U5 U8 U6 0.098 (2.50) D (2X) U9 U10 U11 0.394 (10.00) TYP. U7 0.725 (18.42) 0.715 (18.16) 0.091 (2.30) TYP. 0.035 (0.90) R PIN 1 0.050 (1.27) 0.040 (1.02) TYP. TYP. 2.55 (64.77) TYP. 0.091 (2.30) TYP. PIN 92 0.054 (1.37) 0.046 (1.17) 0.250 (6.35) TYP. 1.95 (49.53) TYP. 4.750 (120.65) TYP. BACK VIEW U12 U13 U14 U15 U16 U17 U18 U19 U20 PIN 184 U21 U22 PIN 93 NOTE: All dimensions are in inches (millimeters); MAX or typical where noted. MIN Data Sheet Designation Released (No Mark): This data sheet contains minimum and maximum limits specified over the complete power supply and temperature range for production devices. Although considered final, these specifications are subject to change, as further product development and data characterization sometimes occur. ® 8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900 E-mail: prodmktg@micron.com, Internet: http://www.micron.com, Customer Comment Line: 800-932-4992 Micron, the M logo, and the Micron logo are trademarks and/or service marks of Micron Technology, Inc. All other trademarks are the property of their respective owners. pdf: 09005aef8074e85b, source: 09005aef8072fe49 DDF18C64_128x72G.fm - Rev. C 11/04 EN 36 Micron Technology, Inc., reserves the right to change products or specifications without notice. ©2004 Micron Technology, Inc. All rights reserved.